EPSON S1D13503 service manual

查询S1D13503供应商查询S1D13503供应商

S1D13503 Graphics LCD Controller

S1D13503
TECHNICAL MANUAL

Issue Date: 01/01/30
Document Number: X18A-Q-001-07

Copyright © 1997, 2001 Epson Research and Development, Inc. All Rights Reserved.

Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

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S1D13503 Issue Date : 01/01/30

Epson Research and Development

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CUSTOMER SUPPORT INFORMATION

Comprehensive Support Tools

Seiko Epson Corp. provides to the system designer and computer OEM manufacturer a complete set of resources and tools
for the development of graphics systems.

Evaluation / Demonstration Board

• Assembled and fully tested graphics evaluation board with installation guide and schematics

• To borrow an evaluation board, please contact your local Seiko Epson Corp. sales representative

VGA Chip Documentation

• Technical manual includes Data Sheet, Application Notes, and Programmer’s Reference

Software

Page iii

•Video BIOS

• OEM Utilities

• User Utilities

• Evaluation Software

• To obtain these programs, contact Application Engineering Support

Application Engineering Support

Engineering and Sales Support is provided by:

Japan

Seiko Epson Corporation
Electronic Devices Marketing Division
421-8, Hino, Hino-shi
Tokyo 191-8501, Japan
Tel: [phone]
Fax: [phone]
http://www.epson.co.jp

Hong Kong

Epson Hong Kong Ltd.
20/F., Harbour Centre
25 Harbour Road
Wanchai, Hong Kong
Tel: [phone]
Fax: [phone]

North America

Epson Electronics America, Inc.
150 River Oaks Parkway
San Jose, CA 95134, USA
Tel: [phone]
Fax: [phone]
http://www.eea.epson.com

Europe

Epson Europe Electronics GmbH
Riesstrasse 15
80992 Munich, Germany
Tel: [phone]
Fax: [phone]

Taiwan, R.O.C.

Epson Taiwan Technology
& Trading Ltd.
10F, No. 287
Nanking East Road
Sec. 3, Taipei, Taiwan, R.O.C.
Tel: [phone]
Fax: [phone]

Singapore

Epson Singapore Pte., Ltd.
No. 1
Temasek Avenue #36-00
Millenia Tower
Singapore, 039192
Tel: [phone]
Fax: [phone]

Issue Date: 01/01/30 S1D13503

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S1D13503 Issue Date : 01/01/30

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INTRODUCTION

S1D13503 Graphics LCD Controller Data Sheet

SPECIFICATION

S1D13503 Hardware Functional Specification

PROGRAMMER’S REFERENCE

S1D13503 Programming Notes and Examples

UTILITIES

13503SHOW.EXE Display Utility
13503VIRT.EXE Display Utility
13503BIOS.COM Display Utility
13503MODE.EXE Display Utility
13503PD.EXE Power Down Utility
13503READ.EXE Diagnostic Utility

Page v

TABLE OF CONTENTS

EVALUATION

S5U13503B00C Rev 1 Evaluation Board User Manual

APPLICATION NOTES

Power Consumption
ISA Bus Interface Considerations
MC68340 Interface Considerations
LCD Panel Options/Memory Requirem ent s
S1D13503/S1D13502 Feature Comparison

Issue Date: 01/01/30 S1D13503

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S1D13503 Issue Date : 01/01/30

GRAPHICS

S1D13503

January 2001

S1D13503 GRAPHICS LCD CONTROLLER

■

DESCRIPTION

The S1D13503 is a dot matrix graphic LCD controller supporting resolutions up to 1024x1024. It is
capable of displaying a maximum of 256 simultaneous colors out of a possible 4096 or 16 gray shades.
Design flexibility allows the S1D13503 to interface to either an MC68000 family microprocessor or an
8/16-bit MPU/bus with minimum external logic. The Static RAM (SRAM) interface used for the display
buffer is optimized for speed and performance, supporting up to 128K bytes.

Two power save modes , combine d with operat ing volta ges of 2.7 vol ts throu gh 5.5 volt s, all ow for a wi de
range of applications while providing min imum power consumption.

■

FEATURES

CPU Interface

Pin compatible with the S1D13502.

•

16-bit 16 MHz MC68xxx MPU interface.

•

8/16-bit MPU interface controlled by a READY

•

(or WAIT#) signal.
Option to use built-in index register or direct-map-

•

ping to access one of sixteen internal registers.

Memory Int e rface

8/16-bit SRAM interface configurations:

•

128K bytes using one 64Kx16 SRAMs.
128K bytes using two 64Kx8 SRAMs.
64K bytes using two 32Kx8 SRAMs.
40K bytes using one 8Kx8 and one 32Kx8
SRAM.
32K bytes using one 32Kx8 SRAM.
16K bytes using two 8Kx8 SRAMs.
8K bytes using one 8Kx8 SRAM.

Display Modes

Black-and-white display.

•

2/4 bits-per-pixel, 4/16-level gray-scale display.

•

2/4/8 bits-per-pixel, 4/16/256-level color display.

•

Display Support

Single-panel, singl e- dr ive pas si v e disp la y.

•

Dual-panel, dual-drive passive display.
Maximum number of vertical lines:

•

1,024 lines (single-panel, single-drive display).
2,048 lines (dual-panel, dual-drive display).

Split screen display support allowing two different

•

images to be simultaneously displayed.
Virtual display support (displays images larger than

•

the panel size through the use of panning).

Clock Source

2-terminal crystal or external oscillator.

•

Power Down Modes

Low power consumption.

•

Two software power-save modes.

•

Package

QFP5-100-S2 package (F00A).

•

QFP15-100-STD package (F01A).

•

X18A-C-002-03

1

GRAPHICS

S1D13503

■

SYSTEM BLOCK DIAGRAM

CLOCK

CPU

Control

Clock

S1D13503

SRAM

Digital Out

CONTACT YOUR SALES REPRESENTATIVE FOR THESE
COMPREHENSIVE DESIGN TOOLS:

• S1D13503 Technical Manual

• S5U13503 Evaluation Boards

• CPU Independent Software Utilities

Japan

Seiko Epson Corporation
Electronic Devices Marketing Division
421-8, Hino, Hino-shi
Tokyo 191-8501, Japan
Tel: [phone]
Fax: [phone]
http://www.epson.co.jp

Hong Kong

Epson Hong Kong Ltd.
20/F., Harbour Centre
25 Harbour Road
Wanchai, Hong Kong
Tel: [phone]
Fax: [phone]

North America

Epson Electronics America, Inc.
150 River Oaks Parkway
San Jose, CA 95134, USA
Tel: [phone]
Fax: [phone]
http://www.eea.epson.com

Europe

Epson Europe Electronics GmbH
Riesstrasse 15
80992 Munich, Germany
Tel: [phone]
Fax: [phone]

Flat Panel

QFP5-100-S2

(S1D13503F00A)

Taiwan

Epson Taiwan Technology
& Trading Ltd.
10F, No. 287
Nanking East Road
Sec. 3, Taipei, Taiwan
Tel: [phone]
Fax: [phone]

Singapore

Epson Singapore Pte., Ltd.
No. 1
Temasek Avenue #36-00
Millenia Tower
Singapore, 039192
Tel: [phone]
Fax: [phone]

QFP15-100-STD

(S1D13503F01A)

Copyright ©1997, 2001 Epson Research and Development, Inc. All rights reserved. VDC
Information in this document is subjec t to change without not ice . You may downlo ad and use thi s docum ent, bu t only for you r ow n use in eva luating S eiko E pson/
EPSON products. You may not modify the document. Epson Research and Develo pment, Inc. disclaims any repr esentati on that the contents of this document are
accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. Microsoft and Windows are registered trademarks of Microsoft Corporation.

2

X18A-C-002-03

S1D13503 Dot Matrix Graphics Color LCD Controller

Hardware Functional Specification

Document Number: X18A-A-001-08

Copyright © 1997, 2001Epson Research and Development, Inc. All Rights Reser ved.

Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

Page 2 Epson Resear ch and Development

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S1D13503 Hardware Functional Specification
X18A-A-001-08 Issue Date : 01/01/29

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Table of Contents

1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.2 Overview Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

2 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1 Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3 Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.4 Display Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.5 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 TYPICAL SYSTEM BLOCK DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . 12

3.1 16-Bit MC68000 MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.2 MPU with READY (or WAIT#) signal . . . . . . . . . . . . . . . . . . . . . . 13

3.3 ISA Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.4 Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.5 Functional Block Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.5.1 Bus Signal Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.5.2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.5.3 Sequence Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.5.4 LCD Panel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.5.5 Look-Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.5.6 Port Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.5.7 Memory Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.5.8 Data Bus Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.5.9 Address Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.5.10 MPU / CRT Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.5.11 Display Data Formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.5.12 Clock Inputs / Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.5.13 SRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4 PINOUT DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.2 Summary of Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . 26

6 D.C. CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7 A.C. CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.1 Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.1.1 MC68000 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7.1.2 Non-MC68000, MPU/Bus With READY (or WAIT#) Signal . . . . . . . . . . . . . . . 33

7.2 Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.2.1 Recommended Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Hardware Functional Specification S1D13503
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7.3 Display Memory Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . 39

7.3.1 Write Data to Display Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7.3.2 Read Data From Display Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.4 LCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

7.4.1 LCD Interface Timing - 4-Bit Single, 8-Bit Single/Dual Monochrome Panels . . . . . . . 41

7.4.2 LCD Interface Timing - 4-Bit Single Color Panel . . . . . . . . . . . . . . . . . . . . . . 44

7.4.3 LCD Interface Timing - 8-Bit Single Color Panels Format 2/8-Bit Dual Color Panels . . . 46

7.4.4 LCD Interface Timing - 16-Bit Single/Dual Color Panels . . . . . . . . . . . . . . . . . . 48

7.4.5 LCD Interface Timing - 8-Bit Single Color Panels Format 1 . . . . . . . . . . . . . . . . 50

7.4.6 LCD Interface Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

8 HARDWARE REGISTER INTERFACE . . . . . . . . . . . . . . . . . . . . . . . .61

8.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

8.2 Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 72

8.2.1 Gray Shade Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

8.2.2 Color Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

8.3 Power Save Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

8.3.1 Power Save Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

8.3.2 Power Save Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

8.3.3 Power Save Mode Function Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

8.3.4 Pin States in Power Save Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

9 DISPLAY MEMORY INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . .79

9.1 SRAM Configurations Supported . . . . . . . . . . . . . . . . . . . . . . . . 79

9.1.1 8-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

9.1.2 16-bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

9.2 SRAM Access Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

9.2.1 8-bit Display Memory Interface: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

9.2.2 16-bit Display Memory Interface: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

9.3 Frame Rate Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

9.3.1 For single panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

9.3.2 For dual panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

9.4 Memory Size Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

9.5 Memory Size Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

10 MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

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List of Tables

Table 4-1: PAD Coordinates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Table 5-1: Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Table 5-2: Display Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Table 5-3: LCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 5-4: Clock Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 5-5: Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 5-6: Summary of Power On / Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Table 5-7: I/O and Memory Addressing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6

Table 6-1: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 6-2: Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 6-3: Input Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 6-4: Output Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 7-1: IOW# Timing (MC68000). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Table 7-2: IOR# Timing (MC68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 7-3: MEMW# Timing (MC68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1

Table 7-4: MEMR# Timing (MC68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 7-5: IOW# Timing (Non-MC68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 7-6: IOR# Timing (Non-MC68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 7-7: MEMW# Timing (Non-MC68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Table 7-8: MEMR# Timing (Non-MC68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 7-9: Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 7

Table 7-10: Write Data to Display Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Table 7-11: Read Data From Display Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 7-12: LCD Interface Timing - 4-Bit Single and 8-Bit Single/Dual Monochrome Panel . . . . . . . . . . . 42

Table 7-13: LCD Interface Timing - 4-Bit Single Color Panel. . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 7-14: LCD Interface Timing - 8-Bit Single Color Panels Format 2/8-Bit Dual Color Panels. . . . . . . . .47

Table 7-15: LCD Interface Timing - 16-Bit Single/Dual Color Panels . . . . . . . . . . . . . . . . . . . . . . .49

Table 7-16: LCD Interface Timing - 8-Bit Single Color Panels Format 1 . . . . . . . . . . . . . . . . . . . . . .51

Table 8-1: Gray Shade/Color Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Table 8-2: LCD Data Width. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Table 8-3: Maximum Value of Line Byte Count Register - 8-Bit Display Memory Interface . . . . . . . . . . .64

Table 8-4: Maximum Value of Line Byte Count Register - 16-Bit Display Memory Interface . . . . . . . . . .64

Table 8-5: Power Save Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Table 8-6: ID Bit Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Table 8-7: Look-Up Table Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Table 8-8: Look-Up Table Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2

Table 8-9: Power Save Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Table 8-10: Power Save Mode Function Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Table 8-11: Pin States in Power Save Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Table 9-1: 8-Bit Display Memory Interface SRAM Access Time . . . . . . . . . . . . . . . . . . . . . . . . .8 3

Table 9-2: 16-Bit Display Memory Interface SRAM Access Time. . . . . . . . . . . . . . . . . . . . . . . . .83

Table 9-3: Memory Size Requirement: Number of Horizontal Pixels = 640 . . . . . . . . . . . . . . . . . . . .85

Table 9-4: Memory Size Requirement: Number of Horizontal Pixels = 480 . . . . . . . . . . . . . . . . . . . .86

Table 9-5: Memory Size Requirement: Number of Horizontal Pixels = 320 . . . . . . . . . . . . . . . . . . . .86

Hardware Functional Specification S1D13503
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List of Figures

Figure 1: 16-Bit 68000 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Figure 2: 8-Bit Mode, Example: Z80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Figure 3: 16-Bit Mode, Example: i8086 (maximum mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Figure 4: 8-Bit Mode (ISA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Figure 5: 16-Bit Mode (ISA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Figure 6: Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Figure 7: S1D13503 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Figure 8: S1D13503 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Figure 9: S1D13503 Pad Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 9

Figure 10: IOW# Timing (MC68000). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 11: IOR# Timing (MC68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 12: MEMW# Timing (MC68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 13: MEMR# Timing (MC68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 14: IOW# Timing (Non-MC68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Figure 15: IOR# Timing (Non-MC68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Figure 16: MEMW# Timing (Non-MC68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Figure 17: MEMR# Timing (Non-MC68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 18: Clock Input Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure 19: Recommended Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Figure 20: Write Data to Display Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Figure 21: Read Data From Display Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Figure 22: LCD Interface Timing - Monochrome Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1

Figure 23: LCD Interface Timing - 4-Bit Single Color Panel. . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Figure 24: LCD Interface Timing - 8-Bit Single Color Panels Format 2/8-Bit Dual Color Panels. . . . . . . . .46

Figure 25: LCD Interface Timing - 16-Bit Single/Dual Color Panels . . . . . . . . . . . . . . . . . . . . . . .4 8

Figure 26: LCD Interface Timing - 8-Bit Single Color Panels Format 1 . . . . . . . . . . . . . . . . . . . . . .50

Figure 27: 4-Bit Single Monochrome Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Figure 28: 8-Bit Single Monochrome Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Figure 29: 8-Bit Dual Monochrome Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Figure 30: 4-Bit Single Color Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Figure 31: 8-Bit Single Color Panel Timing - Format 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Figure 32: 8-Bit Single Color Panel Timing - Format 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Figure 33: 8-Bit Dual Color Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Figure 34: External Circuit Required for 16-Bit Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Figure 35: 16-Bit Single Color Panel Timing with External Circuit . . . . . . . . . . . . . . . . . . . . . . . .59

Figure 36: 16-Bit Dual Color Panel Timing with External Circuit . . . . . . . . . . . . . . . . . . . . . . . . .60

Hardware Functional Specification S1D13503
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Figure 37: 4-Level Gray-Shade Mode Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 38: 16-Level Gray-Shade Mode Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 39: 4-Level Color Mode Look-Up Table Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 40: 16-Level Color Mode Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 41: 256-Level Color Mode Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 42: 8-Bit Mode - 8K bytes SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 43: 8-Bit Mode - 16K bytes SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 44: 8-Bit Mode - 32K bytes SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 45: 8-Bit Mode - 40K bytes SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 46: 8-Bit Mode - 64K bytes SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 47: 16-Bit Mode - 16K bytes SRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 48: 16-Bit Mode - 64K bytes SRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 49: 16-Bit Mode - 128K bytes SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 50: Mechanical Drawing QFP5-100-S2 (S1D13503) . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 51: Mechanical Drawing QFP15-100-STD (S1D13503). . . . . . . . . . . . . . . . . . . . . . . . . . 88

S1D13503 Hardware Functional Specification
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1 INTRODUCTION

1.1 Scope

This is the Functional Specification for the S1D13503 Dot Matrix Graphic Color LCD Controller. Included in this
document are timing diagrams, AC and DC characteristics, register descriptions, and power managem ent descriptions. This
document is intended for two audiences, Video Subsystem Designers and Software Developers.

1.2 Overview Description

This device is designed for products where low cost, low power consumption, and low component count are the major
design considerations. This chip operates f rom 2.7 Volts to 5.5 Volts and up t o 25MHz to suit d ifferent power consump tion,
speed and cost requirements. The S1D13503 offers a flexible microprocessor interface, and is pin compatible with the
S1D13502 within the same package types (e.g. the 13503D0A is pin compatible with the 13502; the 13503 is pin
compatible with the 13502).

The S1D13503 is capable of displaying a maximum of 16 levels of gray shade or 256 simultaneous colors. In gray shade
modes, a 16x4 Look-Up Table is provid ed to allow remapping of the 16 possible gray s hades displayed on the LCD panel.
In color modes, three 16x4 Look-Up Tables are prov ided to allo w remappin g of the 4096 pos sibl e colors display ed on the
LCD panel. The S1D13503S1D13503 can interface to an MC68000 family microprocessor or an 8/16-bit MPU/Bus with
minimum external “glue” logic. This device can directly control up to 128K bytes of static RAM with a 16-bit data path,
or up to 64K bytes with an 8-bit data path.

Hardware Functional Specification S1D13503
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2 FEATURES

2.1 Technology

• low power CMOS

• 2.7 to 5.5 volt operation

• 100 pin QFP5-S2 surface mount package

• 100 pin QFP15-STD surface mount package

2.2 System

• maximum 25 MHz input clock (or pixel clock)

• 2-terminal crystal input for internal oscillator or direct connection to external clock source

• maximum 16 MHz, 16-bit MC68000 MPU interface

• 8-bit or 16-bit MPU/Bus interface with memory accesses controlled by a READY (or WAIT#) signal

• option to use built-in index register or direct-mapping to access one of sixteen internal registers

• 8-bit or 16-bit SRAM data bus interface configurations

• display memory configurations :

• 128k bytes using one 64Kx16 SRAM

• 128k bytes using two 64Kx8 SRAMs

• 64k bytes using two 32Kx8 SRAMs

• 40k bytes using one 8Kx8 and one 32Kx8 SRAM

• 32k bytes using one 32Kx8 SRAM

• 16k bytes using two 8Kx8 SRAMs

• 8k bytes using one 8Kx8 SRAM

2.3 Display Modes

• 1 bit-per-pixel, black-and-white display mode

• 2/4 bits-per-pixel, 4/16 level gray shade display modes

• 2/4/8 bits-per-pixel, 4/16/256 level color display modes

• one 16x4 Look-Up Table provided for gray shade display modes

• three 16x4 Look-Up Tables provided for color display modes

• maximum 16 shades of gray

• maximum 256 simultaneous colors from a possible 4096 colors

• split screen display mode (see AUX[0A])

• virtual display mode (see AUX[0D])

Note

256 color display mode support requires a 16-bit display memory interface

S1D13503 Hardware Functional Specification
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2.4 Display Support

• example resolutions:

• 1024 x 768 black-and-white

• 640 x 480 with 4 colors/grays

• 640 x 400 with 16 colors/grays

• 320 x 240 with 256 colors

• passive monochrome LCD panels:

• 4-bit single (4-bit data transfer)

• 8-bit single (8-bit data transfer)

• 8-bit dual (4-bit data transfer for each half panel)

• passive color LCD panels:

• 4-bit single (4-bit data transfer)

• 8-bit single (8-bit data transfer)

• 8-bit dual (4-bit data transfer for each half panel)

• 16-bit single (8-bit data transfer with external circuit)

• 16-bit dual (8-bit data transfer with external circuit)

See Section 9.5 on page 85 for complete details

2.5 Power Management

• two software power-save modes

• low power consumption

• panel power control switch (see AUX[01] bit 4)

Hardware Functional Specification S1D13503
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3 TYPICAL SYSTEM BLOCK DIAGRAMS

The following figures show typical system implementations of the S1D13503. All of the following block diagrams are
shown without SRAM or LCD display. Refer to the interface specific Application Notes for complete details.

3.1 16-Bit MC68 000 MPU

MC68000

A20 to A23
FC0 to FC1

A1 to A19 AB1 to AB19
D0 to D15

DTACK#

UDS#

LDS#

AS#

R/W#

A14 to A16

A10 to A19

Decoder

Decoder

S1D13503

MEMCS#

IOCS#

DB0 to DB15
READY
AB0

BHE#
IOR#

IOW#

Figure 1: 16-Bit 68000 Series

(example implementation only - actual may vary)

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3.2 MPU with READY (or WAIT#) signal

RDY

CLK

READY

RESET#

8284A

Z80

MREQ#

MI#

IORQ#

A0 to A15

D0 to D7

WAIT#

WR#

RD#

RESET#

8086

(Maximum mode)

CLK

READY
RESET#

A16 to A19

AD0 to AD15

Decoder

A10 to A15

Decoder

Figure 2: 8-Bit Mode, Example: Z80

(example implementation only - actual may vary)

8288

CLK

S2#
S1#
S0#

A16

BHE#

S2#
S1#
S0#

DEN
DT/R

ALE

Decoder

M/IO#
BHE#
A0 to A16

STB

MRDC#

AMWC#

IORC#

AIOWC#

S1D13503

MEMCS#

IOCS#

AB0 to AB15
DB0 to DB7

READY
MEMW#

MEMR#
IOR#

IOW#
RESET

S1D13503

MEMR#
MEMW#
IOR#

IOW#

AB16 to AB19

AB0 to AB15
BHE#
MEMCS#
IOCS#

D0 to D15

T
OE

Transceiver

DB0 to DB15

RESET
READY

Figure 3: 16-Bit Mode, Example: i8086 (maximum mode)

(example implementation only - actual may vary)

Hardware Functional Specification S1D13503
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3.3 ISA Bus

8-Bit ISA Bus

REFRESH

SMEMW#

SMEMR#

IOCHRDY

SD0 to SD7

SA0 to SA19

AEN

IOW#

IOR#

RESET#

0WS#

SA16 to SA13

SA10 to SA15

Decoder

Decoder

optional

Decoder

Figure 4: 8-Bit Mode (ISA)

(example implementation only - actual may vary)

S1D13503

MEMCS#
MEMW#
MEMR#
READY
DB0 to DB7
AB0 to AB19

IOCS#

IOW#
IOR#

RESET

SA(1 or 4) through SA9

16-bit ISA Bus

REFRESH

SMEMW#

SMEMR#

IOCHRDY
SD0 to SD15
SA0 to SA19

IOW#

IOR#

SBHE#

RESET#

IOCS16#

LA17 to LA23

MEMCS16#

SA16 to SA14

AEN

Decoder

SA10 to SA15

(example implementation only - actual may vary)

Decoder

Decoder

Decoder

Figure 5: 16-Bit Mode (ISA)

S1D13503

MEMCS#
MEMW#
MEMR#
READY

DB0 to DB15
AB0 to AB19

IOCS#

IOW#
IOR#

BHE#
RESET

SA(1 or 4) through SA9

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3.4 Internal Block Diagram

Control Re gi sters

IOR#, IOW#, IOCS#,
MEMCS#, MEMR#,
MEMW#, BHE#,
AB[19:0]

READY

DB[15:0]

Bus

Signal

Translation

Port

Decoder

Memory
Decoder

Data Bus

Conversion

Timing Generator

Power Save

Oscillator

Sequence

Controller

Address

Generator

MPU/CRT

Selector

Display

Data

Formatter

SRAM Interface

Lookup

Table

LCD

Panel

Interface

LCDENB

UD[3:0]
LD[3:0]
LP, YD,
XSCL,

WF(XSCL2)

OSC1

OSC2

VOE#

VA[15:0]

VCS0#, VCS1#

VD[15:0]

VWE#

Figure 6: Internal Block Diagram

3.5 Functional Block Descriptions

3.5.1 Bus Signal Translation

According to configuration setting VD2, Bus Signal Translation translates MC68000 type MPU signals, or READY type
MPU signals to internal bus interface signals.

3.5.2 Control Regist ers

The Control Register contains 16 internal control and configuration registers. These registers can be accessed by either
direct-mapping or by using the built-in internal index register.

3.5.3 Sequence Controller

The Sequence Controller generates horizont al and vertical dis play timings accordin g to the con figuration regist ers settings.

3.5.4 LCD Pa nel Int erfac e

The LCD Panel Interface performs frame rate modulation and output data pattern formatting for both passive monochrome
and passive color LCD panels.

Hardware Functional Specification S1D13503
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3.5.5 Look-Up Table

The Look-Up Table contains three 16x4-bit wide pale ttes. In gray s hade modes , the “g reen” p alette can be configured for
the re-mapping of 16 possible shades of gray. In color modes, all three palettes can be configured for the re-mapping of
4096 possible colors.

3.5.6 Port Decoder

According to configuration settings VD1, VD12 - VD4, IOCS# and address lines AB9-1, the Port Decoder validates a given
I/O cycle.

3.5.7 Memory Decoder

According to configuration settings VD15 - VD13, MEMCS# and address lines AB19-17, the Memo ry Decoder validates
a given memory cycle.

3.5.8 Data Bus Conversion

According to configuration setting VD0, Data Bus Conversion maps the external data bus, either 8-b it or 1 6-b it, into th e
internal odd and even data bus.

3.5.9 Address Generator

The Address Generator generates display refresh addresses to be used to access display memory.

3.5.10 MPU / CRT Selector

The MPU / CRT Selector grants access to the display memory from either the MPU or the display refresh circuitry.

3.5.11 Display Data Formatter

The Display Data Formatter reads in the display data from the display memory and outputs th e correct format for all
supported gray shade and color selections.

3.5.12 Clock Inputs / Timing

Clock Inputs / Timing generates the internal master clock according to gray-level / color selected and display memory
interface. The master clock (MCLK) can be:

- MCLK = input clock

- MCLK = 1/2 input clock

- MCLK = 1/4 input clock.

Pixel clock = input clock = f

OSC.

3.5.13 SRAM Interface

The SRAM Interface generates the necessary signals to interface to the Display Memory (SRAM).

S1D13503 Hardware Functional Specification
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4 PINOUT DIAGRAM

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

100

XSCL
LCDENB
VOE#
IOCS#
IOW#
IOR#
MEMCS#
MEMW#
MEMR#
READY
BHE#
OSC1
OSC2
DB0
DB1
DB2
DB3
DB4
DB5
DB6

8079787776757473727170696867666564636261605958575655545352

WF/XSCL2*

LPYDLD0

LD1

LD2

LD3

UD2

UD0

UD1

UD3

VCS1#

VCS0#

VWE#

VA15

VA14

VA13

VA12

VA11

VD15

VD14

VD13

VD12

VD11

VD10

VD9

VD8

V

DDVSS

S1D13503F00A

DB10

DB12

DB13

DB7

V

SS

123

DD

DB15

DB8

V

4

DB11

DB9

5

6

7

DB14

AB0

AB1

AB2

AB3

AB4

AB5

AB6

AB7

101112131415161718192021222324252627282930

8

9

AB10

AB12

AB13

AB14

AB15

AB8

AB11

AB9

AB16

51

VD7

50

VD6

49

VD5

48

VD4

47

VD3

46

VD2

45

VD1

44

VD0

43

VA10

42

VA9

41

VA8

40

VA7

39

VA6

38

VA5

37

VA4

36

VA3

35

VA2

34

VA1

33

VA0

AB19

32
31

RESET

AB17

AB18

Figure 7: S1D13503F00A Pinout Diagram

Package type: 100 pin surface mount QFP5-S2.

Note

* Pin 80 = WF in all display modes except format 1 for 8-bit single color panel.
* Pin 80 = XSCL2 in format 1 for 8-bit single color panel.

Hardware Functional Specification S1D13503
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75747372717069686766656463626160595857565554535251

YD

LD0

LD1

LD2

LD3

UD0

UD1

UD2

UD3

VCS1#

VCS0#

VWE#

VA1 5

VA1 4

VA1 3

VA1 2

VA1 1

VD15

VD14

VD13

VD12

VD11

VD10

VD9

VD8

76
77
78
79

80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

100

LP
WF/XSCL2*
XSCL
LCDENB
VOE#
IOCS#
IOW#
IOR#
MEMCS#
MEMW#
MEMR#
READY
BHE#
OSC1
OSC2
DB0
DB1
DB2
DB3
DB4
DB5
DB6

DB7
VSS

V

DD

DB8

DB9

1

50

V

DD

49

V

SS

48

VD7

47

VD6

46

VD5

45

VD4

44

VD3

43

VD2

42

VD1

41

VD0

40

VA1 0

39

VA9

38

AB15

RESET

AB19
AB18

AB16

AB17

25

VA8
VA7
VA6
VA5
VA4
VA3
VA2
VA1
VA0

37
36
35
34
33
32
31
30

29
28
27
26

S1D13503F01A

DB10

DB12

DB13

DB15

DB11

2

3

456

DB14

AB0

AB1

AB2

AB3

AB4

AB5

AB6

AB7

7

101112131415161718192021222324

8

9

AB10

AB8

AB11

AB9

AB14

AB12

AB13

Figure 8: S1D13503F01A Pinout Diagram

Package type: 100 pin surface mount QFP15-STD.

Note

* Pin 77 = WF in all display modes except format 1 for 8-bit single color panel.
* Pin 77 = XSCL2 in format 1 for 8-bit single color panel.

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VCS1#

VCS0#

LP

YD

LD0

LD1

LD2

LD3

UD0

UD1

UD2

UD3

VWE#

VA1 5

VA1 4

VA1 3

VA1 2

VD15

VD14

VD13

VD12

VD11

VA1 1

VD10

VD9

VD8

V

V

DD

SS

Dummy Pad

WF/XSCL2*

XSCL

LCDENB

VOE#

IOCS#

IOW#

IOR#

MEMCS#

MEMW#

MEMR#

READY

BHE#

OSC1
OSC2

DB0
DB1

DB2
DB3
DB4
DB5
DB6

100

110

120

90

S1D13503D00A

7080

60

50

40

VD7

VD6
VD5
VD4
VD3

VD2

VD1
VD0

VA1 0
VA9

VA8
VA7

VA6
VA5

VA4
VA3

VA2
VA1
VA0
RESET
AB19

DB7

Dummy Pad

110 20

V

V

SS

Chip Size
Chip Thickness
Pad Size
Pad Pitch

DD

DB8

DB9

DB10

DB12

DB13

DB15

AB0

AB1

AB2

AB3

AB4

AB5

AB6

AB7

AB8

AB9

DB11

=
=
=
=

DB14

5.030 mm x 5.030 mm

0.400 mm

0.090 mm x 0.090 mm

0.126 mm (Min.)

AB10

AB11

30

AB12

AB13

AB14

AB15

AB16

AB18

AB17

Figure 9: S1D13503D00A Pad Diagram

Note

* Pad 97 = WF in all display modes except format 1 for 8-bit single color panel.
* Pad 97 = XSCL2 in format 1 for 8-bit single color panel.

Hardware Functional Specification S1D13503
Issue Date: 01/01/29 X18A-A-001-08

Page 20 Epson Resear ch and Development

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Table 4-1: PAD Coordinates

Pad

No.

1 VSS -2.165 -2.390 37 RESET 2.390 -1.535
2 --- -2.000 -2.390 38 VA0 2.390 -1.388
3 VDD -1.840 -2.390 39 VA1 2.390 -1.246
4 DB8 -1.685 -2.390 40 VA2 2.390 -1.106
5 DB9 -1.535 -2.390 41 --- 2.390 -0.969
6 DB10 -1.388 -2.390 42 VA3 2.390 -0.835
7 DB11 -1.246 -2.390 43 VA4 2.390 -0.703
8 DB12 -1.106 -2.390 44 --- 2.390 -0.573

9 DB13 -0.969 -2.390 45 VA5 2.390 -0.444
10 DB14 -0.835 -2.390 46 VA6 2.390 -0.317
11 DB15 -0.703 -2.390 47 --- 2.390 -0.190
12 --- -0.573 -2.390 48 VA7 2.390 -0.063
13 AB0 -0.444 -2.390 49 VA8 2.390 0.063
14 AB1 -0.317 -2.390 50 --- 2.390 0.190
15 AB2 -0.190 -2.390 51 VA9 2.390 0.317
16 AB3 -0.063 -2.390 52 VA10 2.390 0.444
17 AB4 0.063 -2.390 53 --- 2.390 0.573
18 AB5 0.190 -2.390 54 VD0 2.390 0.703
19 AB6 0.317 -2.390 55 VD1 2.390 0.835
20 AB7 0.444 -2.390 56 --- 2.390 0.969
21 --- 0.573 -2.390 57 VD2 2.390 1.106
22 AB8 0.703 -2.390 58 VD3 2.390 1.246
23 AB9 0.835 -2.390 59 VD4 2.390 1.388
24 AB10 0.969 -2.390 60 VD5 2.390 1.535
25 AB11 1.106 -2.390 61 VD6 2.390 1.685
26 AB12 1.246 -2.390 62 --- 2.390 1.840
27 AB13 1.388 -2.390 63 --- 2.390 2.000
28 AB14 1.535 -2.390 64 VD7 2.390 2.165
29 AB15 1.685 -2.390 65 VSS 2.165 2.390
30 AB16 1.840 -2.390 66 --- 2.000 2.390
31 --- 2.000 -2.390 67 VDD 1.840 2.390
32 AB17 2.165 -2.390 68 VD8 1.685 2.390
33 AB18 2.390 -2.340 69 VD9 1.535 2.390
34 --- 2.390 -2.000 70 VD10 1 .388 2.390
35 --- 2.390 -1.840 71 VD11 1 .246 2.390
36 AB19 2.390 -1.685 72 VD12 1.106 2.390

Pin

Name

Pad Center
Coordinate

XY XY

Pad

No.

Pin

Name

Pad Center

Coordinate

S1D13503 Hardware Functional Specification
X18A-A-001-08 Issue Date : 01/01/29

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Table 4-1: PAD Coordinates

Pad

No.

73 VD13 0.969 2.390 102 VOE# -2.390 1.388
74 VD14 0.835 2.390 103 IOCS# -2.390 1.246
75 VD15 0.703 2.390 104 IOW# -2.390 1.106
76 --- 0.573 2.390 105 --- -2.390 0.969
77 VA11 0.444 2.390 106 IOR# -2.390 0.835
78 VA12 0.317 2.390 107 MEMCS# -2.390 0.703
79 VA13 0.190 2.390 108 --- -2.390 0.573
80 VA14 0.063 2.390 109 MEMW# -2.390 0.444
81 VA15 -0.063 2.390 110 MEMR# -2.390 0.317
82 VWE# -0.190 2.390 111 --- -2.390 0.190
83 VCS0# -0.317 2.390 112 READY -2.390 0.063
84 VCS1# -0.444 2.390 113 BHE# -2.390 -0.063
85 --- -0.573 2.390 114 --- -2.390 -0.190
86 UD3 -0.703 2.390 115 OSC1 -2.390 -0.317
87 UD2 -0.835 2.390 116 OSC2 -2.390 -0.444
88 UD1 -0.969 2.390 117 --- -2.390 -0.573
89 UD0 -1.106 2.390 118 DB0 -2.390 -0.703
90 LD3 -1.246 2.390 119 DB1 -2.390 -0.835
91 LD2 -1.388 2.390 120 --- -2.390 -0.969
92 LD1 -1.535 2.390 121 DB2 -2.390 -1.106
93 LD0 -1.685 2.390 122 DB3 -2.390 -1.246
94 YD -1.840 2.390 123 DB4 -2.390 -1.388
95 --- -2.000 2.390 124 DB5 -2.390 -1.535
96 LP -2.340 2.390 125 DB6 -2.390 -1.685
97 WF/XSCL2 -2.390 2.165 126 --- -2.390 -1.840
98 --- -2.390 2.000 127 --- -2.390 -2.000

99 --- -2.390 1.840 128 DB7 -2.390 -2.165
100 XSCL -2.390 1.685 129 Dummy Pad 2.390 2.390
101 LCDENB -2.390 1.535 130 Dummy Pad -2.390 -2.390

Pin

Name

Pad Center
Coordinate

XY XY

Pad

No.

Pin

Name

Pad Center

Coordinate

Hardware Functional Specification S1D13503
Issue Date: 01/01/29 X18A-A-001-08

Page 22 Epson Resear ch and Development

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5 PIN DESCRIPTION

5.1 Description

Key:

I=Input
O=Output
I/O = Bidirectional (Input/Output)
P=Power pin
COx = CMOS level output driver, x denotes driver type (see Table 6-4, “Output Specifications,” on page 28)
COxS = CMOS level output d river with s lew rate cont rol for n oise redu ction, x d enotes dr iver typ e (see Table 6-4,

“Output Spec ifications,” on page 28)

TSx = Tri-state CMOS level output driver, x denotes driver type (see Table 6-4, “Output Specifications,” on

page 28)

TSxD2 = Tri-state CMOS level output driver with pull down resistor (typical values of 100KΩ/200ΚΩ at 5V/3.0V

respectively), x denotes driver type (see Table 6-4, “Output Specifications,” on page 28)

TTL = TTL level input (V

= 5.0V, see Table 6-3, “Input Specifications,” on page 27)

DD

TTLS = TTL level input with hysteresis

Table 5-1: Bus Interface

Pin Name Type

F00A
Pin #

F01A
Pin #

D00A
Pad #

Driver Description

118­119,
121­125,
128,

TS2

These pins are connected to the system data bus. In 8-bit bus
mode, DB8-DB15 must be tied to V

DD

.

DB0­DB15

I/O

94 ­100, 1,
4 -11

91 - 98,
1 - 8

4-11

In MC68000 MPU interface, this pin is connected to the Upper

AB0 I 12 9 13 TTLS

Data Strobe (UDS#) pin of MC68000. In other MPU/Bus
interfaces, this pin is connected to the system address bus.

14-20,
AB1­AB19

I 13 - 31 10 - 28

22-30,

32-33,

TTL These pins are connected to the system address bus.

36

In MC68000 MPU interface, this pin is connected to the Lower

BHE# I 91 88 113 TTLS

Data Strobe (LDS#) pin of MC68000. In other MPU/Bus
interfaces, this pin is the Byte High Enable input for use with
16-bit system. In 8-bit bus mode tie the BHE# input to V

IOCS# I 84 81 103 TTLS Active low input to select one of sixteen internal registers.

DD

.

S1D13503 Hardware Functional Specification
X18A-A-001-08 Issue Date : 01/01/29

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Table 5-1: Bus Interface

Pin Name Type

F00A
Pin #

F01A
Pin #

D00A
Pad #

Driver Description

In MC68000 MPU interface, this pin is connected to the R/W#
pin of MC68000. This input pin defines whether the data

IOW# I 85 82 104 TTLS

transfer is a read (active high) or write (active low) cycle. In
other MPU/Bus interfaces, this is the active low input to write
data into an internal register.

In MC68000 MPU interface, this pin is connected to the AS#

IOR# I 86 83 106 TTLS

pin of MC68000. This input pin indicates a val i d address is
available on the address bus. In other MPU/Bus interfaces, this
is the active low input to read data from an internal register.

MEMCS# I 87 84 107 TTLS Active low input to indicate a memory cycle.
MEMW# I 88 85 109 TTLS

MEMR# I 89 86 110 TTLS

Active low input to indicate a memory write cycle. This pin
should be tied to V

in an MC68000 MPU interface.

DD

Active low input to indicate a memory read cycle. This pin
should be tied to V

in an MC68000 MPU interface.

DD

For MC68000 MPU interface, this pin is connected to the
DTACK# pin of MC68000 and is driven low when the data
transfer is complete. In other MPU/Bus interfaces, this output

READYO9087112TS3

is driven low to force the system to insert wait states when
needed.

READY is placed in a high impedance (Hi-Z) state after the
transfer is completed.

RESET I 32 29 37 TTLS Active high input to force all signals to their inactive states.

Hardware Functional Specification S1D13503
Issue Date: 01/01/29 X18A-A-001-08

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Table 5-2: Display Memory Interface

Pin
Name

VD0­VD15

VA0­VA15

VCS1# O 69 66 84 CO1

VCS0# O 68 65 83 CO1

VWE#O676482CO1

VOE#O8380102CO1

Type

I/O

O

F00A
Pin #

44 - 51,
54 - 61

33 - 43,
62 - 66

F01A
Pin #

41 - 48,
51 - 58

30 - 40
59 - 63

D00A
Pad #

54-55,
57-61,
64,
68-75

38-40,
42-43,
45-46,
48-49,
51-52,
77-81

Driver Description

These pins are connected to the display memory data bus. For 16­bit interface, VD0-VD7 are connected to the display memory data
bus of even byte addresses and VD8-VD15 are connected to the
display memory data bus of odd byt e addresses . The out put drivers
of these pins are placed in a high impedance state when RESET is

TS1D2

CO1 These pins are connected to the display memory address bus.

high.
On the falling edge of RESET, the values of VD0-VD15 are

latched into the chip to configure various hardware options (see
Section Table 5-6: on page 26).

VD0-VD15 each have an internal pull-down resistor (see Section
Table 6-3: on page 27).

Active low chip-select output to the second or odd byte address
SRAM. See Display Memory Interface section for details.

Active low chip-select output to the first or even byte address
SRAM. See Display Memory Interface section for details.

Active low output used for writing data to the display memory.
This pin is connected to the WE# input of the SRAMs.

Active low output to enable reading of data from the display
memory. This pin is connected to the OE# input of the SRAMs.

S1D13503 Hardware Functional Specification
X18A-A-001-08 Issue Date : 01/01/29

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Table 5-3: LCD Interface

TM

Pin Name

UD3-UD0
LD3-LD0

FPDI-1
Pin Name

UD3-UD0
UD3-LD0

a

XSCL FPSHIFT O 81 78 100 CO3

Type

O

F00A
Pin #

70 - 73
74 - 77

F01A
Pin #

67 - 70
71 - 74

D00A
Pad #

86 - 89
90 - 93

Driver Description

Panel display data bus. The data format depends on the

CO3S

specific panel connected. For 4-bit single p anels, LD3-LD0
are driven low (0 state).

Display data shift clock. Data is shifted into the LCD
X-drivers on the falling edge of this signal.

Display data latch clock. The falling edge of this signal is

LP F PLINE O 79 76 96 CO3

used to latch a row of display data in the LCD X-drivers
and to turn on the Y driver (row driver).

For format 1 of 8-bit single color panels this is the second
shift clock.

WF/
XSCL2

MOD
FPSHIFT2

O80 77 97 CO3

For all other modes, this is the LCD backplane BIAS
signal. This output toggles once every frame, or as
programmed in AUX[05] bits 7-2.

Vertical scanning start pulse. A logic ‘1’ on this signal,

YD FPFRAME O 78 75 94 CO3

sampled by the LCD module on the falling edge of LP, is
used by the panel Y driver (row driver) to indicate the start
of the vertical frame.

LCDENB

a

VESA Flat Panel Display Interface Standard (FPDI-1TM)

-----

O82 79 101 CO2

LCD enable signal output. It can be used externally to turn
off the panel supply voltage and backlight.

Table 5-4: Clock Inputs

Pin
Name

Type

F00A
Pin #

F01A
Pin #

D00A
Pad #

Driver Description

This pin, along with OSC2, is the 2-terminal crystal interface when

OSC1I9289115*

using a 2-terminal crystal as the clock input. If an external
oscillator is used as a clock source, then this pin is the clock input.

This pin, along with OSC1, is the 2-terminal crystal interface when

OSC2O9390116*

using a 2-terminal crystal as the clock input. If an external
oscillator is used as a clock source this pin should be left
unconnected.

Table 5-5: Power Supply

Pin Name Type F00A Pin # F01A Pin # D00A Pad # Driver Descripti on

V

DD

V

SS

P 3, 53 50, 100 3, 67 P Voltage supply
P 2, 52 49, 99 1, 65 P Voltage ground

Hardware Functional Specification S1D13503
Issue Date: 01/01/29 X18A-A-001-08

Page 26 Epson Resear ch and Development

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5.2 Summary of Configuration Options

The S1D13503 requires some configuration information on power-up. This information is provided through the SRAM
data lines VD[0...15]. The state of these pins are read on the falling edge of RESET and used to configure the following
options:

Table 5-6: Summary of Power On / Reset Options

Pin Name value on this pin at falling edge of RESET is used to configure: (1/0)

1 0

VD0 16-bit host bus interface 8-bit host bus interface
VD1 Use direct-mapping for I/O accesses Use internal index register for I/O accesses

VD2 MC68000 MPU interface

VD3

VD12-VD4

Swap of high and low data bytes in 16-bit bus
interface

Select I/O mapping address bits [9:1].
These nine bits are latched on power-up and are compared to the MPU address bits [9-1]. A

valid I/O cycle combined with a valid address will enable the internal I/O decoder. Therefore,
both types of I/O mapping are limited to even address boundaries to determine either the
absolute or indexed I/O address of the first register. Note that a “valid I/O cycle” includes
IOCS# being toggled low.

Select memory mapping address bits [3:1]

MPU / Bus interface with memory accesses
controlled by a READY (WAIT#) signal

No byte swap of high and low data bytes in
16-bit bus interface

These three bits are latched on power-up and are compared to the MPU address bits [1 9-1 7]. A
valid memory cycle combined with a valid address will enable the internal memory decoder.
As only the three most significant bits of the address are compared, the maximum amount of

VD15-VD13

Note

The S1D13503 has internal pulldown r esistors on these pins and theref ore will be pulled down
and read on a logic “0” after RESET. If pullup resistors are required refer to Table 6-3, “Input
Specifications,” on page 27 for pulldown resistor values.

Example: If an ISA bus (no byte swap) with memory segment “A” and I/O location 300h are used, the corresponding
settings of VD15-VD0 would be:

Pin Name

VD00011
VD10 101
VD20000
VD30000

VD12-VD4 11 0000 000 11 0000 xxx 11 0000 000 11 0000 xxx

VD15-VD13 101 101 101 101

memory supported is 128K bytes. Note that a “valid memory cycle” includes MEMCS# being
toggled low.

When using 128K byte memo ry it m us t be m apped at an even address such that all 128K bytes
is available without a change in state on A17, as this would invalidate the internal compare
logic.

Table 5-7: I/O and Memory Addressing Example

8-Bit ISA Bus 16-Bit ISA Bus

Index

Register

Direct Mapping

Index

Register

Direct Mapping

Where x = don’t care; 1 = connected to pull-up resistor; 0 = no pull-up resistor

S1D13503 Hardware Functional Specification
X18A-A-001-08 Issue Date : 01/01/29

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6 D.C. CHARACTERISTICS

Table 6-1: Absolute Maximum Ratings

Symbol Parameter Rating Units

-0.3 to + 6.0 V

-0.3 to V

-0.3 to V

+ 0.5 V

DD

+ 0.5 V

DD

-65 to 150 ° C

260 for 10 sec. max at lead ° C

= 0 V 2.7 3.0/3.3/5.0 5.5 V

V

SS

= 6 MHz

f

OSC

256 colors

V

SS

-- V

4.5/5.0/11 mA

-40 25 85 ° C

f

= 6 MHz

OSC

256 colors

13.5/16.5/55 mW

DD

V

V

T
T

V

V

DD

IN
OUT
STG
SOL

Supply Voltage
Input Voltage
Output Voltage
Storage Temperature
Solder Temperature/Time

Table 6-2: Recommended Operating Conditions

Symbol Parameter Condition Min Typ Max Units

V

I
T
P

V

OPR

OPR

TYP

Supply Voltage

DD

Input Voltage

IN

Operatin g Current
Operating Temperature
Typical Active Power Consumption

Table 6-3: Input Specifications

Symbol Parameter Condition Min Typ Max Units

VDD = 4.5V

V

IL

V

IH

Low Level Input Voltage

High Level Input Voltage

V

= 3.0V

DD

V

= 2.7V

DD

VDD = 5.5V
V

= 3.6V

DD

V

= 3.3V

DD

2.0

1.3

1.2

VDD = 5.0

V

T+

V

T-

V

H

I

IZ

Positive-going Threshold

Negative-going Threshold

Hysteresis Voltage

Input Leakage Current

V

= 3.3

DD

V

= 3.0

DD

VDD = 5.0
V

= 3.3

DD

V

= 3.0

DD

VDD = 5.0
V

= 3.3

DD

V

= 3.0

DD

0.6

0.5

0.4

0.1

0.1

0.1

-- -1 1

0.8

0.4

0.3

2.4

1.4

1.3

V

V

V

V

V

µA

Hardware Functional Specification S1D13503
Issue Date: 01/01/29 X18A-A-001-08

Page 28 Epson Resear ch and Development

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Table 6-3: Input Specifications (Continued)

Symbol Parameter Condition Min Typ Max Units

C

IN

R

PD

R

PD

R

PD

Input Pin Capacitance

Pull Down Resistance

Pull Down Resistance

Pull Down Resistance

f =1 MHz,

V

= 0V

DD

VDD = 5.0V

V

= V

I

DD

VDD = 3.3V

V

= V

I

DD

VDD = 3.0V

V

= V

I

DD

12 pF

50 100 200 kΩ

90 180 360 kΩ

100 200 400 kΩ

Table 6-4: Output Specifications

Symbol Parameter Condition Min Typ Max Units

Low Level Output Voltage

V

(5.0V)

OL

Type 1 - TS1D2, CO1
Type 2 - TS2, CO2
Type 3 - TS3, CO3, CO3S

Low Level Output Voltage

V

(3.3V)

OL

Type 1 - TS1D2, CO1
Type 2 - TS2, CO2
Type 3 - TS3, CO3, CO3S

Low Level Output Voltage

VDD = Min

I

= 4 mA

OL

I

= 8 mA

OL

I

= 12 mA

OL

VDD = Min
I

= 2 mA

OL

I

= 4 mA

OL

I

= 6 mA

OL

VDD = Min

0.4 V

0.3 V

I

V

(3.0V)

OL

Type 1 - TS1D2, CO1
Type 2 - TS2, CO2
Type 3 - TS3, CO3, CO3S

High Level Output Volt age

V

(5.0V)

OH

Type 1 - TS1D2, CO1
Type 2 - TS2, CO2
Type 3 - TS3, CO3, CO3S

Low Level Output Voltage

V

(3.3V)

OH

Type 1 - TS1D2, CO1
Type 2 - TS2, CO2
Type 3 - TS3, CO3, CO3S

High Level Output Volt age

V

(3.0V)

OH

Type 1 - TS1D2, CO1
Type 2 - TS2, CO2
Type 3 - TS3, CO3, CO3S

C

C

I

OZ

OUT

BID

Output Leakage Current
Output Pin Capacitance

Bidirectional Pin Capacitance

= 1.8 mA

OL

I

= 3.5 mA

OL

I

= 5 mA

OL

VDD = Min

I

= -4 mA

OH

I

= -8mA

OH

I

= -12 mA

OH

VDD-0.4 V

VDD = Min

I

= -2 mA

OL

I

OL

I

OL

= -4 mA
= -6 mA

VDD-0.3 V

VDD = Min

I

= -1.8 mA

OH

I

= -3.5 mA

OH

I

= -5 mA

OH

VDD-0.3 V

-- -1 1

f =1 MHz,

V

= 0V

DD

f =1 MHz,

V

= 0V

DD

0.3 V

µA

12 pF

12 pF

S1D13503 Hardware Functional Specification
X18A-A-001-08 Issue Date : 01/01/29

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7 A.C. CHARACTERISTICS

Conditions : VDD = 3.0V ± 10%, VDD = 3.3V ± 10%, or VDD = 5.0V ± 10% TA = -40 °C to 85 °C

T

and T

rise

C

= 80pF (Bus/MPU Interface)

L

C

= 100pF (LCD Panel Interface)

L

C

= 20pF (Display Memory Interface)

L

7.1 Bus Interface Timing

7.1.1 MC68000 Interfac e Timing

Note

All input timing parameters are based on a maximum 16MHz MPU clock.

IOW # Timing

for all inputs must be < 5 nsec (10% ~ 90%)

fall

AB[9:1]

IOCS#

AS#

R/W

UDS#/LDS#

DTACK#

DB[15:0]

t1

INVALID

Hi-Z

t5

VALID

Hi-Z

t2

t3

t4

t6

t7

VALID

Hi-Z

t8

Hi-Z

Figure 10: IOW# Timing (MC68000)

Table 7-1: IOW# Timing (MC68000)

3V/3.3V 5V

Symbol Parameter Min Max Min Max Units

t1

AB[9:1] valid before AS# falling edge

t2

AB[9:1] hold from AS# rising edge

t3

IOCS# hold from AS# rising edge

t4

UDS#/LDS# valid before AS# rising edge

t5

UDS#/LDS# falling edge to DTACK# falling edge

t6

AS# rising edge to DTACK# hi-z delay

t7

DB[15:0] setup to AS# rising edge

t8

DB[15:0] hold from AS# rising edge

10 0 ns
20 10 ns

00ns

30 20 ns

40 25 ns

40 25 ns
20 10 ns
20 10 ns

Hardware Functional Specification S1D13503
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IOR# Timing

AB[9:1]

IOCS#

AS#

UDS#/LDS#

R/W#

DTACK#

DB[15:0]

INVALID

Hi-Z

Hi-Z

VALID

t2b

t1

t3

t5

VALID

t2a

t4

Hi-Z

t6

Hi-Z

t7

Figure 11: IOR# Timing (MC68000)

Table 7-2: IOR# Timing (MC68000)

3V/3.3V 5V

Symbol Parameter Min Max Min Max Units

t1

AB[9:1] and IOCS# valid before AS# falling edge

t2

AB[9:1] and IOCS# hold from AS# rising edge

t3

AS# falling edge to DTACK# falling edge

t4

AS# rising edge to DTACK# hi-z delay

t5

AS# falling edge to DB[15:0] valid

t6

DB[15:0] hold from AS# rising edge

t7

AS# rising edge to DB[15:0] hi-z delay

10 0 ns
20 10 ns

40 25 ns
40 25 ns
60 40 ns
20 15 ns
35 25 ns

S1D13503 Hardware Functional Specification
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MEMW# Timing

AB[19:1]

MEMCS#

AS#

UDS#/LDS#

R/W#

DTACK#

DB[15:0]

INVALID

Hi-Z

Hi-Z

t1

t5

VALID

t2

t4

t3

t6

VALID

Hi-Z

Hi-Z

Figure 12: MEMW# Timing (MC68000)

Table 7-3: MEMW# Timing (MC68000)

3V/3.3V 5V

Symbol Parameter Min Max Min Max Units

t1

AB[19:1] and MEMCS# valid before AS# falling edge

t2

AB[19:1] and MEMCS# hold from AS# rising edge

t3

AS# falling edge to DTACK# falling edge

t4

AS# rising edge to DTACK hi-z delay

t5

AS# falling edge to DB[15:0] valid

t6

DB[15:0] hold from AS# rising edge

00ns
00ns

3.5 *

MCLK

+ 20

3.5 *

MCLK

+ 10

40 25 ns

MCLK

-40

MCLK

-20

00ns

ns

ns

Where MCLK period = 1/f

OSC

, or 2/f

OSC

, or 4/f

depending on which disp lay mod e the chi p is in. (s ee s ectio n 9.2 and

OSC

9.3)

Hardware Functional Specification S1D13503
Issue Date: 01/01/29 X18A-A-001-08

Page 32 Epson Resear ch and Development

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MEMR# Timing

AB[19:1]

MEMCS#

AS#

UDS#/LDS#

R/W#

DTACK#

DB[15:0]

t1

INVALID

Hi-Z

Hi-Z

VALID

t2

t4

t3

t5

VALID

Hi-Z

t6

t7

Figure 13: MEMR# Timing (MC68000)

Table 7-4: MEMR# Timing (MC68000)

3V/3.3V 5V

Symbol Parameter Min Max Min Max Units

t1

AB[19:1] and MEMCS# valid before AS# falling edge

t2

AB[19:1] and MEMCS# hold from AS# rising edge

t3

AS# falling edge to DTACK# falling edge

t4

AS# rising edge to DTACK# hi-z delay

t5

DTACK# falling edge to DB[15:0] valid

t6

DB[15:0] hold from AS# rising edge

t7

AS# rising edge to DB[15:0] hi-z delay

00ns
00ns

3.5 *

MCLK

+ 20

3.5 *

MCLK

+ 10

40 15 ns
20 15 ns
25 15 ns
40 30 ns

Hi-Z

ns

Where MCLK period = 1/f

OSC

, or 2/f

OSC

, or 4/f

depending on which disp lay mod e the chi p is in. (s ee s ectio n 9.2 and

OSC

9.3)

S1D13503 Hardware Functional Specification
X18A-A-001-08 Issue Date : 01/01/29

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7.1.2 Non-MC68000, MPU/Bus With READY (or WAIT#) Signal

IOW # Timing

AB[9:0]

BHE#

IOCS#

t1

IOW#

DB[15:0]

VALID

Hi-Z

t5

VALID

t2

t4t3

Hi-Z

Figure 14: IOW# Timing (Non-MC68000)

Table 7-5: IOW# Timing (Non-MC68000)

3V/3.3V 5V

Symbol Parameter Min Max Min Max Units

AB[9:0], BHE# and IOCS# valid before IOW# falling

t1

edge

t2

AB[9:0], BHE# and IOCS# hold from IOW# rising edge

t3

DB[15:0] setup to IOW# rising edge

t4

DB[15:0] hold from IOW# rising edge

t5

Pulse width of IOW#

10 0 ns
20 10 ns

20 10 ns
20 10 ns
30 20 ns

Hardware Functional Specification S1D13503
Issue Date: 01/01/29 X18A-A-001-08

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IOR# Timing

AB[9:0]

BHE#

IOCS#

IOR#

DB[15:0]

t1

Hi-Z

t3

VALID

t2

t4

VALID

t5

Figure 15: IOR# Timing (Non-MC68000)

Table 7-6: IO R# Timing (Non-MC68000)

3V/3.3V 5V

Symbol Parameter Min Max Min Max Units

AB[9:0], BHE# and IOCS# valid before IOR# falling

t1

edge

t2

AB[9:0], BHE# and IOCS# hold from IOR# rising edge

t3

IOR# falling edge to DB[15:0] valid

t4

DB[15:0] hold from IOR# rising edge

t5

IOR# rising edge to DB[15:0] hi-z delay

10 0 ns
20 10 ns

60 40 ns
20 15 ns
35 25 ns

Hi-Z

S1D13503 Hardware Functional Specification
X18A-A-001-08 Issue Date : 01/01/29

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MEMW# Timing

AB[19:0]

BHE#

MEMCS#

MEMW#

READY

DB[15:0]

t1

t3 t6

Hi-Z

VALID

t2

Hi-Z

t5

Hi-Z

t4

VALID

Hi-Z

Figure 16: MEMW# Timing (Non-MC68000)

Table 7-7: MEMW# Timing (Non-MC68000)

3V/3.3V 5V

Symbol Parameter Min Max Min Max Units

AB[19:0], BHE# and MEMCS# valid before MEMW#

t1

falling edge
AB[19:0], BHE# and ME MCS# hold fr om MEMW#

t2

rising edge

t3

MEMW# falling edge to READY falling edge

t4

MEMW# falling edge to DB[15:0] valid

t5

DB[15:0] hold from MEMW# rising edge

t6

READY negated pulse width

00ns

00ns

30 20 ns

MCLK

-40

MCLK

-20

ns

00ns

3.5*

MCLK

+ 20

3.5*

MCLK

+ 10

ns

Where MCLK period = 1/f

OSC

, or 2/f

OSC

, or 4/f

depending on which disp lay mod e the chi p is in. (s ee s ectio n 9.2 and

OSC

9.3)

Hardware Functional Specification S1D13503
Issue Date: 01/01/29 X18A-A-001-08

Page 36 Epson Resear ch and Development

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MEMR# Timing

AB[19:0]

BHE#

MEMCS#

MEMR#

READY

DB[15:0]

t1

t3 t7

Hi-Z

VALID

Hi-Z

t2

Hi-Z

t6

t5

VALID

t4

Figure 17: MEMR# Timing (Non-MC68000)

Table 7-8: MEMR# Timing (Non-MC68000)

3V/3.3V 5V

Symbol Parameter Min Max Min Max Units

AB[19:0], BHE# and MEMCS# valid before MEMR#

t1

falling edge
AB[19:0], BHE# and ME MCS# hold fr om MEMR#

t2

rising edge

t3

MEMR# falling edge to READY falling edge

t4

READY rising edge to DB[15:0] valid

t5

DB[15:0] hold from MEMR# rising edge

t6

MEMR# rising edge to DB[15:0] hi-z delay

t7

READY negated pulse width

00ns

00ns

30 20 ns
15 10 ns
20 10 ns
30 20 ns

3.5*

MCLK

+ 20

3.5*

MCLK

+ 10

Hi-Z

ns

Where MCLK period = 1/f

OSC

, or 2/f

OSC

, or 4/f

depending on which display mode the chip is in. (See sect ion 9.2 and

OSC

9.3.)

S1D13503 Hardware Functional Specification
X18A-A-001-08 Issue Date : 01/01/29

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7.2 Clock Input Requirements

Clock Input Waveform

t

PWL

t

f

90%
V

IH

V

IL

10%

t

t

PWH

r

T

OSC

Figure 18: Clock Input Re quirements

Table 7-9: Clock Input Requirements

Symbol Parameter Min Typ Max Units

T

t
t

OSC
PWH
PWL

t

f

t

r

Input Clock Period (CLKI)
Input Clock Pulse Width High (CLKI)
Input Clock Pulse Width Low (CLKI)
Input Clock Fall Time (10% - 90%)
Input Clock Rise Time (10% - 90%)

40 ns
40% 60% T
40% 60% T

5ns
5ns

OSC
OSC

Hardware Functional Specification S1D13503
Issue Date: 01/01/29 X18A-A-001-08

Page 38 Epson Resear ch and Development

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7.2.1 Recommended Clock Input

The nominal frequency must be calculated based on the formulas found in Frame Rate Calculation on page 84.
The crystal oscillator must be “fundamental mode” and have the following recommended RC load values:

R

= 2MΩ ± 5%

L

C

= 6.8 pF

L

The figure below demonstrates both a crystal interface and an oscillator interface to the S1D13503.

Crystal Interface Oscillator Interface

V

V

CC

CC

NC

S1D13503

92

C

L

R

L

X1

S1D13503

92

OUT

X1

GND

93

C

L

93

Figure 19: Recommended Clock Interface

S1D13503 Hardware Functional Specification
X18A-A-001-08 Issue Date : 01/01/29

Epson Research and Development Page 39

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7.3 Display Memory Interface Timing

7.3.1 Write Data to Display Memory

VA[15:0]

VCS0#, VCS1#

VWE#

VOE#

VD[15:0]

Hi-Z

INPUT

VALID

t1

t2 t3

t4

t5

Hi-Z

t6

OUTPUT

Hi-Z

INPUT

Figure 20: Write Data to Display Memory

Table 7-10: Write Data to Display Memory

3V/3.3V 5V

Symbol Parameter Min Max Min Max Units

t1

Address cycle time
VA[15:0], VCS0# and VCS1# valid before

t2

VWE# falling edge
VA[15:0], VCS0# and VCS1# hold from

t3

VWE# rising edge

t4

Pulse width of VWE#

t5

VD[15:0] setup to VWE# rising edge

t6

VD[15:0] hold from VWE# rising edge

MCLK - 15 MCLK - 10 ns

00ns

00ns

MCLK - 15 MCLK - 10 ns
MCLK - 20 MCLK - 15 ns

00ns

Hi-Z

Where MCLK period = 1/f

OSC

, or 2/f

OSC

, or 4/f

depending on which display mode th e chip is in. (See section 9.2 and

OSC

9.3.)

Hardware Functional Specification S1D13503
Issue Date: 01/01/29 X18A-A-001-08

Page 40 Epson Resear ch and Development

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7.3.2 Read Data From Display Memory

VA[15:0]

VCS0#, VCS1#

VD[15:0]

INPUT

VALID

t2

t1

t3

INPUT

INPUT

Figure 21: Read Data From Display Memory

Table 7-11: Read Data From Display Memory

3V/3.3V 5V

Symbol Parameter Min Max Min Max

t1

Address cycle time

t2

VA[15:0], VCS0# and VCS1# access time

t3

VD[15:0] hold time

Where MCLK period = 1/f

OSC

, or 2/f

OSC

, or 4/f

OSC

MCLK - 15 MCLK - 10

MCLK - 40 MCLK - 25

00

depending on which display mode the chip is in. (See sect ion 9.2 and

9.3.)

S1D13503 Hardware Functional Specification
X18A-A-001-08 Issue Date : 01/01/29

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7.4 LCD Interface

7.4.1 LCD Interface Timing - 4-Bit Single, 8-Bit Single/Dual Monochrome Panels

S1D13503 outputs

t2

YD

t3

LP

t4

WF

S1D13503 outputs
(AUX[01] bit 5 = 0)

t1

S1D13503 outputs
(AUX[01] bit 5 = 1)

XSCL

UD[3:0]
LD[3:0]

LP

XSCL

UD[3:0]
LD[3:0]

LP

80

t6b, t6c

t13

t8

t7a

12

t7b

t11

t9t5 t6a

t12t11

t12

12

t10

t8

t9 t10

Figure 22: LCD Interface Ti ming - Mono chrome Panel

Hardware Functional Specification S1D13503
Issue Date: 01/01/29 X18A-A-001-08

Page 42 Epson Resear ch and Development

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Table 7-12: LCD Interface Timing - 4-Bit Single and 8-Bit Single/Dual Monochrome Panel

4-Bit Single 8-Bit Single/Dual

Symbol Parameter Min Max Min Max Units

t1

LP period (single panel mode)

t1

LP period (dual panel mode)

t2

YD hold from LP falling edge (AUX[01] bit 5 = 0)

t2

YD hold from LP falling edge (AUX[01] bit 5 = 1)

t3

LP pulse width (AUX[01] bit 5 = 0)

t3

LP pulse width (AUX[01] bit 5 = 1)

t4

WF delay from LP falling edge

HT + HNDP -

10

n/a

- 10 8t

8t

OSC

13t

- 10 13t

OSC

6t

- 5 6t

OSC

5t

- 5 5t

OSC

0 20 0 20 ns

HT + HNDP -

10

2(HT + HNDP) -

10

- 10 ns

OSC

- 10 ns

OSC

- 5 ns

OSC

- 5 ns

OSC

LP setup to XSCL falling edge (AUX[01] bit 5 = 0 and

t5

AUX[03]

n/a 2t

- 5 ns

OSC

bit 2 = 0)
LP hold from XSCL falling edge (AUX[01] bit 5 = 0 and

t6a

AUX[03] bit 2 = 0)
LP hold from XSCL falling edge (AUX[01] bit 5 = 0 and

t6a

AUX[03] bit 2 = 1)
XSCL falling edge to LP falling edge - single panel mode

t6b

(AUX[01] bit 5 = 1 and AUX[03] bit 2 = 0)
XSCL falling edge to LP falling edge - single panel mode

t6b

(AUX[01] bit 5 = 1 and AUX[03] bit 2 = 1)
XSCL falling edge to LP falling edge - dual panel mode

t6c

(AUX[01] bit 5 = 1 and AUX[03] bit 2 = 0)
XSCL falling edge to LP falling edge - dual panel mode

t6c

(AUX[01] bit 5 = 1 and AUX[03] bit 2 = 1)
LP falling edge to XSCL falling edge (AUX[01] bit 5 = 0 and

t7a

AUX[03] bit 2 = 0)
LP falling edge to XSCL falling edge (AUX[01] bit 5 = 0 and

t7a

AUX[03] bit 2 = 1)
LP falling edge to XSCL falling edge (AUX[01] bit 5 = 1

t7b

and AUX[03] bit 2 = 0)
LP falling edge to XSCL falling edge (AUX[01] bit 5 = 1

t7b

and AUX[03] bit 2 = 1)

t8

XSCL period (AUX[03] bit 2 = 0)

t8

XSCL period (AUX[03] bit 2 = 1)

t9

XSCL high width (AUX[03] bit 2 = 0)

t9

XSCL high width (AUX[03] bit 2 = 1)

t10

XSCL low width (AUX[03] bit 2 = 0)

t10

XSCL low width (AUX[03] bit 2 = 1)
UD[3:0], LD[3:0] setup to XSCL falling edge (AUX[03] bit 2

t11

= 0)

2t

- 5 4t

2t

OSC

t

- 5 2t

OSC

13t

- 5 15t

OSC

12t

- 5 13t

OSC

n/a 31t

n/a 29t

2t

- 5 4t

OSC

t

- 5 2t

OSC

7t

- 5 9t

OSC

6t

- 5 7t

OSC

4t

- 5 8t

OSC

2t

- 5 4t

OSC

2t

- 5 4t

OSC

t

- 5 2t

OSC

2t

- 10 4t

OSC

t

- 10 2t

OSC

- 10** 4t

OSC

- 5 ns

OSC

- 5 ns

OSC

- 5 ns

OSC

- 5 ns

OSC

- 5 ns

OSC

- 5 ns

OSC

- 5 ns

OSC

- 5 ns

OSC

- 5 ns

OSC

- 5 ns

OSC

- 5 ns

OSC

- 5 ns

OSC

- 5 ns

OSC

- 5 ns

OSC

- 10 ns

OSC

- 10 ns

OSC

- 10** ns

OSC

ns

ns

S1D13503 Hardware Functional Specification
X18A-A-001-08 Issue Date : 01/01/29

Epson Research and Development Page 43

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Table 7-12: LCD Interface Timing - 4-Bit Single and 8-Bit Single/Dual Monochrome Panel

UD[3:0], LD[3:0] setup to XSCL falling edge (AUX[03] bit 2

t11

= 1)
UD[3:0], LD[3:0] hold from XSCL falling edge (AUX[03] bit

t12

2 = 0)
UD[3:0], LD[3:0] hold from XSCL falling edge (AUX[03] bit

t12

2 = 1)

t13

LP falling edge to XSCL rising edge (AUX[01] bit 5 = 1)

Where t
where HT = (number of horizontal panel pi xel s ) * t
where HNDP = horizontal non-display period in units of t
** -10 ns for 5V operation, - 24 ns for 3.0V and 3.3V operation.

OSC

= 1/f

= input (pixel) clock period,

OSC

OSC

,

OSC

(see Section 9.3 o n page 84 for details).

t

- 10** 2t

OSC

2t

- 10 4t

OSC

t

- 10 2t

OSC

5t

- 5 5t

OSC

- 10** ns

OSC

- 10 ns

OSC

- 10 ns

OSC

- 5 ns

OSC

Hardware Functional Specification S1D13503
Issue Date: 01/01/29 X18A-A-001-08

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7.4.2 LCD Interface Timing - 4-Bit Single Color Panel

t2

YD

XSCL

LP

WF

LP

t3

t4

t5

t7

t6

t13

t9

t8

t10

t1

UD

t11 t12

123

Figure 23: LCD Interface Timing - 4-Bit Single Color Panel

4

S1D13503 Hardware Functional Specification
X18A-A-001-08 Issue Date : 01/01/29

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Table 7-13: LCD Interface Timing - 4-Bit Single Color Panel

Symbol Parameter Min Typ Max Units

t1
t2
t3

t4
t5

t6
t7

t8

t9
t10
t11
t12
t13

Where t

OSC

where HT = (number of horizontal panel pi xel s ) * t
where HNDP = horizontal non-display period in units of t
** 5V operation, for 3.0V and 3.3V operation T11 will be 0.5t

LP period
YD hold from LP falling edge
LP pulse width
WF delay from LP falling edge
LP setup to XSCL falling edge
XSCL falling edge to LP falling edge
LP falling edge to XSCL falling edge
XSCL period
XSCL high width
XSCL low width
UD setup to XSCL falling edge
UD hold from XSCL falling edge
LP falling edge to XSCL rising edge

= 1/f

= input (pixel) clock period,

OSC

OSC

,

OSC

HT + HNDP - 10 ns

13t

- 10 ns

OSC

5t

- 5 ns

OSC

020ns

19t

- 5 ns

OSC

20t

- 5 ns

OSC

14t

- 5 ns

OSC

- 5 ns

t

OSC

0.5t

0.5t

0.5t

0.5t

13.5t

(see Section 9.3 o n page 84 for details).

- 24.

OSC

- 5 ns

OSC

- 5 ns

OSC

- 10** ns

OSC

- 10 ns

OSC

- 10 ns

OSC

Hardware Functional Specification S1D13503
Issue Date: 01/01/29 X18A-A-001-08

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7.4.3 LC D Interface Timing - 8-Bit Single Color Panels Format 2/8-Bit Dual Color Panels

t2

YD

XSCL

LP

WF

LP

t3

t4

t5

t7

t6

t13

t12t11

t8

t10t9

t1

UD/LD

123

4

Figure 24: LCD Interface Timing - 8-Bit Single Color Panels Format 2/8-Bit Dual Color Panels

S1D13503 Hardware Functional Specification
X18A-A-001-08 Issue Date : 01/01/29

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Table 7-14: LCD Interface Timing - 8-Bit Si ngle Color Panels Format 2/8-Bit Dual Color Panels

Symbol Parameter Min Typ Max Units

t1

t1

t2

t3

t4

t5

t6

t6

t7

t8

t9
t10
t11
t12
t13

Where t

OSC

where HT = (number of horizontal panel pi xel s ) * t
where HNDP = horizontal non-display period in units of t
** 5V operation, for 3.0V and 3.3V operation T11 will be 1.5t

LP period (single panel mode)
LP period (dual panel mode)
YD hold from LP falling edge
LP pulse width
WF delay from LP falling edge
LP setup to XSCL falling edge
XSCL falling edge to LP falling edge

(single panel mode)
XSCL falling edge to LP falling edge

(dual panel mode)
LP falling edge to XSCL falling edge
XSCL period
XSCL high width
XSCL low width
UD/LD setup to XSCL falling edge
UD/LD hold from XSCL falling edge
LP falling edge to XSCL rising edge

= 1/f

= input (pixel) clock period,

OSC

OSC

,

OSC

HT + HNDP - 10 ns

2(HT + HNDP) - 10 ns

13t

- 10 ns

OSC

5t

- 5 ns

OSC

020ns

19.5t
20t

52t

14.5t

2.5t

1.5t

1.5t

13.5t

(see Section 9.3 o n page 84 for details).

- 24.

OSC

- 5 ns

OSC

- 5 ns

OSC

- 5 ns

OSC

- 5 ns

OSC

- 5 ns

OSC

t

- 5 ns

OSC

- 5 ns

OSC

- 10** ns

OSC

t

- 5 ns

OSC

- 10 ns

OSC

Hardware Functional Specification S1D13503
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Page 48 Epson Resear ch and Development

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7.4.4 LCD Interface Timing - 16-Bit Single/Dual Color Panels

t2

YD

XSCL

LP

WF

LP

t4

t6 t13

t3

t5

t7

t9

t8

t10

t1

UD/LD

t11 t12

123

t14

t15

4

Figure 25: LCD Interface Timing - 16-Bit Single/Dual Color Panels

S1D13503 Hardware Functional Specification
X18A-A-001-08 Issue Date : 01/01/29

Epson Research and Development Page 49

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Table 7-15: LCD Interface Timing - 16-Bit Single/Dual Color Panels

Symbol Parameter Min Typ Max Units

t1
t1
t2
t3

t4
t5

t6

t6
t7

t8

t9
t10
t11
t12
t13
t14
t15

Where t

OSC

where HT = (number of horizontal panel pixels) * t
where HNDP = horizontal non-display period in units of t
** 5V operation, for 3.0V and 3.3V operation T11 will be 1.5t

LP period (single panel mode)
LP period (dual panel mode)
YD hold from LP falling edge
LP pulse width
WF delay from LP falling edge
LP setup to XSCL falling edge
XSCL falling edge to LP falling edge

(single panel mode)
XSCL falling edge to LP falling edge

(dual panel mode)
LP falling edge to XSCL falling edge
XSCL period
XSCL high width
XSCL low width
UD/LD setup to XSCL falling edge
UD/LD hold from XSCL falling edge
LP falling edge to XSCL rising edge
UD/LD setup to XSCL rising edge
UD/LD hold from XSCL rising edge

= 1/f

= input (pixel) clock period,

OSC

OSC

,

OSC

HT + HNDP - 10 ns

2(HT + HNDP) - 10 ns

13t

- 10 ns

OSC

5t

- 5 ns

OSC

020ns

22t

- 5 ns

OSC

20t

- 5 ns

OSC

- 5 ns

52t

OSC

17t

- 5 ns

OSC

- 5 ns

5t

OSC

2t

- 5 ns

OSC

3t

- 10 ns

OSC

1.5t

(see Section 9.3 on page 84 for details).

- 24.

OSC

- 10** ns

OSC

t

- 5 ns

OSC

15t

- 10 ns

OSC

1.5t

- 10 ns

OSC

0.5t

- 5 ns

OSC

Hardware Functional Specification S1D13503
Issue Date: 01/01/29 X18A-A-001-08

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7.4.5 LC D Interface Timing - 8-Bit Single Color Panels Format 1

t2

YD

XSCL2
(WF)

XSCL

LP

LP

t7a

t7b

t14b

t6b

t8b

t14a

t6a

t8a

t3

t9b

t11b t10b

t11a t10a

t1

t9a

t12a t13at12b

UD/LD

t13b

123

Figure 26: LCD Interface Timing - 8-Bit Single Color Panels Format 1

S1D13503 Hardware Functional Specification
X18A-A-001-08 Issue Date : 01/01/29

Epson Research and Development Page 51

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Table 7-16: LCD Interface Timing - 8-Bit Single Color Panels Format 1

Symbol Parameter Min Typ Max Units

t1
t2
t3

t6a
t6b
t7a

t7b
t8a
t8b
t9a
t9b

t10a

t10b

t11a

t11b

t12a

t12b

t13a

t13b

t14a

t14b

Where t

OSC

where HT = (number of horizontal panel pi xel s ) * t
where HNDP = horizontal non-display period in units of t
** 5V operation, for 3.0V and 3.3V operation T12 will be 1.5t

LP period
YD hold from LP falling edge
LP pulse width
LP setup to XSCL falling edge
LP setup to XSCL2 falling edge
XSCL falling edge to LP falling edge
XSCL2 falling edge to LP falling edge
LP falling edge to XSCL falling edge
LP falling edge to XSCL2 falling edge
XSCL period
XSCL2 period
XSCL high width
XSCL2 high width
XSCL low width
XSCL2 low width
UD/LD setup to XSCL falling edge
UD/LD setup to XSCL2 falling edge
UD/LD hold from XSCL falling edge
UD/LD hold from XSCL2 falling edge
LP falling edge to XSCL rising edge
LP falling edge to XSCL2 rising edge

= 1/f

= input (pixel) clock period,

OSC

OSC

,

OSC

HT + HNDP - 10 ns

13t

- 10 ns

OSC

5t

- 5 ns

OSC

22t

- 5 ns

OSC

19.5t
20t

23.5t
17t

14.5t

3t
3t

1.5t

1.5t

16t

13.5t

(see Section 9.3 o n page 84 for details).

- 24.

OSC

- 5 ns

OSC

- 5 ns

OSC

- 5 ns

OSC

- 5 ns

OSC

- 5 ns

OSC

- 5 ns

4t

OSC

4t

- 5 ns

OSC

t

- 5 ns

OSC

- 5 ns

t

OSC

- 10 ns

OSC

- 10 ns

OSC

- 10** ns

OSC

- 10** ns

OSC

t

- 5 ns

OSC

- 5 ns

t

OSC

- 10 ns

OSC

- 10 ns

OSC

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7.4.6 LCD Interface Options

YD

LP

WF

UD[3:0]

LP

WF

XSCL

UD3
UD2
UD1
UD0

Example Timing for a 320x240 single panel

LINE1 LINE2 LINE3 LINE4 LINE239

1-1 1-5
1-2 1-6
1-3
1-4 1-8

1-7

LP : 240 PULSES

LINE240

XSCL: 80 CLOCK PERIODS

LP: 4 PULSES

LINE1 LINE2

1-317
1-318
1-319
1-320

Figure 27: 4-Bit Single Monochrome Panel Timing

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YD

LP

WF

UD[3:0], LD[3:0]

LP

WF

XSCL

UD3
UD2
UD1
UD0

LD3
LD2
LD1
LD0

LP : 480 PULSES

LINE1 LINE2 LINE3 LINE4 LINE479 LINE480

LP: 4 PULSES

XSCL:80 CLOCK PERIODS

1-1 1-9

1-2 1-10 1-634
1-3

1-11
1-4 1-12
1-5 1-13

1-6 1-14
1-7 1-15 1-639

1-8 1-16

1-633

1-635
1-636
1-637
1-638

1-640

LINE1 LINE2

Example timing for a 640x480 panel

Figure 28: 8-Bit Single Monochrome Panel Timing

Hardware Functional Specification S1D13503
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YD

LP

WF

UD[3:0], LD[3:0]

LP

WF

XSCL

UD3
UD2
UD1
UD0

LD3
LD2
LD1
LD0

LP : 240 PULS E S

LINE1/241 LINE 2/2 42 LINE3/243 LINE4/244

LINE 239/479 LINE240/480

LP: 2 PULSES

XSCL: 160 CLOCK PERIODS

1-1 1-5

1-2 1-6 1-638

1-3

1-7

1-4 1-8
241-1 241-5
241-2 241-6
241-3 241-7
241-4 241-8

241-637
241-638
241-639
241-640

LINE1/241 LINE2/242

1-637

1-639
1-640

Example timing for a 640x480 panel

Figure 29: 8-Bit Dual Monochrome Panel Timing

S1D13503 Hardware Functional Specification
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YD

WF

UD[3:0]

LP
WF

XSCL

UD3
UD2
UD1
UD0

LP

LP : 240 PULSES

LINE1 LINE2 LINE3 LINE4 LINE239

LINE240

LP: 4 PULSES

XSCL: 240 CLOCK PERIODS

1-R1 1-G2
1-G1 1-B2

1-B1
1-R2 1-G3 1-B320

1-R3

1-B3
1-R4

1-G4
1-B4

1-B319
1-R320
1-G320

LINE1 LINE2

Example timing for a 320x240 panel

Figure 30: 4-Bit Single Color Panel Timing

Hardware Functional Specification S1D13503
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YD

LP

UD[3:0]

LD[3:0]

LP

XSCL2

XSCL

UD3

UD2

UD1

LP: 480 PULSES

LINE1 LINE480LINE2 LINE3 LINE4 LINE479 LINE1 LINE2

LP: 4 PULSES

XSCL2: 120 CLOCK PERIODS

XSCL: 120 CLOCK PERIODS

1-R1

1-B1

1-G2

1-G1

1-R2

1-B2

1-G6

1-R7

1-B7

1-B6

1-G7

1-R8

1-B11

1-G12

1-R13

1-R12

1-B12

1-G13

1-B635

1-G636

1-R637

1-R636

1-B636

1-G637

UD0

LD3

LD2

LD1

LD0

1-R3

1-B3

1-G4

1-R5

1-B5

1-G3

1-R4

1-B4

1-G5

1-R6

1-G8

1-R9

1-B9

1-G10

1-R11

1-B8

1-G9

1-R10

1-B10

1-G11

1-B13

1-G14

1-R15

1-B15

1-G16

1-R14

1-B14

1-G15

1-R16

1-B16

1-B637

1-G638

1-R639

1-B639

1-G640

1-R638

1-B638

1-G639

1-R640

1-B640

Example timing for a 640x480 panel

Figure 31: 8-Bit Single Color Panel Timing - Format 1 : AUX[03] Bit 3 = 0 and AUX[01] Bit 2 = 1

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YD

LP

WF

UD[3:0]
LD[3:0]

LP

WF

XSCL

UD3
UD2
UD1
UD0

LD3
LD2
LD1
LD0

LP : 240 PULSES

LINE1 LINE2 LINE3 LINE4 LINE239 LINE 240

XSCL: 120 CLOCK PERIODS

1-R1 1-B3

1-G1 1-R4

1-B1

1-R2 1-B4

1-G2 1-R5

1-B2 1-G5

1-R3

1-G3 1-R6

1-G4

1-B5

1-G6

1-B6

1-R7
1-G7

1-B7

1-R8

1-G8
1-B8

LP: 4 PULSES

LINE1 LINE2

1-G318
1-B318

1-R319

1-G319

1-B319
1-R320
1-G320
1-B320

Example timing for a 320x240 panel

Figure 32: 8-Bit Single Color Panel Timing - Format 2 : AUX[03] Bit 3 = 1 and AUX[01] Bit 2 = 1

Hardware Functional Specification S1D13503
Issue Date: 01/01/29 X18A-A-001-08

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YD

LP

WF

UD[3:0]

LD[3:0]

LP

WF

XSCL

UD3

UD2

UD1

UD0

LD3

LD2

LD1

LD0

LP: 240 PULSES

LINE1 LINE240LINE2 LINE3 LINE4 LINE239 LINE1 LINE2

LINE241 LINE480LINE242 LINE243 LINE244 LINE479 LINE241 LINE242

LP: 2 PULSES

XSCL: 480 CLOCK PERIODS

1-R1

1-G1

1-B1

1-R2

241-R1

241-G1

241-B1

241-R2

241-G2

241-B2

241-R3

241-G3

1-G2

1-B2

1-R3

1-G3

1-B3

1-R4

1-G4

1-B4

241-B3

241-R4

241-G4

241-B4

1-R637

1-G637

1-B637

1-R638

241-R637

241-G637

241-B637

241-R638

1-G638

1-B638

1-R639

1-G639

241-G638

241-B638

241-R639

241-G639

1-B639

1-R640

1-G640

1-B640

241-B639

241-R640

241-G640

241-B640

Example timing for a 640x480 panel

Figure 33: 8-Bit Dual Color Panel Timing

UD[3:0]

FROM

UD[3:0]

LD[3:0]

LD[3:0 ]

D

Q

UD[7:4]
LD[7:4 ]

TO 16-BIT
PANEL

S1D13503

XSCL

CK

Figure 34: External Circuit Required for 16-Bit Panel

S1D13503 Hardware Functional Specification
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Pixel D ata

S1D13503 OUTPUTS

YD
LP

WF

LP
WF

XSCL

UD3
UD2
UD1
UD0

LD3
LD2
LD1
LD0

LP : 480PULSES

LINE1 LINE2 LINE3 LINE4 LINE479 LINE480

XSCL: 120 CLOCKS

1-R1

1-B3

1-B1 1-G4

1-R5

1-G2

1-B5

1-R3

1-R4

1-G1

1-B4

1-R2

1-G5

1-B2

1-R6

1-G3

1-B635

1-G636

1-R637

1-B637

1-R636

1-B636

1-G637

1-R638

LP: 4 PULSES

1-G638

1-R639

1-B639

1-G640

1-B638

1-G639

1-R640

1-B640

LINE1

LINE2

UD7
UD6
UD5
UD4

UD3
UD2
UD1
UD0

LD7
LD6

16-BIT PANEL INPUTS

LD5
LD4

LD3
LD2
LD1
LD0

Example timing for a 640x480 panel

1-R1

1-B1

1-G2

1-R3

1-B3

1-G4

1-R5

1-B5

1-G1

1-R2

1-B2

1-G3

1-R4

1-B4

1-G5

1-R6

1-B635

1-G636

1-R637

1-B637

1-G638

1-R639

1-B639

1-G640

1-R636

1-B636

1-G637

1-R638

1-B638

1-G639

1-R640

1-B640

Figure 35: 16-Bit Single Color Panel Timing with External Circuit

Hardware Functional Specification S1D13503
Issue Date: 01/01/29 X18A-A-001-08

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Pixel D ata

S1D13503 OUTPUTS

YD

LP

WF

LP

WF

XSCL

UD3
UD2
UD1
UD0

LD3
LD2
LD1
LD0

LINE1/241

LINE2/242 LINE3/243 LINE4/244 LINE239/479 LINE240/480 LINE1/241 LINE2/242

1-R1

1-G2

1-B3

1-G1 1-B2

1-B1

1-R2

241-R1

241-G1 241-B2 241-R4

241-B1 241-R3 241-B4

241-R2 241-G3 241-B4

1-R4

1-G4

1-R3

1-B4

1-G3

241-G2 241-B3

LP : 240 PULSES

XSCL: 240 CLOCKS

1-G638

1-B638

1-R639

1-G639

241-

G638

241-

B638

241-

R639

241-

G639

LP: 2 PULSES

1-B639

1-R640

1-G640

1-B640

241-

B639

241-

R640

241-

G640

241-

B640

UD7
UD6
UD5
UD4

UD3
UD2
UD1
UD0

LD7
LD6

16-BIT PANELINPUTS

LD5
LD4

LD3
LD2
LD1
LD0

Example timing for a 640x480 panel

1-R1

1-G1

1-B1

1-R2

1-G2

1-B2

1-R3

1-G3

241-R1

241-G1

241-B1

241-R2

241-G2

241-B2

241-R3

241-G3

1-G638

1-B638

1-R639

1-G639

1-B639

1-R640

1-G640

1-B640

241-G638

241-B638

241-R639

241-G639

241-

B639

241-

R640

241-

G640

241-

B640

Figure 36: 16-Bit Dual Color Panel Timing with External Circuit

S1D13503 Hardware Functional Specification
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8 HARDWARE REGISTER INTERFACE

The S1D13503 is configured and control le d via 16 int ern al 8- bit regi ster s. There are two ways to map these registers into
the system I/O space.

1. Direct-mapping: Absolute I/O address = system address lines AB[3:0] + base I/O mapped address
(where base I/O address is selected by VD7-VD12, see Table 5-6)

This scheme requires 16 sequential I/O addresses starting from the I/O mapped base address selected by VD7-VD12
(see Table 5-6).

To perform an I/O access:

write data IOW {absolute I/O address}, {data}
read data IOR {absolute I/O address}

2. Indexing: I/O address = internal index register bits [3:0]

This scheme requires 2 sequential I/O addresses starting from the base address selected by VD4-VD12
(see Table 5-6).

To perform an 8-bit I/O access:

write index IOW {I/O mapped address}, {index} ; write the index of the register to be accessed

then

write data IOW {I/O mapped address +1}, {data} ; write data to the indexed register

or

read data IOR {I/O mapped address +1} ; read the indexed register

To perform a 16-bit I/O access:

write data IOW {I/O mapped address}, {index,data} ; write the index and data of the register to be accessed

read data IOW {I/O mapped address}, {index} ; write to the indexed register

IOR {I/O mapped address +1} ; read the indexed register

8.1 Register Descriptions

AUX[00] Test Register

I/O address = 0000b, Read/Write
Test Mode

Enable

bit 7 Test Mode Enable

bit 6 Reserved

bits 5-0 Test Mode Input and Output Bits [2:0]

Reserved

When this bit = 0 normal operation is enabled. When this bit = 1 the chip is placed in a special test mode.
The test input bits and test output bits (bits 6:0) are used to select various internal test functions.

During normal operation this bit must = 0.

When bit 7 = 1 these are the Test Input Select Input and Output bits. When bits 6 and 7 = 0 (normal opera­tion) these bits may be used as read/write scratch registers.

Test Input
Select Bit 2

Test Input
Select Bit 1

Test Input
Select Bit 0

Test Output
Select Bit 2

Test Output
Select Bit 1

Test Output
Select Bit 0

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AUX[01] Mode Register 0

I/O address = 0001b, Read/Write.

DISP Panel

Mask
XSCL

LCDE

Gray Shade /
Color

LCD Data
Width Bit 0

Memory
Interface

RAMS

bit 7 DISP

This bit selects display on or off. When this bit = 0, Display OFF is selected (LD0-3 and UD0-3 are forced
to 0 ). When this bit = 1, Display ON is selected. This bit goes low on RESET.

bit 6 Panel

This bit selects the LCD panel configuration (single or dual). When this bit = 0, Si ngle LC D panel drive is
selected. When this bit = 1 Dual LCD panel drive is selected. This bit goes low on RESET.

bit 5 Mask XSCL

XSCL is automatically masked during the horizontal non-display period if any of the following criteria is
met:

• AUX[0C] value is greater than 00h.

• Color panel is selected.

• This bit (AUX[01] bit 5) = 1.

. XSCL will not be masked during the horizontal non-display period if color panel is not selected, AUX[0C]

= 00h and this bit = 0.

bit 4 LCDE

The state of this pin determines the state of output pin 82, LCDENB, and is intended for control of an
external LCDBIAS power supply. However, this pin can be used as a general I/O pin if desired. When
LCDE = 0, LCDENB is forced low. When LCDE = 1, LCDENB is forced high. LCDE goes low on
RESET.

bit 3 Gray Shade/Color

In gray shade display modes, this bit selects between 16-level or 4-level gray shade display. When this bit
= 1, 16 gray shades are displayed (4 bits/pixel). When this bit = 0, 4 gray shades of a possible 16 are dis­played (2 bits/pixel).

In color display modes, this bit selects between 16 color or 4 color display. When this bit = 1, 16 colors are
displayed out of a possible of 4096 colors (4 bits/pixel). When this bit = 0, 4 colors are displayed out of a
possible of 4096 colors (2 bits/pixel).

This bit is ignored when either black-and-white (BW) or 256 color mode is selected (AUX[03] bit 2 = 1).
This bit goes low on RESET.

Table 8-1: Gray Shade/Color Mode Selection

Display

Modes

Gray Shade/

Color

AUX[01] bit 3

BW/

256 Colors

AUX[03] bit 2

Color Mode

AUX[03] bit 1

256 Colors don’t care 1 1

16 Colors101

4 Colors001

16 Grays 1 0 0

4 Grays000

BW don’t care 1 0

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bit 2 LCD Data Width Bit 0

Together with LCD Data Width bit 1 (AUX[03] bit 3) this bit selects different display data formats. The
following table shows the function of these two bits:

Table 8-2: LCD Data Width

Panel

LCD Data

Width Bit 1

AUX[03] bit 3

LCD Data

Width Bit 0

AUX[01] bit 2

Function

Monochrome don’t care 0 4-bit LCD data width
Monochrome don’t care 1 8-bit LCD data width

Color 0 0 4-bit LCD data width
Color 0 1 8-bit LCD data width - format 1
Color 1 0 16-bit LCD data width (with external circuit)
Color 1 1 8-bit LCD data width - format 2

For 8-bit dual panels, the data transfer width is forced to 4 bits per panel. This bit goes low on RESET.

bit 1 Memory Interface

This bit selects between the 8-bit or 16-bit memory interface. When this bit = 0, the 16-bit memory inter­face is selected. When this bit = 1, the 8-bit memory interface is selected. If 16-bit bus interface (VD0 = 1
on RESET) or 256 color mode (AUX[03] bits 2-1 = 11) is selected, the Memory Interface bit is forced to 0
internally (16-bit). This bit goes low on RESET.

bit 0 RAMS

This bit configures the display memory address lines for an 8-bit memory interface system. When this bit
= 0, addressing for 8Kx8 SRAM on an 8-bit display m emory data bus interface is selected. When this bit =
1, addressing for 32Kx8 SRAM on an 8-bit display memory data bus interface is selected. This bit goes
low on RESET. This bit is ignored for a 16-bit me m ory interface.

AUX[02] Line Byte Count Register (LSB)

I/O address = 0010b, Read/Write.
Line Byte

Count Bit 7

Line Byte
Count Bit 6

Line Byte
Count Bit 5

Line Byte
Count Bit 4

bits 7-0 Line Byte Count Bits [7:0]

Along with Line Byte Count B i t 8 (AUX[03] bit 0), thi s is the n umber of bytes to be fetched per display
line minus 1. To calculate the Line Byte Count use the following formula:

LineByteCount Decimal

()

Example:

T o calculate the Line Byte Count for 640 horizontal pixels with 16 gray shades (4 bits-per-pixel) and 16-bit
memory interface:

LineByteCount Decimal

Line Byte
Count Bit 3

BitsPerPixel



--------------------------------------------------------------



MemoryInterfaceWidth

BitsPerPixel

4

()

-------------------------------------

=

16

Bits

Line Byte
Count Bit 2

×

HorizontalResolution

×

640 1 159=–

Line Byte
Count Bit 1

Line Byte
Count Bit 0

1–=

Hardware Functional Specification S1D13503
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The following two tables summarize the maximum value of the Line Byte Count Register for different
display modes and display memory interface.

Table 8-3: Maximum Value of Line Byte Count Register - 8-Bit Display Memory Interface

Display Modes

black-and-white (BW) 0FFh 256 x 8 = 2048

4-level gray shade / 4 colors 0FFh 256 x 4 = 1024

16-level gray shade / 16 colors 1FFh 512 x 2 = 1024

Table 8-4: Maximum Value of Line Byte Count Register - 16-Bit Display Memory Interface

Display Modes

black-and-white (BW) 0FFh 256 x 16 = 4096

4-level gray shade / 4 colors 0FFh 256 x 8 = 2048

16-level gray shade / 16 colors 0FFh 256 x 4 = 1024

256 colors 1FFh 512 x 2 = 1024

Maximum Value of

Line Byte Count Register

Maximum Value of

Line Byte Count Register

Corresponding Maximum

Number of Pixels in One

Display Line

Corresponding Maximum

Number of Pixels in One

Display Line

AUX[03] Mode Register 1

I/O address = 0011b, Read/Write
PS

Bit 1

bits 7-6 PS Bits [1:0]

bit 5 LCD Signal State

bit 4 LUT Bypass

PS
Bit 0

Selects the Power Save Modes as shown in the following tab le. The PS bits [1:0] go low on RESET.

Refer to Power Save Modes on page 77 for a complete Power Save Mode description.

When this bit = 0, all LCD interface signals are forced low during Power Save modes. When this bit = 1,
all LCD interface signals are forced to a high impedance (Hi-Z) state during Power Save modes. This bit
goes low on RESET.

When the LUT Bypass bit = 0, the Look-Up Table is used for display data output in gray shade modes.
When this bit = 1, the Look-Up Table is bypassed for display data output in gray shade modes (for power
save purposes). There is no effect on changing this bit in BW and color modes. In BW display mode, the
Look-Up Table is always bypasse d an d i n color display mode the Look-Up Table cannot be byp ass ed. The
LUT Bypass bit goes low on RESET.

LCD Signal
State

Table 8-5: Power Save Mode Selection

PS1 PS0 Mode Activated

0 0 Normal Operation
0 1 Power Save Mode 1
1 0 Power Save Mode 2
11 Reserved

LUT
Bypass

LCD Data
Width Bit 1

BW /
256 colors

Color Mode

Line Byte
Count Bit 8

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bit 3 LCD Data Width Bit 1

Together with LCD Data Width bit 0 (AUX[01] bit 2), this bit selects different display data formats. See
Table 8 -2, “LCD Dat a Width,” on page 63 for details. This bit goes low on RESET.

bit 2 BW / 256 colors

In BW/gray shade display modes, when this bit = 1, black-and-white (BW) mode is selected. When this bit
= 0, either 4-level gray shade mode or 16-level gray shade mode is selected.

In color display modes, when this bit = 1, 256 color mode is selected. When this bit = 0, either 4 color
mode or 16 color mode is selected. See Table 8-1, “Gray Shade/Color Mode Selection,” on page 62 for
details. This bit goes low on RESET.

bit 1 Color Mode

When this bit = 1, color display modes are selected. When bit = 0, BW/g ray shade display modes are
selected. See Table 8-1, “Gray Shade/Color Mode Selection,” on page 62 for details. This bit goes low on
RESET.

bit 0 Line Byte Count Bit 8

This is the MSB of the number of bytes to be fetched per display lin e minus 1 (see AUX[02]). This bit only
has effect when in either 16 colors/gray shades with 8-bit memory interface or 256 colors with 16-bit
memory interface.

.

AUX[04] Total Display Line Count Register (LSB) (Vertical Total)

I/O address = 0100b, Read/Write.
Total Disp.

Line Count
Bit 7

Total Disp.
Line Count
Bit 6

Total Disp.
Line Count
Bit 5

Total Disp.
Line Count
Bit 4

bits 7-0 Total Display Line Count Bits [7:0]

These are the 8 LSB of the 10 bit Total Display Line Count and represent the number of s can lines -1, to a
maximum value of 3FFh or 1024 scan lines.

In single panel mode:

TotalDisplayLineCount NumberOfDisplayLines

In dual pan el mode:

TotalDisplayLineCount

Note that the value programmed partially determines the frame period, and hence affects display duty
cycle. Bits 8 and 9 are located in the following register (AUX[05]).

Total Disp.
Line Count
Bit 3

NumberOfDisplayLines



---------------------------------------------------------------



Total Disp.
Line Count
Bit 2

2

Total Disp.
Line Count
Bit 1

1–=

1–=

Total Disp.
Line Count
Bit 0

Hardware Functional Specification S1D13503
Issue Date: 01/01/29 X18A-A-001-08

Page 66 Epson Resear ch and Development

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.

AUX[05] To tal Display Line Count (MSB) and WF Count Register

I/O address = 0101b, Read/Write

WF Count
Bit 5

bits 7-2 WF Count Bits [5:0]

bits 1-0 Total Display Line Count Bits [9:8]

AUX[06] Screen 1 Display Start Address Register (LSB)

I/O address = 0110b, Read/Write.

WF Count
Bit 4

These bits are used to adjust the WF output signal period. The binary value stored in these bits represents
the number of LP pulses -1 between toggles of the WF output. The power up reset value of these bits is 0,
which causes the WF output to toggle every frame. When values of 01h to 3Fh are programmed into these
bits, the results are WF toggling every 1+n LP pulses, where n is the value programmed. These bits have
no effect when 8-bit single color panel format 1 is selected.

These bits are the two MSB of the Total Display Lin e Count Register ( AUX[04]).

WF Count
Bit 3

WF Count
Bit 2

WF Count
Bit 1

WF Count
Bit 0

Total Disp.
Line Count
Bit 9

Total Disp.
Line Count
Bit 8

Screen 1
Display Start
Addr
Bit 7

AUX[07] Screen 1 Display Start Address Register (MSB)

I/O address = 0111b, Read/Write.
Screen 1

Display
Start Addr
Bit 15

AUX[06] bits 7-0 Screen 1 Display Start Address Bits [15:0]
AUX[07] bits 7-0 These 16 bits determine the Screen 1 Display Start Address. In an 8-bit memory configuration these bits

Note

The absolute address into display mem ory is determined by the Memory Mapping
Address which is set by VD13 - VD15 (see Table 5-6, “Summary of Power On / Re­set Options,” on page 26).

Screen 1
Display Start
Addr
Bit 6

Screen 1
Display
Start Addr
Bit 14

set the 16-bit start address (i.e., byte access). In a 16-bit memory configuration these are the 16 most sig­nificant bits of a 17-bit start address (i.e., word access).

The Screen 1 Display Start Address is the memory address corresponding to the first displayed pixel (top
left corner). In a dual panel configurati on, screen 1 refers to the upper half of the dis play. While in a single
panel configuration, screen 1 refers to the first screen of the Split Screen Display feature where two differ­ent images (screen 1 and screen 2) can be displayed at the same time on one display.

Screen 1
Display Start
Addr
Bit 5

Screen 1
Display
Start Addr
Bit 13

Screen 1
Display Start
Addr
Bit 4

Screen 1
Display
Start Addr
Bit 12

Screen 1
Display Start
Addr
Bit 3

Screen 1
Display
Start Addr
Bit 11

Screen 1
Display St art
Addr
Bit 2

Screen 1
Display
Start Addr
Bit 10

Screen 1
Display St art
Addr
Bit 1

Screen 1
Display
Start Addr
Bit 9

Screen 1
Display St art
Addr
Bit 0

Screen 1
Display
Start Addr
Bit 8

S1D13503 Hardware Functional Specification
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AUX[08] Screen 2 Display Start Address Register (LSB)

I/O address = 1000b, Read/Write.
Screen 2

Display
Start Addr
Bit 7

Screen 2
Display
Start Addr
Bit 6

Screen 2
Display
Start Addr
Bit 5

Screen 2
Display
Start Addr
Bit 4

Screen 2
Display
Start Addr
Bit 3

Screen 2
Display
Start Addr
Bit 2

Screen 2
Display
Start Addr
Bit 1

Screen 2
Display
Start Addr
Bit 0

AUX[09] Screen 2 Display Start Address Register (MSB)

I/O address = 1001b, Read/Write.
Screen 2

Display
Start Addr
Bit 15

Screen 2
Display
Start Addr
Bit 14

Screen 2
Display
Start Addr
Bit 13

Screen 2
Display
Start Addr
Bit 12

Screen 2
Display
Start Addr
Bit 11

Screen 2
Display
Start Addr
Bit 10

Screen 2
Display
Start Addr
Bit 9

Screen 2
Display
Start Addr
Bit 8

AUX[08] bits 7-0 Screen 2 Display Start Address Bits [15:0]
AUX[09] bits 7-0 These 16 bits determine the Screen 2 Display Start Address. In an 8-bit memory configuration these bits

set the 16-bit start address (i.e., byte access). In a 16-bit memory configuration these are the 16 most sig­nificant bits of a 17-bit start address (i.e., word access).

In a dual panel configuration, screen 2 refers to the lower half of the display. The Screen 2 Display Start
Address is the memory address corresponding to the first displayed pixel in the first line of the lower half
of the display. If screen 2 is started right after screen 1, the screen 2 display start address can be calculated
with the following formula:

Screen2DisplayStartAddress hex

()

()

ImageHorizontalRe solution

----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

()

ImageVerticalResolution

MemoryIn terface Width



----------------------------------------------------------------

×

2



8

()××

BytesPerPixel

Screen1DisplayStartAddress

+=

In a single panel configuration, screen 2 refers to the second screen of the Split Screen Display Feature
where two different images (screen 1 and screen 2) can be displayed at the same time on one display. The
Screen 2 Display Start Address is the mem ory addres s corr espond ing to th e first pixel of the second image
stored in display memory. To display screen 2 refer to AUX[0A] Screen 1 Display Line Count Register
(LSB) on page 68.

Hardware Functional Specification S1D13503
Issue Date: 01/01/29 X18A-A-001-08

Page 68 Epson Resear ch and Development

Vancouver Design Center

AUX[0A] Screen 1 Display Line Count Register (LSB)

I/O address = 1010b, Read/Write.
Screen 1

Display
Line Count
Bit 7

AUX[0B] Screen 1 Display Line Count Register (MSB)

I/O address = 1011b, Read/Write.

Screen 1
Display
Line Count
Bit 6

Screen 1
Display
Line Count
Bit 5

Screen 1
Display
Line Count
Bit 4

Screen 1
Display
Line Count
Bit 3

Screen 1
Display
Line Count
Bit 2

Screen 1
Display
Line Count
Bit 1

Screen 1
Display
Line Count
Bit 0

Screen 1

n/a n/a n/a n/a n/a n/a

AUX[0A] bits 7-0 Screen 1 Display Line Count Bits [9:0]
AUX[0B] bits 1-0 These bits are the eight LSB of a 10-bit v alue used to de termine the n umber of lines displayed for scr een 1.

The remaining lines will automatically display from the screen 2 display start addr ess. Th e 10-bit value
programmed is the number of display lines -1.

This register is used to enable the split screen display feature (single panel only) where two different
images can be displayed at the same time on one display.

For example; AUX[0A] = 20h for a 320x240 display system. The display will display 20h+1 = 33 lines on
the upper part of the screen as dictated by the screen 1 display start address registers (AUX[06] and
AUX[07]), and 240 - 33 = 207 lines will be displayed on the lower part of the screen as dictated by the
screen 2 display start address registers (AUX[08] and AUX[09]).

T w o di f ferent images can b e displayed wh en using a dual pan el conf iguration b y changing the s creen 2 dis­play start address. However, by using this method screen 2 is limited to the lower half of the display.

This registe r is ignored in dual pane l mode.

Display
Line Count
Bit 9

Screen 1
Display
Line Count
Bit 8

S1D13503 Hardware Functional Specification
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AUX[0C] Horizontal Non-Display Period

I/O address = 1100b, Read/Write.
Horizontal

Non­Display
Period
Bit 7

bits 7-0 Horizontal Non-Display Per iod Bi ts [7: 0]

Horizontal
Non­Display
Period
Bit 6

These bits are used to adjust the horizontal non-display period (See “Frame Rate Calculation” on page
84 for details). When these bits = 0, the fixed default non-display period (DHNDP) is used. Otherwise, a
non-display period of DHNDP & AUX[0C] +1 is used. The unit of AUX[0C] is the same as the unit of
Line Byte Count Register, i.e. number of bytes to be fetched. See description of AUX[02] and Section

9.3 on page 84 for details.
For example, if an additional 32 pixels wide of horizontal non-display period is desired in a 4

grays (2 bits-per-pixel) and 16-bit display memory interf ace system: A UX[0 C] = [32 / (16 / 2)] - 1
= 3.

Note that the value programmed determines the period of one line, and hence affects the frame period.

Horizontal
Non­Display
Period
Bit 5

Horizontal
Non­Display
Period
Bit 4

Horizontal
Non­Display
Period
Bit 3

Horizontal
Non­Display
Period
Bit 2

Horizontal
Non­Display
Period
Bit 1

Horizontal
Non­Display
Period
Bit 0

AUX[0D] Address Pitch Adjustment Register

I/O address = 1101b, Read/Write.
Addr Pitch

Adjustment
Bit 7

bits 7-0 Address Pitch Adjustm e nt Bits [7:0]

Addr Pitch
Adjustment
Bit 6

This register controls the virtual display by setting the numerical difference between the last address of a
display line, and the first address in the following line.

If the Address Pitch Adjustment is not equal to zero, then a virtual screen is formed. The size of the virtual
screen is only limited by the available display memory. The actual display output is a window that is part
of the whole image stored in the display memory. For example, with 128K of display memory, a 640x400
16-gray image can be stored. If the output display size is 320x240, then the whole image can be seen by
changing display st arti ng addresses through A UX[ 06] and [07], and AUX[08] an d [ 09]. Note that a virtual
screen can be produced on either a single or dual panel.

In 8-bit memory interface, if the Address Pitch Adjustment is not equal to zero, a virtual screen with a line
length of (Line Byte Count +AUX[0D]) bytes is created, with the display reflecting the contents of a win­dow (Line Byte Count+1) bytes wide. The position of the window on the virtual screen is determined by
AUX[06] and [07], and AUX[08] and [09].

In 16-bit memory interface, if the Address Pitch Adjustment is not equal to zero, then a virtual screen with
a line length of 2x(Line Byte Count +AUX[0D]) bytes is created, with the display reflecting the contents
of a window 2x(Line Byte Coun t+1) byt es wide. The pos ition of the wind ow on the virtual screen is deter­mined by AUX[06] and [07], and AUX[08] and [09].

Addr Pitch
Adjustment
Bit 5

Addr Pitch
Adjustment
Bit 4

Addr Pitch
Adjustment
Bit 3

Addr Pitch
Adjustment
Bit 2

Addr Pitch
Adjustment
Bit 1

Addr Pitch
Adjustment
Bit 0

Hardware Functional Specification S1D13503
Issue Date: 01/01/29 X18A-A-001-08

Page 70 Epson Resear ch and Development

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.

AUX[0E] Look-Up Table Address Register

I/O address = 1110b, Read/Write

Green Bank
Bit 1

The S1D13503 has three internal 16 position, 4-bit wide Look-Up Tables (palettes). The 4-bit value programmed into each
table position determines the output gray shade / color weighting of display data. These tables are bypa ssed in black-and­white (BW) display mode.

These three 16 position Look-Up Tables can be arranged in many different configurations to accommodate all the gray
shade / color display modes.

Refer to Look-Up Table Architecture on page 72 for formats.

bits 7-6 Green Bank Bits [1:0]

bits 5-4 ID Bit / RGB Index Bits [1:0]

Green Bank
Bit 0

In 4-level gray / color display modes (2-bits/pixel), the 16 position Green palette is arranged into four, 4
position “banks”. These two bits control which bank is currently selected. These bits have no effect in 16­level gray / color display modes (4-bits/pixel).

In 256 color display modes (8-bit/pixel), the 16 position Green palette is arranged into two, 8 positio n
“banks” for the display of “green” colors. Only bit 0 of these two bits controls which bank is currently
selected.

These bits have dual purpose;

ID Bit /
RGB Index
Bit 1

ID Bit /
RGB Index
Bit 0

Palette
Address
Bit 3

Palette
Address
Bit 2

Palette
Address
Bit 1

Palette
Address
Bit 0

ID Bits: After power on or hardware reset, these bits can be read to identify the S1D13503. These same
bits are used to identify the pin compatible S1D13502 and would only be used in system implementations
where common software is being used. As these bits are R/W they must be read before being written in
order to be used as ID bits.

Table 8-6: ID Bit Usage

Chip

S1D13503 0 0

Power On or

RESET

RGB Index bits [1:0]: These bits are also used to provide access to the three internal Look-Up Tables
(RGB).

Table 8-7: Look-Up Table Access

Aux[0E]

bit 5 bit 4

0 0 Auto-increment (see Note 1)
0 1 Red palette R/W access
1 0 Green palette R/W access
1 1 Blue palette R/W access

F352 0 1
S1D13502 1 0
S1D13502 1 1

Look-Up Table Access

bit 5 bit 4

Aux[0E]

S1D13503 Hardware Functional Specification
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Note

When auto-increment is selected, an internal pointer will default to the Red palette on
power on reset. Each read/write access to Aux[0F] will increment the counter to point
to the next palette in order (RGB). Whenever the Look-Up Table Address register
Aux[0E] is written, the RGB Index will reset the pointer to the Red palette. This pro ­vides a efficient method for sequential writing of RG B data.

bits 3-0 Palette Address Bits [3:0 ]

These 4 bits provide a pointer into the 16 position Look-Up Table currently selected for CPU R/W access.

Note

The Look-Up Table configuration (e.g. 1/2/4 banks) does not affect the R/W access
from the CPU as all 16 positions can be accessed sequentially.

AUX[0F] Look-Up Table Data Register

I/O address = 1111b, Read/Write.
Red Bank

Bit 1

Red Bank
Bit 0

Blue Bank
Bit 1

Blue Bank
Bit 0

Palette Data
Bit 3

Palette Data
Bit 2

Palette Data
Bit 1

Palette Data
Bit 0

bit 7-6 Red Bank Bits [1:0]

In 4-level col or display modes , the 16 positio n Red palette is arran ged into four, 4 position “banks”. These
two bits control which bank is currently selected.
In 256 color display modes, the 16 position, Red palette is arranged into two, 8 position “banks” for the
display of “red” colors. Only bit 0 of these two bits controls which bank is currently selected.
These bits have no effect in all gray shade or 16-color display modes.

bit 5-4 Blue Bank Bits [1:0]

In both the 4 and 256 color display modes, the 16 position Blue palette is arranged into f our 4 position
“banks” for the display of “blue” colors. These two bits control which bank is currently selected.
These bits have no effect in all gray shade display modes or 16 color display modes.

bits 3-0 Palette Data Bits [3:0]

These 4-bits are the gray shade / color values used for display data output. They are programmed into the
4-bit Look-Up Table (palettes) positions pointed to by Palette Address bits [3:0] and RGB Index bit[1:0]
(if in color display modes).

For example; in a 16-level gray shade d isp lay mode, a data value of 0001b (4-bits / pixel) will point to
Look-Up Table position one and display the 4-bit gray shade corresponding to the value programmed into
that location.

Hardware Functional Specification S1D13503
Issue Date: 01/01/29 X18A-A-001-08

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8.2 Look-Up Table Architecture

Table 8-8: Look-Up Table Configurations

Display Mode 4-bit wide Palette

RED GREEN BLUE

Black & White

4-level gray 4 banks of 4

16-level gray 1 bank of 16

4 color 4 banks of 4 4 banks of 4 4 banks of 4

16 color 1 bank of 16 1 bank of 16 1 bank of 16

256 color 2 banks of 8 2 banks of 8 4 banks of 4

Indicates the palette is not used for that display mode

8.2.1 Gray Shade Display Modes

4-Level Gray Shade Mode

Green Look- U p Table

Bank 0

2-bit pixel data

0
1
2
3

Bank 1

0
1
2
3

0
1
2
3

Bank 2

Bank
Select
Logic

4-bit display data output

Bank 3

0
1
2
3

Bank Select bits [1:0]

(Aux[0E] bits [7:6])

Note: the above depiction is intended to show the display data output path only. The CPU R/W access to the individual
Look-Up Tables is not affected by the various ‘banking’ configurations.

Figure 37: 4-Level Gray-Shade Mode Look-Up Table Architecture

S1D13503 Hardware Functional Specification
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16-Level Gray Shade Mode

Green Look-Up Table 16x4

0
1
2

4-bit pixel data

3

4-bit Look-Up Table data output

( P3, P2, P1, P0 )

msb lsb

C
D
E
F

Figure 38: 16-Level Gray-Shade Mode Look-Up Table Architecture

Note

The Look-Up Table is bypassed in black-and-white display mode

Hardware Functional Specification S1D13503
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8.2.2 Color Display Modes

4-Level Color Mode

RED Look-Up Table

Bank 0

2-bit pixel data

Red Bank Select bits [1:0]

(Aux[0F] bits [7:6])

Green Bank Select bits [1:0]

(Aux[0E] bits [7:6])

0
1
2
3

Bank 1

0
1
2
3

Bank 2

0
1
2
3

Bank 3

0
1
2
3

GREEN Look-Up Table

Bank 0

0
1
2
3

Bank 1

0
1
2
3

Bank 2

0
1
2
3

Bank 3

0
1
2
3

Bank
Select
Logic

Bank
Select
Logic

4-bit ‘RED’
display dat a output

4-bit ‘GREEN’
display dat a output

Blue Look-U p Table

Bank 0

0
1
2
3

Bank 1

0
1
2
3

0
1
2
3

Bank 2

Bank
Select
Logic

4-bit ‘BLUE’
display dat a output

Bank 3

0
1
2

Blue Bank Select bits [1:0]

3

(Aux[0F] bits [5:4])

Figure 39: 4-Level Color Mode Look-Up Table Architecture

S1D13503 Hardware Functional Specification
X18A-A-001-08 Issue Date : 01/01/29

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16-Level Color Mode

Red Look-Up Table 16x4

0
1
2

4-bit pixel data

3

C
D
E
F

4-bit ‘RED’ Look-Up Table data output

Green Look-Up Table 16x4

0
1
2
3

C
D
E
F

4-bit ‘GREEN’ Look-Up Table data output

Blue Look-Up Table 16x4

0
1
2
3

4-bit ‘BLUE’ Look-Up Table data output

C
D
E
F

Figure 40: 16-Level Color Mode Look-Up Table Architecture

Hardware Functional Specification S1D13503
Issue Date: 01/01/29 X18A-A-001-08

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256-Level Color Mode

256 Color Data Format:

76543210

R2R1R0G2G1G0B1B

0

3-bit pixel data
(R2, R1, R0)

Red Bank Select bit

(Aux[0F] bit 6)

3-bit pixel data
(G2, G1, G0)

Green Bank Select bit

(Aux[0E] bit 6)

Red Look-Up Table

Bank 0

0
1
2
3
4
5
6
7

Bank 1

0
1
2
3
4
5
6
7

Green Look-Up Table

Bank 0

0
1
2
3
4
5
6
7

Bank 1

0
1
2
3
4
5
6
7

Bank
Select
Logic

Bank
Select
Logic

4-bit ‘RED’
display dat a output

4-bit ‘GREEN’
display data output

Blue Look-Up Table
2-bit pixel data
(B1, B0)

0
1
2
3

Bank 0

Bank 1

0
1
2
3

0
1
2
3

Bank 2

Bank
Select
Logic

4-bit ‘BLUE’
display data output

Bank 3

0
1
2
3

Blue Bank Select bits [1:0]

(Aux[0F] bits [5:4])

Figure 41: 256-Level Color Mode Look-Up Table Architecture

S1D13503 Hardware Functional Specification
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8.3 Power Save Modes

Two software-controlled Power Save Modes have been incorporated into the S1D13503 to accommodate the important
need for power reduction in the hand-h eld devices market. Thes e modes can be enabled by setting the two Power Save bits
(AUX[03] bits 7:6).

The various settings are:

Table 8-9: Power Save Mode Selection

Bit 5 Bit 4 Mod e Activated

0 0 Normal Operation
0 1 Power Save Mode 1
1 0 Power Save Mode 2
11 Reserved

8.3.1 Power Save Mode 1

Power Save Mode 1 has two states. Initially when set, the S1D13503 enters State 1. If no valid memory cycle is detected
within 1, 2, or 4 clocks (input clock frequency dependent), the chip will enter State 2. The number of clocks of inactivity
before entering State 2 is dependent on the display memory interface and the number of Gray shades.

State 1

• I/O read/write of all registers allowed

• Memory read/write allowed

• LCD outputs are either forced low (AUX[03] bit 5=0), or high impedance (AUX[03] bit 5=1)

State 2

The same as State 1 as well as:

• Master clock for display memory access is disabled
Once a valid memory read/write cycle is detected, the S1D13503 returns to State 1 where the MPU access is serviced. The

transition from going from State 2 to State 1 requires 1, 2, or 4 clocks (as described above).

8.3.2 Power Save Mode 2

• I/O read/write of all registers allowed

• Memory read/write is disabled

• Master clock for display memory access is disabled

• LCD outputs are either forced low (AUX[03] bit 5=0), or high impedance (AUX[03] bit 5=1)

• Internal oscillator is disabled.

Hardware Functional Specification S1D13503
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8.3.3 P ower Save Mode Function Summary

Table 8-10: Power Save Mode Function Summary

Power Save Mode (PSM)

Function

Display Active? Yes No No No

I/O Access Possible? Yes Yes Yes Yes

Memory Access Possible? Yes Yes No No

Sequence Controller Running? Yes No No No

Internal Oscillator Disabled? No No No Yes

Normal
(Active)

PSM1 PSM2

State 1 State 2

8.3.4 Pin States in Power Save Modes

Table 8-11: Pin States in Power Save Modes

Pin State

Pin

UD[3:0], LD[3:0],

LP, XSCL, YD,

WF/XSCL2

(Note 1)

UD[3:0], LD[3:0],

LP, XSCL, YD,

WF/XSCL2

(Note 2)

AB[19:0], DB[15:0] Active Active Active Active

IOR#, IOW# Active Active Active Active

MEMR#, MEMW# Active Active Active Active

RESET Active Active Active Active

Normal

(Active)

Active

Active Forced Low For ced Low Forced Low

Impedance

PSM1 PSM2

State 1 State 2

High

High

Impedance

High

Impedance

Note

1. Internal Register AUX[03], bit 5 = 1

2. Internal Register AUX[03], bit 5 = 0

S1D13503 Hardware Functional Specification
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9 DISPLAY MEMO RY INTERFACE

9.1 SRAM Configurations Supported

9.1.1 8-Bit Mode

VD0-7
VWE#

WE#

S1D13503

8Kx8

CS#

VCS0#
VCS1#

VA0 -1 2

n/c

Figure 42: 8-Bit Mode - 8K bytes SRAM

VD0-7
VWE#

WE#

S1D13503

VCS0#
VCS1#

VA0 -1 2

8Kx8

CS#

WE#

8Kx8

CS#

Figure 43: 8-Bit Mode - 16K bytes SRAM

(Requires AUX[01] bit 0 = 0)

Hardware Functional Specification S1D13503
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VD0-7
VWE#

WE#

S1D13503

32Kx8

CS#

VCS0#
VCS1#

VA0 -1 4

n/c

Figure 44: 8-Bit Mode - 32K bytes SRAM

(Requires AUX[01] bit 0 = 1)

VD0-7
VWE#

WE#

S1D13503

VCS0#
VCS1#

VA0 -1 4

8K/32Kx8

CS#

WE#

32K/8Kx8

CS#

[either (8Kx8 + 32Kx8) requiring AUX[01] bit 0 = 0 or (32Kx8 + 8Kx8) requiring AUX[01] bit 0 = 1]

Figure 45: 8-Bit Mode - 40K bytes SRAM

S1D13503 Hardware Functional Specification
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VD0-7
VWE#

9.1.2 16-bit Mode

WE#

S1D13503

VCS0#
VCS1#

VA0 -1 4

32Kx8

CS#

Figure 46: 8-Bit Mode - 64K bytes SRAM

(Requires AUX[01] bit 0 = 1)

VD0-7
VWE#

S1D13503

WE#

32Kx8

CS#

WE#

8Kx8

CS#

VCS0#

VA0 -1 2

VCS1#

CS#

WE#

VD8-15

Figure 47: 16-Bit Mode - 16K bytes SRAM

8Kx8

Hardware Functional Specification S1D13503
Issue Date: 01/01/29 X18A-A-001-08

Page 82 Epson Resear ch and Development

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VD0-7
VWE#

WE#

S1D13503

VCS0#

VA0 -1 4

VCS1#

32Kx8

CS#

CS#

32Kx8

WE#

VD8-15

Figure 48: 16-Bit Mode - 64K bytes SRAM

VWE#

S1D13503

VCS0#

VCS1#

VA0-15

VD0-7

VD8-15

Figure 49: 16-Bit Mode - 128K bytes SRAM

WE#

LB#

UB#

A0-15

I/O 1-8

I/O 9-16

S1D13503 Hardware Functional Specification
X18A-A-001-08 Issue Date : 01/01/29

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9.2 SRAM Access Time

9.2.1 8-bit Display Memory Interface:

Table 9-1: 8-Bit Display Memory Interface SRAM Access Time

Display Mode 3V/3.3V 5V

16-level gray shades / 16-level colors Access time <

4-level gray shades / 4-level colors Access time < 2 / f

Black-and-White (BW) Access time <

1 / f

2 / f

- 40ns Access time < 1 / f

OSC

- 40ns Access time < 2 / f

OSC

- 40ns Access time < 2 / f

OSC

OSC
OSC
OSC

- 25ns

- 25ns

- 25ns

9.2.2 16-bit Display Memory Interface:

Table 9-2: 16-Bit Display Memory Interface SRAM Access Time

Display Mode 3V/3.3V 5V

256-level colors Access time <

16-level gray shades / 16-level colors Access time <

4-level gray shades / 4-level colors Access time <

Black-and-White (BW) Access time <

1 / f
2 / f
4 / f
4 / f

- 40ns Access time < 1 / f

OSC

- 40ns Access time < 2 / f

OSC

- 40ns Access time < 4 / f

OSC

- 40ns Access time < 4 / f

OSC

OSC
OSC
OSC
OSC

- 25ns

- 25ns

- 25ns

- 25ns

Hardware Functional Specification S1D13503
Issue Date: 01/01/29 X18A-A-001-08

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9.3 Frame Rate Ca lculation

9.3.1 For single panel

Black-and-White (BW) Display Mode:

×

f

2

FrameRate

--------------------------------------------------------------------------------------------------------------------------------------------------------------------=

()

Horizontal Pixels P HNDP D HNDP

++

osc

()×

VerticalLines

4+

All Other Display Modes:

f

FrameRate

--------------------------------------------------------------------------------------------------------------------------------------------------------------------=

()

Horizontal Pixels P HNDP D HNDP

++

osc

()×

VerticalLines

4+

9.3.2 For dual panel

Black-and-White (BW) Display Mode:

×

f

2

FrameRate

All Other Display Modes:

------------------------------------------------------------------------------------------------------------------------------------------------------------------------------=

()

HorizontalPixels PHNDP DHNDP

++

osc

VerticalLines



×

×

2

------------------------------------ 2+



2

f

FrameRate

------------------------------------------------------------------------------------------------------------------------------------------------------------------------------=

()

HorizontalPixels PHNDP DHNDP

++

osc

VerticalLines



×

×

------------------------------------ 2+

2



Where DHNDP is Default Horizontal Non-Display Period in term of pixels :

DHNDP = 16 pixels per panel in gray shade display modes, and
DHNDP = 32 pixels per panel in BW display mode and in color display modes.

Where PHNDP is Programmable Horizontal Non-Display Period in term of pixels :

PHNDP = 0 pixels when AUX[0C] = 0, and

[]

()

PHNDP = pixels when AUX[0C] not equal to zero.

AUX0C

---------------------------------------------------------------------------------------------------------------- -

()×

MemoryInterfaceWidth

1+

()

BitsPerPixel

2

S1D13503 Hardware Functional Specification
X18A-A-001-08 Issue Date : 01/01/29

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9.4 Memory Size Calculation

Memory Size (bytes) =

()

HorizontalPixels

------------------------------------------------------------------------------------------------------------------------------------------------

()

VerticalLines

8

()××

BitsPerPixel

Example : For a 640x480, 4 gray shades (2 bits-per-pixel) system :

Memory Size (bytes) =

()

------------------------------------------------ 76800

640

()2()××

480
8

==

bytes

75

Kbyte

9.5 Memo ry Size Requirement

The following tables summarize the preceding information (formulae).
Input clock (f

being used. As a result, different resolutions will have different input clock and memory requirements for a particular frame
rate. Tables 9-3 through 9-5 summ arize the minimum memo ry size and access time requirements for variou s resolutions at
a particular input clock along with the corresponding frame rates.

Display

Mode

Condition AUX[0C] = AUX[02] AUX[0C] = 0 AUX[0C] = 0 AUX[0C] = 0 Example

Display

Memory

Interface

8-bit

480

16-bit

8-bit

400

16-bit

8-bit

320

16-bit

8-bit

256

16-bit

8-bit

240

200

16-bit

8-bit

16-bit

Number of Vertical Lines

) is limited by SRAM access time depending on the display mode and display memory interface that is

OSC

Table 9-3: Memory Size Requirement: Number of Horizontal Pixels = 640

Number of Horizontal Pixels = 640

Black-and-White

(BW)

(1 bit-per-pixel)

Size Access Time Size Access Time Size Access Time Size Access Time

(KB) 3V/3.3V 5V (KB) 3V/3.3V 5V (KB) 3V/3.3V 5V (KB) 3V/3.3V 5V

37.5

32

25

20

19

16

40 ns

125 ns

60 ns

160 ns

85 ns

210 ns
125 ns

290 ns
125 ns

290 ns
160 ns

360 ns

55 ns

140 ns

75 ns

175 ns
100 ns

225 ns
140 ns

305 ns
140 ns

305 ns
175 ns

375 ns

4 Grays / 4 Colors

(2 bits-per-pixel)

(2)

75

62.5

50

40

37.5

32

125 ns

160 ns

210 ns
125 ns

290 ns
125 ns

290 ns
160 ns

360 ns

60 ns

85 ns

140 ns

75 ns

175 ns
100 ns

225 ns
140 ns

305 ns
140 ns

305 ns
175 ns

375 ns

16 Grays / 16 Colors

(4 bits-per-pixel)

(2)

150 (1) (1) 300 (1) (1) 24 MHz 76 Hz 74 Hz

125

100

80

75

62.5

(2)

60 ns

(2)

85 ns

(2)

125 ns

(2)

125 ns

60 ns

160 ns

(2)

75 ns

(2)

100 ns

(2)

140 ns

(2)

140 ns

75 ns

175 ns

256 Colors

(8 bits-per-pixel)

Input
Clock
(f

)

OSC

250 (1) (1) 20 MHz 7 5 Hz 74 Hz

200 (1) (1) 16 MHz 7 5 Hz 73 Hz

160 (1) (1) 12 MHz 7 0 Hz 69 Hz

150 (1) (1) 12 MHz 7 5 Hz 73 Hz

125

(2)(3)
60 ns

(2)(3)

10 MHz 75 Hz 73 Hz

75 ns

Frame Rate

BW /

Color

Gray

(1) Memory more than 128KB cannot be supported by S1D13503.
(2) Memory more than 64KB can only be supported through 16-bit display memory interface.
(3) 256 color mode must use 16-bit display memory interface.
* KB = K byte = 1024 bytes

Hardware Functional Specification S1D13503
Issue Date: 01/01/29 X18A-A-001-08

Page 86 Epson Resear ch and Development

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Table 9-4: Memory Size Requirement: Number of Horizontal Pixels = 480

Number of Horizontal Pixels = 480

Display

Mode

Condition AUX[0C] = AUX[02] AUX[0C] = 0 AUX[0C] = 0 AUX[0C] = 0 Example

Display

Memory

Interface

8-bit

480

16-bit

8-bit

400

16-bit

8-bit

320

16-bit

8-bit

256

16-bit

8-bit

240

200

16-bit

8-bit

16-bit

Number of Vertical LinesNumber of Vertical Lines

Black-and-White

(BW)

(1 bit-per-pixel)

Size Access Time Size Access Time Size Access Time Size Access Time

(KB) 3V/3.3V 5V (KB) 3V/3.3V 5V (KB) 3V/3.3V 5V (KB) 3V/3.3V 5V

29

23.5

19

15

14.5

12

70 ns

180 ns
100 ns

240 ns
125 ns

290 ns
160 ns

360 ns
210 ns

460 ns
210 ns

460 ns

85 ns

195 ns
115 ns

255 ns
140 ns

305 ns
175 ns

375 ns
225 ns

475 ns
225 ns

475 ns

4 Grays / 4 Colors

(2 bits-per-pixel)

70 ns

57

47

37.5

30

29

23.5

180 ns
100 ns

240 ns
125 ns

290 ns
160 ns

360 ns
210 ns

460 ns
210 ns

460 ns

195 ns
115 ns

255 ns
140 ns

305 ns
175 ns

375 ns
225 ns

475 ns
225 ns

475 ns

16 Grays / 16 Colors

(4 bits-per-pixel)

85 ns

113

94

75

60

57

47

(2)

70 ns

(2)

100 ns

(2)

125 ns

60 ns

160 ns

85 ns

210 ns

85 ns

210 ns

(2)

85 ns

(2)

115 ns

(2)

140 ns

75 ns

175 ns
100 ns

225 ns
100 ns

225 ns

256 Colors

(8 bits-per-pixel)

OSC

Frame Rate

BW /

)

Gray

Color

Input
Clock

(f

225 (1) (1 ) 18 MHz 75 Hz 73 Hz

188 (1) (1 ) 14 MHz 70 Hz 68 Hz

150 (1) (1 ) 12 MHz 75 Hz 72 Hz

120

113

94

(2)(3)
60 ns

(2)(3)
85 ns

(2)(3)
85 ns

(2)(3)

10 MHz 77 Hz 75 Hz

75 ns

(2)(3)

8 MHz 66 Hz 64 Hz

100 ns

(2)(3)

8 MHz 79 Hz 77 Hz

100 ns

Table 9-5: Memory Size Requirement: Number of Horizontal Pixels = 320

Number of Horizontal Pixels = 320

Display

Mode

Condition AUX[0C] = AUX[02] AUX[0C] = 0 AUX[0C] = 0 AUX[0C] = 0 Example

Display

Memory

Interface

8-bit

480

16-bit

8-bit

400

16-bit

8-bit

320

16-bit

8-bit

256

16-bit

8-bit

240

16-bit

8-bit

200

16-bit

Black-and-White

(BW)

(1 bit-per-pixel)

Size Access Time Size Access Time Size Access Time Size Access Time

(KB) 3V/3.3V 5V (KB) 3V/3.3V 5V (KB) 3V/3.3V 5V (KB) 3V/3.3V 5V

19

16

12.5

10

9.5

8

125 ns
290 ns

160 ns
360 ns

210 ns
460 ns

290 ns
625 ns

290 ns
625 ns

360 ns
760 ns

140 ns
305 ns

175 ns
375 ns

225 ns
475 ns

305 ns
640 ns

305 ns
640 ns

375 ns
775 ns

4 Grays / 4 Colors

(2 bits-per-pixel)

37.5

32

25

20

19

16

125 ns
290 ns

160 ns
360 ns

210 ns
460 ns

290 ns
625 ns

290 ns
625 ns

360 ns
760 ns

140 ns
305 ns

175 ns
375 ns

225 ns
475 ns

305 ns
635 ns

305 ns
640 ns

375 ns
775 ns

16 Grays / 16 Colors

(4 bits-per-pixel)

75

62.5

50

40

37.5

32

(2)

125 ns

60 ns

160 ns

85 ns

210 ns
125 ns

290 ns
125 ns

290 ns
160 ns

360 ns

(2)

140 ns

75 ns

175 ns
100 ns

225 ns
140 ns

305 ns
140 ns

305 ns
175 ns

375 ns

256 Colors

(8 bits-per-pixel)

150 (1) (1 ) 12 MHz 74 Hz 70 Hz

(2)(3)

125

60 ns
(2)(3)

100

85 ns
(2)(3)

80

125 ns

(2)(3)

75

125 ns

(2)(3)

62.5
160 ns

(1) Memory more than 128KB cannot be supported by S1D13503.
(2) Memory more than 64KB can only be supported through 16-bit display memory interface.
(3) 256 color mode must use 16-bit display memory interface.
* KB = K byte = 1024 bytes

Input
Clock

(f

)

OSC

(2)(3)

10 MHz 74 Hz 70 Hz

75 ns

(2)(3)

8 MHz 73 Hz 70 Hz

100 ns

(2)(3)

6 MHz 69 Hz 66 Hz

140 ns

(2)(3)

6 MHz 73 Hz 70 Hz

140 ns

(2)(3)

5 MHz 73 Hz 70 Hz

175 ns

Frame Rate

BW /
Gray

Color

S1D13503 Hardware Functional Specification
X18A-A-001-08 Issue Date : 01/01/29

Epson Research and Development Page 87

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10 MECHANICAL DATA

QFP5-100PIN-S2
(S1D13503)

± 0.04

23.2

± 0.1

20.0
5180

81

100

130

± 0.1

± 0.05

2.7

0.15

All dimensions in mm

Index

0.65

± 0.1

0.30

± 0.1

1.6

50

31

0.8

± 0.1

± 0.1

14.0

± 0.04

17.2

0~12°

Figure 50: Mechanical Drawing QFP5-100-S2 (S1D13503F00A)

Hardware Functional Specification S1D13503
Issue Date: 01/01/29 X18A-A-001-08

Page 88 Epson Resear ch and Development

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QFP15-100PIN-STD
(S1D13503)

± 0.4

16.0

± 0.1

75 51

14.0

76

Index

100

125

± 0.1

± 0.1

1.4

0.125

All dimensions in mm

0.168

± 0.1

0.5

0.5

± 0.2

1

50

26

± 0.1

± 0.4

16.0

14.0

0~12°

Figure 51: Mechanical Drawing QFP15-100-STD (S1D13503F01A)

S1D13503 Hardware Functional Specification
X18A-A-001-08 Issue Date : 01/01/29

S1D13503 Dot Matrix Graphics LCD Controller

Programming Notes and Examples

Document Number: X18A-G-002-06

Copyright © 1996, 2001 Epson Research and Development, Inc. All Rights Reserved.

Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

Page 2

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THIS PAGE LEFT BLANK

S1D13503 Programming N otes and Examples
X18A-G-002-06 Issue Date : 01/01/30

Epson Research and Development

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TABLE OF CONTENTS

1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 INITIALIZING THE S1D13503 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3 GRAY SHADES / COLORS AND LOOK-UP TABLES . . . . . . . . . . . . . . . 18

3.1 Pixels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.1.1 Memory Organization for One Bit Pixel (Black-and-White) . . . . . . . . . . . . . . . 18

3.1.2 Memory Organization for Two Bit Pixels (4 Colors/Gray Shades) . . . . . . . . . . . . 18

3.1.3 Memory Organization for Four Bit Pixels (16 Colors/Gray Shades) . . . . . . . . . . . 19

3.1.4 Memory Organization for Eight Bit Pixels (256 Colors) . . . . . . . . . . . . . . . . . 19

3.2 Look-Up Table (LUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2.1 LUT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2.2 Look-Up Table Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.2.3 Black-and-White (One Bit/Pixel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.2.4 Four Gray Shades (Two Bits/Pixel in Monochrome Mode) . . . . . . . . . . . . . . . . 26

3.2.5 Four Colors (Two Bits/Pixel in Color Mode) . . . . . . . . . . . . . . . . . . . . . . . 28

3.2.6 Sixteen Gray Shades (Four Bits/Pixel in Monochrome Mode) . . . . . . . . . . . . . . 30

3.2.7 Sixteen Colors (Four Bits/Pixel in Color Mode) . . . . . . . . . . . . . . . . . . . . . 31

3.2.8 256 Colors (Eight Bits/Pixel in Color Mode) . . . . . . . . . . . . . . . . . . . . . . . 32

Page 3

4 DISPLAY MEMORY MODELS . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.2.1 S5U13503B00C Evaluation Board Display Memory . . . . . . . . . . . . . . . . . . . 36

4.2.2 Display Start Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.3 Common Display Memory Requirements for LCD Panel Sizes: . . . . . . . . . . . . . 38

5 ADVANCED TECHNIQUES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.1 Virtual Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.1.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.2 Bitmaps and Text Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.3 Mapping of Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.3.1 Indexed Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.3.2 Direct Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5.4 Split Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.4.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.4.2 Single Panel LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

5.4.3 Dual Panel LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5.5 Panning and Scrolling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

5.5.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

5.5.2 Panning Right and Left . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

5.5.3 Scrolling Up and Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Programming Notes and Examples S1D13503
Issue Date: 01/01/30 X18A-G-002-06

Page 4

5.6 Power Saving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.6.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.6.2 Power Save Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

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6 IDENTIFYING THE S1D13503 . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

7 PROGRAMMING THE S1D13503 . . . . . . . . . . . . . . . . . . . . . . . . . . .57

7.1 Main Loop Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

7.2 Initialization Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

7.3 Advanced Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

8 GLOSSARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

S1D13503 Programming N otes and Examples
X18A-G-002-06 Issue Date : 01/01/30