Epson RX-8581NB, RX-8581JE, RX-8581SA User Manual

MQ372-02

Application Manua

Real Time Clock Module

-8581SA/JE/NB

Model Product Number RX-8581SA Q4185815xxxxx00

RX-8581JE Q4185817xxxxx00 RX-8581NB Q4185819xxxxx00

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RX - 8581 SA

/ JE /

Contents

1. Overview

2. Block Diagram

3. Terminal description

3.1. Terminal connections

3.2. Pin Functions

4. Absolute Maximum Ratings

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5. Recommended Operating Conditions

6. Frequency Characteristics

7. Electrical Characteristics

7.1. DC characteristics

7.2. AC Characteristics

8. Use Methods

8.1. Overview of Functions

8.2. Description of Registers

8.3. Fixed-cycle Timer Interrupt Function

8.4. Time Update Interrupt Function

8.5. Alarm Interrupt Funct ion

8.6. Reading/Writing Data via the I2C Bus Interface

8.7. Backup and Recovery

8.8. Connection with Typical Microcontroller

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9. External Dimensions / Marking Layout

10. Reference Data

11. Application notes

11.1. Notes on handling

11.2. Notes on packaging

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RX - 8581 SA

/ JE /

I2C-Bus Interface Real-time Clock Module

RX - 8581 SA

• Features built-in 32.768-kHz crystal oscillator, frequency adjusted

• Supports I

C-Bus's high speed mode (400 kHz)

• Alarm interrupt function for day, date, hour, and minute settings

• Fixed-cycle timer interrupt function

• Time update interrupt function

• 32.768-kHz output with OE function

• Auto correction of leap years

(Seconds, minutes)

(FOE and FOUT pins)

(from 2000 to 2099)

• Wide interface voltage range: 1.8 V to 5.5 V

• Wide time-keeping voltage range:1.6 V to 5.5 V

• Low current consumption: 0.45

A /3 V (Typ.)

• Compact package (NB: SON−22 pin PKG) The I

1. Overview

This module is an I2C bus interface-compliant real-time clock which includes a 32.768-kHz crystal oscillator. In addition to providing a calendar (year, month, date, day, hour, minute, second) function and a clock counter function, this module provides an abundance of other functions including an alarm function, fixed-cycle timer function, time update interrupt function, and 32.768-kHz output function. The devices in this module are fabricated via a C-MOS process for low current consumption, which enables long-term battery back-up. All of these many functions are implemented in a thin, compact SON package, which makes it suitable for various kinds of mobile telephones and other small electronic devices.

2. Block Diagram

32.768 kHz

C-Bus is a trademark of PHILIPS ELECTRONICS N.V.

FOUT FOE

/ INT

SCL SDA

OSC

DIVIDER

FOUT

CONTROLLER

INTERRUPT

CONTROLLER

I2C-BUS

INTERFACE

CIRCUIT

CLOCK

and

TIMER

ALARM

CONTROL

SYSTEM

CONTROLLER

CALENDAR

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3. Terminal description

3.1. Terminal connections

RX - 8581 SA

SOP − 14 pin

# 1

# 7

No. Pin terminal No. Pin terminal

1 N.C. 14 FOUT 2 SCL 13 N.C. 3 SDA 12 N.C. 4 N.C. 11 VDD 5 GND 10 FOE 6 N.C. 9 N.C. 7

/ INT

3.2. Pin Functions

8 N.C.

# 14

# 8

RX - 8581 JE

VSOJ − 20 pin

# 1

# 10

No. Pin terminal No. Pin terminal

1 N.C. 20 N.C. 2 N.C. 19 N.C. 3 FOE 18 N.C. 4VDD 17 N.C. 5 FOUT 16 N.C. 6 SCL 15 N.C. 7 SDAT 14 N.C. 8

( V

9 GND 12 N.C.

/ INT

13 N.C.

)

11 N.C.

# 14

# 11

RX - 8581 NB

SON − 22 pin

# 1

# 11

No. Pin terminal No. Pin terminal

1 / INT 22 N.C. 2 GND 21 N.C.

( V 4 N.C. 19 N.C. 5 SDA 18 N.C. 6 SCL 17 N.C. 7 FOUT 16 N.C. 8VDD 15 N.C. 9 FOE 14 N.C.

10 N.C. (13) 11 N.C. (12)

)

20 N.C.

−

# 14

(#12)

Signal

name

I/O Function

SCL I This is the serial clock input pin for I2C Bus communications.

This pin's signal is used for input and output of address, data, and ACK bits,

SDA I/O

synchronized with the serial clock used for I Since the SDA pin is an N-ch open drain pin during output, be sure to connect a suitable

C communications.

pull-up resistance relative to the signal line capacity.

This is the C-MOS output pin with output control provided via the FOE pin.

FOUT O

When FOE = "H" (high level), this pin outputs a 32.768-kHz signal. When output is stopped, the FOUT pin = "L" (low level).

This is an input pin used to control the output mode of the FOUT pin.

FOE I

/INT O

VDD

(VDD)

GND

−

When this pin's level is high, the FOUT pin is in output mode. When it is low, output via the FOUT pin is stopped.

This pins is used to output alarm signals, timer signals, time update signals, and other signals. This pin is an open drain pin.

This pin is connected to a positive power supply. Although this pin has the same potential as V

DD,

it should not be connected externally.

This pin is connected to a ground.

This pin is not connected to the internal IC.

N.C.

Leave N.C. pins open or connect them to GND or V

− (Note) Note with caution that in the RX-8581NB (SON-22 pin), the N.C. pins (pins 14 to

22) are interconnected via the internal frame.

Note: Be sure to connect a bypass capacitor rated at least 0.1 µF between VDD and GND.

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4. Absolute Maximum Ratings

Item Symbol Condition Rating Unit

Supply voltage VDD Between VDD and GND Input voltage (1) V Input voltage (2) V

Output voltage (1) V Output voltage (2) V

Storage temperature T

IN1

FOE pin

IN2

SCL and SDA pins

OUT1

FOUT pin

OUT2

SDA and /INT pins

STG

When stored separately,

without packaging

5. Recommended Operating Conditions

GND−0.3 GND−0.3 GND−0.3

GND−0.3

to +7.0 V

−0.3 to VDD+0.3 V to +8.0 V

to VDD+0.3 V to +8.0 V

to +125

−55

GND = 0 V V

Item Symbol Condition Min. Typ. Max. Unit

Operating supply voltage VDD

Clock supply voltage V

Operating temperature T

−

CLK

OPR

No condensation

−

1.8 3.0 5.5 V

1.6 3.0 5.5 V

−40

+25 +85

6. Frequency Characteristics

Item Symbol Condition Rating Unit

Frequency precision

Frequency/voltage

characteristics

Frequency/temperature

characteristics

Oscillation start time t

Aging fa

(∗1)

Precision gap per month: 1 minutes (excluding offset val ue)

∆ f /f Ta = +25 °C, VDD = 3.0 V

f /V

Top

STA

Ta = +25 °C, VDD = 2.0 V to 5.0 V ± 2 Max. × 10-6 /V Ta = −10 °C to +70 °C,

= 3.0 V ; +25 °C reference Ta = +25 °C, VDD = 3.0 V Ta = +25 °C, VDD = 3.0 V, first year ± 5 Max. × 10−6 /year

5 ± 23.0

+10 / −120 × 10

(∗1)

× 10-6

3 Max. s

7. Electrical Characteristics

7.1. DC characteristics Item Symbol Condition Min. Typ. Max. Unit

Current consumption (1) Current consumption (2)

Current consumption (3)

Current consumption (4)

Current consumption (5)

Current consumption (6)

High-level input voltage

Low-level input voltage

High-level output voltage

Low-level output voltage

Input leakage current Output leakage current

DD1

DD2

DD3

SCL

/INT = V FOUT; output OFF

SCL

/INT, FOE = V

*Unless otherwise specified, GND = 0 V , VDD = 1.8 V to 5.5 V , Ta = −40 °C to +85 °C

= 0 Hz

, FOE = GND

( low level )

V V

FOUT;

32.768 kHz output ON ,

DD4

CL = 0 pF

SCL

DD5

= 0 Hz

/INT, FOE = V

FOUT ;

32.768 kHz output ON ,

DD6

CL = 30 pF

IH1

FOE pin

IH2

SCL and SDA pins

VIL Input pin

OH1

V V V V V V V V

FOUT pin

OH2 OH3 OL1

OL2

FOUT pin

OL3 OL4

/INT pin

OL5 OL6

SDA pin

ILK Input pin, V

IOZ /INT, SDA, FOUT pins, V

VDD=5 V, IOH=−1 mA VDD=3 V, IOH=−1 mA VDD=3 V, IOH=−100 µA

=5 V, IOL=1 mA GND GND+0.5

=3 V, IOL=1 mA GND GND+0.8

VDD=3 V, IOL=100 µA

=5 V, IOL=1 mA GND GND+0.25 VDD=3 V, IOL=1 mA GND GND+0.4 V

≥2 V, IOL=3 mA

= VDD or GND

OUT

= VDD or GND

= 5 V = 3 V

= 5 V

= 3 V

= 5 V

= 3 V

0.7 × V

GND − 0.3

0.65 1.2

0.45 0.8

3.0 7.5

1.7 4.5

8.0 20.0

5.0 12.0 V

+ 0.3 V

6.0 V

0.3 × V

4.5 5.0

2.2 3.0

2.9 3.0

GND GND+0.1

GND GND+0.4 V

−0.5

0.5

GND = 0 V

°C

GND = 0 V

−6

µA

µA µA

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7.2. AC Characteristics

GND = 0 V , V

= 1.8 V to 5.5 V , Ta = −40 °C to +85 °C

* Unless otherwise specified,

Item Symbol Condition Min. Typ. Max. Unit

SCL clock frequency f Start condition setup time t Start condition hold time t Data setup time t Data hold time t Stop condition setup time t Bus idle time between

start condition and stop condition Time when SCL = "L" Time when SCL = "H" Rise time for SCL and SDA tr 0.3 Fall time for SCL and SDA t

Allowable spike time on bus t FOUT duty tW /t

Timing chart

STAR T

Protocol

CONDITION

SU ; STA

(S)

LOW tHIGH

BIT 7

MSB (A7)

SCL

400 kHz

SU;STA HD;STA SU;DAT HD;DAT SU;STO

BUF

LOW

HIGH

0.6

µs µs

100 ns 0 ns

0.6

1.3

0.6

µs µs µs

µs µs

1 / f

SCL

BIT 6

(A6)

50% of V

0.3

µs

50 ns

= 2.4 V ∼ 5.5 V

level

BIT 0

LSB

(R/W)

45 50 55 %

ACK

(A)

STOP

CONDITION

(P)

START

CONDITION

(S)

SU ; ST

SCL

(S)

(P)

BUF

(S)

(A)

HD ; STA

SU ; DAT

HD ; DAT

SU ; STO

HD ; STA

Caution: When accessing this device, all communication from transmitting the start condition to transmitting the stop

condition after access should be completed within 0.95 seconds. If such communication requires 0.95 seconds or longer, the I

C bus interface is reset by the internal bus

timeout function.

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8. Use Methods

8.1. Overview of Functions

1) Clock functions

This function is used to set and read out month, day, hour, date, minute, second, and year (last two digits) data. Any (two-digit) year that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year

2099.

∗ For details, see "8.2. Description of Registers".

2) Fixed-cycle interrupt generation function

The fixed-cycle timer interrupt generation function generates an interrupt event periodically at any fixed cycle set between 244.14 µs and 4095 minutes. When an interrupt event is generated, the /INT pin goes to low level ("L") and "1" is set to the TF bit to report that an event has occurred. (However, when a fixed-cycle timer interrupt event has been generated, low-level output from the /INT pin occurs only when the value of the control register's TIE bit is "1". Up to 7.8 ms after the interrupt occurs, the /INT status is automatically cleared (/INT status changes from low level to Hi-Z).

∗ For details, see "8.3. Fixed-cycle Interrupt Function". .

3) Time update interrupt function

The time update interrupt function generates interrupt events at one-second or one-minute intervals, according to the timing of the internal clock. When an interrupt event occurs, the UF bit value becomes "1" and the /INT pin goes to low level to indicate that an event has occurred. (However, when a fixed-cycle timer interrupt event has been generated, low-level output from the /INT pin occurs only when the value of the control register's UIE bit is "1". This /INT status is automatically cleared (/INT status changes from low level to Hi-Z) 7.8 ms (a fixed value) after the interrupt occurs.

∗ For details, see "8.4. Time Update Interrupt Function".

4) Alarm interrupt function

The alarm interrupt generation function generates interrupt events for alarm settings such as date, day, hour, and minute settings. When an interrupt event occurs, the AF bit value is set to "1" and the /INT pin goes to low level to indicate that an event has occurred.

∗ For details, see "8.5. Alarm Interrupt Function".

5) 32.768-kHz clock output

The 32.768-kHz clock (with precision equal to that of the built-in crystal oscillator) can be output via the FOUT pin. The FOUT pin is a CMOS output pin which can be set for clock output when the FOE pin is at high level and for low-level output when the FOE pin is at low level.

6) Interface with CPU

Data is read and written via the I2C bus interface using two signal lines: SCL (clock) and SDA (data). Since neither SCL nor SDA includes a protective diode on the V supply voltages can still be implemented by adding pull-up resistors to the circuit board. The SCL's maximum clock frequency is 400 kHz (when V

∗ For further description of data read/write operations, see "8.6 Reading/Writing Data via the I2C Bus Interface".

side, a data interface between hosts with differing

DD ≥

1.8 V), which supports the I2C bus's high-speed mode.

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8.2. Description of Registers

8.2.1. Register table

Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

0 SEC 1 MIN 2 HOUR 3 WEEK 4 DAY 5 MONTH 6 YEAR 80 40 20 10 8 4 2 1 7 RAM 8 MIN Alarm AE 40 20 10 8 4 2 1 9 HOUR Alarm AE

WEEK Alarm 6 5 4 3 2 1 0

DAY Alarm B Timer Counter 0 128 64 32 16 8 4 2 1 C Timer Counter 1 D Extension Register TEST WADA USEL TE E Flag Register F Control Register

Note

When after the initial power-up or when the result of read out the VLF bit is "1" , initialize all registers, before using the module. Be sure to avoid entering incorrect date and time data, as clock operations are not guaranteed when the data or time data is incorrect.

∗1) During the initial power-up, the TEST bit is reset to "0" and the VLF bit is set to "1".

∗ At this point, all other register values are undefined, so be sure to perform a reset before using the module.

Only a "0" can be written to the UF, TF, AF, or VLF bit.

∗2)

Any bit marked with "!" should be used with a value of "0" after initialization.

∗3) ∗4) Any bit marked with "•" is a RAM bit that can be used to read or write any data.

The TEST bit is used by the manufacturer for testing. Be sure to set "0" for this bit when writing.

∗5)

40 20 10 8 4 2 1

20 10 8 4 2 1

6 5 4 3 2 1 0

20 10 8 4 2 1

10 8 4 2 1

• • • • • • • •

20 10 8 4 2 1

•

• • • •

20 10 8 4 2 1

•

2048 1024 512 256

UF TF AF

UIE TIE AIE

TSEL1 TSEL0

VLF

STOP RESET

Remark

∗3 ∗3 ∗3 ∗3 ∗3 ∗3

−

∗4

−

∗4 ∗4

−

∗4 ∗1, ∗3, ∗5 ∗1, ∗2, ∗3

∗3

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8.2.2. Control register (Reg F) Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

∗1)

The default value is the value that is read (or is set internally) after powering up from 0 V.

∗2)

"o" indicates write-protected bits. A zero is always read from these bits.

∗3)

"−" indicates no default value has been defined.

• This register is used to control interrupt event output from the /INT pin and the stop/start status of clock and

calendar operations.

1) UIE (Update Interrupt Enable) bit When a time update interrupt event is generated (when the UF bit value changes from "0" to "1"), this bit's value specifies if an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT status remains Hi-Z). When a "1" is written to this bit, an interrupt signal is generated (/INT status changes from Hi-Z to low) when an interrupt event is generated. When a "0" is written to this bit, no interrupt signal is generated when an interrupt event occurs.

Control Register

(Default) (0) (0)

UIE

UIE TIE AIE

(−) (−) (−)

(0)

STOP RESET

(−) (−)

Data Function

Write/Read

∗

For details, see "8.4. Time Update Interrupt Function".

When a time update interrupt event occurs, an interrupt signal is not generated or is canceled (/INT status changes from low to Hi-Z).

When a time update interrupt event occurs, an interrupt signal is generated (/INT status changes from Hi-Z to low). ∗

When a time update interrupt event occurs, low-level output from the /INT pin occurs only when the value of the control register's UIE bit is "1". This /INT status is automatically cleared (/INT status changes from low to Hi-Z) 7.8 ms after the interrupt occurs.

2) TIE (Timer Interrupt Enable) bit When a fixed-cycle timer interrupt event occurs (when the TF bit value changes from "0" to "1"), this bit's value specifies if an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT status remains Hi-Z). When a "1" is written to this bit, an interrupt signal is generated (/INT status changes from Hi-Z to low) when an interrupt event is generated. When a "0" is written to this bit, no interrupt signal is generated when an interrupt event occurs.

TIE

Write/Read

∗

For details, see "8.3. Fixed-cycle Timer Interrupt Function".

Data Function

When a fixed-cycle timer interrupt event occurs, an interrupt signal is not generated or is canceled (/INT status changes from low to Hi-Z).

When a fixed-cycle timer interrupt event occurs, an interrupt signal is generated (/INT status changes from Hi-Z to low).

When a fixed-cycle timer interrupt event has been generated low-level output from the /INT pin

occurs only when the value of the control register's TIE bit is "1". Up to 7.8 ms after the interrupt occurs, the /INT status is automatically cleared (/INT status changes from low to Hi-Z)

3) AIE (Alarm Interrupt Enable) bit When an alarm timer interrupt event occurs (when the AF bit value changes from "0" to "1"), this bit's value specifies if an interrupt signal is generated (/INT status changes from Hi-Z to low) or is not generated (/INT status remains Hi-Z). When a "1" is written to this bit, an interrupt signal is generated (/INT status changes from Hi-Z to low) when an interrupt event is generated. When a "0" is written to this bit, no interrupt signal is generated when an interrupt event occurs.

AIE

Data Function

Write/Read

∗

For details, see "8.5. Alarm Interrupt Function".

[Caution]

(1) The /INT pin is a shared interrupt output pin for three types of interrupts. It outputs the OR'ed result of these interrupt outputs.

(2) To keep the /INT pin from changing to low level, write "0" to the UIE, TIE, and AIE bits. To check whether an event has occurred without

When an interrupt has occurred (when the /INT pin is at low level), the UF, TF, read AF flags to determine which flag has a value of "1" (this indicates which type of interrupt event has occurred).

outputting any interrupts via the /INT pin, use software to monitor the value of the UF, TF, and AF interrupt flags.

When an alarm interrupt event occurs, an interrupt signal is not generated or is canceled (/INT status changes from low to Hi-Z).

When an alarm interrupt event occurs, an interrupt signal is generated (/INT status changes from Hi-Z to low). ∗

When an alarm interrupt event has been generated low-level output from the /INT pin occurs only when the value of the control register's AIE bit is "1". This setting is retained until the AF bit value is cleared to zero. (No automatic cancellation)

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