Epson RTC-72421, RTC-72423 Applications Manual

Real Time Clock Module

Application Manual

MQ162-01

RTC-72421/ 72423

NOTICE

• No part of this material may be reproduced or duplicated in any form or any means without the written
permission of Seiko Epson.

• Seiko Epson reserves the right to make changes to this material without notice.

• Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this
material or due to its application or use in any product or circuit and, further, there is no representation
that this material is applicable to products requiring high level reliability, such as, medical products.

• Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there
is no representation or warranty that anything made in accordance with this material will be free from any
patent or copyright infringement of a third party.

• This material of portions thereof may contain technology or the subject relating to strategic products
under the control of the Foreign Exchange and Foreign Trade Control Law of Japan and may require an
export license from the Ministry of international Trade and industry or other approval from another

government agency.

In pursuit of "Saving" Technology ,Epson electronic device.
Our Lineup of semiconductors, Liquid crystal displays and quartz devices
assists in creating the products of our customers' dreams.

Epson IS energy savings.

CONTENTS

■ Overview---------------------------------------------------------------------------------------------------1

■ Block diagram --------------------------------------------------------------------------------------------2

■ Pin connections ------------------------------------------------------------------------------------------2

■ Pin functions ----------------------------------------------------------------------------------------------3

■ Characteristics--------------------------------------------------------------------------------------------4

1. Absolute maximum ratings ------------------------------------------------------------------------------------------------4

2. Operating conditions--------------------------------------------------------------------------------------------------------4

3. Frequency characteristics and current consumption characteristics -------------------------------------------4

4. Electrical characteristics (DC characteristics) ------------------------------------------------------------------------5

■ Switching characteristics (AC characteristics) ---------------------------------------------------6

1. When ALE is used-----------------------------------------------------------------------------------------------------------6

2. When ALE is fixed at VDD--------------------------------------------------------------------------------------------------8

■ Registers---------------------------------------------------------------------------------------------------9

1. Register table-----------------------------------------------------------------------------------------------------------------9

2. Notes----------------------------------------------------------------------------------------------------------------------------9

3. Functions of register bits (overview) ----------------------------------------------------------------------------------10

4. Setting the fixed-period pulse output mode and fixed-period interrupt mode-------------------------------10

5. Resetting the fixed-period pulse output mode and fixed-period interrupt mode----------------------------10

■ Register description -----------------------------------------------------------------------------------11

1. Timing registers-------------------------------------------------------------------------------------------------------------11
(1) S1 to Y10 registers------------------------------------------------------------------------------------------------------11
(2) W register ----------------------------------------------------------------------------------------------------------------11
(3) H10 register (PM/AM, h20, h10)---------------------------------------------------------------------------------------11
(4) Y1 and Y10 registers ---------------------------------------------------------------------------------------------------11
(5) Out-of-range data ------------------------------------------------------------------------------------------------------11

2. CD register (control register D)-------------------------------------------------------------------------------------------12
(1) HOLD bit (D0) -----------------------------------------------------------------------------------------------------------12
(2) BUSY bit (D1)------------------------------------------------------------------------------------------------------------12
(3) IRQ FLAG bit (D2)------------------------------------------------------------------------------------------------------12
(4) 30-second ADJ bit (D3) -----------------------------------------------------------------------------------------------13

3. CE register (control register E)-------------------------------------------------------------------------------------------13
(1) MASK bit (D0) -----------------------------------------------------------------------------------------------------------13
(2) ITRPT/STND bit (D1) --------------------------------------------------------------------------------------------------14
(3) t0 (D2), t1 (D3) bits ------------------------------------------------------------------------------------------------------14

4. CF register (control register F) ------------------------------------------------------------------------------------------15
(1) RESET bit (D0)----------------------------------------------------------------------------------------------------------15
(2) STOP bit (D1)------------------------------------------------------------------------------------------------------------15
(3) 24/12 bit (D2) ------------------------------------------------------------------------------------------------------------15
(4) TEST bit (D3) ------------------------------------------------------------------------------------------------------------15

CONTENTS

■ Using the RTC-72421/RTC-72423 ----------------------------------------------------------------16

1. Power-on procedure (initialization) ------------------------------------------------------------------------------------16

2. Read/write of S1 to W registers-----------------------------------------------------------------------------------------18

3. Write to 30-second ADJ bit ----------------------------------------------------------------------------------------------18

4. Using the CS1 pin ----------------------------------------------------------------------------------------------------------19
(1) Functions-----------------------------------------------------------------------------------------------------------------19
(2) Timing---------------------------------------------------------------------------------------------------------------------19
(3) Note-----------------------------------------------------------------------------------------------------------------------19

■ Power supply circuit example-----------------------------------------------------------------------19

■ Examples of connection to general-purpose microprocessor ------------------------------20

1. Connection to multiplexed bus type------------------------------------------------------------------------------------20

2. Connection to Z80 or compatible CPU --------------------------------------------------------------------------------20

3. Connection to 68-series MPU--------------------------------------------------------------------------------------------20

■ Reference data -----------------------------------------------------------------------------------------21

1. Frequency temperature characteristics (typical) --------------------------------------------------------------------21

2. Frequency voltage characteristics (typical)---------------------------------------------------------------------------21

3. Current consumption voltage characteristics (typical)-------------------------------------------------------------21

■ External dimensions-----------------------------------------------------------------------------------22

1. RTC-72421 -------------------------------------------------------------------------------------------------------------------22

2. RTC-72423 -------------------------------------------------------------------------------------------------------------------22

■ Marking layout ------------------------------------------------------------------------------------------22

■ Application notes---------------------------------------------------------------------------------------23

1. Notes on handling----------------------------------------------------------------------------------------------------------23
(1) Static electricity ---------------------------------------------------------------------------------------------------------22
(2) Noise ----------------------------------------------------------------------------------------------------------------------22
(3) Voltage levels of input pins ------------------------------------------------------------------------------------------22
(4) Treatment of unused input pins-------------------------------------------------------------------------------------22

2. Notes on mounting---------------------------------------------------------------------------------------------------------23
(1) Soldering temperature conditions----------------------------------------------------------------------------------23
(2) Mounting equipment---------------------------------------------------------------------------------------------------24
(3) Ultrasonic cleaning-----------------------------------------------------------------------------------------------------24
(4) Mounting orientation---------------------------------------------------------------------------------------------------24
(5) Leakage between pins------------------------------------------------------------------------------------------------24

Page-1

4-BIT PARALLEL INTERFACE REAL TIME CLOCK MODULE

RTC-72421/72423

■ Overview

The RTC-72421/RTC-72423 module is a real time clock that can be connected directly to a microprocessor's bus. Its built-in
crystal unit enables highly accurate timekeeping with no physical access required for adjustment and, since there is no need
to connect external components, mounting and other costs can be reduced.
In addition to its time and calendar functions, the RTC-72421/RTC-72423 enables the use of 30-seconds correction and
fixed-period interrupt functions.
The RTC-72421/RTC-72423 module is ideally suited for applications requiring timing management, such as personal
computers, dedicated wordprocessors, fax machines, multi-function telephones, and sequencers.

● Built-in crystal unit removes need for adjustment and reduces installation costs

● Use of C-MOS IC enables low current consumption (5

µA max, at VDD=2.0V)

● Compatibility with Intel CPU bus

● Address latch enable (ALE) pin compatible with multiplex bus CPUs

● Time (hours, minutes, seconds) and calendar (year, month, day) counter

● 24-hour/12-hour switchover and automatic leap-year correction functions

● Fixed-period interrupt function

● 30-seconds correction (adjustment) function

● Stop, start, and reset functions

● Battery back-up function

● Same mounting conditions as general-purpose SMD ICs possible (RTC-72423)

* Pins and functions compatible with the SMC5242 series

Page-2

RTC-72421/72423

■ Block diagram

■ Pin connections

RTC-72421 RTC-72423

The (VDD) pins are at the same electrical level as VDD. Do not connect these pins externally.
The N.C. pins are not connected internally. Ground them in order to prevent noise.

Page-3

D0-D3 11-14 14,15,16,19 Bi-

(Data bus) direction

A0-A3 4-7 5,7,9,10 Input

(Address bus)

ALE 3 4 Input

(Address Latch Enable)

WR 10 13 Input

(WRite)

RD 8 11 Input

(ReaD)

CS1, CS0 15,2 20,2 Input

(Chip Select)

STD.P 1 1 Output

(STanDard Pulse)

VDD 18 24

GND 9 12
(VDD) 16,17 22,23

N.C. - 3,6,8,17,18,21

Connect these pins to a bidirectional data bus or CPU data bus. Use
this bus to read to and write from the internal counter and registers.

Address input pins used for connection to CPU addresses, etc. Used
to select the RTC's internal counter and registers (address selection).
When the RTC is connected to a multiplexed-bus type of CPU, these
pins can also be used in combination with the ALE described below.
Reads in address data and CS0 state for internal latching.
When the ALE is high, the address data and CS0 state is read into
the RTC. When the (through-mode) ALE falls, the address data and

CS0 state at that point are held. The held address data and CS0 status

are maintained while the ALE is low.

If the RTC is connected to a CPU that does not have an ALE pin and
thus there is no need to use this ALE pin, fix it to VDD.
Writes the data on D0 to D3 into the register of the address specified
by A0 to A3, at the leading edge of WR.
Make sure that RD and WR are never low at the same time.
Outputs data to D0 to D3 from the register at the address specified by
A0 to A3, while RD is low.
Make sure that RD and WR are never low at the same time.
When CS1 is high and CS0 is low, the RTC's chip-select function is
valid and read and write are enabled.
When the RTC is connected to a multiplexed-bus type of CPU, CS0
requires the operation of the ALE (see the description of the ALE).
Use CS1 connected to a power voltage detection circuit. When CS1 is
high, the RTC is enabled; when it is low, the RTC is on standby.
When CS1 goes low, the HOLD and RESET bits in the RTC registers
are cleared to 0.
This is an N-channel open drain output pin.
Depending on the setting of the CE register, a fixed-period interrupt
signal and a pulse signal are output.
The output from this pin cannot be inhibited by the CS1and

CS0

signals.
Use a load voltage that is less than or equal to VDD. If not using this
pin, keep it open-circuit.
An example of STD.P connection is shown below.

If the STD.P output is not be used during standby operation,
connecting the pull-up resistor to +5 V provides a reduction in current
consumption. If the STD.P output is to be used even during standby,
connect the pull-up resistor to the RTC's VDD. In this case, the current
consumption will be increased by the amount of current flowing
through the pull-up resistor.
Connect this pin to power source. Supply to 5 V ±10% to this pin
during normal operation; at least 2 V during battery back-up
operation.
Connect this pin to ground.
These pins are connected internally to VDD. Leave them open circuit.
These pins are not connected internally. Ground them.

■ Pin functions

Signal Pin No. Input/ Function

RTC-72421RTC-72423 Output

CS-1 CS0 RD WR Mode of D0 to D3

H L L H Output mode (read mode)
H L H L Input mode (write mode)
H L L L Do not use
L H or L High impedance (back-up mode)
H H H or L High impedance (RTC not selected)

ALE Address data and CS0 status

H Read into the RTC to set address data
L Held in the RTC (latched at the trailing edge of the ALE)

RTC-72421/72423

Page-4

■ Characteristics

1. Absolute maximum ratings

2. Operating conditions

3. Frequency characteristics and current consumption characteristics

metIlobmySnoitidnoCsnoitacificepStinU

ecnarelotycneuqerF

∆ 0f/f

C°52=aT

V

DD

V0.5=

A12427-CTR01±

mpp

B12427-CTR05±
A32427-CTR02±

32427-CTR05±

erutarepmetycneuqerF

scitsiretcarahc

:12427-CTR ; C°52+ot01-

)C°52ecnerefer(

021-/01+

:32427-CTRC°58+ot04-

)C°52ecnerefer(

022-/01+

egatlovycneuqerF

scitsiretcarahc

C°52=aT

V

DD

V5.5ot5.2=

.xam5±V/mpp

gnigAafV

DD

C°52=aT,V0.5=.xam5±raey/mpp

ecnatsiserkcohS.R.S

morfdraobdrahanosemit3fotsetporD

G0003ro,thgiehmc57 × sm2 × enis2/1

evaw × snoitcerid3

.xam01±mpp

noitpmusnoctnerruC

I

DD

1

SC,C°52=aT

1

V0=

dedulcxestnerrucO/I

V

DD

V0.5=.pyt0.1.xam01

µA

I

DD

2V

DD

V0.2=.pyt9.0.xam5

metIlobmySnoitidnoCsnoitacificepStinU

egatlovylppuSV

DD

5.5ot5.4V

erutarepmetgnitarepOT

RPO

12427-CTR07+ot01-

C°

32427-CTR58+ot04-

egatlovdlohataDV

HD

5.5ot0.2V

SC

1

emitdlohatadt

RDC

atadnonoitcesehteeS

)91egap(gnimitdloh

.nim0.2

µs

emityrevocernoitarepOrt

metIlobmySnoitidnoCsnoitacificepStinU

egatlovylppuSV

DD

C°52=aT0.7ot3.0-

VegatlovtupnIV

I

C°52=aTVot3.0-DNG

DD

3.0+

egatlovtuptuOV

O

C°52=aTVot3.0-DNG

DD

3.0+

erutarepmetegarotST

GTS

12427-CTR58+ot55-

C°

32427-CTR521+ot55-

snoitidnocgniredloST

LOS

12427-CTR

01nahteromonrofC°062nahtrehgihoN

sdaelehtnosdnoces

051nahtrehgihon(

°

)egakcapehtnihtiwC

32427-CTR

nahteromonrofeciwtC°062nahtrehgihoN

eromonrofC°032rehgihonro,sdnoces01

setunim3naht

Page-5

4. Electrical characteristics (DC characteristics)

metIlangiSnoitidnoCsnipelbacilppA.NIM.PYT.XAMtinU

1egatlovtupnihgiHV

1HI

SCroftpecxesniptupniIIA

1

2.2
V

1egatlovtupniwoLV

1LI

8.0

2egatlovtupnihgiHV

2HI

V

DD

V5.5ot0.2=SC

1

V5/4

DD

2egatlovtupniwoLV

2LI

V5/1

DD

1tnerrucegakaeltupnII

1KL

VIV=DD0/

V

DroftpecxesniptupnI

0

Dot

3

1-/1

µA

2tnerrucegakaeltupnII

2KL

D0Dot

3

01-/01

1egatlovtuptuowoLV

1LO

I

LO

Am5.2=4.0

V

egatlovtuptuohgiHV

HO

I

HO

004-= µA4.2

2egatlovtuptuowoLV

2LO

I

LO

Am5.2=

P.DTS

4.0

tnerrucegakaeletats-ffOI

KLFFO

VIV=

DD

V0/01-/01

µA

ecnaticapactupnIC

I

ycneuqerftupnI

zHM1

DroftpecxesniptupnI

0

Dot

3

01

Fp

ecnaticapactuptuo-tupnIC

O/I

D0Dot

3

P.DTSdna02

RTC-72421/72423

Page-6

■ Switching characteristics (AC characteristics)

1. When ALE is used

Write mode (VDD=5V±0.5V,RTC-72421:Ta=-10°C to +70°C, RTC-72423:Ta=-40°C to +85°C)

Read mode (V

DD=5V±0.5V,RTC-72421:Ta=-10°C to +70°C, RTC-72423:Ta=-40°C to +85°C)

metIlobmySnoitidnoC.NIM.XAMtinU

SC

1

emitpu-test

US

SC(1)0001

sn

ELAerofebemitpu-tessserddAt

US

)ELA-A(05

ELAretfaemitdlohsserddAt

H

)A-ELA(05

htdiweslupELAt

W

)ELA(08

daererofebemitpu-tesELAt

US

)R-ELA(0

daerretfaemitpu-tesELAt

US

)ELA-R(05

daerretfaemitrefsnarttuptuoataDt

VZP

)Q-R(Fp051=LC021

daerretfaemitrefsnartgnitaolftuptuoataDt

ZVP

)Q-R(007

SC

1

emitdloht

H

SC(1)002

emityrevocerdaeRt

CER

)W(0001

metIlobmySnoitidnoC.NIM.XAMtinU

SC

1

emitpu-test

US

SC(1)0001

sn

ELAerofebemitpu-tessserddAt

US

)ELA-A(05

ELAretfaemitdlohsserddAt

H

)A-ELA(05

htdiweslupELAt

W

)ELA(08

etirwerofebemitpu-tesELAt

US

)W-ELA(0

htdiweslupetirWt

W

)W(021

etirwretfaemitpu-tesELAt

US

)ELA-W(05

etirwerofebemitpu-testupniataDt

US

)W-D(08

etirwretfaemitdlohtupniataDt

H

)D-W(01

SC

1

emitdloht

H

SC(1)0001

emityrevoceretirWt

(CER

)W002

Page-7

(1) Write mode

(2) Read mode

Page-8

RTC-72421/72423

2. When ALE is fixed at VDD

Write mode (VDD=5V±0.5V, RTC-72421:Ta=-10°C to +70°C, RTC-72423:Ta=-40°C to +85°C)

Read mode (V

DD=5V±0.5V, RTC-72421:Ta=-10°C to +70°C, RTC-72423:Ta=-40°C to +85°C)

metIlobmySnoitidnoC.NIM.XAMtinU

SC

1

emitpu-test

US

SC(1)0001

sn

SC

1

emitdloht

H

SC(1)0001

etirwerofebemitpu-tessserddAt

US

)W-A(05

etirwretfaemitdlohsserddAt

H

)A-W(01

htdiweslupetirWt

W

)W(021

etirwerofebemitpu-testupniataDt

US

)W-D(08

etirwretfaemitdlohataDt

H

)D-W(01

emityrevoceretirWt

CER

)W(002

metIlobmySnoitidnoC.NIM.XAMtinU

SC

1

emitpu-test

US

SC(1)0001

sn

SC

1

emitdloht

H

SC(1)0001

etirwerofebemitpu-tessserddAt

US

)W-A(05

etirwretfaemitdlohsserddAt

H

)A-W(01

htdiweslupetirWt

W

)W(021

etirwerofebemitpu-testupniataDt

US

)W-D(08

etirwretfaemitdlohataDt

H

)D-W(01

emityrevoceretirWt

CER

)W(002

(2) Read mode

(1) Write mode

(3) Read/write recovery mode

Page-9

■ Registers

1. Register table

2. Notes

(1) The counts at addresses 0 to C are all positive logic. Therefore, a register bit that is 1 appears as a high-level signal on

the data bus. Data representation is BCD.
(2) Do not set an impossible date or time in the RTC. If such a value is set, the effect is unpredictable.
(3) When the power is turned on (before the RTC is initialized), the state of all bits is undefined. Therefore, write to all

registers after power-on, to set initial values. For details of the initialization procedure, see "Using the RTC-72421/RTC-

72423" on page 16.
(4) The TEST bit of control register F is used by EPSON for testing. Operation cannot be guaranteed if 1 is written to this bit,

so make sure that it is set to 0 during power-on initialization.

sserddA3A2A1A0AretsigeRataDtnuoCskrameR

)xeH(eman3D2D1D0D)DCB(

0 0000 1S8s4s2s1s9~0retsigertigiddnoces-1

1 0001 01S*04s02s01s5~0retsigertigidsdnoces-01
20010 1IM8im4im2im1im9~0retsigertigidetunim-1
30011 01IM* 04im02im01im5~0retsigertigidsetunim-01
40100 1H8h4h2h1h9~0retsigertigidruoh-1
50101 01H* MA/MP02h01h2ro1~0retsigertigidsruoh-01
60110 1D8d4d2d1d9~0retsigertigidyad-1
7 0111 01D**02d01d3~0retsigertigidsyad-01
8 1000 1OM8om4om2om1om9~0retsigertigidhtnom-1
91001 01OM***01om1~0retsigertigidshtnom-01
A10101Y8y4y2y1y9~0retsigertigidraey-1
B1011 01Y08y04y02y01y9~0retsigertigidsraey-01
C1100W * 4w2w1w6~0retsigerkeew-eht-fo-yaD
D1101DCJDAs-03GALFQRIYSUBDLOHDretsigerlortnoC

E 1110 EC1t0t

/TPRTI

DNTS

KSAMEretsigerlortnoC

F 1111 FCTSET21/42POTSTESERFretsigerlortnoC

Page-10

RTC-72421/72423

3. Functions of register bits (overview)

4. Setting the fixed-period pulse output mode and fixed-period interrupt mode

5. Resetting the fixed-period pulse output mode and fixed-period interrupt mode

edoMGALFQRIGALFQRInipP.DTS

edomtuptuoeslupdoirep-dexiF

0=KSAM

0=DNTS/TPRTI

0etirWetirwehtretfayletaidemmiteseR

"1"( → )"0"

etirwehtretfayletaidemmiteseR

wol( → )tiucric-nepo

etirwoNdoireptesehtybdenruteryllacitamotuA

"1"( → )"0"

doireptesehtybdenruteryllacitamotuA

wol( → )tiucric-nepo

edomtpurretnidoirep-dexiF

0=KSAM

1=DNTS/TPRTI

0etirWetirwehtretfayletaidemmiteseR

"1"( → )"0"

etirwehtretfayletaidemmiteseR

wol( → )tiucric-nepo

etirwoN .derongierastpurretnitneuqesbuS.teseronhtiw,seunitnoctseuqertpurretniehT

edoMKSAMDNTS/TPRTIDNTS/TPRTInipP.DTSgnimittuptuodoirep-dexiffognitteS

edomtuptuoeslupdoirep-dexiF00

nehw1otteS

evitca

wolteS

evitcanehw

t1 tib0 0 1 1

edomtpurretnidoirep-dexiF01 t

0 tib0 1 0 1

tuptuoeslupdoirep-dexiF

detibihni

11ro0"0"tiucric-nepO

tuptuO

doirep

s46/1s1nim1ruoh1

emantiB

noitcnuF

kram*

.0snrutersyawlatignidaer;tceffeonsahtibsihtotgnitirW.desutoN

raey-ot-sdnoceS

stigid

.edocDCBninettirwllA

tigidkeew-eht-fo-yaD

ot0morfstnuoctI.detnemercnierastigidyadehtemithcaestnemercnitahtretnuoc)7esab(latpesasisihT

gnidocehtesoohcnacresueht,keewehtfoyadehtotpihsnoitaleronsraebretnuocehtnieulavehtecniS.6

:pihsnoitalersihtfoelpmaxeenotsujsigniwollofehT.keewehtfoyadehtoteulavretnuocehtsetalertaht

MA/MP

ehtnehw(edomkcolc-ruoh-21rofylnodilavsitibsihT.semit.m.arof0;semit.m.prof1sitibMA/MPehT

.0syawlasitibsiht,)1sitib21/42ehtnehw(edomkcolc-ruoh-42ni;)0sitib21/42

JDAsdnoces-03

.noitcerrocsdnoces-03asetucexetibsihtot1gnitirW

GALFQRI

ot0gnitirW.edomtpurretnidoirep-dexifnidetarenegsitseuqertpurretninanehw1ottessitibGALFQRIehT

.tceffeonevahlliwsihttub,tibsihtot1etirwotelbissopsititahtetoN.tisraelctibsiht

situptuonipP.DTSehtelihw(evitcasituptuoeslupehtelihw1tasitibsiht,edomtuptuoeslupdoirep-dexifnI

evitcasituptuoeslupelihwtibsihtot0gnitirW.sdnetuptuoeslupnehwderaelcyllacitamotuasidna,)wol

.tuptuoeslupehtslecnacylbicrof

YSUB

SehtniatadgnisseccanehwtibYSUBehtesU 1 noitatnemercniehtgnirud1ottessitibsihT.sretsigerWot

Sehtfoelcyc 1 Sehtotssecca,1sitibYSUBehtnehW.esiwrehto0ottessidna,sretsigerWot 1 Wot

.detibihnisisretsiger

SehtgnisseccanehwdesueboslatsumtibDLOHehttahtetoN 1 1syawlasitibYSUBehT.sretsigerWot

.0sitibDLOHehtnehw

C(sretsigerlortnocehtgnisseccanehwtibYSUBehtkcehcotdeenonsierehT D C, E Cdna, F .)

DLOH

,1sitibDLOHehtelihW.dekcehcebnactibYSUBehtfosutatseht,tibDLOHehtotnettirwneebsah1nehW

tibDLOHehtfineve,ecnoylnodlehsinoitatnemercniehT(.ecnotsujdlehsistigidehtfonoitatnemercniyna

).sdnoceseromroowtrof1tasniamer

SCehtgnicrofyb0ottibDLOHehtraelC 1 .wolnip

t1t,

0

1ro,etunim1,dnoces1,sdnoces46/1(stpurretnidnatuptuoeslupdoirep-dexifrofgnimitehttesstibesehT

.)ruoh

DNTS/TPRTI

ottibsihtot1etirW.edomtpurretnidoirep-dexifdnaedomtuptuoeslupdoirep-dexifstestibDNTS/TPRTIehT

.edom)DNTS(tuptuoesluptesottiot0etirwnehw;edom)TPRTI(tpurretnites

KSAM

dnaksamottibsihtot1etirW.stpurretnidoirep-dexifdnatuptuoeslupdoirep-dexifselbasidtibKSAMehT

.sedomesehtelbaneottiot0etirw;sedomesehttibihni

TSET

os,tibsihtotnettirwsi1fideetnaraugebtonnacnoitarepO.sesopruptsetrofNOSPEybdesusitibTSETehT

.noitazilaitinino-rewopgnirud0ottessititahterusekam

21/42

etirw;edomruoh-42tesottibsihtot1etirW.kcolcruoh-21dnakcolcruoh-42neewtebsehctiwstib21/42ehT

ebtsumedomremitehtdnasretsigerremitehthtob,tessitib21/42ehtnehW.edomruoh-21tesottiot0

.edomkcolc-ruoh-21ni0syawlasiretsiger01Hehtfotib02hehttahtetoN.hctamotteser

POTS

langisdnoces-1ehtfosnoisividerahcihwspetszH-2918ninoitarepokcolcnonoitibihninastestibPOTSehT

dna,1sitibPOTSehtnehwdetibihnisikcolcehT.ecruosnoitallicsozH-867,23lanretnis'CTRehtmorf

tibPOTSehtnehwneveetarepootseunitnoctiucricnoitallicsolanretniehT.0semocebtinehwniagadesaeler

.1si

TESER

esaelerot0;teserottibsihtot1etirW.dnocesenowolebsitahtretnuocehtfotrapehtstesertibTESERehT

.tesereht

SCehtnehw0ottessitibTESERehT 1 .wolseognip

tnuoC0123456

yaDyadnuSyadnoMyadseuTyadsendeWyadsruhTyadirFyadrutaS

Page-11

■ Register description

1. Timing registers

(1) S1 to Y10 registers

These registers are 4-bit, positive logic registers in which the digits of the year, month, day, hour, minute, and second
are continuously written in BCD code.
For example, when(1, 0, 0, 1) has been written to the bits of the S

1 register, the current value in the S1 register is 9. As

described previously, data is handled by 4-bit BCD codes. Therefore, the S

1 to Y10 registers consist of units registers

and tens registers.
When seconds are read, for example, the values in the S

1 and S10 registers are both read out to give the total number

of seconds.

(2) W register

The W register is a counter that increments each time the day digits are incremented. It counts from 0 to 6. Since the
value in the counter bears no relationship to the day of the week, the user can choose the coding that relates the
counter value to the day of the week. The following is just one example of this relationship;

(3) H

10 register (PM/AM, h20, h10)

The H

10 register contains a combination of the 10-hours digit bits and the PM/AM bit. Therefore, the contents of this

register will depend on whether the 12-hour clock or 24-hour clock is selected. If the 12-hour clock is selected, the user
must bear in mind that this register will contain two types of data: 10-hour data in the h

10 bit and a.m./p.m. data in the

PM/AM bit. The PM/AM bit is 0 for a.m. and 1 for p.m.
For example, if a value of 48 is obtained from the H

10 and H1 registers when the H10, H1, M10, and M1 registers are read,

remember that the inclusion of a set PM/AM bit (PM/AM=1) will make the tens digit appear to be 4. Since this bit is 1,
the time is p.m. If the value read from the M

10 and M1 registers is 00, the actual time should be read as 8:00 p.m.

Similarly, if the value read from the H

10 and H1 registers is 11, the PM/AM bit is 0, and so this time is therefore a.m. If

the value read from the M

10 and M1 registers is 30, this time should be read as 11:30 a.m.

When the 12-hour clock is used, the h

20 bit should never be 1, but it is nonetheless physically possible to write a 1 in

this bit. The user should be careful to write a 0, to avoid unpredictable consequences. Note that, if a mistake in the
PM/AM value is made while in 12-hour-clock mode, the date digits will be half a day out. Correct setting is needed.
If the 24-hour clock is selected, the PM/AM bit will always be 0.
For details of how to set 12-hour or 24-hour clock, see the section on the 24/12 bit on page 15.

(4) Y

1 and Y10 registers

The Y

1 and Y10 registers can handle the last two digits of the year in the Gregorian

calendar. Leap years are automatically identified, and this affects the handling of the
month and day digits for February 29.
[Leap years]
In general, a year contains 365 days. However, the Earth takes slightly longer than
exactly 365 days to rotate around the sun, so we need to set leap years in
compensation. A leap year occurs once every four years, in years in the Gregorian
calendar that are divisible by four. However, a further small correction is necessary in
that years that are divisible by 100 are ordinary years, but years that are further
divisible by 400 are leap years.
The main leap and ordinary years since 1900 and into the future are listed on the right.

[Leap years in the RTC-72421/72423]
To identify leap years, the RTC-72421/RTC-72423 checks whether or not the year
digits are divisible by four. As implied above, 2000 will be a leap year, and so no further
correction will be necessary in that case.
This process identifies the following years as leap years:

96, (20)00, (20)04, (20)08, (20)12...
The turn-of-the-century years for which the RTC-72421/RTC-72423 will require a
correction are shown shaded in the table on the right.
If Japanese-era years are set, accurate leap-year identification will only be possible if
the era years that are divisible by four are actually leap years. As it happens, years in
the current era, Heisei, that are divisible by four are leap years, which means that
Heisei years can be set in these registers.

(5) Out-of-range data

If an impossible date or time is set, this may cause errors. If such a date is set, the behavior of the device is in general
unpredictable, so make sure that impossible data is not set.

gnitteSsemitelbissoP

kcolcruoh-21 .m.pdna.m.a,95:11ot00:21
kcolcruoh-4295:32ot00:00

tnuoC0123456

yaDyadnuSyadnoMyadseuTyadsendeWyadsruhTyadirFyadrutaS

dnasraeypaellautcA

sraeyyranidro

raeYraeypaeL

yranidrO

raey

0091

O

:

3991

O

4991

O

5991

O

6991

O

7991

O

8991

O

9991

O

0002

O

1002

O

2002

O

3002

O

4002

O

5002

O

:

0012

O

0022

O

0032

O

0042

O

:

Page-12

RTC-72421/72423

2. CD register (control register D)

(1) HOLD bit (D0)

Use the HOLD bit when accessing the S

1 and W registers. For details, see "Read/write of S1 to W registers" on page

18.

When the HOLD bit is 1, any incrementation in the count is held within the RTC. The held incrementation is
automatically compensated for when the HOLD bit becomes 0. (Second and subsequent incrementations are ignored.)
Therefore, if the HOLD bit is at 1 for two or more seconds in succession, the time will be slightly slow (delay). Make sure
that any access to the S

1 to W registers is completed within one second, then clear the HOLD bit to 0.

The status of the BUSY bit remains as set while the HOLD bit is at 1. If the HOLD bit is not cleared temporarily to 0, the
BUSY bit will not indicate any change within the RTC of the BUSY status. Therefore, when checking the status of the
BUSY bit, write 0 to the HOLD bit each time the BUSY bit is read, to update the status of the BUSY bit.
If the CS

1 pin goes low while the HOLD bit is 1, the HOLD bit is automatically cleared to 0.

There is no need to use the HOLD bit when accessing the control registers (C

D, CE, and CF).

(2) BUSY bit (D

1)

The BUSY bit indicates whether or not the digits from the seconds digit onward are being incremented, and is used
when accessing the S

1 to W registers. For details, see "Read/write of S1 to W registers" on page 18.

There is no need to check the BUSY bit when accessing the control registers (C

D, CE, and CF).

The status of the BUSY bit remains as set while the HOLD bit is at 1. If the HOLD bit is not cleared temporarily to 0, the
BUSY bit will not indicate any change within the RTC of the BUSY status. Therefore, when checking the status of the
BUSY bit, write 0 to the HOLD bit each time the BUSY bit is read, to update the status of the BUSY bit.
The BUSY bit is a read-only bit, so any attempt to write 1 or 0 to it is ignored.

(3) IRQ FLAG bit (D

2)

The IRQ FLAG bit is an internal status bit that corresponds to the status of the STD.P pin output, to indicate whether or
not an interrupt request has been issued to the CPU. When the STD.P pin output is low, the IRQ FLAG bit is 1; when
the STD.P pin output is open-circuit, the IRQ FLAG bit is 0.
When writing data to the CD register, keep the IRQ FLAG bit at 1, except when deliberately writing 0 to it. Writing 0 to
the IRQ FLAG bit cancels its status if it had become 1 at that instant or just before.

i.Interrupt processing (interrupt status monitor function)

Since the IRQ FLAG bit indicates that an interrupt request has been generated to the CPU, it is in synchronizations
with the status of the STD.P pin output. In other words, the status of the STD.P pin output can be monitored by
monitoring the IRQ FLAG bit.
In fixed-period pulse output mode, the relationship between the IRQ FLAG bit and the STD.P pin output is as
follows:

The timing of the IRQ FLAG bit and the STD.P pin output in fixed-period pulse output mode is as follows:

The output levels of the STD.P pin are low (down) and open circuit (up).

ii. STD.P pin output reset function

The STD.P pin output can be reset after an interrupt is generated by writing 0 to the IRQ FLAG bit.
The relationships of this operation are shown below. Note that writing 1 to this bit is possible, but it has no effect.

tuptuonipP.DTStibGALFQRI

woL1

)tuptuoniard-neporof(nepO0

tibYSUBtibYSUBehtfoecnacifingiSnoitidnoCskrameR

0delbanesseccA

1=DLOH

gnitnuoctonsiCTRehT
1delbasidsseccA 091(CTRehtnidetnemercnineebsahtnuocehT µ ).xams
11syawlasiYSUB0=DLOHdekcehcebtonnactnuocehT

tibDLOHtibDLOHnoitcnuF

0 .)dekcehcebtonnacsutatsYSUBeht(1syawlasitibYSUBehT

1 dnadaer,0sitibYSUBehtdna1sitibDLOHehtnehW.dekcehcebnacsutatsYSUBehT

.delbaneeraetirw

Page-13

The output levels of the STD.P pin are low (down) and open circuit (up).
Note: If the STD.P pin output remains low as set, subsequently generated interrupts are ignored. In order to prevent

interrupts from being overlooked, write 0 to the IRQ FLAG bit before the next interrupt is generated, to return
the STD.P pin to high.

iii.Initial setting of IRQ FLAG bit

If the fixed-period interrupt mode is not used, set the IRQ FLAG bit to 1. If the fixed-period interrupt mode is used,
set the IRQ FLAG bit to 0.

(4) 30-second ADJ bit (D

3)

The 30-seconds ADJ bit provides a 30-seconds correction (by which term is meant a rounding to the nearest whole
minute) when 1 is written to it. The 30-seconds correction takes a maximum of 76.3 mseconds to perform, and after the
correction the 30-seconds ADJ bit is automatically returned to 0. This operation also clears the sub-second bits of the
internal counter down to the 1/256-seconds counter. During the 30-seconds correction, access to the counter registers
at addresses 0 to C is inhibited, so monitor the 30-seconds ADJ bit to check that this bit has returned to 0, before
starting subsequent processing. If no access is made to the RTC for 76.3 mseconds or more after 1 is written to the 30­seconds ADJ bit, there is no need to check the 30-seconds ADJ bit again.

i.Operation of 30-seconds ADJ bit

Writing 1 to the 30-seconds ADJ bit performs a 30-second correction. This 30-seconds correction changes the
seconds and minutes digits as shown below. If the minutes digits have been incremented, an upward carry is
propagated.

Example: The correction caused by the 30-seconds ADJ bit sets the time within the RTC to 00:00:00 if it was within

the range of 00:00:00 to 00:00:29, or to 00:01:00 if it was within the range of 00:00:30 to 00:00:59.

ii. Access inhibited after 30-seconds correction

For 76.3 mseconds after 1 is written to the 30-seconds ADJ bit, the RTC is engaged in internal processing, so read
to and write from the S

1 to W registers is inhibited. The 30-seconds ADJ bit is automatically cleared to 0 at the end

of the 76.3 mseconds.

3. CE register (control register E)

(1) MASK bit (D0)

The MASK bit controls the STD.P pin output. The relationships between the MASK bit, ITRPT/STND bit, and STD.P pin
output are as follows:

The timings of the MASK bit, ITRPT/STND bit, and STD.P pin output are as follows:

noitcerrocerofebstigidsdnocesfosutatS noitcerrocretfastigidsdnocesfosutatS

sdnoces92otpU .stigidsetunimehtotyrracoN.sdnoces00

sdnoces95ot03 .stigidsetunimehtotyrraC.sdnoces00

noitcerrocerofebstigidsdnocesfosutatS noitcerrocretfastigidsdnocesfosutatS

sdnoces92otpU .stigidsetunimehtotyrracoN.sdnoces00

sdnoces95ot03 .stigidsetunimehtotyrraC.sdnoces00

tibGALFQRItuptuonipP.DTS

1woL

0)tuptuoniard-neporof(nepO

Page-14

RTC-72421/72423

(2) ITRPT/STND bit (D1)

The ITRPT/STND bit specifies fixed-period pulse output mode or fixed-period interrupt mode for the fixed-period
operating mode.
The mode selected by each setting of this bit is as follows:

For details of the timing of fixed-period operation, see the section on the t

0 and t1 bits below.

(3) t

0 (D2), t1 (D3) bits

These bits select the timing of fixed-period operation in fixed-period pulse output mode or fixed-period interrupt mode.
There is no special counter within the RTC for fixed-period operation; the fixed-period operation is performed at the
incrementation of the time (period) specified by the t

0 and t1 bits.

i.Setting t

0 and t1

Setting these bits specifies the generation timing for fixed-period pulse output or fixed-period interrupts.

ii. STD.P pin output control

The timing of STD.P pin output is at the incrementation of the period specified by the t

0 and t1 bits.

t

1

t

0

)ycneuqerf(doirePskrameR

00 )zH46(dnoces46/1

tuptuonipP.DTSeht,edomtuptuoeslupdoirep-dexifnI

sm5218.7rofwolsi

)sm5218.7sidoirepdnoces-46/1ehtflahtahteton(

01 )zH1(dnoces1

10 )zH06/1(etunim1
11 )zH0063/1(ruoh1

DNTS/TPRTIedomgnitarepO

0edomtuptuoeslupdoirep-dexiF

1edomtpurretnidoirep-dexiF

1. Fixed-period pulse output mode (ITRPT/STND=0)

The output levels of the STD.P pin are low (down) and open circuit (up).

2. Fixed-period interrupt mode (ITRPT/STND=1)

The output levels of the STD.P pin are low (down) and open circuit (up).

Page-15

iii.Frequency of STD.P pin output in fixed-period pulse output mode

In fixed-period pulse output mode, the timing of output is determined by the frequency of the internal crystal unit.
This means that the output can be used to measure any error in the frequency of the crystal unit.

Note: The 30-seconds correction could generate a carry. If such a carry occurs when the t

0 and t1 bits are set to

(0, 1) or (1, 1), the STD.P pin output could end up low. If the ITRPT/STND bit is 0, this low-level STD.P pin
output will be held from the time that the part of the counter that is below one second is cleared by the 30­seconds correction until the incrementation of the 1/64-second digit of the internal counter restarts. Note that
this may be different from the normal case in which the STD.P pin output is low for 7.8125 milliseconds.
The time of the low-level output of the first STD.P pin output after a RESET or STOP operation, or after 1 has
been written to the IRQ FLAG bit, may not be 7.8125 milliseconds.
If any one of the t

0, t1, or ITRPT/STND bits is overwritten, the IRQ FLAG bit may become 1. Therefore, after

writing to any of these bits, it is necessary to first write 0 to the IRQ FLAG bit then wait until the IRQ FLAG bit
changes back to 1.

4. CF register (control register F)

(1) RESET bit (D0)

Writing 1 to the RESET bit clears the sub-second bits of the internal counter down to the 1/256-seconds counter. The
reset continues for as long as the RESET bit is 1. End the reset by writing 0 to the RESET bit. If the level of the CS

1 pin

goes low, the RESET bit is automatically cleared to 0.

(2) STOP bit (D

1)

Writing 1 to the STOP bit stops the clock of the internal counter from the 1/8192 second bit onward. Writing 0 to the
STOP bit restarts the clock.
This function can be used to create a cumulative timer.

(3) 24/12 bit (D

2)

Set the 24/12 bit to select either 12-hour clock or 24-hour clock as the timer mode. In 12-hour clock mode, the PM/AM
bit is used.

i.Switching between 12-hour clock and 24-hour clock

Writing 1 to the 24/12 bit selects 24-hour clock mode. In 24-hour clock mode, the PM/AM bit is inoperative and is
always 0. Writing 0 to the 24/12 bit selects 12-hour clock mode. In 12-hour clock mode, the PM/AM bit becomes
valid. It is 0 for a.m. times and 1 for p.m. times.

ii. Overwriting the 24/12 bit

Overwriting the contents of the 24/12 bit could destroy the contents of the registers from the H

1 register upward

(from the 1-hour digit upward). Therefore, before overwriting the 24/12 bit, it is necessary to save the contents of
the hour (H

1, H10), day (D1, D10), month (MO1, MO10), year (Y1, Y10), and day-of-the-week (W) registers, then re-

write the data back into the registers to suit the new timer mode, after overwriting the 24/12 bit.

(4) TEST bit (D

3)

The TEST bit is used by EPSON for test purposes. Operation cannot be guaranteed if 1 is written to this bit, so make
sure that it is set to 0 during power-on initialization.

Example: STD.P pin output when 1 hour is set

(Conditions: t0 = 1, t1 = 1, MASK = 0)

Page-16

RTC-72421/72423

■ Using the RTC-72421/RTC-72423

1. Power-on procedure (initialization)

When power is turned on, the contents of all registers and the output from the STD.P pin are undefined. Therefore, all
the registers must be initialized after power on. Follow the procedure given below for initialization.

Page-17

(A)Starting the count

(B)Checking the status of the BUSY bit

(C)Stopping and resetting the counter

Wait 250 µs

(C) Stopping and resetting the counter

Page-18

RTC-72421/72423

2. Read/write of S1 to W registers

Use one of the procedures shown below to access registers other than the control registers (CD, CE, and CF) while the
RTC is operating. Note that the control registers can be accessed regardless of the status of the BUSY bit.

Read or write when the HOLD bit is used

or

Read when the HOLD bit is not used

The operation when the HOLD bit is not used involves reading the same
digit twice and comparing the read values. This is to avoid the problem of
reading unstable data that would occur if the data was read while the RTC
was incrementing the count.

3. Write to 30-second ADJ bit

The 30-seconds ADJ function is enabled by writing 1 to the 30-seconds ADJ bit. Note that the counter registers (S1 to
W) cannot be accessed for 76.3 mseconds after this write. Therefore, follow one of the procedures shown below to use
this function.

or

Note
The crystal unit could be damaged if subjected to excessive shock. If the crystal unit should stop operating for such a reason, the timer
within the RTC will stop. While the crystal unit is operating, the BUSY bit is automatically reset every 190 mseconds and the 30-seconds
ADJ bit, every 76.3 mseconds , but this automatic reset cannot be done if the oscillation stops. Therefore, in such a status, it is no longer
possible to escape from the BUSY bit status check loop shown in subsection 2 above or the 30-seconds ADJ bit status check loop shown in
subsection 3 above, and you should consider backing up the system. To design a fail-safe system, provide an escape from the loop to a
procedure that can process such an error if the loop is repeated for more than 0.5 to 1.0 milliseconds.

Page-19

4. Using the CS1 pin

The RTC-72421/RTC-72423 has 2 chip-select signal systems: CS0 and CS1. Use CS0 as chip-select for ordinary bus
access. CS

1 is not only used for CPU bus control, it also has the main function of switching between standby mode and

operating mode.

(1) Functions

Providing the CS

1 pin with the rated voltage levels enables CS1 to have the following functions:

● Enabling interface with microprocessor during operation within the operating voltage range (5.0 V ±0.5 V)

● Reducing current consumption during standby (to prevent through currents caused by unstable inputs, which is

inherent to C-MOS devices)

● Protecting internal data during standby
To ensure these functions, make sure that operation of the CS

1 pins observes that following conditions:

● Make sure that the voltage input to the CS

1 pin during operation is at least 4/5 VDD.

● Make sure that the voltage input to the CS

1 pin during standby is as close as possible to 0 V, to prevent through

currents.

● Make sure that the operation conforms to the timing chart below during a shift to standby mode or a return to
operating mode.

* Standby mode is a state in which a voltage lower than the RTC's rated range of operating supply voltage is applied

(4.5 V to 2.0 V). Under this condition, the timer continues to operate under battery back-up power, but the interface
between the interior and exterior of the RTC cannot be guaranteed.

(2) Timing

(3) Note

If the RTC is operated with timing conditions different from those shown above, data within the RTC could be
overwritten during a shift to standby mode or a return to operating mode. For example, if a write signal (

WR) is generated

during either of the timing conditions (t

CDR, tR) shown in the timing chart above, the data will be input before the RTC

has stabilized. To ensure that data is held throughout the entire standby process, make sure that the timing conditions
shown in the chart are followed.

■ Power supply circuit example

Note 1: This capacitor must be of a high capacity because a transient reverse current flows from the collector to the

emitter of the transistor when the power is turned off.

Note 2: Use a chargeable or lithium battery. If a chargeable battery is used, there is no need for the diode. If a lithium

battery is used, the diode is necessary. For specific details of the resistance of the resistor, contact the
manufacturer of the battery that is used.

Do not access the RTC while the voltage at CS1 is changing.

Page-20

RTC-72421/72423

■ Examples of connection to general-purpose microprocessor

When connecting the RTC-72421/RTC-72423 to a microprocessor, carefully check the AC timings of both the RTC and
the microprocessor.

1. Connection to multiplexed bus type

The resistors on the RD and WR lines are not necessary if the CPU does not have a HALT or HOLD state.

2. Connection to Z80 or compatible CPU 3. Connection to 68-series MPU

* Select IORQ or MEMRQ depending on whether the RTC maps

I/O or memory of the CPU.

Page-21

■ Reference data

Note: This data shows average values for a sample lot.

For rated values, see the specifications on page 4.

1. Connection to multiplexed bus type
(typical)

Finding the frequency stability (clock error)

1. The frequency-temperature characteristics can be
approximated by the following equation:

∆f

T(ppm)=α(θT-θX)

2

2. To determine the overall clock accuracy, add the
frequency tolerance and the voltage characteristics:

∆f/f(ppm)=∆f/f

0 + ∆fT + ∆fV

3. Finding the daily deviation:
Daily error =

∆f/f x 10

-6

x 86400

The clock error is one second per day at 11.574 ppm.

θT = 25˚C Typ.

α = -0.035ppm/˚C

2

Typ.

2. Frequency voltage characteristics
(typical)

3. Current consumption voltage
characteristics (typical)

Page-22

RTC-72421/72423

■ External dimensions

■ Marking layout

1. RTC-72421

2. RTC-72423

Unless otherwise stated, all units are mm.

Note: The illustration is a general representation of the content and location of information on the label,

and is not a detailed specification of the typeface, size, or positioning of printing used on the label.

Page-23

■ Application notes

1. Notes on handling

In order to enable the RTC-72421/RTC-72423 module to operate at low power levels, C-MOS circuitry was used in the
design of the chip. To prevent damage to this RTC, note the following points:

(1) Static electricity

While this module has built-in circuitry designed to protect it against electrostatic discharge, the chip could still be
damaged by a large discharge of static electricity. Containers used for packing and transport should be constructed of
conductive materials. In addition, only soldering irons, measurement circuits, and other such devices which do not
leak high voltages should be used with this module, which should also be grounded when such devices are being
used.

(2) Noise

If a signal with excessive external noise is applied to the power
supply or input pins, the device may malfunction or "latch up". In
order to ensure stable operation, use a bypass capacitor
(preferably ceramic) of 0.01µF to 0.1µF as close as possible to
the power supply pins (V

DD and GND). Also avoid placing any

device that generates high levels of electronic noise near the
RTC-72421/RTC-72423 module.
Do not connect signal lines to the RTC-72421/RTC-72423 module
within the area shown hatched in the figure on the right, and, if
possible, embed this area in a GND land.

(3) Voltage levels of input pins

Apply signal levels that are as close as possible to V

DD and ground, to all pins except the CS1 pin. Mid-level potentials

will cause increased current consumption and a reduced noise margin, and can impair the functioning of the device.
Since it is likely that power consumption will increase excessively and operation cannot be guaranteed, the setting of
the voltage range of V

IH2 and VIL2 at the CS1 pin should be such that the system is designed so that it is not affected

by ripple or other noise.
Note that the CS

1 pin cannot handle a TTL interface.

(4) Unused signal pins

Since the input impedance of the signal pins is extremely high, operating the device with these pins open circuit can
lead to malfunctions due to noise. Pull-up or pull-down resistors should be provided for all unused signal pins. The N.C.
pins should be connected to either V

DD or GND, to prevent noise. If not using the ALE pin, connect it directly to VDD.

Page-24

RTC-72421/72423

2. Notes on mounting

(1) Soldering temperature conditions

i.RTC-72421

Solder is used on the built-in crystal unit. Therefore, if the temperature within the package exceeds 150°C, the
characteristics of the crystal unit will be degraded and it may be damaged. Either use a soldering bath or solder by
hand. If you need to use vapor-phase or infrared reflow soldering, use the RTC-72423 module instead.
Soldering conditions: No higher than 260°C for no more than 10 seconds (on the leads only)

ii. RTC-72423

If the temperature within the package exceeds 260°C, the characteristics of the crystal unit will be degraded and it
may be damaged. Therefore, always check the mounting temperature before mounting this device. Reconfirm if
the mounting conditions are later changed.
Soldering conditions: No higher than 260°C for no more than twice at 10 seconds, or no higher than 230°C for no
more than 3 minutes.

Examples of SMD soldering conditions

Infrared reflow Vapor-phase reflow

(When increasing the temperature of resin, make sure that these curves are as gentle as possible.)

(2) Mounting equipment

While this module can be used with general-purpose mounting equipment, the internal crystal unit may be damaged
in some circumstances, depending on the equipment and conditions. Therefore, you should confirm that the module
will survive the mounting process that will be used before actually using this module in full-scale production. In
addition, if the mounting conditions are later changed, the survivability of the module should be reconfirmed under the
new conditions.

(3) Ultrasonic cleaning

There is a possibility that the crystal unit will be damaged by resonance during ultrasonic cleaning. Since the
conditions under which ultrasonic cleaning is carried out (the type of cleaner, power level, time, state of the inside of
the cleaning vessel, etc.) vary widely, this device is not warranted against damage during ultrasonic cleaning.

(4) Mounting orientation

This device can be damaged if it is mounted in the wrong orientation. Always confirm the orientation of the device
before mounting.

(5) Leakage between pins

Leakage between pins may occur if the power is turned on while the device has condensation or dirt on it. Make sure
the device is dry and clean before supplying power to it.

ELECTRONIC DEVICE MARKETING DEPARTMENT

AMERICA
EPSON AMERICA, INC.

EUROPE
EPSON EUROPE ELECTRONICS GmbH

EPSON EUROPE ELECTRONICS UK Office

EPSON EUROPE ELECTRONICS FRANCE Office

EPSON ITALIA S.P.A.

ASIA
EPSON HONG KONG LTD.

EPSON TAIWAN TECHNOLOGY & TRADING LTD.

EPSON SINGAPORE PTE. LTD.

SHANGHAI EPSON ELECTRONICS CO., LTD.

SEIKO EPSON CORPORATION KOREA Office

Distributor

http://www.epson.co.jp

Eiectoronic devices information on WWW server

20770 Madrona Avenue Torrance, CA 90503 2842 U.S.A.
Phone: [phone] Fax: [phone]

Riesstrasse 15, 80992 Muenchen GERMANY
Phone: (49)-(0)89-14005-0 Fax: 4(49)-(0)89-14005-110

G6 Doncastle House , Doncastle Road, Bracknell, Berkshire, RG12 8PE ,England
Phone: (41)-(0)1-344-381700 Fax : (41)-(0)1-344-381701

Les Conquerants Immeuble "Fujiyama" , L.P 915 1 Avenue de l' Atlantique , Z.A. de Courtaboeuf 2 , 91976 Les Ulis Cedex

Phone: (33)-(0)1-64-86-23-50 Fax: (33)-(0)1-64-86-23-55

V.le F.lli Casiraghi, 427 20099 Sesto San Giovanni, Milan, ITALY
Phone: [phone] Fax: [phone]

20/F., Harbour Centre, 25 Harbour Road, Wanchai, HONG KONG
Phone: [phone] Fax: [phone]

10F, No.287, Nanking East Road, Sec.3, Taipei, TAIWAN, R.O.C.
Phone: [phone] Fax: [phone]

No.1, Temasek Avenue #36-00, Millenia Tower, SINGAPORE 039192
Phone: [phone] Fax: [phone]

4F, Bldg.,27, No.69, Guijing Road, Caoheijing, Shanghai, CHINA
Phone: [phone] Fax: [phone]

10F, KLI 63 Building,60 Yoido-dong, Youngdeungpo-Ku, Seoul, 150-010, KOREA
Phone: [phone] Fax: [phone]

Application Manual

RTC-72421/ 72423