Diodes PAM8803 User Manual

Page 1
Description
The PAM8803 is a 3W, class-D audio amplifier with 64-step digital
volume control. It offers low THD+N, allowing it to produce high-
quality sound reproduction. The new filterless architecture allows the
device to drive the speaker directly, without needing low-pass output
filters which will save 30% system cost and 75% PCB area.
With the same numbers of external components, the efficiency of the
PAM8803 is much better than class-AB cousins. It extends battery
life, making it ideal for portable applications.
The PAM8803 is available in a SSOP-24 package.
Features
3W FILTERLESS STEREO CLASS-D AUDIO
AMPLIFIER WITH DIGITAL VOLUME CONTROL
Pin Assignments
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3W Output at 10% THD with a 4 Load and 5V Power Supply
Filterless, Low Quiescent Current and Low EMI
Low THD+N
64-Step Digital Volume Control
Superior Low Noise
Low Pop Noise
Efficiency up to 90%
Short Circuit Protection
Thermal Shutdown
Few External Components to Save Space and Cost
Pb-Free Packages
Typical Applications Circuit
Applications
LCD Monitors/TV Projectors
Notebook Computers
Portable Speakers
Portable DVD Players, Game Machines
Cellular Phones/Speaker Phones
PAM8803
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Pin Descriptions
Pin
Number
1 -OUT_L Left Channel Negative Output
2 PGND Power GND
3 PGND Power GND
4 +OUT_L Left Channel Positive Output
5 PVDD Power VDD
6 MUTE Mute Control Input (active low), pull-up
7 VDD Analog VDD
8 INL Left Channel Input
9 NC No Connect
10 VREF Internal analog reference, connect a bypass capacitor from VREF to GND
11 NC No Connect
12 NC No Connect
13 DN Volume down Control (active low)
14 UP Volume up Control (active low)
15 RST Volume Controller Reset (active low)
16 NC No Connect
17 INR Right Channel Input
18 GND Analog GND
19 SHDN Shutdown Control Input (active low), pull-down
20 PVDD Power VDD
21 +OUT_R Right Channel Positive Output
22 PGND Power GND
23 PGND Power GND
24 -OUT_R Right Channel Negative Output
Pin
Name
Function
Functional Block Diagram
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Absolute Maximum Ratings (@T
These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for prolonged time periods may affect device reliability. All voltages are with respect to ground.
Parameter Rating Unit
Supply Voltage at No Input Signal 6.0
Input Voltage
Maximum Junction Temperature 150
Storage Temperature -65 to +150
Soldering Temperature 300, 5sec
Recommended Operating Conditions (@T
Parameter Rating Unit
Supply Voltage Range 2.2 to 5.5 V
Ambient Temperature Range -40 to +85 °C
Junction Temperature Range -40 to +125 °C
= +25°C, unless otherwise specified.)
A
-0.3 to V
DD
+0.3
= +25°C, unless otherwise specified.)
A
V
°C
Thermal Information
Parameter Package Symbol Max Unit
Thermal Resistance (Junction to Ambient) SSOP-24
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θ
JA
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96 °C/W
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Electrical Characteristics (@T
Parameter Symbol Test Conditions Min Typ Max Units
Supply Voltage Range
Quiescent Current
Mute Current
Shutdown Current
SHDN Input High
SHDN Input Low
MUTE Input High
MUTE Input Low
Output Offset Voltage
Drain-Source On-State Resistance
Output Power
Total Harmonic Distortion Plus Noise THD+N
Power Supply Ripple Rejection PSRR
Channel Separation CS
Oscillator Frequency
Efficiency η
Signal Noise Ratio SNR
Under Voltage Lock-Out UVLO 1.95 V
Over Temperature Protection OTP 150 °C
Over Temperature Hysteresis OTH 60 °C
PAM8803
Document number: DSxxxxx Rev. 1 - 4
= +25°C, VDD = 5V, Gain = 18dB, RL = 8, unless otherwise specified.)
A
DD
V
2.2 5.5 V
No Load 7 15
8
8.5
2.5 4 mA
0.5 10 µA
1.1 1.3
1.5 1.7
1.9 2.1
2.8 3.0
0.19
0.22
0.17
0.25
45 55 dB
60 80 dB
85 89 %
80 83 %
85 dB
87 dB
I
MUTE
I
SHDN
V
V
V
V
V
R
DS(ON)
f
I
Q
SH
SL
MH
ML
OS
P
OSC
O
RL = 8
RL = 4
V
V
IDS = 0.5A
= 0V
MUTE
= 0V
SHDN
1.2
0.5
1.2
0.5
No Load 120 300 mV
PMOSFET 0.3 0.40
N MOSFET 0.22 0.35
= 8, THD =1%
R
L
f =1kHz
RL = 8, THD = 10%
RL = 4, THD = 1%
RL = 4, THD = 10%
= 8Ω, PO = 0.5W
R
L
RL = 8Ω, PO = 1.0W
RL = 4Ω, PO = 1.0W
RL = 4Ω, PO = 2.0W
No Input, f = 1kHz, V
P
= 1W, RL = 4
O
170 210 250 kHz
P
= 1.7W, f = 1kHz, RL = 8
O
= 200mV
PP
PO = 3.0W, f = 1kHz, RL = 4
R
f = 22 to 22kHz THD = 1%
= 4
L
RL = 8
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mA
V
V
W
%
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Typical Performance Characteristics (@T
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= +25°C, unless otherwise specified.)
A
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Typical Performance Characteristics (cont.) (@T
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= +25°C, unless otherwise specified.)
A
PAM8803
PAM8803
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Typical Performance Characteristics (cont.) (@T
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= +25°C, unless otherwise specified.)
A
PAM8803
Gain Setting (VDD = 5V)
Step Gain (dB) Step Gain (dB) Step Gain (dB) Step Gain (dB)
1 -75.0 17 4.8 33 11.2 49 17.6
2 -39.7 18 5.1 34 11.6 50 18.0
3 -34.0 19 5.5 35 12.0 51 18.4
4 -28.2 20 5.9 36 12.3 52 18.8
5 -22.4 21 6.3 37 12.7 53 19.2
6 -16.5 22 6.7 38 13.2 54 19.6
7 -10.5 23 7.1 39 13.6 55 20.0
8 -8.0 24 7.5 40 14.0 56 20.4
9 -5.5 25 7.9 41 14.4 57 20.9
10 -2.9 26 8.3 42 14.8 58 21.3
11 -0.4 27 8.7 43 15.2 59 21.7
12 1.1 28 9.1 44 15.6 60 22.1
13 2.6 (Note 1) 29 9.6 45 16.0 61 22.5
14 3.6 30 10.0 46 16.4 62 22.9
15 4.0 31 10.4 47 16.8 63 23.4
16 4.4 32 10.7 48 17.2 64 23.8
Note: 1.Power on gain or gain after reset. Gain could have 1dB deviation device to device.
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Application Information
Maximum Gain
As shown in block diagram (Page 2),the PAM8803 has two internal amplifiers stage. The first stage's gain is externally configurable, while the
second stage's is internally fixed in a fixed-gain, inverting configuration. The closed-loop gain of the first stage is set by selecting the ratio of R
while the second stage's gain is fixed at 2x. Consequently, the differential gain for the IC is:
to R
J
A
The PAM8803 sets maximum R
Digital Volume Control (DVC)
The PAM8803 features a digital volume control which consists of the UP, DN and RST pins. An internal clock is used where the clock frequency
value is determined from the following formula:
f
The oscillator frequency f
Volume changes are then effected by toggling either the UP or DN pins with a logic low. After a period of 3.5 clocks pulses with either the UP or
DN pins held low, the volume will change to the next specified step, either UP or DN, and followed by a short delay. This delay decreases the
longer the line is held low, eventually reaching a delay of zero. The delay allows the user to pull the UP or DN terminal low once for one volume
change, or hold down to ramp several volume changes. The delay is optimally configured for push button volume control.
If either the UP or DN pin remains low after the first volume transition the volume will change again, but this time after 9.5 clock pulses. The
followed transition occurs at 2 clock pulses for each volume transition. This is intended to provide the user with a volume control that pauses
briefly after initial application, and then slowly increases the rate of volume change as it is continuously applied. This cycle is shown in the timing
diagram shown in Figure 1.
There are 64 discrete gain settings ranging from +24dB maximum to -75dB minimum. Upon device power on or applied a logic low to the RST
pin, the amplifier's gain is set to a default value of 2.6dB. However, when coming out of mute mode, the PAM8803 will revert back to its previous
gain setting. Volume levels for each step vary and are specified in Gain Setting table on Page 7.
If both the UP and DN pins are held high, no volume change will occur. Trigger points for the UP and DN pins are at 70% of V
logic high, and 20% of V
performance.
= 20*log [2*(RF/RJ)]
VD
= f
OSC
/213
OSC
CLK
= 218k minimum RJ = 27k, thus the maximum closed gain is 24dB.
F
value is 200kHz typical, with ±20% tolerance.The DVC’s clock frequency is 33Hz (cycle time) typical.
minimum for a
DD
maximum for a logic low. It is recommended, however, to toggle UP and DN between VDD and GND for best
DD
F
Figure 1.Timming Diagram
Mute Operation
The MUTE pin is an input for controlling the output state of the PAM8803. A logic low on this pin disables the outputs, and a logic high on this pin
enables the outputs. This pin may be used as a quick disable or enable of the outputs without a volume fade. Quiescent current is listed in the
electrical characteristic table. The MUTE pin can be left floating due to the pull-up internal.
Shutdown Operation
In order to reduce power consumption while not in use, the PAM8803 contains shutdown circuitry that is used to turn off the amplifier's bias
circuitry. This shutdown feature turns the amplifier off when logic low is placed on the SHDN pin. By switching the SHDN pin connected to GND,
the PAM8803 supply current draw will be minimized in idle mode. The SHDN pin cannot be left floating due to the pull-down internal.
PAM8803
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Application Information (cont.)
Power Supply Decoupling
The PAM8803 is a high performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output THD and
PSRR are as low as possible. Power supply decoupling is affecting low frequency response. Optimum decoupling is achieved by using two
capacitors of different types that target different types of noise on the power supply leads. For higher frequency transients, spikes, or digital hash
on the line, a good low equivalent-seriesresistance (ESR) ceramic capacitor, typically 1.0μF, placed as close as possible to the device V
terminal works best. For filtering lowerfrequency noise signals, a larger capacitor of 10µF (ceramic) or greater placed near the audio power
amplifier is recommended.
Input Capacitor (CJ)
Large input capacitors are both expensive and space hungry for portable designs. Clearly, a certain sized capacitor is needed to couple in low
frequencies without severe attenu ation. But in many cases the speakers used in portable systems, whether internal or external, have little ability
to reproduce signals below 100Hz to 150Hz. Thus, using a large input capacitor may not increase actual system performance. In this case, input
capacitor (C
In addition to system cost and size, click and pop performance is affected by the size of the input coupling capacitor, C
capacitor requires more charge to reach its quiescent DC voltage (nominally 1/2 V
feedback and is apt to create pops upon device enable. Thus, by minimizing the capacitor size based on necessary low frequency response,
turn-on pops can be minimized.
Analog Reference Bypass Capacitor (C
The Analog Reference Bypass Capacitor (C
from shutdown mode, C
supply caused by coupling into the output drive signal. This noise is from the internal analog reference to the amplifier, which appears as
degraded PSRR and THD+N.
Bypass capacitor (C
capacitor reduces clicking and popping noise from power on/off and entering and leaving shutdown.
) and input resistance (RJ) of the amplifier form a high-pass filter with the corner frequency determined equation below,
J
1
f
C
C
R2
J
J
. A larger input coupling
J
). This charge comes from the internal circuit via the
DD
)
BYP
) is the most critical capacitor and serves several important functions. During start-up or recovery
BYP
determines the rate at which the amplifier starts up. The second function is to reduce noise produced by the power
BYP
) values of 0.47μF to 1.0μF ceramic is recommended for the best THD and noise performance. Increasing the bypass
BYP
Under Voltage Lock-Out (UVLO)
The PAM8803 incorporates circuitry designed to detect when the supply voltage is low. When the supply voltage drops to 1.85V or below, the
PAM8803 outputs are disable, and the device comes out of this state and starts to normal functional when the supply voltage increases.
Short Circuit Protection (SCP)
The PAM8803 has short circuit protection circuitry on the outputs that prevents damage to the device during output-to-output and output-to- GND
short. When a short circuit is detected on the outputs, the outputs are disable immediately. If the short was removed, the device activates again.
Over Temperature Protection
Thermal protection on the PAM8803 prevents damage to the device when the internal die temperature exceeds +150°C. There is a 15 degree
tolerance on this trip point from device to device. Once the die temperature exceeds the thermal set point, the device outputs are disabled. This
is not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by +60°C. This large hysteresis will prevent motor
boating sound well and the device begins normal operation at this point with no external system interaction.
How to Reduce EMI (Electro Magnetic Interference
A simple solution is to put an additional capacitor 1000µF at power supply terminal for power line coupling if the traces from amplifier to speakers
are short (<20cm).
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Application Information (cont.)
How to Reduce EMI (Electro Magnetic Interference
Most applications require a ferrite bead filter which shows at Figure 3. The ferrite filter reduces EMI around 1 MHz and higher. When selecting a
ferrite bead, choose one with high impedance at high frequencies, but low impedance at low frequencies.
Figure 3. Ferrite Bead Filter to Reduce EMI
PCB Layout Guidelines
Grounding
At this stage it is paramount t h a t we acknowledge the need for separate grounds. Noise currents in the output power stage need to be returned
to output noise ground and nowhere else. Were these currents to circulate elsewhere, they may get into the power supply, the signal ground, etc,
worse yet, they may form a loop and radiate noise. Any of these instances results in degraded amplifier performance. The logical returns for the
output noise currents associated with Class D switching are the respective PGND pins for each channel. The switch state diagram illustrates that
PGND is instrumental in nearly every switch state. This is the perfect point to which the output noise ground trace should return. Also note that
output noise ground is channel specific. A two channels amplifier has two mutually exclusive channels and consequently must have two mutually
exclusive output noise ground traces. The layout of the PAM8803 offers separate PGND connections for each channel and in some cases each
side of the bridge. Output noise grounds must tie to system ground at the power in exclusively. Signal currents for the inputs, reference, etc need
to be returned to quite ground. This ground only ties to the signal components and the GND pin. GND then ties to system ground.
Power Supply Line
As same to the ground, VDD and each channel PVDD need to be separated and tied together at the system power supply. Recommend that all
the trace could be routed as short and thick as possible. For the power line layout, just imagine water stream, any barricade placed in the trace
(shows in Figure 4) could result in the bad performance of the amplifier.
Figure 4
Componemts Placement
The power supply decoupling capacitors need to be placed as close to VDD and PVDD pins as possible. The inputs need to be routed away from
the noisy trace. The V
bypass capacitor also needs to be close to the pin of IC very much.
REF
PCB Top Layer PCB Bottom Layer
Figure 5. Layout Example
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Application Notice
1. When PAM8803 works without filter, we must connect the speaker before turn on. Else, it will be easy to damage the chip.
2. When PAM8803 works without filter, it will be best that adding a ferrite chip bead at the outgoing line of speaker in order to suppress possible
electromagnetic interference .
3. The absolute maximum rating of operation voltage is 6.0V. While using 6V power regulator, even the chip can deliver 4W sine wave with a 4
speaker, it is not recommended for long term using due to the heat dissipation. But if the input signal is a music signal, then it can work in long
term since the average power output is much less than 4W. When using dry battery cell, we should notice that if the battery cell is 4 new dry
batteries or alkaline batteries, even the voltage will be over 6V, it still can work safety. Since the output voltage of the 4 pack of new dry
batteries will be reduced very quickly after turn on due to the internal resistance of the battery. There is no dangerous of damaging the chip
when playing music or speech, even use 4 new dry batteries. To reduce the effect of the increasing of internal resistance of battery after long
term discharging, it is recommended to connect a 1000µF electrolytic capacitor between the power supply and the ground.
4. Because digital volume control has big gain, we can not make input signal too high to cause the clipping of the output signal when increase
volume, also it may damage the chip.
Test Setup for Application Testing
Notes: 2. The AP AUX-0025 low pass filter is necessary for every class-D amplifier measurement done by AP analyzer.
3. Two 22 H inductors are used in series with load resistor to emulate the small speaker for efficiency and quiescent current measurement.
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Ordering Information
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Part Number Part Marking Package Type Standard Package
PAM8803NHR
Marking Information
PAM8803
XXXYWWLL
SSOP-24 2500 Units/Tape&Reel
PAM8803
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Package Outline Dimensions (All dimensions in mm.)
SSOP-24
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Customers represent that they have all necessary expertise in the safety and regulatory ramifications of their life support devices or systems, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of Diodes Incorporated products in such safety-critical, life support devices or systems, notwithstanding any devices- or systems-related information or support that may be provided by Diodes Incorporated. Further, Customers must fully indemnify Diodes Incorporated and its representatives against any damages arising out of the use of Diodes Incorporated products in such safety-critical, life support devices or systems.
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IMPORTANT NOTICE
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