AP7217C
1.25V 600mA CMOS LDO
Features
• Very Low Dropout Voltage
• Low Current Consumption: Typ. 40µA
• Output Voltage: 1.25V
• Guaranteed 600mA (min) Output
• Input Range up to 5.5V
• Current Limiting
• Stability with Low ESR Capacitors
• Thermal shutdown Protection
• Low Temperature Coeff icient
• SOP-8L-EP: Available in “Green” Molding Compound
(No Br, Sb)
• Lead Free Finish / RoHS Compliant (Note 1)
Applications
• CD and MP3 Players
• Cellular and PCS Phones
• Digital Still Camera
• Hand-Held Computers
Typical Application
U1
V
IN
42
General Description
The AP7217C low-dropout linear regulator operates from a 2.5V
to 5.5V supply and delivers a guaranteed 600mA (min)
continuous load current.
The space-saving SOP-8L-EP package is suitable for “pocket”
and hand-held applications.
V
IN
V
OUT
V
OUT
AP7217C
C
1uF
IN
GND
EN
8
7
AP7217C Rev. 3 1 of 9 OCTOBER 2009
DS31424 www.diodes.com © Diodes Incorporated
OFF
ON
C
1uF
OUT
Ordering Information
AP7217C
1.25V 600mA CMOS LDO
AP 7217C - 13 SP G - 13
Output voltage
13 : 1.25V
Device
Package
SP : SOP-8L-EP
Package
Code
Packaging
(Note 2)
G : Green
13” Tape and Reel
Quantity Part Number Suffix
PackingGreen
13 : Tape & Reel
AP7217C-13SPG-13 SP SOP-8L-EP 2500/Tape & Reel -13
Notes: 1. EU Directive 2002/95/EC (RoHS). All applicable RoHS exempt ions a pplied. Please visit our website at
http://www.diodes.com/products/lead_free.html
2. Pad layout as shown on Diodes Inc. suggested pad layout document AP02001, which can be found on our website at
http://www.diodes.com/datasheets/ap02001.pdf.
.
Pin Assignments
(1) SOP-8L-EP
( Top View )
GND
V
OUT
1
2
EN
8
GND
7
GND
V
3
4
IN
SOP-8L-EP
GND
6
5
GND
Pin Descriptions
Pin Name Pin No. Description
GND 1, 3, 5, 6, 7 Ground
V
2 Voltage Output
OUT
VIN 4 Supply Voltage
EN 8 High Enable
AP7217C Rev. 3 2 of 9 OCTOBER 2009
DS31424 www.diodes.com © Diodes Incorporated
Block Diagram
AP7217C
1.25V 600mA CMOS LDO
EN
On
Off
Enable
Bandgap
-
ERROR
AMP
Current
Limit
+
R1
R2
Absolute Maximum Ratings
Symbol Parameter Rating Unit
ESD HBM Human Body Model ESD Protection 3.5 KV
V
V
GND
IN
OUT
ESD MM Machine Model ESD Protection 500 V
VIN Input Voltage +6 V
I
Output Current PD/ (VIN-VO) mA
OUT
PD Power Dissipation
SOP-8L-EP
1650 mW
TJ Operating Junction Temperature Range -40 to +125 ºC
Recommended Operating Conditions
Symbol Parameter Min Max Unit
VIN Input Voltage 2.5 5.5 V
I
Output Current 0 600 mA
OUT
TA Operating Ambient Temperature -40 85 ºC
AP7217C Rev. 3 3 of 9 OCTOBER 2009
DS31424 www.diodes.com © Diodes Incorporated
AP7217C
1.25V 600mA CMOS LDO
Electrical Characteristics
(TA = 25°C, CIN= 1µF, C
Symbol Parameter Test Conditions Min Typ. Max Unit
IQ Quiescent Current IO = 0mA - 40 60 µA
I
Standby Current
STB
V
OUT
∆V
V
DROPOUT
I
LINE
∆V
Dropout Voltage
I
OUT
I
Current Limit V
LIMIT
Short Circuit Current V
SHORT
/∆VIN/V
OUT
OUT
PSRR
VEH Output ON 1.6 V
VEL
IEN Enable Pin Current -0.1 0.1 µA
θ
JA
θ
JC
Notes: 3. Test condition for SOP-8L-EP: Device mounted on 2oz copper, minimum recommended pad layout on top & bottom layer with thermal vias,
double sided FR-4 PCB.
= 1µF, VEN= VIN, unless otherwise noted)
OUT
V
= Off
EN
V
= 5.0V
IN
Output Volt age
Accuracy
Temperature
V
OUT
Coefficient
Maximum Output
Current
Line Regulation 4.3V ≤ V
= 30mA, V
I
O
-40°C to 85°C, I
I
= 100mA, V
OUT
I
= 600mA, V
OUT
V
= 5.3V 600 mA
IN
= 5.3V 750 mA
IN
= 5.3V 70 mA
IN
Load Regulation 1mA ≤ I
Power Supply
Rejection
EN Input Threshold
Thermal Resistance
Junction-to-Ambient
Thermal Resistance
Junction-to-Case
V
= 4.3V+ 0.5Vp-pAC,
IN
I
= 50mA
OUT
Output OFF 0.25 V
SOP-8L-EP (Note 3) 82 ºC/W
SOP-8L-EP (Note 3) 12 ºC/W
= 5V 1.225 1.25 1.275 V
IN
≤ 5.5V; I
IN
≤ 100mA, V
OUT
= 30mA
OUT
= 1.25V 1250
OUT
= 1.25V 2000
OUT
= 30mA 0.01 ±0.2 %/V
OUT
= 5.3V 10 20 mV
IN
2 5
±100
F = 1KHz 55 dB
µA
ppm /
mV
o
C
AP7217C Rev. 3 4 of 9 OCTOBER 2009
DS31424 www.diodes.com © Diodes Incorporated
V
A
Typical Performance Characteristics
AP7217C
1.25V 600mA CMOS LDO
Dr opout V ol tage (m
Output Current vs. Dropout Voltage
(Vout=1.25V)
2500
2000
1500
1000
500
0
100mA 200mA 300mA 400mA 500m A 600mA
Outpu t C u rrent
800
700
600
500
400
300
Max Iou t ( m
200
100
Input Volt age vs . Max Iout
(Vout=1.25V)
0
2.5V 3V 4V 5V 5.5V
Input Voltage
Quiescent Current vs Input Voltage
55
50
45
Quiescent Current vs. Temperature
55
50
45
40
35
30
Quiescent Current (uA)
25
2.5V 3V 4V 5V 5. 5V
Input Voltage
40
35
30
Quiescent Current (uA)
25
-40℃ 0℃ 25℃ 85℃ 100℃ 120℃
Temperature
AP7217C Rev. 3 5 of 9 OCTOBER 2009
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Typical Performance Characteristics (Continued)
Load Transient Response
=1.25V)
(V
OUT
Load Transient Response
AP7217C
1.25V 600mA CMOS LDO
(V
=1.25V)
OUT
AP7217C Rev. 3 6 of 9 OCTOBER 2009
DS31424 www.diodes.com © Diodes Incorporated
Application Note
AP7217C
1.25V 600mA CMOS LDO
Input Capacitor
A 1µF ceramic capacitor is recommended to connect between IN
and GND pins to de couple input po wer supply glitc h and noise.
The amount of the capacitance may be increased without limit. A
lower ESR (Equivalent Series Resistance) capacitor allows the
use of less capac itance, while higher ESR type r equires more
capacitance. This input capacitor must be located as close as
possible to the device to assure input stability and less noise. For
PCB layout, a wide copper trace is required fo r both IN and GND.
Output Capacitor
The output capacitor is required to stabilize and help the transien t
response of the LDO. The AP7217C is designed to have
excellent transient response for most applications with a small
amount of output capacitance. The AP7217C is stable with any
small ceramic output capacitors of 1.0µF or higher value, and the
temperature coefficients of X7R or X5R type. Additional
capacitance helps to reduce undershoot and overshoot during
transient. For PCB layout, the output capacitor must be placed as
close as possible to OUT and GND pins, and keep the leads as
short as possible.
Thermal Considerations
Thermal Shutdown Protection limits power dissipation in
AP7217C. When the operation junction temperature exceeds
140°C, the Over Temperature Protection circuit starts the the rma l
shutdown function and turns the pass element off. The pass
element turn on again after the junction temperature cools by
30°C. For continuous operation, do not exceed absolute
maximum operation junction temperature 125°C. The power
dissipation definition in device is:
PD = (VIN − VOUT) x I
The maximum power dissipation depends on the thermal
resistance of IC package, PCB layout, the rate of surroundings
airflow and temperature difference between junctions to ambient.
The maximum power dissipation can be calculated by following
formula:
P
= ( T
D(MAX)
Where T
125°C, T
to ambient thermal resistance.
Vin Vout
J(MAX)
is the maximum operation junction temperature
J(MAX)
is the ambient temperature and the θJA is the junction
A
Iin
C Co
+ VIN x IQ
OUT
- TA ) / θJA
IN
AP7217C
GND
Iq
OUT
Iout
ESR
ENABLE/SHUTDOWN Operation
The AP7217C (SOP-8L-EP) is turned on by setting the EN pin
high, and is turned off by pulling it low. If this feature is not used,
the EN pin should be tied to IN pin to keep the regulator output on
at all time. To ensure prop er oper atio n, th e si gnal so ur ce us ed to
drive the EN pin must be able to swing above and below the
specified turn-on/off voltage thresholds listed in the Electrical
Characteristics section under V
and VIH.
IL
Current Limit Protection
When output current at OUT pin is higher than current limit
threshold, the current limit protection will be triggered and clamp
the output current to approximately 750mA to prevent
over-current and to protect the regulator from damage due to
overheating.
Short circuit protection
When V
200mV, short circuit protection will be triggered and clamp the
output current to approximately 70mA.
pin is shorted to GND or V
OUT
voltage is less than
OUT
AP7217C Rev. 3 7 of 9 OCTOBER 2009
DS31424 www.diodes.com © Diodes Incorporated
Marking Information
(1) SOP-8L-EP
AP7217C
1.25V 600mA CMOS LDO
( Top View )
8
5
Logo
Part No.
7217C-13 : for 1.25V
7217C-13
WW X
YY
X
E
41
Package Information (All Dimensions in mm)
(1) Package Type: SOP-8L-EP
Detail "A"
7°~9°
45°
3.85/3.95
7°~9°
5.90/6.10
1.30/1.50
1.75max.
Exposed pad
0.35max.
0.15/0.25
0/0.13
1
1.27typ
1
8x-0.60
0.3/0.5
4.85/4.95
Detail "A"
3.70/4.10
0.62/0.82
3.3Ref.
Bottom View
0.254
Gauge Plane
Seating Plane
G : Green
: Year : 08, 09,10~
YY
WW
: Week : 01~52; 52
represents 52 and 53 week
X
: Internal Code
SOP-8L-EP
Exposed pad
2.4Ref.
1
5.4
6x-1.27
8x-1.55
Land Pattem Recommendation
(Unit:mm)
AP7217C Rev. 3 8 of 9 OCTOBER 2009
DS31424 www.diodes.com © Diodes Incorporated
AP7217C
1.25V 600mA CMOS LDO
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Copyright © 2009, Diod es In c orp orat e d
www.diodes.com
AP7217C Rev. 3 9 of 9 OCTOBER 2009
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