The AP7173 is a 1.5A low-dropout (LDO) linear regulator that
features a user-programmable soft-start, an enable input and
a power-good output.
The soft-start reduces inrush current of the load capacitors
and minimizes stress on the input power source during startup. The enable input and power-good output allow users to
configure power management solutions that can meet the
sequencing requirements of FPGAs, DSPs, and other
applications with different start-up and power-down
requirements.
The AP7173 is stable with any type of output capacitor of
2.2µF or more. A precision reference and feedback control
deliver 2% accuracy over load, line, and operating
temperature ranges. The AP7173 is available in both
DFN3030-10 and SO-8EP packages.
PROGRAMMABLE SOFT-START
Pin Assignments
1
IN
IN
2
3
PG
VCC
4
5
EN
1
IN
PG
2
3
EN
4
( T op View )
DFN3030-10
(T op View)
SO-8EP
AP7173
10
OUT
9
OUT
FB
8
7
SS
6
GND
OUT
8
7
FB
SSVCC
6
GND
5
Features
● Low V
● Bias voltage (V
● Low V
● Low dropout: 165mV typical at 1.5A, V
● 2% accuracy over line, load and temperature range
● Power-Good (PG) output for supply monitoring and for
sequencing of other supplies
and wide VIN range: 1.0V to 5.5V
IN
) range: 2.7V to 5.5V
VCC
range: 0.8V to 3.3V
OUT
VCC
= 5V
Applications
• PCs, Servers, Modems, and Set-Top-Boxes
• FPGA Applications
• DSP Core and I/O Voltages
• Post-Regulation Applications
• Applications With Sequencing Requirements
● Programmable soft-start provides linear voltage startup
● Bias supply permits low V
operation with good transient
IN
response
● Stable with any output capacitor ≥ 2.2µF
● DFN3030-10 and SO-8EP: available in “Green” molding
compound (No Br, Sb)
●Lead-free finish/ RoHS Compliant (Note 1)
Note: 1. EU Directive 2002/95/EC (RoHS). All applicable RoHS exemptions applied. Please visit our website at http://www.diodes.com/products/lead_free.html.
1.5A LOW DROPOUT LINEAR REGULATOR WITH
PROGRAMMABLE SOFT-START
Description
Power-Good pin, open-drain output. When the V
PG threshold the PG pin is driven low; when the V
threshold, the PG pin goes into a high-impedance state. To use the PG
pin, use a 10kΩ to 1MΩ pull-up resistor to pull it up to a supply of up to
5.5V, which can be higher than the input voltage.
Bias Input pin, provides input voltage for internal control circuitry. This
voltage should be higher than the V
Enable pin. This pin should be driven either high or low and must not
be floating. Driving this pin high enables the regulator, while pulling it
low puts the regulator into shutdown mode.
Soft-Start pin. Connect a capacitor between this pin and the ground to
set the soft-start ramp time of the output voltage. If no capacitor is
connected, the soft-start time is typically 100µS.
Feedback pin. Connect this pin to an external voltage divider to set the
output voltage.
Solder this pad to large ground plane for increased thermal
performance.
Notes: 4. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods
may affect device reliability.
5. Ratings apply to ambient temperature at 25°C . The JEDEC High-K board design used to derive this data was a 2 inch x 2 inch multilayer board
with 1-ounce internal power and ground planes and 2-ounce copper traces on the top and bottom of the board.
Recommended Operating Conditions
SymbolParameterMinMaxUnit
Note: 6. At VIN =1V, the maximum load currents may be lower than 1.5A.
Input Voltage Range -0.3 to +6 V
VCC
VEN Enable Voltage Range -0.3 to +6 V
VPG Power-Good Voltage Range -0.3 to +6 V
VSS Soft-Start Voltage Range -0.3 to +6 V
VFB Feedback Voltage Range -0.3 to +6 V
V
Output Voltage Range -0.3 to VIN +0.3 V
OUT
I
Maximum Output Current Internally Limited
OUT
PD
TJ Junction Temperature Range -40 to +150 ºC
TST Storage Junction Temperature Range -65 to +150 ºC
V
IN
V
VCC
I
OUT
T
A
Continuous Total Power
Dissipation (Note 5)
Input Voltage (Note 6) 1.0 5.5 V
Bias Voltage 2.7 5.5 V
Output Current 0 1.5 A
Operating Ambient Temperature -40 85 ºC
DFN3030-10 3690
SO-8EP 5650
1.5A LOW DROPOUT LINEAR REGULATOR WITH
PROGRAMMABLE SOFT-START
The AP7173 is a low VIN, low dropout regulator that uses
an NMOS pass FET. The VCC pin must be connected to a
DC bias supply V
the gate drive of the pass FET to function properly and to
obtain low dropout. The V
higher than the V
27 illustrates the typical application circuit for the AP7173.
VCC
for the internal control circuitry and
VCC
needs to be equal to or
and in the range of 2.7V-5.5V. Figure
IN
VCC
AP7173
PROGRAMMABLE SOFT-START
Using high quality, low ESR capacitors and placing them
close to the OUT and GND pins can improve perfomance.
DROPOUT VOLTAGE
The very low dropout makes the AP7173 well suited for
high-current, low V
/low V
IN
specified low-dropout performance for such applications,
the VCC pin should be connected to a separate supply of
at least 3.25V higher than V
application circuit where V
applications. To achieve the
OUT
. Figure 28 shows an
OUT
is 5V and V
VCC
is 1.2V.
OUT
Figure 27. Typical Application Circuit for AP7173
ADJUSTABLE OUTPUT VOLTAGE
With an external voltage divider, the AP7173 can provide
output voltage from 0.8V to 3.3V. R1 and R2 can be
calculated for any output voltage using the following
equation, where V
=0.8 is the AP7173’s internal
REF
reference voltage. Refer to Table 1 for resistor
combinations for commonly used output voltages. For
maximum voltage accuracy, R2 should be ≤ 5kΩ.
V
= V
OUT
x (1 + R1/R2)
REF
INPUT VIN AND BIAS V
CAPACITORS
VCC
It is important to keep the IN and VCC pins clear of large
Figure. 28 Typical Application Circuit for AP7173
Using Separate VCC and IN Rails
For applications where low dropout is not required or a
separate V
supply is not available, the IN and VCC pins
VCC
can be tied together. In this situation, a voltage difference
of at least 1.7V between the V
maintained for the V
to provide enough gate drive to
VCC
the pass FET. Therefore, the V
more below V
, as shown in Figure 29.
IN
and V
VCC
needs to be 1.7V or
OUT
ripples, glitches and other noises by connecting capacitors
to the IN and VCC pins. The required capacitance on thes e
pins is strongly dependent on source and wiring
impedance of the supplies.
To provide good decoupling for the input power supply V
,
IN
it is recommended that a ceramic capacitor with
capacitance of at least 1μF is connected between the IN
and GND pins at a location as close to them as possible.
High quality, low ESR capacitors should be used for better
performance.
It is critical to provide good decoupling to the VCC pin for
the AP7173’s internal control circuitry to function properly.
The minimum recommended capacitance for the V
1μF when the V
and V
are connected to the same supply, the
VCC
recommended minimum capacitance for V
and VIN are separate supplies. If the VIN
VCC
is 4.7μF.
VCC
Again good quality, low ESR capacitors should be used for
optimum performance.
OUTPUT CAPACITOR
The output capacitor affects the stability and transient
response of the LDO. The AP7173 is designed to be stable
for all types of output capacitors ≥ 2.2μF, single or multiple
VCC
is
Figure. 29 Typical Application Circuit for AP7173
Without an Auxiliary VCC Rail
PROGRAMMABLE SOFT-START
The AP7173 features a voltage-controlled soft-start that is
programmable with an external capacitor (C
AP7173 achieves a monotonic soft-start by tracking the
voltage ramp of the external soft-start capacitor until the
ramp voltage reaches the internal reference voltage.
The relationship between the soft-start time and the softstart charging current (I
and the internal reference voltage (V
t
SS
Refer to Table 2 for suggested soft-start capacitor values
ENABLE/SHUTDOWN
The EN pin can be used with standard digital signals or
relatively slow-ramping analog signals. Pulling the V
below 0.4V turns the regulator off, while driving the V
above 1.1V turns the regulator on. Figure 30 shows an
example where an RC circuit is used to delay start the
AP7173.
If not used, the EN pin can be connected to the VCC or IN
pin when the V
decoupling measures are taken for the EN pin.
is greater than 1.1V, as long as good
IN
), soft-start capacitance (CSS),
SS
) is
REF
= (V
x CSS) / I
REF
SS
EN
EN
AP7173
PROGRAMMABLE SOFT-START
over-current protection circuitry to protect the device
against overload conditions. It limits the device current to
a typical value of 3A and reduces the V
tries to pull more current.
For more effective protection against short-circuit failure,
the AP7173 also includes a short-circuit foldback
mechanism that lowers the current limit to a typical value
of 1.0A when the VFB drops to below 0.2V.
THERMAL PROTECTION
Thermal shutdown limits the AP7173 junction
temperature and protects the device from damage as a
result of overheating.
Thermal protection turns off the V
OUT
junction temperature rises to approximately +150°C,
allowing it to cool down. When the junction temperature
drops to approximately +130°C, the output is re-enabled.
Therefore, the thermal protection circuit may cycle on
and off at a rate dependent on the power dissipation,
thermal resistance, and ambient temperature.
when the load
OUT
when the AP7173’s
Figure 30. Delayed Start Using an RC
Circuit to Enable AP7173
POWER-GOOD
The power-good (PG) pin is an open-drain output and can
be pulled up through a resistor of 10kΩ to1MΩ to V
or any other rail that is 5.5V or lower. When the V
V
PG,TH+VPG,HYS
V
drops to below V
OUT
, the PG output is high-impedance; if the
, V
PG,TH
≤ 1.9V or the device i s
VCC
, V
IN
OUT
≥
OUT
disabled, the PG pin is pulled to low by an internal
MOSFET.
OVER-CURRENT AND SHORT-CIRCUIT
PROTECTION
The AP7173 features a factory-trimmed, temperature and
supply voltage compensated internal current limit and an
POWER DISSIPATION
Thermal shutdown is intented to protect the AP7173
against abnormal overheating. For normal operation,
excessive power dissipation should be avoided and good
heatsinking should be provided. Power dissipation in the
device is the product of the device dropout voltage and
the load current,
P
= (V
- V
D
IN
As can be seen, power dissipation can be minimized by
using the lowest input voltage necessary to achieve the
required output voltage regulation.
To ensure that the device junction temperature does not
exceed the specified limit of 125°C, an application should
provide heat conduction paths that have junction-toambient thermal resistance lower than the calculated
value here:
= (125°C –T
R
θJA
For the DFN package with exposed pad, the primary
conduction path for heat is through the exposed pad to
the printed circuit board (PCB). The pad should be
attached to an appropriate amount of copper PCB area to
ensure that the device does not overheat.
1.5A LOW DROPOUT LINEAR REGULATOR WITH
PROGRAMMABLE SOFT-START
G -
PackageGreen
FN : DFN 3030-10
SO-8E
SP :
Device
AP7173-FNG-7 FN DFN3030-10 3000/Tape & Reel -7
AP7173-SPG-13 SP SO-8EP 2500/Tape & Reel -13
Note: 12. Pad layout as shown on Diodes Inc. suggested pad layout document AP02001, which can be found on our website at
http://www.diodes.com/datasheets/ap02001.pdf.
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