Page 1
AP65550
Document number: DS36336 Rev. 2 - 2
1 of 14
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AP65550
Description
The AP65550 is an adaptive constant on-time mode synchronous
buck converter providing high efficiency, excellent transient response
and high DC output accuracy for low-voltage regulation in digital TV
and monitor.
The constant-on-time control scheme handles wide input/output
voltage ratios and provides low external component count. The
internal proprietary circuit enables the device to adopt both low
equivalent series resistance (ESR) output capacitors, such as SPCAP or POSCAP and ultra-low ESR ceramic capacitors.
The adaptive on-time control supports seamless transition between
continuous conduction mode (CCM) at higher load conditions and
discontinuous conduction mode (DCM) at lighter load conditions.
DCM allows AP65550 maintain high efficiency at light load conditions.
The AP65550 also features programmable soft-start, UVLO, OTP and
OCP to protect the circuit.
This IC is available in SO-8EP package.
Features
Fixed Frequency Emulated Constant On-time Control
Good Stability Independent of the Output Capacitor ESR
Fast Load Transient Response
Synchronous Rectification: 65mΩ Internal High-side Switch and
36mΩ Internal Low-side Switch
Wide Input Voltage Range: 4.5V to 18V
Output Voltage Range: 0.76V to 6V
5A Continuous Output Current
650kHz Switching Frequency
Built-in Over Current Limit
Built-in Thermal Shutdown Protection
Programmable Soft-start
Pre-biased Start-up
Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
Halogen and Antimony Free. “Green” Device (Note 3)
Pin Assignments
SW
VREG5
SS
EN
BS
GND
VIN
( Top View )
1
2
3
4
8
7
6
5
FB
SO-8EP
Applications
Gaming Consoles
Flat Screen TV sets and Monitors
Set Top Boxes
Distributed power systems
Home Audio
Consumer electronics
Network Systems
FPGA, DSP and ASIC Supplies
Green Electronics
AP65550
L1
1.5μH
R1
8.25kΩ
R2
22.1kΩ
C5
0.1µF
C2
44μF
C1
20μF
C4
8.2nF
ON
OFF
8
IN
4
SS
1
EN
3
VREG5
6
SW
7
BST
2
FB
C3
1µF
5
GND
INPUT
OUTPUT
V
OUT
1.05V
VIN
12V
Figure 1. Typical Application Circuit
5A, 18V, 650kHz ADAPTIVE COT STEP-DOWN CONVERTER
Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant.
2. See http://www.diodes.com/quality/lead_free.html for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green"
and Lead-free.
3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and
<1000ppm antimony compounds.
Typical Applications Circuit
Page 2
AP65550
Document number: DS36336 Rev. 2 - 2
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AP65550
Pin
Name
Pin Number
Function
SO-8EP
EN
1
Enable input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the
regulator, drive it low to turn off. Pull up with 100kΩ resistor for automatic startup.
FB
2
Feedback Input. FB senses the output voltage and regulates it. Drive FB with a resistive voltage
divider connected to it from the output voltage.
VREG5
3
Internal power supply output pin to connect an additional capacitor. Connect a 1μF (typical) capacitor
as close as possible to the VREG5 and GND. This pin is not active when EN is low.
SS
4
Soft-start control input pin. SS controls the soft start period. Connect a capacitor from SS to GND to
set the soft-start period.
GND
5
Ground pin is the main power ground for the switching circuit.
SW
6
Power Switching Output. SW is the switching node that supplies power to the output. Connect the
output LC filter from SW to the output load. Note that a capacitor is required from SW to BS to power
the high-side switch.
BS
7
Bootstrap pin. A bootstrap capacitor is connected between the BS pin and SW pin. The voltage across
the bootstrap capacitor drives the internal high-side NMOS switch. A 0.1μF (typical) capacitor is
required for proper operation
VIN
8
Supply input pin. A capacitor should be connected between the VIN pin and GND pin to keep the DC
input voltage constant.
EP
—
Connect the exposed thermal pad to GND on the PCB
Pin Descriptions
Functional Block Diagram
Figure 2. Functional Block Diagram
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AP65550
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AP65550
Symbol
Parameter
Rating
Unit
VIN
Supply Voltage
-0.3 to 20
V
V
REG5
VREG5 Pin Voltage
-0.3V to +6.0
V
VSW
Switch Node Voltage
-1.0 to V
IN
+0.3
V
VBS
Bootstrap Voltage
-0.3 to VSW +6.0
V
VFB
Feedback Voltage
-0.3V to +6.0
V
VEN
Enable/UVLO Voltage
-0.3V to +6.0
V
VSS
SoftStart PIN
-0.3V to +6.0
V
V
GND
GND Pin Voltage
-0.3 to 0.3
V
TST
Storage Temperature
-65 to +150
°C
TJ
Junction Temperature
+160
°C
TL
Lead Temperature
+260
°C
ESD Susceptibility (Note 5)
HBM
Human Body Model
2
kV
MM
Machine Model
200
V
Symbol
Parameter
Rating
Unit
θ
JA
Junction to Ambient
SO-8EP
70
°C/W
θ
JC
Junction to Case
SO-8EP
30
°C/W
Symbol
Parameter
Min
Max
Unit
VIN
Supply Voltage
4.5
18.0
V
TJ
Operating Junction Temperature Range
-40
+125
°C
TA
Operating Ambient Temperature Range
-40
+85
°C
Absolute Maximum Ratings (Note 4) (@T
= +25°C, unless otherwise specified.)
A
Notes: 4. Stresses greater than the 'Absolute Maximum Ratings' specified above may cause permanent damage to the device. These are stress ratings only;
functional operation of the device at these or any other conditions exceeding those indicated in this specification is not implied. Device reliability may
be affected by exposure to absolute maximum rating conditions for extended periods of time.
5. Semiconductor devices are ESD sensitive and may be damaged by exposure to ESD events. Suitable ESD precautions should be taken when
handling and transporting these devices.
Thermal Resistance (Note 6)
Note: 6. Test condition: SO-8: Device mounted on 1"x1" FR-4 substrate PCB, 2oz copper, with minimum recommended pad layout.
Recommended Operating Conditions (Note 7) (@T
Note: 7. The device function is not guaranteed outside of the recommended operating conditions.
= +25°C, unless otherwise specified.)
A
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AP65550
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
SUPPLY VOLTAGE (VIN PIN)
Input Voltage
V
IN
—
4.5 — 18
V
Quiescent Current
IQ
VFB=0.85V
—
0.9 — mA
Shutdown Supply Current
I
SHDN
VEN=0V
—
3.6
10
μA
UNDER VOLTAGE LOCKOUT
UVLO Threshold
V
UVLO
VIN Rising Test VREG5
Voltage
3.45
3.75
4.05
V
UVLO Hysteresis
V
HYS
VIN Falling Test VREG5
Voltage
0.19
0.32
0.45
V
ENABLE (EN PIN)
EN High-level Input Voltage
V
ENH
—
1.9 — —
V
EN Low-level Input Voltage
V
ENL
— — —
0.6
V
VOLTAGE REFERENCE (FB PIN)
Feedback Voltage
VFB
V
OUT
=1.05V
0.753
0.765
0.777
V
Feedback Bias Current
IFB
VFB=0.8V
-0.1
0
0.1
μA
VREG5 OUTPUT
VREG5 Output Voltage
V
VREG5
6.0V<VIN<18V 0<I
VREG5
<5mA
4.7
5.1
5.5
V
Source Current Capability
—
VIN=6V, V
VREG5
=4V
—
110 — mA
Load Regulation
—
0<I
VREG5
<5mA
— — 60
mV
Line Regulation
—
6.0V<VIN<18V I
VREG5
=5mA
—
—
20
mV
MOSFET
High-side Switch On-resistance
R
DSONH
—
—
0.065 — Ω
Low-side Switch On-resistance
R
DSONL
—
—
0.036 — Ω
CURRENT LIMIT
High Level Current Limit
I
LIM-H
L=1.5μH
5.6
6.4
7.9
A
ON-TIME TIMER
On Time
tON
VIN=12V, VOUT=1.05V
—
150 — ns
Minimum Off Time
t
OFF-MIN
VFB=0.7V
—
260
310
ns
THERMAL SHUTDOWN
Thermal Shutdown
T
OTSD
— — +160 — °C
Thermal Shutdown Hysteresis
T
HYS
— — +30 — °C
SOFT START (SS PIN)
Soft-start Source Current
I
SS-SOURCE
VSS=1V
4.2
6.0
7.8
μA
Soft-start Discharge Current
I
SS-DISCHARGE
VSS=0.5V
0.1
0.2 — mA
Electrical Characteristics (@T
= +25°C, VIN = 12V, unless otherwise specified.)
A
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AP65550
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AP65550
85˚C
-40˚C
25˚C
85˚C
25˚C
-40˚C
85˚C
25˚C
-40˚C
IO=5A
IO=2A
IO=3A
IO=4A
Typical Performance Characteristics (@T
= +25°C, VIN = 12V, V
A
= 3.3V, unless otherwise specified.)
OUT
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AP65550
VO=3.3V
VO=5V
VO=3.3V
VO=2.5V
VO=1.05V
VO=1.2V
VO=1.5V
VO=1.8V
VO=2.5V
VO=1.8V
VO=1.05V
IO=10mA
IO=1A
Typical Performance Characteristics (cont.) (@T
= +25°C, VIN = 12V, V
A
= 3.3V, unless otherwise specified.)
OUT
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AP65550
Steady State Test 5A
Time-1µs/div
Startup Through VIN No Load
Time-500µs/div
Startup Through VIN 5A Load
Time-500µs/div
Steady State Test 5A
Time-50ns/div
Shutdown Through VIN No load
Time-50ms/div
Shutdown Through VIN 5A Load
Time-50ms/div
Startup Through VEN No Load
Time-1ms/div
Startup Through VEN 5A Load
Time-2ms/div
Short Circuit Test
Time-100µs/div
Shutdown Through VEN No load
Time-20ms/div
Shutdown Through VEN 5A Load
Time-20ms/div
Short Circuit Recovery
Time-1ms/div
VIN (12V/DIV)
VOUT (1V/DIV)
IOUT (1A/DIV)
SW (10V/DIV)
VIN (12V/DIV)
VOUT (1V/DIV)
IOUT (5A/DIV)
SW (10V/DIV)
VIN (12V/DIV)
VOUT (1V/DIV)
IOUT (5A/DIV)
SW (10V/DIV)
VIN (12V/DIV)
VOUT (1V/DIV)
IOUT (1A/DIV)
SW (10V/DIV)
VEN (3V/DIV)
VOUT (1V/DIV)
IOUT (1A/DIV)
SW (10V/DIV)
VEN (3V/DIV)
VOUT (1V/DIV)
IOUT (5A/DIV)
SW (10V/DIV)
VEN (3V/DIV)
VOUT (1V/DIV)
IOUT (5A/DIV)
SW (10V/DIV)
VEN (3V/DIV)
VOUT (1V/DIV)
IOUT (1A/DIV)
SW (10V/DIV)
VOUT (500mV/DIV)
IOUT (2A/DIV)
VOUT (500mV/DIV)
IOUT (2A/DIV)
VIN_AC (1V/DIV)
VOUT_AC (50mV/DIV)
ISW (2A/DIV)
SW (10V/DIV)
VIN_AC (1V/DIV)
VOUT_AC (50mV/DIV)
ISW (2A/DIV)
SW (10V/DIV)
Typical Performance Characteristics (cont.)
(@TA = +25°C, VIN = 12V, V
= 1.05V, L = 1.5µH, C1 = 20µF, C2 = 44µF, unless otherwise specified.)
OUT
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AP65550
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AP65550
DCM Voltage Ripple 30mA
Time-1µs/div
Startup with VREG5 No Load
Time-1ms/div
EN (3V/DIV)
VREG5 (5V/DIV)
VOUT (500mV/DIV)
VOUT_AC (50mV/DIV)
SW (5V/DIV)
Typical Performance Characteristics (cont.)
(@TA = +25°C, VIN = 12V, V
= 1.05V, L = 1.5µH, C1 = 20µF, C2 = 44µF, unless otherwise specified.)
OUT
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AP65550
EN
FB
VREG5
SS
EP
GND
SW
VIN
BS
8.25KΩ
22.1KΩ
1.5µH
EN
VOUT
VIN
VOUT
AP65550
1
2
3
4 5
6
7
8
8.2nF
1µF
10µF
22µF
0.1µF
R3
R1
C4
C6
L1
C1
10µF
C2 C8
22µF
C5
C9
fV
V
T
IN
OUT
ON
ON
OUTIN
LOAD
T
2L
VV
I
Application Information
Figure 3. Typical Application of AP65550
PWM Operation and Adaptive On-time Control
The AP65550 is synchronous step-down converters with internal power MOSFETs. Adaptive constant on time (COT) control is employed to
provide fast transient response and easy loop stabilization. At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is
turned off after internal one shot timer expires. This one shot is set by the converter input voltage(VIN), and the output voltage(V
pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The output voltage variation is sensed by FB
voltage. The one-shot timer is reset and the high-side MOSFET is turned on again when FB voltage falls below the 0.76V.
AP65550 uses an adaptive on-time control scheme and does not have a dedicated in board oscillator. It runs with a pseudo-constant frequency of
650kHz by using the input voltage and output voltage to set the on-time one-shot timer. The on-time is inversely proportional to the input voltage
and proportional to the output voltage. It can be calculated using the following equation:
) to maintain a
OUT
V
is the output voltage
OUT
VIN is the input voltage
f is the switching frequency
After an ON-time period, the AP65550 goes into the OFF-time period. The OFF-time period length depends on VFB in most case. It will end when
the FB voltage decreases and below 0.76V then the ON-time periods is triggered. If the OFF-time period is less than the minimum OFF time, the
minimum OFF time will be applied, which is about 260ns typical.
Power Save Mode
The AP65550 is designed with Power Save Mode (PSM) at light load conditions for high efficiency. The AP65550 automatically reduces the
switching frequency and change the Ton time to Tmin-on time during a light load condition to get high efficiency and low output ripple. As the
output current decreases form heavy load condition, the inductor current decreases as well, eventually comes close to zero current, which is the
boundary between CCM and DCM. The low side MOSFET is turned off when the inductor current reaches zero level. The load is provided only by
output capacitor, when FB voltage is lower than 0.76V, the next cycle ON cycle is beginning. The on-time is the minimum on time that benefit for
decreasing V
OUT
keep output voltage. The transition point to light load operation can be calculated using the following equation:
TON is on-time
Enable
Above the ‘EN high-level input voltage’, the internal regulator is turned on and the quiescent current can be measured above this threshold. The
enable (EN) input allows the user to control turning on or off the regulator. To enable the AP65550, EN must be pulled above the ‘EN high-level
input voltage’ and to disable the AP65550, EN must be pulled below ‘EN low-level input voltage’.
ripple at light load condition. When the output current increases from light to heavy load, the switching frequency increases to
Page 10
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AP65550
SS
FBSS
SS
I
VCt
OC
COMPARATOR
-266mV
Q1
Q2
S
Q
R
1
0.765
V
RR
OUT
21
Figure 5. Feedback Divider Network
Output Voltage (V)
R1 (kΩ)
R2 (kΩ)
1
6.81
22.1
1.05
8.25
22.1
1.2
12.7
22.1
1.5
21.5
22.1
1.8
30.1
22.1
2.5
49.9
22.1
3.3
73.2
22.1 5 124
22.1
Table 1. Resistor Selection for Common Output
Application Information (cont.)
Soft-start
The soft-start time of the AP65550 is programmable by selecting different CSS value. When the EN pin becomes high, the C
current source, generating a ramp signal fed into non-inverting input of the error comparator. Reference voltage V
voltage SS whichever is smaller dominates the behavior of the non-inverting inputs of the error amplifier. Accordingly, the output voltage will follow
the SS signal and ramp up smoothly to its target level. The capacitor value required for a given soft-start ramp time can be expressed as:
Where CSS is the required capacitor between SS pin and GND, tSS is the desired soft-start time and VFB is the feedback voltage.
or the internal soft-start
REF
Over Current Protection (OCP)
Figure 4 shows the over current protection (OCP) scheme of AP65550. In each switching cycle, the inductor current is sensed by monitoring the
low-side MOSFET in the OFF period. When the voltage between GND pin and SW pin is smaller than the over current trip level, the OCP will be
triggered and the controller keeps the OFF state. A new switching cycle will begging when the measured voltage is larger than limit voltage. The
internal counter is incremented when OCP is triggered. After 16 sequential cycles, the internal OCL (Over Current Logic) threshold is set to a
lower level, reducing the available output current. When a switching cycle occurs where the switch current is below the lower OCL threshold, the
counter is reset and OCL limit is returned to higher value.
Because the R
dependency of R
of MOSFET increases with temperature, V
DS(ON)
.
DS(ON)
has xppm/oC temperature coefficient to compensate this temperature
Limit
is charged by a 6μA
SS
Under Voltage Lockout
The AP65550 provides an under voltage lockout circuit to prevent it from undefined status when startup. The UVLO circuit shuts down the device
when VIN drops below 3.45V. The UVLO circuit has 320mV hysteresis, which means the device starts up again when V
latch)
Thermal shutdown
If the junction temperature of the device reaches the thermal shutdown limit of 160°C, the AP65550 shuts itself off, and both HMOS and LMOS will
be turned off. The output is discharge with the internal transistor. When the junction cools to the required level (130°C nominal), the device initiates
soft-start as during a normal power -up cycle.
Setting the Output Voltage
The output voltage can be adjusted from 1.000 to 5V using an external resistor divider. Table 1 shows a list of resistor selection for common
output voltages. Resistor R1 is selected based on a design tradeoff between efficiency and output voltage accuracy. For high values of R1 there
is less current consumption in the feedback network. However the trade off is output voltage accuracy due to the bias current in the error
amplifier. R1 can be determined by the following equation:
Figure 4. Over Current Protection Scheme
rise to 3.75V. (non-
REG
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AP65550
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AP65550
SWLIN
OUTINOUT
fΔIV
)V(VV
L
L
ΔI
SW
f
2
ΔI
II
L
LOADL(MAX)
Output Voltage (V)
C10(pF)
L1(µH)
C5+C9(µF)
1
—
1.0-1.5
22-68
1.05
—
1.0-1.5
22-68
1.2
—
1.0-1.5
22-68
1.5
—
1.5
22-68
1.8
5-22
1.5
22-68
2.5
5-22
2.2
22-68
3.3
5-22
2.2
22-68
5
5-22
3.3
22-68
Application Information (cont.)
Inductor
Calculating the inductor value is a critical factor in designing a buck converter. For most designs, the following equation can be used to calculate
the inductor value;
Where
And
Choose the inductor ripple current to be 30% of the maximum load current. The maximum inductor peak current is calculated from:
Peak current determines the required saturation current rating, which influences the size of the inductor. Saturating the inductor decreases the
converter efficiency while increasing the temperatures of the inductor and the internal MOSFETs. Hence choosing an inductor with appropriate
saturation current rating is important.
A 1µH to 3.3µH inductor with a DC current rating of at least 25% percent higher than the maximum load current is recommended for most
applications. For highest efficiency, the inductor’s DC resistance should be less than 100mΩ. Use a larger inductance for improved efficiency
under light load conditions.
The phase boost can be achieved by adding a additional feed forward capacitor (C4) in parallel with R1.
is the inductor ripple current.
is the buck converter switching frequency.
Input Capacitor
The input capacitor reduces the surge current drawn from the input supply and the switching noise from the device. The input capacitor has to
sustain the ripple current produced during the on time on the upper MOSFET. It must hence have a low ESR to minimize the losses.
The RMS current rating of the input capacitor is a critical parameter that must be higher than the RMS input current. As a rule of thumb, select an
input capacitor which has RMs rating that is greater than half of the maximum load current.
Due to large dI/dt through the input capacitors, electrolytic or ceramics should be used. If a tantalum must be used, it must be surge protected.
Otherwise, capacitor failure could occur. For most applications, greater than 10µF ceramic capacitor is sufficient.
Output Capacitor
The output capacitor keeps the output voltage ripple small, ensures feedback loop stability and reduces the overshoot of the output voltage. The
output capacitor is a basic component for the fast response of the power supply. In fact, during load transient, for the first few microseconds it
supplies the current to the load. The converter recognizes the load transient and sets the duty cycle to maximum, but the current slope is limited
by the inductor value.
Table 2. Recommended Component Selection
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AP65550
ESR*ΔIVout
inductorcapacitor
2
out
2
out
2
inductor
out
o
V)V V(Δ
)
2
ΔI
L(I
C
Application Information (cont.)
Output Capacitor (cont.)
Maximum capacitance required can be calculated from the following equation:
ESR of the output capacitor dominates the output voltage ripple. The amount of ripple can be calculated from the equation below:
An output capacitor with ample capacitance and low ESR is the best option. For most applications, a 22µF to 68µF ceramic capacitor will be
sufficient.
WhereΔVis the maximum output voltage overshoot.
Bootstrap Capacitor
To ensure the proper operation, a ceramic capacitor must be connected between the VBST and SW pin. A 0.1µF ceramic capacitor is sufficient.
VREG5 Capacitor
To ensure the proper operation, a ceramic capacitor must be connected between the VREG5 and GND pin. A 1µF ceramic capacitor is sufficient.
PC Board Layout
1. The AP65550 works at 5A load current, heat dissipation is a major concern in layout the PCB. A 2oz Copper in both top and bottom
layer is recommended.
2. Provide sufficient vias in the thermal exposed pad for heat dissipate to the bottom layer.
3. Provide sufficient vias in the Output capacitor GND side to dissipate heat to the bottom layer.
4. Make the bottom layer under the device as GND layer for heat dissipation. The GND layer should be as large as possible to provide
better thermal effect.
5. Make the Vin capacitors as close to the device as possible.
6. Make the VREG5 capacitor as close to the device as possible.
7. The thermal pad of the device should be soldered directly to the PCB exposed copper plane to work as a heatsick. The thermal vias in
the exposed copper plane increase the heat transfer to the bottom layer.
Figure 6. PC Board Layout
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AP65550
AP65550 XX - 13
Packing
Package
SP : SO-8EP
13 : Tape & Reel
Part Number
Package Code
Part Marking
Identification Code
Tape and Reel
Quantity
Part Number Suffix
AP65550SP-13
SP
SO-8EP
—
2500
-13
( Top View )
AP65550
YY WW X
Logo
Part No
5
8
41
E
WW : Week : 01~52; 52
YY : Year : 08, 09,10~
G : Green
represents 52 and 53 week
E : SO-8EP Blank SO-8
X
X : Internal Code
SO-8EP (SOP-8L-EP)
Dim
Min
Max
Typ A 1.40
1.50
1.45
A1
0.00
0.13 - b
0.30
0.50
0.40
C
0.15
0.25
0.20 D 4.85
4.95
4.90
E
3.80
3.90
3.85
E0
3.85
3.95
3.90
E1
5.90
6.10
6.00 e - - 1.27
F
2.75
3.35
3.05
H
2.11
2.71
2.41 L 0.62
0.82
0.72 N - - 0.35 Q 0.60
0.70
0.65
All Dimensions in mm
Gauge Plane
Seating Plane
E1
E
N
e
b
A
45°
E0
H
F
Exposed Pad
Bottom View
L
Q
C
7°
4° ± 3°
9° (All sides)
A1
D
1 4
8 5
Ordering Information
Note: 8. For packaging details, go to our website at http://www.diodes.com/products/packages.html
Marking Information
(1) SO-8EP
Package Outline Dimensions (All dimensions in mm.)
Please see AP02002 at http://www.diodes.com/datasheets/ap02002.pdf for latest version.
(1) SO-8EP
Page 14
AP65550
Document number: DS36336 Rev. 2 - 2
14 of 14
www.diodes.com
April 2014
© Diodes Incorporated
AP65550
Dimensions
Value (in mm)
C
1.270
X
0.802
X1
3.502
X2
4.612
Y
1.505
Y1
2.613
Y2
6.500
C
Y1
X1
X
Y
Y2
X2
Suggested Pad Layout
Please see AP02001 at http://www.diodes.com/datasheets/ap02001.pdf for the latest version.
(1) SO-8EP
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IMPORTANT NOTICE
LIFE SUPPORT
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