• Halogen and Antimony Free. “Green” Device (Note 3)
Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant.
2. See http://www.diodes.com/quality/lead_free.html for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green"
and Lead-free.
3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and
<1000ppm antimony compounds.
High-Side Gate Drive Boost Input. BS supplies the drive for the high-side N-Channel MOSFET a
0.01µF or greater capacitor from SW to BS to power the high side switch.
Power Input. IN supplies the power to the IC, as well as the step-down converter switches. Drive IN
with a 4.75V to 17V power source. Bypass IN to GND with a suitably large capacitor to eliminate noise
on the input to the IC. See Input Capacitor.
Power Switching Output. SW is the switching node that supplies power to the output. Connect the
output LC filter from SW to the output load. Note that a capacitor is required from SW to BS to power
the high-side switch.
Feedback Input. FB senses the output voltage and regulates it. Drive FB with a resistive voltage
divider connected to it from the output voltage. The feedback threshold is 0.800V. See Setting the
Output Voltage.
Compensation Node. COMP is used to compensate the regulation control loop. Connect a series RC
network from COMP to GND. In some cases, an additional capacitor from COMP to GND is required.
See Compensation Components.
Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the
regulator; low to turn it off. Attach to IN with a 100k pull up resistor for automatic startup.
Soft-Start Control Input. SS controls the soft-start period. Connect a capacitor from SS to GND to set
the soft-start period. A 0.1µF capacitor sets the soft-start period to 13ms. To disable the soft-start
feature, leave SS floating.
Notes: 4. Stresses greater than the 'Absolute Maximum Ratings' specified above may cause permanent damage to the device. These are stress ratings only;
functional operation of the device at these or any other conditions exceeding those indicated in this specification is not implied. Device reliability may
be affected by exposure to absolute maximum rating conditions for extended periods of time.
5. Semiconductor devices are ESD sensitive and may be damaged by exposure to ESD events. Suitable ESD precautions should be taken when handling and transporting these devices.
Supply Voltage
Switch Node Voltage
Bootstrap Voltage
Feedback Voltage -0.3V to +6.0 V
Enable/UVLO Voltage -0.3V to +6.0 V
Comp Voltage -0.3V to +6.0 V
Storage Temperature -65 to +150 °C
Junction Temperature +160 °C
Lead Temperature +260 °C
= +25°C, unless otherwise specified.)
A
-0.3 to 20
-1.0 to V
V
-0.3 to VSW +6.0
SW
IN
+0.3
V
V
V
Thermal Resistance
Symbol Parameter Rating Unit
JA
JC
Note: 6. Test condition: SO-8EP: Device mounted on FR-4 substrate (2s2p) 2"x2" PCB, with 2oz copper trace thickness and minimum recommended pad on top
layer and thermal vias to bottom layer ground plane.
Recommended Operating Conditions(Note 7) (@T
Symbol Parameter Min Max Unit
VIN
TA
Note: 7. The device function is not guaranteed outside of the recommended operating conditions.
The AP65503 is a 5A current mode control, synchronous buck regulator with built in power MOSFETs. Current mode control assures excellent
line and load regulation and a wide loop bandwidth for fast response to load transients. The Figure 1 depicts the functional block diagram of
AP65503.
The operation of one switching cycle can be explained as follows. At the beginning of each cycle, HS (high-side) MOSFET is off. The error
amplifier (EA) output voltage is higher than the current sense amplifier output, and the current comparator’s output is low. The rising edge of the
750kHz oscillator clock signal sets the RS Flip-Flop. Its output turns on HS MOSFET. The current sense amplifier is reset for every switching
cycle.
When the HS MOSFET is on, inductor current starts to increase. The current sense amplifier senses and amplifies the inductor current. Since
the current mode control is subject to sub-harmonic oscillations that peak at half the switching frequency, ramp slope compensation is utilized.
This will help to stabilize the power supply. This ramp compensation is summed to the current sense amplifier output and compared to the error
amplifier output by the PWM comparator. When the sum of the current sense amplifier output and the slope compensation signal exceeds the
EA output voltage, the RS Flip-Flop is reset and HS MOSFET is turned off.
For one whole cycle, if the sum of the current sense amplifier output and the slope compensation signal does not exceed the EA output, then the
falling edge of the oscillator clock resets the Flip-Flop. The output of the error amplifier increases when feedback voltage (VFB) is lower than the
reference voltage of 0.8V. This also increases the inductor current as it is proportional to the comp voltage.
If in one cycle the current in the power MOSFET does not reach the COMP set current value, the power MOSFET will be forced to turn off. When
the HS MOSFET turns off, the synchronous LS MOSFET turns on until the next clock cycle begins. There is a “dead time” between the HS turn
off and LS turn on that prevents the switches from “shooting through” from the input supply to ground.
The voltage loop is compensated through an internal transconductance amplifier and can be adjusted through the external compensation
components.
Enable
Above the ‘EN Rising Threshold’, the internal regulator is turned on and the quiescent current can be measured above this threshold. The enable
(EN) input allows the user to control turning on or off the regulator. To enable the AP65503, EN must be pulled above the ‘EN Lockout Threshold
Voltage’ and to disable the AP65503, EN must be pulled below ‘EN Lockout Threshold Voltage - EN Lockout Hysteresis’
(2.2V-0.22V =1.98V).
Automated No-Load and Light-Load Operation
The AP65503 operates in Light load high efficiency mode during light load operation. The advantage of this light load high efficiency mode is low
power loss at no-load and light-load conditions. The AP65503 automatically detects the output current and enters the light load high efficiency
mode. The output current reaches a critical level at which the transitions between the light-load and heavy current mode occurs. Once the output
current exceeds the critical level, the AP65503 transitions from light load high efficiency mode to continuous PWM mode.
External Soft Start
Soft start is traditionally implemented to prevent the excess inrush current. This in turn prevents the converter output voltage from overshooting
when it reaches regulation. The AP65503 has an internal current source with a soft start capacitor to ramp the reference voltage from 0V to
0.800V. The soft start current is 6µA. The soft start sequence is reset when there is a Thermal Shutdown, Under Voltage Lockout (UVLO) or
when the part is disabled using the EN pin.
External Soft Start can be calculated from the formula below:
DV
I=
Where;
I
C = External Capacitor
DV=change in feedback voltage from 0V to maximum voltage
The AP65503 has an external COMP pin through which system stability and transient response can be controlled. COMP pin is the output of the
internal trans-conductance error amplifier. A series capacitor-resistor combination sets a pole-zero combination to control the characteristics of
the control system. The DC gain of the voltage feedback loop is given by:
V
FB
V
OUT
is the load resistor value, GCS is the current sense trans-conductance and A
LOAD
f
=
P2
G
×
EA
VOUT
(V)
2.5 44 72 10.5 6.8 4.7
3.3 44 72 10.5 6.8 4.7
5 44 72 10.5 6.8 4.7
12 44 72 10.5 6.8 6.5 - 10
1
××π
fs1.02C2
×××π
G
CS
C
/C1
IN
(µF)
Table 2 Recommended Component Selection
R2C2
V
OUT
V
LOAD
FB
C
OUT
(µF)
/C2
Rc/R3
(kΩ)
Cc/C3
(nF)
L1
(µH)
is the error
VEA
, to below one fourth of the
Z1
VEA
3R3C2
V
OUT
V
FB
AGRA×××=
VEACSLOADVDC
<×
Where V
amplifier voltage gain. The control loop transfer function incorporates two poles one is due to the compensation capacitor (C3) and the output
resistor of error amplifier, and the other is due to the output capacitor and the load resistor. These poles are located at:
Where G
One zero is present due to the compensation capacitor (C3) and the compensation resistor (R3). This zero is located at:
The goal of compensation design is to shape the converter transfer function to get a desired loop gain. The system crossover frequency where
the feedback loop has the unity gain is crucial.
A rule of thumb is to set the crossover frequency to below one-tenth of the switching frequency. Use the following procedure to optimize the
compensation components:
1. Choose the compensation resistor (R3) to set the desired crossover frequency. Determine the R3 value by the following equation:
Where f
2. Choose the compensation capacitor (C3) to achieve the desired phase margin set the compensation zero, f
crossover frequency to provide sufficient phase margin. Determine the C3 value by the following equation:
Where R3 is the compensation resistor value.
is the feedback voltage (0.800V), R
FB
G
f
=
P1
is the error amplifier trans-conductance.
EA
f
=
Z1
3R×
=
is the crossover frequency, which is typically less than one tenth of the switching frequency.
C
3C
>
EA
××π
A3C2
1
××π
fc2C2
××π
GG
×
CSEA
2
fc3R
××π
Inductor
Calculating the inductor value is a critical factor in designing a buck converter. For most designs, the following equation can be used to calculate
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