The AP6508 is a 500kHz switching frequency internal
compensated synchronous DCDC buck converter. It has
integrated compensation, and low R
MOSFETs.
The AP6508 enables continues load current of up t o 3A with
efficiency as high as 93%.
The AP6508 features current mode control operation, which
enables fast transient response times and easy loop
stabilization.
The AP6508 has external programmable softstart and a
Power Good indicator enabling sequencing and ramp control.
The AP6508 simplifies board layout and reduces space
requirements with its high level of integration and minimal
need for external components, making it ideal for distributed
power architectures.
The AP6508 is available in a standard Green DFN4030-14
package with exposed PAD for improved thermal
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performance and is RoHS compliant.
high and low side
DSON
Pin Assignments
1
IN
2
SW
3
SW
4
SW
5
SW
BST
7
EN
(Top View)
Exposed Pad
DFN4030-14
AP6508
14
AGND
13
GND
12
GND
11
VCC
10
SS
96
PG
8
FB
Features
• VIN 4.5V to 21V
• V
• 500kHz switching frequency
• Enable pin
• External Softstart
• Power Good
• Protection
adjustable to 0.8V
OUT
o OCP
Applications
• Gaming Consoles
• TV sets and Monitors
• Set Top Boxes
• Distributed power systems
• Home Audio
• Consumer electronics
o Thermal Shutdown
•Lead Free Finish/ RoHS Compliant (Note 1)
Note: 1. EU Directive 2002/95/EC (RoHS). All applicable RoHS exemptions applied. Please visit our website at
2,3,4,5 SW Switch Output. Use wide PCB trace to make the connection.
6 BST
7 EN
8 FB
9 PG Power Good
10 SS External Softstart
11
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12, 13 GND
14 AGND Analog Ground
Exposed PAD
Functional Block Diagram
V
CC
AP6508
500kHz 21V 3A SYNCHRONOUS DC/DC BUCK CONVERTER
Supply Voltage. The AP6508 operates from a 4.5V to 21V input rail. C1 is needed to
decouple the input rail. Use wide PCB trace to make the connection.
Bootstrap. A capacitor connected between SW and BS pins is required to form a floating
supply across the high-side switch driver.
EN=1 to enable the chip. For automatic start-up, connect EN pin to VIN by proper EN resistor
divider as Figure 1 shows.
Feedback. An external resistor divider from the output to GND, tapped to the FB pin, sets the
output voltage. To prevent current limit run away during a short circuit fault condition the
frequency fold-back comparator lowers the oscillator frequency when the FB voltage is below
500mV.
BIAS Supply. Decouple with 0.μ1F – 0.22μF cap. And the capacitance should be no mor e
than 0.22μF
System Ground. This pin is the reference ground for the regulated output voltage. For this
reason care must be taken in its PCB layout. Suggested to be connected to GND with copper
and vias.
No internal connection. It is recommended to connect exposed pad to GND plane for optimal
thermal performance
Notes: 2. Stresses greater than the 'Absolute Maximum Ratings' specified above, may cause permanent damage to the device. These are stress ratings
only; functional operation of the device at these or any other conditions exceeding those indicated in this specification is not implied. Device
reliability may be affected by exposure to absolute maximum rating conditions for extended periods of time.
3. Semiconductor devices are ESD sensitive and may be damaged by exposure to ESD events. Suitable ESD precautions should be taken when
handling and transporting these device.
4. Test condition for SO-8EP: Device mounted on 2"*2" FR-4 substrate PC board, 2oz copper, with minimum recommended pad on top layer and
thermal vias to bottom layer ground plane.
5. The device function is not guaranteed outside of the recommended operating conditions.
AP6508
Document number: DS33437 Rev. 5 - 2
Supply Voltage
Switch Node Voltage -0.3 to 23 V
Bootstrap Voltage VSW + 6 V
Feedback Voltage –0.3V to +6 V
Enable/UVLO Voltage –0.3V to +6 V
Comp Voltage –0.3V to +6 V
Storage Temperature -65 to +150 °C
Junction Temperature +150 °C
Lead Temperature +260 °C
Junction to Ambient 52 °C/W
Junction to Case 11 °C/W
Supply Voltage
Operating Ambient Temperature Range
Symbol Parameter Test Conditions Min Typ. Max Unit
IIN
IIN
R
DS(ON)1
R
DS(ON)2
SW
LKG
I
Limit
FSW
FFB
D
MAX
VFB
IFB
V
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EN_Rising
V
EN_HYS
IEN
EN
TD-Off
PG
Vth-Hi
PG
Vth-Lo
PGTD
VPG
I
PG_LEAK
ISS
INUV
INUV
HYS
VCC VCC Regulator
TSD
Note: 6. Guaranteed by design
Shutdown Supply Current
Supply Current (Quiescent)
High-Side Switch On-Resistance
(Note 6) 120 mΩ
Low-Side Switch On-Resistance
(Note 6) 20 mΩ
Switch Leakage Current
Current Limit 5.8 A
Oscillator Frequency
Fold-back Frequency
Maximum Duty Cycle
Feedback Voltage
Feedback Current
EN Rising Threshold 1.1 1.3 1.5 V
EN Threshold Hysteresis 0.4 V
EN Input Current
EN Turn Off Delay
(Note 6) 5
Power Good Rising Threshold 0.9
Power Good Falling Threshold 0.7
Power Good Delay 20
Power Good Sink Current Capability 0.4
Power Good Leakage Current 50
Soft-Start Current 10.5
The AP6508 is a 3A current mode, synchronous buck
regulator with built in power MOSFETs. current mode
control assures excellent line and load regulation and a
wide loop bandwidth for fast response to load transients.
Figure. 2 depicts the functional block diagram of AP6508.
The operation of one switching cycle can be explained as
follows. At the beginning of each cycle, HS (high-side)
MOSFET is off. The EA output voltage is higher than the
current sensing amplifier output, and the current
comparator’s output is low. The rising edge of the 500kHz
oscillator clock signal sets the RS Flip-Flop. Its output
turns on HS MOSFET. The current sensing amplifier is
reset for every switching cycle.
When the HS MOSFET is on, inductor current starts to
increase. The current sensing amplifier senses and
amplifies the inductor current. Since the current mode
control is subject to sub-harmonic oscillations that peak at
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half the switching frequency, slope compensation is
utilized. This will help to stabilize the power supply. This
slope compensation is summed to the current sensing
amplifier output and compared to the error amplifier output
by the PWM comparator. When the sum of the current
sensing amplifier output and the slope compensation
signal exceeds the EA output voltage, the RS Flip-Flop is
reset and HS MOSFET is turned off.
For one whole cycle, if the sum of the current sensing
amplifier output and the slope compensation signal does
not exceed the EA output, then the falling edge of the
oscillator clock resets the flip-flop. The output of the error
amplifier increases when feedback voltage (VFB) is lower
than the reference voltage of 0.807V. This also increases
the inductor current as it is proportional to the EA voltage.
When the HS MOSFET turns off, the synchronous LS
MOSFET turns on until the next clock cycle begins. There
is a “dead time” between the HS turn off and LS turn on
that prevents the switches from “shooting through” from
the input supply to ground.
The voltage loop is internally compensated with the 50pF
and 200kΩ RC network. The maximum EAMP voltage
output is precisely clamped at 2.1V.
Internal Regulator
Most of the internal circuitry including the bottom driver
are powered from the 5V internal regulator. When Vin is
less than 5V, this internal regulator cannot maintain the
5V regulation and hence the output voltage would also
drop from regulation.
AP6508
Document number: DS33437 Rev. 5 - 2
Enable
The enable (EN) input allows the user to control turning
on or off the converter. To enable the converter EN must
be pulled above the ‘EN Rising Threshold’ and to dis able
the converter EN must be pulled below ‘EN falling
Threshold’ (EN rising threshold – EN threshold
Hysteresis).
Few conditions on EN function:
1) EN must be pulled low for at least 5us to disable the
2) The voltage on EN cannot exceed 5V.
3) The AP6508 can be enabled by Vin through a voltage
Power Good
Power Good (PGOOD) is an open drain and active high
output. This output can be pulled up high to the
appropriate level with an external resistor. The PGOOD
is flagged low when Vfb=0.7V and is an open drain
output when Vfb=0.9V. The PGOOD output can deliver
a max of 4 mA sink current at 0.4 V when de- asserted.
The PGOOD pin is held low during soft-start. Once
output voltage reaches 90% of its final value, PGOOD
goes high if there are no faults.
Soft start is traditionally implemented to prevent the
excess inrush current. This in turn prevents the converter
output voltage from overshooting when it reaches
regulation. The AP6508 has an internal current source
with a soft start capacitor to ramp the reference voltage
from 0V to 0.807V. The soft start time is int ernally fixed at
2ms (TYP). The soft start time can be extended > 2ms by
adding a soft start capacitor externally. The soft start
sequence is reset when there is a thermal shutdown,
Under Voltage Lockout (UVLO) or when the part is
disabled using the EN pin.
External soft start can be calculated from the formula
below:
DV
*CI
=
SS
Where;
Iss = Soft Start Current
C = External Capacitor
DV=change in feedback voltage from 0V to maximum
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voltage
DT = Soft Start Time
Current Limit Protection
The AP6508 has cycle-by-cycle current limiting
implementation. The voltage drop across the int ernal HS
MOSFET is sensed and compared with the internally set
current limit threshold. This voltage drop is sensed at
about 30ns after the HS turns on. This voltage drop is
proportional to the peak inductor current. When the peak
inductor current exceeds the set current limit threshold,
current limit protection is activated. During this time the
feedback voltage (VFB) drops down. When the volt age at
the FB pin reaches 0.3V, the internal oscillator shifts the
frequency from the normal operating frequen cy of 500kHz
to a fold-back frequency of 150kHz. The current limit is
reduced to 70% of nominal current limit when the part is
operating at 150kHz. This low fold-back frequency
prevents current runaway.
Under Voltage Lockout (UVLO)
Under Voltage Lockout is implemented to prevent the
IC from operating under insufficient input voltages. The
AP6508 has a UVLO comparator that monitors the input
voltage and internal bandgap reference. If the input
voltage falls below 3.8V, the AP6508 will latch an under
voltage fault. In this event the AP6508 will be disabled
and power has to be re-cycled to reset the UVLO fault.
Thermal Shutdown
The AP6508 has on-chip thermal protection that prevents
damage to the IC when the die temperature exceeds safe
margins. It implements a thermal sensing to monitor the
operating junction temperature of the IC. Once the die
temperature rises to approximately 140°C, the thermal
protection feature gets activated .The internal thermal
sense circuitry turns the IC off thus preventing the po wer
switch from damage.
AP6508
Document number: DS33437 Rev. 5 - 2
DT
500kHz 21V 3A SYNCHRONOUS DC/DC BUCK CONVERTER
A hysteresis in the thermal sense circuit allows the
device to cool down to approximately 120°C before the
IC is enabled again through soft start. This thermal
hysteresis feature prevents undesirable oscillations of
the thermal protection circuit.
Setting the Output Voltage
The output voltage can be adjusted from 0.807V to 15 V
using an external resistor divider.
resistor selection for common output voltages. Resistor
R1 is selected based on a design tradeoff between
efficiency and output voltage accuracy. F or high values
of R1 there is less current consumption in the feedback
network. However the trade off is output voltage
accuracy due to the bias current in the error amplifier. R2
can be determined by the following equation:
RR
21
Figure 2. Feedback Divider Network
When output voltage is low, a T-type net work as shown
in Figure 2 is recommended.
Calculating the inductor value is a critical factor in
designing a buck converter. For most designs, the
following equation can be used to calcul ate the inductor
value;
L
=
ΔI
Where
And
Choose the inductor ripple current to be 30% of the
maximum load current. The maximum inductor peak
current is calculated from:
Peak current determines the required saturation current
rating, which influences the size of the inductor.
Saturating the inductor decreases the converter
efficiency while increasing the temperatures of the
inductor and the internal MOSFETs. Hence choosing an
inductor with appropriate saturation current rating is
important.
A 1µH to 10µH inductor with a DC current rating of at
least 25% percent higher than the maximum load current
is recommended for most applications.
For highest efficiency, the inductor’s DC resistance
should be less than 200mΩ. Use a larger inductance for
improved efficiency under light load conditions.
Input Capacitor
The input capacitor reduces the surge current drawn from
the input supply and the switching noise fr om the device.
The input capacitor has to sustain the ripple current
produced during the on time on the upper MOSFET. It
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must hence have a low ESR to minimize the losses.
The RMS current rating of the input capacitor is a critical
parameter that must be higher than the RMS input
current. As a rule of thumb, select an input capacitor
which has an RMS rating that is greater than half of the
maximum load current.
Due to large dI/dt through the input capacitors,
electrolytic or ceramics should be used. If a tantalum
must be used, it must be surge protected. Otherwise,
capacitor failure could occur. For most applications, a
4.7µF ceramic capacitor is sufficient.
Output Capacitor
The output capacitor keeps the output voltage ripple
small, ensures feedback loop stability and reduces the
overshoot of the output voltage. The output c apacitor is a
basic component for the fast response of the power
supply. In fact, during load transient, for the first few
microseconds it supplies the current to the load. The
converter recognizes the load transient and sets the duty
cycle to maximum, but the current slope is limited by the
inductor value.
Maximum capacitance required can be calculated from
the following equation:
ΔI
out
inductor
+
out
L(I
C
=
o
2
)
2
2
−+
2
V)V V(Δ
out
Where
is the maximum output voltage overshoot.
ΔV
ESR of the output capacitor dominates the output voltage
ripple. The amount of ripple can be calculated from t he
equation below:
=
inductorcapacitor
ESR*ΔIVout
AP6508
Document number: DS33437 Rev. 5 - 2
AP6508
An output capacitor with ample capacitance and low ESR
is the best option. For most applications, a 22µF ceramic
capacitor will be sufficient.
PC Board Layout
This is a high switching frequency converter. Hence
attention must be paid to the switching currents
interference in the layout. Switching current from one
power device to another can generate volt age transients
across the impedances of the interconnecting bond wires
and circuit traces. These interconnecting impedances
should be minimized by using wide, short printed circuit
traces.
The input capacitor C1
must be placed as close
as possible to the IC and
the inductor L1
34mm
AP6508 is exposed at the bottom of the package and
must be soldered directly to a well designed thermal pad
on the PCB. This will help to increase the power
dissipation.
External Bootstrap Diode
It is recommended that an external bootstrap diode be
added when the input voltage is lower than or equal to 5V
and the duty cycle is greater than 65%. This external
diode can be connected to the input or a 5V rail that is
available in the system. This helps improv e the efficiency
of the converter. The bootstrap diode can be a l ow cost
one such as BAT54 or a Schottky that has a low Vf.
Figure 3. External Bootstrap Diode
11 of 14
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The external feedback
resistor divider must be
placed as close as possible
to the FB pin of the IC
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