The AP389X is a low-cost high-resolution single chip
solution for APA capacitive touch screen. It is an
8-bit single cycle 8051 microcontroller with I
Interface. The chip includes 8-bit successive
approximation analog-to-digital converters with an
2
I
C interface and multiplexer-switcher circuits for
flexible measurement of analog signal from APA
panel. An accurate switched-capacitor integrator is
built-in and it can auto calibrate the pixel parameters
for a wide range of capacitance on the touch screen
(0.1pF to 4pF). On-chip capacitor can replace
external component. This touch screen controller
(TSC) with CMOS integration circuit provides an
ideal choice for APA touch panel. The AP389X is
specified over the temperature range of -40°C to
95°C.
The AP389X is available in QFN-7×7-56 (for
AP3890) and QFN-8×8-68 (for AP3891 and AP3892)
packages.
2
Features
•
Mutual Capacitive Touch Sensing
• Dual Power Supply: 2.8V to 3.6V Operation
Voltage; 1.6V to 2.0V Operation Voltage
•
Up to 30/38/36 Drive Lines and 17/22/23 Sense
Lines
• Dedicated Internal Two-wire Serial Control Bus
2
I
C and UART between AP389X and Host
•
Single-end Integrator with Programmable Gain
Control and Offset Control
• Multiplexed Analog Digitization with Two 8-bit
Resolution Odd/Even Scan SAR ADCs and Its
Dedicated 2X to 8X Accumulator XSRAM
Buffers
State); 48MHz from IOSC(With Wait State)
4MHz to 48MHz Internal Oscillator (IOSC)
64K-byte Flash ROM
256-byte Internal SRAM and 12032-byte
XSRAM
Extra XSRAMs for AFE:
896×12-bit×2 XSRAM for 8-bit SAR ADC
896×8-bit XSRAM for 8-bit Parasitical
Capacitor Compensator
Two 16-bit Timers T0/T1 and One 16-bit ECT
Timer T2
2
One I
C Slave Controller and One I2C Master
Controller Shared with the Same Port
With Asynchronous I
Detection Logic Design
4 General Purpose GPIO Pins
One External Interrupt Pin
One UART Data Transfer Output Pin
• ISP/IAP via I²C Port
• Operation Temperature Range: -40°C to 95°C
• Package Types: QFN-7×7-56 and QFN-8×8-68
• RoHS Compliance
• O perating Mode:
Mode Description
Power-downNo scan with power-down mode
Standard Higher scan rate when fingers are
Test Mode Enable High Active
This pin has an internal weakly pull low
resistor connected. If it is connected high, the
chip enters into Test Mode condition
Port 1.2 GPIO
8051 P1.2 GPIO
SDA
This pin also can be configured as the SDA
signal of the I2C master or I2C slave controller.
In this operation mode, this pin should also be
configured as bi-directional I/O with
open-drain output
Port 1.3 GPIO
8051 P1.3 GPIO
SCL
This pin also can be configured as the SCL
signal of the I
2
In I
C master mode, this pin should be
configured as open-drain output. In I
this pin should be configured as input only
Reset Low Active
Typically connect a resistor to VDD18 and a
capacitor to VSS
Low asserted and threshold at 0.5×V
forced low, the chip enters into reset condition
This pin should not be connected to any level
above V
AP389X Support 7” to 13” Touch Panel, Listed Below:
PN TX/ RX Multi - Touch Package Panel size
AP3890 30/17 10 point 100HZ QFN-7x7-56 7” to 10”
AP3891 38/22 10 point 100HZ QFN-8x8-68 8” to 13”
AP3892 36/23 10 point 100HZ QFN-8x8-68 8” to 13”
Absolute Maximum Ratings (Note 1)
ParameterSymbol Value Unit
Supply Voltage 1 VDD 2.8 to 3.6 V
Supply Voltage 2 V
Analog Input Voltage (Other pins) V
Logic Input Voltage V
Power Dissipation PD 250 mW
Maximum Junction Temperature TJ 100 °C
Operating T em perature TOP -40 to 95 °C
Storage Temperature T
1.6 to 2.0 V
DD18
-0.3 to VDD+0.3 V
DDA
-0.3 to VDD+0.3 V
DDD
-65 to 150 °C
STG
Note 1: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. These are stress ratings only, and functional operation of the device at these or any other conditions
beyond those indicated under “Recommended Operating Conditions” is not implied. Exposure to “Absolute
Maximum Ratings” for extended periods may affect device reliability.
TA=–40°C to 95°C, VDD=3.3V, I2C bus frequency=400kHz, unless otherwise noted.
Parameter Symbol Test Condition Min Typ Max Unit
ADC DC Accuracy
Resolution 8 Bits
No Missing Codes
Integral Linearity Error INL
Differential Linearity Error
Offset Error
DNL External V
Gain Error
Analog Input
Full-scale Input Span
Absolute Input Range
ADC Sampling Dynamics
Throughput Rate 500 ksps
Reference Input
Input Voltage Range 1.8 VDD V
Switched-capacitor Integrator
Output Voltage Range 0.3 VDD-0.3 V
Integrator Capacitor C
INT
Digital Input/Output
Logic Family CMOS
Input High Voltage VIH 0.7×VDD V
Input Low Voltage VIL -0.3 0.3×VDD V
Output High Voltage VOH 0.8×VDD V
Output Low Voltage VOL 0.4 V
Input High Voltage for
P3.6 (GPIO18)
Input Low Voltage for P3.6
(GPIO18)
Output High Voltage for
P3.6 (GPIO18)
Output Low Voltage for
P3.6 (GPIO18)
DA/AC Characteristics for 8051 CPU Core, Digital GPIO pins, Digital Peripherals, and
IOSC
T
=–40°C to 95°C, VDD=2.8V to 3.6V, unless otherwise noted.
A
Parameter Symbol Min Typ Max Unit Note
Power Supply Current
Normal Mode Supply Current
Using IOSC up to 48MHz
Normal Mode Supply Current
Using IOSC=4MHz
PMM Mode Supply Current Using
IOSC up to 48MHz
PMM Mode Supply Current Using
IOSC=4MHz
Idle Mode Supply Current Using
IOSC up to 48MHz
Stop Mode Supply Current Using
IOSC Keeps Low
I
, normal IOSC1 25 mA 2
DD
I
, normal IOSC2 2.9 mA 2
DD
I
, PMM IOSC1 6 mA 2
DD
, PMM IOSC2 1.5 mA 2
I
DD
I
, idle IOSC1 3 mA 2
DD
I
, stop 3
DD
A
2
Digital GPIO Characteristics
Input High Voltage VIH 2 3.6 V 3
Input Low Voltage VIL -0.3 0.8 V 3
Output High Voltage VOH 2.4 V 3
Output Low Voltage VOL 0.4 V 3
I
(2mA) 3.0 7.87 12.9 mA
High Level Output Current
@V
(min)
OH
Low Level Output Current
@V
(max)
OL
Input Pull Up Resistance RPU 34 74
Input Pull Down Resistance RPD 29 86
OH
IOH(4mA) 7.7 15.6 25.8 mA
I
(2mA) 3.4 5.4 7.4 mA
OL
IOL(4mA) 6.7 10.7 14.7 mA
k
k
3
3
Input Low to High Level, RSTN VIH, RSTN 0.85 0.93 V 4
Input High to Low Level, RSTN VIL, RSTN 0.63 0.71 V 4
Output Rise Time t
Output Fall Time t
5 ns 7
RISE
5 ns 7
FALL
Internal 3.3V-to-1.8V LDO from AFE
Internal 1.8V Regulato r Output V
Power On/Off Reset Level V
, 15mA 1.6 1.8 2.0 V 5
DD18
, Reset 80 85 90 % 6
DD18
Note 2: Does not include load current and tested under NOP loop and all peripheral disabled.
Note 3: For Digital I/O only.
Note 4: For RSTN pin only.
Note 5: Supply to internal digital and analog circuit only.
Note 6: This is measured as the percentage of steady state value of V
DD18
.
Note 7: This is measured with 20pF load and 20% to 80% output level.
BCD Semiconductor Manufacturing Limited reserves the right to make changes without further notice to any products or specifications herein. BCD Semiconductor Manufacturing Limited does not assume any responsibility for use of any its products for any
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particular purpose, nor does BCD Semiconductor Manufacturing Limited assume any liability arising out of the application or use
of any its products or circuits. BCD Semiconductor Manufacturing Limited does not convey any license under its patent rights or
BCD Semiconductor Manufacturing Limited reserves the right to make changes without further notice to any products or specifi-
BCD Semiconductor Manufacturing Limited reserves the right to make changes without further notice to any products or specifi-
other rights nor the rights of others.
cations herein. BCD SemiconductorManufacturing Limited does not assume any responsibility for use of any its products for any
cations herein. BCD SemiconductorManufacturing Limited does not assume any responsibility for use of any its products for any
particular purpose, nordoes BCD Semiconductor Manufacturing Limited assume anyliability arising out ofthe application or use
particular purpose, nordoes BCD Semiconductor Manufacturing Limited assume anyliability arising out ofthe application or use
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of any its products or circuits. BCD Semiconductor Manufacturing Limited does not convey any license under its patent rights or
of any its products or circuits. BCD Semiconductor Manufacturing Limited does not convey any license under its patent rights or