Diodes AP389X User Manual
Data Sheet
Enhanced Multi-touch Capacitive Touch Screen Controller AP389X
General Description
The AP389X is a low-cost high-resolution single chip
solution for APA capacitive touch screen. It is an
8-bit single cycle 8051 microcontroller with I
Interface. The chip includes 8-bit successive
approximation analog-to-digital converters with an
2
I
C interface and multiplexer-switcher circuits for
flexible measurement of analog signal from APA
panel. An accurate switched-capacitor integrator is
built-in and it can auto calibrate the pixel parameters
for a wide range of capacitance on the touch screen
(0.1pF to 4pF). On-chip capacitor can replace
external component. This touch screen controller
(TSC) with CMOS integration circuit provides an
ideal choice for APA touch panel. The AP389X is
specified over the temperature range of -40°C to
95°C.
The AP389X is available in QFN-7×7-56 (for
AP3890) and QFN-8×8-68 (for AP3891 and AP3892)
packages.
2
Features
•
Mutual Capacitive Touch Sensing
• Dual Power Supply: 2.8V to 3.6V Operation
Voltage; 1.6V to 2.0V Operation Voltage
•
Up to 30/38/36 Drive Lines and 17/22/23 Sense
Lines
• Dedicated Internal Two-wire Serial Control Bus
2
I
C and UART between AP389X and Host
•
Single-end Integrator with Programmable Gain
Control and Offset Control
• Multiplexed Analog Digitization with Two 8-bit
Resolution Odd/Even Scan SAR ADCs and Its
Dedicated 2X to 8X Accumulator XSRAM
Buffers
QFN-7×7-56
Figure 1. Package Types of AP389X
Apr. 2013 Rev. 1. 0 BCD Semiconductor Manufacturing Limited
Features (Continued)
• Single Cycle 8051 CPU Core, Maximum Opera-
ting Clock up to 24MHz from IOSC (Zero Wait
C
State); 48MHz from IOSC(With Wait State)
4MHz to 48MHz Internal Oscillator (IOSC)
64K-byte Flash ROM
256-byte Internal SRAM and 12032-byte
XSRAM
Extra XSRAMs for AFE:
896×12-bit×2 XSRAM for 8-bit SAR ADC
896×8-bit XSRAM for 8-bit Parasitical
Capacitor Compensator
Two 16-bit Timers T0/T1 and One 16-bit ECT
Timer T2
2
One I
C Slave Controller and One I2C Master
Controller Shared with the Same Port
With Asynchronous I
Detection Logic Design
4 General Purpose GPIO Pins
One External Interrupt Pin
One UART Data Transfer Output Pin
• ISP/IAP via I²C Port
• Operation Temperature Range: -40°C to 95°C
• Package Types: QFN-7×7-56 and QFN-8×8-68
• RoHS Compliance
• O perating Mode:
Mode Description
Power-down No scan with power-down mode
Standard Higher scan rate when fingers are
on panel, IOSC can up to 4MHz
to 48MHz
2
C Slave Address
Applications
• Mobile Phones
• Personal Digital Assistants
• Smart Hand-held or Gaming Devices
1
QFN-8×8-68
Data Sheet
Enhanced Multi-touch Capacitive Touch Screen Controller AP389X
Pin Configuration
FN Package
(QFN-7×7-56)
Pin 1 Mark
56
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28
EP
43444546474849505152535455
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Figure 2. Pin Configuration of AP3890 (Top View)
Apr. 2013 Rev. 1. 0 BCD Semiconductor Manufacturing Limited
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Data Sheet
Enhanced Multi-touch Capacitive Touch Screen Controller AP389X
Pin Configuration (Continued)
FN Package
(QFN-8×8-68)
Pin 1 Mark
S8
P1.7/
TXD1
/PINT0.1/EXTCLKIN
TESTEN
P1.2/SDA
P1.3/SCL
RSTN
D38
D37
D36
D35
D34
D33
D32
D31
D30
D29
D28
D27
/T0
S22
68
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
S19
S20
S21
67
66
65
202122232425262728293031323334
19
S16
S14
S15
S17
S18
63626160595857
64
EP
S13
S11
S10
S12
5655545352
69 VSS
S9
S7
S6
51
S5
50
S4
49
S3
48
S2
47
S1
46
VDD33
45
VDD18
44
P3.6/RXD1(GPIO18)
43
D1
42
D2
41
D3
40
D4
39
D5
38
D6
37
D7
36
D8
35
D9
D24
D22
D26
D25
D23
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
Figure 3. Pin Configuration of AP3891 (Top View)
Apr. 2013 Rev. 1. 0 BCD Semiconductor Manufacturing Limited
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Data Sheet
Enhanced Multi-touch Capacitive Touch Screen Controller AP389X
Pin Configuration (Continued)
FN Package
(QFN-8×8-68)
S8
S9
S23
68
S22
67
S21
66
S17
S18
S19
S20
63626160595857
64
65
S16
S15
S14
S13
S12
5655545352
S11
S10
S7
202122232425262728293031323334
18
19
D9
D24
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D8
Figure 3. Pin Configuration of AP3892 (Top View)
Apr. 2013 Rev. 1. 0 BCD Semiconductor Manufacturing Limited
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Data Sheet
Enhanced Multi-touch Capacitive Touch Screen Controller AP389X
Pin Description
Pin Number
QFN-56
AP3890
QFN-68
AP3891 AP3892
1 1 1
2 2 2 TESTEN I
3 3 3
4 4 4
5 5 5 RSTN I
Pin Name
P1.7/
TXD1/
PINT0.1/
EXTCLKIN/
T0
P1.2/SDA
(open-drain)
P1.3/SCL
(open-drain)
Pin
Type
I/O
I/O
I/O
Pin Function
Port 1.7 GPIO
8051 P1.7 GPIO
TXD1
This pin also can be configured as TXD of
UART 1
PINT0.1
This pin also can be configured as the
expanded INT0 interrupt
External Clock Input
External clock input source.
T0 Timer 0 Input
This pin also can be configured as Timer 0
input
Test Mode Enable High Active
This pin has an internal weakly pull low
resistor connected. If it is connected high, the
chip enters into Test Mode condition
Port 1.2 GPIO
8051 P1.2 GPIO
SDA
This pin also can be configured as the SDA
signal of the I2C master or I2C slave controller.
In this operation mode, this pin should also be
configured as bi-directional I/O with
open-drain output
Port 1.3 GPIO
8051 P1.3 GPIO
SCL
This pin also can be configured as the SCL
signal of the I
2
In I
C master mode, this pin should be
configured as open-drain output. In I
this pin should be configured as input only
Reset Low Active
Typically connect a resistor to VDD18 and a
capacitor to VSS
Low asserted and threshold at 0.5×V
forced low, the chip enters into reset condition
This pin should not be connected to any level
above V
2
C master or I2C slave controller.
DD18
2
C slave,
. When
DD18
Apr. 2013 Rev. 1. 0 BCD Semiconductor Manufacturing Limited
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Data Sheet
Enhanced Multi-touch Capacitive Touch Screen Controller AP389X
Pin Description (Continued)
Pin Number
QFN-56
AP3890
-
- 8 to 13 6 to 11
6 to 35
36 44 42
37 69 43 VSS Power
38 45 44 VDD18 Power
39 46 45 VDD33 Power
40 to 56
-
- - 68 S23 I, A
QFN-68
AP3891 AP3892
6, 7
14 to
43
47 to
63
64 to
68
-
12 to
41
46 to
62
63 to
67
Pin
Name
D38,
D37
D36 to
D31
D30 to
D1
P3.6/
RXD1
(open-
drain)
S1 to
S17
S18 to
S22
Pin
Type
O, A
O, A
O, A
I/O
I, A
I, A
Pin Function
D38, D37
Driving line 38 to line 37
D36, D35, D34, D33, D32, D31
Driving line 36 to line 31
D30, D29, D28, D27, D26, D25, D24, D23, D22,
D21, D20, D19, D18, D17, D16, D15, D14, D13,
D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2,
D1
Driving line 30 to line 1
Port 3.6 GPIO
8051 P3.6 GPIO
This pin should be configured as open-drain output
and the input range can be 1.8V to 3.3V
RXD1
This pin also can be configured as RXD of UART 1
Ground Voltage. 0V
Internal Regulator Output. 1. 6V to 2.0V
Typical decoupling capacitors of 0.1F and 10F
should be connected between VDD18 and VSS
Supply Voltage. 2.8V to 3.6V
A good decoupling capacitor between VDD33 and
VSS is critical for good performance
S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12,
S13, S14, S15, S16, S17
Sensing line 1to line 17
S18, S19, S20, S21, S22
Sensing line 18 to line 22
S23
Sensing line 23
Apr. 2013 Rev. 1. 0 BCD Semiconductor Manufacturing Limited
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