Diodes AP386X User Manual
Preliminary Datasheet
Superior Multi-touch Capacitive Touch Screen Controller AP386X
General Description
The AP386X is a low-cost high-resolution single chip
solution for APA (All point addressable) capacitive
touch screen. It is an 8-bit single cycle 8051
microcontroller with ICP Interface. The chip includes
12-bit successive approximation analog-to-digital
converters with an I
multiplexer-switcher circuits for flexible
measurement of analog signal from APA panel. An
accurate switched-capacitor integrator is built-in and
it can auto calibrate the pixel parameters for a wide
range of capacitance on the touch screen (1pF to
32pF). This touch screen controller (TSC) with
CMOS integration circuit provides an ideal choice for
APA touch panel. The AP386X is specified over the
temperature range of -40°C to 85°C.
The AP386X is available in QFN-5×5-40 (for
AP3860) and QFN-6×6-48 (for AP3861) packages.
2
C interface and
Features
•
Mutual Capacitive Touch Sensing
•
Single Power Supply: 2.8V to 3.6V Operation
Voltage; LDO inside to Support 1.6V to 2.0V
Operation Voltage
•
Up to 17/23 Drive Lines and 10/12 Sense Lines
•
Charge Pump Support up to 6V, Doubling SNR
•
Internal Two-wire Serial Control Bus I
•
Single-end Integrator with Programmable Gain
Control
• Multiplexed Analog Digitization with 12-bit
Resolution Scan SAR ADCs and Its Dedicated
2X to 8X Accumulator XSRAM Buffers
Aug. 2013 Rev. 1. 0 BCD Semiconductor Manufacturing Limited
QFN-5×5-40
2
C
Figure 1. Package Types of AP386X
Features (Continued)
• Single Cycle 8051 CPU Core, Maximum Opera-
ting Clock up to 28MHz from IOSC (Zero Wait
State)
4 to 28MHz Internal Oscillator (IOSC)
32k-byte Flash ROM
6k-byte Internal SRAM
T wo 16-bit Timers T0/T1
Configurable I
Controller Shared with the Same Ports
With Asynchronous I
Detection Logic Design
4 General Purpose GPIO Pins
One External Interrupt Pin
• ISP/IAP via I²C Port
• Operation Temperature Range: -40°C to 85°C
• Package Type Alternatives: QFN-5×5-40 and
QFN-6×6-48
• RoHS Compliance
•
Operating Mode:
Mode Description
Power-down No scan with power-down mode
Idle While only 8051 CPU core is idle,
Standard Higher scan rate when fingers are
2
C Slave Controller and SPI Slave
2
C Slave Address
all peripherals remain active
on panel, IOSC can up to 4MHz
to 28MHz
Applications
• Mobile Phones
• Personal Digital Assistants
• Smart Hand-held or Gaming Devices
1
QFN-6×6-48
Preliminary Datasheet
Superior Multi-touch Capacitive Touch Screen Controller AP386X
Pin Configuration
FN Package
(QFN-5×5-40)
Pin 1 Mark
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D16
1
2
3
4
5
6
7
8
9
10
11 12
D5
S9
S8
13
D4
D3
S6
S7
15
14
D2
S4
S5
353637383940
16 17 18 19
D1
D0
S3
3334
41
VDD3V
VDDHV
S2
32
VSS
S1
31
20
VDD18
30
VDD3V
S0
29
28
INT/GPIO1
WAKE/GPIO0
27
26
RSTN
MISO/GPIO2
25
24
MOSI/SDA
23
SCK/GPIO3
SS/SCL
22
21
TESTEN
Figure 2. Pin Configuration of AP3860 (Top View)
Aug. 2013 Rev. 1. 0 BCD Semiconductor Manufacturing Limited
2
Preliminary Datasheet
Superior Multi-touch Capacitive Touch Screen Controller AP386X
Pin Configuration (Continued)
FN Package
(QFN-6×6-48)
D22
D9
S11
D8
S10
D7
S9
D6
S8
D5
S7
D4
S6
D3
S5
D2
S4
D1
S3
D0
S2
S1
VDD3V
VDDHV
Figure 3. Pin Configuration of AP3861 (Top View)
Aug. 2013 Rev. 1. 0 BCD Semiconductor Manufacturing Limited
3
Preliminary Datasheet
Superior Multi-touch Capacitive Touch Screen Controller AP386X
Pin Description
Pin Number
QFN-5×5-40
AP3860
QFN-6×6-48
AP3861
Pin
Name
Pin
Type
Pin Function
40, 1 to 16 6 to 22
- 48, 1 to 5
D16 to
D0
D22 to
D17
I/O, A
I/O, A
17 23 VDDHV O
18, 30 24, 35 VDD3V P
19 25 VSS P
20 26 VDD18 O
21 27 TESTEN I
22 28 SS/SCL I/O
23 29
24 30
25 31
SCK/
GPIO3
MOSI/
SDA
MISO/
GPIO2
I/O
I/O
I/O
Driving Lines 16 to 0
These pins can also be configured as I/O
bi-directional ports for test
Driving Lines 22 to 17
These pins can also be configured as I/O
bi-directional ports for test
High Voltage. 6V
Charge pump high Voltage. This output pin can be
configured as VDD3V or 6V accordingly
Supply Voltage. 2.8V to 3.6V
A good decoupling capacitor between VDD3V and
VSS pins is critical for good performance
Ground Voltage. 0V
Internal Regulator Output. 1. 6V to 2.0V
Typical decoupling capacitors of 0.1F and 10F
should be connected between VDD18 and VSS
Test Mode Enable High Active
This pin has an internal weakly pull low resistor
connected. If it is connected high, the chip enters into
Test Mode condition
SS/SCL
This pin can be configured as the SCL signal of the
I
2
C master or I2C slave controller. When I2C is
enabled, the pin is configured as an open-collector.
While in SPI mode, this pin is configured as the
slave chip select pin
Port 1.3 GPIO
8051 P1.3 GPIO. This pin can also be configured as
the serial clock from SPI master while SPI interface
is activated
SDA
This pin can be configured as the SDA signal of the
2
I
C master or I2C slave controller. In this operation
mode, this pin should also be configured as
open-collector. While SPI interface is selected, the
pin serves as the data port from SPI master to SPI
slave
Port 1.2 GPIO
8051 P1.2 GPIO. This pin can also be configured as
the output data pin from slave to master for SPI
interface
Aug. 2013 Rev. 1. 0 BCD Semiconductor Manufacturing Limited
4
Preliminary Datasheet
Superior Multi-touch Capacitive Touch Screen Controller AP386X
Pin Description (Continued)
Pin Number
QFN-5×5-40
AP3860
QFN-6×6-48
AP3861
Pin
Name
Pin
Type
Pin Function
Reset Low Active
Typically connect a resistor to VDD3V and a
26 32 RSTN I
capacitor to VSS. Low asserted and threshold at
0.5*V
. When forced low, the chip enters into reset
DD
condition. This pin should not be connected to any
27 33
28 34
WAKE/
GPIO0
INT/
GPIO1
I/O
I/O
level above V
Port 1.0 GPIO
8051 P1.0 GPIO. This pin can also be configured as
the wakeup pin from the host
Port 1.1 GPIO
8051 P1.1 GPIO. Open Drain output. This pin can
also be configured as the interrupt pin to notify the
host
DD
Sensing Lines 0 to 9
29, 31 to 39 36 to 45 S0 to S9 I/O, A
These pins can also be configured as I/O
bi-directional ports for test
Sensing Lines 10 to 11
- 46, 47 S10, S11 I/O, A
These pins can also be configured as I/O
bi-directional ports for test
41 49 EP
Exposed Pad
“I/O” means input/output; “I” means input; “O” means Output; “P” means power; “A” means analog.
SCL and SDA Pin Description
Pull-up Enable
The pull-up enable for SCL and SDA is activated for AP386X, meaning that AP38 6X always has pull-up SCL
and SDA to VDD3V. During reset, SCL and SDA are as input pin. Moreover, if the pin connecting to the system
is floating, the internal pull-up will tie the pin to VDD3V (10k). After AP386X is reset, SCL and SDA are
input until its corresponding register is configured.
Mode Selection
SCL and SDA can be used in I
open drain pin) by register setting.
Wakeup
SCL and SDA can be used for wakeup input signals in different mode. While I
protocol (SDA is low and SCL is high) on SCL and SDA is a wakeup signal to AP386X. While SPI mode is
enabled, an active low on the pin of SCL (serving as a slave select in SPI) is a wakeup signal to AP386X.
Moreover, a wakeup signal can be asserted by host from GPIO0.
INT/GPIO1
GPIO1 can be configured as open-drain or push-pull mode. Furthermore, GPIO1 pin has internal pull-up to
VDD3V (60k) or VDD18 (10k) based on different register definition.
2
C and SPI mode. AP386X can enable I2C mode (SCL and SDA configured as
2
C mode is enabled, a START
Aug. 2013 Rev. 1. 0 BCD Semiconductor Manufacturing Limited
5
Loading...