16-11, YUSHIMA 3-CHOME, BUNKYO-KU, TOKYO 113-0034 JAPAN
X0172V.02 DE/CDM 0309
SAFETY PRECAUTIONS
The following check should be performed for the continued protection of the customer and service technician.
LEAKAGE CURRENT CHECK
Before returning the unit to the customer, make sure you make either (1) a leakage current check or (2) a line to chassis
resistance check. If the leakage current exceeds 0.5 milliamps, or if the resistance from chassis to either side of the
power cord is less than 460 kohms, the unit is defective.
500V
1M
2AVR-1404/484
(1)
(2)
(1)
(2)
2
DISASSEMBLY
(Follow the procedure below in reverse order when reassembling.)
1. Top Cover
(1) Remove 6 screws ① and 3 screws ② , detach the Top cover in the arrow direction.
Top Cover
1
3AVR-1404/484
2
1
2. Front Panel
(1) Remove 4 screws ③ and 2 screws ④ .
(2) Detach the Front Panel in the arrow direction.
4
Front Panel
3. Rear Panel
(1) Remove cord bushing ⑤ from the Rear Panel.
(2) Remove 30 screws ⑥ .
(3) Detach the Rear Panel in the arrow direction.
3
5
Rear Panel
6
6
3
LEVEL DIAGRAMS (1/2)
4AVR-1404/484
DIGITAL
CD IN
6CH IN
40dB
30dB
20dB
10dB
6CH IN (200mV)
-
-
0dB
10dB
20dB
6CH IN
CD IN
INPUT
BUFFER
AMP
FRONT
-
12dB
/
D IN
A
REV AMP
A
/
D IN
REV AMP
-
-
-
0dBFS
10dBFS
20dBFS
30dBFS
M62446
ELECTRIC
VOLUME
-
18dB
PRE AMP
MUTE
15.5dB
VOL 00
POWER AMP
25.5dB
-
35.5dB
ATT
SPK OUT
FRONT
/
P OUT
H
SPK OUT
FRONT
2.83V
/
8ohm)
(1W
/
P OUT
H
47mV
(0.27W 8ohm)
/
A OUT
D
LPF
HPF
DIR
A
/
D
A
/
D
DSP
-
10dBFS
-
20dBFS
-
30dBFS
D
0dBFS
/
A
MUTE
D
/
A
6dB
/
A OUT
D
100mV REF
REV AMP
SW SUM
REV AMP
SUM S
TONE
/
W
6CH IN
6CH IN
40dB
30dB
20dB
10dB
(200mV)
-
-
0dB
10dB
20dB
CENTER
SURROUND
DSP OUT
-
10dBFS
-
20dBFS
-
30dBFS
D
0dBFS
/
A
M62446
MUTE
25.5dB
-
18dB
VOL 00
15.5dB
D
/
A
D
/
A OUT
100mV REF
MUTE
6dB
SPK OUT
CENTER
SURROUND
SPK OUT
2.83V
(1W
/
8ohm)
4
LEVEL DIAGRAMS (2/2)
5AVR-1404/484
SUB_WOOFER
6CH INPUT
(200mV)
6CH IN
(112mV)
-
18dB
ELECTRIC
VOLUME
M62446
VOL 00
PRE AMP
25.5
(
15.5+5+5)dB
MUTE
SUB WOOFER
PRE OUT
SUB WOOFER
PRE OUT
150mV
/
A OUT
D
LPF
D
/
-
10dBFS
-
-
-
-
35dBFS
0dBFS
20dBFS
25dBFS
30dBFS
A
MUTE
/
A
D
/
A Out
Front D
200mV ref
LFE
LFE
6dB
6dB
DSP OUT
30dB
20dB
10dB
0dB
-
5dB
-
10dB
-
20dB
-
30dB
Config2
Config1
REV AMP
SW SUM
REV AMP
TO FRONT CH
10.5dB
5dB
5
BLOCK DIAGRAM
6AVR-1404/484
6
ADJUSTMENT
Tuner Section
CONNECTION DIAGRAM OF MEASURING INSTRUMENTS
FM
T402 T403
R471
IC402
7AVR-1404/484
STEREO
MODULATOR
VR402
TUNER B'D
FM ALIGNMENT
Alignment
Step
AM
Item
Center
1
Adjustment
2Distortion
3Repeat Steps 1 and 2
4Signal Level
Tuning
Frequency
Setting
98.1MHz
(98.0MHz)
98.1MHz
(98.0MHz)
98.1MHz
(98.0MHz)
TypeFrequency
FM SSG 98.1MHz60dBP
FM SSG 98.1MHz60dBP
FM SSG 98.1MHz20dBPOFF
InputOutputAdjustment
Input
Level
Modulation CouplingTypeConnect toPointsAdjust to
Mono
1kHz 100%
Mono
1kHz 100%
75ohm
Antenna
Terminal
Antenna
Terminal
Antenna
Terminal
FM SSG
Digital
Voltmeter
Digital
Voltmeter
Distortion
Meter
Light “TUNED” on
Terminal (L)
FL Display
R471T402r 50mV
Output
T403
VR402
Minimum
Distortion
+14
20
−10
dB
AM ALIGNMENT
Step
1Signal Level
Alignment
Item
FrequencyInput
999 (1000)
kHz
AM SSGVR401
T402 T403
R471
IC402
VR401
TUNER B’D
OutputAdjustment
TypeConnect toPointsAdjust to
Light “TUNED” on
7
FL Display
Remarks
SSG OUTPUT
74dBP (EMF)
Audio Section
Idling Current
Required measurement equipment : DC Voltmeter
Preparation
(1) Avoid direct blow from an air conditioner or an electric fan, and adjust the unit at normal room tempereture
15 °C ~ 30 °C (59 °F ~ 86 °F).
(2) Presetting
● POWER (Power sourse switch)→ OFF
● SPEAKER (Speaker terminal)→ No load (Do not connect speaker, dummy resistor, etc.)
Adjustment
(1) Remove top cover and set VR101, VR102, VR103, VR104, VR105 on Amp. Unit at full counterclockwise ( )
position.
(2) Connect DC Voltmeter to test points (FRONT-Lch: TP104, FRONT-Rch: TP105, CENTER ch: TP103,
SURROUND-Lch: TP101, SURROUND-Rch: TP102).
(3) Connect power cord to AC Line, and turn power switch "ON".
1VD1Digital positive supply
2DGND1Digital supply ground
3AUDATA3, XMT958SPDIF transmitter output, Digital audio output 3
4WR, DS, EMWR, GPIO10Host write strobe or host data strobe or external memory write enable or general purpose input & output number 10
5RD, R/W, EMOE, GPIO11
Host parallel output enable or host parallel R/W or external memory output enable or general purpose input & output number11
6A1, SCDINHost address bit one or SPI serial control data input
7A0, SCCLKHost parallel address bit zero or serial control port clock
8DATA7, EMAD7, GPIO7
9DATA6, EMAD6, GPIO6
10DATA5, EMAD5, GPIO5
11DATA4, EMAD4, GPIO4
12VD2Digital positive supply
13DGND2Digital supply ground
14DATA3, EMAD3, GPIO3
15DATA2, EMAD2, GPIO2
16DATA1, EMAD1, GPIO1
17DATA0, EMAD0, GPIO0
18CSHost parallel chip select, host serial SPI chip select
19SCDIO, SCDOUT, PSEL, GPIO9Serial control port data input and output, parallel port type select
20INTREQ, ABOOTControl port interrupt request, automatic boot enable
21EXTMEM, GPIO8External memory chip select or general purpose input & output number 8
22SDATAN1PCM audio data input number one
23VD3Digital positive supply
24DGND3Digital supply ground
25SCLKN1, STCCLK2PCM audio input bit clock
26LRCLKN1PCM audio input sample rate clock
27CMPDAT, SDATAN2, RCV958PCM audio data input number two
28CMPCLK, SCLKN2PCM audio input bit clock
29CMPREQ, LRCLKN2PCM audio input sample rate clock
30CLKINMaster clock input
31CLKSELDSP clock select
32FILT2Phase locked loop filter
33FILT1Phase locked loop filter
34VAAnalog positive supply
35AGNDAnalog supply ground
36RESETMaster reset input
37DDReserved
38DCReserved
39AUDATA2Digital audio output 2
40AUDATA1Digital audio output 1
41AUDATA0Digital audio output 0
42LRCLKAudio output sample rate clock
43SCLKAudio output bit clock
44MCLKAudio master clock
12
LC89055W (IC810)
LC89055W Terminal Function
Pin
No.
1DISELIData input terminal (select input pin of DIN0, DIN1)
2DOUTOInput bi-phase data through output terminal
3DIN0IAmp built-in coaxial/optical input correspond data input terminal
4DIN1IAmp built-in coaxial/optical input correspond data input terminal
5DIN2IOptical input correspond data input terminal
6DGNDDigital GND
7DVDDDigital power supply
8RIVCO gain control input terminal
9VINIVCO free-run frequency setting input terminal
10 LPFOPLL loop filter setting terminal
11 AVDDAnalog power supply
12 AGNDAnalog GND
13 CKOUTOClock output terminal (256fs, 384fs, 512fs, X’tal osc., VCO free-run osc.)
14 BCKO64fs clock output terminal
15 LRCKOfs clock output terminal (L: Rch, H: Lch, I2S: Reverse)
16 DATAOOData output terminal
17 XSTATEOInput data detecting result output terminal
18 DGNDDigital GND
19 DVDDDigital power supply
20 XMCKOX’tal osc. clock output terminal (24.576MHz or 12.288MHz)
21 XOUTOX’tal osc. connection output terminal
22 XINIX’tal osc. connection input terminal, external signal input possible (24.576MHz or 12.288MHz)
23 EMPHAOEmphasis information output terminal of channel status
24 AUDIOOBit1 output terminal of channel status
25 CSFLAGOTop 40bit revise flag output terminal of channel status
26 F0/P0/C0OInput fs cal. sig. out/data type out/input word inf. output terminal
27 F1/P1/C1OInput fs cal. sig. out/data type out/input word inf. output terminal
28 F2/P2/C2OInput fs cal. sig. out/data type out/input word inf. output terminal
29 VF/P3/C3OValidity flag out/data type out/input word inf. output terminal
30 DVDDDigital power supply
31 DGNDDigital GND
32 AUTOONon PCM burst data transfer detect sig. output terminal
33 BPSYNCONon PCM burst data preamble Pa, Pb, Pc, Pd sync sig. output terminal
34 ERROROPLL lock error, data error flag output terminal
35 DOO CPU/IFD read data output terminal
36 DIICPU I/F write data input terminal
37 CEICPU I/F chip enable input terminal
38 CLICPU I/F chip enable input terminal
39 XSELIFrequency select input pin of XIN X’tal osc. (24.576MHz or 12.288MHz)
40 MODE0IMode setting input terminal
41 MODE1IMode setting input terminal
42 DGNDDigital GND
43 DVDDDigital power supply
44 DOSEL0IData output format select input terminal
45 DOSEL1IData output format select input terminal
46 CKSEL0IOutput clock select input terminal
47 CKSEL1IOutput clock select input terminal
48 XMODEIReset input terminal
For latch-up countermeasure, set digital (DVDD) and analog (AVDD) power on/off in the same timing.
Pin NameFunctionI/O
13AVR-1404/484
13
AK4527BVQ (IC813)
L0OP1
L0OP0/SDA/CDTI
444342
DIF1/SCL/CCLK
DIF0/CSN
P/S
MCLK
39
38
40
41
DZF1
37
AVSS
36
AVDD
35
VCOM
VREFH
34
14AVR-1404/484
22
CAD1
CAD0
33
DZ F2/OVF
32
RIN+
31
RIN–
30
LIN+
29
LIN–
28
ROUT1
27
LOUT1
26
ROUT2
25
LOUT2
24
ROUT3
23
LOUT3
SDOS
I2C
SMUTE
BICK
LRCK
SDTI1
SDTI2
SDTI3
SDTO
DAUX
DFS
1
2
3
4
5
6
7
8
9
10
11
12
13 14
NC
AK4527BVQ
15
TVDD
DZ FE
Top View
16 17 18
PDN
DVSS
DVDD
192021
NC
TST
ADIF
AK4527BVQ Terminal Function
Pin
Pin Name I/OFunction
No.
1SDOSI SDTO source select pin, L: Internal ADC output, H: DAUX input
2I2CI Serial control mode select pin, L: 3-core serial, H: I2C bus
3SMUTEI Soft mute pin, H: Soft mute start, L: Release
4BICKI Audio serial data clock pin
5LRCKI Input channel clock pin
6SDTI1I DAC1 audio serial data input pin
7SDTI2I DAC2 audio serial data input pin
8SDTI3I DAC3 audio serial data input pin
9SDTOO Audio serial data output pin
10 DAUXI Auxiliary audio serial data input pin
11 DFSI Double speed sampling mode pin, L: Normal, H: Double
12 NC No Connect, No internal bonding
13 DZFEI Zero input detect enable pin
14 TVDD Power pin for output buffer, 2.7V~5.5V
15 DVDD Digital power pin, 4.5V~5.5V
16 DVss Digital GND pin, 0V
17 PDNI Power down & reset pin, L: Powered-down and register initialized, Reset with PDN when switching P/S or CAD0-1
18 TSTI Test pin, connected to DVSS
19 NC No Connect, No internal bonding
20 ADIFI Analog Input Format Select pin
21 CAD1I Chip address-1 pin
22 CAD0I Chip address-0 pin
23 LOUT3O DAC3L channel analog out pin
24 ROUT3O DAC3R channel analog out pin
25 LOUT2O DAC2L channel analog out pin
26 ROUT2O DAC2R channel analog out pin
27 LOUT1O DAC1L channel analog out pin
28 ROUT1O DAC1R channel analog out pin
29 LIN-I L-ch analog inverted input pin
30 LIN+I L-ch analog non-inverted input pin
31 RIN-I R-ch analog inverted input pin
32 RIN+I R-ch analog non-inverted input pin
33 DZF2/OVFO 0 input detect 2 pin/Analog input overflow detect pin
34 VCOMO Common V-out pin, AVDD/2, connect large capacitor to avoid noise
35 VREFHI Ref. V input pin, AVDD
36 AVDD Analog GND pin, 4.5V~5.5V
37 AVss Analog GND pin, 0V
38 DZF1O 0 input detect pin, H: Input data of G1 is 8192 times “0” in a raw or RSTN bit “0”
39 MCLKI Master clock input pin
40 P/SI Parallel/Serial select pin, L: Serial control
DIF0I Audio data I/F format 0 pin (parallel control)
41
CSNI Chip select pin (3-wire serial control), connect to DVDD when I
DIFII Audio data I/F format 1 pin (parallel control)
42
SCL/CCLKI Control data clock pin (serial control), I
LOOP0I Loop back mode 0 pin (parallel control), effects digital loop back ADC to all DAC
43
SDA/CDTII/O Control data input pin (serial control), I
H = H I G H v o l t a g e l e v e l
L = L O W v o l t a g e l e v e l
X = d o n ' t c a r e
= L O W - t o - H I G H c l o c k t r a n s i t i o n
= H I G H - t o - L O W c l o c k t r a n s i t i o n