Dell R910, R810, M910 User Manual
Dell PowerEdge 11th
Generation Servers: R810,
R910, and M910 Memory
Guidance
A Dell Technical White Paper
Dell │Product Group
Armando Acosta and James Pledge
PowerEdge 11th Generation Servers: R810, R910, and M910 Memory Guidance
THIS WHITE PAPER IS FOR INFORMATIONAL PURPOSES ONLY, AND MAY CONTAIN TYPOGRAPHICAL
ERRORS AND TECHNICAL INACCURACIES. THE CONTENT IS PROVIDED AS IS, WITHOUT EXPRESS OR
IMPLIED WARRANTIES OF ANY KIND.
© 2010 Dell Inc. All rights reserved. Reproduction of this material in any manner whatsoever without
the express written permission of Del l Inc. is strictly forbidden. For more information, contact Dell.
Dell, the DELL logo, and PowerEdge are trademarks of Dell Inc. Intel and Xeon are registered
trademarks of Intel Corporation in the U.S. and other countries. Other trademarks and trade names
may be used in this document to re f e r to either the entities claiming the marks and names or their
products. Dell Inc. disclaims any proprietary interest in trademarks and trade names other than its
own.
March 2010
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PowerEdge 11th Generation Servers: R810, R910, and M910 Memory Guidance
Contents
Introduction ........................................................................................................... 2
Quick Reference Guide (Terminology Definition s) .............................................................. 2
Overview Intel Architecture ........................................................................................ 3
PowerEdge R810 and M910 .......................................................................................... 4
FlexMem Bridge Technology ........................................................................................ 4
PowerEdge R910 ...................................................................................................... 6
Optimizing Memory Performance for Intel Xeon 7500 and 6500 Series Processors ........................ 7
Best Performance .............................................................................................. 7
Better Performance ........................................................................................... 7
Good Performance ............................................................................................. 8
Memory RAS Features ............................................................................................... 13
Sparing ............................................................................................................. 13
Mirroring ........................................................................................................... 14
Tables
Table 1. Quick Reference R810, R910, and M910 Memory Guide ............................................ 3
Table 2. Quick Comparison Intel Xeon 5500-5600 Series to Intel Xeon 7500-6500 ....................... 3
Table 3. Intel Xeon 7500/6500 Series Processor Performance and Max Memory Speed ................ 17
Figures
Figure 1. FlexMem Bridge Illustration ............................................................................ 5
Figure 2. R810 and M910 Series Servers Memor y Illustration ................................................. 6
Figure 3. R910 Series Servers Memor y Illustration .............................................................. 7
Figure 4. R910 Relative Memory Bandwid t h for the Intel Xeon 7500 Series P r ocessors .................. 8
Figure 5. M910/R810 Relative Memory Band width for the Intel Xeon 6500 and 7500 Series Processors 9
Figure 6. R910 With 64 Identical DIMMs, 2 DIMMs Per Channel .............................................. 10
Figure 7. R810 or M910 With 32 Identical DIMMs, 2 DIMMs Per Channel ................................... 11
Figure 8. R910 With 32 Identical DIMMs, 1 DIMM Per Channel ............................................... 12
Figure 9. R810 and M910 With 16 Identical DIMMs, 1 DIMM Per Channel ................................... 13
Figure 10. Example of Sparing for Dual R an k and Quad Rank DIMMs ...................................... 14
Figure 11. Example of R910 Intra-Socket Mir r oring .......................................................... 15
Figure 12. Example of R810 and M910 Intra-Node Mirroring ............................................... 16
Figure 13. Example of R810 and M910 Inter-Socket Mirroring ............................................. 17
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PowerEdge 11th Generation Servers: R810, R910, and M910 Memory Guidance
Introduction
This paper serves as memory gu id ance for Dell™ 11th Generation PowerEdge™ R810, R910, and M910
servers released March 2010 using the new Intel® Xeon® 7500 and 6500 series processors that support
DDR3 memory technology. This document explains what De ll supports and describes rules for installing
memory. Examples of terminology definitions and details about perfo rm ance or Reliability, Availability,
and Serviceability (RAS) features are shown as follows.
Quick Reference Guide (Terminology D ef in itions)
DDR3 (Double Data Rate): The latest (3rd) generation of DDR DRAM; replaces DDR and DDR2 memory.
DIMM: Dual Inline Memory Module. This is the memory stick that is installed in each memory slot. It is
comprised of multiple memory chips and, in some cases, registers, buffers and/or temperature sensors.
Dual Rank (DR): Two rows of DRAM comprising 64 bits of d ata each.
ECC (Error Checking and Correcting): This memory coding method is able to correct and identify
certain types of DRAM and interface errors.
Enhanced ECC: Like ECC, but this memory coding method protects against additi onal memory error
types including control line errors.
Hemisphere Mode: This mode allows interleaving between a processor’s two memory controllers
leading to improved perfo r mance. Interleaving also adds benefits to memory thermal pe rformance by
spreading memory accesses across mul ti pl e DIM Ms and reducing memory “hot spots.”
Lock-step: Pairs of DIMMs are accessed as a single double-wide (128-data bit) DIMM, allowing more
powerful error-correction codes to be used, including detecting address errors.
MC: Memory Controller
Intel 7500 Scalable Memory Buffer: Translates one Scalable Memory Interconnect (SMI) bus into two
DDR3 buses. Intel Xeon 7500 and 6500 series proce ssors must have this device to operate.
Mirror Mode (Mirroring): Two memory controllers are configured to allow the same data to be written
to each. Each controller’s data is identical to the other; thus, if one fails or has multiple bit errors,
there is a backup. The operating system will report half of your installed memory.
Quad Rank (QR): Four rows of DRAM comprising 64 bits of data each.
Rank: A row of DRAM devices compri sing 64 bits of data per DIMM.
RAS: Reliability, Availability, and Serviceability
SDDC: Single Device Data Correction. Memory systems that utilize Single Device Data Correction can
detect and correct multiple bit errors that come from a single memo r y chip on the DIMM.
Single Rank (SR): One row of DRAM comprising 64 bits of data.
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PowerEdge 11th Generation Servers: R810, R910, and M910 Memory Guidance
DIMM Feature
Combine
Rules
Mixed Capacity
Yes
DIMMs must match (capacity, rank) across channels. For exampl e, a
Mixed Speeds
Mixed Vendors
Yes
Any Dell-sourced DDR3 DIMMs are supported , regardless of vendor or
Feature
Intel Xeon 5500-5600 Series
Intel Xeon 7500-6500 Series
DIMM Type
DDR3 (UDIMM or RDIMM)
DDR3 (RDIMM only)
DIMM Rank
DR, SR, or QR
DR, SR, or QR
All Memory channels operate at
Memory controllers per socket
Memory Channels per socket
3
4/8
Maximum DIMMs per channel
DIMM Speed
1333 MTs (1 and 2 DPC)
1066 MTs (1 or 2 DPC)
Sparing (DIMM and Rank): The system allocates a Rank or DIMM per channel as a Spare memory region,
and is able to move a Rank or DIM M exhibiting correctable errors to the Spare while the operating
system is running.
RDIMM: Registered DIMMs. Address, Control, and Clock lines are buffered and re-driven on the DIMM.
Overview Intel Architecture
PowerEdge 11Th Generation 4-socket servers use the new Intel Xeon 7500 and 6500 series processors
that support DDR3 memory technology. Each processor has two memory cont rollers that support two
Millbrook Memory Buffers. Every Millbrook Memory Buffer sup p or ts up to four DIMMs, which allows for
greater scalability and memor y performance.
It is important to recognize that memory speed and the processor chosen have interdependencies. The
processor’s maximum QuickPath Interconnect (QPI) speed will determine the memory performance
(1066 MTS, 978 MTS, or 800 MTs). Memory speed remains locked regardless of DIMM population. There
is no speed change when populating increasing numbers of DIMMs. However, there are recommended
population practices when up gr ading or changing memory. DIMMs always must be populated identically
in pairs (A1-A2, for example).
Table 1. Quick Reference R810, R910, and M910 Memory Guide
Mixed Ranks Yes DIMMs of different Ranks can be mixe d . The first slot of each
channel populated (first two white tab DIMM slots on each memory
buffer: A1, A2, A3, and A4) must be populated with the highest
ranked DIMM.
1 GB RDIMM in A1 and A2 implies that A3 and A4 would need to be 1
GB RDIMMs also. DIMM slots A5, A6, A7, and A8 could be a different
capacity and rank.
Yes Nehalem EX Architecture will support a maximum memory spee d of
1066 MTs.
vendor mix. Where possible, Dell recommends using the same DIMM
manufacturer.
Note: Only RDIMMS are supported with Intel 7500 and 6500 series processors.
Table 2. Quick Comparison Intel Xeon 5500-5600 Series to Intel Xeon 7500-6500
Yes Yes
the same frequency
1 2
3 2
(Speed shown is for top
bin…may be slower for down-
1066 MTs (2 DPC)
800 MTs (3 DPC)
(4 SMI Buses/8 DDR3 Channels)
(Same speed for SR, DR, or QR
DIMMs)
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PowerEdge 11th Generation Servers: R810, R910, and M910 Memory Guidance
bin SKUs)
(Slower with QR DIMMs)
Minimum memory populat ion
Hemisphere Mode
No
Yes
Memory RAS Features
1 DIMM 2 DIMMs
(must populate with identical
DIMM pairs)
ECC, DIMM Sparing, Lock-step,
Mirroring, x4 or x8 SDDC
Enhanced ECC, DIMM sparing,
Lock-step, Mirroring, x4 or x8
SDDC, Rank sparing
PowerEdge R810 and M910
The R810 and M910 servers utilize DDR3 memory providing a high performance, high-speed memory
interface capable of low latency response and high throughput. The R810 and M910 support Registered
DDR3 DIMMs (RDIMMs) only.
The R810 and M910 utilize Intel Xeon 7500 and 6500 series processors that have four SMI channels for
each socket. Each of those memory controllers then has two SMI channels that connect to the Intel
7500 Scalable Memory Buffer.
The DDR3 memory interface consists of eight Intel 7500 Scalable Memory Buffers (two per socket), each
of which has two DDR3 memory chan nels. Each channel supports up to two RDIMMs for
single/dual/quad rank. By l imiting to two DIMMs per DDR channel, the system can support quad-rank
DIMMs at 1066 MTs. The R810 and M910 support a maximum of 32 DIMMS with four SMI channels per
socket, two Intel 7500 Scalable Memory Buffers per SMI channel, and two DDR3 channels per memory
buffer supporting two DIMMs each.
FlexMem Bridge Technology
In a four-CPU configuration, the R810 and M910 use only one memory controller per CPU. This single
controller connects to two memory buffers via SMI links. Each memory buffer in turn connects to four
DDR3 DIMMs with a total of 32 DIMMs accessible. In a two-CPU configuration, normally this would mean
that only four memory buffers are connected; therefore, a total of only 16 D IMMs are accessible.
To overcome this limitation w it h two CPUs, the R810 and M910 use a pass-through, called the FlexMem
Bridge, in the sockets without CPUs (CPU 3 and CPU 4). This allows CPU 1 and CPU 2 to connect to the
memory of their respective adjacent sockets (CPU 3 and CPU 4) and access the additional 16 DIMMs.
The FlexMem Bridge provides the following:
• Two pass-through links for SMI
• One pass-through link for QPI
• The pass-through SMI links connect the two installed CPUs to additional Intel 7500 Scalable
Memory Buffers; therefore, the CPUs will have the following memory attached:
• CPU 1 will have access to DIMMs A1-A8 and to DIMMs C1-C8 (those normally associate d with
CPU 3)
• CPU 2 will have access to DIMMs B1-B8 and to DIMMs D1-D8 (those normally associated with
CPU 4)
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