Dell Latitude G5 5587 Schematics

Vinafix.com

A

B

C

D

E

MODEL NAME :

PCB NO :

BOM P/N :

1 1

LA-E993P

Firestar MLK/Firestar-B

451A9U31L01
451A9U31L02
451A9U31L03
451A9U31L04

DDK51 - Firestar MLK / DDK52 - Firestar-B / DDK53 - Armani MLK

Armani MLK:

451A9U31L51
451A9U31L52
451A9U31L53
451A9U31L54

Dell/Compal Confidential

2 2

Schematic Document

Coffee Lake-H

N17P

Firestar-B, Firestar/Armani MLK

3 3

2018-03-06

Rev: 1.0 (A00)

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2017/01/06 2018/01/06

2017/01/06 2018/01/06

2017/01/06 2018/01/06

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Page

Cover Page

Cover Page

LA-E993P

LA-E993P

LA-E993P

E

1.0(A00)

1.0(A00)

1 78Tuesday, March 06, 2018

1 78Tuesday, March 06, 2018

1 78Tuesday, March 06, 2018

1.0(A00)

Vinafix.com

A

128M x32 *4 =2G
256M x32 *4 =4G

VRAM * 4
GDDR5

P28-29

HDMI 2.0

1 1

Conn.

HDMI2.0

P34

Retimer
PS8409A

P33

IFP

B

GPU
N17P-G0/G1

GB4-128

P23-31

PEG 3.0 x16

C

Intel

CFL-Lake-H

DDR4 ChannelA
DDR4 ChannelB

D

DDRIV-DIMM X2

1.2V DDR4 2666 MHz

P14-15

32GB Max

E

Processor

45W

BGA

DMI x4

100MHz
5GB/s

Intel

CNL-H-PCH

BGA 874 Balls

P6-12

P36~37P50

PCI-E x1

CNVi

PCI-E x1

Port 14

PCI-E x4

Port 9-Port 12

SATA1A

DDI1 x4
DDI2 x4

PCI-E x4

Port 21-Port 24

Port 15

CRT
Conn.

P35

DP to VGA
RTD2166-CG

CIO/USB3.1

USB3.1
TypeC

2 2

P50

USB2.0/CC

TPS65982D

RJ45

P38

I2C/USB2.0

DP

Thunderbolt
Alpine Ridge-SP

M.2 Slot A Key-E

(WLAN+BT4.0)

LOM
Killer E2400

M.2 Slot C Key-M

(SATA/PCIe SSD)

P41

P40P40

P39

HM370

HDD
Conn.

P39

Main SPKR *2

Universal
Audio Jack

3 3

P43

P43

HDA Codec
ALC3246

SPI Flash
(BIOS 32MB)

TPM
NPCT750JAAYX

P42

P14

P45

SATA0B

HD Audio

SPI

SMBus

I2C

P16-22

eDP1.4 x4

USB2.0

Port 1

USB3.0

Port 1

USB Powershare
TPS2544

USB 3.0 Re-driver
PS8713

USB2.0
USB3.0

USB2.0
USB3.0

USB2.0

USB2.0

USB2.0 SD3.0

Port 6

Card Reader 2 in 1
RTS5144-GR SD / MS

USB2.0

15.6''
HD / FHD / UHD

P31

P31 P51

Port 2
Port 2

Port 3
Port 3

Port 5

Port 7

Port 8

P53 P53

Port 9

P38

USB 3.0

Type-A

USB 3.0

Type-A

USB 3.0

Type-A

Digital Camera
Conn.

M.2 Slot A Key-EUSB2.0

(WLAN+BT4.0)

Touch Panel
Conn.

Touch Finger Print w/ power button
Conn.

Power Button Board

Left

Right

P52

Right

P52

P35

P41

P35

P48

FFS
LNG2DMTR

4 4

P39

Touch Pad

LED

LED Board

Power Button

PS2

P47

P48

P48

Power Button Board

A

B

eSPI

MEC 1416

KBC

SMBus

Charger &
Battery

C

PWM

FAN

P47

I2C

P44

P59/P60 P59

Thermal Sensor
F75303M

KB Conn.

P46

AC Adaptor

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

P45

Compal Secret Data

Compal Secret Data

2017/01/06 2018/01/06

2017/01/06 2018/01/06

2017/01/06 2018/01/06

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Block diagram

Block diagram

Block diagram

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

E

LA-E993P

LA-E993P

LA-E993P

2 78Tuesday, March 06, 2018

2 78Tuesday, March 06, 2018

2 78Tuesday, March 06, 2018

1.0(A00)

1.0(A00)

1.0(A00)

Vinafix.com

5

Refer Page 44

Board ID

X00

X01

X02

D D

X03

A00

Resistor

10K

17.8K

27K

37.4K

49.9K

HSIO port Alloction

USB31DESTINATION

USB JUSB3 (Left Side)

USB JUSB1 (Right Side)

2

USB JUSB2 (Right Side)

3

4

None

5

None

6

None

4

PCI EXPRESS

Lane 1

Lane 2

Lane 3

Lane 4

Lane 5

Lane 6

Lane 7

Lane 8

DESTINATION

None

None

None

None

None

None

None

None

3

2

1

DESTINATIONUSB3

7

8

9

10

None

None

None

None

Lane 9

USB2 DESTINATION

USB JUSB3 (Left Side)

1

USB JUSB1 (Right Side)

2

USB JUSB2 (Right Side)

3

4

None

CAMERA

5

Card Reader

6

NGFF - WLAN + BT

7

8

C C

9

10

11

12

13

14

Touch screen

Finger Print

None

None

None

None

None

Lane 10

Lane 11

Lane 12

Lane 13

Lane 14

Lane 15

Lane 16

Lane 17

Lane 18

Lane 19

Lane 20

Lane 21

Lane 22

Lane 23

Lane 24

NGFF - NVMe SSD

None (HDD)

LOM

NGFF - WLAN

Alpine Ridge - SP

SATA

0a

1a

0b

1b

2

3None

4

5 None

DESTINATION

None (NVMe)

NGFF - SSD

HDD

None (LOM)

None (WLAN)

None

None

0

1

2

3

4

5

6

7

8

9

3

DESTINATIONCLK_REQ

None

None

LOM

NGFF - WLAN + BT

None

Alpine Ridge - SP

NGFF - SSD

GPU

None

None

None

None

None

None

None

None

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/01/06

2017/01/06

2017/01/06

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

2018/01/06

2018/01/06

2018/01/06

Symbol Note :

: means Digital Ground

: means Analog Ground

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Notes List

Notes List

Notes List

LA-E993P

LA-E993P

Tuesday, March 06, 2018

Tuesday, March 06, 2018

Tuesday, March 06, 2018

LA-E993P

1

3 78

3 78

3 78

1.0(A00)

1.0(A00)

1.0(A00)

DDI

B B

A A

5

1

2

3

DESTINATION

Alpine Ridge

Alpine Ridge

None

DESTINATIONCLK_PCIE

0

None

1

None

LOM

2

NGFF - WLAN + BT

3

4

None

Alpine Ridge - SP

5

NGFF - SSD

6

GPU

7

None

8

9

None

10

11

12

13

14

15

4

None

None

None

None

None

None

10

11

12

13

14

15

Vinafix.com

5

D D

C C

P59

ACIN Adapter

130W/180W

VIN

P60

Charger IC

TI BQ24780SRUYR

P59

B B

A A

5

(PU700)

BATT+

Battery

56W

B+

4

P71-74

NCP81215MNTXG

EN : VR_ON
PG : IMVP_VR_PG

P61

EN : 3V_5V_EN
PG : POK

P62

PU5000

NCP302045MN x4
(PU5101/PU5102/
PU5103/PU5202)

NCP302045MN x1

(PU5201)

NCP302035MNTXG x1

(PU5203)

AON7408L/AON7506

(PQ201/PQ202)

RT8207PGQW
PU200

EN 0.6V : SM_PG_CTRL
EN 1.2V : 1.2V_VDDQ_EN
PG : 1.2V_PGOOD

P76

SY8286RAC

(PU4000)

EN : VCCIO_EN
PG : +VCCIO_PG

P64

SY8286RAC

(PU100)

EN : PCH_PRIM_EN
PG : 1V_PG

P32

SI3457BDV-T1-E3

(QV11)

EN : SIO_SLP_S3#

TPS51285BRUKR
PU300

AON7380/AON6796

(PQ301/PQ302)

AON7380/AON6796

(PQ303/PQ304)

P65

SY8286RAC

(PU18V00)

EN : PCH_PRIM_EN
PG : PRIM_PWRGD_R

(PQ6000/PQ6001

PQ6002/PQ6003)
RT8816AGQW
PU6000

AON6992 x1

(PQ6200)

RT8816AGQW
PU6101

PJP800

EN : NVVDD_EN
PG : GPU_CORE_PG

EN : NVVDDS_EN
PG : NC

+1.35VS_B+

P67

P68

+VCC_CORE

+VCCGT

+VCCSA

+1.2VP

+1.2V_DDR

PJP201/PJP202

+0.6VSP

+0.6VS

PJP203

+VCCIOP

+VCCIO

PJP4001

+1VALWP

+1P05VALW

PJP12

+INV_PWR_SRC

+3VALWP

+3VALW

PJP33/PJP34

+5VALWP

+5VALW

PJP31/PJP32

+1.8VSP

+1.8V_PRIM

PJP18V2

+GPU_CORE

+GPU_CORE_VDDS

AON6962 x1

(PQ800)

RT8812AGQW-GP
PU800

EN : FBVDD_EN
PG : DGPU_PWROK

P69

B+

PL5100

CPU_B+

CPU_B+

CPU_B+

B+

B+

B+

PJP200

PJP400

PJP11

1.2V_B+

B+_VCCIO

+1V_B+

B+

B+

B+

B+

PL300
PL301

PJP18V1

PL6000

3/5V_B+

1.8V_B+

GPU_B+ AON6992 x4

GPU_B+

GPU_B+

4

3

APE8937GN2

(UZ16)

EN : SIO_SLP_S3#

RH123 +1P05V_VCCUSB

RH597 +1P05V_VCCPRIM_MPHY

RH598 +1P05V_VCCAMPHYPLL

RH600 +1P05V_SRC

RH603 +1P05V_VCCAPLL

RH602 +1P05V_BCLK

RH607 +1P05V_XTAL

RH614 +1P05V_XDP

TPS22961DNYR

(UZ15)

EN : VCCST_EN

TPS22961DNYR
(UZ9 Reserved)

EN : VCCSTG_EN

PJP25V1

EM5209VF

(UZ1)

EN : SIO_SLP_S3#

TPS22967DSGR

(UZ25)

EN : PCH_PRIM_EN

SY6288C20AAC

(UL2)

EN : LAN_EN

SY6288D20AAC

(UE4)

EN : TP_EN#

SY6288C20AAC

(UZ8)

EN : ENVDD

RT97 +3.3V_TBT_SX

RE12 +3VALW_EC

RE130 +DEBUG_PWR

RTPM10 +3V_TPM

RT53 +3VALW_PD

1.0VS_VGAP_VIN +1.0VS_VGAP

PJP10V1

TPS2544RTER

(US1)

EN : USB_POWERSHARE_VBUS_EN

SY6288D20AAC

(US2)

EN : USB_EN#

EM5209VF

(UZ1)

EN : SIO_SLP_S3#

APE8937GN2

(UZ24)

EN : DGPU_PWR_EN

APE8937GN2

(UZ17)

EN : 1V8_RUN_EN

RE15 +1.8VALW_EC

+1.35VS_VGAP

+1.35VS_VGA

PJP801/PJP802

3

P55

+1.2V_VCCPLL_OC

P55

P18

P18

P18

P18

P18

P18

P18

P20

P54

+VCCST

P54

P55

+VCCSTG

P55

P63

VIN_2.5V +2.5V_MEMP

RT9059GSP

(PU25V00)

EN : SIO_SLP_S4#
PG : 2.5V_PGOOD

P54

P54

P55

P40

P47

P54

P51

P52

P54

P31

P31

+3VS

P55

+3VALW_PCH

P40

+LAN_IO

P47

+3VS_TP

P54

+EDPVDD

P37

P44

P44

P45

P50

P66

RT8061AZQW

(PU10V00)

EN : NVVDDS_EN
PG : 1VS_GFX_PG

P51

+5V_CHGUSB_3

P51

+5V_CHGUSB_1

P54

+5VS

P31

+1.8V_GFX_AON

P31

+1.8V_GFX_RUN

P44

RZ119

PJP25V2

+2.5V_MEM

+1VS_GFX

2

RP31

RP28 +3V_RTM

RZ37 +3VS_CAM

RT124 +3VS_TBT

RVGA1 +AVCC33

RVGA2 +VDD_DAC_33

RZ36
RZ117

RA5 +3V_DVDD

RW4 +3V_FPSW

RI59 +3V_USBRD

P63

RI52 +3VS_CR

G9090-180T11U

(UA1)

EN : +3VS RC delay

RH121 +3V_ROM

RH604 +3V_PCH_SPI

RH605 +3V_PCH_DSW

LH1 +3V_HDA

RN2 +3VA_WLAN

P34

AP2330W-7

(UV17)

RZ26 +5VS_TS

DVGA1
FVGA1

RZ34 +5VS_HDD

P66PJP10V3

RA7
RA10

RA8 +5V_AVDD

F1 +5VS_KBL

RE104 +5VS_FAN1

RE105 +5VS_FAN2

P33

+1.2V_RTM

P33

P35

P37

P38

P38

P39

+3.3VDX_SSD

P42

P42

P50

P53

P42

+1.8V_DVDD

P14

P14

P14

P14

P41

P34

+VDISPLAY_VCC

P35

P38

+CRT_5V_OUT

P39

P42

+5V_PVDD

P42

P46

P47

P47

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATI ON IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATI ON IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE INFORMATI ON IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2015/09/01

2015/09/01

2015/09/01

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

1

Title

Title

Title

2016/09/01

2016/09/01

2016/09/01

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Power Map

Power Map

Power Map

LA-E993P

LA-E993P

LA-E993P

Tuesday, March 06, 2018

Tuesday, March 06, 2018

Tuesday, March 06, 2018

4 78

4 78

4 78

1.0(A00)

1.0(A00)

1.0(A00)

Vinafix.com

5

4

3

2

1

1K

D D

C C

B B

PCH

Host

AW44

BB43

AY44

BB39

Host

AR41

AR44

Slave

AW42

AW45

Address: 0x88/0x89

SMBCLK
SMBDATA

SML0_SMBCLK
SML0_SMBDATA

I2C1_SCK_TP
I2C1_SDA_TP

GPU_THM_SMBCLK
GPU_THM_SMBDAT

1K

499

499

2.2K

2.2K

5.1K(@)

+3VALW

+3VS

DMN65D8L

DMN65D8L

+3VALW

+3VS

+3VS

DMN65D8L

DMN65D8L

MEC1416

Host

Host

1K

1K

PCH_SMBCLK
PCH_SMBDATA

2.4K

2.4K

I2C1_SCK_TP_C
I2C1_SDA_TP_C

2.2K

2.2K

GPU_THM_SMBCLK
GPU_THM_SMBDAT

GPU_THM_SMBCLK
GPU_THM_SMBDAT

PBAT_CHG_SMBCLK
PBAT_CHG_SMBDAT

Host

+3VS

+3VS_TP

+3VALW_EC

+3VS

DMN65D8L

DMN65D8L

ALL_GPWRGD

DMN65D8L

DMN65D8L

4.7K

4.7K

2.2K

2.2K

Slave

DIMMA

Slave

DIMMB

Slave

FFS

Slave

RTD2166

Slave

Touch
Pad

Address: 0xA0/0xA1

Address: 0xA4/0xA5

Address: 0x52/0x53

Address: 0x64/0x65, 0x68/0x69

Address: 0x2C/0x2D

10K

10K

THM_SML1_CLK
THM_SML1_DATA

1.8K

1.8K

VGA_SMB_CK2
VGA_SMB_DA2

+3VALW_EC

Slave

BATT

Slave

CHAGER

+3VALW_EC

+3VS

Slave

Thermal
Sensor

Address: 0x9A/0x9B

+1.8V_GFX_AON

Slave

GPU

Address: 0x9E/0x9F

Address: 0x16/0x17

Address: 0x12/0x13

TYPEC_SMBCLK
TYPEC_SMBDA

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2017/01/06 2018/01/06

2017/01/06 2018/01/06

2017/01/06 2018/01/06

0 Ohm

0 Ohm

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

PD_I2C_SCL_R
PD_I2C_SDA_R

2

Slave

TPS65982D

Address: 0x70/0x71

Compal Electronics, Inc.

Title

Title

Title

SMBus Block Diagram

SMBus Block Diagram

SMBus Block Diagram

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

LA-E993P

LA-E993P

LA-E993P

1

5 78Tuesday, March 06, 2018

5 78Tuesday, March 06, 2018

5 78Tuesday, March 06, 2018

1.0(A00)

1.0(A00)

1.0(A00)

Vinafix.com

5

PEG_CTX_C_GRX_P[0..15]<23>

PEG_CTX_C_GRX_N[0..15]<23>

D D

C C

PEG_CRX_GTX_P[0..15]<23>

PEG_CRX_GTX_N[0..15]<23>

PEG_CTX_C_GRX_P[0..15]

PEG_CTX_C_GRX_N[0..15]

PEG_CRX_GTX_P[0..15]

PEG_CRX_GTX_N[0..15]

To PCH To PCH

4

CFL-H

PEG_CRX_GTX_P15
PEG_CRX_GTX_N15

PEG_CRX_GTX_P14
PEG_CRX_GTX_N14

PEG_CRX_GTX_P13
PEG_CRX_GTX_N13

PEG_CRX_GTX_P12
PEG_CRX_GTX_N12

PEG_CRX_GTX_P11
PEG_CRX_GTX_N11

PEG_CRX_GTX_P10
PEG_CRX_GTX_N10

PEG_CRX_GTX_P9
PEG_CRX_GTX_N9

PEG_CRX_GTX_P8
PEG_CRX_GTX_N8

PEG_CRX_GTX_P7
PEG_CRX_GTX_N7

PEG_CRX_GTX_P6
PEG_CRX_GTX_N6

PEG_CRX_GTX_P5
PEG_CRX_GTX_N5

PEG_CRX_GTX_P4
PEG_CRX_GTX_N4

PEG_CRX_GTX_P3
PEG_CRX_GTX_N3

PEG_CRX_GTX_P2
PEG_CRX_GTX_N2

PEG_CRX_GTX_P1
PEG_CRX_GTX_N1

PEG_CRX_GTX_P0

RH24

24.9_0402_1%

PEG_CRX_GTX_N0

PEG_RCOMP

DMI_CRX_PTX_P0
DMI_CRX_PTX_N0

DMI_CRX_PTX_P1
DMI_CRX_PTX_N1

DMI_CRX_PTX_P2
DMI_CRX_PTX_N2

DMI_CRX_PTX_P3
DMI_CRX_PTX_N3

+VCCIO

1 2

DMI_CRX_PTX_P0<16>
DMI_CRX_PTX_N0<16>

DMI_CRX_PTX_P1<16>
DMI_CRX_PTX_N1<16>

DMI_CRX_PTX_P2<16>
DMI_CRX_PTX_N2<16>

DMI_CRX_PTX_P3<16>
DMI_CRX_PTX_N3<16>

UH1C

E25
D25

E24
F24

E23
D23

E22
F22

E21
D21

E20
F20

E19
D19

E18
F18

D17
E17

F16
E16

D15
E15

F14
E14

D13
E13

F12
E12

D11
E11

F10
E10

G2

D8
E8

E6
F6

D5
E5

J8
J9

CFL-H_BGA1440

PEG_RXP_0
PEG_RXN_0

PEG_RXP_1
PEG_RXN_1

PEG_RXP_2
PEG_RXN_2

PEG_RXP_3
PEG_RXN_3

PEG_RXP_4
PEG_RXN_4

PEG_RXP_5
PEG_RXN_5

PEG_RXP_6
PEG_RXN_6

PEG_RXP_7
PEG_RXN_7

PEG_RXP_8
PEG_RXN_8

PEG_RXP_9
PEG_RXN_9

PEG_RXP_10
PEG_RXN_10

PEG_RXP_11
PEG_RXN_11

PEG_RXP_12
PEG_RXN_12

PEG_RXP_13
PEG_RXN_13

PEG_RXP_14
PEG_RXN_14

PEG_RXP_15
PEG_RXN_15

PEG_RCOMP

DMI_RXP_0
DMI_RXN_0

DMI_RXP_1
DMI_RXN_1

DMI_RXP_2
DMI_RXN_2

DMI_RXP_3
DMI_RXN_3

PEG_TXP_10
PEG_TXN_10

PEG_TXP_11
PEG_TXN_11

PEG_TXP_12
PEG_TXN_12

PEG_TXP_13
PEG_TXN_13

PEG_TXP_14
PEG_TXN_14

PEG_TXP_15
PEG_TXN_15

3 OF 13

PEG_TXP_0
PEG_TXN_0

PEG_TXP_1
PEG_TXN_1

PEG_TXP_2
PEG_TXN_2

PEG_TXP_3
PEG_TXN_3

PEG_TXP_4
PEG_TXN_4

PEG_TXP_5
PEG_TXN_5

PEG_TXP_6
PEG_TXN_6

PEG_TXP_7
PEG_TXN_7

PEG_TXP_8
PEG_TXN_8

PEG_TXP_9
PEG_TXN_9

DMI_TXP_0
DMI_TXN_0

DMI_TXP_1
DMI_TXN_1

DMI_TXP_2
DMI_TXN_2

DMI_TXP_3
DMI_TXN_3

@

3

B25
A25

B24
C24

B23
A23

B22
C22

B21
A21

B20
C20

B19
A19

B18
C18

A17
B17

C16
B16

A15
B15

C14
B14

A13
B13

C12
B12

A11
B11

C10
B10

B8
A8

C6
B6

B5
A5

D4
B4

PEG_CTX_GRX_P15
PEG_CTX_GRX_N15

PEG_CTX_GRX_P14
PEG_CTX_GRX_N14

PEG_CTX_GRX_P13
PEG_CTX_GRX_N13

PEG_CTX_GRX_P12
PEG_CTX_GRX_N12

PEG_CTX_GRX_P11
PEG_CTX_GRX_N11

PEG_CTX_GRX_P10
PEG_CTX_GRX_N10

PEG_CTX_GRX_P9
PEG_CTX_GRX_N9

PEG_CTX_GRX_P8
PEG_CTX_GRX_N8

PEG_CTX_GRX_P7
PEG_CTX_GRX_N7

PEG_CTX_GRX_P6
PEG_CTX_GRX_N6

PEG_CTX_GRX_P5
PEG_CTX_GRX_N5

PEG_CTX_GRX_P4
PEG_CTX_GRX_N4

PEG_CTX_GRX_P3
PEG_CTX_GRX_N3

PEG_CTX_GRX_P2
PEG_CTX_GRX_N2

PEG_CTX_GRX_P1
PEG_CTX_GRX_N1

PEG_CTX_GRX_P0
PEG_CTX_GRX_N0

DMI_CTX_PRX_P0
DMI_CTX_PRX_N0

DMI_CTX_PRX_P1
DMI_CTX_PRX_N1

DMI_CTX_PRX_P2
DMI_CTX_PRX_N2

DMI_CTX_PRX_P3
DMI_CTX_PRX_N3

1 2

CH5 0.22U_0201_6.3V6M

1 2

CH6 0.22U_0201_6.3V6M

1 2

CH7 0.22U_0201_6.3V6M

1 2

CH8 0.22U_0201_6.3V6M

1 2

CH9 0.22U_0201_6.3V6M

1 2

CH10 0.22U_0201_6.3V6M

1 2

CH11 0.22U_0201_6.3V6M

1 2

CH12 0.22U_0201_6.3V6M

1 2

CH13 0.22U_0201_6.3V6M

1 2

CH14 0.22U_0201_6.3V6M

1 2

CH15 0.22U_0201_6.3V6M

1 2

CH16 0.22U_0201_6.3V6M

1 2

CH17 0.22U_0201_6.3V6M

1 2

CH18 0.22U_0201_6.3V6M

1 2

CH19 0.22U_0201_6.3V6M

1 2

CH20 0.22U_0201_6.3V6M

1 2

CH21 0.22U_0201_6.3V6M

1 2

CH22 0.22U_0201_6.3V6M

1 2

CH23 0.22U_0201_6.3V6M

1 2

CH24 0.22U_0201_6.3V6M

1 2

CH25 0.22U_0201_6.3V6M

1 2

CH26 0.22U_0201_6.3V6M

1 2

CH27 0.22U_0201_6.3V6M

1 2

CH28 0.22U_0201_6.3V6M

1 2

CH29 0.22U_0201_6.3V6M

1 2

CH30 0.22U_0201_6.3V6M

1 2

CH31 0.22U_0201_6.3V6M

1 2

CH32 0.22U_0201_6.3V6M

1 2

CH33 0.22U_0201_6.3V6M

1 2

CH34 0.22U_0201_6.3V6M

1 2

CH35 0.22U_0201_6.3V6M

1 2

CH36 0.22U_0201_6.3V6M

DMI_CTX_PRX_P0 <16>
DMI_CTX_PRX_N0 <16>

DMI_CTX_PRX_P1 <16>
DMI_CTX_PRX_N1 <16>

DMI_CTX_PRX_P2 <16>
DMI_CTX_PRX_N2 <16>

DMI_CTX_PRX_P3 <16>
DMI_CTX_PRX_N3 <16>

2

PEG_CTX_C_GRX_P15
PEG_CTX_C_GRX_N15

PEG_CTX_C_GRX_P14
PEG_CTX_C_GRX_N14

PEG_CTX_C_GRX_P13
PEG_CTX_C_GRX_N13

PEG_CTX_C_GRX_P12
PEG_CTX_C_GRX_N12

PEG_CTX_C_GRX_P11
PEG_CTX_C_GRX_N11

PEG_CTX_C_GRX_P10
PEG_CTX_C_GRX_N10

PEG_CTX_C_GRX_P9
PEG_CTX_C_GRX_N9

PEG_CTX_C_GRX_P8
PEG_CTX_C_GRX_N8

PEG_CTX_C_GRX_P7
PEG_CTX_C_GRX_N7

PEG_CTX_C_GRX_P6
PEG_CTX_C_GRX_N6

PEG_CTX_C_GRX_P5
PEG_CTX_C_GRX_N5

PEG_CTX_C_GRX_P4
PEG_CTX_C_GRX_N4

PEG_CTX_C_GRX_P3
PEG_CTX_C_GRX_N3

PEG_CTX_C_GRX_P2
PEG_CTX_C_GRX_N2

PEG_CTX_C_GRX_P1
PEG_CTX_C_GRX_N1

PEG_CTX_C_GRX_P0
PEG_CTX_C_GRX_N0

1

CFL-H

UH1D

CPU_DP1_P0<36>

B B

TBT-AR

TBT-AR

A A

5

CPU_DP1_N0<36>
CPU_DP1_P1<36>
CPU_DP1_N1<36>
CPU_DP1_P2<36>
CPU_DP1_N2<36>
CPU_DP1_P3<36>
CPU_DP1_N3<36>

CPU_DP1_AUXP<36>
CPU_DP1_AUXN<36>

CPU_DP2_P0<36>
CPU_DP2_N0<36>
CPU_DP2_P1<36>
CPU_DP2_N1<36>
CPU_DP2_P2<36>
CPU_DP2_N2<36>
CPU_DP2_P3<36>
CPU_DP2_N3<36>

CPU_DP2_AUXP<36>
CPU_DP2_AUXN<36>

4

CPU_DP1_P0
CPU_DP1_N0
CPU_DP1_P1
CPU_DP1_N1
CPU_DP1_P2
CPU_DP1_N2
CPU_DP1_P3
CPU_DP1_N3

CPU_DP1_AUXP
CPU_DP1_AUXN

CPU_DP2_P0
CPU_DP2_N0
CPU_DP2_P1
CPU_DP2_N1
CPU_DP2_P2
CPU_DP2_N2
CPU_DP2_P3
CPU_DP2_N3

CPU_DP2_AUXP
CPU_DP2_AUXN

K36
K37
J35
J34
H37
H36
J37
J38

D27
E27

H34
H33
F37
G38
F34
F35
E37
E36

F26
E26

C34
D34
B36
B34
F33
E33
C33
B33

A27
B27

CFL-H_BGA1440

DDI1_TXP_0
DDI1_TXN_0
DDI1_TXP_1
DDI1_TXN_1
DDI1_TXP_2
DDI1_TXN_2
DDI1_TXP_3
DDI1_TXN_3

DDI1_AUXP
DDI1_AUXN

DDI2_TXP_0
DDI2_TXN_0
DDI2_TXP_1
DDI2_TXN_1
DDI2_TXP_2
DDI2_TXN_2
DDI2_TXP_3
DDI2_TXN_3

DDI2_AUXP
DDI2_AUXN

DDI3_TXP_0
DDI3_TXN_0
DDI3_TXP_1
DDI3_TXN_1
DDI3_TXP_2
DDI3_TXN_2
DDI3_TXP_3
DDI3_TXN_3

DDI3_AUXP
DDI3_AUXN

PROC_AUDIO_CLK

PROC_AUDIO_SDI

PROC_AUDIO_SDO

4 of 13

EDP_TXP_0
EDP_TXN_0
EDP_TXP_1
EDP_TXN_1
EDP_TXP_2
EDP_TXN_2
EDP_TXP_3
EDP_TXN_3

EDP_AUXP

EDP_AUXN

EDP_DISP_UTIL

DISP_RCOMP

@

EDP_TXP0

D29

EDP_TXN0

E29

EDP_TXP1

F28

EDP_TXN1

E28

EDP_TXP2

A29

EDP_TXN2

B29

EDP_TXP3

C28

EDP_TXN3

B28

EDP_AUXP

C26

EDP_AUXN

B26

EDP_DISP_UTIL BIA_PWM_PCH

A33

EDP_COMP

D37

EDP_COMP
CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.

AUD_AZA_CPU_SCLK

G27

AUD_AZA_CPU_SDO

G25

AUD_AZA_CPU_SDI AUD_AZA_CPU_SDI_R

G29

EDP_AUXP <35>
EDP_AUXN <35>

1 2

RH20

0_0402_5%

1 2

RH30

24.9_0402_1%

RH145

EDP_TXP0 <35>
EDP_TXN0 <35>
EDP_TXP1 <35>
EDP_TXN1 <35>
EDP_TXP2 <35>
EDP_TXN2 <35>
EDP_TXP3 <35>
EDP_TXN3 <35>

@

1 2

20_0402_5%

BIA_PWM_PCH <13,35>

AUD_AZA_CPU_SCLK <15>
AUD_AZA_CPU_SDO <15>
AUD_AZA_CPU_SDI_R <15>

+VCCIO

Close to CPU

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

2011/08/25 2012/07/25

2011/08/25 2012/07/25

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Title

Title

Title

CPU(1/7) DMI,PEG,DDI,EDP

CPU(1/7) DMI,PEG,DDI,EDP

CPU(1/7) DMI,PEG,DDI,EDP

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

LA-E993P

LA-E993P

LA-E993P

1

6 78Tuesday, March 06, 2018

6 78Tuesday, March 06, 2018

6 78Tuesday, March 06, 2018

1.0(A00)

1.0(A00)

1.0(A00)

Vinafix.com

5

4

3

2

1

Non-Interleave

DDR_A_D[0..63]<21>
DDR_A_MA[0..13]<21>
DDR_A_DQS#[0..7]<21>
DDR_A_DQS[0..7]<21>

DDR_B_D[0..63]<22>
DDR_B_MA[0..13]<22>

D D

UH1A

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38

C C

B B

DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47

DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4

BR6

DDR0_DQ_0/DDR0_DQ_0

BT6

DDR0_DQ_1/DDR0_DQ_1

BP3

DDR0_DQ_2/DDR0_DQ_2

BR3

DDR0_DQ_3/DDR0_DQ_3

BN5

DDR0_DQ_4/DDR0_DQ_4

BP6

DDR0_DQ_5/DDR0_DQ_5

BP2

DDR0_DQ_6/DDR0_DQ_6

BN3

DDR0_DQ_7/DDR0_DQ_7

BL4

DDR0_DQ_8/DDR0_DQ_8

BL5

DDR0_DQ_9/DDR0_DQ_9

BL2

DDR0_DQ_10/DDR0_DQ_10

BM1

DDR0_DQ_11/DDR0_DQ_11

BK4

DDR0_DQ_12/DDR0_DQ_12

BK5

DDR0_DQ_13/DDR0_DQ_13

BK1

DDR0_DQ_14/DDR0_DQ_14

BK2

DDR0_DQ_15/DDR0_DQ_15

BG4

DDR0_DQ_16/DDR0_DQ_32

BG5

DDR0_DQ_17/DDR0_DQ_33

BF4

DDR0_DQ_18/DDR0_DQ_34

BF5

DDR0_DQ_19/DDR0_DQ_35

BG2

DDR0_DQ_20/DDR0_DQ_36

BG1

DDR0_DQ_21/DDR0_DQ_37

BF1

DDR0_DQ_22/DDR0_DQ_38

BF2

DDR0_DQ_23/DDR0_DQ_39

BD2

DDR0_DQ_24/DDR0_DQ_40

BD1

DDR0_DQ_25/DDR0_DQ_41

BC4

DDR0_DQ_26/DDR0_DQ_42

BC5

DDR0_DQ_27/DDR0_DQ_43

BD5

DDR0_DQ_28/DDR0_DQ_44

BD4

DDR0_DQ_29/DDR0_DQ_45

BC1

DDR0_DQ_30/DDR0_DQ_46

BC2

DDR0_DQ_31/DDR0_DQ_47

AB1

DDR0_DQ_32/DDR1_DQ_0

AB2

DDR0_DQ_33/DDR1_DQ_1

AA4

DDR0_DQ_34/DDR1_DQ_2

AA5

DDR0_DQ_35/DDR1_DQ_3

AB5

DDR0_DQ_36/DDR1_DQ_4

AB4

DDR0_DQ_37/DDR1_DQ_5

AA2

DDR0_DQ_38/DDR1_DQ_6

AA1

DDR0_DQ_39/DDR1_DQ_7

V5

DDR0_DQ_40/DDR1_DQ_8

V2

DDR0_DQ_41/DDR1_DQ_9

U1

DDR0_DQ_42/DDR1_DQ_10

U2

DDR0_DQ_43/DDR1_DQ_11

V1

DDR0_DQ_44/DDR1_DQ_12

V4

DDR0_DQ_45/DDR1_DQ_13

U5

DDR0_DQ_46/DDR1_DQ_14

U4

DDR0_DQ_47/DDR1_DQ_15

R2

DDR0_DQ_48/DDR1_DQ_32

P5

DDR0_DQ_49/DDR1_DQ_33

R4

DDR0_DQ_50/DDR1_DQ_34

P4

DDR0_DQ_51/DDR1_DQ_35

R5

DDR0_DQ_52/DDR1_DQ_36

P2

DDR0_DQ_53/DDR1_DQ_37

R1

DDR0_DQ_54/DDR1_DQ_38

P1

DDR0_DQ_55/DDR1_DQ_39

M4

DDR0_DQ_56/DDR1_DQ_40

M1

DDR0_DQ_57/DDR1_DQ_41

L4

DDR0_DQ_58/DDR1_DQ_42

L2

DDR0_DQ_59/DDR1_DQ_43

M5

DDR0_DQ_60/DDR1_DQ_44

M2

DDR0_DQ_61/DDR1_DQ_45

L5

DDR0_DQ_62/DDR1_DQ_46

L1

DDR0_DQ_63/DDR1_DQ_47

LP3/DDR4

BA2

NC/DDR0_ECC_0

BA1

NC/DDR0_ECC_1

AY4

NC/DDR0_ECC_2

AY5

NC/DDR0_ECC_3

BA5

NC/DDR0_ECC_4

BA4

NC/DDR0_ECC_5

AY1

NC/DDR0_ECC_6

AY2

NC/DDR0_ECC_7

CFL-H_BGA1440

CFL-H

DDR CHANNEL A

DDR0_CKP_0/DDR0_CKP_0
DDR0_CKN_0/DDR0_CKN_0
DDR0_CKP_1/DDR0_CKP_1
DDR0_CKN_1/DDR0_CKN_1

NC/DDR0_CKP_2
NC/DDR0_CKN_2
NC/DDR0_CKP_3
NC/DDR0_CKN_3

DDR0_CKE_0/DDR0_CKE_0
DDR0_CKE_1/DDR0_CKE_1
DDR0_CKE_2/DDR0_CKE_2
DDR0_CKE_3/DDR0_CKE_3

DDR0_CS#_0/DDR0_CS#_0
DDR0_CS#_1/DDR0_CS#_1

NC/DDR0_CS#_2
NC/DDR0_CS#_3

DDR0_ODT_0/DDR0_ODT_0

NC/DDR0_ODT_1
NC/DDR0_ODT_2
NC/DDR0_ODT_3

DDR0_CAB_4/DDR0_BA_0
DDR0_CAB_6/DDR0_BA_1
DDR0_CAA_5/DDR0_BG_0

DDR0_CAB_3/DDR0_MA_16
DDR0_CAB_2/DDR0_MA_14
DDR0_CAB_1/DDR0_MA_15

DDR0_CAB_9/DDR0_MA_0
DDR0_CAB_8/DDR0_MA_1
DDR0_CAB_5/DDR0_MA_2

NC/DDR0_MA_3

NC/DDR0_MA_4
DDR0_CAA_0/DDR0_MA_5
DDR0_CAA_2/DDR0_MA_6
DDR0_CAA_4/DDR0_MA_7
DDR0_CAA_3/DDR0_MA_8
DDR0_CAA_1/DDR0_MA_9

DDR0_CAB_7/DDR0_MA_10
DDR0_CAA_7/DDR0_MA_11
DDR0_CAA_6/DDR0_MA_12
DDR0_CAB_0/DDR0_MA_13

DDR0_CAA_9/DDR0_BG_1
DDR0_CAA_8/DDR0_ACT#

NC/DDR0_PAR

NC/DDR0_ALERT#

DDR4(IL)/LP3-DDR4(NIL)

DDR0_DQSN_0/DDR0_DQSN_0
DDR0_DQSN_1/DDR0_DQSN_1
DDR0_DQSN_2/DDR0_DQSN_4
DDR0_DQSN_3/DDR0_DQSN_5
DDR0_DQSN_4/DDR1_DQSN_0
DDR0_DQSN_5/DDR1_DQSN_1
DDR0_DQSN_6/DDR1_DQSN_4
DDR0_DQSN_7/DDR1_DQSN_5

DDR0_DQSP_0/DDR0_DQSP_0
DDR0_DQSP_1/DDR0_DQSP_1
DDR0_DQSP_2/DDR0_DQSP_4
DDR0_DQSP_3/DDR0_DQSP_5
DDR0_DQSP_4/DDR1_DQSP_0
DDR0_DQSP_5/DDR1_DQSP_1
DDR0_DQSP_6/DDR1_DQSP_4
DDR0_DQSP_7/DDR1_DQSP_5

DDR0_DQSP_8/DDR0_DQSP_8

DDR0_DQSN_8/DDR0_DQSN_8

1 OF 13

@

AG1
AG2
AK2
AK1
AL3
AK3
AL2
AL1

AT1
AT2
AT3
AT5

AD5
AE2
AD2
AE5

AD3
AE4
AE1
AD4

AH5
AH1
AU1

AH4
AG4
AD1

AH3
AP4
AN4
AP5
AP2
AP1
AP3
AN1
AN3
AT4
AH2
AN2
AU4
AE3
AU2
AU3

AG3
AU5

BR5
BL3
BG3
BD3
AA3
U3
P3
L3

BP5
BK3
BF3
BC3
AB3
V3
R3
M3

AY3
BA3

DDR_B_DQS#[0..7]<22>
DDR_B_DQS[0..7]<22>

DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1

DDR_A_CKE0
DDR_A_CKE1

DDR_A_CS#0
DDR_A_CS#1

DDR_A_ODT0
DDR_A_ODT1

DDR_A_BA0
DDR_A_BA1
DDR_A_BG0

DDR_A_MA16_RAS#
DDR_A_MA14_WE#
DDR_A_MA15_CAS#

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_BG1
DDR_A_ACT#

DDR_A_PAR
DDR_A_ALERT#

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#4
DDR_A_DQS#5
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#4
DDR_B_DQS#5

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS4
DDR_A_DQS5
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS4
DDR_B_DQS5

DDR_A_CLK0 <21>
DDR_A_CLK#0 <21>
DDR_A_CLK1 <21>
DDR_A_CLK#1 <21>

DDR_A_CKE0 <21>
DDR_A_CKE1 <21>

DDR_A_CS#0 <21>
DDR_A_CS#1 <21>

DDR_A_ODT0 <21>
DDR_A_ODT1 <21>

DDR_A_BA0 <21>
DDR_A_BA1 <21>
DDR_A_BG0 <21>

DDR_A_MA16_RAS# <21>
DDR_A_MA14_WE# <21>
DDR_A_MA15_CAS# <21>

DDR_A_BG1 <21>
DDR_A_ACT# <21>

DDR_A_PAR <21>
DDR_A_ALERT# <21>

1 2

RH148 121_0402_1%

1 2

RH149 75_0402_1%

1 2

RH150 100_0402_1%

DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23

DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_RCOMP0
DDR_RCOMP1
DDR_RCOMP2

UH1B

DDR4(IL)/LP3-DDR4(NIL)

BT11

DDR1_DQ_0/DDR0_DQ_16

BR11

DDR1_DQ_1/DDR0_DQ_17

BT9

DDR1_DQ_2/DDR0_DQ_18

BR8

DDR1_DQ_3/DDR0_DQ_19

BP11

DDR1_DQ_4/DDR0_DQ_20

BN11

DDR1_DQ_5/DDR0_DQ_21

BP8

DDR1_DQ_6/DDR0_DQ_22

BN8

DDR1_DQ_7/DDR0_DQ_23

BL12

DDR1_DQ_8/DDR0_DQ_24

BL11

DDR1_DQ_9/DDR0_DQ_25

BL8

DDR1_DQ_10/DDR0_DQ_26

BJ8

DDR1_DQ_11/DDR0_DQ_27

BJ11

DDR1_DQ_12/DDR0_DQ_28

BJ10

DDR1_DQ_13/DDR0_DQ_29

BL7

DDR1_DQ_14/DDR0_DQ_30

BJ7

DDR1_DQ_15/DDR0_DQ_31

BG11

DDR1_DQ_16/DDR0_DQ_48

BG10

DDR1_DQ_17/DDR0_DQ_49

BG8

DDR1_DQ_18/DDR0_DQ_50

BF8

DDR1_DQ_19/DDR0_DQ_51

BF11

DDR1_DQ_20/DDR0_DQ_52

BF10

DDR1_DQ_21/DDR0_DQ_53

BG7

DDR1_DQ_22/DDR0_DQ_54

BF7

DDR1_DQ_23/DDR0_DQ_55

BB11

DDR1_DQ_24/DDR0_DQ_56

BC11

DDR1_DQ_25/DDR0_DQ_57

BB8

DDR1_DQ_26/DDR0_DQ_58

BC8

DDR1_DQ_27/DDR0_DQ_59

BC10

DDR1_DQ_28/DDR0_DQ_60

BB10

DDR1_DQ_29/DDR0_DQ_61

BC7

DDR1_DQ_30/DDR0_DQ_62

BB7

DDR1_DQ_31/DDR0_DQ_63

AA11

DDR1_DQ_32/DDR1_DQ_16

AA10

DDR1_DQ_33/DDR1_DQ_17

AC11

DDR1_DQ_34/DDR1_DQ_18

AC10

DDR1_DQ_35/DDR1_DQ_19

AA7

DDR1_DQ_36/DDR1_DQ_20

AA8

DDR1_DQ_37/DDR1_DQ_21

AC8

DDR1_DQ_38/DDR1_DQ_22

AC7

DDR1_DQ_39/DDR1_DQ_23

DDR4(IL)/LP3-DDR4(NIL)

W8

DDR1_DQ_40/DDR1_DQ_24

W7

DDR1_DQ_41/DDR1_DQ_25

V10

DDR1_DQ_42/DDR1_DQ_26

V11

DDR1_DQ_43/DDR1_DQ_27

W11

DDR1_DQ_44/DDR1_DQ_28

W10

DDR1_DQ_45/DDR1_DQ_29

V7

DDR1_DQ_46/DDR1_DQ_30

V8

DDR1_DQ_47/DDR1_DQ_31

R11

DDR1_DQ_48/DDR1_DQ_48

P11

DDR1_DQ_49/DDR1_DQ_49

P7

DDR1_DQ_50/DDR1_DQ_50

R8

DDR1_DQ_51/DDR1_DQ_51

R10

DDR1_DQ_52/DDR1_DQ_52

P10

DDR1_DQ_53/DDR1_DQ_53

R7

DDR1_DQ_54/DDR1_DQ_54

P8

DDR1_DQ_55/DDR1_DQ_55

L11

DDR1_DQ_56/DDR1_DQ_56

M11

DDR1_DQ_57/DDR1_DQ_57

L7

DDR1_DQ_58/DDR1_DQ_58

M8

DDR1_DQ_59/DDR1_DQ_59

L10

DDR1_DQ_60/DDR1_DQ_60

M10

DDR1_DQ_61/DDR1_DQ_61

M7

DDR1_DQ_62/DDR1_DQ_62

L8

DDR1_DQ_63/DDR1_DQ_63

LP3/DDR4

AW11

NC/DDR1_ECC_0

AY11

NC/DDR1_ECC_1

AY8

NC/DDR1_ECC_2

AW8

NC/DDR1_ECC_3

AY10

NC/DDR1_ECC_4

AW10

NC/DDR1_ECC_5

AY7

NC/DDR1_ECC_6

AW7

NC/DDR1_ECC_7

G1

DDR_RCOMP_0

H1

DDR_RCOMP_1

J2

DDR_RCOMP_2

CFL-H_BGA1440

CFL-H

DDR CHANNEL B

DDR1_CKP_0/DDR1_CKP_0
DDR1_CKN_0/DDR1_CKN_0
DDR1_CKP_1/DDR1_CKP_1
DDR1_CKN_1/DDR1_CKN_1

DDR1_CKE_0/DDR1_CKE_0
DDR1_CKE_1/DDR1_CKE_1
DDR1_CKE_2/DDR1_CKE_2
DDR1_CKE_3/DDR1_CKE_3

DDR1_CS#_0/DDR1_CS#_0
DDR1_CS#_1/DDR1_CS#_1

DDR1_ODT_0/DDR1_ODT_0

DDR1_CAB_3/DDR1_MA_16
DDR1_CAB_2/DDR1_MA_14
DDR1_CAB_1/DDR1_MA_15

DDR1_CAB_4/DDR1_BA_0
DDR1_CAB_6/DDR1_BA_1

DDR1_CAA_5/DDR1_BG_0

DDR1_CAB_9/DDR1_MA_0
DDR1_CAB_8/DDR1_MA_1
DDR1_CAB_5/DDR1_MA_2

DDR1_CAA_0/DDR1_MA_5
DDR1_CAA_2/DDR1_MA_6
DDR1_CAA_4/DDR1_MA_7

DDR1_CAA_3/DDR1_MA_8

DDR1_CAA_1/DDR1_MA_9
DDR1_CAB_7/DDR1_MA_10
DDR1_CAA_7/DDR1_MA_11
DDR1_CAA_6/DDR1_MA_12
DDR1_CAB_0/DDR1_MA_13

DDR1_CAA_9/DDR1_BG_1

DDR1_CAA_8/DDR1_ACT#

DDR1_DQSN_0/DDR0_DQSN_2
DDR1_DQSN_1/DDR0_DQSN_3
DDR1_DQSN_2/DDR0_DQSN_6
DDR1_DQSN_3/DDR0_DQSN_7
DDR1_DQSN_4/DDR1_DQSN_2
DDR1_DQSN_5/DDR1_DQSN_3
DDR1_DQSN_6/DDR1_DQSN_6
DDR1_DQSN_7/DDR1_DQSN_7

DDR1_DQSP_0/DDR0_DQSP_2
DDR1_DQSP_1/DDR0_DQSP_3
DDR1_DQSP_2/DDR0_DQSP_6
DDR1_DQSP_3/DDR0_DQSP_7
DDR1_DQSP_4/DDR1_DQSP_2
DDR1_DQSP_5/DDR1_DQSP_3
DDR1_DQSP_6/DDR1_DQSP_6
DDR1_DQSP_7/DDR1_DQSP_7

DDR1_DQSP_8/DDR1_DQSP_8
DDR1_DQSN_8/DDR1_DQSN_8

2 OF 13

LP3/DDR4

NC/DDR1_CKP_2

NC/DDR1_CKN_2

NC/DDR1_CKP_3

NC/DDR1_CKN_3

NC/DDR1_CS#_2
NC/DDR1_CS#_3

NC/DDR1_ODT_1
NC/DDR1_ODT_2
NC/DDR1_ODT_3

NC/DDR1_MA_3
NC/DDR1_MA_4

NC/DDR1_PAR

NC/DDR1_ALERT#

DDR4(IL)/LP3-DDR4(NIL)

DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ

@

AM9
AN9
AM7
AM8
AM11
AM10
AJ10
AJ11

AT8
AT10
AT7
AT11

AF11
AE7
AF10
AE10

AF7
AE8
AE9
AE11

AH10
AH11
AF8

AH8
AH9
AR9

AJ9
AK6
AK5
AL5
AL6
AM6
AN7
AN10

AN8
AR11
AH7
AN11
AR10
AF9
AR7
AT9

AJ7
AR8

BN9
BL9
BG9
BC9
AC9
W9
R9
M9

BP9
BJ9
BF9
BB9
AA9
V9
P9
L9

AW9
AY9

BN13
BP13
BR13

DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1

DDR_B_CKE0
DDR_B_CKE1

DDR_B_CS#0
DDR_B_CS#1

DDR_B_ODT0
DDR_B_ODT1

DDR_B_MA16_RAS#
DDR_B_MA14_WE#
DDR_B_MA15_CAS#

DDR_B_BA0
DDR_B_BA1
DDR_B_BG0

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7

DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_BG1
DDR_B_ACT#

DDR_B_PAR
DDR_B_ALERT#

DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#6
DDR_A_DQS#7
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#6
DDR_B_DQS#7

DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS6
DDR_A_DQS7
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS6
DDR_B_DQS7

DDR_B_CLK0 <22>
DDR_B_CLK#0 <22>
DDR_B_CLK1 <22>
DDR_B_CLK#1 <22>

DDR_B_CKE0 <22>
DDR_B_CKE1 <22>

DDR_B_CS#0 <22>
DDR_B_CS#1 <22>

DDR_B_ODT0 <22>
DDR_B_ODT1 <22>

DDR_B_MA16_RAS# <22>
DDR_B_MA14_WE# <22>
DDR_B_MA15_CAS# <22>

DDR_B_BA0 <22>
DDR_B_BA1 <22>
DDR_B_BG0 <22>

DDR_B_BG1 <22>
DDR_B_ACT# <22>

DDR_B_PAR <22>
DDR_B_ALERT# <22>

+V_DDR_REFB_R+V_DDR_REFA_R

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

2011/08/25 2012/07/25

2011/08/25 2012/07/25

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

CPU(2/7) DDRIV

CPU(2/7) DDRIV

CPU(2/7) DDRIV

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

LA-E993P

LA-E993P

LA-E993P

7 78Tuesday, March 06, 2018

7 78Tuesday, March 06, 2018

1

7 78Tuesday, March 06, 2018

1.0(A00)

1.0(A00)

1.0(A00)

Vinafix.com

5

4

3

2

1

+VCCSTG

CFG Straps for Processor

Stall reset sequence after CPU PLL lock until de-asserted

D D

CFG0

1 = (Default) Normal Operation; No stall.

*

0 = Stall.

RH183

1 2

@

1K_0402_5%

CFG0

+VCCST

RH165

RH163

RH156

RH164

RH151

RH152

RH144

1 2

1K_0402_5%

1 2

1K_0402_5%

1 2

51_0402_5%

1 2

1K_0402_5%

1 2

100_0402_5%

1 2

56.2_0402_1%

1 2

49.9_0402_1%

PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS

CFG2

C C

1: Normal Operation; Lane # definition matches
socket pin map definition

0:Lane Reversed

*

RH184

1 2

1K_0402_5%

CFG2

Display Port Presence Strap

CFG4

PCIE Port Bifurcation Straps

B B

CFG[6:5]

1 : Disabled; No Physical Display Port
attached to Embedded Display Port

0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

*

RH185

RH186

RH187

1 2

1K_0402_5%

1 2

@

1K_0402_5%

1 2

@

1K_0402_5%

CFG4

11: (Default) x16 - Device 1 functions 1 and 2 disabled

*

10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled

01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

CFG5

CFG6

SM_PG_CTRL<62>

If change to x8, need cheange setting.

PEG DEFER TRAINING

CFG7

A A

1: (Default) PEG Train immediately following xxRESETB
de assertion

*

0: PEG Wait for BIOS for training

RH188

1 2

1K_0402_5%

5

@

CFG7

4

H_PROCHOT#

H_THERMTRIP#_R

XDP_PREQ#

@

H_VCCST_PWRGD

VR_SVID_DATA

VR_SVID_ALERT#

H_CATERR#

@

VR_SVID_ALERT#<71>
VR_SVID_CLK<71>
VR_SVID_DATA<71>
H_PROCHOT#<44,59,60,71>

H_VCCST_PWRGD<15,20>

H_CPUPWRGD<15>
PLTRST_CPU#<13,20>
H_PM_SYNC_R<13>

H_PM_DOWN<13>
PECI_EC<13,44>
H_THERMTRIP#_R<13>

PROC_DETECT#<17>

VR_SVID_ALERT#
VR_SVID_CLK
VR_SVID_DATA

H_VCCST_PWRGD

H_PM_DOWN
PECI_EC

PROC_DETECT#

+1.2V_DDR

0.1U_0402_10V7K

2

SM_PG_CTRL

RH93

220K_0402_5%

1

CH197

Reserve for ESD

H_VCCST_PWRGD

PLTRST_CPU#

H_PROCHOT#_R

H_CPUPWRGD

Pilot.
Pop CH232 and change from 0.1u to 100p

PCH_TRIGGER<19>

CPU_TRIGGER<19>

CH210

CH233

CH211

CH232

PCH_TRIGGER PCH_TRIGGER_R
CPU_TRIGGER CPU_TRIGGER_R

CFL-H

UH1E

PCH_CPU_BCLK_P<14>
PCH_CPU_BCLK_N<14>

PCH_CPU_PCIBCLK_P<14>
PCH_CPU_PCIBCLK_N<14>

CPU_24MHZ_P<14>
CPU_24MHZ_N<14>

1 2

RH153 220_0402_5%

1 2

RH158 499_0402_1%

1 2

RH154 60.4_0402_1%

1 2

RH155 20_0402_5%

1 2

RH190 0_0402_5%@

1 2

RH89 0_0402_5%@

+3VS

UC1

5

12

Security Classification

Security Classification

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

VCC

4

Y

74AUP1G07SE-7_SOT353

SA00007WE00

1 2

100P_0402_50V8J@ESD@

1 2

470P_0402_50V7K@ESD@

1 2

100P_0402_50V8J

1 2

100P_0402_50V8J

RH167 30_0402_5%
RH192 30_0402_5%

Issued Date

Issued Date

Issued Date

3

1

NC

2

A

3

GND

1 2
1 2

2011/08/25 2012/07/25

2011/08/25 2012/07/25

2011/08/25 2012/07/25

PCH_CPU_BCLK_P
PCH_CPU_BCLK_N

PCH_CPU_PCIBCLK_P
PCH_CPU_PCIBCLK_N

CPU_24MHZ_P
CPU_24MHZ_N

VR_SVID_ALERT#_R

H_PROCHOT#_RH_PROCHOT#

DDR_VTT_PG_CTRL

VCCST_PWRGD_CPU

H_CPUPWRGD
PLTRST_CPU#
H_PM_SYNC_R
H_PM_DOWN_R
PECI_EC_R
H_THERMTRIP#_R

H_CATERR#

DDR_VTT_PG_CTRL

Compal Secret Data

Compal Secret Data

Compal Secret Data

B31
A32

D35
C36

E31

D31

BH31
BH32
BH29
BR30

BT13

H13

BT31
BP35

BM34

BP31
BT34

J31

BR33

BN1

BM30

AT13

AW13

AU13

AY13

E2

E3

E1

D1

BR1
BT2

BN35

J24

H24

BN33

BL34

N29

R14
AE29
AA14
AP29
AP14

A36

A37

H23

J23

F30

E30

B30

C30

G3

J3

BR35
BR31
BH30

Deciphered Date

Deciphered Date

Deciphered Date

BCLKP
BCLKN

PCI_BCLKP
PCI_BCLKN

CLK24P
CLK24N

VIDALERT#
VIDSCK
VIDSOUT
PROCHOT#

DDR_VTT_CNTL

VCCST_PWRGD

PROCPWRGD
RESET#
PM_SYNC
PM_DOWN
PECI
THERMTRIP#

SKTOCC#
PROC_SELECT#

CATERR#

ZVM#
MSM#

RSVD1
RSVD2

CFL-H_BGA1440

UH1M

RSVD_TP5
IST_TRIG
RSVD_TP4
RSVD_TP3

RSVD_TP1
RSVD_TP2

RSVD15

RSVD28
RSVD27
RSVD14
RSVD13

RSVD30
RSVD31
RSVD2
RSVD1
RSVD5
RSVD4
VSS_A36

VSS_A37

PROC_TRIGIN
PROC_TRIGOUT

RSVD24

RSVD23

RSVD7
RSVD21

RSVD26
RSVD29

RSVD19
RSVD18
RSVD9

CFL-H_BGA1440

2

5 OF 13

CFL-H

13 OF 13

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8

CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15

CFG_17
CFG_16
CFG_19
CFG_18

BPM#_0
BPM#_1
BPM#_2
BPM#_3

PROC_TDO

PROC_TDI
PROC_TMS
PROC_TCK

PROC_TRST#
PROC_PREQ#
PROC_PRDY#

CFG_RCOMP

RSVD11
RSVD10

RSVD12

RSVD3

RSVD25

RSVD22
RSVD20
RSVD17
RSVD16

RSVD8
RSVD6

@

@

BN25
BN27
BN26
BN28
BR20
BM20
BT20
BP20
BR23
BR22
BT23
BT22
BM19
BR19
BP19
BT19

BN23
BP23
BP22
BN22

BR27
BT27
BM31
BT30

BT28
BL32
BP28
BR28

BP30
BL30
BP27

BT25

BK28
BJ28

BL31
AJ8
G13

C38
C1
BR2
BP1
B38
B2

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

CFG17
CFG16
CFG19
CFG18

XDP_BPM#0
XDP_BPM#1

CPU_XDP_TDO
CPU_XDP_TDI
CPU_XDP_TMS
CPU_XDP_TCK

CPU_XDP_TRST#
XDP_PREQ#
XDP_PRDY#

CFG_RCOMP

CFG[0..19] <20>

XDP_BPM#0 <20>
XDP_BPM#1 <20>

CPU_XDP_TDO <2 0>
CPU_XDP_TDI <20>
CPU_XDP_TMS <20>
CPU_XDP_TCK <15,2 0>

CPU_XDP_TRST# <19,20>
XDP_PREQ# <19,20>
XDP_PRDY# <19,20>

12

RH59

49.9_0402_1%

Compal Electronics, Inc.

Title

Title

Title

CPU(3/7) RSVD,CFG,XDP

CPU(3/7) RSVD,CFG,XDP

CPU(3/7) RSVD,CFG,XDP

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

LA-E993P

LA-E993P

LA-E993P

1

8 78Tuesday, March 06, 2018

8 78Tuesday, March 06, 2018

8 78Tuesday, March 06, 2018

1.0(A00)

1.0(A00)

1.0(A00)

Vinafix.com

5

4

3

2

1

+VCC_CORE +VCC_CORE

D D

C C

B B

AA13
AA31
AA32
AA33
AA34
AA35
AA36
AA37
AA38
AB29
AB30
AB31
AB32
AB35
AB36
AB37
AB38
AC13
AC14
AC29
AC30
AC31
AC32
AC33
AC34
AC35
AC36
AD13
AD14
AD31
AD32
AD33
AD34
AD35
AD36
AD37
AD38
AE13
AE14
AE30
AE31
AE32
AE35
AE36
AE37
AE38

AF29
AF30
AF31
AF32
AF33
AF34
AF35
AF36
AF37

AF38
AG14
AG31
AG32
AG33
AG34
AG35
AG36

UH1I

CFL-H_BGA1440

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63

CFL-H

9 OF 13

VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98

VCC99
VCC100
VCC101
VCC102
VCC103
VCC104
VCC105
VCC106
VCC107
VCC108
VCC109
VCC110
VCC111
VCC112
VCC113
VCC114
VCC115
VCC116
VCC117
VCC118
VCC119
VCC120
VCC121
VCC122
VCC123
VCC124

VCC_SENSE
VSS_SENSE

@

AH13
AH14
AH29
AH30
AH31
AH32
AJ14
AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35
AJ36
AK31
AK32
AK33
AK34
AK35
AK36
AK37
AK38
AL13
AL29
AL30
AL31
AL32
AL35
AL36
AL37
AL38
AM13
AM14
AM29
AM30
AM31
AM32
AM33
AM34
AM35
AM36
AN13
AN14
AN31
AN32
AN33
AN34
AN35
AN36
AN37
AN38
AP13
AP30
AP31
AP32
AP35
AP36
AP37
AP38
K13

AG37
AG38

+VCC_CORE

12

RH197

100_0402_1%

12

RH29

100_0402_1%

96000mA(Hexa Core GT2)

1 2

RH198 0_0402_5%@

1 2

RH28 0_0402_5%@

VCCSENSE
VSSSENSE

VCCSENSE <71>
VSSSENSE <7 1>

UH1J

K14

L13

L14
N13
N14
N30
N31
N32
N35
N36
N37
N38
P13
P14
P29
P30
P31
P32
P33
P34
P35
P36
R13
R31
R32
R33
R34
R35
R36
R37
R38
T29
T30
T31
T32
T35
T36
T37
T38
U29
U30
U31
U32
U33
U34
U35
U36
V13
V14
V31
V32
V33
V34
V35
V36
V37
V38

W13
W14
W29
W30
W31
W32

CFL-H_BGA1440

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63

CFL-H

10 OF 13

VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75

+VCC_CORE+VCC_CORE

@

W35
W36
W37
W38
Y29
Y30
Y31
Y32
Y33
Y34
Y35
Y36

A A

Security Classification

Security Classification

Security Classification

2011/08/25 2012/07/25

2011/08/25 2012/07/25

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/08/25 2012/07/25

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

CPU(4/7) PWR,RSVD

CPU(4/7) PWR,RSVD

CPU(4/7) PWR,RSVD

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

LA-E993P

LA-E993P

LA-E993P

1

9 78Tuesday, March 06, 2018

9 78Tuesday, March 06, 2018

9 78Tuesday, March 06, 2018

1.0(A00)

1.0(A00)

1.0(A00)

Vinafix.com

5

4

3

2

1

570805_CFL_EDS_Vol1_Rev0.7
+VCC_SA
Max: 11100mA

D D

570805_CFL_EDS_Vol1_Rev0.7
+VCC_IO
Max: 6400mA

C C

+VCCIO

+VCCSA

K29
K30
K31
K32
K33
K34
K35
L31
L32
L35
L36
L37

L38
M29
M30
M31
M32
M33
M34
M35
M36

AG12

G15
G17
G19
G21
H15
H16
H17
H19
H20
H21
H26
H27

J30

J15
J16
J17
J19
J20
J21
J26
J27

UH1L

CFL-H_BGA1440

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
VCCSA9
VCCSA10
VCCSA11
VCCSA12
VCCSA13
VCCSA14
VCCSA15
VCCSA16
VCCSA17
VCCSA18
VCCSA19
VCCSA20
VCCSA21
VCCSA22

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21

CFL-H

12 OF 13

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VDDQ22
VDDQ23
VDDQ24
VDDQ25

VCCPLL_OC1
VCCPLL_OC2
VCCPLL_OC3

VCCST

VCCSTG2

VCCSTG1

VCCPLL1
VCCPLL2

VCCSA_SENSE

VSSSA_SENSE

VCCIO_SENSE
VSSIO_SENSE

@

+1.2V_DDR

AA6
AE12
AF5
AF6
AG5
AG9
AJ12
AL11
AP6
AP7
AR12
AR6
AT12
AW6
AY6
J5
J6
K12
K6
L12
L6
R6
T6
W6
Y12

BH13
BJ13
G11

H30

H29

G30

H28
J28

M38
M37

H14
J14

570805_CFL_EDS_Vol1_Rev0.7
+1.2V_VDDQ_CPU
Max: 3300mA

1 2

RH107

@

0_0402_5%

+VCCST

Max: 60mA

Max: 20mA

Max: 150mA

RH201 100_0402_1%
RH202 0_0402_5%@
RH31 0_0402_5%@
RH41 100_0402_1%

RH515 100_0402_1%
RH514 0_0402_5%@
RH513 0_0402_5%@
RH516 100_0402_1%

+VCCSTG

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

+VCCST

+1.2V_DDR+1.2V_VCCPLL_OC

+VCCSA

VCCSA_SENSE
VSSSA_SENSE

+VCCIO

VCCIO_SENSE
VSSIO_SENSE

VCCSA_SENSE <71>
VSSSA_SENSE <71>

VCCIO_SENSE <76>
VSSIO_SENSE <76>

CH111

CH133

+VCCSA

10U_0603_6.3V6M

+VCCSA

1U_0402_6.3V6K

1

2

1

2

CH112

CH114

CH113

1

10U_0603_6.3V6M

10U_0603_6.3V6M

2

CH115

1

1

10U_0603_6.3V6M

10U_0603_6.3V6M

2

2

1

2

CH116

CH117

1

1

10U_0603_6.3V6M

10U_0603_6.3V6M

2

2

DVT2.
Add CH234 22uF 0603 cap

B B

CH103

CH102

10U_0603_6.3V6M

A A

CH104

1

1

10U_0603_6.3V6M

2

2

Back cap
close CPU ball

5

CH129

1

10U_0603_6.3V6M

2

22U_0603_6.3V6M

CH131

CH130

1

1

22U_0603_6.3V6M

2

2

Back cap
close CPU ball

CH132

1

22U_0603_6.3V6M

22U_0603_6.3V6M

2

+1.2V_DDR+1.2V_DDR

CH118

1

2

10U_0603_6.3V6M

+1.2V_DDR

10U_0603_6.3V6M

CH216

TD team 12 * 10u

4

CH121

CH120

1

1

10U_0603_6.3V6M

2

2

Back cap
close CPU ball

10U_0603_6.3V6M

CH217

1

1

2

2

Back cap
close CPU ball

+VCCST+VCCIO

CH119

1

10U_0603_6.3V6M

10U_0603_6.3V6M

2

571391_PDG V0.71
+1.2V_VDDQ_CPU: 10uF * 11 22uF * 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

CH122

CH123

1

10U_0603_6.3V6M

10U_0603_6.3V6M

2

CH126

CH125

1

1

10U_0603_6.3V6M

10U_0603_6.3V6M

2

2

2011/08/25 2012/07/25

2011/08/25 2012/07/25

2011/08/25 2012/07/25

3

CH128

CH127

1

1

10U_0603_6.3V6M

10U_0603_6.3V6M

2

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

1

2

CH124

CH110

1

10U_0402_6.3V6M

2

1U_0402_6.3V6K

CH204

1

2

Back cap
close CPU ball
1uF * 1 close H30
1uF * 1 close J28

2

close to CPU Ball H30/J28

CH234

1

1U_0402_6.3V6K

2

1

22U_0603_6.3V6M

@

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

+VCCSTG

CH106

1U_0402_6.3V6K

1

2

+1.2V_VCCPLL_OC

1U_0201_6.3V6M

1

CC36

2

Back cap
close CPU ball
1uF * 1 close BJ13
1uF * 1 close G11

Compal Electronics, Inc.

CPU(5/7) PWR,BYPASS

CPU(5/7) PWR,BYPASS

CPU(5/7) PWR,BYPASS

LA-E993P

LA-E993P

LA-E993P

1

1U_0201_6.3V6M

1

CC37

2

1.0(A00)

1.0(A00)

1.0(A00)

10 78Tuesday, March 06, 2018

10 78Tuesday, March 06, 2018

10 78Tuesday, March 06, 2018

Vinafix.com

5

4

3

2

1

GT
55000mA(Hexa Core GT2)

CFL-H

UH1K

AT14

VCCGT1

AT31

VCCGT2

AT32

VCCGT3

AT33

VCCGT4

AT34

VCCGT5

D D

C C

B B

A A

AT35
AT36
AT37
AT38
AU14
AU29
AU30
AU31
AU32
AU35
AU36
AU37
AU38
AV29
AV30
AV31
AV32
AV33
AV34
AV35

AV36
AW14
AW31
AW32
AW33
AW34
AW35
AW36
AW37
AW38

AY29

AY30

AY31

AY32

AY35

AY36

AY37

AY38

BA13

BA14

BA29

BA30

BA31

BA32

BA33

BA34

BA35

BA36

BB13

BB14

BB31

BB32

BB33

BB34

BB35

BB36

BB37

BB38

BC29

BC30

BC31

BC32

BC35

BC36

BC37

BC38

BD13

BD14

BD29

BD30

BD31

BD32

BD33

BD34

BP37

BP38

BR15

BR16

BR17

VCCGT6
VCCGT7
VCCGT8
VCCGT9
VCCGT10
VCCGT11
VCCGT12
VCCGT13
VCCGT14
VCCGT15
VCCGT16
VCCGT17
VCCGT18
VCCGT19
VCCGT20
VCCGT21
VCCGT22
VCCGT23
VCCGT24
VCCGT25
VCCGT26
VCCGT27
VCCGT28
VCCGT29
VCCGT30
VCCGT31
VCCGT32
VCCGT33
VCCGT34
VCCGT35
VCCGT36
VCCGT37
VCCGT38
VCCGT39
VCCGT40
VCCGT41
VCCGT42
VCCGT43
VCCGT44
VCCGT45
VCCGT46
VCCGT47
VCCGT48
VCCGT49
VCCGT50
VCCGT51
VCCGT52
VCCGT53
VCCGT54
VCCGT55
VCCGT56
VCCGT57
VCCGT58
VCCGT59
VCCGT60
VCCGT61
VCCGT62
VCCGT63
VCCGT64
VCCGT65
VCCGT66
VCCGT67
VCCGT68
VCCGT69
VCCGT70
VCCGT71
VCCGT72
VCCGT73
VCCGT74
VCCGT75
VCCGT76
VCCGT77
VCCGT78
VCCGT79
VCCGT159
VCCGT160
VCCGT161
VCCGT162
VCCGT163

CFL-H_BGA1440

VSSGT_SENSE

11 OF 13

VCCGT_SENSE

VCCGT80
VCCGT81
VCCGT82
VCCGT83
VCCGT84
VCCGT85
VCCGT86
VCCGT87
VCCGT88
VCCGT89
VCCGT90
VCCGT91
VCCGT92
VCCGT93
VCCGT94
VCCGT95
VCCGT96
VCCGT97
VCCGT98

VCCGT99
VCCGT100
VCCGT101
VCCGT102
VCCGT103
VCCGT104
VCCGT105
VCCGT106
VCCGT107
VCCGT108
VCCGT109
VCCGT110
VCCGT111
VCCGT112
VCCGT113
VCCGT114
VCCGT115
VCCGT116
VCCGT117
VCCGT118
VCCGT119
VCCGT120
VCCGT121
VCCGT122
VCCGT123
VCCGT124
VCCGT125
VCCGT126
VCCGT127
VCCGT128
VCCGT129
VCCGT130
VCCGT131
VCCGT132
VCCGT133
VCCGT134
VCCGT135
VCCGT136
VCCGT137
VCCGT138
VCCGT139
VCCGT140
VCCGT141
VCCGT142
VCCGT143
VCCGT144
VCCGT145
VCCGT146
VCCGT147
VCCGT148
VCCGT149
VCCGT150
VCCGT151
VCCGT152
VCCGT153
VCCGT154
VCCGT155
VCCGT156
VCCGT157
VCCGT158
VCCGT164
VCCGT165
VCCGT166
VCCGT167
VCCGT168

+VCCGT+VCCGT

@

BD35
BD36
BE31
BE32
BE33
BE34
BE35
BE36
BE37
BE38
BF13
BF14
BF29
BF30
BF31
BF32
BF35
BF36
BF37
BF38
BG29
BG30
BG31
BG32
BG33
BG34
BG35
BG36
BH33
BH34
BH35
BH36
BH37
BH38
BJ16
BJ17
BJ19
BJ20
BJ21
BJ23
BJ24
BJ26
BJ27
BJ37
BJ38
BK16
BK17
BK19
BK20
BK21
BK23
BK24
BK26
BK27
BL15
BL16
BL17
BL23
BL24
BL25
BL26
BL27
BL28
BL36
BL37
BM15
BM16
BM17
BM36
BM37
BN15
BN16
BN17
BN36
BN37
BN38
BP15
BP16
BP17
BR37
BT15
BT16
BT17
BT37

AH37
AH38

+VCCGT

12

12

RH33

100_0402_1%

RH203

100_0402_1%

RH204 0_0402_5%@
RH32 0_0402_5%@

1 2
1 2

VSSGT_SENSE
VCCGT_SENSE

1. VccGT_SENSE / VssGT_SENSE Trace Length Match < 25 mils

2. Maintain 25-mil separation distance away from any other dynamic signals.

3. RC12, RC13 should be placed within 2 inches (50.8 mm) of CPU

VSSGT_SENSE <71>
VCCGT_SENSE <71>

Security Classification

Security Classification

Security Classification

2011/08/25 2012/07/25

2011/08/25 2012/07/25

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/08/25 2012/07/25

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

CPU(6/7) PWR

CPU(6/7) PWR

CPU(6/7) PWR

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

LA-E993P

LA-E993P

LA-E993P

1

11 78Tuesday, March 06, 2018

11 78Tuesday, March 06, 2018

11 78Tuesday, March 06, 2018

1.0(A00)

1.0(A00)

1.0(A00)

Vinafix.com

5

4

3

2

1

CFL-H

UH1F

A10

VSS_1

A12

VSS_2

A16

VSS_3

A18

VSS_4

A20

VSS_5

D D

C C

B B

A22
A24
A26
A28
A30

AA12
AA29
AA30
AB33
AB34

AB6
AC1

AC12

AC2

AC3
AC37
AC38

AC4

AC5

AC6
AD10
AD11
AD12
AD29
AD30

AD6

AD8

AD9
AE33
AE34

AE6

AF1
AF12
AF13
AF14

AF2

AF3

AF4

AG10
AG11
AG13
AG29
AG30

AG6
AG7

AG8
AH12
AH33
AH34
AH35
AH36

AH6

AJ1

AJ13

AJ2

AJ3
AJ37
AJ38

AJ4

AJ5

AJ6

Y10

Y11

Y13

Y14

Y37

Y38

AK29
AK30

A6
A9

W4
W5

Y7
Y8
Y9

VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81

CFL-H_BGA1440

6 OF 13

VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162

@

AK4
AL10
AL12
AL14
AL33
AL34
AL4
AL7
AL8
AL9
AM1
AM12
AM2
AM3
AM37
AM38
AM4
AM5
AN12
AN29
AN30
AN5
AN6
AP10
AP11
AP12
AP33
AP34
AP8
AP9
AR1
AR13
AR14
AR2
AR29
AR3
AR30
AR31
AR32
AR33
AR34
AR35
AR36
AR37
AR38
AR4
AR5
AT29
AT30
AT6
AU10
AU11
AU12
AU33
AU34
AU6
AU7
AU8
AU9
AV37
AV38
AW1
AW12
AW2
AW29
AW3
AW30
AW4
U6
V12
V29
V30
A14
AD7
V6
W1
W12
W2
W3
W33
W34

AW5
AY12
AY33
AY34

BA10
BA11
BA12
BA37
BA38

BA6
BA7
BA8
BA9
BB1

BB12

BB2

BB29

BB3

BB30

BB4
BB5

BB6
BC12
BC13
BC14
BC33
BC34

BC6
BD10
BD11
BD12
BD37

BD6

BD7

BD8

BD9

BE1
BE2

BE29

BE3

BE30

BE4
BE5

BE6
BF12
BF33
BF34

BF6

BG12
BG13
BG14
BG37
BG38

BG6

BH1
BH10
BH11
BH12
BH14

BH2

BH3

BH4

BH5

BH6

BH7

BH8

BH9

U37

U38
BJ12
BJ14

T33
T34

UH1G

VSS_163
VSS_164
VSS_165
VSS_166

B9

VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230

T2

VSS_231

T3

VSS_232
VSS_233
VSS_234

T4

VSS_235

T5

VSS_236

T7

VSS_237

T8

VSS_238

T9

VSS_239
VSS_240
VSS_241
VSS_242
VSS_243

CFL-H_BGA1440

CFL-H

7 OF 13

VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324

@

BJ15
BJ18
BJ22
BJ25
BJ29
BJ30
BJ31
BJ32
BJ33
BJ34
BJ35
BJ36
BK13
BK14
BK15
BK18
BK22
BK25
BK29
BK6
BL13
BL14
BL18
BL19
BL20
BL21
BL22
BL29
BL33
BL35
BL38
BL6
BM11
BM12
BM13
BM14
BM18
BM2
BM21
BM22
BM23
BM24
BM25
BM26
BM27
BM28
BM29
BM3
BM33
BM35
BM38
BM5
BM6
BM7
BM8
BM9
BN12
BN14
BN18
BN19
BN2
BN20
BN21
BN24
BN29
BN30
BN31
BN34
P38
P6
R12
R29
AY14
BD38
R30
T1
T10
T11
T12
T13
T14

BN4

BN7
BP12
BP14
BP18
BP21
BP24
BP25
BP26
BP29
BP33
BP34

BP7
BR12
BR14
BR18
BR21
BR24
BR25
BR26
BR29
BR34
BR36

BR7

BT12
BT14
BT18
BT21
BT24
BT26
BT29
BT32

BT5

M14

C11
C13
C15
C17
C19
C21
C23
C25
C27
C29
C31
C37

D10
D12
D14
D16
D18
D20
D22
D24
D26
D28

D30
D33

E34
E35
E38

N33
N34

P12
P37

F11
F13

C5
C8
C9

D3

D6
D9

N3

N4
N5
N6
N7
N8
N9

M6
N1

UH1H

VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360
VSS_361
VSS_362
VSS_363
VSS_364
VSS_365
VSS_366
VSS_367
VSS_368
VSS_369
VSS_370
VSS_371
VSS_372
VSS_373
VSS_374
VSS_375
VSS_376
VSS_377
VSS_378
VSS_379
VSS_380
VSS_381
VSS_382
VSS_383
VSS_384
VSS_385
VSS_386
VSS_387
VSS_388
VSS_389
VSS_390

E4

VSS_391

E9

VSS_392
VSS_393
VSS_394
VSS_395
VSS_396
VSS_397
VSS_398
VSS_399
VSS_400
VSS_401
VSS_402
VSS_403
VSS_404
VSS_405
VSS_406
VSS_407
VSS_408

CFL-H_BGA1440

CFL-H

VSS_409
VSS_410
VSS_411
VSS_412
VSS_413
VSS_414
VSS_415
VSS_416
VSS_417
VSS_418
VSS_419
VSS_420
VSS_421
VSS_422
VSS_423
VSS_424
VSS_425
VSS_426
VSS_427
VSS_428
VSS_429
VSS_430
VSS_431
VSS_432
VSS_433
VSS_434
VSS_435
VSS_436
VSS_437
VSS_438
VSS_439
VSS_440
VSS_441
VSS_442
VSS_443
VSS_444
VSS_445
VSS_446
VSS_447
VSS_448
VSS_449
VSS_450
VSS_451
VSS_452
VSS_453
VSS_454
VSS_455
VSS_456
VSS_457
VSS_458
VSS_459
VSS_460
VSS_461
VSS_462
VSS_463
VSS_464
VSS_465
VSS_466
VSS_467
VSS_468
VSS_469
VSS_470
VSS_471
VSS_472
VSS_473
VSS_474
VSS_475
VSS_476
VSS_477
VSS_478
VSS_479

VSS_A3

VSS_A34

VSS_A4
VSS_B3

VSS_B37

VSS_BR38

VSS_BT3
VSS_BT35
VSS_BT36

VSS_BT4

VSS_C2

8 OF 13

VSS_D38

@

F15
F17
F19
F2
F21
F23
F25
F27
F29
F3
F31
F36
F4
F5
F8
F9
G10
G12
G14
G16
G18
G20
G22
G23
G24
G26
G28
G4
G5
G6
G8
G9
H11
H12
H18
H22
H25
H32
H35
J10
J18
J22
J25
J32
J33
J36
J4
J7
K1
K10
K11
K2
K3
K38
K4
K5
K7
K8
K9
L29
L30
L33
L34
M12
M13
N10
N11
N12
N2
BT8
BR9

A3
A34
A4
B3
B37
BR38
BT3
BT35
BT36
BT4
C2
D38

A A

Security Classification

Security Classification

Security Classification

2011/08/25 2012/07/25

2011/08/25 2012/07/25

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/08/25 2012/07/25

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

CPU(7/7) VSS

CPU(7/7) VSS

CPU(7/7) VSS

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

LA-E993P

LA-E993P

LA-E993P

12 78Tuesday, March 06, 2018

12 78Tuesday, March 06, 2018

12 78Tuesday, March 06, 2018

1

1.0(A00)

1.0(A00)

1.0(A00)

Vinafix.com

5

D D

SSD

LAN

HDD

SSD

PROJECT ID2
(GPP_G4)

0

0

PROJECT_ID1
PROJECT_ID2
TPM_ID

STRAP

GPP_J9

TPM ID

SW TPM
HW TPM

PROJECT ID

C C

Firestar MLK
Firestar B
Armani MLK

Not Used

+3VS

12

@

RH557

10K_0402_5%

10K_0402_5%

B B

A A

10K_0402_5%

12

@

RH558

10K_0402_5%

RH558

FSTR@

10K_0402_5%

SD028100280

RH557

AMN@

10K_0402_5%

SD028100280

+1.8V_PRIM

RH591 10K_0402_5%@

The signal has a weak internal pull-down
0 = VCCPSPI is connected to 3.3V rail
1 = VCCPSPI is connected to 1.8V rail
Note: If VCCPSPI is connected to 1.8V rail, this pin
strap must be a ‘1’ for the proper functionality
of the SPI (Flash) I/Os

(GPP_G7)

PROJECT ID1
(GPP_G3)

12

@

RH561

12

@

RH562

RH562

10K_0402_5%

SD028100280

RH562

10K_0402_5%

SD028100280

12

TPM ID

0
1

0

1
0 1
1 1

12

TPM@

RH616

10K_0402_5%

12

NON_TPM@

RH617

10K_0402_5%

FSTR@

AMN@

5

PCIE_PTX_DRX_P11<39>

PCIE_PTX_DRX_N11<39>
PCIE_PRX_DTX_P11<39>
PCIE_PRX_DTX_N11<39>

PCIE_PTX_DRX_N14<40>

PCIE_PTX_DRX_P14<40>
PCIE_PRX_DTX_N14<40>
PCIE_PRX_DTX_P14<40>

SATA_PTX_DRX_N0B<39>

SATA_PTX_DRX_P0B<39>
SATA_PRX_DTX_N0B<39>
SATA_PRX_DTX_P0B<39>

SATA_PTX_DRX_P1A<39>

SATA_PTX_DRX_N1A<39>
SATA_PRX_DTX_P1A<39>
SATA_PRX_DTX_N1A<39>

TBT_CIO_PLUG_EVENT#<36>

KB_BL_DET<46>

+3VS

1 2

RH559

TH135 @

CNV_BRI_PTX_DRX<41>

CNV_BRI_PRX_DTX<41>

CNV_RGI_PTX_DRX<41>

CNV_RGI_PRX_DTX<41>

For DDX03 R02

+1.8V_PRIM

+1.8V_PRIM

XTAL Frequency Select

1 2

RH590 1K_0402_5%

This signal has a weak internal pull-down.
0 = 38.4/19.2MHz XTAL frequency selected.
1 = 24MHz XTAL frequency selected. (DDX03)
Notes:

1. The internal pull-down is disabled after RSMRST#
de-asserts.

2. This signal is in the primary well.

M.2 CNV Mode Select

RH588 100K_0402_5%

RH589 10K_0402_5%@

An external pull-up or pull-down is required.
0 = Integrated CNVi enable.
1 = Integrated CNVi disable.

CNVi CRF have internal pull down 1K.
CNV_RGI_DT strap pin have internal pull up 20K.
CNV_RGI_DT will detect low and enable CNVi when insert CNVi CRF.

T94PAD@

12

12

4

PCIE_PTX_DRX_P11
PCIE_PTX_DRX_N11
PCIE_PRX_DTX_P11
PCIE_PRX_DTX_N11

PCIE_PTX_DRX_N14
PCIE_PTX_DRX_P14
PCIE_PRX_DTX_N14
PCIE_PRX_DTX_P14

SATA_PTX_DRX_N0B
SATA_PTX_DRX_P0B
SATA_PRX_DTX_N0B
SATA_PRX_DTX_P0B

SATA_PTX_DRX_P1A
SATA_PTX_DRX_N1A
SATA_PRX_DTX_P1A
SATA_PRX_DTX_N1A

CAM_CBL_DET#

TBT_CIO_PLUG_EVENT#
PROJECT_ID1
PROJECT_ID2
LCD_DBC
KB_BL_DET
TPM_ID

LCD_DBC

10K_0402_5%

CPU_VCCIO_PWR_GATE#

CNV_BRI_PTX_DRX
CNV_BRI_PRX_DTX
CNV_RGI_PTX_DRX
CNV_RGI_PRX_DTX

GPP_J9

CNV_BRI_PTX_DRX

CNV_RGI_PTX_DRX

4

STRAP

STRAP

3

UH2C

AR2

CL_CLK

AT5

CL_DATA

AU4

CL_RST#

P48

GPP_K8

V47

GPP_K9

V48

GPP_K10

W47

GPP_K11

L47

GPP_K0

L46

GPP_K1

U48

GPP_K2

U47

GPP_K3

N48

GPP_K4

N47

GPP_K5

P47

GPP_K6

R46

GPP_K7

C36

PCIE11_TXP/SATA0A_TXP

B36

PCIE11_TXN/SATA0A_TXN

F39

PCIE11_RXP/SATA0A_RXP

G38

PCIE11_RXN/SATA0A_RXN

AR42

GPP_F10/SATA_SCLOCK

AR48

GPP_F11/SATA_SLOAD

AU47

GPP_F13/SATA_SDATAOUT0

AU46

GPP_F12/SATA_SDATAOUT1

C39

PCIE14_TXN/SATA1B_TXN

D39

PCIE14_TXP/SATA1B_TXP

D46

PCIE14_RXN/SATA1B_RXN

C47

PCIE14_RXP/SATA1B_RXP

B38

PCIE13_TXN/SATA0B_TXN

C38

PCIE13_TXP/SATA0B_TXP

C45

PCIE13_RXN/SATA0B_RXN

C46

PCIE13_RXP/SATA0B_RXP

E37

PCIE12_TXP/SATA1A_TXP

D38

PCIE12_TXN/SATA1A_TXN

J41

PCIE12_RXP/SATA_1A_RXP

H42

PCIE12_RXN/SATA1A_RXN

B44

PCIE20_TXP/SATA7_TXP

A44

PCIE20_TXN/SATA7_TXN

R37

PCIE20_RXP/SATA7_RXP

R35

PCIE20_RXN/SATA7_RXN

D43

PCIE19_TXP/SATA6_TXP

C44

PCIE19_TXN/SATA6_TXN

N42

PCIE19_RXP/SATA6_RXP

M44

PCIE19_RXN/SATA6_RXN

CNP-H_BGA874

UH2M

AW13

GPP_G0/SD_CMD

BE9

GPP_G1/SD_DATA0

BF8

GPP_G2/SD_DATA1

BF9

GPP_G3/SD_DATA2

BG8

GPP_G4/SD_DATA3

BE8

GPP_G5/SD_CD#

BD8

GPP_G6/SD_CLK

AV13

GPP_G7/SD_WP

AP3

GPP_I11/M2_SKT2_CFG0

AP2

GPP_I12/M2_SKT2_CFG1

AN4

GPP_I13/M2_SKT2_CFG2

AM7

GPP_I14/M2_SKT2_CFG3

AV6

GPP_J0/CNV_PA_BLANKING

AY3

GPP_J1/CPU_C10_GATE#

AR13

GPP_J11/A4WP_PRESENT

AV7

GPP_J10

AW3

GPP_J_2

AT10

GPP_J_3

AV4

GPP_J4/CNV_BRI_DT/UART0B_RTS#

AY2

GPP_J5/CNV_BRI_RSP/UART0B_RXD

BA4

GPP_J6/CNV_RGI_DT/UART0B_TXD

AV3

GPP_J7/CNV_RGI_RSP/UART0B_CTS#

AW2

GPP_J8/CNV_MFUART2_RXD

AU9

GPP_J9/CNV_MFUART2_TXD

CNP-H_BGA874

The 30 HSIO lanes on PCH-H supports the following configurat ions:

1. Up to 24 PCIe* Lanes
—A maximum of 16 PCIe* Ports (or devices) can be enabled

When a GbE Port is enabled, the maximum number of PCIe* Por ts (or

‧

devices) that can be enabled reduces based off the following :
Max PCIe* Ports (or devices) = 16 - GbE (0 or 1)
— PCIe* Lanes 1-4 (PCIe* Controller #1), 5-8 (PCIe* Controll er #2), 9-12 (PCIe*
Controller #3), 13-16 (PCIe* Controller #4), 17-20 (PCIe* Co ntroller #5), and
21-24 (PCIe* Controller #6) can be individually configured

2. Up to 6 SATA Lanes
— A maximum of 6 SATA Ports (or devices) can be enabled
— SATA Lane 0 has the flexibility to be mapped to Flex I/O L ane 16 or 18
— SATA Lane 1 has the flexibility to be mapped to Flex I/O L ane 17 or 19

3. Up to 10 USB 3.1 Lanes
— A maximum of 10 USB 3.1 Ports (or devices) can be enabled

4. Up to 4 GbE Lanes
— A maximum of 1 GbE Port (or device) can be enabled

5. Supports up to 3 Remapped (IntelR Rapid Storage Technolog y) PCIe* storage
devices
— x2 and x4 PCIe* NVMe SSD
— x2 IntelR Optane? Memory Device
— See the “PCI Express* (PCIe*)” chapter for the PCH PCIe* C ontrollers,configurations
, and lanes that can be used for IntelR Rapid Storage Techno logy PCIe* storage support

6. For unused SATA/PCIe* Combo Lanes, Flex I/O Lanes that ca n be configured as PCIe* or SATA,
the lanes must be statically assigned to SATA or PCIe* via t he SATA/PCIe Combo Port Soft
Straps discussed in the SPI Programming Guide and
through the IntelR Flash Image Tool (FIT) tool.

CNP-H

PCIE15_RXN/SATA2_RXN
PCIE15_RXP/SATA2_RXP

PCIE_15_SATA_2_TXN

PCIE15_TXP/SATA2_TXP

PCIE16_RXN/SATA3_RXN
PCIE16_RXP/SATA3_RXP

PCIE16_TXN/SATA3_TXN
PCIE16_TXP/SATA3_TXP

PCIE17_RXN/SATA4_RXN
PCIE17_RXP/SATA4_RXP
PCIE17_TXN/SATA4_TXN

PCIE17_TXP/SATA4_TXP

PCIE18_RXN/SATA5_RXN
PCIE18_RXP/SATA5_RXP

PCIE18_TXN/SATA5_TXN
PCIE18_TXP/SATA5_TXP

GPP_E8/SATA_LED#

GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2

GPP_F0/SATAXPCIE3/SATAGP_3

GPP_F1/SATAXPCIE4/SATAGP4
GPP_F2/SATAXPCIE5/SATAGP5
GPP_F3/SATAXPCIE6/SATAGP6
GPP_F4/SATAXPCIE7/SATAGP7

GPP_F21/EDP_BKLTCTL

GPP_F20/EDP_BKLTEN

GPP_F19/EDP_VDDEN

3 OF 13

CNP-H

3.3V

CNV_WT_RCOMP

1.8V

GPPJ_RCOMP_1P81
GPPJ_RCOMP_1P82
GPPJ_RCOMP_1P83

13 OF 13

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

PCIE9_RXN

PCIE9_RXP
PCIE9_TXN
PCIE9_TXP

PCIE10_RXN
PCIE10_RXP
PCIE10_TXN

PCIE10_TXP

THRMTRIP#

PECI

PM_SYNC

PLTRST_CPU#

PM_DOWN

CNV_WR_CLKN
CNV_WR_CLKP

CNV_WR_D0N
CNV_WR_D0P
CNV_WR_D1N
CNV_WR_D1P

CNV_WT_CLKN
CNV_WT_CLKP

CNV_WT_D0N
CNV_WT_D0P
CNV_WT_D1N
CNV_WT_D1P

PCIE_RCOMPN

PCIE_RCOMPP
SD_1P8_RCOMP
SD_3P3_RCOMP

RSVD2
RSVD3

RSVD1

@

PCIE_PRX_DTX_N9

G36

PCIE_PRX_DTX_P9

F36

PCIE_PTX_DRX_N9

C34

PCIE_PTX_DRX_P9

D34

PCIE_PRX_DTX_N10

K37

PCIE_PRX_DTX_P10

J37

PCIE_PTX_DRX_N10

C35

PCIE_PTX_DRX_P10

B35

PCIE_PRX_DTX_N15

F44

PCIE_PRX_DTX_P15

E45

PCIE_PTX_DRX_N15

B40

PCIE_PTX_DRX_P15

C40

L41
M40
B41
C41

K43
K44
A42
B42

P41
R40
C42
D42

PCH_SATA_LED#

AK48

AH41

mCARD_PCIE_SATA#

AJ43
AK47
AN47
AM46
AM43
AM47
AM48

BIA_PWM_PCH

AU48

L_BKLT_EN_EC

AV46

ENVDD_PCH

AV44

H_THERMTRIP#

AD3
AF2

PECI
H_PM_SYNC

AF3

PLTRST_CPU#

AG5

H_PM_DOWN

AE2

Rev1.0

@

CLK_CNV_PRX_DTX_N

BD4

CLK_CNV_PRX_DTX_P

BE3

CNV_PRX_DTX_N0

BB3

CNV_PRX_DTX_P0

BB4

CNV_PRX_DTX_N1

BA3

CNV_PRX_DTX_P1

BA2

CLK_CNV_PTX_DRX_N

BC5

CLK_CNV_PTX_DRX_P

BB6

CNV_PTX_DRX_N0

BE6

CNV_PTX_DRX_P0

BD7

CNV_PTX_DRX_N1

BG6

CNV_PTX_DRX_P1

BF6

CNV_WT_RCOMP

BA1

PCIE_RCOMPN

B12

PCIE_RCOMPP

A13

SD_RCOMP_1P8

BE5

SD_RCOMP_3P3

BE4
BD1

GPPJ_RCOMP_1P8

BE1
BE2

Y35

Add TH136 test point for CVNi check list

Y36

BC1
AL35

TP

Rev1.0

#571483_CFL_H_RVP_CRB_TDK_Rev0p5
Recommend external test point

2011/08/25 2012/07/25

2011/08/25 2012/07/25

2011/08/25 2012/07/25

TH136@
TH101@

Compal Secret Data

Compal Secret Data

Compal Secret Data

2

PCIE_PRX_DTX_N9 <39>
PCIE_PRX_DTX_P9 <39>
PCIE_PTX_DRX_N9 <39>
PCIE_PTX_DRX_P9 <39>

PCIE_PRX_DTX_N10 <39>
PCIE_PRX_DTX_P10 <39>
PCIE_PTX_DRX_N10 <39>
PCIE_PTX_DRX_P10 <39>

PCIE_PRX_DTX_N15 <41>

PCIE_PRX_DTX_P15 <41>
PCIE_PTX_DRX_N15 <41>
PCIE_PTX_DRX_P15 <41>

PCH_SATA_LED# <48>

mCARD_PCIE_SATA# <39>

BIA_PWM_PCH <6,35>
L_BKLT_EN_EC <44>
ENVDD_PCH <54>

1 2

RH191 620_0402_5%

1 2

RH138 1 3_0402_5%
RH189

1 2

30_0402_5%

PLTRST_CPU# <8,2 0>
H_PM_DOWN <8>

CLK_CNV_PRX_DTX_N <41 >
CLK_CNV_PRX_DTX_P <41>

CNV_PRX_DTX_N0 <41>
CNV_PRX_DTX_P0 <41>
CNV_PRX_DTX_N1 <41>
CNV_PRX_DTX_P1 <41>

CLK_CNV_PTX_DRX_N <41 >
CLK_CNV_PTX_DRX_P <41>

CNV_PTX_DRX_N0 <41>
CNV_PTX_DRX_P0 <41>
CNV_PTX_DRX_N1 <41>
CNV_PTX_DRX_P1 <41>

1 2

RH25 150_0402_1%

1 2

RH108 100_0402_1%

1 2

RH586 200_0402_1%

1 2

RH23 200_0402_1%

1 2

RH587 200_0402_1%

Deciphered Date

Deciphered Date

Deciphered Date

2

H_THERMTRIP#_R
PECI_EC
H_PM_SYNC_R

1

mCARD_PCIE_SATA#

SSD

CAM_CBL_DET#

PCH_SATA_LED#

RH68

RH79

RH80

1 2

10K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

NGFF WLAN

H_THERMTRIP#_R <8>
PECI_EC <8,44>
H_PM_SYNC_R <8>

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PCH (1/7) SATA,PCIE,CNVi

PCH (1/7) SATA,PCIE,CNVi

PCH (1/7) SATA,PCIE,CNVi

LA-E993P

LA-E993P

LA-E993P

1

13 78Tuesday, March 06, 2018

13 78Tuesday, March 06, 2018

13 78Tuesday, March 06, 2018

+3VALW_PCH

+3VS

1.0(A00)

1.0(A00)

1.0(A00)

Vinafix.com

5

4

3

2

1

+3VS

RP3

RH74

@

RH568

RH601

@

993@EMI@

PCH

CLKREQ_PCIE#2
CLKREQ_PCIE#7
CLKREQ_PCIE#3
CLKREQ_PCIE#6

XCLK_BIASREF
Trace Width/Space: 15mil /15 mil
Max Trace Length: 1000 mil

PCH_SPI_0_CS#0

TPM_PIRQ#

GPP_H12

RH582

994@EMI@

STRAP

0_0402_5%

SD028000080

PCH_SPI_0_CLK_R<45>

PCH_SPI_0_CLK

PCH_SPI_0_CLK_R

CH215

@RF@

10P_0402_25V8J

Reserve for RF

12

12

12

12

PCH_SPI_0_WP#

PCH_SPI_0_HOLD#

PCH_SPI_0_SI

GPP_H15

PCH_SPI_0_CLK_R
PCH_SPI_0_SO PCH_SPI_0_SO_R
PCH_SPI_0_SI
PCH_SPI_0_WP#

STRAP

1 2

RE126 33_0402_5%EMI@

1 2

RE127 33_0402_5%

1 2

RE128 33_0402_5%

1 2

RE129 33_0402_5%

1 2

RE71 33_0402_5%

SPI ROM FOR ME ( 16MByte )

PCH_SPI_0_CS#0

CPU_24MHZ_P<8>
CPU_24MHZ_N<8>

PCH_CPU_BCLK_P<8>
PCH_CPU_BCLK_N<8>

RH593

CLKREQ_PCIE#2<40>
CLKREQ_PCIE#3<41>

CLKREQ_PCIE#5<36>
CLKREQ_PCIE#6<39>
CLKREQ_PCIE#7<23>

PCH_SPI_0_SI<20,45>

PCH_SPI_0_SO<45>

RH582

1

PCH_SPI_0_WP#<20>

2

PCH_SPI_0_CS#2<45>

FFS_INT2<39>
TPM_PIRQ#<45>

RH101 0_0402_5%@

PCH_SPI_0_CLK_ROM

PCH_SPI_0_SI_R
PCH_SPI_0_WP#_R
PCH_SPI_0_HOLD#_RPCH_SPI_0_HOLD#

4 5
3 6
2 7
1 8

10K_0804_8P4R_5%

D D

+3V_ROM

1 2

4.7K_0402_5%

+3VALW_PCH

1 2

10K_0402_5%

+3VALW_PCH

1 2

4.7K_0402_5%

This signal has a weak internal pull-down.
0 = Master Attached Flash Sharing (MAFS) enabled (Default)
1 = Slave Attached Flash Sharing (SAFS) enabled.
Notes:

C C

1. This signal is in the primary well.
Warning: This strap must be configured to ‘0’ if the
eSPI or LPC strap is configured to ‘0’

RH582

15_0402_5%

SD028150A80

B B

A A

1 2

RH610

100K_0402_5%

+3V_ROM

#571182_CNL_PCH_H_EDS_Rev0p7

RH3 100K_0402_5%

RH4 100K_0402_5%

RH583 100K_0402 _5%

+3VALW_PCH

RH99 100K_0402_5%

#571182_CNL_PCH_H_EDS_V1_Rev0.5
External pull-up is required. Recommend 100K if pulled
up to 3.3V or 75K if pulled up to 1.8V.

1 2

60.4_0402_1%

1 2

@EMI@

15_0402_5%

1 2

T92PAD@

CPU_24MHZ_P
CPU_24MHZ_N

PCH_CPU_BCLK_P
PCH_CPU_BCLK_N

XTAL24_OUT
XTAL24_IN

XCLK_BIASREF

PCH_RTCX1
PCH_RTCX2

CLKREQ_PCIE#2
CLKREQ_PCIE#3

CLKREQ_PCIE#5
CLKREQ_PCIE#6
CLKREQ_PCIE#7

T17PAD@

T4943PAD@
T4944PAD@

PCH_SPI_0_SI
PCH_SPI_0_SO
PCH_SPI_0_CS#0
PCH_SPI_0_CLK

PCH_SPI_0_WP#
PCH_SPI_0_HOLD#
PCH_SPI_0_CS#2

FFS_INT2
TPM_PIRQ#

PCH_SPI_0_CS#_R
PCH_SPI_0_SO_R
PCH_SPI_0_WP#_R

SPI ROM

UH2G

BE33

GPP_A16/CLKOUT_48

D7

CLKOUT_CPUNSSC_P

C6

CLKOUT_CPUNSSC#

B8

CLKOUT_CPUBCLK_P

C8

CLKOUT_CPUBCLK#

U9

XTAL_OUT

U10

XTAL_IN

T3

XCLK_BIASREF

BA49

RTCX1

BA48

RTCX2

BF31

GPP_B5/SRCCLKREQ0#

BE31

GPP_B6/SRCCLKREQ1#

AR32

GPP_B7/SRCCLKREQ2#

BB30

GPP_B8/SRCCLKREQ3#

BA30

GPP_B9/SRCCLKREQ4#

AN29

GPP_B10/SRCCLKREQ5#

AE47

GPP_H0/SRCCLKREQ6#

AC48

GPP_H1/SRCCLKREQ7#

AE41

GPP_H2/SRCCLKREQ8#

AF48

GPP_H3/SRCCLKREQ9#

AC41

GPP_H4/SRCCLKREQ10#

AC39

GPP_H5/SRCCLKREQ11#

AE39

GPP_H6/SRCCLKREQ12#

AB48

GPP_H7/SRCCLKREQ13#

AC44

GPP_H8/SRCCLKREQ14#

AC43

GPP_H9/SRCCLKREQ15#

V2

CLKOUT_PCIE_N15

V3

CLKOUT_PCIE_P15

T2

CLKOUT_PCIE_N14

T1

CLKOUT_PCIE_P14

AA1

CLKOUT_PCIE_N13

Y2

CLKOUT_PCIE_P13

AC7

CLKOUT_PCIE_N12

AC6

CLKOUT_PCIE_P12

CNP-H_BGA874

UH2A

BE36

GPP_A11/PME#/SD_VDD2_PWR_EN#

R15

RSVD2

R13

RSVD1

AL37

VSS

AN35

TP

AU41

SPI0_MOSI

BA45

SPI0_MISO

AY47

SPI0_CS0#

AW47

SPI0_CLK

AW48

SPI0_CS1#

AY48

SPI0_IO2

BA46

SPI0_IO3

AT40

SPI0_CS2#

BE19

GPP_D1/SPI1_CLK/SBK1_BK1

BF19

GPP_D0/SPI1_CS#/SBK0_BK0

BF18

GPP_D3/SPI1_MOSI/SBK3_BK3

BE18

GPP_D2/SPI1_MISO/SBK2_BK2

BC17

GPP_D22/SPI1_IO3

BD17

GPP_D21/SPI1_IO2

CNP-H_BGA874

UH8

1
2
3
4

W25Q128JVSIQ_SO8

SA00005VV20

DVT2.
Change UH8 from SA00009RI10 W25Q256JVEIQ_WSON8_8X6
to SA00005VV20 W25Q128JVSIQ_SO8

Close to UH8

5

4

CNP-H

CLKOUT_ITPXDP#

CLKOUT_ITPXDP_P

CLKOUT_CPUPCIBCLK#

CLKOUT_CPUPCIBCLK_P

CLKOUT_PCIE_N0
CLKOUT_PCIE_P0

CLKOUT_PCIE_N1
CLKOUT_PCIE_P1

CLKOUT_PCIE_N2
CLKOUT_PCIE_P2

CLKOUT_PCIE_N3
CLKOUT_PCIE_P3

CLKOUT_PCIE_N4
CLKOUT_PCIE_P4

CLKOUT_PCIE_N5
CLKOUT_PCIE_P5

CLKOUT_PCIE_N6
CLKOUT_PCIE_P6

CLKOUT_PCIE_N7
CLKOUT_PCIE_P7

CLKOUT_PCIE_N8
CLKOUT_PCIE_P8

CLKOUT_PCIE_N9
CLKOUT_PCIE_P9

CLKOUT_PCIE_N10
CLKOUT_PCIE_P10

CLKOUT_PCIE_N11
CLKOUT_PCIE_P11

7 OF 13

CNP-H

1 OF 13

RH121

@

0_0402_5%

8

VCC

CS#
DO(IO1)
IO2
GND

7

IO

6

CLK

5

DI(IO0)

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

@

Y3
Y4

B6
A6

AJ6
AJ7

AH9
AH10

AE14
AE15

AE6
AE7

AC2
AC3

AB2
AB3

W4
W3

W7
W6

AC14
AC15

U2
U3

AC9
AC11

AE9
AE11

R6

CLKIN_XTAL

Rev1.0

GPP_B13/PLTRST#

GPP_K16/GSXCLK

GPP_K12/GSXDOUT

GPP_K13/GSXSLOAD

GPP_K14/GSXDIN

GPP_K15/GSXSRESET#

GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3

GPP_H18/SML4ALERT#

GPP_H17/SML4DATA

GPP_H16/SML4CLK

GPP_H15/SML3ALERT#

GPP_H14/SML3DATA

GPP_H13/SML3CLK

GPP_H12/SML2ALERT#

GPP_H11/SML2DATA

GPP_H10/SML2CLK

INTRUDER#

+3V_ROM+3VALW_PCH

12

PCH_SPI_0_HOLD#_R
PCH_SPI_0_CLK_ROM
PCH_SPI_0_SI_R

3

PCH_XDP_CLK_N
PCH_XDP_CLK_P

PCH_CPU_PCIBCLK_N
PCH_CPU_PCIBCLK_P

CLK_PCIE_N2
CLK_PCIE_P2

CLK_PCIE_N3
CLK_PCIE_P3

CLK_PCIE_N5
CLK_PCIE_P5

CLK_PCIE_N6
CLK_PCIE_P6

CLK_PEG_N7
CLK_PEG_P7

REFCLK_CNV

@

PCH_PLTRST#

AV29

TBT_FORCE_PWR

Y47

RTD3_CIO_PWR_EN

Y46
Y48
W46
AA45

AL47

TOUCH_SCREEN_PD#

AM45

TOUCHPAD_INTR#

BF32

GC6_THM_DIS#

BC33

AE44
AJ46
AE43

GPP_H15

AC47
AD48
AF47

GPP_H12

AB47
AD47
AE48

BB44

Rev1.0

INTRUDER#

2011/08/25 2012/07/25

2011/08/25 2012/07/25

2011/08/25 2012/07/25

PCH_XDP_CLK_N <20>
PCH_XDP_CLK_P <20>

PCH_CPU_PCIBCLK_N <8>
PCH_CPU_PCIBCLK_P <8>

CLK_PCIE_N2 <40>
CLK_PCIE_P2 <40>

CLK_PCIE_N3 <41>
CLK_PCIE_P3 <41>

CLK_PCIE_N5 <36>
CLK_PCIE_P5 <36>

CLK_PCIE_N6 <39>
CLK_PCIE_P6 <39>

CLK_PEG_N7 <23>
CLK_PEG_P7 <23 >

REFCLK_CNV <41>

12

RN36

CNVI@

10K_0402_5%

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

LAN

NGFF - WLAN

TBT-AR

NGFF - SSD

GPU

XTAL24_OUT XTAL_24M_PCH_OUT

XTAL24_IN

DVT1.
Move RN36 from page 41 to page 14 and
connnet to net REFCLK_CNV.

TBT_FORCE_PWR <36>
RTD3_CIO_PWR_EN <36>

TOUCH_SCREEN_PD# <35>

GC6_THM_DIS# <44>

PCH_PLTRST#

12

RH612

100K_0402_5%

MC74VHC1G08DFT2G_SC70-5

2

SA00000OH00

PCH_RTCX2

PCH_RTCX1

10P_0402_50V

DVT1.
Change CH45, CH46 form 8pF 0402 to 10pF 0402.

1 2

RH570

EMI@

33_0201_5%

1 2

RH569

33_0201_5%

TOUCH_SCREEN_PD#

TOUCHPAD_INTR#

GC6_THM_DIS#

INTRUDER#

TOUCHPAD_INTR# PTP_INT#

EMI@

XTAL_24M_PCH_IN

15P_0402_50V8J

RB751S40_SOD523-2

AZ5125-01HPR7G_SOD523-2

Reserve for ESD

1

2

RH1

1 2

@

0_0402_5%

+3VS

5

VCC

IN1

IN2

GND

3

PCH_PLTRST#

OUT

CH208

UH7

PCH_PLTRST#_EC

4

12

RH77

100K_0402_5%

Title

Title

Title

PCH (2/7) CLK,SPI,PLTRST

PCH (2/7) CLK,SPI,PLTRST

PCH (2/7) CLK,SPI,PLTRST

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

RTC CRYSTAL

1 2

RH70

10M_0402_5%

YH1

32.768KHZ 9PF 20PPM 9H03280012

SJ10000Q400

12

CH45

12

Trace Space: 15 mil
Max Trace Length: 1000 mil

PCH CRYSTAL

1 2

RH72

1M_0402_5%

YH2

24MHZ_12PF_7V24000020

3

3

GND

GND

1

CH47

2

1 2

RH69

10K_0402_5%

1 2

RH179

10K_0402_5%

1 2

RH573

10K_0402_5%

1 2

RH143

1M_0402_5%

DH1

2 1

1 2

100P_0402_50V8J@ESD@

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

2

4

+3VS

+RTCVCC_PCH

PCH_PLTRST#_EC <23,36,39,40,41,44,45>

LA-E993P

LA-E993P

LA-E993P

1

12

CH46
10P_0402_50V

1

1

1

CH48

15P_0402_50V8J

2

PTP_INT# <44,47>

14 78Tuesday, March 06, 2018

14 78Tuesday, March 06, 2018

14 78Tuesday, March 06, 2018

1.0(A00)

1.0(A00)

1.0(A00)

Vinafix.com

5

+3VALW_PCH

D D

C C

B B

A A

1 2

RH21 1K_0402_5%

1 2

RH22 1K_0402_5%

1 2

RH62 499_0402_1%

1 2

RH63 499_0402_1%

+3VS

1 2

RH27 1K_0402_5%

1 2

RH26 1K_0402_5%

1 2

RH86 10K_0402_5%

1 2

RH13 100K_0402_5%

1 2

RH581 100K_0402_5%

1 2

RH613 100K_0402_5%

RTCRST_ON<44,47>

SMBCLK

SMBDATA

RTCRST_ON

100K_0402_5%

2

6 1

SMBCLK
SMBDATA

SML0_SMBCLK
SML0_SMBDATA

PCH_SMBCLK
PCH_SMBDATA
DGPU_PWROK

PCH_RSMRST#
SYS_PWROK
HDA_BIT_CLK

2

G

12

RH571

+3VS

QH4A
DMN65D8LDW-7_SOT363-6

5

3 4

QH4B
DMN65D8LDW-7_SOT363-6

PCH_RTCRST#

13

D

QH6
2N7002K_SOT23-3

S

SB00000EN00

PCH to DDR

PCH_SMBCLK

PCH_SMBDATA

AUD_AZA_CPU_SDO<6>

AUD_AZA_CPU_SDI_R<6>

AUD_AZA_CPU_SCLK<6>

Buffer with Open Drain Output For VTT power control

+3VALW

12

CC298

0.1U_0402_16V7K

UC16

1

ME_FWP<44>

NC

2

A

3

GND

74AUP1G07SE-7_SOT353

SA00007WE00

VR_ON

Service Mode Switch:
Add a switch to ME_FWP signal to unlock the ME region and
allow the entire region of the SPI flash to be updated using FPT.

5

VCC

4

Y

ME_FWP

RH18 1K_0402_5%

H_VCCST_PWRGD

1 2

HDA_SDOUT_R<42>

HDA_SYNC_R<42>

1 2

CH50

10P_0402_25V8J@EMI@

HDA_BIT_CLK_R<42>

HDA_SDIN0<42>

PCH_RSMRST#<20,44>

PCH_SMBCLK <20,21,22,38 ,39>

PCH_SMBDATA <20,21,22,38,39>

H_VCCST_PWRGD <8,20>

HDA_SDOUT

HDA_SDOUT_R HDA_S DOUT

HDA_SYNC_R HDA_SYNC

AUD_AZA_CPU_SCLK

PCH_RSMRST#

ME_FWP PCH has internal 20K PD.

FLASH DESCRIPTOR SECURITY OVERRIDE

Disable ME Protect (ME can be updated)
Enable ME Protect (ME cannot be updated)(Default position)

5

4

Close to PCH

RH146

RH147

CLKREQ_CNV#<41>
CNV_RF_RESET#<41>

DGPU_PWROK<23,69>

RH503
0_0402_5%

RH9
0_0402_5%

GPU_THM_SMBCLK<23,44,45>

GPU_THM_SMBDAT<23,44,45>

+VCCIO_PG<76>

IMVP_VR_PG<71>

ALL_SYS_PWRGD<15,44,61>

IMVP_VR_ON<44>

RH552

10K_0402_5%

SD028100280

RH554

10K_0402_5%

SD028100280

4

RP15

1 8
2 7
3 6
4 5

33_0804_8P4R_5%

1 2

1 2

30_0402_5%

1 2

30_0402_5%

1 2

1 2

GPU ID

N/A
N17P-G0
N17E-G1
N17P-G1

UMA@

UMA@

3

HDA_BIT_CLK

RH57233_0402_5% EMI@

HDA_SDIN0
HDA_SDOUT
HDA_SYNC

AUD_AZA_CPU_SDO_RAUD_AZA_CPU_SDO
AUD_AZA_CPU_SDI_R
AUD_AZA_CPU_SCLK_R

GPU_ID2
GPU_ID1
CLKREQ_CNV#
CNV_RF_RESET#

DGPU_PWROK

PCH_RTCRST#
PCH_SRTCRST#

PCH_PWROK
PCH_RSMRST#_R AC_PRESENT

@

PCH_DPWROK

@

SMBALERT#
SMBCLK
SMBDATA
SML0ALERT#
SML0_SMBCLK
SML0_SMBDATA
SML1ALERT#
GPU_THM_SMBCLK
GPU_THM_SMBDAT

RH103

1 2

@

0_0402_5%

IMVP_VR_PG

ALL_SYS_PWRGD

MC74VHC1G08DFT2G_SC70-5

IMVP_VR_ON

SIO_SLP_S3#

MC74VHC1G08DFT2G_SC70-5

GPU ID2
(GPP_D6)

SA00000OH00

SA00000OH00

1

IN1

2

IN2

1

IN1

2

IN2

GPU ID1

(GPP_D5)
0
0
1
1

RH551

N17P_G0@

RH552

10K_0402_5%

SD028100280

RH554

10K_0402_5%

SD028100280

N17P_G0@

10K_0402_5%

SD028100280

RH553

10K_0402_5%

SD028100280

UH2D

BD11

HDA_BCLK/I2S0_SCLK

BE11

HDA_SDI0/I2S0_RXD

BF12

HDA_SDO/I2S0_TXD

BG13

HDA_SYNC/I2S0_SFRM

BE10

HDA_RST#/I2S1_SCLK

BF10

HDA_SDI1/I2S1_RXD

BE12

I2S1_TXD/SNDW2_DATA

BD12

I2S1_SFRM/SNDW2_CLK

AM2

HDACPU_SDO

AN3

HDACPU_SDI

AM3

HDACPU_SCLK

AV18

GPP_D8/I2S2_SCLK

AW18

GPP_D7/I2S2_RXD

BA17

GPP_D6/I2S2_TXD/MODEM_CLKREQ

BE16

GPP_D5/I2S2_SFRM/CNV_RF_RESET#

BF15

GPP_D20/DMIC_DATA0/SNDW 4_DATA

BD16

GPP_D19/DMIC_CLK0/SNDW4_C LK

AV16

GPP_D18/DMIC_DATA1/SNDW 3_DATA

AW15

GPP_D17/DMIC_CLK1/SNDW3_C LK

BE47

RTCRST#

BD46

SRTCRST#

AY42

PCH_PWROK

BA47

RSMRST#

AW41

DSW_PWRO K

BE25

GPP_C2/SMBALERT#

BE26

GPP_C0/SMBCLK

BF26

GPP_C1/SMBDATA

BF24

GPP_C5/SML0ALERT#

BF25

GPP_C3/SML0CLK

BE24

GPP_C4/SML0DATA

BD33

GPP_B23/SML1ALERT#/PCHHOT#

BF27

GPP_C6/SML1CLK

BE27

GPP_C7/SML1DATA

CNP-H_BGA874

@

+3VS

12

RH180

100K_0402_5%

RH105

1 2

@

0_0402_5%

+3VS

5

UH14

VCC

4

OUT

GND

3

+3VALW

5

UZ21

VCC

4

OUT

GND

3

0
1
0
1

RH551

N17E_G1@

10K_0402_5%

SD028100280

RH553

N17E_G1@

10K_0402_5%

SD028100280

ALL_SYS_PWRGD+VCCIO_PG

PCH_PWROK

12

RH94

10K_0402_5%

VR_ON

12

RZ71

100K_0402_5%

N17P_G1@

N17P_G1@

CNP-H

GPP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF#

GPP_A13/SUSWARN#/SUSPW RDNACK

4 OF 13

ALL_SYS_PWRGD <15,44,61>

VR_ON <71>

+3VS

12

RH551

@

10K_0402_5%

10K_0402_5%

12

RH552

@

10K_0402_5%

10K_0402_5%

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

GPP_A8/CLKRUN#

GPD11/LANPHYPC

GPD9/SLP_WLAN#

DRAM_RESET#

GPP_B2/VRALERT#

GPP_B1/GSPI1_CS1#/TIME_SYNC1

GPP_B0/GSPI0_CS1#

GPP_K17/ADR_COMPLETE

GPP_B11/I2S_MCLK

SYS_PWROK

WAKE#

GPD6/SLP_A#

SLP_LAN#

GPP_B12/SLP_S0#

GPD4/SLP_S3#
GPD5/SLP_S4#

GPD10/SLP_S5#

GPD8/SUSCLK

GPD0/BATLOW#

GPP_A15/SUSACK#

GPD2/LAN_WAKE#

GPD1/ACPRESENT

SLP_SUS#

GPD3/PWRBTN#

SYS_RESET#

GPP_B14/SPKR

CPUPWRGD

ITP_PMODE

PCH_JTAGX
PCH_JTAG_TMS
PCH_JTAG_TDO

PCH_JTAG_TDI

PCH_JTAG_TCK

12

RH553

@

GPU_ID1
GPU_ID2

12

RH554

@

2011/08/25 2012/07/25

2011/08/25 2012/07/25

2011/08/25 2012/07/25

Rev1.0

2

6/18:
PCH_PCIE_WAKE#_XDP
PCH_BATLOW#
LAN_WAKE#
AC_PRESENT are DSW rail

BF36
AV32

BF41

BD42

H_DRAMRST#

BB46
BE32
BF33
BE29
R47
AP29

SYS_PWROK

AU3

PCH_PCIE_WAKE#

BB47

SIO_SLP_A#

BE40
BF40

SIO_SLP_S0#

BC28

SIO_SLP_S3#

BF42

SIO_SLP_S4#

BE42

SIO_SLP_S5#

BC42

BE45

SUSCLK
PCH_BATLOW#

BF44
BE35

ME_SUS_PWR_ACK

BC37

LAN_WAKE#

BG44
BG42
BD39

SIO_PWRBTN#

BE46

SYS_RESET#

AU2
AW29

SPKR
H_CPUPWRGD

AE3

PCH_ITP_PMODE

AL3

PCH_JTAGX CPU_XDP_TCK

AH4

PCH_JTAG_TMS

AJ4

PCH_JTAG_TDO

AH3

PCH_JTAG_TDI

AH2

PCH_JTAG_TCK

AJ3

+RTCVCC_PCH

1 2

RH83 20K_0402_5%

+RTCVCC_PCH

1 2

RH84 20K_0402_5%

H_DRAMRST# <21>

SYS_PWROK <20,44>

1 2

RH114 0_0402_5%@

SIO_SLP_S0# <45>
SIO_SLP_S3# <31,33,35,36,54,55,62>
SIO_SLP_S4# <54,55,63>

SUSCLK <39,41,44>

1 2

RH11 0_0402_5%@

2 1

DV1

SIO_PWRBTN# <20,44>
SYS_RESET# <20>
SPKR <42>
H_CPUPWRGD <8>

PCH_ITP_PMODE <20>

PCH_JTAG_TMS <20>
PCH_JTAG_TDO <20>
PCH_JTAG_TDI <20>
PCH_JTAG_TCK <20>

RTC Reset

CH52

1U_0402_6.3V6K

CH53

1U_0402_6.3V6K

RB751S40_SOD523-2

PCH_SRTCRST#

12

PCH_RTCRST#

12

12

CLRP1

@

SHORT PADS

PCIE_WAKE#

LANWAKE#
ACAV_IN

AZ5125-01HPR7G_SOD523-2

1 2

RH38

Reserve for ESD

CH212

CH209

12

100P_0402_50V8JESD@

12

100P_0402_50V8J@ESD@

PCH_RSMRST#

SYS_RESET#

Reserve for RF please close to UH1

CH51

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

1 2

10P_0402_25V8J@RF@

HDA_SDOUT

@

PCH_PCIE_WAKE#
PCH_BATLOW#
LAN_WAKE#
AC_PRESENT

SYS_RESET#

ME_SUS_PWR_ACK

SIO_SLP_S3#
SIO_SLP_S4#

T4947 PAD

@

T4938 PAD

@

LANWAKE# <44>
ACAV_IN <44,59,60>

0_0402_5%

+3VALW_PCH

1

RH17 1K_0402_5%
RH81 10K_0402_5%
RH181 10K_0402_5%
RH125 100K_0402_5%

RH193 8.2K_0402_5%@

RH67 1M_0402_5%@

RH608 100K_0402_5%
RH609 100K_0402_5%

PCIE_WAKE# <36,40,41,44>

CPU_XDP_TCK <8,20>

1 2

RH66 2.2K_0402_5%@

1 2
1 2
1 2
1 2

1 2

1 2

1 2
1 2

+3VALW_PCH

SMBALERT#

TLS CONFIDENTIALITY

1 2

Enable
Disable

SML0ALERT#

HIGH
LOW(DEFAULT)

+3VALW_PCH

RH64 2.2K_0402_5%

EC interface

1 2

ESPI*
LPC

SML1ALERT#

HIGH
LOW(DEFAULT)

+3VALW_PCH

RH65 150K_0402_5%

PCHHOT#

1 2

Enable
Disable

SPKR

+3VALW_PCH

RH82 2.2K_0402_5%@

HIGH
LOW(DEFAULT)

Top Swap Override (internal PD)

HIGH
LOW(DEFAULT)

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PCH (3/7) PM,HDA,SMB,JTAG

PCH (3/7) PM,HDA,SMB,JTAG

PCH (3/7) PM,HDA,SMB,JTAG

ENABLE
DISABLE

LA-E993P

LA-E993P

LA-E993P

1

15 78Tuesday, March 06, 2018

15 78Tuesday, March 06, 2018

15 78Tuesday, March 06, 2018

+3VALW_PCH

+1.8V_PRIM

1.0(A00)

1.0(A00)

1.0(A00)

Vinafix.com

5

4

3

2

1

DMI_CTX_PRX_N0<6>
DMI_CTX_PRX_P0<6>

DMI_CRX_PTX_N0<6>

DMI_CRX_PTX_P0<6>
DMI_CTX_PRX_N1<6>
DMI_CTX_PRX_P1<6>

DMI_CRX_PTX_N1<6>

DMI_CRX_PTX_P1<6>

D D

C C

B B

Left USB Type-A

Right USB Type-A

Right USB Type-A

DMI_CTX_PRX_N2<6>
DMI_CTX_PRX_P2<6>

DMI_CRX_PTX_N2<6>

DMI_CRX_PTX_P2<6>
DMI_CTX_PRX_N3<6>
DMI_CTX_PRX_P3<6>

DMI_CRX_PTX_N3<6>

DMI_CRX_PTX_P3<6>

USB3_PTX_DRX_N1<51>

USB3_PTX_DRX_P1<51>
USB3_PRX_DTX_N1<51>
USB3_PRX_DTX_P1<51>

USB3_PTX_DRX_N2<52>

USB3_PTX_DRX_P2<52>
USB3_PRX_DTX_N2<52>
USB3_PRX_DTX_P2<52>

USB3_PTX_DRX_P3<52>

USB3_PTX_DRX_N3<52>
USB3_PRX_DTX_P3<52>
USB3_PRX_DTX_N3<52>

DMI_CTX_PRX_N0
DMI_CTX_PRX_P0
DMI_CRX_PTX_N0
DMI_CRX_PTX_P0
DMI_CTX_PRX_N1
DMI_CTX_PRX_P1
DMI_CRX_PTX_N1
DMI_CRX_PTX_P1
DMI_CTX_PRX_N2
DMI_CTX_PRX_P2
DMI_CRX_PTX_N2
DMI_CRX_PTX_P2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P3
DMI_CRX_PTX_N3
DMI_CRX_PTX_P3

USB3_PTX_DRX_N1
USB3_PTX_DRX_P1
USB3_PRX_DTX_N1
USB3_PRX_DTX_P1

USB3_PTX_DRX_N2
USB3_PTX_DRX_P2
USB3_PRX_DTX_N2
USB3_PRX_DTX_P2

USB3_PTX_DRX_P3
USB3_PTX_DRX_N3
USB3_PRX_DTX_P3
USB3_PRX_DTX_N3

UH2B

K34

DMI0_RXN

J35

DMI0_RXP

C33

DMI0_TXN

B33

DMI0_TXP

G33

DMI1_RXN

F34

DMI1_RXP

C32

DMI1_TXN

B32

DMI1_TXP

K32

DMI2_RXN

J32

DMI2_RXP

C31

DMI2_TXN

B31

DMI2_TXP

G30

DMI3_RXN

F30

DMI3_RXP

C29

DMI3_TXN

B29

DMI3_TXP

A25

DMI7_TXP

B25

DMI7_TXN

P24

DMI7_RXP

R24

DMI7_RXN

C26

DMI6_TXP

B26

DMI6_TXN

F26

DMI6_RXP

G26

DMI6_RXN

B27

DMI5_TXP

C27

DMI5_TXN

L26

DMI5_RXP

M26

DMI5_RXN

D29

DMI4_TXP

E28

DMI4_TXN

K29

DMI4_RXP

M29

DMI4_RXN

G17

PCIE1_RXN/USB31_7_RXN

F16

PCIE1_RXP/USB31_7_RXP

A17

PCIE1_TXN/USB31_7_TXN

B17

PCIE1_TXP/USB31_7_TXP

R21

PCIE2_RXN/USB31_8_RXN

P21

PCIE2_RXP/USB31_8_RXP

B18

PCIE2_TXN/USB31_8_TXN

C18

PCIE2_TXP/USB31_8_TXP

K18

PCIE3_RXN/USB31_9_RXN

J18

PCIE3_RXP/USB31_9_RXP

B19

PCIE3_TXN/USB31_9_TXN

C19

PCIE3_TXP/USB31_9_TXP

N18

PCIE4_RXN/USB31_10_RXN

R18

PCIE4_RXP/USB31_10_RXP

D20

PCIE4_TXN/USB31_10_TXN

C20

PCIE4_TXP/USB31_10_TXP

F20

PCIE5_RXN

G20

PCIE5_RXP

B21

PCIE5_TXN

A22

PCIE5_TXP

K21

PCIE6_RXN

J21

PCIE6_RXP

D21

PCIE6_TXN

C21

PCIE6_TXP

B23

PCIE7_TXP

C23

PCIE7_TXN

J24

PCIE7_RXP

L24

PCIE7_RXN

F24

PCIE8_RXN

G24

PCIE8_RXP

B24

PCIE8_TXN

C24

PCIE8_TXP

CNP-H_BGA874

UH2F

F9

USB31_1_TXN

F7

USB31_1_TXP

D11

USB31_1_RXN

C11

USB31_1_RXP

C3

USB31_2_TXN

D4

USB31_2_TXP

B9

USB31_2_RXN

C9

USB31_2_RXP

C17

USB31_6_TXN

C16

USB31_6_TXP

G14

USB31_6_RXN

F14

USB31_6_RXP

C15

USB31_5_TXN

B15

USB31_5_TXP

J13

USB31_5_RXN

K13

USB31_5_RXP

G12

USB31_3_TXP

F11

USB31_3_TXN

C10

USB31_3_RXP

B10

USB31_3_RXN

C14

USB31_4_TXP

B14

USB31_4_TXN

J15

USB31_4_RXP

K16

USB31_4_RXN

CNP-H_BGA874

CNP-H

GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_F15/USB2_OC4#
GPP_F16/USB2_OC5#
GPP_F17/USB2_OC6#
GPP_F18/USB2_OC7#

USB2_VBUSSENSE

2 OF 13

CNP-H

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS0#

GPP_A6/SERIRQ/ESPI_CS1#

GPP_A7/PIRQA#/ESPI_ALERT0#

GPP_A0/RCIN#/ESPI_ALERT1#

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_E6/SATA_DEVSLP2
GPP_E5/SATA_DEVSLP1
GPP_E4/SATA_DEVSLP0
GPP_F9/SATA_DEVSLP7
GPP_F8/SATA_DEVSLP6
GPP_F7/SATA_DEVSLP5
GPP_F6/SATA_DEVSLP4
GPP_F5/SATA_DEVSLP3

6 OF 13

USB2N_1

USB2P_1

USB2N_2

USB2P_2

USB2N_3

USB2P_3

USB2N_4

USB2P_4

USB2N_5

USB2P_5

USB2N_6

USB2P_6

USB2N_7

USB2P_7

USB2N_8

USB2P_8

USB2N_9

USB2P_9
USB2N_10
USB2P_10
USB2N_11
USB2P_11
USB2N_12
USB2P_12
USB2N_13
USB2P_13
USB2N_14
USB2P_14

USB2_COMP

RSVD1

USB2_ID

GPD7

PCIE24_TXP

PCIE24_TXN
PCIE24_RXP
PCIE24_RXN

PCIE23_TXP

PCIE23_TXN
PCIE23_RXP
PCIE23_RXN

PCIE22_TXP

PCIE22_TXN
PCIE22_RXP
PCIE22_RXN

PCIE21_TXP

PCIE21_TXN
PCIE21_RXP
PCIE21_RXN

GPP_K19/SMI#

GPP_K18/NMI#

@

Rev1.0

Rev1.0

USB20_N1

J3

USB20_P1

J2

USB20_N2

N13

USB20_P2

N15

USB20_N3

K4

USB20_P3

K3
M10
L9

USB20_N5

M1

USB20_P5

L2

USB20_N6

K7

USB20_P6

K6

USB20_N7

L4

USB20_P7

L3

USB20_N8

G4

USB20_P8

G5

USB20_N9

M6

USB20_P9

N8
H3
H2
R10
P9
G1
G2
N3
N2
E5
F6

USB_OC0# USB_OC6#

AH36

USB_OC1#

AL40

USB_OC2#

AJ44

USB_OC3#

AL41

USB_OC4#

AV47

USB_OC5#

AR35

USB_OC6#

AR37

USB_OC7#

AV43

USB2_COMP

F4

USB2_VBUSSENSE

F3
U13

USB2_ID

G3

GPD_7

BE41

PCIE_PTX_TRX_P24

G45

PCIE_PTX_TRX_N24

G46

PCIE_PRX_TTX_P24

Y41

PCIE_PRX_TTX_N24

Y40

PCIE_PTX_TRX_P23

G48

PCIE_PTX_TRX_N23

G49

PCIE_PRX_TTX_P23

W44

PCIE_PRX_TTX_N23

W43

PCIE_PTX_TRX_P22

H48

PCIE_PTX_TRX_N22

H47

PCIE_PRX_TTX_P22

U41

PCIE_PRX_TTX_N22

U40

PCIE_PTX_TRX_P21

F46

PCIE_PTX_TRX_N21

G47

PCIE_PRX_TTX_P21

R44

PCIE_PRX_TTX_N21

T43

@

BB39
AW37
AV37
BA38

BE38
AW35
BA36
BE39
BF38

BB36
BB34

T48
T47

AH40
AH35
AL48
AP47
AN37
AN46
AR47
AP48

ESPI_IO0_R
ESPI_IO1_R
ESPI_IO2_R
ESPI_IO3_R

ESPI_CS#
ESPI_ALERT#
PIRQA#

ESPI_RESET#

ESPI_CLK_R

mSATA_DEVSLP
HDD_DEVSLP

USB20_N1 <51>
USB20_P1 <5 1>
USB20_N2 <52>
USB20_P2 <5 2>
USB20_N3 <52>
USB20_P3 <5 2>

USB20_N5 <35>
USB20_P5 <3 5>
USB20_N6 <53>
USB20_P6 <5 3>
USB20_N7 <41>
USB20_P7 <4 1>
USB20_N8 <35>
USB20_P8 <3 5>
USB20_N9 <48>
USB20_P9 <4 8>

USB_OC0# <51>
USB_OC1# <52>

1 2

RH109 113_0402_1%

1 2

RH112 1K_0402_5%

1 2

RH113 1K_0402_5%

PCIE_PTX_TRX_P24 <36>
PCIE_PTX_TRX_N24 <36>

PCIE_PRX_TTX_P24 <36>

PCIE_PRX_TTX_N24 <36>
PCIE_PTX_TRX_P23 <36>
PCIE_PTX_TRX_N23 <36>

PCIE_PRX_TTX_P23 <36>

PCIE_PRX_TTX_N23 <36>
PCIE_PTX_TRX_P22 <36>
PCIE_PTX_TRX_N22 <36>

PCIE_PRX_TTX_P22 <36>

PCIE_PRX_TTX_N22 <36>
PCIE_PTX_TRX_P21 <36>
PCIE_PTX_TRX_N21 <36>

PCIE_PRX_TTX_P21 <36>

PCIE_PRX_TTX_N21 <36>

1 2

RH574 15_0402_5%

1 2

RH575 15_0402_5%

1 2

RH576 15_0402_5%

1 2

RH577 15_0402_5%

ESPI_CS# <44>
ESPI_ALERT# <44 >

ESPI_RESET# < 44>

1 2

RH168

33_0402_5%

mSATA_DEVSLP < 39>
HDD_DEVSLP <39>

EMI@

ESPI_CLK

Left USB Type-A

Right USB Type-A

Right USB Type-A

Camera

Card Reader

M.2-WLAN

Touch Screen

Finger Print

ESPI_IO0 <44>
ESPI_IO1 <44>
ESPI_IO2 <44>
ESPI_IO3 <44>

ESPI_CLK <44>

TBT-AR

USB_OC0#
USB_OC1#
USB_OC3#
USB_OC2#

USB_OC7#
USB_OC5#
USB_OC4#

PIRQA#

ESPI_ALERT#

ESPI_RESET#

RP16

4 5
3 6
2 7
1 8

10K_0804_8P4R_5%

RP8

4 5
3 6
2 7
1 8

10K_0804_8P4R_5%

+3VALW_PCH

GPD_7

STRAP

X'tal Input:
High: Differential
Low: Single ended

1 2

RH546 10K_0402_5%

1 2

RH578 8.2K_0402_5%

1 2

RH611 100K_0402_5%

+3VALW_PCH

+3VALW_PCH

12

RH12

100K_0402_5%

12

RH584

@

10K_0402_5%

6/18:
GPD_7 is DSW rail

+1.8V_PRIM

Reserve for EMI

A A

ESPI_CLK

12

CC4

@EMI@ 12P_0402_50V8J

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

2011/08/25 2012/07/25

2011/08/25 2012/07/25

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PCH (4/7) DMI,PCIE,USB,ESPI

PCH (4/7) DMI,PCIE,USB,ESPI

PCH (4/7) DMI,PCIE,USB,ESPI

LA-E993P

LA-E993P

LA-E993P

1

16 78Tuesday, March 06, 2018

16 78Tuesday, March 06, 2018

16 78Tuesday, March 06, 2018

1.0(A00)

1.0(A00)

1.0(A00)

Vinafix.com

5

DVT1.

+3VS

+3VALW_PCH

D D

Un-pop RH159.

1 2

RH10 10K_0402_5%

1 2

RH159 49.9K_0402_1%@

1 2

RH160 49.9K_0402_1%

1 2

RH119 2.2K_0402_5%

1 2

RH120 2.2K_0402_5%

1 2

RH545 100K_0402_5%

1 2

RH91 10K_0402_5%

1 2

RZ96 100K_0402_5%

1 2

RH567 100K_0402_5%

GPU HDMI HPD.

SIO_EXT_SCI#
UART_2_CTXD_DRXD
UART_2_CRXD_DTXD
I2C_1_SCL
I2C_1_SDA
GPU_GC6_FB_EN_H

SIO_EXT_WAKE#
IR_CAM_DET#

HDMI_HPD_PCH

GPU_GC6_FB_EN_H<23>

GPU_EVENT#<23>

UART_2_CTXD_DRXD<41>

UART_2_CRXD_DTXD<41>

TP

4

BBS_BIT0

SIO_EXT_SCI#

FFS_INT1<39>

BT_RADIO_DIS#<41>

HDMI_HPD_PCH<33>

SIO_EXT_WAKE#<44>

I2C_1_SCL<47>

I2C_1_SDA<47>

FFS_INT1

NRB_BIT

GPU_GC6_FB_EN_H
GPU_EVENT#

BT_RADIO_DIS#

HDMI_HPD_PCH
PHASE_ID2
PHASE_ID1

IR_CAM_DET#
SIO_EXT_WAKE#
UART_2_CTXD_DRXD
UART_2_CRXD_DTXD

I2C_1_SCL
I2C_1_SDA

UH2K

BA26

GPP_B22/GSPI1_MOSI

BD30

GPP_B21/GSPI1_MISO

AU26

GPP_B20/GSPI1_CLK

AW26

GPP_B19/GSPI1_CS0#

BE30

GPP_B18/GSPI0_MOSI

BD29

GPP_B17/GSPI0_MISO

BF29

GPP_B16/GSPI0_CLK

BB26

GPP_B15/GSPI0_CS0#

BB24

GPP_C9/UART0A_TXD

BE23

GPP_C8/UART0A_RXD

AP24

GPP_C11/UART0A_CTS#

BA24

GPP_C10/UART0A_RTS#

BD21

GPP_C15/UART1_CTS#/ISH_UART1_CTS#

AW24

GPP_C14/UART1_RTS#/ISH_UART1_RTS#

AP21

GPP_C13/UART1_TXD/ISH_UART1_TXD

AU24

GPP_C12/UART1_RXD/ISH_UART1_RXD

AV21

GPP_C23/UART2_CTS#

AW21

GPP_C22/UART2_RTS#

BE20

GPP_C21/UART2_TXD

BD20

GPP_C20/UART2_RXD

BE21

GPP_C19/I2C1_SCL

BF21

GPP_C18/I2C1_SDA

BC22

GPP_C17/I2C0_SCL

BF23

GPP_C16/I2C0_SDA

BE15

GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4_BK4

BE14

GPP_D23/ISH_I2C2_SCL/I2C3_SCL

CNP-H_BGA874

3

CNP-H

GPP_D9/ISH_SPI_CS#/GSPI2_CS0#

GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO

GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI

GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN

GPP_D10/ISH_SPI_CLK/GSPI2_CLK

GPP_D16/ISH_UART0_CTS#/CNV_WCEN

GPP_D14/ISH_UART0_TXD/I2C2_SCL

GPP_D13/ISH_UART0_RXD/I2C2_SDA

GPP_H20/ISH_I2C0_SCL
GPP_H19/ISH_I2C0_SDA

GPP_H22/ISH_I2C1_SCL
GPP_H21/ISH_I2C1_SDA

GPP_A23/ISH_GP5
GPP_A22/ISH_GP4
GPP_A21/ISH_GP3
GPP_A20/ISH_GP2
GPP_A19/ISH_GP1

GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7

11 OF 13

GPP_A18/ISH_GP0

Rev1.0

@

BA20
BB20
BB16
AN18

BF14
AR18
BF17
BE17

AG45
AH46

AH47
AH48

AV34
AW32
BA33
BE34
BD34
BF35
BD38

2

DGPU_HOLD_RST#
WLAN_WIGIG60GHZ_DIS#
DGPU_PWR_EN

KB_DET#

DGPU_HOLD_RST# <23>
WLAN_WIGIG60GHZ_DIS# <41>
DGPU_PWR_EN <31>

KB_DET# <46>

DGPU_PWR_EN

KB_DET#

1

1 2

RH129 10K_0402_5%

1 2

RH128 10K_0402_5%

+3VS

+1.8V_PRIM

PCH Strap PIN

C C

CPU_DP1_HPD<36>
CPU_DP2_HPD<36>

EDP_HPD<35>

EDP_HPD

RV551

RH547

10K_0402_5%

RH548

10K_0402_5%

+3VS

12

@

12

@

PHASE ID2 PHASE ID1
(GPP_C13) (GPP_C12)

B B

PHASE ID

A A

EVT
DVT1
DVT2
Pilot

5

12

100K_0402_5%

12

RH549

@

10K_0402_5%

12

RH550

@

10K_0402_5%

0
0
1
1

RH548

10K_0402_5%

SD028100280

PHASE_ID1
PHASE_ID2

RH547

10K_0402_5%

SD028100280

RH548

10K_0402_5%

SD028100280

0

RH547

1
0
1

10K_0402_5%

SD028100280

EVT@

DVT1@

DVT2@

PILOT@

RH550

EVT@

10K_0402_5%

SD028100280

RH550

DVT1@

10K_0402_5%

SD028100280

RH549

DVT2@

10K_0402_5%

SD028100280

RH549

PILOT@

10K_0402_5%

SD028100280

4

CPU_DP1_HPD
CPU_DP2_HPD

EDP_HPD

UH2E

AT6

GPP_I0/DDPB_HPD0/DISP_MISC0

AN10

GPP_I1/DDPC_HPD1/DISP_MISC1

AP9

GPP_I2/DPPD_HPD2/DISP_MISC2

AL15

GPP_I3/DPPE_HPD3/DISP_MISC3

AN6

GPP_I4/EDP_HPD/DISP_MISC4

CNP-H_BGA874

CNP-H

GPP_I6/DDPB_CTRLDATA

GPP_I8/DDPC_CTRLDATA

GPP_I10/DDPD_CTRLDATA

GPP_F23/DDPF_CTRLDATA

GPP_F22/DDPF_CTRLCLK

5 OF 13

GPP_I5/DDPB_CTRLCLK

GPP_I7/DDPC_CTRLCLK

GPP_I9/DDPD_CTRLCLK

GPP_F14/PS_ON#

GPP_K23/IMGCLKOUT1
GPP_K22/IMGCLKOUT0

GPP_H23/TIME_SYNC0

GPP_K21
GPP_K20

Rev1.0

@

AL13
AR8
AN13
AL10
AL9
AR3
AN40
AT49

AP41

M45
L48
T45
T46
AJ47

CPU_DP1_CTRL_DATA

CPU_DP2_CTRL_DATA

T2 PAD@

PROC_DETECT#

+3VALW_PCH +3VALW_PCH

RH130 2.2K_0402_5%@

1 2

PROC_DETECT# <8>

BBS_BIT0

Boot BIOS Strap Bit (internal PD)
HIGH

LOW(DEFAULT)

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/08/25 2012/07/25

2011/08/25 2012/07/25

2011/08/25 2012/07/25

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

LPC
SPI

CPU_DP1_CTRL_DATA

CPU_DP2_CTRL_DATA

1 2

RH92 2.2K_0402_5%@

RH580

RH579

NO REBOOT mode (internal PD)

HIGH
LOW(DEFAULT)

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PCH (5/7) I2C,GPIO,DDC

PCH (5/7) I2C,GPIO,DDC

PCH (5/7) I2C,GPIO,DDC

LA-E993P

LA-E993P

LA-E993P

ENABLE
DISABLE

1

1 2

2.2K_0402_5%

1 2

2.2K_0402_5%

NRB_BIT

17 78Tuesday, March 06, 2018

17 78Tuesday, March 06, 2018

17 78Tuesday, March 06, 2018

+3VS

1.0(A00)

1.0(A00)

1.0(A00)

Vinafix.com

5

4

3

2

1

GPIO Group Voltage

GPPA

@

GPPB
GPPC

GPPD

GPPE
GPPF

GPPG

GPPH

GPPI

GPPJ

12

0_0603_5%

+1P05VALW

1 2

RH123

RH597

D D

RH598

RH600

LH2

RH602

RH607

LH1

C C

@

0_0402_5%

1 2

@

0_0402_5%

1 2

@

0_0402_5%

1 2

@

0_0402_5%

RF@

1 2

BLM15BD601SN1D_2P

1 2

@

0_0402_5%

12

@

0_0402_5%

1 2

BLM15PX221SN1D_2P

+1P05V_VCCPRIM_MPHY

+1P05V_VCCAMPHYPLL

+1P05V_SRC

+1P05V_VCCAPLL

+1P05V_BCLK

+1P05V_XTAL

+3V_HDA+3VALW_PCH

+1P05VALW+1P05V_VCCUSB

+1P05V_VCCPRIM_MPHY

+1P05V_VCCAMPHYPLL

+1P05V_SRC

+1P05V_BCLK

+1P05V_VCCUSB

+1P05V_VCCDSW

+1P05VALW

+1P05V_XTAL

+1P05V_VCCAPLL

+1P05V_VCCAPLL

4.174A

0.33A

0.01A

0.088A

0.114A

0.005A

0.141A

0.034A

0.007A

UH2H

AA22

VCCPRIM_1P051

AA23

VCCPRIM_1P052

AB20

VCCPRIM_1P053

AB22

VCCPRIM_1P054

AB23

VCCPRIM_1P055

AB27

VCCPRIM_1P056

AB28

VCCPRIM_1P057

AB30

VCCPRIM_1P058

AD20

VCCPRIM_1P059

AD23

VCCPRIM_1P0510

AD27

VCCPRIM_1P0511

AD28

VCCPRIM_1P0512

AD30

VCCPRIM_1P0513

AF23

VCCPRIM_1P0516

AF27

VCCPRIM_1P0517

AF30

VCCPRIM_1P0518

U26

VCCPRIM_1P0523

U29

VCCPRIM_1P0524

V25

VCCPRIM_1P0525

V27

VCCPRIM_1P0526

V28

VCCPRIM_1P0527

V30

VCCPRIM_1P0528

V31

VCCPRIM_1P0529

AD31

VCCPRIM_1P0514

AE17

VCCPRIM_1P0515

W22

VCCDUSB_1P051

W23

VCCDUSB_1P052

BG45

VCCDSW_1P051

BG46

VCCDSW_1P052

W31

VCCPRIM_MPHY_1P05

D1

VCCPRIM_1P0521

E1

VCCPRIM_1P0522

C49

VCCAMPHYPLL_1P051

D49

VCCAMPHYPLL_1P052

E49

VCCAMPHYPLL_1P053

P2

VCCA_XTAL_1P051

P3

VCCA_XTAL_1P052

W19

VCCA_SRC_1P051

W20

VCCA_SRC_1P052

C1

VCCAPLL_1P054

C2

VCCAPLL_1P055

V19

VCCA_BCLK_1P05

B1

VCCAPLL_1P051

B2

VCCAPLL_1P052

B3

VCCAPLL_1P053

CNP-H_BGA874

CNP-H

8 OF 13

VCCPRIM_3P32

DCPRTC1
DCPRTC2

VCCPRIM_3P35

VCCSPI

VCCRTC1
VCCRTC2

VCCPGPPG_3P3

VCCPRIM_3P33
VCCPRIM_3P34

VCCPGPPHK1
VCCPGPPHK2
VCCPGPPEF1
VCCPGPPEF2

VCCPGPPD
VCCPGPPBC1
VCCPGPPBC2

VCCPGPPA

VCCPRIM_3P31

VCCDSW_3P31
VCCDSW_3P32

VCCHDA
VCCPRIM_1P83
VCCPRIM_1P84
VCCPRIM_1P85
VCCPRIM_1P86
VCCPRIM_1P87

VCCPRIM_1P81
VCCPRIM_1P82

VCCPRIM_1P0520
VCCPRIM_1P0519

VCCPRIM_1P241
VCCPRIM_1P242

VCCDPHY_1P241
VCCDPHY_1P242
VCCDPHY_1P243

VCCMPHY_SENSE
VSSMPHY_SENSE

Rev1.0

@

AW9

BF47
BG47

V23

AN44

BC49
BD49

AN21
AY8
BB7

AC35
AC36
AE35
AE36

AN24
AN26
AP26

AN32

AT44
BE48
BE49

BB14
AG19
AG20
AN15
AR15
BB11

AF19
AF20

AG31
AF31
AK22
AK23

AJ22
AJ23
BG5

K47
K46

+3VALW_PCH

0.318A+0.582A(CNVi)

+3VALW_PCH

0.00031A

+RTCVCC_PCH

+3VALW_PCH

+3VALW_PCH

+1.8V_PRIM

+3V_PCH_DSW

+3V_HDA

+1.8V_PRIM_LDO

+1P05VALW

+1P24V_VCCDPHY

0.042A

0.145A for VCCGPPG

0.219A

0.145A

0.117A

0.286A

0.085A

0.094A

0.007A

0.152A+0.582A(CNVi)

0.882A

1P05V_VCCMPHY_SENSE
1P05V_VSSMPHY_SENSE

+DCPRTC

1 2

RH615

+3VALW_PCH

+1P24V_VCCLDOSRAM_IN

+1P24V_VCCDPHY_CAP

0_0402_5%

GEN8@

+3VALW_PCH

+3VALW_PCH

eSPI need use +1.8V_PRIM

+3VALW_PCH

+1.8V_PRIM

+3V_PCH_DSW

1 2

RH606

T4945 PAD @
T4946 PAD @

@

0_0402_5%

+RTCVCC

+1.8V_PRIM

1 2

@

0_0402_5%

+3VALW_PCH

RH124

+3VALW_PCH

+3V_PCH_SPI

RH604

1 2

RH605

@

0_0402_5%

+1P24V_VCCDPHY +1P24V_VCCLDOSRAM_IN

eSPI: 1.8V

3.3V

3.3V

3.3V

3.3V

3.3VGPPK

3.3V Only

1.8V Only

+1P05V_VCCAPLL +1P05VALW +1P05V_VCCAMPHYPLL +1P05VALW +1P05VALW +1.8V_PRIM

B B

External Pin Name

VCCAPLL_1P05

VCCPRIM_1P05

VCCA_XTAL_1P05

VCCAMPHYPLL_1P05

VCCDSW_1P05

VCCPRIM_1P8 4.7 uF 0402 x1
VCCPGPPA

VCCPGPPBC
VCCPGPPD
VCCPGPPEF

A A

VCCPGPPHK
VCCPSPI
VCCPRIM_3P3

VCCPDSW_3P3

VCCHDA

VCCRTC 1uF 0402 x1

Cap Number

1uF 0402 x1

0.5P 0402 x1
22 uF 0603 x1

1u 0402 x3
47 uF 0805 x1

47 uF 0805 x1
1uF 0402 x1

1uF 0402 x1 (@)

1uF 0402 x1

0.1uF 0402 x2

0.1uF 0402 x1

0.5P 0402 x1

0.1uF 0402 x1

CH221

CH230

1

1

RF@

0.5P_0402_50V8

1U_0402_6.3V6K

edge cap-5mm
close B1/B2/B3/C1/C2

CH226

Back cap-3mm
close P2/P3

2

2

1

47U_0805_6.3V6M

2

CH177

edge cap-3mm
close U26/U29
V25/V27/V28/V30/V31

CH227

Back cap-3mm
close C49/D49/E49

VCCDPHY_1P24 4.7 uF 0402 x1

5

4

CH180

1

1U_0402_6.3V6K

22U_0603_6.3V6M

2

1

47U_0805_6.3V6M

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CH222

1

2

+3VALW_PCH +3VALW_PCH +3VALW_PCH +3V_PCH_DSW+1P05V_XTAL +1P05V_VCCAMPHYPLL +1P05V_VCCDSW +DCPRTC

CH200

Back cap-3mm
close AE35/AE36

1

1U_0402_6.3V6K

2

edge cap-3mm
close C49/D49/E49

1

0.1U_0402_10V6K

2

2011/08/25 2012/07/25

2011/08/25 2012/07/25

2011/08/25 2012/07/25

3

CH223

1

1U_0402_6.3V6K

2

edge cap-3mm
close AF31/AG31

CH70

1

0.1U_0402_10V6K

2

Back cap-3mm
close AC35/AC36

Compal Secret Data

Compal Secret Data

Compal Secret Data

edge cap-3mm
close AD31/AA22/AA23

CH188

1

1U_0402_6.3V6K

2

Back cap-3mm
close AY8/BB7

Deciphered Date

Deciphered Date

Deciphered Date

CH224

1

1U_0402_6.3V6K

2

CH203

Back cap-3mm
close BE48/BE49

edge cap-3mm
close AG19/AG20
/AR15/AN15/BB11

1

0.1U_0402_10V6K

2

2

CH225

1

4.7U_0402_6.3V6M

2

CH228

1

@

1U_0402_6.3V6K

2

edge cap-5mm
close BG45

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet

+RTCVCC_PCH

CH80

CH173

1

1U_0402_6.3V6K

2

edge cap-3mm
close BC49/BD49

CH229

1

@

1U_0402_6.3V6K

2

edge cap-5mm
close BG47

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

PCH (6/7) PWR

PCH (6/7) PWR

PCH (6/7) PWR

+1P24V_VCCDPHY_CAP

1

0.1U_0402_10V6K

2

LA-E993P

LA-E993P

LA-E993P

CH220

1

4.7U_0402_6.3V6M

2

edge cap-5mm
close BG5

+3V_HDA

CH231

1

RF@

0.5P_0402_50V8

2

close BB14

18 78Tuesday, March 06, 2018

18 78Tuesday, March 06, 2018

18 78Tuesday, March 06, 2018

1

1.0(A00)

1.0(A00)

1.0(A00)

of

Vinafix.com

5

D D

4

3

2

1

CNP-H

UH2I

A2

VSS

A28

VSS

A3

VSS

A33

VSS

A37

VSS

A4

VSS

A45

VSS

A46

VSS

A47

VSS

A48

VSS

A5

VSS

A8

VSS

AA19

VSS

AA20

VSS

AA25

VSS

AA27

VSS

AA28

VSS

AA30

VSS

AA31

VSS

AA49

VSS

AA5

C C

B B

AB19
AB25
AB31
AC12
AC17
AC33
AC38

AC4

AC46

AD19

AD22
AD25
AD49
AE12
AE33
AE38

AE46
AF22
AF25
AF28

AG1
AG22
AG23
AG25
AG27
AG28
AG30
AG49

AH12
AH17
AH33
AH38

AJ19
AJ20
AJ25
AJ27
AJ28
AJ30

AJ31
AK19
AK20
AK25
AK27
AK28
AK30
AK31

AK46

AD1

AD2

AE4

AK4

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

CNP-H_BGA874

9 OF 13

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

Rev1.0

@

AL12
AL17
AL21
AL24
AL26
AL29
AL33
AL38
AM1
AM18
AM32
AM49
AN12
AN16
AN34
AN38
AP4
AP46
AR12
AR16
AR34
AR38
AT1
AT16
AT18
AT21
AT24
AT26
AT29
AT32
AT34
AT45
AV11
AV39
AW10
AW4
AW40
AW46
B47
B48
B49
BA12
BA14
BA44
BA5
BA6
BB41
BB43
BB9
BC10
BC13
BC15
BC19
BC24
BC26
BC31
BC35
BC40
BC45
BC8
BD43
BE44
BF1
BF2
BF3
BF48
BF49
BG17
BG2
BG22
BG25
BG28

BG3
BG33
BG37

BG4
BG48

C12
C25
C30

C48

D12
D16
D17
D30
D33

E10
E13
E15
E17
E19
E22
E24
E26
E31
E33
E35
E40
E42

G44

K11

K39
M16
M18
M21

F41
F43
F47

J10
J26
J29

J40
J46
J47
J48

UH2L

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

C4

VSS
VSS

C5

VSS
VSS
VSS
VSS
VSS
VSS

D8

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

E8

VSS
VSS
VSS
VSS
VSS

G6

VSS

H8

VSS
VSS
VSS
VSS

J4

VSS
VSS
VSS
VSS
VSS

J9

VSS
VSS
VSS
VSS
VSS
VSS

CNP-H_BGA874

CNP-H

12 OF 13

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

Rev1.0

@

M24
M32
M34
M49
M5
N12
N16
N34
N35
N37
N38
P26
P29
P4
P46
R12
R16
R26
R29
R3
R34
R38
R4
T17
T18
T32
T4
T49
T5
T7
U12
U15
U17
U21
U24
U33
U38
V20
V22
V4
V46
W25
W27
W28
W30
Y10
Y12
Y17
Y33
Y38
Y9

CNP-H

UH2J

RSVD7
RSVD8
RSVD6
RSVD5

RSVD3
RSVD4

RSVD2
RSVD1

PREQ#
PRDY#

CPU_TRST#

TRIGGER_OUT

TRIGGER_IN

10 OF 13

CNP-H_BGA874

@

Rev1.0

Y14
Y15
U37
U35

N32
R32

AH15
AH14

AL2
AM5
AM4
AK3
AK2

XDP_PREQ#
XDP_PRDY#
CPU_XDP_TRST#
PCH_TRIGGER
CPU_TRIGGER

XDP_PREQ# <8,20>
XDP_PRDY# <8,20>
CPU_XDP_TRST# <8,20 >
PCH_TRIGGER <8>
CPU_TRIGGER <8>

A A

Security Classification

Security Classification

Security Classification

2011/08/25 2012/07/25

2011/08/25 2012/07/25

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/08/25 2012/07/25

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PCH (7/7) VSS

PCH (7/7) VSS

PCH (7/7) VSS

LA-E993P

LA-E993P

LA-E993P

19 78Tuesday, March 06, 2018

19 78Tuesday, March 06, 2018

19 78Tuesday, March 06, 2018

1

1.0(A00)

1.0(A00)

1.0(A00)

Vinafix.com

5

+VCCSTG

1 2

RH497 51_0402_5%

1 2

D D

C C

RH496 51_0402_5%

1 2

RH56 51_0402_5%

1 2

RH95 51_0402_5%@

1 2

RH61 51_0402_5%

1 2

RH60 51_0402_5%@

+1P05V_XDP

1 2

RH520 2.2K_0402_5%

+VCCST

1 2

RH97 51_0402_5%@

1 2

RH98 51_0402_5%@

1 2

RH100 51_0402_5%@

+3VALW_PCH

1 2

RH521 2.2K_0402_5%

CPU_XDP_TDO

CPU_XDP_TMS

CPU_XDP_TDI

PCH_JTAG_TCK

CPU_XDP_TCK

CPU_XDP_TRST#

XDP_PLTRST#

PCH_JTAG_TDO

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_SYS_PWROK_XDP

Pin XDP Signal Name I/OTarget Signal Device

1 XDP Pin#1 Refer

3 OBSFN_A0 PROC_PREQ# O Coffee Lake

XDP_PRESENT#
routing guidelines

NA Coffee Lake

5 OBSFN_A1 PROC_PRDY# I Coffee Lake

7 GND GND NA

OBSDATA_A0 CFG[0]9 Coffee LakeI/O

OBSDATA_A1 CFG[1]11 Coffee LakeI/O

13 GND GND NA

OBSDATA_A2 CFG[2]15 Coffee LakeI/O

OBSDATA_A3 CFG[3] Coffee Lake17 I/O

B B

GND GND19 NA

OBSFN_B0 BPM#[0] Coffee Lake

21 I/O

OBSFN_B1 BPM#[1] Coffee Lake23 I/O

GND GND25 NA

OBSDATA_B0 CFG[4] Coffee Lake27 I/O

OBSDATA_B1 CFG[5] Coffee LakeI/O29

GND GND NA31

OBSDATA_B2 CFG[6] Coffee Lake33 I/O

OBSDATA_B3 CFG[7] Coffee LakeI/O35

GND GND NA37

HOOK0 RSMRST# Coffee LakeI39

HOOK1 PWRBTN# Coffee LakeO41

VCC_OBS_AB PCH V1.0A43 NA

HOOK2 Open NA

45

HOOK3

A A

GND GND NA49

SPIO_MOSI Coffee LakeO47

XDP_SDA SDA system51 I/O

XDP_SCL SCL I/O53 system

XDP_TCK1 PCH_JTAG_TCK O55 Coffee Lake

XDP_TCK0 PROC_TCK

JTAGX

O57 Coffee Lake

GND GND NA59

5

4

CFG[0..19]<8>

CFG3

RH517 1K_0402_5%XDP@

XDP_PREQ#<8,19>

XDP_PRDY#<8,19>

XDP_BPM#0<8>
XDP_BPM#1<8>

PCH_SMBDATA<15,21,22,38,39>

PCH_SMBCLK<15,21,22,38,39>

PCH_JTAG_TCK<15>
CPU_XDP_TCK<8,15>

+VCCIO

1 2

RH526 150_0402_5%@

+3VALW_PCH

1 2

RH540 1K_0402_5%XDP@

1 2

RH529 1K_0402_5%XDP@

+3VS

1 2

RH531 1K_0402_5%

4

1 2

RH614 0_0402_5%@

12

CH206

@

0.1U_0402_10V7K

3

+1P05V_XDP +1P05V_XDP

JXDP1

2

XDP_PREQ#
XDP_PRDY#

CFG0
CFG1

CFG2
CFG3

XDP_BPM#0
XDP_BPM#1

CFG4
CFG5

CFG6
CFG7

XDP_PWRGOOD
PWRBTN#_XDP

PWR_DEBUG#_XDP
PCH_SYS_PWROK_XDP

PCH_SMBDATA
PCH_SMBCLK
PCH_JTAG_TCK
CPU_XDP_TCK

PWR_DEBUG#_XDP

XDP_PRESENT#

PWRBTN#_XDP

XDP_DBRESET#

1

2

12

RH518

@

0_0402_5%

PCH_JTAG_TDO

PCH_JTAG_TDI

PCH_JTAG_TMS

XDP_TRST#

1

2

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

112

4

334

6

556

8

778

10

9910

12

111112

14

131314

16

151516

18

171718

20

191920

22

212122

24

232324

26

252526

28

272728

30

292930

32

313132

34

333334

36

353536

38

373738

40

393940

42

414142

44

434344

46

454546

48

474748

50

494950

52

515152

54

535354

56

555556

58

575758

60

595960

CONN@

SAMTE_BSH-030-01-L-D-A-TR

SAMTE_BSH-030-01-LDA-TR_60P-NPM

SP02000L900

1 2

RH533 0_0402_5%@

1 2

RH534 0_0402_5%@

1 2

RH535 0_0402_5%@

1 2

RH536 0_0402_5%@

1 2

RH528 1K_0402_5%

1 2

RH519 1K_0402_5%XDP@

1 2

RH530 0_0402_5%XDP@

1 2

RH532 0_0402_5%@

CH207

XDP@

0.1U_0402_10V7K

2017/01/06 2018/01/06

2017/01/06 2018/01/06

2017/01/06 2018/01/06

3

CFG17
CFG16

CFG8
CFG9

CFG10
CFG11

CFG19
CFG18

CFG12
CFG13

CFG14
CFG15

PCH_XDP_CLK_P
PCH_XDP_CLK_N

XDP_PLTRST#
XDP_DBRESET#

PCH_JTAG_TDO
XDP_TRST#
PCH_JTAG_TDI
PCH_JTAG_TMS
XDP_PRESENT#

CFG0

Compal Secret Data

Compal Secret Data

Compal Secret Data

+1P05V_XDP+1P05VALW

1

CH205

XDP@

0.1U_0402_10V7K

2

PCH_XDP_CLK_P <14>
PCH_XDP_CLK_N <14>

PCH_JTAG_TDO <15>

PCH_JTAG_TDI <15>
PCH_JTAG_TMS <15>

PCH

CPU

CPU_XDP_TDO <8>

CPU_XDP_TDI <8>

CPU_XDP_TMS <8>

CPU_XDP_TRST# <8,19 >

PCH_SPI_0_WP# <14>

SIO_PWRBTN# <15,44>

SYS_RESET# <15>

Deciphered Date

Deciphered Date

Deciphered Date

2

2

XDP_PLTRST#

PCH_SYS_PWROK_XDP

XDP_PWRGOOD

Pin XDP Signal Name I/OTarget Signal Device

2 GND GND NA

6 OBSFN_C1 CFG(16) I Coffee Lake

8 GND GND NA

22

46 Coffee Lake

52 I Coffee Lake

54 O Coffee Lake

1

12

RH5220_0402_5% XDP@

12

RH5231K_0402_5% @

12

RH5240_0402_5% @

12

RH5251K_0402_5% XDP@

12

RH5411K_0402_5% XDP@

12

RH5421K_0402_5% @

PCH_ITP_PMODE <15>

PLTRST_CPU# <8,13>

SYS_PWROK <15,44>

PCH_SPI_0_SI <14,45>

PCH_RSMRST# <15,44>

H_VCCST_PWRGD <8,15>

OBSFN_C0 CFG(17)4 I Coffee Lake

OBSDATA_C0 CFG[8]10 Coffee LakeI/O

OBSDATA_C1 CFG[9]12 Coffee LakeI/O

GND GND14 NA

OBSDATA_C2 CFG[10] Coffee Lake16 I/O

OBSDATA_C3 CFG[11] Coffee LakeI/O18

GND GND NA20

OBSFN_D0 CFG(19) I Coffee Lake

OBSFN_D1 CFG(18) I Coffee Lake24

GND GND NA26

OBSDATA_D0 CFG[12] Coffee Lake28 I/O

OBSDATA_D1 CFG[13] Coffee Lake30 I/O

GND GND NA32

OBSDATA_D2 CFG[14] Coffee Lake34 I/O

OBSDATA_D3 CFG[15] Coffee LakeI/O36

GND GND NA38

ITPCLK/HOOK4 CLKOUT_ITPXDP_P Coffee LakeI

ITPCLK#/HOOK540CLKOUT_ITPXDP_N Coffee Lake42 I

VCC_OBS_AB PCH V1.0A NA44

HOOK6/RESET# ITP_PMODE I

HOOK7/DBR# SYS_RESET# Coffee LakeO48

GND GND NA50

XDP_TDO PROC_TDO

XDP_TRSTn PROC_TRST#

XDP_TDI PROC_TDI

XDP_TMS PROC_TMS

GND
(XDP_PRESENT#)

Title

Title

Title

XDP CONN

XDP CONN

XDP CONN

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

PCH_JTAG_TDO

PCH_TRST#

PCH_JTAG_TDI

PCH_JTAG_TMS
Refer

XDP_PRESENT#
routing guidelines

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

LA-E993P

LA-E993P

LA-E993P

O56 Coffee Lake

O58 Coffee Lake

NA60 system

20 78Tuesday, March 06, 2018

20 78Tuesday, March 06, 2018

20 78Tuesday, March 06, 2018

1

1.0(A00)

1.0(A00)

1.0(A00)

Vinafix.com

5

DDR_A_D[0..63]<7>
DDR_A_MA[0..13]<7>
DDR_A_DQS#[0..7]<7>
DDR_A_DQS[0..7]<7>

Layout Note:
Place near JDIMM1.257,259

D D

+2.5V_MEM +3VS+0.6VS

CD10

CD3

CD9

1

10U_0603_6.3V6M

10U_0603_6.3V6M

2

Layout Note:
Place near JDIMM1

CD4

1

1

1

1U_0402_6.3V6K

1U_0402_6.3V6K

2

2

2

Layout Note:
Place near JDIMM1.258

CD12

CD13

CD14

1

1

1U_0402_6.3V6K

2

1

10U_0603_6.3V6M

10U_0603_6.3V6M

2

2

+1.2V_DDR

CD2

CD75

CD74

CD1

1

1

1U_0402_6.3V6K

1U_0402_6.3V6K

2

C C

2

CD77

1

1

1U_0402_6.3V6K

1U_0402_6.3V6K

2

2

CD79

CD76

1

1U_0402_6.3V6K

2

CD78

1

1

1U_0402_6.3V6K

2

1

1U_0402_6.3V6K

1U_0402_6.3V6K

2

2

+1.2V_DDR

CD7

CD6

CD5

1

1

10U_0603_6.3V6M

10U_0603_6.3V6M

2

2

CD70

CD71

CD72

CD8

1

10U_0603_6.3V6M

2

1

1

10U_0603_6.3V6M

10U_0603_6.3V6M

2

2

CD73

1

1

10U_0603_6.3V6M

2

1

10U_0603_6.3V6M

10U_0603_6.3V6M

2

2

+1.2V_DDR

12

B B

DDR4_DRAMRST#<22> H_DRAMRST# <15>

RH45

1 2

2_0402_1%

+1.2V_DDR

12

12

RH206
1K_0402_1%

+V_DDR_REFA

RH209
1K_0402_1%

+V_DDR_REFA_R

20mil

1

CH101

0.022U_0402_16V7K

2

12

RH211

A A

24.9_0402_1%

1

CD97

@ESD@

.1U_0402_16V7K

2

1 2

RD31

@

0_0402_5%

RD35

470_0402_1%

H_DRAMRST#DDR4_DRAMRST#

1

CD69

@ESD@

.1U_0402_16V7K

2

DIMM_CHA_SA2

DIMM_CHA_SA1

DIMM_CHA_SA0

4

Layout Note:
Place near JDIMM1.255

CD15

1

10U_0603_6.3V6M

2

CD17

CD16

1

1

2.2U_0402_6.3V6M

0.1U_0402_10V6K

2

2

Layout Note:
PLACE THE CAP near
JDIMM1. 164

+V_DDR_REFA

CD11

@

DDR4_DRAMRST#

2.2uF*1

0.1uF*1

CD98

2

2

@

2.2U_0402_6.3V6M

0.1U_0402_10V6K

1

1

CD99

@

2

0.1U_0402_10V6K

1

PLACE NEAR TO SODIMM

1

CD103

@

1U_0402_6.3V6K

2

+2.5V_MEM

3

+1.2V_DDR

JDIMM1

1

VSS1

3

DQ5

5

DDR_A_D0

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D7

DDR_A_D3

DDR_A_D13

DDR_A_D12

DDR_A_D15 DDR_A_D10

DDR_A_D14 DDR_A_D11

DDR_A_D37

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D38

DDR_A_D34

DDR_A_D45

DDR_A_D44

DDR_A_D46

DDR_A_CKE0<7>

DDR_A_BG1<7>
DDR_A_BG0<7>

DDR_A_CLK0<7>
DDR_A_CLK#0<7>

DDR_A_PAR<7>
DDR_A_BA1<7>

DDR_A_CS#0<7>
DDR_A_MA14_WE#<7>

DDR_A_ODT0<7>
DDR_A_CS#1<7>

DDR_A_ODT1<7>

DDR_A_CKE0

DDR_A_BG1
DDR_A_BG0

DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA6

DDR_A_MA3
DDR_A_MA1

DDR_A_CLK0
DDR_A_CLK#0

DDR_A_PAR
DDR_A_BA1

DDR_A_CS#0
DDR_A_MA14_WE#

DDR_A_ODT0
DDR_A_CS#1

DDR_A_ODT1

DDR_A_D20

DDR_A_D21

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18

DDR_A_D19

DDR_A_D25

DDR_A_D24

+1.2V_DDR

DDR_A_D29

DDR_A_D49

DDR_A_D48

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D53

DDR_A_D51

DDR_A_D60

+1.2V_DDR

+3VS

PCH_SMBCLK<15,20,22,38,39>

DDR_A_D57

DDR_A_D56

DDR_A_D61 DDR_A_D58

PCH_SMBCLK

VSS3

7

DQ1

9

VSS5

11

DQS0_c

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16

33

DM1_n/DBI_n

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25

53

DQS2_c

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36

75

DM3_n/DBI3_n

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45

95

DQS8_c

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

CS0_n

151

WE_n/A14

153

VDD15

155

ODT0

157

CS1_n

159

VDD17

161

ODT1

163

VDD19

165

C1, CS3_n,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

DEREN_40-42271-26001RHF
CONN@

SP07001CW00

VSS2

VSS4

VSS6

DM0_n/DBI0_n

VSS7

VSS9

VSS11

DQ12

VSS13

VSS15

DQS1_c

DQS1_t

VSS18

DQ14

VSS20

DQ11

VSS22

DQ20

VSS24

DQ16

VSS26

DM2_n/DBI2_n

VSS27

DQ22

VSS29

DQ18

VSS31

DQ28

VSS33

DQ24

VSS35

DQS3_c

DQS3_t

VSS38

DQ31

VSS40

DQ27

VSS42

CB4/NC

VSS44

CB0/NC

VSS46

DM8_n/DBI_n/NC

VSS47

CB6/NC

VSS49

CB7/NC

VSS51

RESET_n

CKE1
VDD2

ACT_n

ALERT_n

VDD4

VDD6

VDD8

EVENT_n/NF

VDD10
CK1_t/NF
CK1_c/NF

VDD12

A10/AP

VDD14

RAS_n/A16

VDD16

CAS_n/A15

VDD18

C0/CS2_n/NC

VREFCA

VSS54

DQ36

VSS56

DQ32

VSS58

DM4_n/DBI4_n

VSS59

DQ39

VSS61

DQ35

VSS63

DQ45

VSS65

DQ41

VSS67

DQS5_c

DQS5_t

VSS70

DQ47

VSS72

DQ43

VSS74

DQ53

VSS76

DQ48

VSS78

DM6_n/DBI6_n

VSS79

DQ54

VSS81

DQ50

VSS83

DQ60

VSS85

DQ57

VSS87

DQS7_c

DQS7_t

VSS90

DQ63

VSS92

DQ59

VSS94

GND2

2

1

+1.2V_DDR

2

DDR_A_D1DDR_A_D4

4

DQ4

6

DDR_A_D5

8

DQ0

10
12
14

DDR_A_D6

16

DQ6

18

DDR_A_D2

20

DQ2

22

DDR_A_D9

24
26

DDR_A_D8

28

DQ8

30

DDR_A_DQS#1

32

DDR_A_DQS1

34
36
38
40
42
44

DDR_A_D32

46
48

DDR_A_D33DDR_A_D36

50
52
54
56

DDR_A_D35

58
60

DDR_A_D39

62
64

DDR_A_D40

66
68

DDR_A_D41

70
72

DDR_A_DQS#5

74

DDR_A_DQS5

76
78

DDR_A_D42DDR_A_D43

80
82

DDR_A_D47

84
86
88
90
92
94
96
98
100
102
104
106

DDR4_DRAMRST#

108

DDR_A_CKE1

110
112

DDR_A_ACT#

114

DDR_A_ALERT#

116
118

DDR_A_MA11

120

A11

DDR_A_MA7

122

A7

124

DDR_A_MA5

126

A5

DDR_A_MA4

128

A4

130

DDR_A_MA2

132

A2

134
136

DDR_A_CLK1

138

DDR_A_CLK#1

140
142

DDR_A_MA0

144

A0

DDR_A_MA10

146
148

DDR_A_BA0

150

BA0

DDR_A_MA16_RAS#

152
154

DDR_A_MA15_CAS#

156

DDR_A_MA13

158

A13

160
162
164

DIMM_CHA_SA2

166

SA2

168

DDR_A_D17

170
172

DDR_A_D16

174
176
178
180

DDR_A_D22

182
184

DDR_A_D23

186
188

DDR_A_D26

190
192

DDR_A_D30

194
196

DDR_A_DQS#3

198

DDR_A_DQS3

200
202

DDR_A_D31DDR_A_D27

204
206

DDR_A_D28

208
210

DDR_A_D50

212
214

DDR_A_D54

216
218
220
222

DDR_A_D52

224
226

DDR_A_D55

228
230

DDR_A_D59

232
234

DDR_A_D62

236
238

DDR_A_DQS#7

240

DDR_A_DQS7

242
244

DDR_A_D63

246
248
250
252

PCH_SMBDATA

254

SDA

DIMM_CHA_SA0

256

SA0

258

VTT

DIMM_CHA_SA1

260

SA1

262

DDR_A_CKE1 <7>

DDR_A_ACT# <7>
DDR_A_ALERT# <7>

DDR_A_CLK1 <7>
DDR_A_CLK#1 <7>

DDR_A_BA0 <7>
DDR_A_MA16_RAS# <7>

DDR_A_MA15_CAS# <7>

CD96

+1.2V_DDR

+1.2V_DDR

PCH_SMBDATA <15,20,22,38,39>

+V_DDR_REFA

1

0.1U_0402_10V6K

All VREF traces should
have 10 mil trace width

2

+0.6VS

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/08/25 2012/07/25

2011/08/25 2012/07/25

2011/08/25 2012/07/25

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

DDR4 DIMMA

DDR4 DIMMA

DDR4 DIMMA

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

LA-E993P

LA-E993P

LA-E993P

1

21 78Tuesday, March 06, 2018

21 78Tuesday, March 06, 2018

21 78Tuesday, March 06, 2018

1.0(A00)

1.0(A00)

1.0(A00)

Vinafix.com

5

DDR_B_D[0..63]<7>
DDR_B_MA[0..13]<7>
DDR_B_DQS#[0..7]<7>
DDR_B_DQS[0..7]<7>

Layout Note:
Place near JDIMM2.257,259

D D

+2.5V_MEM +0.6VS +3VS

CD30

CD31

CD27

1

1U_0402_6.3V6K

1U_0402_6.3V6K

2

Layout Note:
Place near JDIMM2

CD28

1

1

1

10U_0603_6.3V6M

10U_0603_6.3V6M

2

2

2

Layout Note:
Place near JDIMM2.258

CD89

CD90

CD32

1

1U_0402_6.3V6K

2

1

1

10U_0603_6.3V6M

10U_0603_6.3V6M

2

2

+1.2V_DDR

CD19

CD20

CD21

1

1U_0402_6.3V6K

1U_0402_6.3V6K

C C

2

CD22

1

1

1U_0402_6.3V6K

2

2

+1.2V_DDR

CD23

CD24

1

10U_0603_6.3V6M

10U_0603_6.3V6M

2

B B

+V_DDR_REFB_R

CD26

CD25

1

1

10U_0603_6.3V6M

2

2

+1.2V_DDR

20mil

RH46

1 2

2_0402_1%

1

CH100

0.022U_0402_16V7K

2

12

RH212

A A

24.9_0402_1%

1U_0402_6.3V6K

10U_0603_6.3V6M

12

12

CD83

1

2

CD87

1

2

RH207
1K_0402_1%

+V_DDR_REFB

RH210
1K_0402_1%

CD81

CD80

CD82

1

1

1U_0402_6.3V6K

2

1

1U_0402_6.3V6K

2

1

1U_0402_6.3V6K

1U_0402_6.3V6K

2

2

SF000003100

CD85

CD84

1

1

10U_0603_6.3V6M

2

1

10U_0603_6.3V6M

10U_0603_6.3V6M

2

2

CD33

CD86

1

330U_2.5V_M

10U_0603_6.3V6M

2

+3VS

DIMM_CHB_SA1

DIMM_CHB_SA2

DIMM_CHB_SA0

4

Layout Note:
Place near JDIMM2.255

CD35

CD88

1

10U_0603_6.3V6M

2

1

+

2

CD34

1

1

2.2U_0402_6.3V6M

0.1U_0402_10V6K

2

2

Layout Note:
PLACE THE CAP near
JDIMM2. 164

+V_DDR_REFB

CD101

@

DDR4_DRAMRST#

2.2uF*1

0.1uF*1

CD100

@

2

2

2.2U_0402_6.3V6M

0.1U_0402_10V6K

1

1

CD102

@

2

0.1U_0402_10V6K

1

PLACE NEAR TO SODIMM

+2.5V_MEM

3

+1.2V_DDR

JDIMM2

1

VSS1

3

DQ5

5

DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D3

DDR_B_D2

DDR_B_D8

DDR_B_D12

DDR_B_D14 DDR_B_D11

DDR_B_D15 DDR_B_D10

DDR_B_D22

DDR_B_D23

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D21

DDR_B_D16

DDR_B_D25

DDR_B_D24

DDR_B_D31

DDR_B_D27 DDR_B_D30

DDR_B_CKE0<7>

DDR_B_BG1<7>
DDR_B_BG0<7>

DDR_B_CLK0<7>
DDR_B_CLK#0<7>

DDR_B_PAR<7>
DDR_B_BA1<7>

DDR_B_CS#0<7>
DDR_B_MA14_WE#<7>

DDR_B_ODT0<7>
DDR_B_CS#1<7>

DDR_B_ODT1<7>

+1.2V_DDR

+1.2V_DDR

+3VS

PCH_SMBCLK<15,20,21,38,39>

DDR_B_CKE0

DDR_B_BG1
DDR_B_BG0

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA6

DDR_B_MA3
DDR_B_MA1

DDR_B_CLK0
DDR_B_CLK#0

DDR_B_PAR
DDR_B_BA1

DDR_B_CS#0
DDR_B_MA14_WE#

DDR_B_ODT0
DDR_B_CS#1

DDR_B_ODT1

DDR_B_D32

DDR_B_D38

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D37

DDR_B_D39

DDR_B_D40

DDR_B_D45

DDR_B_D47 DDR_B_D46

DDR_B_D42

DDR_B_D52

DDR_B_D51

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D55

DDR_B_D50

DDR_B_D61

DDR_B_D57

DDR_B_D63

DDR_B_D58

PCH_SMBCLK

VSS3

7

DQ1

9

VSS5

11

DQS0_c

13

DQS0_t

15

VSS8

17

DQ7

19

VSS10

21

DQ3

23

VSS12

25

DQ13

27

VSS14

29

DQ9

31

VSS16

33

DM1_n/DBI_n

35

VSS17

37

DQ15

39

VSS19

41

DQ10

43

VSS21

45

DQ21

47

VSS23

49

DQ17

51

VSS25

53

DQS2_c

55

DQS2_t

57

VSS28

59

DQ23

61

VSS30

63

DQ19

65

VSS32

67

DQ29

69

VSS34

71

DQ25

73

VSS36

75

DM3_n/DBI3_n

77

VSS37

79

DQ30

81

VSS39

83

DQ26

85

VSS41

87

CB5/NC

89

VSS43

91

CB1/NC

93

VSS45

95

DQS8_c

97

DQS8_t

99

VSS48

101

CB2/NC

103

VSS50

105

CB3/NC

107

VSS52

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

A9

123

VDD5

125

A8

127

A6

129

VDD7

131

A3

133

A1

135

VDD9

137

CK0_t

139

CK0_c

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

CS0_n

151

WE_n/A14

153

VDD15

155

ODT0

157

CS1_n

159

VDD17

161

ODT1

163

VDD19

165

C1, CS3_n,NC

167

VSS53

169

DQ37

171

VSS55

173

DQ33

175

VSS57

177

DQS4_c

179

DQS4_t

181

VSS60

183

DQ38

185

VSS62

187

DQ34

189

VSS64

191

DQ44

193

VSS66

195

DQ40

197

VSS68

199

DM5_n/DBI5_n

201

VSS69

203

DQ46

205

VSS71

207

DQ42

209

VSS73

211

DQ52

213

VSS75

215

DQ49

217

VSS77

219

DQS6_c

221

DQS6_t

223

VSS80

225

DQ55

227

VSS82

229

DQ51

231

VSS84

233

DQ61

235

VSS86

237

DQ56

239

VSS88

241

DM7_n/DBI7_n

243

VSS89

245

DQ62

247

VSS91

249

DQ58

251

VSS93

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

261

GND1

DEREN_40-42271-26001RHF
CONN@

SP07001CW00

VSS2

VSS4

VSS6

DM0_n/DBI0_n

VSS7

VSS9

VSS11

DQ12

VSS13

VSS15

DQS1_c

DQS1_t

VSS18

DQ14

VSS20

DQ11

VSS22

DQ20

VSS24

DQ16

VSS26

DM2_n/DBI2_n

VSS27

DQ22

VSS29

DQ18

VSS31

DQ28

VSS33

DQ24

VSS35

DQS3_c

DQS3_t

VSS38

DQ31

VSS40

DQ27

VSS42

CB4/NC

VSS44

CB0/NC

VSS46

DM8_n/DBI_n/NC

VSS47

CB6/NC

VSS49

CB7/NC

VSS51

RESET_n

CKE1
VDD2

ACT_n

ALERT_n

VDD4

VDD6

VDD8

EVENT_n/NF

VDD10
CK1_t/NF
CK1_c/NF

VDD12

A10/AP

VDD14

RAS_n/A16

VDD16

CAS_n/A15

VDD18

C0/CS2_n/NC

VREFCA

VSS54

DQ36

VSS56

DQ32

VSS58

DM4_n/DBI4_n

VSS59

DQ39

VSS61

DQ35

VSS63

DQ45

VSS65

DQ41

VSS67

DQS5_c

DQS5_t

VSS70

DQ47

VSS72

DQ43

VSS74

DQ53

VSS76

DQ48

VSS78

DM6_n/DBI6_n

VSS79

DQ54

VSS81

DQ50

VSS83

DQ60

VSS85

DQ57

VSS87

DQS7_c

DQS7_t

VSS90

DQ63

VSS92

DQ59

VSS94

GND2

2

1

+1.2V_DDR

2

DDR_B_D5DDR_B_D0

4

DQ4

6

DDR_B_D4

8

DQ0

10
12
14

DDR_B_D7

16

DQ6

18

DDR_B_D6

20

DQ2

22

DDR_B_D9

24
26

DDR_B_D13

28

DQ8

30

DDR_B_DQS#1

32

DDR_B_DQS1

34
36
38
40
42
44

DDR_B_D18

46
48

DDR_B_D19

50
52
54
56

DDR_B_D20

58
60

DDR_B_D17

62
64

DDR_B_D28

66
68

DDR_B_D29

70
72

DDR_B_DQS#3

74

DDR_B_DQS3

76
78

DDR_B_D26

80
82
84
86
88
90
92
94
96
98
100
102
104
106

DDR4_DRAMRST#

108

DDR_B_CKE1

110
112

DDR_B_ACT#

114

DDR_B_ALERT#

116
118

DDR_B_MA11

120

A11

DDR_B_MA7

122

A7

124

DDR_B_MA5

126

A5

DDR_B_MA4

128

A4

130

DDR_B_MA2

132

A2

134
136

DDR_B_CLK1

138

DDR_B_CLK#1

140
142

DDR_B_MA0

144

A0

DDR_B_MA10

146
148

DDR_B_BA0

150

BA0

DDR_B_MA16_RAS#

152
154

DDR_B_MA15_CAS#

156

DDR_B_MA13

158

A13

160
162
164

DIMM_CHB_SA2

166

SA2

168

DDR_B_D34

170
172

DDR_B_D36

174
176
178
180

DDR_B_D35

182
184

DDR_B_D33

186
188

DDR_B_D44

190
192

DDR_B_D41

194
196

DDR_B_DQS#5

198

DDR_B_DQS5

200
202
204
206

DDR_B_D43

208
210

DDR_B_D54

212
214

DDR_B_D48

216
218
220
222

DDR_B_D53

224
226

DDR_B_D49

228
230

DDR_B_D59

232
234

DDR_B_D62

236
238

DDR_B_DQS#7

240

DDR_B_DQS7

242
244

DDR_B_D60

246
248

DDR_B_D56

250
252

PCH_SMBDATA

254

SDA

DIMM_CHB_SA0

256

SA0

258

VTT

DIMM_CHB_SA1

260

SA1

262

DDR4_DRAMRST# <21>
DDR_B_CKE1 <7>

DDR_B_ACT# <7>
DDR_B_ALERT# <7>

DDR_B_CLK1 <7>
DDR_B_CLK#1 <7>

DDR_B_BA0 <7>
DDR_B_MA16_RAS# <7>

DDR_B_MA15_CAS# <7>

CD29

+1.2V_DDR

+1.2V_DDR

PCH_SMBDATA <15,20,21,38,39>

+V_DDR_REFB

1

0.1U_0402_10V6K

All VREF traces should
have 10 mil trace width

2

+0.6VS

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2011/08/25 2012/07/25

2011/08/25 2012/07/25

2011/08/25 2012/07/25

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

DDR4 DIMMB

DDR4 DIMMB

DDR4 DIMMB

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

LA-E993P

LA-E993P

LA-E993P

1

22 78Tuesday, March 06, 2018

22 78Tuesday, March 06, 2018

22 78Tuesday, March 06, 2018

1.0(A00)

1.0(A00)

1.0(A00)

Vinafix.com

5

PEG_CTX_C_GRX_P[0..15]<6>

PEG_CTX_C_GRX_N[0..15]<6>

PEG_CRX_GTX_P[0..15]<6>

PEG_CRX_GTX_N[0..15]<6>

PEG_CRX_GTX_P0
PEG_CRX_GTX_N0

PEG_CRX_GTX_P1
PEG_CRX_GTX_N1

PEG_CRX_GTX_P2

D D

PEG_CRX_GTX_N2

PEG_CRX_GTX_P3
PEG_CRX_GTX_N3

PEG_CRX_GTX_P4
PEG_CRX_GTX_N4

PEG_CRX_GTX_P5
PEG_CRX_GTX_N5

PEG_CRX_GTX_P6
PEG_CRX_GTX_N6

PEG_CRX_GTX_P7
PEG_CRX_GTX_N7

PEG_CRX_GTX_P8
PEG_CRX_GTX_N8

PEG_CRX_GTX_P9
PEG_CRX_GTX_N9

PEG_CRX_GTX_P10
PEG_CRX_GTX_N10

PEG_CRX_GTX_P11
PEG_CRX_GTX_N11

PEG_CRX_GTX_P12
PEG_CRX_GTX_N12

PEG_CRX_GTX_P13
PEG_CRX_GTX_N13

C C

PEG_CRX_GTX_P14
PEG_CRX_GTX_N14

PEG_CRX_GTX_P15
PEG_CRX_GTX_N15

+1.8V_GFX_AON

12

RV39

@

10K_0402_5%

12

RV573

N17P@

100K_0402_5%

B B

DGPU_PWROK<15,69>

PEG_CTX_C_GRX_P[0..15]

PEG_CTX_C_GRX_N[0..15]

PEG_CRX_GTX_P[0..15]

PEG_CRX_GTX_N[0..15]

N17P@

12

CV531 0.22U_0201_6.3V6M

12

CV532 0.22U_0201_6.3V6M

N17P@

N17P@

12

CV533 0.22U_0201_6.3V6M

12

CV534 0.22U_0201_6.3V6M

N17P@

N17P@

12

CV535 0.22U_0201_6.3V6M

12

CV536 0.22U_0201_6.3V6M

N17P@

N17P@

12

CV537 0.22U_0201_6.3V6M

12

CV538 0.22U_0201_6.3V6M

N17P@

N17P@

12

CV539 0.22U_0201_6.3V6M

12

CV540 0.22U_0201_6.3V6M

N17P@

N17P@

12

CV541 0.22U_0201_6.3V6M

12

CV542 0.22U_0201_6.3V6M

N17P@

N17P@

12

CV543 0.22U_0201_6.3V6M

12

CV544 0.22U_0201_6.3V6M

N17P@

N17P@

12

CV545 0.22U_0201_6.3V6M

12

CV546 0.22U_0201_6.3V6M

N17P@

N17P@

12

CV547 0.22U_0201_6.3V6M

12

CV548 0.22U_0201_6.3V6M

N17P@

N17P@

12

CV550 0.22U_0201_6.3V6M

12

CV551 0.22U_0201_6.3V6M

N17P@

N17P@

12

CV552 0.22U_0201_6.3V6M

12

CV557 0.22U_0201_6.3V6M

N17P@

N17P@

12

CV558 0.22U_0201_6.3V6M

12

CV559 0.22U_0201_6.3V6M

N17P@

N17P@

12

CV560 0.22U_0201_6.3V6M

12

CV561 0.22U_0201_6.3V6M

N17P@

N17P@

12

CV562 0.22U_0201_6.3V6M

12

CV563 0.22U_0201_6.3V6M

N17P@

N17P@

12

CV564 0.22U_0201_6.3V6M

12

CV565 0.22U_0201_6.3V6M

N17P@

N17P@

12

CV566 0.22U_0201_6.3V6M

12

CV567 0.22U_0201_6.3V6M

N17P@

RV40

DGPU_PEX_RST#_RDGPU_PEX_RST#

1 2

@

0_0402_5%

+1.8V_GFX_AON

5

UV19

1VS_GFX_PG

DGPU_PWROK

CLKREQ_PCIE#7<14>

TC7SZ08FU_SSOP5

SA00001DG90

1

B

2

A

3

PEG_CRX_C_GTX_P0
PEG_CRX_C_GTX_N0

PEG_CRX_C_GTX_P1
PEG_CRX_C_GTX_N1

PEG_CRX_C_GTX_P2
PEG_CRX_C_GTX_N2

PEG_CRX_C_GTX_P3
PEG_CRX_C_GTX_N3

PEG_CRX_C_GTX_P4
PEG_CRX_C_GTX_N4

PEG_CRX_C_GTX_P5
PEG_CRX_C_GTX_N5

PEG_CRX_C_GTX_P6
PEG_CRX_C_GTX_N6

PEG_CRX_C_GTX_P7
PEG_CRX_C_GTX_N7

PEG_CRX_C_GTX_P8
PEG_CRX_C_GTX_N8

PEG_CRX_C_GTX_P9
PEG_CRX_C_GTX_N9

PEG_CRX_C_GTX_P10
PEG_CRX_C_GTX_N10

PEG_CRX_C_GTX_P11
PEG_CRX_C_GTX_N11

PEG_CRX_C_GTX_P12
PEG_CRX_C_GTX_N12

PEG_CRX_C_GTX_P13
PEG_CRX_C_GTX_N13

PEG_CRX_C_GTX_P14
PEG_CRX_C_GTX_N14

PEG_CRX_C_GTX_P15
PEG_CRX_C_GTX_N15

CLK_PEG_P7<14>
CLK_PEG_N7<14>

N17P@

P

ALL_GPWRGD

4

O

G

10K_0402_5%

CLKREQ_PCIE#7 CLKREQ_PCIE#7_M

+1.8V_GFX_AON

RV56

N17P@

1 2
2

G

QV3

N17P@

1 3

D

S

BSS138W 1N SOT-323-3

RV57

N17P@

10K_0402_5%

1 2

PEG_CTX_C_GRX_P0
PEG_CTX_C_GRX_N0
PEG_CTX_C_GRX_P1
PEG_CTX_C_GRX_N1
PEG_CTX_C_GRX_P2
PEG_CTX_C_GRX_N2
PEG_CTX_C_GRX_P3
PEG_CTX_C_GRX_N3
PEG_CTX_C_GRX_P4
PEG_CTX_C_GRX_N4
PEG_CTX_C_GRX_P5
PEG_CTX_C_GRX_N5
PEG_CTX_C_GRX_P6
PEG_CTX_C_GRX_N6
PEG_CTX_C_GRX_P7
PEG_CTX_C_GRX_N7
PEG_CTX_C_GRX_P8
PEG_CTX_C_GRX_N8
PEG_CTX_C_GRX_P9
PEG_CTX_C_GRX_N9
PEG_CTX_C_GRX_P10
PEG_CTX_C_GRX_N10
PEG_CTX_C_GRX_P11
PEG_CTX_C_GRX_N11
PEG_CTX_C_GRX_P12
PEG_CTX_C_GRX_N12
PEG_CTX_C_GRX_P13
PEG_CTX_C_GRX_N13
PEG_CTX_C_GRX_P14
PEG_CTX_C_GRX_N14
PEG_CTX_C_GRX_P15
PEG_CTX_C_GRX_N15

PEG_CRX_C_GTX_P0
PEG_CRX_C_GTX_N0
PEG_CRX_C_GTX_P1
PEG_CRX_C_GTX_N1
PEG_CRX_C_GTX_P2
PEG_CRX_C_GTX_N2
PEG_CRX_C_GTX_P3
PEG_CRX_C_GTX_N3
PEG_CRX_C_GTX_P4
PEG_CRX_C_GTX_N4
PEG_CRX_C_GTX_P5
PEG_CRX_C_GTX_N5
PEG_CRX_C_GTX_P6
PEG_CRX_C_GTX_N6
PEG_CRX_C_GTX_P7
PEG_CRX_C_GTX_N7
PEG_CRX_C_GTX_P8
PEG_CRX_C_GTX_N8
PEG_CRX_C_GTX_P9
PEG_CRX_C_GTX_N9
PEG_CRX_C_GTX_P10
PEG_CRX_C_GTX_N10
PEG_CRX_C_GTX_P11
PEG_CRX_C_GTX_N11
PEG_CRX_C_GTX_P12
PEG_CRX_C_GTX_N12
PEG_CRX_C_GTX_P13
PEG_CRX_C_GTX_N13
PEG_CRX_C_GTX_P14
PEG_CRX_C_GTX_N14
PEG_CRX_C_GTX_P15
PEG_CRX_C_GTX_N15

CLK_PEG_P7
CLK_PEG_N7
CLKREQ_PCIE#7_M

DGPU_PEX_RST#_R
PEX_TERMP

RV50

N17P@

2.49K_0402_1%

1 2

XTAL_OUT

XTALIN

10P_0402_50V8J

4

CV70

N17P@

UV1A

AN12

PEX_RX0

AM12

PEX_RX0_N

AN14

PEX_RX1

AM14

PEX_RX1_N

AP14

PEX_RX2

AP15

PEX_RX2_N

AN15

PEX_RX3

AM15

PEX_RX3_N

AN17

PEX_RX4

AM17

PEX_RX4_N

AP17

PEX_RX5

AP18

PEX_RX5_N

AN18

PEX_RX6

AM18

PEX_RX6_N

AN20

PEX_RX7

AM20

PEX_RX7_N

AP20

PEX_RX8

AP21

PEX_RX8_N

AN21

PEX_RX9

AM21

PEX_RX9_N

AN23

PEX_RX10

AM23

PEX_RX10_N

AP23

PEX_RX11

AP24

PEX_RX11_N

AN24

PEX_RX12

AM24

PEX_RX12_N

AN26

PEX_RX13

AM26

PEX_RX13_N

AP26

PEX_RX14

AP27

PEX_RX14_N

AN27

PEX_RX15

AM27

PEX_RX15_N

AK14

PEX_TX0

AJ14

PEX_TX0_N

AH14

PEX_TX1

AG14

PEX_TX1_N

AK15

PEX_TX2

AJ15

PEX_TX2_N

AL16

PEX_TX3

AK16

PEX_TX3_N

AK17

PEX_TX4

AJ17

PEX_TX4_N

AH17

PEX_TX5

AG17

PEX_TX5_N

AK18

PEX_TX6

AJ18

PEX_TX6_N

AL19

PEX_TX7

AK19

PEX_TX7_N

AK20

PEX_TX8

AJ20

PEX_TX8_N

AH20

PEX_TX9

AG20

PEX_TX9_N

AK21

PEX_TX10

AJ21

PEX_TX10_N

AL22

PEX_TX11

AK22

PEX_TX11_N

AK23

PEX_TX12

AJ23

PEX_TX12_N

AH23

PEX_TX13

AG23

PEX_TX13_N

AK24

PEX_TX14

AJ24

PEX_TX14_N

AL25

PEX_TX15

AK25

PEX_TX15_N

AJ11

NC

AL13

PEX_REFCLK

AK13

PEX_REFCLK_N

AK12

PEX_CLKREQ_N

AJ26

NC

AK26

NC

AJ12

PEX_RST_N

AP29

PEX_TERMP

N17P-GT_BGA908

1 2

RV52

10M_0402_5%

YV1

1

1

GND

2

27MHZ_10PF_7V27000050

SJ100009700

3

NVVDD_PWM_VID
GPU_GC6_FB_EN
GC6_EVENT#_D
NVVDDS_PWM_VID
1V8_MAIN_EN
FRM_LCK
GPU_PSI

MEM_VDD_CTL
THERMAL_ALERT#
MEM_VREF

GPU_LEVEL

SYS_PEX_RST_MON#

GPU_PEX_RST_HOLD#

HPD_IFPC

I2CB_SCL
I2CB_SDA

VGA_EDID_CLK
VGA_EDID_DATA

VGA_SMB_CK2
VGA_SMB_DA2

+GPCPLL_AVDD

+XS_PLLVDD

+SP_PLLVDD

+VID_PLLVDD

XTALIN
XTAL_OUT

XTALOUT
XTALSSIN

12

13

D

2

G

S

100K_0402_5%

W=40mils
W=40mils
W=40mils
W=40mils

RV49

N17P@

10K_0402_5%

RV627

12

RV628

N17P@

NVVDD_PWM_VID <67>

NVVDDS_PWM_VID <68>
1V8_MAIN_EN <31>

GPU_PSI <67,68>

MEM_VDD_CTL <69>

MEM_VREF <28,29>

GPU_LEVEL <59>

1VS_GFX_PG<66>

12

RV51

N17P@

10K_0402_5%

1 2

@

0_0402_5%

+1.8V_GFX_AON

UV22

5

N17P@

1

P

B

4

O

2

A

G

TC7SZ08FU_SSOP5

3

P.P

1VS_GFX_PG

GPU_GC6_FB_EN

GPU_GC6_FB_EN GPU_GC6_FB_EN_H

GPU_THM_SMBCLK<15,44,45>

GPU_THM_SMBDAT<15,44,45>

GPU_HPD_RT

DGPU_PEX_RST#_R

GPU_HPD_RT <33>

RES

I2CB_SCL

I2CB_SDA

I2CC_SCL
I2CC_SDA

I2C

I2CS_SCL

I2CS_SDA

GPCPLL_AVDD

XS_PLLVDD

SP_PLLVDD

VID_PLLVDD

XTAL_OUT

CLK

XTAL_OUTBUFF

XTAL_SSIN

BSS138W 1N SOT-323-3

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27

RES
RES
RES

RES
RES

RES
RES
RES

XTAL_IN

@

P6
M3
L6
P5
P7
L7
M7
N8
L3
M2
L1
M5
N3
M4
N4
P2
R8
M6
R1
P3
P4
P1
P8
T8
L2
R4
R5
U3

AK9
AL10
AL9

AM9
AN9

AG10
AP9
AP8

R7
R6

R2
R3

T4
T3

H26

AD8

AE8

AD7

H3
H2

J4
H1

HPD_IFPC

QV94

N17P@

Part 1 of 7

GPIO

PCI EXPRESS

@

N17P@

3

3

GND

CV71

N17P@

4

10P_0402_50V8J

2

GC6_EVENT#_D
GPU_PSI
THERMAL_ALERT#
GPU_LEVEL
SYS_PEX_RST_MON#
1V8_MAIN_EN
GPU_PEX_RST_HOLD#
FRM_LCK

GPU_GC6_FB_EN
MEM_VREF

VGA_SMB_CK2
VGA_SMB_DA2

I2CB_SCL
I2CB_SDA

VGA_EDID_CLK
VGA_EDID_DATA
HPD_IFPC

DV13

N17P@

2

1

3

BAT54CW_SOT323-3

BAT54CW-7-F_SOT323-3

SCS00003800

+1.8V_GFX_AON

G

2

QV10

N17P@

13

D

S

BSS138W 1N SOT-323-3

DV9

N17P@

2 1

RB751S40_SOD523-2

AZ5125-01HPR7G_SOD523-2

DV11

N17P@

2 1

RB751S40_SOD523-2

AZ5125-01HPR7G_SOD523-2

GPU_PWR_LEVEL

Low
High

GPU_THM_SMBCLK

GPU_THM_SMBDAT

1 2

RV42 10K_0402_5%N17P@

1 2

RV574 10K_0402_5%@

1 2

RV526 10K_0402_5%N17P@

1 2

RV60 100K_0402_5%N17P@

1 2

RV532 10K_0402_5%N17P@

1 2

RV55 10K_0402_5%N17P@

1 2

RV41 10K_0402_5%N17P@

1 2

RV581 10K_0402_5%N17P@

1 2

RV37 10K_0402_5%N17P@

1 2

RV27 100K_0402_5%N17P@

1 2

RV191 1.8K_0402_5%N17P@

1 2

RV192 1.8K_0402_5%N17P@

1 2

RV512 1.8K_0402_5%N17P@

1 2

RV513 1.8K_0402_5%N17P@

1 2

RV514 1.8K_0402_5%N17P@

1 2

RV515 1.8K_0402_5%N17P@

1 2

RV626 10K_0402_5%N17P@

FBVDD_EN

12

RV209

N17P@

100K_0402_5%

GPU_EVENT#GC6_EVENT#_D

GPU_PWR_LEVELGPU_LEVEL

Low Performace
High Performace

QV1A

6 1

5

DMN63D8LDW-7 2N SOT363-6

QV1B

N17P@

3 4

DMN63D8LDW-7 2N SOT363-6

+1.8V_GFX_AON +1.8V_PLLVDD

+1.8V_GFX_AON

FBVDD_EN <31,69>

GPU_GC6_FB_EN_H <17>

GPU_EVENT# <17>

GPU_PWR_LEVEL <44>

RV572

0_0402_5%

RV571

0_0402_5%

2

N17P@

VGA_SMB_CK2

VGA_SMB_DA2

1

Under

RV583

@

0_0402_5%

12

CV833

1

N17P@

0.1U_0402_10V7K

2

CV939

@

0.1U_0402_10V7K

+GPCPLL_AVDD

1

2

12/21 follow NV spec.

+1.8V_PLLVDD

RV584

@

0_0402_5%

12

Under

CV72

N17P@

0.1U_0402_10V7K

+XS_PLLVDD

CV940

1

1

@

0.1U_0402_10V7K

2

2

12/21 follow NV spec.

+1.8V_PLLVDD

+1.8V_PLLVDD

ALL_GPWRGD

12

@

DGPU_PEX_RST#

12

@

RV585

@

0_0402_5%

RV586

@

0_0402_5%

+1.8V_PLLVDD

CV51

N17P@

Under

+SP_PLLVDD

12

CV52

1

N17P@

0.1U_0402_10V7K

2

Under

+VID_PLLVDD

12

CV53

1

N17P@

0.1U_0402_10V7K

2

LV7

N17P@

1 2

BLM15AX300SN1D

+1.8V_GFX_RUN

Near

CV50

1

1

N17P@

22U_0603_6.3V6M

4.7U_0603_6.3V6K

2

2

GC6 2.1 function

DGPU_HOLD_RST#

RV58

N17P@

10K_0402_5%

1 2

5

DGPU_HOLD_RST#

PCH_PLTRST#_EC

TC7SZ08FU_SSOP5

SA00001DG90

SYS_PEX_RST_MON#

GPU_PEX_RST_HOLD#

TC7SZ08FU_SSOP5

SA00001DG90

DGPU_HOLD_RST#<17>

A A

PCH_PLTRST#_EC<14,36,39,40,41,44,45>

1

2

+1.8V_GFX_AON

5

UV14

1

B

2

A

3

+1.8V_GFX_AON

5

UV18

1

B

2

A

3

CV212

@

0.1U_0402_10V7K

N17P@

P

4

O

G

@

P

4

O

G

RV587

1 2

0_0402_5%

12

RV208

@

0_0402_5%

@

SYS_PEX_RST_MON#

THERMATRIP_GPU#<24>

DGPU_PEX_RST# < 24>

4

THERMATRIP_GPU#

+1.8V_GFX_AON+1.8V_GFX_AON

RV619

N17P@

10K_0402_5%

1 2

QV88A

2

3

DGPU_PEX_RST#

12

RV620

@

0_0402_5%

QV88B

5

61

N17P@

DMN63D8LDW-7 2N SOT363-6

CMP_VOUT0

34

N17P@

DMN63D8LDW-7 2N SOT363-6

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

CMP_VOUT0 <44,61>

Compal Secret Data

Compal Secret Data

2017/01/06 2018/01/06

2017/01/06 2018/01/06

2017/01/06 2018/01/06

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

N17P_PCIE/DAC/GPIO

N17P_PCIE/DAC/GPIO

N17P_PCIE/DAC/GPIO

LA-E993P

LA-E993P

LA-E993P

1

23 78Tuesday, March 06, 2018

23 78Tuesday, March 06, 2018

23 78Tuesday, March 06, 2018

1.0(A00)

1.0(A00)

1.0(A00)

Vinafix.com

5

4

3

2

1

UV1D

AM6

IFPA_L3

AN6

IFPA_L3_N

AP3

IFPA_L2

D D

GPU_IFPC_P0<33>
GPU_IFPC_N0<33>
GPU_IFPC_P1<33>
GPU_IFPC_N1<33>
GPU_IFPC_P2<33>
GPU_IFPC_N2<33>
GPU_IFPC_P3<33>

12

RV630

@

0_0402_5%

2

QV93B

N17P@

3 4

@

@

GPU_IFPC_N3<33>

+1.8V_GFX_AON

12

5

12

0_0402_5%

12

0_0402_5%

12

12

RV621

N17P@

10K_0402_5%

C C

+1.8V_GFX_AON

1 2

DGPU_PEX_RST#<23>

B B

HDMI_CTRL_CLK<33,34>

HDMI_CTRL_DAT<33,34>

IFPC_I2C_8409_DAT<33>

IFPC_I2C_8409_CLK<33>

A A

RV629 0_0402_5%@

Vgs:0.5V~1V

QV93A

N17P@

6 1

DMN61D9UDW-7 2N SOT363-6

SB00001GW00

GPU_IFPC_CTRL_DATA_M

DMN61D9UDW-7 2N SOT363-6

SB00001GW00

HDMI_CTRL_CLK GPU_IFPC_CTRL_CLK_M

HDMI_CTRL_DAT

IFPC_I2C_8409_DAT

IFPC_I2C_8409_CLK

RV624

RV623

RP10

RP9

0_0402_5%

@PS8409@

0_0402_5%

@PS8409@

GPU_IFPC_P0
GPU_IFPC_N0
GPU_IFPC_P1
GPU_IFPC_N1
GPU_IFPC_P2
GPU_IFPC_N2
GPU_IFPC_P3
GPU_IFPC_N3

12

RV622

N17P@

10K_0402_5%

GPU_IFPC_CTRL_CLKGPU_IFPC_CTRL_CLK_M
GPU_IFPC_CTRL_DATA

GPU_IFPC_CTRL_DATA_M

AN3

IFPA_L2_N

AN5

IFPA_L1

AM5

IFPA_L1_N

AL6

IFPA_L0

AK6

IFPA_L0_N

AJ6

IFPA_AUX_SCL

AH6

IFPA_AUX_SDA_N

AJ9

IFPB_L3

AH9

IFPB_L3_N

AP6

IFPB_L2

AP5

IFPB_L2_N

AM7

IFPB_L1

AL7

IFPB_L1_N

AN8

IFPB_L0

AM8

IFPB_L0_N

AK8

IFPB_AUX_SCL

AL8

IFPB_AUX_SDA_N

AK1

IFPC_L0

AJ1

IFPC_L0_N

AJ3

IFPC_L1

AJ2

IFPC_L1_N

AH3

IFPC_L2

AH4

IFPC_L2_N

AG5

IFPC_L3

AG4

IFPC_L3_N

AM1

IFPD_L0

AM2

IFPD_L0_N

AM3

IFPD_L1

AM4

IFPD_L1_N

AL3

IFPD_L2

AL4

IFPD_L2_N

AK4

IFPD_L3

AK5

IFPD_L3_N

AD2

IFPE_L0

AD3

IFPE_L0_N

AD1

IFPE_L1

AC1

IFPE_L1_N

AC2

IFPE_L2

AC3

IFPE_L2_N

AC4

IFPE_L3

AC5

IFPE_L3_N

AE3

IFPF_L0

AE4

IFPF_L0_N

AF4

IFPF_L1

AF5

IFPF_L1_N

AD4

IFPF_L2

AD5

IFPF_L2_N

AG1

IFPF_L3

AF1

IFPF_L3_N

AG3

IFPC_AUX_SCL

AG2

IFPC_AUX_SDA_N

AK3

IFPD_AUX_SCL

AK2

IFPD_AUX_SDA_N

AB3

IFPE_AUX_SCL

AB4

IFPE_AUX_SDA_N

AF3

IFPF_AUX_SCL

AF2

IFPF_AUX_SDA_N

N17P-GT_BGA908

Part 4 of 7

TEST

TMDS

JTAG_TRST_N

SERIAL

GENERAL

NC

VDD_SENSE

GND_SENSE

NVJTAG_SEL

JTAG_TCK

JTAG_TDI
JTAG_TDO
JTAG_TMS

ROM_CS_N
ROM_SCLK

ROM_SI

ROM_SO

BUFRST_N

OVERT

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
STRAP5

THERMDP
THERMDN

@

AC6

NC

AJ28

NC

AJ4

NC

AJ5

NC

AL11

NC

C15

NC

D19

NC

D20

NC

D23

NC

D26

NC

V32

NC

trace width: 16mils
differential voltage sensing.
differential signal routing.

VCCSENSE_VGA

L4

VSSSENSE_VGA

L5

AK11

TESTMODE

GPU_JTAG_TCK

AM10

GPU_JTAG_TDI

AM11

GPU_JTAG_TDO

AP12

GPU_JTAG_TMS

AP11

GPU_JTAG_TRST#

AN11

ROM_CS

H6

ROM_SCLK

H4

ROM_SI

H5

ROM_SO

H7

E1

THERMATRIP_GPU#

M1

J2
J7
J6
J5
J3
J1

K3
K4

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
STRAP5

VCCSENSE_VGA <67>

VSSSENSE_VGA <67>

T98PAD @
T99PAD @
T100PAD @
T101PAD @

T97PAD @

ROM_SCLK <30>
ROM_SI <30 >
ROM_SO <30>

THERMATRIP_GPU# <23>

STRAP0 <30>
STRAP1 <30>
STRAP2 <30>
STRAP3 <30>
STRAP4 <30>
STRAP5 <30>

TESTMODE

10K_0402_5%

GPU_JTAG_TRST#

10K_0402_5%

+1.8V_GFX_AON

RV34

N17P@

10K_0402_5%

1 2

12

RV62

N17P@

12

RV63

N17P@

THERMATRIP_GPU#

Security Classification

Security Classification

Security Classification

2017/01/06 2018/01/06

2017/01/06 2018/01/06

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2017/01/06 2018/01/06

3

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

N17P_eDP/HDMI/mDP

N17P_eDP/HDMI/mDP

N17P_eDP/HDMI/mDP

LA-E993P

LA-E993P

LA-E993P

1

1.0(A00)

1.0(A00)

1.0(A00)

24 78Tuesday, March 06, 2018

24 78Tuesday, March 06, 2018

24 78Tuesday, March 06, 2018