Page 1
5
4
3
2
1
COMPAL CONFIDENTIAL
MODEL NAME :EDC41
D D
PCB NO :LA-G891P
14 WHL-U UMA(non TBT)
BOM P/N :XXXXX
Whiskey Lake U42
2019-02-12
REV : 1.0 (A00)
@ : Nopop Component
EMI@ : EMI Component
@EMI@ : EMI Nopop Component
C C
B B
ESD@ : ESDComponent
@ESD@ : ESD Nopop Component
RF@ : RF Component
@RF@ : RF Nopop Component
CONN@ : Connector Component
DS3@ : Deep sleep support
NDS3@ : non Deep sleep support
CXDP@ : XDP Component
RTD3@ : RTD Component
NRTD3@ : RTD Component
ST33@ : ST TPM Component
Par
t Number
Description
DA8001GT000
A A
COPYRIGHT 2017
ALL RIGHT RESERVED
REV:X00
PWB:
PCB 2FB LA-G891P REV0 MB UU NAR 1
Layout Dell logo
Power CKT :
5
GPIO map :
NORTHBAY 14UU_WHL_PWR_0128
X10
_CSLP GPIO map Rev1.3_20180529
4
750@ : NUVOTON TPM Component
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
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DEL
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Com
Com
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pal Electronics, Inc.
pal Electronics, Inc.
Tit
Tit
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le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronics, Inc.
Cov
Cov
Cov
er Sheet
er Sheet
er Sheet
LA-
LA-
LA-
G891P
G891P
G891P
1
1 10
1 10
1 10
0.3
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
2Monday, February 25, 2019
of
of
of
Page 2
5
www.schematic-x.blogspot.com
4
3
2
1
Northbay 15U UMA_NAR Block Diagram
Memory BUS (DDR4)
DDR4 2400MHz for WHL-U
Up to 2x16GB Modules
D D
TX/RX
Type C CONN.
CC
P45
Card reader
RTS5242
uSD4.0
PCIE[8]
P70
P70
C C
PCIE[9]
Intel Jacksonville
WGI219(LM/V)
Transformer
RJ45
P51
P51
P51
HDMI
CONN
DP SWITCH RETIMER
PS8802
PD Solution
TPS65982DD
P44
Micro SIM
P52
P40
P46
M.2,3042 Key B
WWAN/LTE/HCA
USB3.0 [5]
HDMI
SMBUS from EC
USB2.0[1]
SMBUS from EC
EDP CONN
PCIE[12]
P52
USB2.0[7]
P38
HDMI 1.4
Active LS
PS8407
2-Lane eDP1.3
PCIE[10]
M.2,2230 Key E
WLAN+BT/CNVi
P40
CNVi
P52
USB2.0[10]
DDI[1]
DDI[2]
INTEL
WHL-U 42
PAGE 6~19
USB
USB2.0[2]
SLGC55544CVTR
USB POWER SHARE
USB3.0[2] USB3.0[2]
DDR4-SO-DIMM X2
BANK 0, 1, 2, 3
P20~21
I2C[0]
USB2.0[6]
USB2.0[2]_PS
P71
USB2.0[3]
USB3.0[3]
USB2.0[4]
USB3.0[4]
LCD Touch
Camera
USB3.0 Conn
PS(Ext Port 1)
USB3.0 Conn
(Ext Port 2)
USB3.0 Conn
(Ext Port 3)
P38
P38
Through eDP Cable
P71
P72
P72
PCIE[13][14][15][16]
B B
Smart Card
USH
A A
5
TDA8034HN
RFID/NFC
Fingerprint
CONN
USH
BCM58202
USB/SPI FOR FIPS FPR
USB2[8]
SMSC KBC
MEC5106
4
SPI
SATA[0]
vPro
W25Q256JVEIQ
32MB 4K sector WSON8
ESPI
P58-59
Non-vPro
W25Q64JVZEIQ
8MB 4K sector WSON8 P8
Non-vPro
W25Q128JVSIQ
16MB 4K sector SOP8 P8
TPM2.0
ST33HTPH2E32AHC1
KB/TP CONN
FAN CONN
3
P66
SATA REPEATER
PI3EQX6741STZDEX
P65
SATA HDD
P77
Conn
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
P67
HD Audio I/F
P67
HDA Codec
ALC3204
M.2 2280 Key M
SSD Conn
2
P56
P68
INT.Speaker
Universal Jack
Dig. MIC
P56
P56
P38
Through eDP Cable
DELL
CONFIDENTIAL/PROPRIETARY
Titl
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Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
LID SWITCH for
Laptop mode
FP in PBTN CONN
CPU&PCH XDP Port
AUTOMATIC POWER
SWITCH(APS)
Free Fall sensor
DC/DC Interface
POWER ON/OFF
SW & LED
Comp
Comp
Bloc
Bloc
onday, February 25, 2019
onday, February 25, 2019
1
USH CONN
P14 & 79
al Electronics, Inc.
al Electronics, Inc.
k Diagram
k Diagram
LA-G8
LA-G8
91P
91P
2 102M
2 102M
P64
P66
P66
P11
P67
P78
P64
of
of
of
0.3
0.3
Page 3
5
POW
ER STATES
Signal
State
S0 (Full ON) / M0
D D
S0ix/Moff LOW HIGH HIGH ON ON ON OFF
S4 (Suspend to DISK) / M3 ON ON OFF
S5 (SOFT OFF) / M3 ON ON OFFLOW HIGHLOW
S0ix (Suspend to RAM) / M-OFF
S4 (Suspend to DISK) / M-OFF HIGH
S5 (SOFT OFF) / M-OFF
C C
SLP
S3#
HIGH
LOW HIGH HIGH
LOW HIGH HIGH LOW ON ONOFF OFF OFF
LOW LOW LOW ON OFF OFF OFF OFF
LOW LOW LOW LOW ON OFF OFF OFF OFF
SLP
SLP
S5#
S4#
HIGH HIGH
LOW
LOW
SLP
A#
HIGH
HIGH
ALWAYS
PLANE
ON
4
M
PLANE
ON
SUS
PLANE
RUN
PLANE
ON ON ON
OFF
OFF
CLOCKS
OFF
OFF
OFF
3
USB3.0
USB3.0-1
USB3.0-2
USB3.0-3
USB3.0-4
USB3.0-5
USB3.0-6
2
PCIEGbE
PCIE-1
PCIE-2
PCIE-3
PCIE-4
PCIE-5
PCIE-6
SATA
Type-C
JUSB1
JUSB2
JUSB3
M.2 3042(LTE)
NA
PCIE-7
PCIE-8
PCIE-9
PCIE-10 M.2 2230(BT)
PCIE-11
PCIE-12
SATA-0
SATA-1
Card Reader
LOM
M.2 2230(WLAN)
HDD
M.2 3042(LTE)
USB PORT#DESTINATION
1
2
3
4
5
6
7
8
9
10
1
DESTINATION
Type-C
JUSB1
JUSB2
JUSB3
NA
Camera
M2 3042(WWAN)
USH
FPR in PB
PCIE-13
PCIE-14
PCIE-15
PCIE-16
SATA-1*
SATA-2
M.2 2280 SSD
(PCIex4 or SATA)
PM TABLE
+5V_ALW
+3.3V_ALW
power
plane
B B
State
S0
S0ix
S5 S4/AC
S5 S4/AC doesn't exist
A A
5
+3.3V_ALW_DSW
+3.3V_ALW_PCH
+RTC_CELL
+1.8V_PRIM
+5V_ALW2
+3.3V_ALW2
+3.3V_RTC_LDO
+1V_PRIM
ON
ON
+3.3V_CV2
+1.2V_MEM
+2.5V_MEM
ON ON
ON
OFF
OFFOFF
+5V_RUN
+3.3V_RUN
+0.6V_DDR_VTT
+1.8V_RUN
+1.2V_RUN
OFFON
OFF
OFF
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
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Date: Sheet
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Port
Port
assignment
assignment
LA-
LA-
G891P
G891P
1
3 10
3 10
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
of
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Page 4
5
Barrel
ADAPTER
D D
CHARGER
ISL9538
(PU700)
Type-C
ADAPTER
+
PWR_SRC
BATTERY
C C
SY8210A
(PU200)
SYX198D
(PU301)
SY8288C
(PU102)
SY8288B
(PU100)
4
SIO_SLP_S4#
0.6V_DDR_VTT_ON
PCH_PRIM_EN
(SIO_SLP_SUS#)
ALWON
ALWON
+1.2V_MEM
+0.6V_DDR_VTT
+1.0V_PRIM
+5V_ALW
+5V_ALW2
+3.3V_RTC_LDO
+3.3V_ALW2
+3.3V_ALW
TPS22961
(UZ27)
3
SIO_SLP_S3#
SIO_SLP_S0#
VCCSTG_EN
+VCC_SFR_OC
SY8057B
(PU401)
SY8057C
(PU402)
EM5209
(UZ47)
SLGC55544C
(UI3)
SY6288
(UI1)
SY6288
(UI2)
RUN_ON
PCH_PRIM_EN
(SIO_SLP_SUS#)
RUN_ON
USB_POWERSHARE_VBUS_EN
USB_PWR_EN1#
USB_PWR_EN2#
+1.0VS_VCCIO
+1.0V_PRIM_CORE
+USB_EX2_PWR
+USB_EX3_PWR
TPS22961
(UZ19)
TPS22961
(UZ21)
+5V_RUN
+5V_USB_CHG_PWR
2
1
CPU PWR
PCH PWR
GT3 PWR
RUN_ON
SIO_SLP_S0#
RUN ON
LP2301
(QV8)
EM5209
(@UZ5)
+1.0V_VCCSTG
+1.0V_VCCST
3.3V_TS_EN
@PCH_3.3V_TS_EN
AUD_PWR_EN
Peripheral Device PWR
TYPE-C Power
GPU PWR
+5V_TSP
+5V_RUN_AUDIO
RUN_ON
RUN_ON
3.3V_CAM_EN#
AUD_PWR_EN
+1.8V_RUN
+1.2V_RUN
+3.3V_CAM
+3.3V_RUN_AUDIO
9
PCH_PRIM_EN
SIO_SLP_LAN#
PCH_PRIM_EN
RUN_ON
WLAN_PWR_EN
LCD_VCC_TEST_EN
ENVDD_PCH
3.3V_WWAN_EN
CV2_ON
SIO_SLP_S4#
+1.8V_PRIM
+3.3V_LAN
+3.3V_ALW_PCH
+3.3V_RUN
+3.3V_WLAN
+LCDVDD
+3.3V_WWAN
+3.3V_CV2
+2.5V_MEM
for DDR4
USH/B
RT8097A
FDMF3
035
ISL95857
(PU602)
VR_ON
B B
IMVP_
+VCC_SA
FDMF3035
(PU612)
IMVP_VR_ON
+VCC_GT
(PU610)
FDMF3035
(PU613)
U42@
IMVP_VR_ON
+VCC_CORE
AO6405
(QV1)
+BL_
NVPWR
EN_I
PWR_SRC
TYPE-C
+5V_ALW
+TBTA_VBUS(5V~20V)
A A
AP2204
(UT8)
+5V_ALW
+5V_TBT_VBUS
TPS65982D\
(UT5)
AP2112K
(UT7)
+20V_TBTA_VBUS_1(5V~20V)
+3.3V_VDD_PIC_R
(PU501)
EM5209
(UZ43)
EM5209
(UZ3)
EM520
(UZ47)
G524B1T11U
(UV24)
EM5209
(UZ43)
TPS22967
(UZ18)
AP7361C
(PU503)
AOZ1336
(UZ8)
AP7361
(PU502)
LP2301A
(QZ1)
EM5209
(@UZ5)
DELL CONFIDENTIAL/PROPRIETARY
Comp
Comp
al Electronics, Inc.
Titl
Titl
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PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
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NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
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2
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Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
Powe
Powe
r rails
r rails
LA-G
LA-G
891P
891P
1
0.3
4 102M
4 102M
0.3
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Page 5
5
Timing Diagram for S5 to S0 mode
D D
6
C C
B B
+3.3V_WLAN
11
A A
VCCST_PWRGD
12
H_CPUPWRGD
15
PCH_PLTRST#
17
0.6V_DDR_VTT_ON
12
+1.
0V_PRIM_CORE
+1.8V_PRIM
6
+1.0V_PRIM SY8286
+3.
3V_ALW
EM5
209VF
6
SLP
11
_WLAN#_GATE
OR
Gate
CPU
VCCST_PWRGD
PROCPWRGD
PLTRST#
DDR_VTT_CNTL
+PWR_SRC
TPS
62134
+3.3V_ALW
RT8097
+PWR_SRC
SIO
_SLP_WLAN#
SIO_SLP_WLAN#
NMO
AUX_EN_WOWL
VDDQ
VDDQC
VCCPLL_OC
S
4
+VCC_CORE
VCC
+1.0VS_VCCIO
VCCIO SYS_PWROK
+VCC_GT
VCCGT
+1.2V_MEM
VCCST
VCCSTG
VCCPLL
VCC
SA
+1.
0V_VCCST
+VCC_SA
11
+1.0V_PRIM
TPS22961
SIO
+LCDVDD
SIO
_SLP_SUS#
11
+5V_TSP
EC
5105
11
+5V
RUN_ON
11
3.3
V_WWAN_EN
_ALW
EM5
209VF
+3.
3V_ALW
EM5209VF
+1.
8V_PRIM
EM5
209VF +1.8V_RUN
+PWR_SRC
TLV
62130
+3.
3V_ALW
EM5209VF
+5V_RUN
+3.
+1.
+3.3V_WWAN
+3.3V_ALW
3
+3.3V_SPI
_SLP_S4#
3V_RUN
0VS_VCCIO
LP2
LP2301ALT1G+3.3V_CAM
13
3
+1.0V_MPHYGT
+3.3V_ALW_DSW
+3.3V_ALW_PCH
5
6
+1.0V_PRIM_CORE
6
17
4
+3.3V_ALW
G52
4B1T11
+3.3V_ALW
EM5209VF+3.3V_LAN
+5V
_RUN
301ALT1G
+3.
3V_RUN
+3.
3V_HDD_M2
+VCC_SA
+VCC_CORE
+VCC_GT
+1.0V_PRIM
+1.8V_PRIM
+RTC_CELL
PCH_PLTRST#
PCH_DPWROK
ENV
DD_PCH
SIO_SLP_LAN#
@PC
H_3.3V_TS_EN
3.3
V_TS_EN (EC)
3.3
V_CAM_EN#
10
+PW
ISL
PCH_PWROK
VCCPRIM_1P0
VCCPRIM_CORE
DCPDSW_1P0
VCCMPHYAON_1P0
VCCAPLL_1P0
VCCCLK1~6
VCCMPHYGT_1P0
VCCSRAM_1P0
VCCAMPHYPLL_1P0
VCCAPLLEBB
VCCDSW_3P3
VCCHDA
VCCSPI
VCCPRIM_3P3
VCCPGPPA~E
VCCRTCPRIM
VCCPGPPG
VCCATS
VCCRTC
VCC
PRIM_CORE
PLTRST#
DSW_PWROK
EDP
_VDDEN
SLP_LAN#
GPP_B21
GPD7
ADA
PTER
BATTERY
PCH
7
PCH_DPWROK
4
RES
16
SIO_SLP_SUS#
5
SIO_SLP_S4#
SIO_SLP_S5#
9
SIO
SIO_SLP_S3#
11
SIO_SLP_A#
R_SRC
95857
PCH
SLP_WLAN#/GPD9
VCCST_PWRGD
_RSMRST#
ET_OUT#
_SLP_LAN#
12
IMV
P_VR_ON
PWRBTN#
RSMRST#
SLP_SUS#
SLP_LAN#
PCH_PWROK
PROCPWRGD
14
SLP_S5#
SLP_S4#
SLP_S3#
SLP_A#
BAT
2
Pow
SIO_PWRBTN#
PCH_RSMRST#
SIO_SLP_SUS#
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_S3#
SIO_SLP_A#
SIO_SLP_LAN#
SIO_SLP_WLAN#
RESET_OUT#
PCH_PWROK
VCCST_PWRGD
H_CPUPWRGD
er Button
2AC1
ALW
ON
5
PCH_PRIM_EN
EN_INVPWR
10
SIO_SLP_S4#
0.6
V_DDR_VTT_ON
8
7
5
9
10
11
16
14
12
15
+PWR_SRC
SYV
828EC 5105
+PWR_SRC
SY8288
+3.
EM5209VF
+PWR_SRC
3V_ALW
AO6
405
+PWR_SRC
SY8
210
+5V_ALW2
+5V_ALW
+3.3V_RTC_LDO
+3.3V_ALW2
+3.3V_ALW
+3.3V_ALW_PCH
+BL_PWR_SRC
+1.
2V_MEM
+0.6V_DDR_VTT
12
1
1BAT
2AC
5
18
VDD
Q
DDR
VTT
DEL
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Com
Com
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Tit
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PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
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Size Document Numb er Rev
Size Document Numb er Rev
Size Document Numb er Rev
Date: Sheet
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Pow
Pow
er Sequence
er Sequence
LA-
LA-
G891P
G891P
1
5 10
5 10
of
of
of
0.3
0.3
2Monday, February 25 , 2019
2Monday, February 25 , 2019
Page 6
5
4
3
2
1
For 2LANE EDP
+3.3V_RUN
RC503 2.2K_0402_5%
RC178 2.2K_0402_5%
RC176 2.2K_0402_5%
D D
C C
B B
RC502 2.2K_0402_5%
RC438 2.2K_0402_5%@
RC437 2.2K_0402_5%@
Jony_01/16 : Refer RVP new adds
575962_WHL-U_DDR4_RVP_Sch_Rev0p5.pdf
All VREF traces should
have 10 mil trace width
TYPE
12
12
12
12
12
12
C_CON_SEL1
CPU_DP1_CTRL_CLK
CPU_DP1_CTRL_DATA
CPU_DP2_CTRL_CLK
CPU_DP2_CTRL_DATA
CPU_DDPD_CTRL_CLK
CPU_DDPD_CTRL_DATA
COMP
ENSATION PU FOR eDP
CAD Note:
Trace width=5 mils
Isolation Spacing=25mil,
Max length=100 mils.
+3.3
V_ALW_PCH
RC74
4
@
10K_0402_5%
1 2
TYPE
RC74
5
@
10K_0402_5%
C_CON_SEL2
12
+3.3
V_ALW_PCH
@
10K_0402_5%
1 2
12
@
1
RC74
3
RC63
0K_0402_5%
HDMI
TYPE-C
+1.0
VS_VCCIO
CPU_DP1_N0[40]
CPU_DP1_P0[40]
CPU_DP1_N1[40]
CPU_DP1_P1[40]
CPU_DP1_N2[40]
CPU_DP1_P2[40]
CPU_DP1_N3[40]
CPU_DP1_P3[40]
CPU_DP2_N0[46]
CPU_DP2_P0[46]
CPU_DP2_N1[46]
CPU_DP2_P1[46]
CPU_DP2_N2[46]
CPU_DP2_P2[46]
CPU_DP2_N3[46]
CPU_DP2_P3[46]
RC8 24
CPU_
DP1_CTRL_CLK[40]
CPU_
DP1_CTRL_DATA[40]
+3.3
V_ALW_PCH
1 2
@
1 2
RC10
1
GPP_
20K_0402_5%
CNV_
CNV_
CNV_
CNV_
CNV_
CNV_
CNV_
CNV_
CLK_
CNV_PRX_DTX_N[52]
CLK_
CNV_PRX_DTX_P[52]
CLK_
CNV_PTX_DRX_N[52]
CLK_
CNV_PTX_DRX_P[52]
.9_0402_1%
CPU_
CPU_
CPU_
CPU_
CPU_
CPU_
H17
PRX_DTX_N0[52]
PRX_DTX_P0[52]
PRX_DTX_N1[52]
PRX_DTX_P1[52]
PTX_DRX_N0[52]
PTX_DRX_P0[52]
PTX_DRX_N1[52]
PTX_DRX_P1[52]
150_0402_1%
EDP_
COMP
DP1_CTRL_CLK
DP1_CTRL_DATA
DP2_CTRL_CLK
DP2_CTRL_DATA
DDPD_CTRL_CLK
DDPD_CTRL_DATA
GPP_
H17
1 2
CNV_
T406
PAD~D@
T407
PAD~D@
SBIO
CNV_
CNV_
UC1A
AL5
DDI1_TXN_0
AL6
DDI1_TXP_0
AJ5
DDI1_TXN_1
AJ6
DDI1_TXP_1
AF6
DDI1_TXN_2
AF5
DDI1_TXP_2
AE5
DDI1_TXN_3
AE6
DDI1_TXP_3
AC4
DDI2_TXN_0
AC3
DDI2_TXP_0
AC1
DDI2_TXN_1
AC2
DDI2_TXP_1
AE4
DDI2_TXN_2
AE3
DDI2_TXP_2
AE1
DDI2_TXN_3
AE2
DDI2_TXP_3
AM6
DISP
_RCOMP
CC8
GPP_
E18/DPPB_CTRLCLK/CNV_BT_HOST_WAKE#
CC9
GPP_
E19/DPPB_CTRLDATA
CH4
GPP_
E20/DPPC_CTRLCLK
CH3
GPP_
E21/DPPC_CTRLDATA
CP4
GPP_
E22/DPPD_CTRLCLK
CN4
GPP_
E23/DPPD_CTRLDATA
CR26
GPP_
H16/DDPF_CTRLCLK
CP26
GPP_
H17/DDPF_CTRLDATA
WHL-U42_BGA1528
CNV_
PRX_DTX_N0
CNV_
PRX_DTX_P0
CNV_
PRX_DTX_N1
CNV_
PRX_DTX_P1
CNV_
PTX_DRX_N0
CNV_
PTX_DRX_P0
CNV_
PTX_DRX_N1
CNV_
PTX_DRX_P1
CLK_
CNV_PRX_DTX_N
CLK_
CNV_PRX_DTX_P
CLK_
CNV_PTX_DRX_N
CLK_
CNV_PTX_DRX_P
CNV_
WT_RCOMP
RC44
8
CNV_
COEX3[52]
COEX2[52]
COEX1[52]
COEX3
DDR_
CHA_EN
1
DDR_
CHB_EN
1
SBIO
S_TX
S_TX[79]
TYPE
C_CON_SEL1
TYPE
C_CON_SEL2
CNV_
COEX2
CNV_
COEX1
DDI
DISPLAY SIDEBANDS
UC1I
CR30
CNV_
CP30
CNV_
CM30
CNV_
CN30
CNV_
CN32
CNV_
CM32
CNV_
CP33
CNV_
CN33
CNV_
CN31
CNV_
CP31
CNV_
CP34
CNV_
CN34
CNV_
CP32
CNV_
CR32
CNV_
CP20
GPP_
CK19
GPP_
CG17
GPP_
CR14
GPP_
CP14
GPP_
CN14
GPP_
CM14
GPP_
CJ17
GPP_
CH17
GPP_
CF17
GPP_
W
HL-U42_BGA1528
C
NVio
WR_D0N
WR_D0P
WR_D1N
WR_D1P
WT_D0N
WT_D0P
WT_D1N
WT_D1P
WR_CLKN
WR_CLKP
WT_CLKN
WT_CLKP
WT_RCOMP_0
WT_RCOMP_1
F0/CNV_PA_BLANKING
F1
F2
C8/UART0_RXD
C9/UART0_TXD
C10/UART0_RTS#
C11/UART0_CTS#
F8/CNV_MFUART2_RXD
F9/CNV_MFUART2_TXD
F23/A4WP_PRESENT
1 of
20
GPP_
EMMC
9 of
20
EDP
GPP_
E13/DDPB_HPD0/DISP_MISC0
GPP_
E14/DDPC_HPD1/DISP_MISC1
GPP_
E15/DPPD_HPD2/DISP_MISC2
GPP_
E16/DPPE_HPD3/DISP_MISC3
GPP_
GPP_
H18/CPU_C10_GATE#
GPP_
H19/TIMESYNC_0
GPP_
H21/XTAL_FREQ_SELECT
D4/IMGCLKOUT0/BK4/SBK4
GPP_
H20/IMGCLKOUT_1
GPP_
F12/EMMC_DATA0
GPP_
F13/EMMC_DATA1
GPP_
F14/EMMC_DATA2
GPP_
F15/EMMC_DATA3
GPP_
F16/EMMC_DATA4
GPP_
F17/EMMC_DATA5
GPP_
F18/EMMC_DATA6
GPP_
F19/EMMC_DATA7
GPP_
F20/EMMC_RCLK
GPP_
F21/EMMC_CLK
GPP_
F11/EMMC_CMD
GPP_
F22/EMMC_RESET#
EMMC
E17/EDP_HPD/DISP_MISC4
GPP_
H22
GPP_
H23
GPP_
F10
GPD7
GPP_
F3
_RCOMP
AG4
EDP_TXN_0
AG3
EDP_TXP_0
AG2
EDP_TXN_1
AG1
EDP_TXP_1
AJ4
EDP_TXN_2
AJ3
EDP_TXP_2
AJ2
EDP_TXN_3
AJ1
EDP_TXP_3
AH4
EDP_AUX_N
AH3
EDP_AUX_P
AM7
DISP_UTILS
AC7
DDI1_AUX_N
AC6
DDI1_AUX_P
DDI2_AUX_N
DDI2_AUX_P
DDI3
DDI3
EDP_
EDP_
EDP_
BKLTCTL
CN27
CM27
CF25
CN26
CM26
CK17
B
V35
CN20
CG25
CH25
CR20
CM20
CN19
CM19
CN18
CR18
CP18
CM18
CM16
CP16
CR16
CN16
CK15
_AUX_N
_AUX_P
BKLTEN
VDDEN
CPU_
GPP_
GPP_
GPD7
CPU_DP2_AUXN
AD4
CPU_DP2_AUXP
AD3
CPU_DP3_AUXN
AG7
CPU_
AG6
CN6
CM6
CP7
CP6
CM7
CK11
CG11
CH11
This strap should sample HIGH.
There should NOT be any on-board device
driving it to opposite direction during strap sampling.
C10_GATE#
H21
H23
EMMC
DP3_AUXP
HDMI
_DP1_HPD
CPU_
DP2_HPD
FFS_
INT2
EDP_
HPD
CPU_
C10_GATE# [17,58,87]
Jony_01/16 : CK15 - Keep 200 ohm
575962_WHL-U_DDR4_RVP_Sch_Rev0p5.pdf
_RCOMP
1 2
RC10 2
00_0402_1%
EDP_TXN0 [38]
EDP_TXP0 [38]
EDP_TXN1 [38]
EDP_TXP1 [38]
EDP_AUXN [38]
EDP_AUXP [38]
CPU_DP2_AUXN [44,46]
CPU_DP2_AUXP [44,46]
1
@
PAD
~D
1
@
PAD
~D
HDMI
_DP1_HPD [40]
CPU_
DP2_HPD [44,46]
FFS_
INT2 [67]
EDP_
HPD [38]
PANE
L_BKLEN [38]
ENVD
D_PCH [38]
EDP_
BIA_PWM [38]
+3.3V_RUN
CPU_DP2_AUXN
FFS_INT2
CPU_DP2_AUXP
T1
T2
EDP_HPD
CPU_
DP2_HPD
GPD7
RC44
4.7K_0402_5%
RC44
@
20K_0402_5%
@
RC53
4.7K_0402_5%
RC44
@
20K_0402_5%
0K_0402_5%@
1
00K_0402_5%
20K_0402_5%
+3.3
V_ALW_PCH
3
4
+3.3
V_ALW_PCH
7
6
@
12
RC731100K_0402_5% @
12
RC72610K_0402_5%
12
RC732100K_0402_5% @
12
RC2100K_0402_5%
12
RC610
+3.3
V_ALW_PCH
RC95
1 2
RC45
4
1 2
1 2
GPP_
H21
LOW: 38.4/19.2MHZ (DEFAULT)
HIGH: 24MHZ
1 2
0 = Master Attached Flash Sharing
(MAFS) enabled. (Default)
1 = Slave Attached Flash Sharing
(SAFS) enabled.
1 2
GPP_
H23
1 2
A A
Vend
or TBDTBDFOXCONJAE
TYPEC_CON_SEL1 LOW
TYPEC_CON_SEL2
5
LOW
HIGH LOW
LOW
HIGHHIGH
HIGH
DELL
CONFIDENTIAL/PROPRIETARY
Comp
Comp
Comp
al Electronics, Inc.
al Electronics, Inc.
Titl
Titl
Title
e
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
4
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
e
P07-
P07-
P07-
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
MCP(1/14)DDI,EDP,CSI2,EMMC
MCP(1/14)DDI,EDP,CSI2,EMMC
MCP(1/14)DDI,EDP,CSI2,EMMC
LA-G
LA-G
LA-G
891P
891P
891P
6 102M
6 102M
6 102M
of
of
1
of
0.3
0.3
0.3
Page 7
5
DDR4, Ballout for side by side(Non-Interleave)
4
3
2
1
CPU Need update CIS
DDR_A_DQS#[0..7][23]
DDR_A_D[0..63][23]
DDR_A_DQS[0..7][23]
DDR_A_MA[0..16][23]
D D
UC1B
_A_D5
_A_D6
_A_D7
_A_D8
_A_D9
_A_D10
_A_D11
_A_D12
_A_D13
_A_D14
_A_D15
_A_D32
_A_D33
_A_D34
_A_D35
_A_D36
_A_D37
_A_D38
_A_D39
_A_D40
_A_D41
_A_D42
_A_D43
_A_D44
_A_D45
_A_D46
_A_D47
_B_D0
_B_D1
_B_D2
_B_D3
_B_D4
_B_D5
_B_D6
_B_D7
_B_D8
_B_D9
_B_D10
_B_D11
_B_D12
_B_D13
_B_D14
_B_D15
_B_D32
_B_D33
_B_D34
_B_D35
_B_D36
_B_D37
_B_D38
_B_D39
_B_D40
_B_D41
_B_D42
_B_D43
_B_D44
_B_D45
_B_D46
_B_D47
Interleave / Non-Interleaved
A26
DDR0_DQ_0/DDR0_DQ_0
D26
DDR0_DQ_1/DDR0_DQ_1
D28
DDR0_DQ_2/DDR0_DQ_2
C28
DDR0_DQ_3/DDR0_DQ_3
B26
DDR
C26
DDR
B28
DDR
A28
DDR
B30
DDR
D30
DDR
B33
DDR
D32
DDR
A30
DDR
C30
DDR
B32
DDR
C32
DDR
H37
DDR
H34
DDR
K34
DDR
K35
DDR
H36
DDR
H35
DDR
K36
DDR
K37
DDR
N36
DDR
N34
DDR
R37
DDR
R34
DDR
N37
DDR
N35
DDR
R36
DDR
R35
DDR
AN35
DDR
AN34
DDR
AR35
DDR
AR34
DDR
AN37
DDR
AN36
DDR
AR36
DDR
AR37
DDR
AU35
DDR
AU34
DDR
AW35
DDR
AW34
DDR
AU37
DDR
AU36
DDR
AW36
DDR
AW37
DDR
BA35
DDR
BA34
DDR
BC35
DDR
BC34
DDR
BA37
DDR
BA36
DDR
BC36
DDR
BC37
DDR
BE35
DDR
BE34
DDR
BG35
DDR
BG34
DDR
BE37
DDR
BE36
DDR
BG36
DDR
BG37
DDR
WHL-U42 _BGA1528
0_DQ_4/DDR0_DQ_4
0_DQ_5/DDR0_DQ_5
0_DQ_6/DDR0_DQ_6
0_DQ_7/DDR0_DQ_7
0_DQ_8/DDR0_DQ_8
0_DQ_9/DDR0_DQ_9
0_DQ_10/DDR0_DQ_10
0_DQ_11/DDR0_DQ_11
0_DQ_12/DDR0_DQ_12
0_DQ_13/DDR0_DQ_13
0_DQ_14/DDR0_DQ_14
0_DQ_15/DDR0_DQ_15
0_DQ_16/DDR0_DQ_32
0_DQ_17/DDR0_DQ_33
0_DQ_18/DDR0_DQ_34
0_DQ_19/DDR0_DQ_35
0_DQ_20/DDR0_DQ_36
0_DQ_21/DDR0_DQ_37
0_DQ_22/DDR0_DQ_38
0_DQ_23/DDR0_DQ_39
0_DQ_24/DDR0_DQ_40
0_DQ_25/DDR0_DQ_41
0_DQ_26/DDR0_DQ_42
0_DQ_27/DDR0_DQ_43
0_DQ_28/DDR0_DQ_44
0_DQ_29/DDR0_DQ_45
0_DQ_30/DDR0_DQ_46
0_DQ_31/DDR0_DQ_47
0_DQ_32/DDR1_DQ_0
0_DQ_33/DDR1_DQ_1
0_DQ_34/DDR1_DQ_2
0_DQ_35/DDR1_DQ_3
0_DQ_36/DDR1_DQ_4
0_DQ_37/DDR1_DQ_5
0_DQ_38/DDR1_DQ_6
0_DQ_39/DDR1_DQ_7
0_DQ_40/DDR1_DQ_8
0_DQ_41/DDR1_DQ_9
0_DQ_42/DDR1_DQ_10
0_DQ_43/DDR1_DQ_11
0_DQ_44/DDR1_DQ_12
0_DQ_45/DDR1_DQ_13
0_DQ_46/DDR1_DQ_14
0_DQ_47/DDR1_DQ_15
0_DQ_48/DDR1_DQ_32
0_DQ_49/DDR1_DQ_33
0_DQ_50/DDR1_DQ_34
0_DQ_51/DDR1_DQ_35
0_DQ_52/DDR1_DQ_36
0_DQ_53/DDR1_DQ_37
0_DQ_54/DDR1_DQ_38
0_DQ_55/DDR1_DQ_39
0_DQ_56/DDR1_DQ_40
0_DQ_57/DDR1_DQ_41
0_DQ_58/DDR1_DQ_42
0_DQ_59/DDR1_DQ_43
0_DQ_60/DDR1_DQ_44
0_DQ_61/DDR1_DQ_45
0_DQ_62/DDR1_DQ_46
0_DQ_63/DDR1_DQ_47
2 o
f 20
DDR0_CKN_0/DDR0_CKN_0
DDR0_CKP_0/DDR0_CKP_0
DDR0_CKN_1/DDR0_CKN_1
DDR
0_CKP_1/DDR0_CKP_1
DDR
0_CKE_0/DDR0_CKE_0
DDR
0_CKE_1/DDR0_CKE_1
DDR
0_CKE_2/NC
DDR
0_CKE_3/NC
DDR
0_CS#_0/DDR0_CS#_0
DDR
0_CS#_1/DDR0_CS#_1
DDR
0_ODT_0/DDR0_ODT_0
NC/
DDR0_ODT_1
DDR
0_CAB_9/DDR0_MA_0
DDR
0_CAB_8/DDR0_MA_1
DDR
0_CAB_5/DDR0_MA_2
NC/
DDR0_MA_3
NC/
DDR0_MA_4
DDR
0_CAA_0/DDR0_MA_5
DDR
0_CAA_2/DDR0_MA_6
DDR
0_CAA_4/DDR0_MA_7
DDR
0_CAA_3/DDR0_MA_8
DDR
0_CAA_1/DDR0_MA_9
DDR
0_CAB_7/DDR0_MA_10
DDR
0_CAA_7/DDR0_MA_11
DDR
0_CAA_6/DDR0_MA_12
DDR
0_CAB_0/DDR0_MA_13
DDR
0_CAB_2/DDR0_MA_14
DDR
0_CAB_1/DDR0_MA_15
DDR
0_CAB_3/DDR0_MA_16
DDR
0_CAB_4/DDR0_BA_0
DDR
0_CAB_6/DDR0_BA_1
DDR
0_CAA_5/DDR0_BG_0
DDR
0_CAA_8/DDR0_ACT#
DDR
0_CAA_9/DDR0_BG_1
Interleave / Non-Interleaved
DDR
0_DQSN_0/DDR0_DQSN_0
DDR
0_DQSP_0/DDR0_DQSP_0
DDR
0_DQSN_1/DDR0_DQSN_1
DDR
0_DQSP_1/DDR0_DQSP_1
DDR
0_DQSN_2/DDR0_DQSN_4
DDR
0_DQSP_2/DDR0_DQSP_4
DDR
0_DQSN_3/DDR0_DQSN_5
DDR
0_DQSP_3/DDR0_DQSP_5
DDR
0_DQSN_4/DDR1_DQSN_0
DDR
0_DQSP_4/DDR1_DQSP_0
DDR
0_DQSN_5/DDR1_DQSN_1
DDR
0_DQSP_5/DDR1_DQSP_1
DDR
0_DQSN_6/DDR1_DQSN_4
DDR
0_DQSP_6/DDR1_DQSP_4
DDR
0_DQSN_7/DDR1_DQSN_5
DDR
0_DQSP_7/DDR1_DQSP_5
NC/
DDR0_ALERT#
NC/
DDR
DDR
0_VREF_DQ_0
DDR
0_VREF_DQ_1
DDR
1_VREF_DQ
DDR
LPDDR3 / DDR4
LPDDR3 / DDR4
DDR0_PAR
_VREF_CA
_VTT_CTL
V32
V31
T32
T31
U36
U37
U34
U35
AE32
AF32
AE31
AF31
AC37
AC36
AC34
AC35
AA35
AB35
AA37
AA36
AB34
W36
Y31
W34
AA34
AC32
AC31
AB32
Y32
W32
AB31
V34
V35
W35
C27
D27
D31
C31
J35
J34
P34
P35
AP35
AP34
AV34
AV35
BB35
BB34
BF34
BF35
W37
W31
F36
D35
D37
E36
C35
DDR_A_CLK#0
DDR_A_CLK0
DDR_A_CLK#1
DDR_A_CLK1
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
_A_MA0
DDR
_A_MA1
DDR
_A_MA2
DDR
_A_MA3
DDR
_A_MA4
DDR
_A_MA5
DDR
_A_MA6
DDR
_A_MA7
DDR
_A_MA8
DDR
_A_MA9
DDR
_A_MA10
DDR
_A_MA11
DDR
_A_MA12
DDR
_A_MA13
DDR
_A_MA14
DDR
_A_MA15
DDR
_A_MA16
DDR
_A_DQS#0
DDR
_A_DQS0
DDR
_A_DQS#1
DDR
_A_DQS1
DDR
_A_DQS#4
DDR
_A_DQS4
DDR
_A_DQS#5
DDR
_A_DQS5
DDR
_B_DQS#0
DDR
_B_DQS0
DDR
_B_DQS#1
DDR
_B_DQS1
DDR
_B_DQS#4
DDR
_B_DQS4
DDR
_B_DQS#5
DDR
_B_DQS5
_A_CKE0
_A_CKE1
_A_CKE2
_A_CKE3
_A_CS#0
_A_CS#1
_A_ODT0
_A_ODT1
DDR_A_CLK#0 [23]
DDR_A_CLK0 [23]
DDR_A_CLK#1 [23]
DDR
_A_CLK1 [23]
DDR
_A_CKE0 [23]
DDR
_A_CKE1 [23]
1
PAD~D
1
PAD~D
DDR
_A_CS#0 [23]
DDR
_A_CS#1 [23]
DDR
_A_ODT0 [23]
DDR
_A_ODT1 [23]
DDR
_A_BA0 [23]
DDR
_A_BA1 [23]
DDR
_A_BG0 [23]
DDR
_A_ACT# [23]
DDR
_A_BG1 [23]
DDR
_A_ALERT# [23]
DDR
_A_PARITY [23]
DDR
_VTT_CTRL [23]
@
T35
1
@
T35
0
+DD
+DD
DDR0_PAR,DDR0_ALERT#
for DDR4
R_VREF_CA
R_VREF_B_DQ
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
C C
B B
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
_A_D20
_A_D21
_A_D22
_A_D23
_A_D24
_A_D25
_A_D26
_A_D27
_A_D28
_A_D29
_A_D30
_A_D31
_A_D48
_A_D49
_A_D50
_A_D51
_A_D52
_A_D53
_A_D54
_A_D55
_A_D56
_A_D57
_A_D58
_A_D59
_A_D60
_A_D61
_A_D62
_A_D63
_B_D16
_B_D17
_B_D18
_B_D19
_B_D20
_B_D21
_B_D22
_B_D23
_B_D24
_B_D25
_B_D26
_B_D27
_B_D28
_B_D29
_B_D30
_B_D31
_B_D48
_B_D49
_B_D50
_B_D51
_B_D52
_B_D53
_B_D54
_B_D55
_B_D56
_B_D57
_B_D58
_B_D59
_B_D60
_B_D61
_B_D62
_B_D63
UC1C
lnterleave /
Non-lnterleaved
J22
DDR1_DQ_0/DDR0_DQ_16
H25
DDR1_DQ_1/DDR0_DQ_17
G22
DDR1_DQ_2/DDR0_DQ_18
H22
DDR
1_DQ_3/DDR0_DQ_19
F25
DDR
1_DQ_4/DDR0_DQ_20
J25
DDR
1_DQ_5/DDR0_DQ_21
G25
DDR
1_DQ_6/DDR0_DQ_22
F22
DDR
1_DQ_7/DDR0_DQ_23
D22
DDR
1_DQ_8/DDR0_DQ_24
C22
DDR
1_DQ_9/DDR0_DQ_25
C24
DDR
1_DQ_10/DDR0_DQ_26
D24
DDR
1_DQ_11/DDR0_DQ_27
A22
DDR
1_DQ_12/DDR0_DQ_28
B22
DDR
1_DQ_13/DDR0_DQ_29
A24
DDR
1_DQ_14/DDR0_DQ_30
B24
DDR
1_DQ_15/DDR0_DQ_31
G31
DDR
1_DQ_16/DDR0_DQ_48
G32
DDR
1_DQ_17/DDR0_DQ_49
H29
DDR
1_DQ_18/DDR0_DQ_50
H28
DDR
1_DQ_19/DDR0_DQ_51
G28
DDR
1_DQ_20/DDR0_DQ_52
G29
DDR
1_DQ_21/DDR0_DQ_53
H31
DDR
1_DQ_22/DDR0_DQ_54
H32
DDR
1_DQ_23/DDR0_DQ_55
L31
DDR
1_DQ_24/DDR0_DQ_56
L32
DDR
1_DQ_25/DDR0_DQ_57
N29
DDR
1_DQ_26/DDR0_DQ_58
N28
DDR
1_DQ_27/DDR0_DQ_59
L28
DDR
1_DQ_28/DDR0_DQ_60
L29
DDR
1_DQ_29/DDR0_DQ_61
N31
DDR
1_DQ_30/DDR0_DQ_62
N32
DDR
1_DQ_31/DDR0_DQ_63
AJ29
DDR
1_DQ_32/DDR1_DQ_16
AJ30
DDR
1_DQ_33/DDR1_DQ_17
AM32
DDR
1_DQ_34/DDR1_DQ_18
AM31
DDR
1_DQ_35/DDR1_DQ_19
AM30
DDR
1_DQ_36/DDR1_DQ_20
AM29
DDR
1_DQ_37/DDR1_DQ_21
AJ31
DDR
1_DQ_38/DDR1_DQ_22
AJ32
DDR
1_DQ_39/DDR1_DQ_23
AR31
DDR
1_DQ_40/DDR1_DQ_24
AR32
DDR
1_DQ_41/DDR1_DQ_25
AV30
DDR
1_DQ_42/DDR1_DQ_26
AV29
DDR
1_DQ_43/DDR1_DQ_27
AR30
DDR
1_DQ_44/DDR1_DQ_28
AR29
DDR
1_DQ_45/DDR1_DQ_29
AV32
DDR
1_DQ_46/DDR1_DQ_30
AV31
DDR
1_DQ_47/DDR1_DQ_31
BA32
DDR
1_DQ_48/DDR1_DQ_48
BA31
DDR
1_DQ_49/DDR1_DQ_49
BD31
DDR
1_DQ_50/DDR1_DQ_50
BD32
DDR
1_DQ_51/DDR1_DQ_51
BA30
DDR
1_DQ_52/DDR1_DQ_52
BA29
DDR
1_DQ_53/DDR1_DQ_53
BD29
DDR
1_DQ_54/DDR1_DQ_54
BD30
DDR
1_DQ_55/DDR1_DQ_55
BG31
DDR
1_DQ_56/DDR1_DQ_56
BG32
DDR
1_DQ_57/DDR1_DQ_57
BK32
DDR
1_DQ_58/DDR1_DQ_58
BK31
DDR
1_DQ_59/DDR1_DQ_59
BG29
DDR
1_DQ_60/DDR1_DQ_60
BG30
DDR
1_DQ_61/DDR1_DQ_61
BK30
DDR
1_DQ_62/DDR1_DQ_62
BK29
DDR
1_DQ_63/DDR1_DQ_63
WHL-U42 _BGA1528
3 o
f 20
DDR1_CKN_0/DDR1_CKN_0
DDR1_CKP_0/DDR1_CKP_0
DDR1_CKN_1/DDR1_CKN_1
DDR
1_CKP_1/DDR1_CKP_1
DDR
1_CKE_0/DDR1_CKE_0
DDR
1_CKE_1/DDR1_CKE_1
DDR
1_CKE_2/NC
DDR
1_CKE_3/NC
DDR
1_CS#_0/DDR1_CS#_0
DDR
1_CS#_1/DDR1_CS#_1
DDR
1_ODT_0/DDR1_ODT_0
NC/
DDR1_ODT_1
DDR
1_CAB_9/DDR1_MA_0
DDR
1_CAB_8/DDR1_MA_1
DDR
1_CAB_5/DDR1_MA_2
NC/
DDR1_MA_3
NC/
DDR1_MA_4
DDR
1_CAA_0/DDR1_MA_5
DDR
1_CAA_2/DDR1_MA_6
DDR
1_CAA_4/DDR1_MA_7
DDR
1_CAA_3/DDR1_MA_8
DDR
1_CAA_1/DDR1_MA_9
DDR
1_CAB_7/DDR1_MA_10
DDR
1_CAA_7/DDR1_MA_11
DDR
1_CAA_6/DDR1_MA_12
DDR
1_CAB_0/DDR1_MA_13
DDR
1_CAB_2/DDR1_MA_14
DDR
1_CAB_1/DDR1_MA_15
DDR
1_CAB_3/DDR1_MA_16
DDR
1_CAB_4/DDR1_BA_0
DDR
1_CAB_6/DDR1_BA_1
DDR
1_CAA_5/DDR1_BG_0
DDR
1_CAA_9/DDR1_BG_1
DDR
1_CAA_8/DDR1_ACT#
lnt
erleave / Non-lnterleaved
DDR
1_DQSN_0/DDR0_DQSN_2
DDR
1_DQSP_0/DDR0_DQSP_2
DDR
1_DQSN_1/DDR0_DQSN_3
DDR
1_DQSP_1/DDR0_DQSP_3
DDR
1_DQSN_2/DDR0_DQSN_6
DDR
1_DQSP_2/DDR0_DQSP_6
DDR
1_DQSN_3/DDR0_DQSN_7
DDR
1_DQSP_3/DDR0_DQSP_7
DDR
1_DQSN_4/DDR1_DQSN_2
DDR
1_DQSP_4/DDR1_DQSP_2
DDR
1_DQSN_5/DDR1_DQSN_3
DDR
1_DQSP_5/DDR1_DQSP_3
DDR
1_DQSN_6/DDR1_DQSN_6
DDR
1_DQSP_6/DDR1_DQSP_6
DDR
1_DQSN_7/DDR1_DQSN_7
DDR
1_DQSP_7/DDR1_DQSP_7
NC/
DDR1_ALERT#
NC/
DRA
DDR
DDR
DDR
LPDDR3 / DDR4
DDR1_PAR
M_RESET#
_RCOMP_0
_RCOMP_1
_RCOMP_2
AF28
AF29
AE28
AE29
T28
T29
V28
V29
AL37
AL35
AL36
AL34
AG36
AG35
AF34
AG37
AE35
AF35
AE37
AC29
AE36
AB29
AG34
AC28
AB28
AK35
AJ35
AK34
AJ34
AJ37
AJ36
W29
Y28
W28
H24
G24
C23
D23
G30
H30
L30
N30
AL31
AL30
AU31
AU30
BC31
BC30
BH31
BH30
Y29
AE34
BU31
BN28
BN27
BN29
DDR_B_CLK#0
DDR_B_CLK0
DDR_B_CLK#1
DDR_B_CLK1
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
_A_DQS#2
DDR
_A_DQS2
DDR
_A_DQS#3
DDR
_A_DQS3
DDR
_A_DQS#6
DDR
_A_DQS6
DDR
_A_DQS#7
DDR
_A_DQS7
DDR
_B_DQS#2
DDR
_B_DQS2
DDR
_B_DQS#3
DDR
_B_DQS3
DDR
_B_DQS#6
DDR
_B_DQS6
DDR
_B_DQS#7
DDR
_B_DQS7
DDR
_B_ALERT#
DDR
_B_PARITY
DDR
_DRAMRST#
SM_
SM_
SM_
_B_CKE0
_B_CKE1
_B_CS#0
_B_CS#1
_B_ODT0
_B_ODT1
_B_MA0
_B_MA1
_B_MA2
_B_MA3
_B_MA4
_B_MA5
_B_MA6
_B_MA7
_B_MA8
_B_MA9
_B_MA10
_B_MA11
_B_MA12
_B_MA13
_B_MA14
_B_MA15
_B_MA16
RCOMP0
RCOMP1
RCOMP2
DDR_B_DQS#[0..7][24]
DDR_B_D[0..63][24]
DDR_B_DQS[0..7][24]
DDR_B_MA[0..16][24]
DDR_B_CLK#0 [24]
DDR_B_CLK0 [24]
DDR_B_CLK#1 [24]
DDR
_B_CLK1 [24]
DDR
_B_CKE0 [24]
DDR
_B_CKE1 [24]
1
PAD~D
1
PAD~D
DDR
_B_CS#0 [24]
DDR
_B_CS#1 [24]
DDR
_B_ODT0 [24]
DDR
_B_ODT1 [24]
DDR
_B_BA0 [24]
DDR
_B_BA1 [24]
DDR
_B_BG0 [24]
DDR
_B_BG1 [24]
DDR
_B_ACT# [24]
DDR
_B_ALERT# [24]
DDR
_B_PARITY [24]
DDR
_DRAMRST# [23]
@
T35
3
@
T35
4
DDR1_PAR,DDR1_ALERT#
for DDR4
Hank3/5:575962_WHL_DDR4_RVP_RN_TDK_Rev0p7.pdf page12,keep setting
DDR4 COMPENSATION SIGNALS
SM_
RCOMP0
1 2
RC5 1
SM_
RCOMP1
RC5
SM_
RCOMP2
RC7 1
CAD Note:
Trace width=12~15 mil, Spacing=20 mils
Max trace length= 500 mil
A A
21_0402_1%
1 2
04 80.6_0402_1 %
1 2
00_0402_1%
DELL CONFIDENTIAL/PROPRIETARY
Com
Com
Com
pal Electronics, Inc.
pal Electronics, Inc.
Tit
Tit
Tit
le
le
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
le
Size Docum ent Numbe r Rev
Size Docum ent Numbe r Rev
Size Docum ent Numbe r Rev
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronics, Inc.
P08
P08
P08
-MCP(2/14)DDR4
-MCP(2/14)DDR4
-MCP(2/14)DDR4
LA-G
LA-G
LA-G
891P
891P
891P
1
7 10
7 10
7 10
of
of
of
0.3
0.3
0.3
2Mond ay, February 25, 2 019
2Mond ay, February 25, 2 019
2Mond ay, February 25, 2 019
Page 8
5
SPI_MOSI= SPI_IO0
SPI_MISO= SPI_IO1
PCH EDS R0.7 p.235~236
PCH_SPI_CLK
PCH_SPI_D1
PCH_CL_CLK1[52]
PCH_CL_DATA1[52]
PCH_CL_RST1#[52]
ESPI
WWAN_B B_RST#
WWAN_GPIO_PERST#
_ALERT#[58]
PCH_SPI_D0
PCH_SPI_D2
PCH_SPI_D3
PCH_SPI_CS#0
PCH_SPI_CS#1
PCH_SPI_CS#2
ESPI_ALERT#
1 2
0K_0402_1%
12
12
WWAN_
12
RC7561
@
00K_0402_5%@
0K_0402_5%
RC505 1K_0402_1%CXDP@
RC11 1K_0402_1%CXDP@
ESPI
_ALERT#
GPIO_PERST#
ESPI
PCH_SP
1 2
WWAN_GPIO_PERST#[52]
_RESET#
I_CLK
PCH_SPI_CS#2[66]
RTC_DET#[83]
WWAN_BB _RST#[52]
MEDIACARD_IRQ#[70]
PCH_SPI_DO_XDP[79]
PCH_SPI_DO2_XDP[79]
D D
+1.8
V_PRIM
1 2
RC244 1
0K_0402_5%
C C
RC833 1
RC96 10
For
signal deglitch, refer to 575412_WHL_U_PDG rev0p8
Strap pin
Strap pin
Strap pin
1.8V
1.8V
CH37
CF37
CF36
CF34
CG34
CG36
CG35
CH34
CF20
CG22
CF22
CG23
CH23
CG20
BV29
BV28
CH7
CH8
CH9
UC1E
SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0#
SPI0_CS1#
SPI0_CS2#
GPP_D1/SPI1_CLK/BK1/SBK1
GPP_D2/SPI1_MISO_IO1/BK2/SBK2
GPP_D3/SPI1_MOSI_IO0/BK3/SBK3
GPP_D21/SPI1_IO2
GPP_D22/SPI1_IO3
GPP_D0/SPI1_CS0#/BK0/SBK0
CL_CLK
CL_DATA
CL_RST#
GPP_A0/RCIN#/TIME_SYNC1
GPP_
A6/SERIRQ
WHL-U42_BGA1528
SPI - FLASH
4
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C5/SML0ALERT#
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_B23/SML1ALERT#/PCHHOT#
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME#/ESPI_CS#
GPP_A14/SUS_STAT#/ESPI_RESET#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_A10/CLKOUT_LPC1
GPP_A8/CLKRUN#
+3.3
V_ALW_PCH
12
RC94
10
0K_0402_5%
PCH_SP
I_D0
12
RC518
@
4
.7K_0402_5%
Disabled
Enabled
V_ALW_PCH
12
RC62
10
0K_0402_5%
PCH_SP
I_D3
12
RC515
@
4
.7K_0402_5%
PLACE RC62 AND RC515 CLOS
TO THE SPI SIGNAL TO AVOID STUB
Disabled
Enabled
SPI - TOUCH
C LINK
SMBUS , SMLINK
LPC , ESPI
5 of
20
WEAK INTERNAL PU WEAK INTERNAL PU
BOOT HALT
HIGH
LOW
+3.3
WEAK INTERNAL PU
A0 PERSONALITY STRAP
HIGH
LOW
3
MEM_SMBCLK
CK14
MEM_SMBDATA
CH15
PCH_SMB_ALERT#
CJ15
Strap pin
SML0_SMBCLK
CH14
SML0_SMBDATA
CF15
GPP_C5
Strap pin
CG15
SML1_SMBCLK
CN15
SML1_SMBDATA
CM15
GPP_B23
CC34
ESPI_IO0_R
1.8V
CA29
ESPI_IO1_R
1.8V
BY29
ESPI_IO2_R
1.8V
BY27
ESPI_IO3_R
1.8V
BV27
CA28
1.8V
1.8V
CA27
ESPI_CLK
BV32
BV30
GPP_A8
BY30
566439_CNL_PCH_UY_EDS_Vol_1_Rev_1.1.pdf
External pull-up is required. Recommend 100K if pulled
up to 3.3V or 75K if pulled up to 1.8V. This strap should sample HIGH.
There should NOT be any on-board device driving it to opposite direction
during strap sampling.
SML0_SMBCLK [51]
SML0_SMBDATA [51]
SML1_SMBCLK [58]
SML1_SMBDATA [58]
1 2
RC366 15_0402_5%
1 2
RC367 15_0402_5%
1 2
RC368 15_0402_5%
1 2
RC369 15_0402_5%
ESPI_CS# [58,79]
ESPI_RESET# [58,79]
1 2
RC19 33_0402_5% EMI@
+3.3
V_ALW_PCH
12
RC61
10
0K_0402_5%
PCH_SP
12
RC519
@
4
.7K_0402_5%
PLACE RC61 AND RC519 CLOS
CONSENT STRAP
HIGH
LOW
TO THE SPI SIGNAL TO AVOID STUB
Disabled
Enabled
I_D2
ESPI_IO0 [58,79]
ESPI_IO1 [58,79]
ESPI_IO2 [58,79]
ESPI_IO3 [58,79]
RVP 15 ohm
575962_WHL-U_DDR4_RVP_Sch_Rev0p5.pdf
ESPI_CLK_5105 [58,79]
ESPI
_CLK_5105
SML0
_SMBCLK
SML1
_SMBCLK
MEM_
2
RF Request
1 2
CC316@
RF@ 33P_0402_50V8J
1 2
CC318@
RF@ 33P_0402_50V8J
1 2
CC319@
RF@ 33P_0402_50V8J
SMBCLK
1 2
CC320@
RF@ 33P_0402_50V8J
MEM_SMBCLK
MEM_SMBDATA
Place close CPU side
+3.3V_RUN
6
5
L2N7002DW1T1G_SC88-6
3 4
QC2B
L2N7002DW1T1G_SC88-6
2
1
DDR_XDP_WAN_SMBCLK [23,24,67,79]
QC2A
DDR_XDP_WAN_SMBDAT [23,24,67,79]
DDR_
XDP_WAN_SMBDAT
DDR_
XDP_WAN_SMBCLK
GPP_
MEM_
SMBCLK
MEM_
SMBDATA
SML1
_SMBCLK
SML1
_SMBDATA
SML0
_SMBCLK
SML0
_SMBDATA
RTC_DE
T#
SML0
_SMBCLK
SML0
_SMBDATA
RC318 2
RC319 2
A8
1
1 2
1 2
1 2
RC849
1 2
RC12 1K
1 2
RC14 1K
1 2
RC15 1K
1 2
RC507
1 2
RC347
1 2
RC348
1 2
RC866
1 2
RC506
1 2
RC20 49
+3.3
.2K_0402_5%
.2K_0402_5%
8.2K_0402_5%@
+3.3
_0402_5%
_0402_5%
_0402_5%
1K_0402_5%
499_0402_1%
499_0402_1%
1
0K_0402_5%
+3.3
499_0402_1%@
9_0402_1%@
V_RUN
V_ALW_PCH
V_LAN
+3.3
V_ALW_PCH
PCH_SM
B_ALERT#
1 2
RC266 4
.7K_0402_5%
B B
PCH_SP
I_D1_R1[66]
PCH_SP
I_D0_R1[66]
PCH_SP
I_CLK_R1[66]
PCH_
SPI_CLK_1_R
33_0402_5%
@
12
EMI@
RC289
A A
33P_0402_50V8J
12
CC145
2
5
PCH_
SPI_CLK_0_R
33_0402_5%
@
12
EMI@
RC299
@EMI@
33P_0402_50V8J
@EMI@
12
CC145
3
PCH_
PCH_
PCH_
PCH_
SPI_CS#0_R1
SPI_D2_R1
SPI_CS#1_R1
SPI_D2_R1
4
RC32 0_
@
1 2
1 2
RC33 49
VPRO@
NVPRO@
1 2
RC302 0
1 2
RC35 33
NVPRO@
0201_5%
.9_0201_1%
_0201_5%
_0201_1%
PCH_
PCH_
PCH_
PCH_
PCH_
PCH_
SPI_CS#0_R2
SPI_D1_0_R
SPI_D2_0_R
SPI_CS#1_R2
SPI_D1_1_R
SPI_D2_1_R
SOFTWARE TAA
VPRO PDG P.296 R1 50 ohm
PCH_
SPI_D1_R1
RC734 4
PCH_
SPI_D0_R1
RC570 4
PCH_
SPI_CLK_R1
RC571 4
PCH_
SPI_D3_R1
RC572 4
NVPRO follow PDG P.298 R1 33 oh m
PCH_
SPI_D1_R1
RC573 3
PCH_
SPI_D0_R1
RC574 3
PCH_
SPI_CLK_R1
RC575 3
PCH_
SPI_D3_R1
RC576 3
PDG SPI0 2 resistor 50ohm, SPI0 3 resistor 33ohm
CLOSEED TO ROM
Please place close for future replace to RP
For vPro
32MB WSON8 Flash ROM
For Non-vPro
8MB WSON8 Flash ROM
UC5VPRO@
1
CS#
2
DO
3
IO2
4
GND
W25Q
256JVEIQ_WSON8_8X6
For Non-vPro
16MB SOP8 Flash ROM
UC6NVPRO@
1
CS#
2
DO(I
3
IO2
4
GND
W25Q
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
Them
VCC
O1)
CLK
DI(I
O0)
128JVSIQ_SO8
PCH_
SPI_D1_0_R
9.9_0201_1%VPRO@
PCH_
SPI_D0_0_R
9.9_0201_1%VPRO@
PCH_
SPI_CLK_0_R
9.9_0201_1%VPRO@
PCH_
SPI_D3_0_R
9.9_0201_1%VPRO@
PCH_
SPI_D1_1_R
3_0201_1%NVPRO@
PCH_
SPI_D0_1_R
3_0201_1%NVPRO@
PCH_
SPI_CLK_1_R
3_0201_1%NVPRO@
PCH_
SPI_D3_1_R
3_0201_1%NVPRO@
+3.3
V_SPI
0.1
U_0201_10V6K
8
VCC
PCH_
SPI_D3_0_R
7
IO3
PCH_
SPI_CLK_0_R
6
CLK
PCH_
SPI_D0_0_R
5
DI
9
alPad
+3.3
V_SPI
0.
8
7
IO
6
5
1U_0201_10V6K
PCH_
SPI_D3_1_R
PCH_
SPI_CLK_1_R
PCH_
SPI_D0_1_R
3
CC9
1 2
NVPRO@
CC10
1 2
VPRO
PDG P.296 R2 5 ohm
NVPRO PDG P.298 R2 10 ohm
1 2
NVPRO@
RC24 0_
1 2
RC25 4.
VPRO@
1 2
RC26 4.
VPRO@
1 2
RC27 4.
VPRO@
1 2
RC28
@
1 2
RC29 4.
VPRO@
1 2
RC30 4.
VPRO@
+3.3
V_SPI
+3.3
V_ALW_PCH
@
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
RC31
DC4
PROM_
1 2
RB52
PCH_SP
PCH_SP
0201_5%
PCH_SP
99_0201_1%
PCH_SP
PCH_SP
PCH_SP
99_0201_1%
PCH_SP
99_0201_1%
PCH_SP
PCH_SP
PCH_SP
0_
0201_5%
PCH_SP
99_0201_1%
PCH_SP
PCH_SP
99_0201_1%
PCH_SP
BIOS_R[63]
0_
0402_5%
21
1CM-30T2R_SOD923-2
I_CS#1_R1
I_D0_R1
I_D1_R1
I_CLK_R1
I_CS#0_R1
I_D2_R1
I_D3_R1
JSPI
1
CONN@
1
I_CS#1
I_D0
I_D1
I_CLK
I_CS#0
I_D2
I_D3
2
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
2
1
GND1
2
2
GND2
ACES_50506-02041-P01
TLS CONFIDENTIALITY
HIGH
LOW(DEFAULT)
GPP_
C5
GPP_
C5
EC interface
HIGH
LOW (DEFAULT)
GPP_
ENABLE
DISABLE
1 2
RC277
@
1 2
RC397 2
ESPI
LPC
B23
1 2
RC317 1
for DCI-OOB
EXI BOOT STALL BYPASS
HIGH
LOW(DEFAULT)
WEAK
INTERNAL PD
ENABLED
DIABLED
+3.3
4
.7K_0402_5%
0K_0402_5%
+3.3
50K_0402_5%
V_ALW_PCH
V_ALW_PCH
DELL CONFIDENTIAL/PROPRIETARY
Comp
Comp
Comp
al Electronics, Inc.
al Electronics, Inc.
Titl
Titl
Titl
e
e
e
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
P09-M
P09-M
P09-M
CP(3/14)SPI,SMB,LPC
CP(3/14)SPI,SMB,LPC
CP(3/14)SPI,SMB,LPC
LA-G8
LA-G8
LA-G8
91P
91P
91P
1
8 102M
8 102M
8 102M
of
of
of
0.3
0.3
0.3
Page 9
5
D D
HDD_FALL_INT[67]
T12
PCH_3.3V_TS_EN[38]
CNV_BRI_PRX_DTX[52]
CNV
_RGI_PTX_DRX_R[52]
CNV
_BRI_PTX_DRX_R[52]
CNV
_RGI_PRX_DTX[52]
PU OPTION TO AVOID RSP SIGNALS
+1.
C C
B B
FROM FLOATING IN CASE INTERNAL PUS NOT ENABLED IN A0
8V_PRIM
12
12
+3.
3V_RUN
12
RC5
12
12
RC8
@
CNV
_BRI_PRX_DTX
RC7
2420K_0402_5% @
CNV
_RGI_PRX_DTX
RC7
3320K_0402_5% @
HDD
_FALL_INT
810K_0402_5%
PCH
_3.3V_TS_EN
RC7
47100K_0402_5% @
GPP
_A7
4110K_0402_5%
1 2
RC7
10 33_0402_5%
1 2
RC7
11 33_0402_5%
@
T39
9
PAD~D
@
T40
0
PAD~D
TS
TP
T38
T38
T37
T37
add I2C3 TP for for sensor IC(Reserved)
add I2C3_ANT TP for ACTIVE STEERING ANT for MERION 14"
TS_
TS_
@
PAD~D
TPM_PIRQ#[66]
I2C_SDA[38]
I2C_SCL[38]
I2C
I2C
@
8
@
9
@
8
@
9
1
1
PAD~D
PAD~D
PAD~D
PAD~D
P_S
TS_
INT#[38]
1_SDA_TP[63]
1_SCK_TP[63]
4
PRIM_CORE_OPT_DIS
GPP_A7
ONE_DIMM#
NRB_BIT
HDD_FALL_INT
1
PME#
TPM_PIRQ#
PCH_3.3V_TS_EN
GPP_B22
CNV_BRI_PRX_DTX
CNV
_RGI_PTX_DRX
CNV
_BRI_PTX_DRX
CNV
_RGI_PRX_DTX
3MM
_CAM_DET#
ENSOR_PWR_SAVE#
TS_
INT#
I2C
2_SDA_ALS
1
I2C
2_SCL_ALS
1
I2C
3_ANT_SDA
1
I2C
3_ANT_SCL
1
UC1F
CC27
GPP_B15/GSPI0_CS0#
CC32
GPP_A7/PIRQA#/GSPI0_CS1#
CE28
GPP_B16/GSPI0_CLK
CE27
GPP_B17/GSPI0_MISO
CE29
GPP_B18/GSPI0_MOSI
CA31
GPP_B19/GSPI1_CS0#
CA32
GPP_A11/PME#/GSPI1_CS1#/SD_VDD2_PWR_EN#
CC29
GPP_B20/GSPI1_CLK
CC30
GPP_B21/GSPI1_MISO
CA30
GPP_B22/GSPI1_MOSI
CK20
GPP_F5/CNV_BRI_RSP
CG19
GPP
_F6/CNV_RGI_DT
CJ20
GPP
_F4/CNV_BRI_DT
CH19
GPP
_F7/CNV_RGI_RSP
CR12
GPP
_C20/UART2_RXD
CP12
GPP
_C21/UART2_TXD
CN12
GPP
_C22/UART2_RTS#
CM12
GPP
CM11
CN11
CK12
CJ12
CF27
CF29
CH27
CH28
CJ30
CJ31
WHL-U42_BGA1528
+1.
8V_PRIM
1 2
12
_C23/UART2_CTS#
GPP
_C16/I2C0_SDA
GPP
_C17/I2C0_SCL
GPP
_C18/I2C1_SDA
GPP
_C19/I2C1_SCL
GPP
_H4/I2C2_SDA
GPP
_H5/I2C2_SCL
GPP
_H6/I2C3_SDA
GPP
_H7/I2C3_SCL
GPP
_H8/I2C4_SDA
GPP
_H9/I2C4_SCL
20K_0402_5%
RC8
42
CNV
4.7K_0402_5%
@
RC8
32
_RGI_PTX_DRX_R
I2C
, UART
3
ISH
6 o
f 20
GPP_D11/ISH_SPI_MISO/GSPI2_MISO
GPP_D12/ISH_SPI_MOSI/GSPI2_MOSI
GPP
GPP
_D16/ISH_UART0_CTS#/SML0BALERT#
GPP
GPP
GPP
_C14/UART1_RTS#/ISH_UART1_RTS#
GPP
_C15/UART1_CTS#/ISH_UART1_CTS#
GPP
_A12/ISH_GP6/BM_BUSY#/SX_EXIT_HOLDOFF#
GPP_D9/ISH_SPI_CS#/GSPI2_CS0#
GPP_D10/ISH_SPI_CLK/GSPI2_CLK
GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL
GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL
GPP
_H10/I2C5_SDA/ISH_I2C2_SDA
GPP
_H11/I2C5_SCL/ISH_I2C2_SCL
GPP
_D13/ISH_UART0_RXD
GPP
_D14/ISH_UART0_TXD
_D15/ISH_UART0_RTS#/GSPI2_CS1#
_C12/UART1_RXD/ISH_UART1_RXD
_C13/UART1_TXD/ISH_UART1_TXD
GPP
_A18/ISH_GP0
GPP
_A19/ISH_GP1
GPP
_A20/ISH_GP2
GPP
_A21/ISH_GP3
GPP
_A22/ISH_GP4
GPP
_A23/ISH_GP5
2
IR_CAM_DET#
CN22
CR22
TBT_DET#
CM22
GPP_D12
CP22
ISH_I2C0_ACC_SDA
CK22
ISH_I2C0_ACC_SCL
CH20
ISH_I2C1_ALS_SDA
CH22
ISH_I2C1_ALS_SCL
CJ22
ISH
CJ27
ISH
CJ29
SML0
CM24
SML0
CN23
WWA
CM23
CR24
SIO
CG12
CH12
LCD
CF12
PCH
CG14
ISH
BW35
ISH
BW34
ISH
CA37
ISH
CA36
ISH
CA35
ISH
CA34
ISH
BW37
NB_MODE for NB13/Bandon
LID_CL#_NB for NB13/Bandon
LID_CL#_TAB for NB13/Bandon
ISH
_I2C2_SDA
ISH
_I2C2_SCL
1
1
1
1
_I2C2_SDA
_I2C2_SCL
B_SMBDATA
B_SMBCLK
N_FULL_PWR_EN
_EXT_WAKE#
_CBL_DET#
_HDD_EN
_ACC1
1
_ACC2
1
_TABLE_MODE#
1
_ALS
1
_NB_MODE
1
_LID_CL#_NB
1
_LID_CL#_TAB
1
5/23 Fibocom recommend to PH 1.8V.
1 2
RC3
63 1K_0402_5%
1 2
RC3
62 1K_0402_5%
IR_CAM_DET# [38]
@
T415
PAD~D
@
T416
PAD~D
@
T401
PAD~D
@
T402
PAD~D
ISH
_I2C2_SDA [52]
ISH
_I2C2_SCL [52]
RESERVE
WWA
N_FULL_PWR_EN [52]
SIO
_EXT_WAKE# [58]
LCD
_CBL_DET# [38]
PCH
_HDD_EN [67]
@
T39
5
PAD~D
@
T39
6
PAD~D
@
T39
7
PAD~D
@
T39
8
PAD~D
@
T37
5
PAD~D
@
T37
6
PAD~D
@
T37
7
PAD~D
+3.
3V_RUN
SML
0B_SMBCLK
PRI
M_CORE_OPT_DIS
SIO
_EXT_WAKE#
SML0
B_SMBCLK
SML0
B_SMBDATA
GPP
_D12
LCD
_CBL_DET#
IR_
CAM_DET#
TBT_DET#
RF Request
RC8
RC7
RC8
RC8
RC8
RC7
RC3
1
+3.3V_ALW_PCH
RC400
10K_0402_5%
1 2
12
10K_0402_5%
RC401
@
1 2
CC1
476@RF@ 33P_0402_50V8J
Place close CPU side
+3.
1 2
62 10K_0402_5%
1 2
48 10K_0402_5%
1 2
29 1K_0402_5%@
1 2
30 1K_0402_5%@
1 2
47 100K_0402_5%
1 2
49 100K_0402_5%
12
45 100K_0402_5%
3V_ALW_PCH
+3.
3V_RUN
AR_DET#
HIGH NON AR
LOW A
R
M.2
CNVI MODES
0 = Integrated CNVi enable.
1 = Integrated CNVi disable. (Disable CNVi for bring up)
4
WEAK INTERNAL PU
DIMM Detect
HIGH
LOW
+3.
3V_ALW_PCH
5
PRI
M_CORE_OPT_DIS
SIO
SIO
_SLP_S0#[11,17,66,79,87]
ONE
_DIMM#
10K_0402_5%
12
RC5
3
1 DIMM
2 DIMM
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
_SLP_S0#
1
2
1 2
RC8
67 0_0201_5%@
RC6
INB
INA
3
1 2
60 0_0201_5%@
UC9
M
C74VHC1G32DFT2G_SC70-5~D
P
4
O
G
2
RES
ERVE FOR WAKE ON VOICE
VR_
LPM_R# [87]
DEL
Tit
Tit
Tit
le
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
L CONFIDENTIAL/PROPRIETARY
Com
Com
Com
pal Electronics, Inc.
pal Electronics, Inc.
pal Electronics, Inc.
P10
P10
P10
-MCP(4/14)GSPI,I2C,UART,ISH
-MCP(4/14)GSPI,I2C,UART,ISH
-MCP(4/14)GSPI,I2C,UART,ISH
LA-
LA-
LA-
G891P
G891P
G891P
1
9 10
9 10
9 10
of
of
of
2Monday, February 25, 2019
2Monday, February 25, 2019
2Monday, February 25, 2019
0.3
0.3
0.3
+3.
3V_ALW_PCH
NRB
1 2
RC8
31 4.7K_0402_5%
_BIT
NO REBOOT STRAP
2.2K_0402_5%
RC4
6
_B22
No REBOOT
REBOOT ENABLE
HIGH
LOW(DEFAULT)
Weak IPD
+3.
3V_ALW_PCH
A A
12
@
GPP
BOOT BIOS Destination(Bit 6)
HIGH
LOW(DEFAULT)
5
LPC
SPI
Page 10
5
4
3
2
1
AR,NB_Bandon DSC(follow WHL 180306C port map)
D D
M.2 3042 (LTE) --->
Card Reader RTS5242--->
10/100/1G LAN --->
M.2 2230(WLAN) --->
C C
Spindel HDD--->
M.2 3042(SATA Cache
or/HCA)--->
M2 2280 SSD --->
B B
USB3_PRX_DTX_N5[52]
USB3_PRX_DTX_P5[52]
USB3_PTX_DRX_N5[52]
USB3_PTX_DRX_P5[52]
PCIE
_PRX_DTX_N8[70]
PCIE
_PRX_DTX_P8[70]
PCIE
_PTX_DRX_N8[70]
PCIE
_PTX_DRX_P8[70]
PCIE
_PRX_DTX_N9[51]
PCIE
_PRX_DTX_P9[51]
PCIE
_PTX_DRX_N9[51]
PCIE
_PTX_DRX_P9[51]
PCIE
_PRX_DTX_N10[52]
PCIE
_PRX_DTX_P10[52]
PCIE
_PTX_DRX_N10[52]
PCIE
_PTX_DRX_P10[52]
SATA
_PRX_DTX_N11[67]
SATA
_PRX_DTX_P11[67]
SATA
_PTX_DRX_N11[67]
SATA
_PTX_DRX_P11[67]
PCIE
_PRX_DTX_N12[52]
PCIE
_PRX_DTX_P12[52]
PCIE
_PTX_DRX_N12[52]
PCIE
_PTX_DRX_P12[52]
PCIE
_PRX_DTX_N13[68]
PCIE
_PRX_DTX_P13[68]
PCIE
_PTX_DRX_N13[68]
PCIE
_PTX_DRX_P13[68]
PCIE
_PRX_DTX_N14[68]
PCIE
_PRX_DTX_P14[68]
PCIE
_PTX_DRX_N14[68]
PCIE
_PTX_DRX_P14[68]
PCIE
_PRX_DTX_N15[68]
PCIE
_PRX_DTX_P15[68]
PCIE
_PTX_DRX_N15[68]
PCIE
_PTX_DRX_P15[68]
PCIE
_PRX_DTX_N16[68]
PCIE
_PRX_DTX_P16[68]
PCIE
_PTX_DRX_N16[68]
PCIE
_PTX_DRX_P16[68]
1 2
RC50 1
Jony _12/21: Refer RVP keep it setting
570990_CFL_U_DDR4_RVP_CRB_Sch_Rev0p8.pdf
00_0402_1%
PCIE
PCIE
_RCOMPN
_RCOMPP
UC1H
BW9
PCIE5_RXN/USB31_5_RXN
BW8
PCIE5_RXP/USB31_5_RXP
BW4
PCIE5_TXN/USB31_5_TXN
BW3
PCIE5_TXP/USB31_5_TXP
BU6
PCIE6_RXN/USB31_6_RXN
BU5
PCIE6_RXP/USB31_6_RXP
BU4
PCIE6_TXN/USB31_6_TXN
BU3
PCIE6_TXP/USB31_6_TXP
BT7
PCIE
7_RXN
BT6
PCIE
7_RXP
BU2
PCIE
7_TXN
BU1
PCIE
7_TXP
BU9
PCIE
8_RXN
BU8
PCIE
8_RXP
BT4
PCIE
8_TXN
BT3
PCIE
8_TXP
BP5
PCIE
9_RXN
BP6
PCIE
9_RXP
BR2
PCIE
9_TXN
BR1
PCIE
9_TXP
BN6
PCIE
10_RXN
BN5
PCIE
10_RXP
BR4
PCIE
10_TXN
BR3
PCIE
10_TXP
BN10
PCIE
11_RXN/SATA0_RXN
BN8
PCIE
11_RXP/SATA0_RXP
BN4
PCIE
11_TXN/SATA0_TXN
BN3
PCIE
11_TXP/SATA0_TXP
BL6
PCIE
12_RXN/SATA1A_RXN
BL5
PCIE
12_RXP/SATA1A_RXP
BN2
PCIE
12_TXN/SATA1A_TXN
BN1
PCIE
12_TXP/SATA1A_TXP
BK6
PCIE
13_RXN
BK5
PCIE
13_RXP
BM4
PCIE
13_TXN
BM3
PCIE
13_TXP
BJ6
PCIE
14_RXN
BJ5
PCIE
14_RXP
BL2
PCIE
14_TXN
BL1
PCIE
14_TXP
BG5
PCIE
15_RXN/SATA1B_RXN
BG6
PCIE
15_RXP/SATA1B_RXP
BL4
PCIE
15_TXN/SATA1B_TXN
BL3
PCIE
15_TXP/SATA1B_TXP
BE5
PCIE
16_RXN/SATA2_RXN
BE6
PCIE
16_RXP/SATA2_RXP
BJ4
PCIE
16_TXN/SATA2_TXN
BJ3
PCIE
16_TXP/SATA2_TXP
CE6
PCIE
_RCOMP_N
CE5
PCIE
_RCOMP_P
CR28
GPP_
CP28
GPP_
CN28
GPP_
CM28
GPP_
WHL-U42_BGA1528
H12/M2_SKT2_CFG_0
H13/M2_SKT2_CFG_1
H14/M2_SKT2_CFG_2
H15/M2_SKT2_CFG_3
USB_
OC3#
USB_
OC0#
USB_
OC1#
USB_
OC2#
PCIE / USB3.1 / SATA
8 of
1 2
RC75
7 20K_0402_5%@
1 2
RC75
8 20K_0402_5%@
1 2
RC75
9 20K_0402_5%@
1 2
RC76
0 20K_0402_5%@
PCIE1_RXN/USB31_1_RXN
PCIE1_RXP/USB31_1_RXP
PCIE1_TXN/USB31_1_TXN
PCIE1_TXP/USB31_1_TXP
PCIE2_RXN/USB31_2_RXN/SSIC_1_RXN
PCIE2_RXP/USB31_2_RXP/SSIC_1_RXP
PCIE2_TXN/USB31_2_TXN/SSIC_1_TXN
PCIE2_TXP/USB31_2_TXP/SSIC_1_TXP
PCIE3_RXN/USB31_3_RXN
PCIE
3_RXP/USB31_3_RXP
PCIE
3_TXN/USB31_3_TXN
PCIE
3_TXP/USB31_3_TXP
PCIE
4_RXN/USB31_4_RXN
PCIE
4_RXP/USB31_4_RXP
PCIE
4_TXN/USB31_4_TXN
PCIE
4_TXP/USB31_4_TXP
USB2
.0
USB2
USB2
GPP_
E9/USB2_OC0#/GP_BSSB_CLK
GPP_
E10/USB2_OC1#/GP_BSSB_DI
GPP_
GPP_
GPP_
GPP_
20
_VBUSSENSE
GPP_
E11/USB2_OC2#
GPP_
E12/USB2_OC3#
GPP_
GPP_
GPP_
E0/SATAXPCIE0/SATAGP0
E1/SATAXPCIE1/SATAGP1
E2/SATAXPCIE2/SATAGP2
E8/SATALED#/SPI1_CS1#
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
_10N
USB2
_10P
_COMP
USB2
E4/DEVSLP0
E5/DEVSLP1
E6/DEVSLP2
RSVD
CB5
CB6
CA4
CA3
BY8
BY9
CA2
CA1
BY7
BY6
BY4
BY3
BW6
BW5
BW2
BW1
CE3
_1N
CE4
_1P
CE1
_2N
CE2
_2P
CG3
_3N
CG4
_3P
CD3
_4N
CD4
_4P
CG5
_5N
CG6
_5P
CC1
_6N
CC2
_6P
CG8
_7N
CG9
_7P
CB8
_8N
CB9
_8P
CH5
_9N
CH6
_9P
CC3
CC4
CC5
CE8
_ID
CC6
CK6
CK5
CK8
CK9
CP8
CR8
CM8
CN8
CM10
CP10
CN7
AR3
_69
USB2
M304
M228
USBC
USB2
_ID
VBUS
USB_
OC3#
HDD_
DEVSLP
HDD_
DET#
M304
2_PCIE#_SATA
M228
0_PCIE_SATA#
HDD_DET#_reserve and HDD_DEVSLP is reserve for HDD SATA direct connect to PCH
_ID
2_PCIE#_SATA
0_PCIE_SATA#
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
OMP
RC47 1
SENSE
RC49 1
Reser
ve
HDD_
@
RC33
7
1 2
1 2
RC52
1 1K_0402_5%@
1 2
RC73
0 1K_0402_5%@
USB3_PRX_MTX_N1 [46]
USB3_PRX_MTX_P1 [46]
USB3_PTX_MRX_N1 [46]
USB3_PTX_MRX_P1 [46]
USB3_PRX_DTX_N2 [71]
USB3_PRX_DTX_P2 [71]
USB3_PTX_DRX_N2 [71]
USB3_PTX_DRX_P2 [71]
USB3_PRX_DTX_N3 [72]
USB3
_PRX_DTX_P3 [72]
USB3
_PTX_DRX_N3 [72]
USB3
_PTX_DRX_P3 [72]
USB3
_PRX_DTX_N4 [72]
USB3
_PRX_DTX_P4 [72]
USB3
_PTX_DRX_N4 [72]
USB3
_PTX_DRX_P4 [72]
0_N1 [44]
0_P1 [44]
0_N2 [71]
0_P2 [71]
0_N3 [72]
0_P3 [72]
0_N4 [72]
0_P4 [72]
0_N6 [38]
0_P6 [38]
0_N7 [52]
0_P7 [52]
0_N8 [66]
0_P8 [66]
0_N9 [66]
0_P9 [66]
0_N10 [52]
0_P10 [52]
1 2
1 2
USB_
USB_
USB_
HDD_
M304
M228
M304
M228
13_0402_1%
USB2
_ID [44]
K_0402_5%
OC0# [71]
OC1# [72]
OC2# [72]
DEVSLP [67]
2_DEVSLP [52]
0_DEVSLP [68]
DET# [67]
2_PCIE#_SATA [58]
0_PCIE_SATA# [68]
0_0402_5%
-----> TYPE-C (GEN2)
-----> Ext USB3 Port 1 Charge
-----> Ext USB3 Port 2
-----> Ext USB3 Port 3
Typce-C(NON AR)
Ext
USB Port 1 Charge
Ext USB Port 2
Ext
USB Port 3
Camera
M.2
3042 (WWAN)
USH
FPR in PB
M.2 2230 (BT)
M228
0_PCIE_SATA#
2_PCIE#_SATA
DET#
DET#
@
RC76
RC76
RC76
RC52
M304
HDD_
HDD_
12
4 10K_0402_5%
12
6 10K_0402_5%
12
5 10K_0402_5%
1 2
0
1K_0402_5%
+3.3
+3.3
V_RUN
V_ALW_PCH
USB_
OC3#
RC83
USB_
USB_
USB_
M304
A A
2_DEVSLP
6
OC0#
RC83
7 10K_0402_5%
OC1#
RC83
9 10K_0402_5%
OC2#
RC83
8 10K_0402_5%
RC86
5 10K_0402_5%
10K_0402_5%
12
12
12
12
12
DELL CONFIDENTIAL/PROPRIETARY
Comp
Comp
Comp
al Electronics, Inc.
al Electronics, Inc.
Titl
Titl
Title
e
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
e
P11-
P11-
P11-
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
MCP(5/14)PCIE,USB,SATA
MCP(5/14)PCIE,USB,SATA
MCP(5/14)PCIE,USB,SATA
LA-G
LA-G
LA-G
891P
891P
891P
10 102M
10 102M
10 102M
of
of
1
of
0.3
0.3
0.3
Page 11
5
CLK_PCIE_N0[52]
M.2 3042 WWAN--->
M.2 2230 WLAN--->
D D
M.2 2280 SSD--->
LAN--->
Card Reader --->
+3.
3V_LAN
RL7
0 10K_0402_5%@
+3.
3V_ALW_DSW
RC3
23 10K_0402_5 %
RC6
+1.
0V_VCCST
7 1K_0402_5%
RC7
1 1K_040 2_5%
RC5
36 10K_040 2_5%@
C C
PCH GLITCH ISSUE MITIGATION(PDG p.130)
B B
+3.
3V_ALW_PCH
A A
H_C
PUPWR GD
100P_0402_50V8J
12
CC30
0ESD@
ESD Request:place near CPU side
CLK_PCIE_P0[52]
CLKREQ_PCIE#0[52]
+3.3V_RUN
CLK_PCIE_N1[52]
CLK_PCIE_P1[52]
CLKREQ_PCIE#1[52]
+3.3V_RUN
CLK_PCIE_N2[68]
CLK_PCIE_P2[68]
CLKREQ_PCIE#2[68]
+3.3V_RUN
CLK_PCIE_N3[51]
CLK_PCIE_P3[51]
CLKREQ_PCIE#3[51]
+3.3V_RUN
CLK_PCIE_N4[70]
CLK_PCIE_P4[70]
CLKREQ_PCIE#4[70]
+3.3V_RUN
LAN
_WAKE#
12
12
PCH
_PCIE_W AKE#
12
VCC
ST_PWRGD
12
PCH
_PWROK
12
SIO
_SLP_SUS #
12
RC2
29100K_0 402_5%
12
CC1
4650.33U_0402_ 10V6K~D @
SIO
_SLP_S4#
12
RC2
32100K_0 402_5%
12
CC1
4670.33U_0402_ 10V6K~D @
SIO
_SLP_S3#
12
RC2
31100K_0 402_5%
12
CC1
4680.33U_0402_ 10V6K~D @
SIO
_SLP_A#
12
RC2
33100K_0 402_5%
12
CC1
4690.33U_0402_ 10V6K~D @
SIO
_SLP_W LAN#
12
RC2
34100K_0 402_5%
12
CC1
4700.33U_0402_ 10V6K~D @
SIO
_SLP_LAN#
12
RC7
61100K_0 402_5%
12
CC1
4710.33U_0402_ 10V6K~D @
SIO
_SLP_S5#
12
RC2
30100K_0 402_5% @
PCH
_PLTRST#
12
RC2
37100K_0 402_5%
@
SIO
_SLP_S0#
12
RC7
63100K_0 402_5%
VCC
ST_PWRGD
100P_0402_50V8J
12
CC30
1ESD@
5
RC297 0_020 1_5%
1 2
@RF@
RC189 10K_0402_5 %
RC526 0_0402_5%
@RF@
RC522 10K_0402_5 %
RC727 0_0402_5%
@RF@
RC525 10K_0402_5 %
RC527 0_0402_5%
@RF@
RC523 10K_0402_5 %
RC528 0_0402_5%
@RF@
RC51 10K_0402 _5%
1 2
1 2
1 2
1 2
PCH
_PLTRST#
12
12
12
12
12
M
C74VHC1G08D FT2G SC70
S4 power side PD need @,need check
RC215
POP
NO Support Deep sleep
DE-POP
Support Deep sleep
PCH
_DPWR OK
1 2
RC2
15 0_0402_5%
@NDS3@
0.01UF_0402_25V7K
100K_0402_1%
12
1
@
CC26
RC22
6
0
2
RC7
@
UC7
PCH
_RSMRST#_AN D
CLKREQ_PC IE#0_R
CLKREQ_PC IE#1_R
CLKREQ_PC IE#2_R
CLKREQ_PC IE#3_R
CLKREQ_PC IE#4_R
1 2
39
+3.
3V_ALW_PCH
1
B
2
A
@
T35
5
1
12
0K_0402_5%
5
3
PAD~D
0_0402_5%
P
PCH
4
O
12
G
1
VCC
RC75
AW2
CF32
CE32
CF30
CE31
CE30
CF31
PLT
RST_LAN# [51]
_PLTRST#_AND
@
RC6
5
100K_0402_ 5%
PCH
_RSMRST#_AND[63,79]
H_C
PUPWR GD_R
ST_PWRGD[59,79]
ME_
SUS_PWR_ACK is for LPC use only
SUSA
CK# is for LPC use only
4
CPU@
UC1J
CLKOUT_PCIE_N_0
AY3
CLKOUT_PCIE_P_0
GPP_B5/SRCCLKREQ0#
BC1
CLKOUT_PCIE_N_1
BC2
CLKOUT_PCIE_P_1
GPP_B6/SRCCLKREQ1#
BD3
CLKOUT_PCIE_N_2
BC3
CLKOUT_PCIE_P_2
GPP_B7/SRCCLKREQ2#
BH3
CLKOUT_PCIE_N_3
BH4
CLKOUT_PCIE_P_3
GPP_B8/SRCCLKREQ3#
BA1
CLKOUT_PCIE_N_4
BA2
CLKOUT_PCIE_P_4
GPP_B9/SRCCLKREQ4#
BE1
CLKOUT_PCIE_N_5
BE2
CLK
OUT_PCIE_P_5
GPP
_B10/SRCCLKREQ5#
WHL-U42 _BGA1528
PCH
_PLTRST#_AND [38,52,68,70]
SYS
_RESET#[79]
1 2
RC7
7 1K_0402_5%@
1 2
RC7
8 62_0402_5%
SYS
PCH
PCH
T38
0
T38
1
PCH
_PCIE_WAKE#[58,59]
PM_
LANPHY_ENABLE[51]
PCH
_PLTRST#_AND
.047U_0402_16V7K
12
CC19
6ESD@
For ESD solution
4
3
CLOCK SINGNALS
10
of 20
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
GPD8/SUSCLK
XTAL_OUT
XCLK_BIASREF
CLKIN_XTAL
SRTCRST#
RTCRST#
XTAL_IN
RTCX1
RTCX2
AU1
AU2
BT32
CK3
CK2
CJ1
CM3
BN31
BN32
BR37
BR34
CLK_ITPXDP_N
CLK_ITPXDP_P
SUSCLK
XTAL24_IN_CPU
XTAL24_OUT_CPU
XCLK_BIASR EF
REFCLK_CNV
PCH_RTCX1
PCH_RTCX2
SRTCRST#
PCH_RTCRST#
1 2
RC530 0_0402_5%@
1 2
RC298 0_0402_5%@
@
1 2
RC402 60.4_040 2_1%
1 2
LC5 BLM15BD121S N1D_2P~DESD@
LC5 place near CPU side
ESD Request
0419 ESD YuHeng: follow Intel recomme ndation
RC56 20K_0402 _5%
CC24 1U_0 201_6.3V6M
PCH_RTCRST# [58,79]
RC57 20K_0402 _5%
CC25 1U_0 201_6.3V6M
1
SUSCLK [52,68]
12
CC93 0.1U 16V K X5R 020 1
1 2
1 2
1 2
1 2
2
1
2
CMO
S1 SHORT PADS~D@
CLK_ITPXDP_N_R [79]
CLK_ITPXDP_P_R [79]
REFCLK_CNV_L [52]
+RTC_CELL_PCH
CMOS1 must take care short & touch risk on layout placement
PCH
_PLTRST#
PCH
_PLTRST#_AND
Support DS3
No Support DS3
1 2
RC6
0 0_0402_5%@
1 2
RC7
38 0_0402_5 %@
RC439
RC440RE536 RC215 RC441RC442
V V V
X X
PLT
RST_TPM# [66]
X
X
V V V
X
VCC
DSW_EN_GPIO[18]
VCC
DSW_EN[58]
X
@
ALW
_PWRGD_3V_5V[63,85]
'V' mean POP, 'X' mean DE-POP
UC1
PCH
_PLTRST#
SYS
_RESET#
PCH
_RSMRST#_AN D
H_C
PUPWR GD
VCC
ST_PWRGD _CPU
_PWROK[58,79]
_PWROK[88 ]
_DPWROK[58]
LAN
GPP
_A13
1
@
PAD~D
GPP
_A15
1
@
PAD~D
_WAKE#[51,58]
K
BJ35
GPP
_B13/PLTRST#
CN10
SYS
_RESET#
BR36
RSM
RST#
AR2
PRO
CPWRGD
BJ2
VCC
ST_PWRGOOD
CR10
SYS
_PWROK
BP31
PCH
_PWROK
BP30
DSW
_PWROK
BV34
GPP
_A13/SUSWARN#/SUSPWRDACK
BY32
GPP
_A15/SUSACK#
BU30
WAK
E#
BU32
GPD
2/LAN_WAKE#
BU34
GPD
11/LANPHYPC
WHL-U42 _BGA1528
XDP
_DBRESET#[79]
SYSTEM POWER MANAGEMENT
GPP
11
of 20
+3.
3V_ALW_PCH
RC2
48
@
2.2K_0402_ 5%
1 2
@
RC2
1
CC7
0.1U_0402_2 5V6
2
GPP
_B12/SLP_S0#
GPD
GPD
GPD
GPD
9/SPL_WLAN#
GPD
GPD
3/PWRBTN#
GPD
1/ACPRESENT
GPD
INT
_B11/EXT_PWR_GATE#
GPP
_B2/VRALERT#
INP
1 2
43
8
4/SLP_S3#
5/SLP_S4#
10/SLP_S5#
SLP
_SUS#
SLP
_LAN#
6/SLP_A#
0/BATLOW#
RUDER#
UT3VSEL
SYS
0_0402_5%
BJ37
BU36
BU27
BT29
BU29
BT31
BT30
BU37
BU28
BU35
BV36
BR35
CC37
CC36
BT27
_RESET#
ESD Request:place near CPU side
SIO
SIO
SIO
PCH
INT
3.3
VRA
INP
12
_SLP_S0#
_SLP_S5#
_SLP_A#
_BATLOW#
RUDER#
V_CAM_EN #
LERT#
UT3VSEL
SYS
_RESET#
0.1U_0402_25V6
@ESD@
CC30
2
SIO
_SLP_S0# [9, 17,66,79,87]
SIO
_SLP_S3# [17 ,59,79]
SIO
_SLP_S4# [17 ,79,86,87]
SIO
_SLP_S5# [79 ]
SIO
_SLP_SUS# [58]
SIO
_SLP_LAN# [78]
SIO
_SLP_WLAN# [78]
SIO
_SLP_A# [79]
SIO
_PWRBTN# [58,79]
AC_
PRESENT [58]
3.3
V_CAM_EN# [38]
ESD Request
0419 ESD YuHeng: follow Intel recomme ndation
2
XTAL24_IN_CPU
XTAL24_OUT_CPU
PCH_RTCX2
1 2
RC4
45
0_0402_5%
+3.
3V_ALW_PCH
RC4
51
@
20K_0402_5 %
RC4
52
4.7K_0402_ 5%
REF
CLK_CNV
4.7P_0402_50V8C
ESD@
1
CC14
2
77
ESD Request:place near CPU side
Jony_1221: Refer RVP is 200 K ohm
570990_CFL_U_DDR4_RVP_CRB_Sch_Rev0p8.pdf
RECOMMENDED BY EMI
1 2
RC728 33_0402_5%
1 2
RC729 33_0402_5%
0_0402_5%
1 2
RC403
@
RC404
@
NDS3
R
B751540_S OD523
NDS3
R
B751540_S OD523
For deglitch,
refer to 575412_WHL_U_PDG rev0p8
0 = 3.3V supply is 3.3V +/- 5% (3.3V for bring up)
1 = 3.3V supply is 3.0V +/- 5%
1 2
INP
UT3VSEL
1 2
DC1
@
2 1
@
0_0402_5%
SIO
_SLP_SUS #
VCC
DSW_E N_Q
DC2
21
1 2
2
00K_0402_1%
XTAL24_IN
1 2
XTAL24_OUT
PCH_RTCX1_RPCH_RTCX1
PCH_RTCX2_R
@
RC531 0_0402_5%
RC5
@
REF
CLK_CNV
SUS
CLK
RC4
41
DS3@
1 2
0_0402_5%
RC4
42
@NDS3@
1 2
0_0402_5%
3.3
V_CAM_EN #
8/21 can change to 10K for merge to RP
PCH
_BATLOW#
AC_
PRESENT
INT
RUDER#
VRA
LERT#
SIO
_SLP_LAN#
RC59
XTAL24_OUT_R
1 2
RC66
10M_0402_5 %
1 2
1 2
32
0_0402_5%
RC7
51 10K_0402_5 %
1 2
RC4
8 1K_0 402_5%@
PCH
1 2
RC8
34 100K_040 2_5%
1 2
RC7
2 10K_ 0402_5%
1 2
RC5
55 10K_0402_5%
1 2
RC6
9 1M_0402_5%
1 2
RC7
3 10K _0402_5%
1 2
RC3
44 10K_0402_5 %@
1 2
RC6
8 10K _0402_5%@
1
15P_0402_5 0V8J
3
4
YC1
24MHZ_12PF_ 8Y24000034
1
2
15P_0402_5 0V8J
12
YC2
32.768KHZ_1 2.5PF_9H032 00042
ESR MAX=50k ohm
RTC
X2
12
_PRIM_EN [78,87]
+3.
3V_ALW_PCH
+3.
+RT
C_CELL_PCH
+3.
3V_ALW_PCH
+3.
CC21
1 2
CC22
1 2
CC23
1 2
15P_0402_5 0V8J
CC26
1 2
15P_0402_5 0V8J
3V_ALW_DSW
3V_ALW
DELL CONFIDENTIAL/PROPRIETARY
Com
Com
Com
pal Electronics, Inc.
pal Electronics, Inc.
Tit
Tit
Tit
le
le
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
le
P12
P12
P12
Size Docum ent Numbe r Rev
Size Docum ent Numbe r Rev
Size Docum ent Numbe r Rev
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronics, Inc.
-MCP(6/14)CLK,PM,RTC
-MCP(6/14)CLK,PM,RTC
-MCP(6/14)CLK,PM,RTC
LA-G
LA-G
LA-G
891P
891P
891P
1
11 10
11 10
11 10
of
of
of
0.3
0.3
0.3
2Mond ay, February 25, 2 019
2Mond ay, February 25, 2 019
2Mond ay, February 25, 2 019
Page 12
5
4
3
2
1
UC1G
BN34
HDA_SYNC/I2S0_SFRM
BN37
HDA_BCLK/I2S0_SCLK
BN36
HDA_SDO/I2S0_TXD
BN35
HDA_SDI0/I2S0_RXD
BL36
HDA_SDI1/I2S1_RXD/SNDW1_DATA
BL35
HDA_RST#/I2S1_SCLK/SNDW1_CLK
CK23
GPP_D23/I2S_MCLK
BL37
I2S1_SFRM/SNDW2_CLK
BL34
I2S1_TXD/SNDW2_DATA
1.8V
CJ32
GPP_H1/I2S2_SFRM/CNV_BT_I2S_BCLK/CNV_RF_RESET#
CH32
GPP_H0/I2S2_SCLK/CNV_BT_I2S_SCLK
1.8V
CH29
GPP_H2/I2S2_TXD/CNV_BT_I2S_SDI/MODEM_CLKREQ
CH30
GPP_
H3/I2S2_RXD/CNV_BT_I2S_SDO
CP24
GPP_
D19/DMIC_CLK0/SNDW4_CLK
CN24
GPP_
D20/DMIC_DATA0/SNDW4_DATA
CK25
GPP_
D17/DMIC_CLK1/SNDW3_CLK
CJ25
GPP_
D18/DMIC_DATA1/SNDW3_DATA
CF35
GPP_
B14/SPKR
WHL-U42_BGA1528
12
ENABLE
DISABLE
SPKR
3 2.2K_0402_5%@
AUDIO SDIO / SDXC
GPP_
A17/SD_VDD1_PWR_EN#/ISH_GP7
7 of
20
GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
GPP_G5/SD_CD#
GPP_G6/SD_CLK
GPP_G7/SD_WP
GPP_
A16/SD_1P8_SEL
SD_1
P8_RCOMP
SD_3
P3_RCOMP
RF Request. Place near CPU side (Intel MOW)
HDA_
RST#
1
1
2
CC33
2.2P_0402_50V8C
@RF@
HDA_
SDIN0
1
2
2
CC33
2.2P_0402_50V8C
@RF@
HDA_
SDOUT
1
3
2
CC33
2.2P_0402_50V8C
@RF@
CH36
CL35
CL36
CPU_GC6_FB_EN
CM35
CONTACTLESS_DET#
CN35
HOST_SD_WP#
CH35
AUD_PWR_EN
CK36
SKP_DET#
CK34
ISH_
BW36
BY31
CK33
SD_R
CM34
P_SENSOR_INT#
COMP
1
PAD~D
1
PAD~D
1
P
AD~D
1 2
RC11
6 200_0402_1%
CAM_MIC_CBL_DET# [38]
T383
@
CONTACTLESS_DET# [66]
HOST_SD_WP# [70]
AUD_PWR_EN [56]
@
T384
@
T385
CNVI
HDA_SDIN0[56]
_EN#[52]
ET#[63]
HDA_SYNC
HDA_BIT_CLK
HDA_SDOUT
HDA_RST#
WWAN_GPIO_WAKE#
CNV_RF_RESET#
CLKREQ_CNV#
CNVI
_EN#
KB_D
ET#
DGPU
_PWROK
SPKR
+3.3
V_ALW_PCH
RC18
TOP SWAP STRAP
HIGH
LOW(DEFAULT)
Inte
rnal 20k PD
1 2
HDA_SYNC_R[56]
HDA_BIT_CLK_R[56]
HDA_SDOUT_R[56]
47P_0402_50V8J
Close
+3.3
V_ALW_PCH
+3.3
V_RUN
ME_FWP_PCH[79]
RF@
to RC93
RC27
RC27
RC29
D D
C C
B B
ME_FWP_PCH
HDA_RST#_R[56]
HDA_BIT_CLK_R
1
CC27
2
RC72
5 10K_0402_5%
RC84
0 10K_0402_5%
8 10K_0402_5%
9 10K_0402_5%
2 10K_0402_5%
RC92 33_0402_5%
RC93 33_0402_5%EMI@
RC561 33_0402_5%
RC562 1K_0402_5%
RC560 33_0402_5%
CAM_
MIC_CBL_DET#
12
WWAN
_GPIO_WAKE#
12
CONT
ACTLESS_DET#
12
AUD_
PWR_EN
12
HOST
_SD_WP#
12
1 2
1 2
1 2
1 2
WWAN_GPIO_WAKE#[52]
CNV_RF_RESET#[52]
CLKREQ_CNV#[52]
DVT2.0
1210 Add CNVI_EN#
KB_D
DGPU
_PWROK[58]
SPKR[
56]
+3.3
V_ALW_PCH
KB_D
ET#
RC28
A A
12
8 10K_0402_5%
CLKR
12
RC75
2 71.5K_0402_1%
1 2
RC64
0 75K_0402_5%
1 2
RC86
8 75K_0402_5%
5
CNV_
CNVI
EQ_CNV#
RF_RESET#
_EN#
+3.3
V_ALW_PCH
HDA_
SDOUT
RC18
12
7 4.7K_0402_5%@
Flash Descriptor Security override
HIGH
LOW(DEFAULT)
4
DISABLE
ENABLE
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DELL
CONFIDENTIAL/PROPRIETARY
Comp
Comp
Comp
al Electronics, Inc.
al Electronics, Inc.
Titl
Titl
Titl
e
e
e
P13-
P13-
P13-
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
MCP(7/14)MISC,JTAG,HDA,SDIO
MCP(7/14)MISC,JTAG,HDA,SDIO
MCP(7/14)MISC,JTAG,HDA,SDIO
LA-G
LA-G
LA-G
891P
891P
891P
1
0.3
0.3
12 102M
12 102M
12 102M
0.3
of
of
of
Page 13
5
4
3
2
1
1 2
RC120 1K_0402_1%@
EAR-STALL/NOT STALL RESET
SEQUENCE AFTER PCU PLL IS LOCKED
D D
CFG0
1 2
RC405 1K_0402_1%@
PCH/ PCH LESS MODE SELECTION
CFG1
1 2
RC4
06 1K_0402_1%@
PCI EXPRESS STATIC LANE REVERSAL
FOR ALL PEG PORTS
CFG2
C C
1 2
RC4
07 1K_0402_1%@
PCH/ PCH LESS MODE SELECTION
CFG3
1 2
RC7
23
0: AN EXTERNAL DISPLAY PORT DEVICE PORT IS CONNECTED TO THE EMBEDDED PORT
1: NO PHYSICAL DISPLAY PORT ATTACHED TO EMBEDDED DISPLAY PORT
DISPLAY PORT PRESENCE STRAP
CFG4
B B
RC4
RC4
1 2
09 1K_0402_1%@
1 2
10 1K_0402_1%@
CFG0
1:(DEFAULT)NORMAL OPERATION; NO STALL
0:STALL
CFG1
1: (DEFAULT) NORMAL OPERATION
0: PCH-LESS MODE
CFG
2
1: (DEFAULT)NORMAL OPERATION
0: LANE REVERSAL
CFG
3
1:(DEFAULT) NORMAL OPERATION
0: PCH-LESS MODE
CFG
4
1K_0402_5%
0: ENABLED
1: DISABLED;
CFG
5
CFG
6
1 2
RC411 1K_0402_1%@
PEG DEFER TRAINING
CFG7
1 2
RC412 1K_0402_1%@
ALLOW THE USE OF CFG ON LOCKED UNITS
1: DISABLED(DEFAULT); IN THIS CASE, CFG WILL BE
DISABLED IN LOCKED UNITS AND ENABLED IN UN-LOCKED UNITS AND
CFG8
0: EENABLED; CFG WILL BE
AVAILABLE REGARDLESS OF THE LOCKING OF THE UNIT
1 2
RC4
13 1K_0402_1%@
NO SVID PROTOCOL CAPABLE VR CONNECTED
CFG9
1 2
RC4
14 1K_0402_1%@
SAFE MODE BOOT
1: POWER FEATURES ACTIVATED DURING RESET
CFG10
0: POWER FEATURES (ESPECIALLY CLOCK GATINE ARE NOT ACTIVATED
1 2
RC4
15 1K_0402_1%@
DMI AC COUPLING - JUST A PLACE HOLDER.
NOT APPLICABLE FOR ULX-ULT
1:(DEFULT)
DMI WILL BE CONFIGURED AS HALF SWING DC COUPLED
CFG11
0:DMI WILL BE CONFIGURED AS FULL SWING AC COUPLED
1 2
RC4
16 1K_0402_1%@
PM SYNC LEGACY
CFG12
PCIE PORT BIFURCATION STRAPS
11: DEVICE1 FUNTION 1, DEVICE 1 FUNCTION2 DISABLED
10: DEVICE1 FUNTION 1, ENABLED DEVICE 1 FUNCTION2 DISABLED
RC4
1 2
17 1K_0402_1%@
CFG7
1: (DEFAULT) PEG TRAIN IMMEDIATELY
FOLLOWING XXRESETB DE ASSERTION
0: PEG WAIT FOR BIOS FOR TRAINING
CFG8
CFG
9
1:VRS SUPPORTING SVID PROTOCOL ARE PRESENT
0: NO VR SUPPORTING SVID
CFG
10
CFG
11
CFG
12
1: (DEFAULT) PMSYNC 2.0
0 : LEGACY
CFG
13
CFG[0..19][79]
Refer RVP CFG_RCOMP Keep 49.9 ohm to GND
570990_CFL_U_DDR4_RVP_CRB_Sch_Rev0p8.pdf
+1.
0V_PRIM_XDP
Refer RVP CFG_RCOMP Keep 1.5K to 1.0 VA
570990_CFL_U_DDR4_RVP_CRB_Sch_Rev0p8.pdf
nee
RC6
24 49.9_0402_1%
RC1
25 1.5K_0402_5%
ITP
_PMODE[79]
d check
UC1
Q
RES
_0
_1
_2
_3
_4
_5
_6
_7
_8
_9
_10
_11
_12
_13
_14
_15
_16
_18
_17
_19
_RCOMP
_PMODE
D25
D24
D34
D33
D22
D23
D66
D67
D17
D16
D35
D7
D6
D1
D30
D32
D31
ERVED SIGNALS
20
of 20
T4
CFG
0
CFG
R4
CFG
1
CFG
T3
CFG
2
CFG
R3
CFG
3
CFG
J4
CFG
4
CFG
M4
CFG
5
CFG
J3
CFG
6
CFG
M3
CFG
7
CFG
R2
CFG
8
CFG
N2
CFG
9
CFG
R1
CFG
10
CFG
N1
CFG
11
CFG
J2
CFG
12
CFG
L2
CFG
13
CFG
J1
CFG
14
CFG
L1
CFG
15
CFG
L3
CFG
16
CFG
N3
CFG
18
CFG
L4
CFG
17
CFG
N4
CFG
19
CFG
CFG
_RCOMP
12
ITP
_PMODE
12
AB5
CFG
W4
ITP
CG2
RSV
CG1
RSV
H4
RSV
H3
RSV
BV24
RSV
BV25
RSV
G3
RSV
G4
RSV
BK36
RSV
BK35
RSV
W3
RSV
AM4
RSV
AM3
RSV
A35
RSV
D34
RSV
G2
RSV
G1
RSV
WHL-U42_BGA1528
RSV
RSV
RSV
RSV
RSV
SKT
F37
D_TP5
F34
D_TP4
CP36
IST
_TRIG
CN36
D_TP3
BJ36
RSV
D15
BJ34
RSV
D14
BK34
TP_
1
BR18
TP_
2
BT9
RSV
D21
BT8
RSV
D20
BP8
RSV
D18
BP9
RSV
D19
CR4
RSV
D29
CP3
RSV
D26
CR3
RSV
D27
BP36
VSS
_434
AT3
RSV
D12
AU3
RSV
D13
AN1
RSV
D8
AN2
RSV
D9
AN4
RSV
D11
AN3
RSV
D10
AL2
RSV
D72
AL1
RSV
D73
AL4
RSV
D74
AL3
RSV
D75
BP34
TP_
4
BP35
TP_
3
C34
RSV
D68
A34
D_TP1
B35
D_TP2
CR35
RSV
D28
AH26
RSV
D36
AJ27
RSV
D37
E1
OCC#
SKT
@
RC4
OCC#
1
P
AD~D
1
P
AD~D
1
P
AD~D
1
P
AD~D
1
P
AD~D
1
P
AD~D
1
PAD~D
RC8
48 0_0201_5%
1
PAD~D
1
PAD~D
@
20
1
PAD~D
1
PAD~D
1
PAD~D
1
PAD~D
1 2
RC5
@
64 0_0402_5%
1 2
RC5
@
65 0_0402_5%
@
T16
@
T17
@
T18
@
T19
@
T20
@
T21
@
T36
12
@
T36
@
T36
0_0201_5%
12
@
T36
@
T36
@
T42
@
T41
0
1
3
+1.
0V_VCCSTG
4
5
3
9
12
36
RC4
100_0402_1%
@
CFG5,6
PCH/ PCH LESS MODE SELECTION
01: DEVICE1 FUNTION 1, DISABLED, DEVICE 1 FUNCTION2 ENABLED
00: DEVICE 1 FUNCTION 1 ENABLED, DEVICE 1 FUNCTION 2 ENABLED
PMSYNC AYNC MODE- PM SYNC
1: (DEFAULT)SYNCHCRONOUS (1 24 MHZ CYCLE PER BIT)
CFG13
0: ASYNC - 4-24MHZ CYCLES PER BIT
A A
RC4
1 2
18 1K_0402_1%@
CFG
14
RC4
1 2
19 1K_0402_1%@
CFG
15
DELL CONFIDENTIAL/PROPRIETARY
Com
Com
Com
pal Electronics, Inc.
pal Electronics, Inc.
CFG14 CFG15
5
Tit
Tit
Tit
le
le
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronics, Inc.
P14
P14
P14
-MCP(8/14)CFG,RSVD
-MCP(8/14)CFG,RSVD
-MCP(8/14)CFG,RSVD
LA-
LA-
LA-
G891P
G891P
G891P
1
13 10
13 10
13 10
of
of
of
0.3
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
2Monday, February 25, 2019
Page 14
5
+1.0V_VCCST
1 2
RC218 1K_0402 _1%
1 2
RC219 49.9_0402_1%@
1 2
CC1481 100P_0 201_50 V8JRF@
+1.0V_VCCSTG
1 2
RC558 1K_0402 _1%
D D
+3.3V_RUN
1 2
RC82 10K_0201_5%@
12
RC567 1 0K_040 2_5%
H_THERMTRIP#_R
H_CATERR#
PROCHOT#
TOUCH_SCREEN_PD#
TOUCHPAD_INTR#
PECI_EC[58]
PROCHOT#[58,84,88]
H_THERMTRIP#[23,24,59]
PROCHOT#
TOUCH_SCREEN_DET#[38]
@
TOUCHPAD_INTR#[58,63]
4
1 2
RC84 4 99_040 2_1%
1 2
RC559
0_0402_ 5%
XDP_OBS0_R[79]
XDP_OBS1_R[79]
12
12
6
7
RC10
RC10
49.9_0402_1%
CB34
CC35
BP27
BW25
AA4
AR1
Y4
BJ1
U1
U2
U3
U4
CE9
CN3
L5
N5
UC1D
CATERR#
PECI
PROCHOT#
THRMTRIP#
BPM#_0
BPM#_1
BPM#_2
BPM#_3
GPP_E3/ CPU_GP0
GPP_E7/ CPU_GP1
GPP_B3/ CPU_GP2
GPP_B4/ CPU_GP3
PROC_POP IRCOMP
PCH_OPIRCOMP
RSVD
RSVD
WHL-U42_BGA1528
H_CATERR#
PROCHOT#_R
H_THERMTRIP#_R
XDP_OBS0_R
XDP_OBS1_R
MEM_INTERLE AVED
TOUCH_SCREEN_PD#
TOUCHPAD_INTR#
CPU_POPIRCOMP
PCH_POPIRCOMP
EDRAM_OPIO_RCOMP
EOPI
O_RCOMP
12
12
9
8
RC10
RC10
49.9_0402_1%
@
@
49.9_0402_1%
49.9_0402_1%
need check
RC10
8,RC109
This is applicable only for CFL U43e. These pins are
RSVD in WHL and hence can be left unconnected
3
CPU_XDP_TCLK
T6
PROC_TCK
CPU MISC
70
71
4 of
PROC_TDI
JTAG
PROC_TDO
PROC_TMS
PROC_TRST#
PCH_TCK
PCH_TDI
PCH_TDO
PCH_TMS
PCH_TRST#
PCH_JTAGX
PROC_PREQ#
PROC_PRDY#
20
U6
Y5
T5
AB6
W6
U5
W5
P5
Y6
P6
W2
W1
CPU_XDP_TDI
CPU_XDP_TDO
CPU_XDP_TMS
CPU_XDP_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
CPU_XDP_TRST#
RC87 1 K_0201 _5%@
CPU_XDP_PREQ#
CPU_XDP_PRDY#
1 2
CPU_XDP_TCLK [79]
CPU_XDP_TDI [79]
CPU_XDP_TDO [79]
CPU_XDP_TMS [79]
1 2
RC86 51_0402_5%@
PCH_JTAG_TCK [79]
PCH_JTAG_TDI [79]
PCH_JTAG_TDO [79]
PCH_JTAG_TMS [79]
CPU_XDP_TRST# [79]
XDP_JTAGX [79]
+1.0V_VCCSTG
CPU_XDP_PREQ# [79]
CPU_XDP_PRDY# [79]
2
TOUCH_SCREE N_PD#
TOUCH_SCREEN_PD# don't move to RPC,
TOUCH_SCREE N_PD
TOUCH_SCREE N_PD#
L2N7002 DW1T1G_ SC88-6
Rese
rve for Panel side TS PH voltage problem
1 2
RC566 0_0402_ 5%@
+3.3V_RUN
12
RC104
10K_040 2_5%
6
2
QC4A
@
1
MEM_
INTERLEAVE D
TOUCH_SCREEN_PD#_R
@
+3.3
1
34
@
L2N7002 DW1T1G_ SC88-6
5
V_ALW_PCH
@
10K_040 2_5%
RC84
1 2
TOUCH_SCREEN_PD#_R [38]
QC4B
3
C C
B B
PCH_
JTAG_TDO
0.1U_0402_25V6
@ESD@
12
CC30
3
A A
PCH_
JTAG_TDI
0.1U_0402_25V6
@ESD@
12
CC30
4
ESD request,Place near CPU side.
XDP_
JTAGX
0.1U_0402_25V6
@ESD@
12
CC30
5
CPU_
XDP_TRST#
0.1U_0402_25V6
@ESD@
12
CC30
8
ESD request,Place near UC8 side.
1 2
10K_040 2_5%
RC84
4
DIMM TYPE
HIGH Interleave
Non-InterleaveLOW
DELL
CONFIDENTIAL/PROPRIETARY
Titl
Titl
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
Titl
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
e
e
e
onday, February 25, 2019
onday, February 25, 2019
onday, February 25, 2019
Comp
Comp
Comp
al Electronics, Inc.
al Electronics, Inc.
al Electronics, Inc.
P15-
P15-
P15-
MCP(9/14)XDP
MCP(9/14)XDP
MCP(9/14)XDP
LA-G8
LA-G8
LA-G8
1
91P
91P
91P
0.3
0.3
14 102M
14 102M
14 102M
0.3
of
of
of
Page 15
5
PSC(Primary side cap) : Place as close to the package as possible
BSC(Backside cap) : Place on secondary side, underneath the package
Component placement order:
Package edge > 0402 caps > 0805 caps > Bulk caps >Power source
+VCC_CORE: 0.55~1.5V, 29A
D D
+VCC_EDRAM: 1V, 2.5A
+V1.8S_EDRAM: 1.8V, 50mA - REMOVE
+VCC_EOPIO: 0.8~1V, 2A - REMOVE
UC1
O
K12
K14
K15
K17
K18
K20
L25
M24
M26
P24
P26
R24
R25
R26
W25
V24
C C
Y25
Y24
RESERVED SIGNALS
RSV
D48
RSV
D49
RSV
D50
RSV
D51
RSV
D52
RSV
D53
RSV
D54
RSV
D55
RSV
D56
RSV
D57
RSV
D58
RSV
D59
RSV
D60
RSV
D61
RSV
D62
RSV
D63
RSV
D64
RSV
D65
WHL-U42_BGA1528
15
of 20
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
4
AA24
D38
AA26
D39
AB25
D40
AC24
D41
AC25
D42
AC26
D43
AD24
D44
AD26
D45
D46
D47
VCC
V25
T25
EOPIO_SENSE
VSS
EOPIO_SENSE
1
@
T36
8
PAD~D
1
@
T36
9
PAD~D
@
T37
1
PAD~D
@
T37
2
PAD~D
@
T37
3
PAD~D
@
T37
4
PAD~D
1
1
1
1
+VC
+VC
+VC
+VC
3
C_CORE_G0
C_CORE_G1
C_CORE_G2
C_CORE_G3
+VCC_CORE
2
UC1L
AN9
VCCCORE5
AN10
VCCCORE1
AN24
VCCCORE2
AN26
VCCCORE3
AN27
VCCCORE4
AP2
VCCCORE6
AP9
VCCCORE9
AP24
VCCCORE7
AP26
VCCCORE8
AR5
VCCCORE13
AR6
VCCCORE14
AR7
VCCCORE15
AR8
VCCCORE16
AR10
VCCCORE10
AR25
VCCCORE11
AR27
VCCCORE12
AT9
VCCCORE19
AT24
VCC
AT26
VCC
AU5
VCC
AU6
VCC
AU7
VCC
AU8
VCC
AU9
VCC
AU24
VCC
AU25
VCC
AU26
VCC
AU27
VCC
AV2
VCC
AV5
VCC
AV7
VCC
AV10
VCC
AV27
VCC
AW5
VCC
AW6
VCC
AW7
VCC
AW8
VCC
AW9
VCC
AW10
VCC
BB9
RSV
BC24
RSV
AY9
RSV
BB24
RSV
WHL-U42_BGA1528
VCCOPC,VCCOPC_1P8,VCCEOPIO for SKYLAKE-U 2+3e
(w/ on package cache)
CORE17
CORE18
CORE24
CORE25
CORE26
CORE27
CORE28
CORE20
CORE21
CORE22
CORE23
CORE30
CORE32
CORE33
CORE29
CORE31
CORE39
CORE40
CORE41
CORE42
CORE43
CORE34
D3
D4
D1
D2
CPU POWER 1 OF 4
12
of 20
VCCCORE35
VCCCORE36
VCCCORE37
VCCCORE38
VCCCORE44
VCCCORE45
VCCCORE48
VCCCORE49
VCCCORE50
VCCCORE46
VCCCORE47
VCCCORE51
VCCCORE52
VCCCORE56
VCCCORE57
VCCCORE58
VCCCORE59
VCC
CORE53
VCC
CORE54
VCC
CORE55
VCC
CORE63
VCC
CORE64
VCC
CORE60
VCC
CORE61
VCC
CORE62
VCC
CORE69
VCC
CORE65
VCC
CORE66
VCC
CORE67
VCC
CORE68
VCC
CORE70
VCC
CORE73
VCC
CORE71
VCC
CORE72
VCC
CORE74
VCC
VSS
VID
VID
VCC
_SENSE
_SENSE
ALERT#
VID
SCK
SOUT
RSV
STG1
1
+VCC_CORE
AW24
AW25
AW26
AW27
AY24
AY26
BA5
BA7
BA8
BA25
BA27
BB2
BB26
BC5
BC6
BC7
BC9
BC10
BC26
BC27
BD5
BD8
BD10
BD25
BD27
BE9
BE24
BE25
BE26
BE27
BF2
BF9
BF24
BF26
BG27
AN6
AN5
AA3
AA1
AA2
Y3
D5
BG3
H_C
PU_SVIDALRT#
VID
SCLK_R
VID
SOUT_R
+1.
0V_VCCSTG_R
VCC
VSS
SENSE_R
SENSE_R
RC1
53
@
0_0402_5%
@
RC4
30
1 2
1 2
0_0402_5%
@
RC4
29
12
+VC
C_CORE
0_0603_5%
12
12
50
RC1
100_0402_1%
51
RC1
100_0402_1%
1V@
Close CPU
+1.
0V_VCCSTG
0.05A
VCC
_SENSE_IA [88]
VSS
_SENSE_IA [88]
+1.
SVID ALERT
B B
VID
ALERT_N[88]
SVID DATA
VID
SOUT[88]
SVID CLK
VID
A A
SCLK[88]
0V_VCCST
+1.
0V_VCCST
+1.
0V_VCCST
56_0402_1%
12
RC1
54
100_0402_1%
12
RC1
56
@
RC1
43_0402_5%
@
12
RC1
58
@
RC1
CAD Note: Place the PU resistors close to CPU
RC154 close to CPU 1000 - 1500mils
H_C
PU_SVIDALRT#
12
RC1
55220_0402_5%
CAD Note: Place the PU resistors close to CPU
RC156close to CPU 1000 - 1500mils
57
59
0_0402_5%
VID
VID
SOUT_R
SCLK_R
12
CAD Note: Place the PU resistors close to CPU
RC158close to CPU 1000 - 1500mils
0_0402_5%
12
DELL CONFIDENTIAL/PROPRIETARY
Com
Com
Com
pal Electronics, Inc.
pal Electronics, Inc.
Tit
Tit
Title
le
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Monday, February 25, 2019
Monday, February 25, 2019
Monday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronics, Inc.
P16
P16
P16
-MCP(10/14)PWR-VCC CORE
-MCP(10/14)PWR-VCC CORE
-MCP(10/14)PWR-VCC CORE
LA-
LA-
LA-
G891P
G891P
G891P
15
15
15
1
0.3
0.3
0.3
of
of
of
10
10
10
2
2
2
Page 16
5
4
3
2
1
THE BALLOUT ONLY FOR WHL ES2 CPU
D D
+VCCGT: 0.55~1.5V, 54A
+VCCGTX : 0.55~1.5V, 7A
+VCC_GT+VCC_GT+VCC_CORE
1.5V@54A
UC1M
A5
A6
A8
A11
A12
A14
A15
A17
A18
A20
AA9
AB2
AB8
AB9
AB10
AC8
AD9
AE8
AE9
AE10
C C
B B
AF10
AJ10
AL10
AF2
AF8
AG8
AG9
AH9
AK2
AK9
AM8
C11
C12
C14
C15
C17
C18
C20
D11
D12
D14
AJ8
AL8
AL9
V2
Y10
Y8
B3
B4
B6
B8
B11
B14
B17
B20
C2
C3
C6
C7
C8
D4
D7
CPU POWER 2 OF 4
VCCG
T8
VCCG
T9
VCCG
T10
VCCG
T1
VCCG
T2
VCCG
T3
VCCG
T4
VCCG
T5
VCCG
T6
VCCG
T7
ES1/
ES2
VCCG
T11/VCCCORE75
VCCG
T13/VCCCORE76
VCCG
T14/VCCCORE77
VCCG
T15/VCCCORE78
VCCG
T12/VCCCORE79
VCCG
T16/VCCCORE80
VCCG
T17/VCCCORE81
VCCG
T19/VCCCORE82
VCCG
T20/VCCCORE83
VCCG
T18/VCCCORE84
VCCG
T22/VCCCORE85
VCCG
T23/VCCCORE86
VCCG
T21/VCCCORE87
VCCG
T24/VCCCORE88
VCCG
T25/VCCCORE89
VCCG
T26/VCCCORE90
VCCG
T28/VCCCORE91
VCCG
T27/VCCCORE92
VCCG
T29//VCCCORE93
VCCG
T30/VCCCORE94
VCCG
T32/VCCCORE95
VCCG
T33/VCCCORE96
VCCG
T31/VCCCORE97
VCCG
T34/VCCCORE98
VCCG
T115/VCCCORE99
VCCG
T119/VCCCORE100
VCCG
T120/VCCCORE101
VCCG
T39
VCCG
T40
VCCG
T41
VCCG
T42
VCCG
T35
VCCG
T36
VCCG
T37
VCCG
T38
VCCG
T49
VCCG
T51
VCCG
T52
VCCG
T53
VCCG
T54
VCCG
T43
VCCG
T44
VCCG
T45
VCCG
T46
VCCG
T47
VCCG
T48
VCCG
T50
VCCG
T62
VCCG
T63
VCCG
T55
VCCG
T56
VCCG
T57
WHL-U42_BGA1528
D15
VCCG
T58
D17
VCCG
T59
D18
VCCG
T60
D20
VCCG
T61
E4
VCCG
T64
F5
VCCG
T69
F6
VCCG
T70
F7
VCCG
T71
F8
VCCG
T72
F11
VCCG
T65
F14
VCCG
T66
F17
VCCG
T67
F20
VCCG
T68
G11
VCCG
T73
G12
VCCG
T74
G14
VCCG
T75
G15
VCCG
T76
G17
VCCG
T77
G18
VCCG
T78
G20
VCCG
T79
H5
VCCG
T87
H6
VCCG
T88
H7
VCCG
T89
H8
VCCG
T90
H11
VCCG
T80
H12
VCCG
T81
H14
VCCG
T82
H15
VCCG
T83
H17
VCCG
T84
H18
VCCG
T85
H20
VCCG
T86
J7
VCCG
T95
J8
VCCG
T96
J11
VCCG
T91
J14
VCCG
T92
J17
VCCG
T93
J20
VCCG
T94
K2
VCCG
T98
K11
VCCG
T97
L7
VCCG
T100
L8
VCCG
T101
L10
VCCG
T99
M9
VCCG
T102
N7
VCCG
T104
N8
VCCG
T105
N9
VCCG
T106
N10
VCCG
T103
P2
VCCG
T107
P8
VCCG
T108
R9
VCCG
T109
T8
VCCG
T111
T9
VCCG
T112
T10
VCCG
T110
U8
VCCG
T114
U10
VCCG
T113
V9
VCCG
T116
W8
VCCG
T117
W9
VCCG
T118
VCCG
T_SENSE
T_SENSE
E3
D2
VCCG
VSSG
13 o
f 20
VSSG
T_SENSE_R
T_SENSE_R
1 2
1 2
RC63
@
2
@
RC63
1 0_0402_5%
0_0402_5%
+VCC
_GT
12
0
Clos
e CPU
RC16
100_0402_1%
VCC_
SENSE_GT [88]
VSS_
SENSE_GT [88]
12
1
RC16
100_0402_1%
A A
DELL CONFIDENTIAL/PROPRIETARY
Comp
Comp
Comp
al Electronics, Inc.
al Electronics, Inc.
Titl
Titl
Title
e
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
e
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
P17-
P17-
P17-
MCP(11/14)PWR-VCCGT
MCP(11/14)PWR-VCCGT
MCP(11/14)PWR-VCCGT
LA-G
LA-G
LA-G
891P
891P
891P
1
0.3
0.3
16 102M
16 102M
16 102M
0.3
of
of
of
Page 17
5
4
3
2
1
+1.2V_DDR: 1.2V, 3.5A
+1.0V_VCCST: 1V, 120mA; VCCPLL: 1V, 120mA
+1.0V_VCCSTG: 1V, 40mA
+VCCPLL_OC: 1.2V, 260mA
+1.0VS_VCCIO: 0.85~0.95V, 3.1A
+VCC_SA: 1.15V, 5.1A
D D
+VCCPLL_OC source
CZ1
02 1U_0201_6.3V 6M
VCC
STG_EN
SIO
_SLP_S3#[11,17,59,79]
SIO
_SLP_S0#[9 ,11,66,79,87]
C C
Follow 575962 RVP V0P7,VCCSFR_OC enable gated by VCCSTG_EN
1 2
@
RZ1
20 0_0402_5%
1 2
RZ1
418 0_0402_5%@
1 2
RZ1
419 0_0402_5%@
+1.2V_MEM +VCCPLL_OC
1 2
@
RZ1
19 0_040 2_5%
UZ27
1
VIN
PLL_EN
2
7
3
4
VIN
VIN
VBI
ON
EM5
1
2
thermal
AS
201V DFN3X3
12
+5V
_ALW
VCC
6
VOU
T
5
GND
+1.
0V_VCCSTG
2
CZ3
0.1U_0201_1 0V6K
1
+1.0V_VCCSTG source
+1.
0V_PRIM
+3.
3V_RUN
RZ1
422
1 2
CPU
_C10_GATE#[6,58,87]
RUN
B B
1 2
420
0_0402_5%
MC74VHC1G0 8DFT2G SC70
1 2
RZ3
20 0_040 2_5%@
RZ1
@
_ON[17,58,59,78,87]
100K_0402_5%
UZ3
5
12
CZ1
05 1U_02 01_6.3V6M
+5V
_ALW
+3.
3V_ALW
5
1
P
B
O
2
A
G
3
VCC
4
UZ19
1
VIN
2
VIN
7
VIN
3
VBI
4
ON
EM5
201V DFN3X3
4.4mohm/6A
TR=12.5us@Vin=1.05V
STG_EN
1
2
thermal
AS
Follow 575962 RVP V0P7,VCCSTG RAIL design
12
PJP
2
PAD-OPEN1x1m
+1.
0V_VCCSTG_C
6
VOU
T
5
GND
+1.0V_VCCST source
+1.
0V_PRIM
VCC
ST_EN
UZ21
1
VIN
1
2
VIN
2
7
VIN
thermal
3
VBI
AS
4
ON
EM5
201V DFN3X3
4.4mohm/6A
TR=12.5us@Vin=1.05V
+1.
0V_VCCST_C
6
VOU
T
5
GND
12
CZ1
00 1U_0201_6.3V 6M
+5V
_ALW
RZ1
RZ1
@
RZ1
_ON[17,58,59,78,87]
1 2
416 0_0402_5%@
1 2
417 0_0402_5%@
423 0_ 0402_5%
1 2
SIO
_SLP_S3#[11,17,59,79]
SIO
_SLP_S4#[11,79,86,87]
RUN
A A
Follow 575962 V0p7 PDG page519,Premium design Vccst gated by RUN_ON
PJP
1
PAD-OPEN1x1m
1 2
CZ1
01 0.1U_ 0201_10V6K
12
03
RZ1
1 2
51 0_060 3_5%@
+1.
pop option with UZ19
1 2
CZ1
06
0.1U_0201_1 0V6K
+1.
0V_VCCST
RF Request
0V_VCCST
+1.2V_MEM
RF@
1200P_0402_50V7K
1
CC14
78
2
place as close as CPU
RF@
680P_0402_50V7K
1
CC14
79
2
+1.0V_VCCST
PSC
1V@0.12A
0814 Confirmed with
Intel can change to 0201
CC28
U_0201_6.3V6M
1
PDG P.479 0402
+1.
0V_VCCSTG
close to package
+1.
0V_VCCSTG
1
2
1V@0.04A
1
0814 Confirmed with
PDG P.479 0402
+1.
2V_MEM
Primary Side
Secondary Side
Intel can change to 0201
CC29
2
U_0201_6.3V6M
1
+VC
CPLL_OC
PSC
1.2V@0.26A
close to package
1
1
2
CC32
RF@
2.2P_0402_50V8C
1
2
0U_0402_6.3V6M
1
1
2
0U_0402_6.3V6M
1
PDG P.479 0402
CC34
0U_0402_6.3V6M
1
CC46
0U_0402_6.3V6M
1
0
CC43
2
1U_0201_6.3V6M
0814 Confirmed with
Intel can change to 0201
1
1
CC35
CC36
2
2
0U_0402_6.3V6M
1
1
1
5
55
CC19
CC14
2
2
1U_0201_6.3V6M
2
RF Request
WHL
_U PDG rev0.8 P.479
VDDQ:
Primary Side cap
1x 22uF 0603 + 6x 10uF 0402
Secondary Side cap
4x 1uF 0402/0201 + 3x 10uF 0402
PDG P.479 22U 0603,10U 0402
1
1
CC32
CC33
2
2
2U_0603_6.3V6M
2
PDG P.479 1U 0402/0201,10U 0402
1
1
54
CC45
CC14
2
2
10U_0402_6.3V6M
Follow RVP rev1.0
1
80
CC14
2
PDG P.479 0805
Reserve
0.1U_0201_10V6K
1
1
CC37
2
2
0U_0402_6.3V6M
0U_0402_6.3V6M
1
1
1
1
56
CC14
2
2
1U_0201_6.3V6M
1U_0201_6.3V6M
+1.2V_MEM
AD36
1.2V@3.5A
AH32
AH36
AM36
AN32
AW32
AY36
BE32
BH36
R32
Y36
BC28
BP11
BP2
BG1
BG2
BL27
BM26
BR11
BT11
+1.
0V_VCCST_R
1V@0.12A
close to package
1
1
CC31
CC96
2
2
U_0201_6.3V6M
2U_0603_6.3V6M
1
2
PDG P.479 0402
PSC
Reserve for BSOD issue
0814 Confirmed with
Intel can change to 0201
CC38
0U_0402_6.3V6M
1
57
CC14
1U_0201_6.3V6M
UC1N
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDD
Q10
VDD
Q11
RSV
D1
VCC
ST1
VCC
ST2
VCC
STG1
VCC
STG2
VCC
PLL_OC1
VCC
PLL_OC2
VCC
PLL1
VCC
PLL2
WHL-U42 _BGA1528
@
0_0603_5%
1 2
1
PDG P.479 0201
62
CC14
2
0.1U_0201_10V6K
CPU POWER 3 OF 4
14
of 20
+1.
0V_VCCST
RC8
64
VCC
VSS
VCC
VSS
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
IO_SENSE
IO_SENSE
SA_SENSE
SA_SENSE
+VC
IO11
IO12
IO13
IO14
IO15
IO16
SA2
SA1
SA3
SA5
SA6
SA4
SA9
SA7
SA8
SA13
SA14
SA10
SA11
SA12
SA15
SA16
C_SA
+1.
0VS_VCCIO
+1.0VS_VCCIO
AK24
0.95V@3.1A
AK26
AL24
AL25
AL26
AL27
AM25
AM27
BH24
BH25
BH26
BH27
BJ24
BJ26
BP16
BP18
BG8
BG10
BH9
BJ8
BJ9
BJ10
BK8
BK25
BK27
BL8
BL9
BL10
BL24
BL26
BM24
BN25
BP28
BP29
BE7
BG7
RC1
Primary Side
VCC
IO_SENSE
VSS
IO_SENSE
@
RC4
25 0_040 2_5%
1 2
RC4
26
@
1 2
1 2
66 100_0402_1 %
PDG P.479 0201
1
1
58
CC14
2
2
1U_0201_6.3V6M
1.15V@5.1A
59
CC14
Primary or Secondary Side
1
1
4
5
CC23
CC23
2
2
10U_0402_6.3V6M
PDG P.479 0402
Placeholder
1
1
CC39
CC40
2
2
@
@
0U_0402_6.3V6M
1
0_0402_5%
1
2
1U_0201_6.3V6M
1
2
10U_0402_6.3V6M
1
2
0U_0402_6.3V6M
1
+VC
C_SA
12
4
RC16
100_0402_1%
WHL
VCCIO:
Primary Side cap
4x 1uF 0201
Primary or Secondary Side
6x 10uF 0402
Placeholder Only
1
4x 10uF 0402
61
60
CC14
CC14
2
1U_0201_6.3V6M
1U_0201_6.3V6M
PDG P.479 0402
1
1
6
7
CC51
CC23
CC23
2
2
0U_0402_6.3V6M
1
10U_0402_6.3V6M
10U_0402_6.3V6M
1
CC41
CC42
2
@
@
0U_0402_6.3V6M
0U_0402_6.3V6M
1
1
+1.
0VS_VCCIO
Clo
se CPU
12
RC1
63
100_0402_1 %
VCC
IO_SENSE [87]
VSS
IO_SENSE [87]
12
@
RC1
65
0_0201_5%
VSS
_SENSE_SA [88]
VCC
_SENSE_SA [88]
_U PDG rev0.8 P.479
1
CC52
2
0U_0402_6.3V6M
1
DEL
L CONFIDENTIAL/PROPRIETARY
Tit
Tit
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
Tit
Size Docum ent Numbe r Rev
Size Docum ent Numbe r Rev
Size Docum ent Numbe r Rev
Date: Sheet
Date: Sheet
Date: Sheet
Com
Com
Com
pal Electronics, Inc.
pal Electronics, Inc.
le
le
le
pal Electronics, Inc.
P18
P18
P18
-MCP(12/14)PWR-VCCIO,MEM
-MCP(12/14)PWR-VCCIO,MEM
-MCP(12/14)PWR-VCCIO,MEM
LA-G
LA-G
LA-G
1
891P
891P
891P
17 10
17 10
17 10
of
of
of
0.3
0.3
0.3
2Mond ay, February 25, 2 019
2Mond ay, February 25, 2 019
2Mond ay, February 25, 2 019
Page 18
5
4
3
2
1
close UC1 <100mil
1 2
LC1 LQM18PN2R2NC0L_2P~D
RC422
@
0.01_0603_1%
D D
+1.0
C C
1 2
0809 BSOD
Pop LC2 INDUCTOR,CC100 22U_0603
V_PRIM
depop RC175
Add CC103 22U_0603
1 2
LC2 LQ
RC17
5
@
0.01_0603_1%
1 2
+1.0
V_PRIM
M18PN2R2NC0L_2P~D
PJP3
1 2
P
AD-OPEN1x3m
1
2
+1.0V_MPHYGT source
close UC1 <120mil
0809 BSOD
Pop LC3 INDUCTOR,CC102 22U_0603
+1.0
V_MPHYGT
depop RC173
Add CC104 22U_0603
1 2
LC3 LQ
@
0.01_0603_1%
1 2
B B
A A
Support DS3
No Support DS3
'V' mean POP, 'X' mean DE-POP
RC17
M18PN2R2NC0L_2P~D
3
+3.3
V_ALW_DSW
22U_0603_6.3V6M
1
2
RC43
V V V
X X
5
1
1
2
2
CC104
22U_0603_6.3V6M
RC44
RC21
@
22U_0603_6.3V6M
@
CC27
CC280
1
9
2
9
RC440RE536RC215RC441 RC442
X
V V V
+1.0V_APLL+1.0V_PRIM
1
1
CC85
CC86
2
2
@
@
2U_0603_6.3V6M
22U_0603_6.3V6M
2
+1.0
V_CLK
1
1
1
0
CC83
2
2
2
CC10
CC103
22U_0603_6.3V6M
+1.0
CC102
CC10
PDG0.8 P.505 0402
0801 Confirmed with
Intel can change to 0201*2
1 2
0 0_0402_5%@NDS3@
1 2
4 0_0402_5%@
RC43
U_0201_6.3V6M
1
22U_0603_6.3V6M
CC10
3/CC83/CC70 close to CP5
PDG0.8 P.505 0402
0801 Confirmed with
Intel can change to 0201*2
V_MPHYGT
+1.0
V_AMPHYPLL
1
1
CC80
CC69
2
2
U_0201_6.3V6M
U_0201_6.3V6M
1
22U_0603_6.3V6M
1
4/CC80/CC69 close to BV2
+3.3
+3.3
1 2
9 0_0402_5%DS3@
X
X
CC70
U_0201_6.3V6M
1
PDG
rev0.8 P.509
Place an 22uF edge cap not more than
12 mm away measuring from package edge.
+3.3
V_ALW_PCH
LP23
V_ALW_DSW_R
12
DS3@
X
L2
N7002WT1G_SC-70-3
QC6
V_ALW_PCH
LC4
BL
M18EG221TN1D_2P~D
1 2
PDG P.505 no decoup.
12
@RF@
0_0402_5%
RC84
5
1
CC77
RF@
2
.2P_0201_25V
2
QC7DS3@
01ALT1G_SOT23-3
123
D
S
G
DS3@
49.9K_0402_1%
0.1U_0402_25V6K
RC43
12
@
CC34
3
0
13
D
2
G
S
+1.0
CC89 close to CP17
PCH Internal VRM
close to BT24
PDG P.505 0402
V_MPHYGT
1.05V@2.878A
2
1
+3.3
V_ALW
DS3@
499K_0402_1%
12
RC43
2
100K_0402_5%
1 2
4
+1.8V_PRIM
1.8V@0.696A
1
PDG P.505 0402
CC98
2
U_0201_6.3V6M
0814 Confirmed with
Intel can change to 0201
1
0814 Confirmed with
Intel can change to 0201
PDG P.504 0402 reserve
+VCC
PDSW_1P05
1.05V@0.024A
1
0814 Confirmed with
Intel can change to 0201
CC65
2
U_0201_6.3V6M
1
1
PDG P.504 0603
CC71
2
PDG P.505 no decoup.
RF@
2
.2P_0201_25V
RC43
1
VCCD
2U_0603_6.3V6M
2
VCCH
CC95
+1.0
V_MPHYGT
SW_EN_GPIO [11]
+1.0
+3.3
V_AMPHYPLL
+1.0
+1.0
V_ALW_DSW
DA
+3.3
V_ALW_PCH
+1.0
V_PRIM
+1.0
V_APLL
+1.0V_PRIM
1.05V@1.625A
CC67/CC68 close to BP20
1
CC68
2
+3.3
V_ALW_PCH
3.3V@0.199A
+1.0
V_PRIM_CORE
1.05V@4.26A
CC66
close to BV18
1
CC66
@
2
U_0201_6.3V6M
1
+1.0
V_APLL
1.05V@0.102A
1.05V@0.152A
1.05V@0.102A
1.05V@0.129A
3.3V@0.001A
3.3V@0.006A
V_PRIM
3.3V@0.002A
V_PRIM
0814 Confirmed with
Intel can change to 0201
1
CC67
2
U_0201_6.3V6M
U_0201_6.3V6M
1
1
BP20
BW16
BW18
BW19
BY16
CA14
CC15
CD15
CD16
CP17
CB22
CB23
CC22
CC23
CD22
CD23
CP29
BU15
BU22
BV15
BV16
BV18
BV19
BV20
BV22
BW20
BW22
CA12
CA16
CA18
CA19
CA20
CB12
CB14
CB15
BT24
BU14
BV12
BW12
BW14
BY12
BY14
BR15
CC12
BR24
BT20
BV23
BT18
BT19
BU18
BU19
BT22
BP22
BV14
BV2
3
UC1P
VCCPRIM_1P05_1
VCCPRIM_1P05_9
VCCPRIM_1P05_10
VCCPRIM_1P05_11
VCCPRIM_1P05_12
VCCPRIM_1P05_14
VCCPRIM_1P8_1
VCCPRIM_1P8_4
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCD
VCCA
VCCP
VCCP
VCCP
VCCP
VCCP
VCCA
VCCA
VCCD
VCCD
VCCH
VCCS
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
WHL-U42_BGA1528
CPU POWER 4 OF 4
RIM_1P8_5
RIM_1P8_8
RIM_3P3_4
RIM_3P3_5
RIM_3P3_6
RIM_3P3_7
RIM_3P3_8
RIM_3P3_9
RIM_3P3_10
RIM_CORE1
RIM_CORE2
RIM_CORE3
RIM_CORE4
RIM_CORE5
RIM_CORE6
RIM_CORE7
RIM_CORE8
RIM_CORE9
RIM_CORE10
RIM_CORE11
RIM_CORE12
RIM_CORE13
RIM_CORE14
RIM_CORE15
RIM_CORE16
RIM_CORE17
RIM_CORE18
SW_1P05
PLL_1P05_4
RIM_MPHY_1P05_1
RIM_MPHY_1P05_3
RIM_MPHY_1P05_4
RIM_MPHY_1P05_5
RIM_MPHY_1P05_6
MPHYPLL_1P05
PLL_1P05_2
USB_1P05
SW_3P3_1
DA
PI
RIM_1P05_4
RIM_1P05_5
RIM_1P05_7
RIM_1P05_8
RIM_1P05_6
RIM_1P05_2
RIM_MPHY_1P05_2
16 o
f 20
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
VCCPRIM_3P3_3
VCCPRIM_1P05_13
VCCP
VCCA
VCCA
VCCA
VCCA
VCCA
VCCD
VCCD
VCCD
VCCD
VCCD
VCCD
VCCA
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
GPP_
GPP_
VCCRTC
DCPRTC
RIM_1P05_3
PLL_1P05_3
_BCLK_1P05
PLL_1P05_1
_SRC_1P05
_XTAL_1P05
PHY_1P24_2
PHY_1P24_4
PHY_1P24_1
PHY_1P24_3
PHY_1P24_5
SW_3P3_2
_19P2_1P05
RIM_1P8_2
RIM_1P8_3
RIM_1P8_6
RIM_1P8_7
RIM_1P8_9
RIM_3P3_2
RIM_3P3_1
B0/CORE_VID0
B1/CORE_VID1
CB16
BR23
BY20
BP24
BR20
BT12
BP14
BR14
BU12
CP5
BY24
CA24
BY23
CA23
CP25
BT23
BR12
CC18
CC19
CD18
CD19
CP23
BW23
BP23
CB36
CB35
1.05V@0.009A
1.05V@0.102A
1.05V@0.034A
1.05V@0.034A
1.24V@0.61A
PCH Internal VRM
1.05V@0.027A
3.3V@0.199A
PDG P.505 0402 reserve
3.3V@0.199A
3.3V@0.199A
2
+3.3V_ALW_PCH
1
CC75
2
@
+1.0V_PRIM
PDG P.505 0201 reserve
+1.0
V_PRIM
+1.0
V_APLL
+1.0
V_PRIM
+1.0
V_APLL
+1.0
V_PRIM
+1.0
V_CLK
+VCC
+1.0
V_PRIM
+3.3
+3.3
CORE
_VID0 [87]
CORE
_VID1 [87]
0814 Confirmed with
Intel can change to 0201
CC74/CC75close to CP29
U_0201_6.3V6M
1
DCPRTC
PCH
close to BP24
LDOSRAM_1P24
1.8V@0.696A
V_ALW_PCH
V_ALW_PCH
DELL
CONFIDENTIAL/PROPRIETARY
+RTC_CELL_PCH
3.0V@0.002A
PDG P.505 0402
1
CC76
2
@
U_0201_6.3V6M
1
Internal VRM
CAD NOTE: CAPs
+VCC
DPHY_1P24
1
CC72
2
1
CC84
2
.7U_0402_6.3V6M
4
CC72/CC73 close to CP29
1
CC73
2
PDG P.505 0402
0814 Confirmed with
Intel can change to 0201
U_0201_6.3V6M
1
.1U_0201_6.3V6K
0
PCH Internal VRM
close to CP25
PDG P.505 0402
+3.3
V_ALW_DSW
3.3V@0.199A
1
63
+1.8
V_PRIM
1
64
2
CC1464 close to CP23
CC14
PDG P.505 0402 reserve
@
1U_0201_6.3V6M
0814 Confirmed with
Intel can change to 0201
Comp
Comp
Titl
Titl
Titl
e
e
e
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Comp
P19-
P19-
P19-
onday, February 25, 2019
onday, February 25, 2019
onday, February 25, 2019
CC1463 close to BR24
CC14
2
PDG P.505 0402 reserve
@
0814 Confirmed with
1U_0201_6.3V6M
Intel can change to 0201
al Electronics, Inc.
al Electronics, Inc.
al Electronics, Inc.
MCP(13/14)PCH PWR
MCP(13/14)PCH PWR
MCP(13/14)PCH PWR
LA-G
LA-G
LA-G
891P
891P
891P
18 102M
18 102M
1
18 102M
0.3
0.3
0.3
of
of
of
Page 19
5
4
3
2
1
D D
C C
B B
CR34
BT5
BY5
CP35
CM37
CK37
AW1
CM1
BD6
AY4
B34
E35
A4
AE24
AE26
AF25
AG24
AG26
AH24
AH25
B2
B36
C36
C37
CN1
CN2
CN37
CP2
D1
A32
F33
A3
BJ7
CJ36
A36
BK10
CJ4
AB27
BK2
CK1
AB3
BK28
AB30
BK3
CK4
AB33
BK33
CK7
AB36
BK4
CL2
AB4
BK7
CM13
AB7
BL25
CM17
AC10
BL28
CM21
AC27
BL29
CM25
AC30
BL30
CM29
BL31
CM31
AD33
BL32
CM33
AD35
WHL-U42_BGA1528
UC1R
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GND 1 OF 3
_10
_11
_12
_13
_14
_15
_16
_17
_18
_19
_20
_21
_22
_23
_24
_25
_26
_27
_28
_29
_30
_31
_32
_33
_34
_35
_36
_37
_38
_39
_40
_41
_42
_43
_44
_45
_46
_47
_48
_49
_50
_51
_52
_53
_54
_55
_56
_57
_58
_59
_60
_61
_62
_63
_64
_65
_66
_67
_68
_69
_70
_71
_72
17
of 20
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
_100
_101
_102
_103
_104
_105
_106
_107
_108
_109
_110
_111
_112
_113
_114
_115
_116
_117
_118
_119
_120
_121
_122
_123
_124
_125
_126
_127
_128
_129
_130
_131
_132
_133
_134
_135
_136
_137
_138
_139
_140
_141
_142
_143
_144
BL7
AE25
BM33
CM5
AE27
BM35
CM9
AE30
BM36
CN13
_82
AE7
_83
BM9
_84
CN17
_85
AF27
_86
BN30
_87
CN21
_88
AF3
_89
BN7
_90
CN25
_91
AF30
_92
CN29
_93
AF33
_94
BP15
_95
AF36
_96
AF4
_97
CN5
_98
AF7
_99
BP25
CN9
AG10
BP3
CP1
BP32
CP11
AH27
BP33
CP13
AH28
BP4
CP15
AH29
BP7
CP19
AH30
CP21
AH31
BR19
CP27
AH33
BR25
AH35
CP37
AJ25
BT15
AJ28
BT16
CP9
AJ7
CR2
AK3
CR36
AK33
D21
AK36
BT25
D25
AK4
BT28
AL28
BT33
D5
AL29
BT35
D6
AL32
BT36
D8
AL7
D9
AM10
BU11
E23
AM28
E27
AM33
BU23
E29
AM35
BU24
E31
BU25
E33
AN25
BU7
E9
AN28
BV11
F12
AN29
F15
AN30
F18
AN31
BV3
F2
AN7
BV31
F21
AN8
BV33
F24
BV4
F3
AP3
BW11
F4
AP33
BW15
G21
AP36
G27
AP4
G33
AR28
G35
G36
AT33
BW24
G9
AT35
H21
AT36
BW7
H27
AT4
BY11
AU10
BY15
H9
AU28
BY22
J12
AU29
J15
WHL-U42_BGA1528
UC1S
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS
_154
VSS
_155
VSS
_156
VSS
_157
VSS
_158
VSS
_159
VSS
_160
VSS
_161
VSS
_162
VSS
_163
VSS
_164
VSS
_165
VSS
_166
VSS
_167
VSS
_168
VSS
_169
VSS
_170
VSS
_171
VSS
_172
VSS
_173
VSS
_174
VSS
_175
VSS
_176
VSS
_177
VSS
_178
VSS
_179
VSS
_180
VSS
_181
VSS
_182
VSS
_183
VSS
_184
VSS
_185
VSS
_186
VSS
_187
VSS
_188
VSS
_189
VSS
_190
VSS
_191
VSS
_192
VSS
_193
VSS
_194
VSS
_195
VSS
_196
VSS
_197
VSS
_198
VSS
_199
VSS
_200
VSS
_201
VSS
_202
VSS
_203
VSS
_204
VSS
_205
VSS
_206
VSS
_207
VSS
_208
VSS
_209
VSS
_210
VSS
_211
VSS
_212
VSS
_213
VSS
_214
VSS
_215
VSS
_216
GND 2 OF 3
18
BY25
VSS_217
J18
VSS_218
AU32
VSS_219
BY28
VSS_220
J21
VSS_221
AV25
VSS_222
BY33
VSS_223
J24
VSS_224
AV28
VSS_225
BY35
VSS
_226
J33
VSS
_227
AV3
VSS
_228
BY36
VSS
_229
J36
VSS
_230
AV33
VSS
_231
J6
VSS
_232
AV36
VSS
_233
C1
VSS
_234
K21
VSS
_235
AV4
VSS
_236
C21
VSS
_237
K22
VSS
_238
AV6
VSS
_239
C25
VSS
_240
K24
VSS
_241
AV8
VSS
_242
C29
VSS
_243
K25
VSS
_244
AW28
VSS
_245
C33
VSS
_246
K27
VSS
_247
AW29
VSS
_248
C4
VSS
_249
K28
VSS
_250
AW3
VSS
_251
C9
VSS
_252
K29
VSS
_253
AW30
VSS
_254
CA11
VSS
_255
K3
VSS
_256
AW31
VSS
_257
CA15
VSS
_258
K30
VSS
_259
AY33
VSS
_260
CA22
VSS
_261
K31
VSS
_262
AY35
VSS
_263
K32
VSS
_264
B12
VSS
_265
K4
VSS
_266
B15
VSS
_267
CA25
VSS
_268
K9
VSS
_269
B18
VSS
_270
CB11
VSS
_271
L27
VSS
_272
B21
VSS
_273
L33
VSS
_274
B23
VSS
_275
L35
VSS
_276
B25
VSS
_277
CB18
VSS
_278
L36
VSS
_279
B27
VSS
_280
CB19
VSS
_281
L6
VSS
_282
B29
VSS
_283
CB2
VSS
_284
N25
VSS
_285
B31
VSS
_286
CB20
VSS
_287
N27
VSS
_288
CB25
VSS
_289
of 20
N6
VSS_290
B37
VSS_291
CB3
VSS_292
P10
VSS_293
B5
VSS_294
CB33
VSS_295
P3
VSS_296
B7
VSS_297
CB4
VSS
P33
VSS
B9
VSS
CB7
VSS
P36
VSS
BA10
VSS
CC11
VSS
P4
VSS
BA28
VSS
P7
VSS
BA3
VSS
CC20
VSS
R27
VSS
BB3
VSS
CC25
VSS
R28
VSS
BB33
VSS
CC28
VSS
R29
VSS
BB36
VSS
CC31
VSS
R30
VSS
BB4
VSS
CC7
VSS
R31
VSS
BC25
VSS
CD11
VSS
T27
VSS
CD12
VSS
T30
VSS
BC29
VSS
CD14
VSS
T33
VSS
T35
VSS
BC32
VSS
CD24
VSS
T36
VSS
CD25
VSS
T7
VSS
BC8
VSS
CE33
VSS
U26
VSS
BD28
VSS
CE35
VSS
U7
VSS
BD33
VSS
CE36
VSS
V26
VSS
BD35
VSS
CE7
VSS
V27
VSS
BD36
VSS
CF11
VSS
V3
VSS
BE10
VSS
CF14
VSS
V30
VSS
BE28
VSS
CF19
VSS
V33
VSS
BE29
VSS
CF2
VSS
V36
VSS
BE3
VSS
WHL-U42_BGA1528
UC1T
_298
_299
_300
_301
_302
_303
_304
_305
_306
_307
_308
_309
_310
_311
_312
_313
_314
_315
_316
_317
_318
_319
_320
_321
_322
_323
_324
_325
_326
_327
_328
_329
_330
_331
_332
_333
_334
_335
_336
_337
_338
_339
_340
_341
_342
_343
_344
_345
_346
_347
_348
_349
_350
_351
_352
_353
_354
_355
_356
_357
_358
_359
_360
_361
GND 3 OF 3
19
CF23
VSS_362
V4
VSS_363
BE30
VSS_364
CF28
VSS_365
W10
VSS_366
BE31
VSS_367
CF3
VSS_368
W27
VSS_369
CF4
VSS
_370
W30
VSS
_371
BF3
VSS
_372
CG33
VSS
_373
W7
VSS
_374
BF33
VSS
_375
CG7
VSS
_376
BF36
VSS
_377
Y26
VSS
_378
BF4
VSS
_379
CH31
VSS
_380
Y27
VSS
_381
BG25
VSS
_382
Y30
VSS
_383
BG28
VSS
_384
CJ11
VSS
_385
Y33
VSS
_386
CJ14
VSS
_387
Y35
VSS
_388
BH28
VSS
_389
CJ19
VSS
_390
Y7
VSS
_391
BH29
VSS
_392
CJ23
VSS
_393
BH32
VSS
_394
CJ28
VSS
_395
BH33
VSS
_396
CJ33
VSS
_397
BH35
VSS
_398
CJ35
VSS
_399
BP19
VSS
_400
BR16
VSS
_401
BY18
VSS
_402
BY19
VSS
_403
CC16
VSS
_404
BU16
VSS
_405
CC14
VSS
_406
BR22
VSS
_407
BU20
VSS
_408
CD20
VSS
_409
BT14
VSS
_410
BP12
VSS
_411
CB24
VSS
_412
CC24
VSS
_413
J5
VSS
_414
U24
VSS
_415
BD7
VSS
_416
AR4
VSS
_417
AU4
VSS
_418
AW4
VSS
_419
BA6
VSS
_420
BC4
VSS
_421
BE4
VSS
_422
BE8
VSS
_423
BA4
VSS
_424
BD4
VSS
_425
BG4
VSS
_426
CJ2
VSS
_427
CJ3
VSS
_428
AM5
VSS
_429
CM4
VSS
_430
AC5
VSS
_431
AG5
VSS
_432
CR6
VSS
_433
of 20
A A
DEL
L CONFIDENTIAL/PROPRIETARY
Com
Com
Com
pal Electronics, Inc.
pal Electronics, Inc.
Tit
Tit
Tit
le
le
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronics, Inc.
P20
P20
P20
-MCP(14/14)VSS
-MCP(14/14)VSS
-MCP(14/14)VSS
LA-
LA-
LA-
G891P
G891P
G891P
1
19 10
19 10
19 10
of
of
of
0.3
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
2Monday, February 25, 2019
Page 20
5
D D
C C
4
3
2
1
Reserve
B B
A A
DELL
CONFIDENTIAL/PROPRIETARY
Comp
Comp
al Electronics, Inc.
Titl
Titl
Titl
e
e
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
e
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
SOC o
SOC o
r PCH / FCH
r PCH / FCH
LA-G
LA-G
891P
891P
0.3
20 102M
20 102M
of
of
of
1
0.3
Page 21
5
D D
C C
4
3
2
1
Reserve
B B
A A
DEL
L CONFIDENTIAL/PROPRIETARY
Com
Com
pal Electronics, Inc.
Tit
Tit
Tit
le
le
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronics, Inc.
SOC
SOC
or PCH / FCH
or PCH / FCH
LA-
LA-
G891P
G891P
21 10
21 10
of
of
of
1
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
Page 22
5
D D
C C
4
3
2
1
Reserve
B B
A A
DELL
CONFIDENTIAL/PROPRIETARY
Comp
Comp
al Electronics, Inc.
Titl
Titl
Titl
e
e
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
e
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
SOC o
SOC o
r PCH / FCH
r PCH / FCH
LA-G
LA-G
891P
891P
0.3
22 102M
22 102M
of
of
of
1
0.3
Page 23
5
DDR_A_DQS#[0..7][7]
DDR_A_D[0..63][7]
DDR_A_DQS[0..7][7]
DDR_A_MA[0..16][7]
Layout Note:
Place near JDIMM1
D D
C C
B B
A A
+1.2V_MEM
+1.
0814 Confirmed with
Intel can change to 0201
+0.
6V_DDR_VTT
10P_0402_50V8J
12
*
10
10
U_0603_10V6M
U_0603_10V6M
CD2
CD1
12
12
12
2V_MEM
1U_
1
U_0201_6.3V6M
0201_6.3V6M
12
12
12
CD9
CD10
Layout Note:
Place near
JDIMM1.258
Refence WHL RVP rev0.7
Refence WHL RVP rev0.7
Refence WHL RVP rev0.7Refence WHL RVP rev0.7
1
0U_0603_10V6M
@
@
CD63
12
12
CD76RF
DIMM Select
SA01SA1
0
DIMM1
DIMM2
1
0
DIMM3
1
DIMM4
10U_0603_10V6M
10
10
U_0603_10V6M
U_0603_10V6M
CD4
CD3
12
12
1
1U_0201_6.3V6M
1
U_0201_6.3V6M
U_0201_6.3V6M
12
12
CD12
CD11
1
1
1U_0201_6.3V6M
U_0201_6.3V6M
0U_0603_10V6M
CD23
CD22
CD24
1
1
2
2
0814 Confirmed with
Intel can change to 0201
SA2
0
0
0
0
0
0
1
Refence WHL RVP rev0.7
Refence WHL RVP rev0.7
Refence WHL RVP rev0.7Refence WHL RVP rev0.7
10
10U_0603_10V6M
U_0603_10V6M
CD5
CD7
CD6
12
12
12
1
1U_0201_6.3V6M
U_0201_6.3V6M
12
12
12
CD15
CD13
CD14
WHL_U PDG rev0.8 P.92
VTT:
Place on VTT plane close to SODIMM
2x 10uF 0603(1 cap stuffed, 1 placeholder)
4x 1uF 0402
VDDSPD:
Place close to DIMM
2x 0.1uF 0402
2x 2.2uF 0402
1U_0201_6.3V6M
1
U_0201_6.3V6M
CD69
CD70
1
1
2
2
+3.
+3.
3V_RUN
3V_RUN
12
RD4
@
0
_0402_5%
12
0
_0402_5%
@
RD5
WHL
VDDQ:
4 near each side of the DIMM
3
10
30U_D3_2.5VY_R6M
connector close to VDD pins
U_0603_10V6M
16x 10uF 0603
@
12
16x 1uF 0402
CD17
CD8
+
Placeholder
1x 330uF 7343
VPP:
DIMM pin side, 1 per DIMM
2x 10uF 0603
2x 1uF 0402
+2.
1
U_0201_6.3V6M
CD16
0814 Confirmed with
Intel can change to 0201
+3.
3V_RUN
12
@
RD1
0_0603_5%
2
.2U_0402_6.3V6M
1
CD27
2
+3.
3V_RUN
12
12
12
@
0
_0402_5%
0
_0402_5%
@
RD8
RD6
@
0
_0402_5%
DIM
M1_SA0
DIM
M1_SA1
DIM
M1_SA2
12
0
_0402_5%
@
RD9
RD7
_U PDG rev0.8 P.92
5V_MEM
1
1
U_0201_6.3V6M
U_0201_6.3V6M
1
1
1
CD18
CD19
2
2
2
0
+3.
3V_RUN_DIMM 1
0
1
5P_0402_50V8J
.1U_0201_10V6K
RF@
1
CD28
12
CD73
2
+DD
R_VREF_A_ CA
4
3
2
1
For DDR4
Link LOTES_ADDR0206-P001A02 done 0410
CONN@
DDR_A_CLK 1[7]
DDR_A_CKE 1[7]
DDR
AD~D @
AD~D @
DDR
DDR
DDR
_A_ALERT#[7]
DDR_A_CLK 0
DDR_A_CLK #0
DDR_A_CLK 1
DDR_A_CLK #1
DDR_A_CKE 0
DDR_A_CKE1
DDR
_A_CS#0[ 7]
_A_CS#1[ 7]
_A_ODT0[7]
_A_ODT1[7]
_A_BG0[7]
_A_BG1[7]
_A_ACT#[7]
_A_PARITY[7]
12
_A_CS#0
DDR
_A_CS#1
1
T50P
1
T51P
DDR
_A_ODT0
DDR
_A_ODT1
DDR
_A_BG0
DDR
_A_BG1
DDR
_A_BA0
_A_BA0[7]
DDR
_A_BA1
_A_BA1[7]
DDR
_A_MA0
DDR
_A_MA1
DDR
_A_MA2
DDR
_A_MA3
DDR
_A_MA4
DDR
_A_MA5
DDR
_A_MA6
DDR
_A_MA7
DDR
_A_MA8
DDR
_A_MA9
DDR
_A_MA10
DDR
_A_MA11
DDR
_A_MA12
DDR
_A_MA13
DDR
_A_MA14
DDR
_A_MA15
DDR
_A_MA16
DDR
_A_ACT#
DDR
_A_PARITY
DDR
_A_ALERT#
JDI
MM1_EVEN T#
DDR
_DRAMRST#_R
DIM
M1_SA2
DIM
M1_SA1
DIM
M1_SA0
+1.
2V_MEM
4
70_0402_1%
RD11
DDR
_DRAMRST#
DDR_A_CLK 0[7]
DDR_A_CLK #0[7]
DDR_A_CLK #1[7]
DDR_A_CKE 0[7]
DDR
DDR
DDR
DDR
DDR
DDR
_XDP_W AN_SMBD AT[8,24,67,79]
_XDP_W AN_SMBC LK[8,24,67,79]
0_0402_5%
+1.
DDR
DDR
DDR
2V_MEM
1
1
0U_0603_10V6M
0U_0603_10V6M
1
CD21
CD20
2
1
CD2
9
@
0.1U_0402_2 5V6
0
.1U_0201_6.3V6K
1
1
CD25
2
2
DDR
_DRAMRST#_R[24]
2
2
.2U_0402_6.3V6M
CD26
1 2
@
RD1
2
137
139
138
140
109
110
1
49
1
57
162
165
155
161
1
15
1
13
1
50
1
45
14
13
13
13
12
12
12
12
12
12
146
1
20
1
19
1
58
151
156
152
114
143
116
134
108
2
54
2
53
1
66
2
60
2
56
92
91
101
105
88
87
100
104
97
95
12
33
54
75
178
199
220
241
96
DDR
_DRAMRST# [7]
JDIMM1A
REVERSE
CK0(T)
CK0#(C)
CK1(T)
CK1#(C)
CKE0
CKE1
S0#
S1#
S2#
/C0
S3#
/C1
ODT
0
ODT
1
BG0
BG1
BA0
BA1
4
A0
3
A1
2
A2
1
A3
8
A4
6
A5
7
A6
2
A7
5
A8
1
A9
A10
_AP
A11
A12
A13
A14
_WE#
A15
_CAS#
A16
_RAS#
ACT
#
PAR
ITY
ALE
RT#
EVE
NT#
RES
ET#
SDA
SCL
SA2
SA1
SA0
CB0
_NC
CB1
_NC
CB2
_NC
CB3
_NC
CB4
_NC
CB5
_NC
CB6
_NC
CB7
_NC
DQS
8(T)
DQS
8#(C)
DM0
#/DBI0#
DM1
#/DBI1#
DM2
#/DBI2#
DM3
#/DBI3#
DM4
#/DBI4#
DM5
#/DBI5#
DM6
#/DBI6#
DM7
#/DBI7#
DM8
#/DBI8#
LOTES_ADDR02 06-P001A
8
DQ0
7
DQ1
20
DQ2
21
DQ3
4
DQ4
3
DQ5
16
DQ6
1
7
DQ7
13
DQS
0(T)
11
DQS
0#(C)
2
8
DQ8
2
9
DQ9
41
DQ1
0
42
DQ1
1
24
DQ1
2
25
DQ1
3
38
DQ1
4
37
DQ1
5
34
DQS
1(T)
32
DQS
1#(C)
50
DQ1
6
49
DQ1
7
62
DQ1
8
63
DQ1
9
46
DQ2
0
45
DQ2
1
58
DQ2
2
59
DQ2
3
55
DQS
2(T)
53
DQS
2#(C)
70
DQ2
4
71
DQ2
5
83
DQ2
6
84
DQ2
7
66
DQ2
8
67
DQ2
9
79
DQ3
0
80
DQ3
1
76
DQS
3(T)
74
DQS
3#(C)
174
DQ3
2
173
DQ3
3
187
DQ3
4
186
DQ3
5
170
DQ3
6
169
DQ3
7
183
DQ3
8
182
DQ3
9
179
DQS
4(T)
177
DQS
4#(C)
195
DQ4
0
194
DQ4
1
207
DQ4
2
208
DQ4
3
191
DQ4
4
190
DQ4
5
203
DQ4
6
204
DQ4
7
200
DQS
5(T)
198
DQS
5#(C)
216
DQ4
8
215
DQ4
9
228
DQ5
0
229
DQ5
1
211
DQ5
2
212
DQ5
3
224
DQ5
4
225
DQ5
5
221
DQS
6(T)
219
DQS
6#(C)
237
DQ5
6
236
DQ5
7
249
DQ5
8
250
DQ5
9
232
DQ6
0
233
DQ6
1
245
DQ6
2
246
DQ6
3
242
DQS
7(T)
240
DQS
7#(C)
DDR
_VTT_CTRL[7]
DDR_A_D2
DDR_A_D5
DDR_A_D1
DDR_A_D7
DDR_A_D0
DDR_A_D4
DDR_A_D6
DDR_A_D3
DDR
_A_DQS0
DDR
_A_DQS#0
DDR
_A_D8
DDR
_A_D13
DDR
_A_D15
DDR
_A_D11
DDR
_A_D12
DDR
_A_D10
DDR
_A_D9
DDR
_A_D14
DDR
_A_DQS1
DDR
_A_DQS#1
DDR
_A_D32
DDR
_A_D36
DDR
_A_D34
DDR
_A_D35
DDR
_A_D37
DDR
_A_D33
DDR
_A_D39
DDR
_A_D38
DDR
_A_DQS4
DDR
_A_DQS#4
DDR
_A_D41
DDR
_A_D45
DDR
_A_D46
DDR
_A_D43
DDR
_A_D40
DDR
_A_D44
DDR
_A_D42
DDR
_A_D47
DDR
_A_DQS5
DDR
_A_DQS#5
DDR
_A_D29
DDR
_A_D25
DDR
_A_D30
DDR
_A_D26
DDR
_A_D28
DDR
_A_D24
DDR
_A_D27
DDR
_A_D31
DDR
_A_DQS3
DDR
_A_DQS#3
DDR
_A_D23
DDR
_A_D16
DDR
_A_D22
DDR
_A_D20
DDR
_A_D18
DDR
_A_D19
DDR
_A_D17
DDR
_A_D21
DDR
_A_DQS2
DDR
_A_DQS#2
DDR
_A_D52
DDR
_A_D49
DDR
_A_D55
DDR
_A_D51
DDR
_A_D48
DDR
_A_D53
DDR
_A_D54
DDR
_A_D50
DDR
_A_DQS6
DDR
_A_DQS#6
DDR
_A_D57
DDR
_A_D60
DDR
_A_D62
DDR
_A_D59
DDR
_A_D61
DDR
_A_D56
DDR
_A_D63
DDR
_A_D58
DDR
_A_DQS7
DDR
_A_DQS#7
1
NC
2
A
3
GND
7
4AUP1G07GW _TSSOP5
+DD
R_VREF_A_ CA
+1.
UD1
2V_MEM
5
Y
4
1 2
CD3
2@ 0.1U_0201_10V6 K
1 2
RD1
9 100K_0402_5 %
VCC
+3.
3V_RUN_DIMM 1
+DD
R_VREF_A_ CA
+1.2V_ME M
+DD
0.6
V_DDR_VTT_ON [86]
+3.
3V_RUN
CONN@
JDIMM1B
111
VDD1
112
VDD2
117
VDD3
118
VDD4
123
VDD
124
VDD
129
VDD
130
VDD
135
VDD
136
VDD
255
VDD
164
VRE
1
VSS
2
VSS
5
VSS
6
VSS
9
VSS
10
VSS
14
VSS
15
VSS
18
VSS
19
VSS
22
VSS
23
VSS
26
VSS
27
VSS
30
VSS
31
VSS
35
VSS
36
VSS
39
VSS
40
VSS
43
VSS
44
VSS
47
VSS
48
VSS
51
VSS
52
VSS
56
VSS
57
VSS
60
VSS
61
VSS
64
VSS
65
VSS
68
VSS
69
VSS
72
VSS
73
VSS
77
VSS
78
VSS
81
VSS
82
VSS
85
VSS
86
VSS
89
VSS
90
VSS
93
VSS
94
VSS
98
VSS
262
GND
264
NPT
LOTES_ADDR02 06-P001A
JDI
MM1_EVEN T#
R_VREF_A_CA
5
6
7
8
9
10
SPD
FCA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
1
H2
REVERSE
RD1
4 1K_0 402_5%@
6/8 Change to SA00007WE00 DII
VDD11
VDD12
VDD13
VDD14
VDD
VDD
VDD
VDD
VDD
VPP
VPP
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GND
NPT
1 2
+1.
2V_MEM
12
12
VTT
1
K_0402_1%
1
K_0402_1%
+1.2V_ME M
141
142
147
148
153
15
154
16
159
17
160
18
163
19
2
58
257
1
259
2
99
48
102
49
103
50
106
51
107
52
167
53
168
54
171
55
172
56
175
57
176
58
180
59
181
60
184
61
185
62
188
63
189
64
192
65
193
66
196
67
197
68
201
69
202
70
205
71
206
72
209
73
210
74
213
75
214
76
217
77
218
78
222
79
223
80
226
81
227
82
230
83
231
84
234
85
235
86
238
87
239
88
243
89
244
90
247
91
248
92
251
93
252
94
261
2
263
H1
RD15
1 2
RD1
7 2_0402_1%
RD16
12
2
12
4.9_0402_1%
RD18
+0.
6V_DDR_VTT
+2.
5V_MEM
H_T
HERMTRIP# [14,24,59]
+DD
R_VREF_CA
0
.022U_0402_16V7K
CD31
DEL
L CONFIDENTIAL/PROPRIETARY
Tit
Tit
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
Tit
Size Docum ent Numbe r Rev
Size Docum ent Numbe r Rev
Size Docum ent Numbe r Rev
Date: Sheet
Date: Sheet
Date: Sheet
Com
Com
Com
pal Electronics, Inc.
pal Electronics, Inc.
le
le
le
pal Electronics, Inc.
DDR
DDR
DDR
4 DIMMA
4 DIMMA
4 DIMMA
LA-G
LA-G
LA-G
891P
891P
891P
23 10
23 10
1
23 10
0.3
0.3
0.3
2Mond ay, February 25, 2 019
2Mond ay, February 25, 2 019
2Mond ay, February 25, 2 019
of
of
of
Page 24
5
DDR_B_DQS#[0..7][7]
DDR_B_D[0..63][7]
DDR_B_DQS[0..7][7]
DDR_B_MA[0..16][7]
4
3
2
1
For DDR4
Link LOTES_ADDR0206-P001A02 done 0410
CONN@
Layout Note:
D D
+1.2V_MEM
10
10
10
U_0603_10V6M
CD33
12
12
+1.2
V_MEM
1U_
0201_6.3V6M
12
12
CD41
0814 Confirmed with
Intel can change to 0201
C C
+0.6
V_DDR_VTT
10
1
RF@
0P_0402_50V8J
U_0603_10V6M
@
CD66
12
12
CD77
B B
10
U_0603_10V6M
U_0603_10V6M
U_0603_10V6M
CD34
CD35
CD36
12
12
1U_
1U_
1U_
0201_6.3V6M
0201_6.3V6M
0201_6.3V6M
12
12
CD42
CD43
CD44
Layout Note:
Place near
JDIMM2.258
Refence WHL RVP rev0.7
Refence WHL RVP rev0.7
Refence WHL RVP rev0.7Refence WHL RVP rev0.7
1U_
10
U_0603_10V6M
0201_6.3V6M
CD55
CD54
1
12
2
0814 Confirmed with
Intel can change to 0201
1
2
DIMM Select
SA2
SA01SA1
DIMM1
DIMM2
DIMM3
*
DIMM4
0
0
0
0
0
1
0
0
0
1
1
Place near JDIMM2
Refence WHL RVP rev0.7
Refence WHL RVP rev0.7
Refence WHL RVP rev0.7Refence WHL RVP rev0.7
10
10U_0603_10V6M
U_0603_10V6M
CD37
CD38
12
12
12
1U_
1U_0201_6.3V6M
0201_6.3V6M
12
12
12
CD45
CD46
1U_
1U_0201_6.3V6M
0201_6.3V6M
CD56
CD71
1
1
2
2
+3.3
+3.3
V_RUN
12
RD20
@
0
_0402_5%
12
0
_0402_5%
@
RD21
WHL_
U PDG rev0.8 P.92
VDDQ:
10
U_0603_10V6M
CD39
12
1U_
0201_6.3V6M
12
CD47
WHL_U PDG rev0.8 P.92
VTT:
Place on VTT plane close to SODIMM
2x 10uF 0603(1 cap stuffed, 1 placeholder)
4x 1uF 0402
VDDSPD:
Place close to DIMM
2x 0.1uF 0402
2x 2.2uF 0402
1U_0201_6.3V6M
CD72
V_RUN
12
0
_0402_5%
@
RD22
12
RD23
@
0
_0402_5%
4 near each side of the DIMM
10
33
U_0603_10V6M
0U_D3_2.5VY_R6M
connector close to VDD pins
@
16x 10uF 0603(2 DIMMS TOTAL)
12
CD40
CD49
+
16x 1uF 0402(2 DIMMS TOTAL)
Placeholder
1x 330uF 7343
VPP:
DIMM pin side, 1 per DIMM
2x 10uF 0603
2x 1uF 0402
+2.5
V_MEM
1U_
0201_6.3V6M
1
CD48
2
0814 Confirmed with
Intel can change to 0201
+3.3
V_RUN
12
12
0
1U_
0201_6.3V6M
CD50
RD24
@
0
_0402_5%
DIMM
DIMM
DIMM
_0402_5%
RD25
@
2_SA0
2_SA1
2_SA2
10
15
RF@
RF@
P_0402_50V8J
P_0402_50V8J
12
12
CD74
CD75
+3.3
V_RUN
12
12
1
2
@
0
_0603_5%
+DDR
1U_
0201_6.3V6M
CD51
RD26
2.
2U_0402_6.3V6M
CD59
_VREF_B_C A
1
2
+3.3
1
2
10
U_0603_10V6M
1
CD52
2
V_RUN_DIMM2
0.
1U_0201_10V6K
CD60
0.
1U_0201_6.3V6K
CD57
1
2
10
U_0603_10V6M
CD53
DDR_
DRAMRST#_R[23]
0
2.
2U_0402_6.3V6M
CD58
1
2
CD61
.1U_0402_25 V6
1
@
2
DDR_
DDR_
DDR_B_CLK 0[7]
DDR_B_CLK #0[7]
DDR_B_CLK 1[7]
DDR_B_CLK #1[7]
DDR_B_CKE 0[7]
DDR_B_CKE 1[7]
DDR_B_CS# 0[7]
DDR_B_CS# 1[7]
DDR_B_ODT0[7]
DDR_B_ODT1[7]
DDR_B_BG0[7]
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
XDP_W AN_SMBDA T[8,23,67,79]
XDP_W AN_SMBCL K[8,23,67,79 ]
DDR_B_CLK 0
DDR_B_CLK #0
DDR_B_CLK 1
DDR_B_CLK #1
DDR_B_CKE 0
DDR_B_CKE 1
DDR_B_CS# 0
DDR_B_CS# 1
T54PAD~D @
T55PAD~D @
DDR_B_ODT0
DDR_B_ODT1
DDR_B_BG0
DDR_B_BG1
B_BG1[7]
DDR_
B_BA0[7]
B_BA1[7]
B_PARITY[7]
B_ALERT#[7]
B_BA0
DDR_
B_BA1
DDR_
B_MA0
DDR_
B_MA1
DDR_
B_MA2
DDR_
B_MA3
DDR_
B_MA4
DDR_
B_MA5
DDR_
B_MA6
DDR_
B_MA7
DDR_
B_MA8
DDR_
B_MA9
DDR_
B_MA10
DDR_
B_MA11
DDR_
B_MA12
DDR_
B_MA13
DDR_
B_MA14
DDR_
B_MA15
DDR_
B_MA16
DDR_
B_ACT#
B_ACT#[7]
DDR_
B_PARITY
DDR_
B_ALERT#
JDIM
M2_EVENT#
DDR_
DRAMRST#_R
DIMM
2_SA2
DIMM
2_SA1
DIMM
2_SA0
+1.2
V_MEM
JDIM
M2_EVENT#
1 2
RD27 1
JDIMM2A
REVERSE
137
CK0(T)
139
CK0#(C)
138
CK1(T)
140
CK1#(C)
109
CKE0
110
CKE1
149
S0#
157
S1#
162
1
S2#/C0
1
165
S3#/C1
155
ODT0
161
ODT1
115
BG0
11
3
BG1
15
0
BA0
14
5
BA1
144
A0
133
A1
132
A2
131
A3
128
A4
126
A5
127
A6
122
A7
125
A8
121
A9
146
A10_
AP
12
0
A11
11
9
A12
15
8
A13
151
A14_
WE#
156
A15_
CAS#
152
A16_
RAS#
1
14
ACT#
143
PARI
TY
116
ALER
T#
134
EVEN
T#
108
RESE
T#
25
4
SDA
25
3
SCL
16
6
SA2
26
0
SA1
25
6
SA0
92
CB0_
NC
91
CB1_
NC
101
CB2_
NC
105
CB3_
NC
88
CB4_
NC
87
CB5_
NC
100
CB6_
NC
104
CB7_
NC
97
DQS8
(T)
95
DQS8
#(C)
12
DM0#
/DBI0#
33
DM1#
/DBI1#
54
DM2#
/DBI2#
75
DM3#
/DBI3#
178
DM4#
/DBI4#
199
DM5#
/DBI5#
220
DM6#
/DBI6#
241
DM7#
/DBI7#
96
DM8#
/DBI8#
LOTES_ADDR02 06-P001A
K_0402_5%@
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS0(T)
DQS0#(C)
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS1
(T)
DQS1
#(C)
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS2
(T)
DQS2
#(C)
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS3
(T)
DQS3
#(C)
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS4
(T)
DQS4
#(C)
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS5
(T)
DQS5
#(C)
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS6
(T)
DQS6
#(C)
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS7
(T)
DQS7
#(C)
H_TH
ERMTRIP# [14,23,59]
8
7
20
21
4
3
16
17
13
11
28
29
41
42
24
25
3
8
3
7
34
32
5
0
4
9
6
2
6
3
4
6
4
5
5
8
5
9
55
53
7
0
7
1
8
3
8
4
6
6
6
7
7
9
8
0
76
74
1
74
1
73
1
87
1
86
1
70
1
69
1
83
1
82
179
177
1
95
1
94
2
07
2
08
1
91
1
90
2
03
2
04
200
198
2
16
2
15
2
28
2
29
2
11
2
12
2
24
2
25
221
219
2
37
2
36
2
49
2
50
2
32
2
33
2
45
2
46
242
240
DDR_B_D1
DDR_B_D4
DDR_B_D6
DDR_B_D7
DDR_B_D0
DDR_B_D5
DDR_B_D3
DDR_B_D2
DDR_B_DQS0
DDR_B_DQS# 0
DDR_B_D13
DDR_B_D11
DDR_B_D14
DDR_B_D10
DDR_B_D9
DDR_B_D8
DDR_B_D12
DDR_
B_D15
DDR_
B_DQS1
DDR_
B_DQS#1
DDR_
B_D32
DDR_
B_D37
DDR_
B_D38
DDR_
B_D35
DDR_
B_D36
DDR_
B_D33
DDR_
B_D34
DDR_
B_D39
DDR_
B_DQS4
DDR_
B_DQS#4
DDR_
B_D41
DDR_
B_D47
DDR_
B_D43
DDR_
B_D42
DDR_
B_D45
DDR_
B_D46
DDR_
B_D40
DDR_
B_D44
DDR_
B_DQS5
DDR_
B_DQS#5
DDR_
B_D17
DDR_
B_D20
DDR_
B_D22
DDR_
B_D19
DDR_
B_D16
DDR_
B_D21
DDR_
B_D23
DDR_
B_D18
DDR_
B_DQS2
DDR_
B_DQS#2
DDR_
B_D25
DDR_
B_D29
DDR_
B_D27
DDR_
B_D30
DDR_
B_D24
DDR_
B_D28
DDR_
B_D26
DDR_
B_D31
DDR_
B_DQS3
DDR_
B_DQS#3
DDR_
B_D48
DDR_
B_D49
DDR_
B_D51
DDR_
B_D54
DDR_
B_D52
DDR_
B_D53
DDR_
B_D50
DDR_
B_D55
DDR_
B_DQS6
DDR_
B_DQS#6
DDR_
B_D57
DDR_
B_D60
DDR_
B_D59
DDR_
B_D63
DDR_
B_D61
DDR_
B_D56
DDR_
B_D58
DDR_
B_D62
DDR_
B_DQS7
DDR_
B_DQS#7
+DDR_VREF _B_CA
+3.3V_RUN_ DIMM2
+DDR_VREF _B_CA
+DDR
_VREF_B_CA
CONN@
JDIMM2B
REVERSE
111
VDD1
112
VDD2
117
VDD3
118
VDD4
123
VDD5
124
VDD6
129
VDD7
130
VDD8
135
VDD9
136
VDD10
255
VDDSPD
164
VREF
CA
1
VSS1
2
VSS2
5
VSS3
6
VSS4
9
VSS5
1
0
VSS6
1
4
VSS7
1
5
VSS8
1
8
VSS9
19
VSS1
0
22
VSS1
1
23
VSS1
2
26
VSS1
3
27
VSS1
4
30
VSS1
5
31
VSS1
6
35
VSS1
7
36
VSS1
8
39
VSS1
9
40
VSS2
0
43
VSS2
1
44
VSS2
2
47
VSS2
3
48
VSS2
4
51
VSS2
5
52
VSS2
6
56
VSS2
7
57
VSS2
8
60
VSS2
9
61
VSS3
0
64
VSS3
1
65
VSS3
2
68
VSS3
3
69
VSS3
4
72
VSS3
5
73
VSS3
6
77
VSS3
7
78
VSS3
8
81
VSS3
9
82
VSS4
0
85
VSS4
1
86
VSS4
2
89
VSS4
3
90
VSS4
4
93
VSS4
5
94
VSS4
6
98
VSS4
7
2
62
GND1
264
NPTH
2
LOTES_ADDR02 06-P001A
+1.2
V_MEM
1K
12
_0402_1%
RD28
RD30 2
1K
_0402_1%
12
RD29
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VTT
VPP1
VPP2
VSS4
VSS4
VSS5
VSS5
VSS5
VSS5
VSS5
VSS5
VSS5
VSS5
VSS5
VSS5
VSS6
VSS6
VSS6
VSS6
VSS6
VSS6
VSS6
VSS6
VSS6
VSS6
VSS7
VSS7
VSS7
VSS7
VSS7
VSS7
VSS7
VSS7
VSS7
VSS7
VSS8
VSS8
VSS8
VSS8
VSS8
VSS8
VSS8
VSS8
VSS8
VSS8
VSS9
VSS9
VSS9
VSS9
VSS9
GND2
NPTH
1 2
+1.2V_ME M+1.2V_ME M
141
142
147
148
153
154
159
160
163
258
2
57
2
59
99
8
102
9
103
0
106
1
107
2
167
3
168
4
171
5
172
6
175
7
176
8
180
9
181
0
184
1
185
2
188
3
189
4
192
5
193
6
196
7
197
8
201
9
202
0
205
1
206
2
209
3
210
4
213
5
214
6
217
7
218
8
222
9
223
0
226
1
227
2
230
3
231
4
234
5
235
6
238
7
239
8
243
9
244
0
247
1
248
2
251
3
252
4
2
61
263
1
_0402_1%
12
24
.9_0402_1%
12
RD31
+0.6V_DDR_ VTT
+2.5
V_MEM
+DDR
_VREF_B_DQ
0.
022U_0402_16V7K
CD62
A A
DELL
CONFIDENTIAL/PROPRIETARY
Comp
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al Electronics, Inc.
Titl
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PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
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e
Size Docum ent Numbe r Rev
Size Docum ent Numbe r Rev
Size Docum ent Numbe r Rev
onday, February 2 5, 2019
onday, February 2 5, 2019
onday, February 2 5, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
DDR4
DDR4
DDR4
DIMMB
DIMMB
DIMMB
LA-G8
LA-G8
LA-G8
91P
91P
91P
1
0.3
0.3
24 102M
24 102M
24 102M
0.3
of
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pal Electronics, Inc.
DDR
DDR
LA-
LA-
G891P
G891P
25 10
25 10
1
of
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0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
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4
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Size Document Number Rev
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Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
DDR
DDR
LA-G
LA-G
891P
891P
26 102M
26 102M
1
of
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0.3
0.3
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Date: Sheet
pal Electronics, Inc.
DGPU
DGPU
LA-
LA-
G891P
G891P
1
27 10
27 10
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
of
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onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
DGPU
DGPU
LA-G
LA-G
891P
891P
28 102M
28 102M
1
0.3
0.3
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Date: Sheet
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Date: Sheet
pal Electronics, Inc.
DGPU
DGPU
LA-
LA-
G891P
G891P
1
29 10
29 10
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
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Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
DGPU
DGPU
LA-G
LA-G
891P
891P
30 102M
30 102M
1
0.3
0.3
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Date: Sheet
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Date: Sheet
pal Electronics, Inc.
DGPU
DGPU
LA-
LA-
G891P
G891P
1
31 10
31 10
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
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onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
DGPU
DGPU
LA-G
LA-G
891P
891P
32 102M
32 102M
1
0.3
0.3
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Date: Sheet
pal Electronics, Inc.
DGPU
DGPU
LA-
LA-
G891P
G891P
1
33 10
33 10
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
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onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
DGPU
DGPU
LA-G
LA-G
891P
891P
34 102M
34 102M
1
0.3
0.3
of
of
of
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pal Electronics, Inc.
VRAM
VRAM
LA-
LA-
G891P
G891P
1
35 10
35 10
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
of
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Size Document Number Rev
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Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
VRAM
VRAM
LA-G
LA-G
891P
891P
36 102M
36 102M
1
0.3
0.3
of
of
of
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Date: Sheet
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Date: Sheet
pal Electronics, Inc.
DGPU
DGPU
_DC/DC Interface
_DC/DC Interface
LA-
LA-
G891P
G891P
1
37 10
37 10
of
of
of
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
Page 38
5
LINK 50398-04041-001 DONE
D D
C C
BIA_
PWM
12
DISP
12
B B
JEDP1
41
G1
42
G2
43
G3
44
G4
45
G5
ACES_5039 8-04041-001
CONN@
DV1
4.
7K_0402_5%
4.
7K_0402_5%
1
BA
RV1
_ON
RV2
T54CW_SO T323-3
DV2
1
BA
T54CW_SO T323-3
For signal deglitch, refer to 575412_WHL_U_PDG rev0p8.
it recommends to pop 100k, but 4.7k is ok so follow previous CKT .
+TS_PWR_SRC
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
EDP_
3
BIA_
2
3
2
USB20_N6_R
USB20_P6_R
EMI@
DISP_ON
BIA_PWM
PWM_EC
TOUC
EDP_
EDP_
EDP_
EDP_
EDP_
EDP_
PRIVACY_ENABLE [58]
+3.3V_RUN_QZ1
+3.3V_CAM
CAM_MIC_CBL_DET# [12]
Pin15: LOOP_BACK
+BL_PWR_SRC
1 2
LV1
EDP_
LCD_
+LCD
VDD
H_SCREEN_ DET#
AUXN_C
AUXP_C
TXP0_C
TXN0_C
TXP1_C
TXN1_C
LCD_
EDP_
BIA_
PANE
L_BKLEN [6]
PANE
L_BKEN_EC [58]
Due to SB12/14 Mic. receive path is different between Touch and
Non-Touch Panel, so add TOUCH_SCREEN_DET# pin for different verb
table
TOUCH_SCREEN_PD#_R [14]
2
A
ZC199-02SPR7G_SOT23-3
3
ESD@
223
DV14
1
TOUC
H_SCREEN_DET# [14]
12
1U_0402_25V 6
12
1U_0402_25V 6
12
1U_0402_25V 6
12
1U_0402_25V 6
12
1U_0402_25V 6
12
1U_0402_25V 6
1
EDP_
EDP_
EDP_
EDP_
EDP_
EDP_
EDP_
BIA_PWM
BLM15PX2 21SN1D_2P
HPD [6]
TST [58]
CV1 0.
CV2 0.
CV3 0.
CV4 0.
CV5 0.
CV6 0.
CBL_DET# [9]
BIA_PWM [6]
PWM_EC [58]
4
PRIVACY_ENA BLE
DMIC0 [56]
ESD@
3
DV13
AZ51
25-02S.R7G 3P C/A SOT23
1
DMIC_CLK0 [56]
1
8
00P_0402_50V8J
2P_0402_50V8J
12
12
CA5RF@
CA6RF@
EMI Request
HPD
1 2
RV7 10
AUXN [6]
AUXP [6]
TXP0 [6]
TXN0 [6]
TXP1 [6]
TXN1 [6]
0K_0402_5%@
TOUC
H_SCREEN_ DET#
If touch panel, GPIO Low-> Touch Mic. EQ ;
others the GPIO is High -> Non-Touch Mic.
EQ
1 2
RV802 1M_0 402_5%
+LCD
VDD
Reserve for EA
+3.3
V_RUN
10
K_0402_5%
RV8
1 2
3
TOUCH SCREEN & IR CAMERA connector
JIRTS1
CONN@
1
2
3
4
5
6
7
8
9
10
GND1
GND2
ACES_5020 8-01001-P03
1
2
3
4
5
6
7
8
9
10
11
12
PCH_PLTRST#_AND [11,52,68,70]
TS_INT# [9]
IR_CAM_DET# [9]
+13.5VB_FU+13.5VB_IR
1 2
LC6 HCB1608KF-1 21T30
RF@
1A_65V_T0603 FF1000TM
ACES_50208-01001-P03
Backlight POWER
+BL_
D
6
2
1
G
AO
6405_TSOP6
QV2
L2
N7002W T1G_SC-70-3
123
D
G
LP23
+3.3
V_CAM_F
PWR_SRC_P
12
S
QZ1
01ALT1G_SOT23-3
123
D
G
12
0.1U_0402_25V6K
1
000P_0402_50V7K
CV13
1 2
0
.01U_0402_50V7K
1
CV14
2
WebCAM
+3.3
V_CAM
3.3V
_CAM_EN#[11]
+13.
5VB
27
0K_0402_5%
1 2
RV5 47
EN_I
RV4
BL_P
WR_SRC_ON
1 2
NVPWR[58]
@
FZ5
2 1
1A
_65V_T0603FF10 00TM
@
RZ38
8 0_0402_5%
QV1
S
4 5
3
K_0402_5%
Replace RZ90 with FUSE (1206L150THWR 1.5A 8 V UL/TUV FAST) for OCP test
12
RZ14
850_0603_5% @
1 2
FZ1
21
FZ2
1A
_65V_T0603FF10 00TM
0
.1U_0402_25V6
CV15
RZ14
1A
+3.3
V_RUN_F
S
1A
@
RZ14
@
CZ22
0
+13.5VB
+BL_
PWR_SRC
21
1 2
84 0_0 603_5%@
@
FZ4
21
_65V_T0603FF10 00TM
FZ3
21
_65V_T0603FF10 00TM
1 2
86 0_0603_5%
223
1
3
1
+3.3
+3.3
A
ZC199-02SPR7G_SOT23-3
ESD@
DZ10
V_RUN_QZ1
V_RUN
2
TS_I2C_SDA [9]
TS_I2C_SCL [9]
LCDVDD POWER
1
For 2LANE EDP &5V_TSP,NB15
1 2
1 2
+EDP
_VDD
DV3
2
3
BA
T54CW_SO T323-3
+3.3V_RUN
12
12
12
12
1
1
VOUT
2
GND
3
/OC
G
524B1T11U_SO T23-5
EN_L
CDPWR
RF Request
+13.5VB
10
0P_0402_50V8J
1
2
UV24
5
VIN
4
EN
Touch pull up at the panel side
TS_I2C_SDA
RV98 2.2K_0402_5%@
TS_I2C_SCL
RV99 2.2K_0402_5%@
TS_INT#
RV311 100K _0402_5%@
TS_INT#
@
RV319 1K _0402_5%
RF Request
CV16
RF@
1
00P_0402_5 0V8J
TS_I2C_SDA
TS_I2C_SCL
+LCD
VDD
@JUMP@
12
LCD_
VCC_TEST_EN[58]
ENVD
D_PCH[6]
CV54@RF@ 33P_0402_5 0V8J
CV55@
RF@ 33P_0402_ 50V8J
PJP1
2
1 2
PAD-OPEN1x1m
1 2
LC7 H
CB1608KF-12 1T30RF@
RF@
CZ3
+3.3
V_ALW
0
.01UF_0402_25V7K
@
CV17
12
10
0K_0402_5%
RV3
1 2
LZ1
+TS_
Close to JEDP1.1
+BL_
PWR_SRC
Close to JEDP1.17~19
PWR_SRC
1
2
0
.1U_0603_50V7K
12
RF Request
+LCD
VDD
1
@RF@
2P_0402_50V8J
1
CV20
2
A A
+3.3
V_CAM
8
2P_0402_50V8J
1
2
1
RF@
RF@
RF@
1
2P_0402_50V8J
00P_0201_50V8J
1
12
CV21
CV12
CV22
2
5
+BL_
PWR_S RC
RF@
8
2P_0402_50V8J
1
2
1
100P_0201_50V8J
RF@
2P_0402_50V8J
1
12
CV31
CV23
2
RF@
8
RF@
RF@
100P_0201_50V8J
2P_0402_50V8J
1
12
CV75
CV24
CV25
2
7
+3.3
V_RUN
1
00P_0402_50V8J
0.1U_0201_10V6K
CV11
RF@
12
@
CZ20
CA75
3
Close to JEDP1.10
+3.3
V_CAM
@
Close to JEDP1.11
4
RF Request
0.
+TS_
1U_0201_10V6K
1
2
0.1U_0201_10V6K
1
2
PWR_S RC
@
CA7
8
1
RF@
RF@
2P_0402_50V8J
2P_0402_50V8J
1
1
CV19
CV18
2
2
@
CZ20
2
3.3V
_TS_EN[58]
PCH_
3.3V_TS_EN[9]
USB2
0_N6[10]
USB2
0_P6[10]
For Touchscreen
@
RV32
3
1 2
@
1 2
RV32
4 0_0402_5%
3
0_0402_5%
+3.3
V_RUN
12
EMI@
1
1
443
DL
M0NSN900HY2 D_4P
+TS_
+5V_
RUN
47
K_0402_5%
RV6
100K_0402_5%
1 2
RV32
RV40
0
@
6
L2
N7002WT1G_SC-70-3
13
D
QV7
2
G
S
USB2
0_N6_R
2
2
USB2
0_P6_R
3
PWR_SRC
FV1
1A
_65V_T0603FF10 00TM
LP23
PWR_QV 8
0_0402_5%
QV8
01ALT1G_SOT23-3
123
D
S
G
0.1U_0402_25V6K
12
@
1 2
RV73
3 0_0603_5%@
1 2
RV73
2 0_0603_5%@
CV63
5
2
+5V_
RUN
+3.3
V_RUN
2 1
+TS_
1 2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL
CONFIDENTIAL/PROPRIETARY
Comp
Comp
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al Electronics, Inc.
Titl
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e
e
Size Docum ent Numbe r Rev
Size Docum ent Numbe r Rev
Size Docum ent Numbe r Rev
onday, February 2 5, 2019
onday, February 2 5, 2019
onday, February 2 5, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
eDP
eDP
eDP
CONN & Touch screen
CONN & Touch screen
CONN & Touch screen
LA-G8
LA-G8
LA-G8
91P
91P
91P
1
0.3
0.3
38 102M
38 102M
38 102M
0.3
of
of
of
Page 39
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C C
4
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A A
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PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronics, Inc.
DP
DP
LA-
LA-
G891P
G891P
1
39 10
39 10
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
of
of
of
Page 40
5
5
3
+1.2V_RUN
0.1U_0402_25V6
0.1U_0402_25V6
D D
CPU_
CPU_
CPU_
CPU_
CPU_
CPU_
CPU_
CPU_
C C
CV314
CV30
DP1_P0[6]
CV30
DP1_N0[6]
CV30
DP1_P1[6]
CV30
DP1_N1[6]
CV30
DP1_P2[6]
CV30
DP1_N2[6]
CV30
DP1_P3[6]
CV30
DP1_N3[6]
+3.3
V_RUN
+3.3
V_RUN
0.1U_0402_25V6
CV31
CV31
1
1
3
2
2
2
12
4 0.1U_0402_10V7K
12
5 0.1U_0402_10V7K
12
2 0.1U_0402_10V7K
12
3 0.1U_0402_10V7K
12
0 0.1U_0402_10V7K
12
1 0.1U_0402_10V7K
12
6 0.1U_0402_10V7K
12
7 0.1U_0402_10V7K
1 2
RV30
0 4.7K_0402_5%@
1 2
RV30
2 4.7K_0402_5%
0.01U_0402_16V7K
0.1U_0402_25V6
CV31
CV31
1
2
1
1
0
1
2
2
HDMI_
TX_P0_C
HDMI_
TX_N0_C
HDMI_
TX_P1_C
HDMI_
TX_N1_C
HDMI_
TX_P2_C
HDMI_
TX_N2_C
HDMI_
CLKP_C
HDMI_
CLKN_C
HDMI
_BUF
HDMI
_EQ
HDMI
_PRE
4.02K_0402_1%
100K_0402_5%
12
12
@
RV73
RV30
7
3
4
UV21
19
VDD1
20
VDD2
31
VDD3
12
VDD4
40
VDD5
1
IN_D
2p
2
IN_D
2n
4
IN_D
1p
5
IN_D
1n
6
IN_D
0p
7
IN_D
0n
9
IN_C
Kp
10
IN_C
Kn
14
DDCB
UF/SDA_CTL
13
DCIN
_EN/SCL_CTL
17
EQ/I
2C_ADDR0
8
I2C_
CTL_EN
1
8
REXT
36
PD#
23
CFG
/ I2C_ADDR1
16
PRE
PS8407ATQFN40GTR2A1_TQFN40_5X5
PS8407ATQFN40GTR2-A1
VDD6
VDD7
OUT_D2p
OUT_D2n
OUT_
OUT_
OUT_
OUT_
OUT_
OUT_
SDA_
SCL_
SDA_
SCL_
HPD_
HPD_
GND1
GND2
EPAD
ISET
3
+3.3V_RUN
0.01U_0402_16V7K
0.1U_0402_25V6
CV30
CV30
9
11
37
TMDSE_RP_P2
30
TMDSE_RP_N2
29
TMDSE
_RP_P1
27
D1p
TMDSE
_RP_N1
26
D1n
TMDSE
_RP_P0
25
D0p
TMDSE
_RP_N0
24
D0n
TMDSE
_RP_CLK
22
CKp
TMDSE
_RP_CLK#
21
CKn
CPU_
DP1_CTRL_DATA
39
SRC
CPU_
DP1_CTRL_CLK
38
SRC
HDMI
_SDA_SINK
33
SNK
HDMI
_SCL_SINK
32
SNK
3
SRC
SNK
HDMI
_ISET
3
4
HDMI
_HPD_SINK
28
1
5
3
5
4
1
1
8
2
1
2
HDMI
_SCL_SINK
HDMI
_SDA_SINK
CPU_
DP1_CTRL_DATA [6]
CPU_
DP1_CTRL_CLK [6]
HDMI
_DP1_HPD [6]
HDMI
_HPD_SINK
1 2
RV73
5 2.2K_0402_5%
1 2
RV10 2
0K_0402_5%@
.2K_0402_5%
12
RV552
+VHDMI_VCC
2
TMDSE_RP_N2
TMDSE_RP_P2
TMDSE_RP_P1
TMDS
E_RP_N1
TMDS
E_RP_N0
TMDS
E_RP_P0
TMDS
E_RP_CLK
TMDS
E_RP_CLK#
1 2
RV686 5.6_0402_1%EMI@
@EMI@
LV3
1
1
4
1 2
1 2
LV6
4
1
1 2
9
1 2
0 5.6_0402_1%EMI@
@EMI@
LV9
1
4
1 2
1
1 2
2
LV12
4
1
1 2
3 8.2_0402_1%EMI@
@EMI@
@EMI@
2
3
5.6_0402_1%EMI@
3
2
5.6_0402_1%EMI@
2
3
5.6_0402_1%EMI@
8.2_0402_1%EMI@
3
2
4
DLW21SN900HQ2L_0805_4P
RV687 5.6_0402_1%EMI@
RV688
4
1
DLW21SN900HQ2L_0805_4P
RV68
RV69
1
4
DL
W21SN900HQ2L_0805_4P
RV69
RV69
4
1
D
LW21SN900HQ2L_0805_4P
RV69
1
2
3
3
2
2
3
3
2
TMDSE_CON_N2
RV683
150_0402_5%
1 2
TMDSE_CON_P2
TMDSE_CON_P1
RV684
150_0402_5%
1 2
TMDS
E_CON_N1
TMDS
E_CON_N0
RV65
4
150_0402_5%
1 2
TMDS
E_CON_P0
TMDS
E_CON_CLK
RV68
5
150_0402_5%
1 2
TMDS
E_CON_CLK#
+3.3
V_RUN
4.7K_0402_5%
12
RV30
4
HDMI_
BUF
4.7K_0402_5%
12
@
B B
A A
RV30
5
Receiver equalization setting; Internal pull down at ~150kΩ, 3.3V I/O.
L: programmable EQ for channel loss up to 5.3dB
H: programmable EQ for channel loss up to 10dB
M: programmable EQ for channel loss up to 14dB
+3.3
V_RUN
4.7K_0402_5%
12
@
RV20
8
HDMI_
ISET
4.7K_0402_5%
12
@
RV20
9
+3.3
V_RUN
4.7K_0402_5%
12
RV73
4
HDMI_
EQ
4.7K_0402_5%
12
@
RV30
7
+3.3
V_RUN
4.7K_0402_5%
12
RV20
7
HDMI_
PRE
4.7K_0402_5%
12
RV17
5
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
+5V_
RUN
0.1U_0201_10V6K
1
@
CV65
3
1
2
+3.3
V_RUN
IN
GND2OUT
AP
2330W-7_SC59-3
UV2
3
12
2
RV73
+VHD
MI_VCC
1
0
.1U_0201_10V6K
0U_0402_6.3V6M
CV27
1
12
@
CV26
2
HDMI
HDMI
_HPD_SINK
HDMI
_SDA_SINK
HDMI
_SCL_SINK
HDMI_
CECHDMI_CEC
TMDSE
6@10K_0402_5%
_CON_CLK#
TMDSE
_CON_CLK
TMDSE
_CON_N0
TMDSE
_CON_P0
TMDSE
_CON_N1
TMDSE
_CON_P1
TMDSE
_CON_N2
TMDSE
_CON_P2
DELL
CONFIDENTIAL/PROPRIETARY
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Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
connector
JHDM
I1
CONN@
19
HP_D
ET
18
+5V
17
DDC/
CEC_GND
16
SDA
15
SCL
14
Rese
rved
13
CEC
12
CK-
GND1
11
CK_s
GND2
hield
10
CK+
GND3
9
D0-
GND4
8
D0_s
hield
7
D0+
6
D1-
5
D1_s
hield
4
D1+
3
D2-
2
D2_s
hield
1
D2+
YUQIU_HD074-F19M1BR-C
Comp
Comp
Comp
al Electronics, Inc.
al Electronics, Inc.
al Electronics, Inc.
HDMI
HDMI
HDMI
LA-G
LA-G
LA-G
2
0
2
1
2
2
2
3
CONN
CONN
CONN
891P
891P
891P
0.3
0.3
40 102M
40 102M
40 102M
0.3
of
of
of
1
Page 41
5
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A A
DEL
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PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
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Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronics, Inc.
CRT
CRT
LA-
LA-
G891P
G891P
1
41 10
41 10
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
of
of
of
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C C
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A A
DELL
CONFIDENTIAL/PROPRIETARY
Comp
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Titl
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PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
e
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
TBT-
TBT-
AR-DP,PCIE
AR-DP,PCIE
LA-G
LA-G
891P
891P
0.3
42 102M
42 102M
of
of
1
of
0.3
Page 43
5
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C C
4
3
2
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Reserve
B B
A A
DEL
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PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
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Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronics, Inc.
TBT
TBT
-AR-VCC/VSS
-AR-VCC/VSS
LA-
LA-
G891P
G891P
1
43 10
43 10
of
of
of
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
Page 44
5
4
3
2
1
+3.3V_TBTA_FLA SH +3.3V_TBTA_FLA SH
12
12
12
12
CT70
RT50
.3K_0402_5%
3
1U_0402_16V7K
.
TBTA_ROM_HOLD#_PD
TBTA_ROM_CLK_PD_R UPD1_SMBDAT_Q
D D
C C
B B
A A
TBTA_ROM_DI_PD_R
TBTA_ROM_CLK_PD_R
TBTA_ROM_DI_PD_R
TBTA_ROM_DO_PD_R
TBTA_ROM_CS#_PD_R
7
GND1
8
GND2
JX
T_FP241AH-006GAAM
CONN@
DIV = R2/(R1+R2)
DIV_maxDIV_min
0.080.00
0.10
0.18
0.280.20
0.380.30
0.40
0.48
0.580.50
0.680.60
0.70 1.00
8
7
6
5
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
+3.3V_TBTA_FLA SH
JDB1
1
1
TBTA
2
2
TBTA
3
3
TBTA
4
4
TBTA
5
5
6
6
Configuratio n
0
1
2
3
4
5
76Infinite boot re try from Flas h to Host I/F cyc les.
UT6
TBTA_ROM_CS#_PD_R
1
CS#
VCC
HOLD#(IO3)
CLK
DI(IO0)
GD25Q80CSIGR_SO8
_ROM_CLK_PD_R
_ROM_DI_PD_R
_ROM_DO_PD_R
_ROM_CS#_PD_R
UFP
5V @0.9A S ink capabi lity with " Ask for Max/" f or
anything from 0.9 -3.0A
TBT Alternate Mo des not sup ported
DisplayPort Alternate Mo des not su pported
TI VID supported
UFP only
5V @0.9A S ink capabi lity with " Ask for Max/" f or
anything from 0.9 -3.0A
TBT Alternate Mo des not sup ported
DisplayPort Alternate Mo des -Sink, C and D pin configurati on
TI VID supported
UFP only
5V @3.0A S ource capab ility
TBT Alternate Mo des not sup ported
DisplayPort Alternate Mo des not su pported
TI VID supported
UFP only
5V @3.0A S ource capab ility
TBT Alternate Mo des not sup ported
DisplayPort Alternate Mo des -Sink, C and D pin configurati on
TI VID supported
DRP
5V @0.9-3.0A Sink cap ability
5V @3.0A S ource capab ility
TBT Alternate Mo des not sup ported
DisplayPort Alternate Mo des not su pported
TI VID supported
Accepts d ata and pow er role sw aps, but do es not
initiate.
DRP
5V @0.9-3.0A Sink cap ability
5V @3.0A S ource capab ility
TBT Alternate Mo des not sup ported
DisplayPort Alternate Mo des - Sourc e, C, D, and E
pin configu rations.
TI VID supported
Accepts p ower role s waps but will not i nitiate.
Accepts d ata role sw ap to UFP a nd can init iate.
DRP
5V @0.9-3.0A Sink cap ability
5V @3.0A S ource capab ility
TBT Alternate Mo des not sup ported
DisplayPort Alternate Mo des - Sourc e, C, D, and E
pin configu rations.
TI VID supported
Accepts p ower role s waps but will not i nitiate.
Accepts d ata role sw ap to DFP a nd can init iate.
DO(IO1)
WP#(IO2)
12
12
12
12
only
GND
RT54
RT55
RT56
RT57
DescriptionFactory Device
2
3
4
@
@
@
@
TBTA_ROM_DO_PD_R
TBTA_ROM_WP#_PD
TBTA_ROM_CLK_PD
TBTA_ROM_DI_PD
TBTA_ROM_DO_PD
TBTA_ROM_CS#_PD
12
RT52
RT53
RT51
.3K_0402_5%
.3K_0402_5%
3
3
.3K_0402_5%
3
UPD1_SMB CLK[58 ]
UPD1_SMB DAT[58]
UPD1_SMB INT#[5 8]
+3.3
V_TBTA_FLASH
RT76
1
0K_0402_1%
1 2
12
RT37
43K_0402_1%
RT81 1
RT82 1
MUX1_DP_S EL/MUX1_ USB_SEL c ontrol by:
GPIO: Pop RT69,RT90; Depop RT375,RT37 6
I2C:Depop RT69,RT90 ;pop RT375,RT376
PD1_G
PIO8
7
UART_
12
00K_0402_5%
UART_
12
M_0402_5%@
TI S
PEC: 100K PD
INTEL SCH :1M PD
Route in pass through manner so AUX can be snooped by 546
+3.3
V_TBTA_FLASH
CPU_DP
12
RT95 1
RT96 1
12
00K_0402_5%
CPU_DP
00K_0402_5%
+3.3V_VDD _PIC
0_0402_5%
1 2
5
QT1B
@
DMN66D0LDW-7_SOT363-6
@
RT59
1 2
1 2
1 2
RT48
2 0_0402_5%@
1 2
RT48
3 0_0402_5%
MUX1
EN_P
CPU_
USB2
MUX1
MUX1
+VCC1V
UPD1_SMBCLK_Q
34
0_0402_5%
+3.3
V_VDD_PIC_P DA
1
CT71
2
.2U_0402_25V6K
2
_FLIP_SEL[46]
D_HV_1[8 2,84]
DP2_HPD[6,4 6]
_ID[10]
_DP_SEL[46]
_USB_SEL[46]
8D_TBTA_LDO
UPD1_SMBUS_ALERT#
1
1
CT72
2
2
.2U_0402_25V6K
2
+3.3
+3.3
V_ALW
MUX1_
MUX1_
UPD1_
UPD1_
CPU_
CPU_
1 2
RT97 0
126
QT1A
@
DMN66D0LDW-7_SOT363-6
@
RT58
@
RT60 0_0402_5%
X10 +3.3V_VDD_PIC_PDA change connect to +3.3V_ALW
+3.3
V_VDD_PIC
+3.3
V_ALW
MOSI
MISO
2_AUXN_C
2_AUXP_C
+TBT
A_LDO_BMC
+VCC1V
+VCC1V
CT73
.2U_0402_25V6K
2
V_TBTA_FLASH
FLIP_SEL
@
@
@
@
UART_
MOSI
UART_
MISO
RT84 0
RT85 0
USB_SEL
SMBCLK_Q
SMBDAT_Q
DP2_AUXP[6,46]
DP2_AUXN[6,46]
_0402_5%@
8D_TBTA_LDO
8A_TBTA_LDO
+3.3
V_TBTA_FLASH
RT66 3
RT67 3
RT68 1
RT69 0
@
RT70
RT71 1
RT72 0
RT73 0
RT74 0
RT75 0
RT33
9 0_0402_5%@
@
12
_0402_5%@
12
_0402_5%@
Follow TI SPEC
RT86 change to 100K
RT86 1
1 2
RT87 0
1 2
RT88 0
1 2
1 2
RT89
@
RT90
@
1 2
1 2
RT92 0
RT93 0
1 2
CT80 0
1 2
CT81 0
+3.3
V_TBTA_FLASH
@
RT98
_0402_5%
0
1 2
12
RT99
@
_0402_5%
0
UPD1_SMBCLK_Q
UPD1_SMBDAT_Q
+5V_
ALW
+3.3
V_VDD_PIC_P DA
1
CT74
2
12
RT37
8 10K_0402_5%
12
RT37
9 10K_0402_5%
UPD1_
12
.3K_0402_5%@
UPD1_
12
.3K_0402_5%@
UPD1_
12
0K_0402_5%@
MUX1_
_0402_5%
12
EN_PD_
12
0
_0402_5%
PD1_G
12
M_0402_5%
AC1_DI
12
_0402_5%
PCH_DP2
12
_0402_5%
OTG_
12
_0402_5%
PD1_G
12
_0402_5%@
PD1_G
12
PD1_G
TBTA
TBTA
TBTA
TBTA
USB2
0_P1[10]
USB2
0_N1[10]
12
RT83 0
TBTA
TBTA
12
00K_0201_5%
_0402_5%@
_0402_5%@
0
_0402_5%
0
_0402_5%
_0402_5%@
_0402_5%@
.1U_0201_10V6K@
.1U_0201_10V6K@
12
+3.3V_RUN
5
3 4
QT10B
L2N7002DW1T1G_SC88-6
PJP8
1 2
P
AD-OPEN 1x3m
@
RT63 0
1 2
0U_0402_6.3V6M
1
SMBDAT_Q
SMBCLK_Q
SMBUS_ALERT#
FLIP_SEL_R
HV_1_R
PIO2
SC#
_HPD_R
ID
PIO6
PIO7
PIO8
_ROM_CLK_PD
_ROM_DI_PD
_ROM_DO_PD
_ROM_CS#_PD
_0402_5%
_SWD_DATA_R
_SWD_CLK_R
TBTA
_MRESET
TBTA
_LSTX_R
TBTA
_LSRX_R
TBTA
_DEBUG3
TBTA
_DEBUG4
TBTA
_DEBUG1
TBTA
_DEBUG2
CPU_DP
2_AUXP_C
CPU_DP
2_AUXN_C
TBTA
_ROSC
0
RT10
15K_0402_0.1%
2
1
6
QT10A
L2N7002DW1T1G_SC88-6
TI is 1x47uf+1x0.1uf
1
CT75
2
2U_0805_25V6M
2
_0402_5%
UT5
F1
I2C_
ADDR
D1
I2C_
SDA1
D2
I2C_
SCL1
C1
I2C_
IRQ1_N
A5
I2C_
SDA2
B5
I2C_
SCL2
B6
I2C_
IRQ2_N
B2
GPIO
0
C2
GPIO
1
D10
GPIO
2
G11
GPIO
3
C10
GPIO
4
E10
GPIO
5
G10
GPIO
6
D7
GPIO
7
H6
GPIO
8
A3
SPI_
CLK
B4
SPI_
MOSI
A4
SPI_
MISO
B3
SPI_
SS_N
L5
USB_
RP_P
K5
USB_
RP_N
E2
UART
_TX
F2
UART
_RX
F4
SWD_
DATA
G4
SWD_
CLK
E11
MRES
ET
L4
TBT_
LSTX/R2P
K4
TBT_
LSRX/P2R
L3
DIG_
AUD_P/DEBUG3
K3
DIG_
AUD_N/DEBUG4
L2
DEBU
G1
K2
DEBU
G2
J1
AUX_
P
J2
AUX_
N
F10
BUSP
OWER_N
G2
R_OS
C
PS8802_CSCL [4 6]
PS8802_CSDA [46]
1
1
CT76
2
2
2U_0805_25V6M
2
H1
B1
O
3V3
VDDI
VIN_
For Non-AR config
TBTA
0_0402_5%
0_0402_5%
_CC1 [4 5]
TBTA
+3.3
V_TBTA_FLASH
RF requeat
_CC2 [4 5]
DP2_
DP2_
+5V_
ALW_P DA
100P_0402_50V8J~D
@
12
CT22RF
1
2
MIC_SBU1 [4 5,46]
MIC_SBU2 [4 5,46]
1
CT85
CT86
2
20P_0402_50V8J
20P_0402_50V8J
2
2
+20V
1
CT77
CT78
2
2U_0805_25V6M
2U_0805_25V6M
2
2
+5V_
ALW_P DA
1
1
1
1
6
A1
B1
C1
D1
PP1
ABLE
PP_C
5
3
4
2
GND1
GND1
GND1
GND1
E8
B8
D8
0
.22U_0402_16V7K
A
PP2
PP3
PP4
6
7
8
9
0
GND1
GND1
GND1
GND1
GND2
F6
F7
F8
G6
G7
G8
CT87
H10
K1
A2
E1
BMC
1V8A
1V8D
LDO_
LDO_
LDO_
0
1
ET
GND8
GND9
GND1
GND5
HRES
GND6
GND7
GND1
7
5
1
5
6
F
E
A
E
E
D6
H4
H5
G5
12
1
RT10
100K_0402_5%
_TBTA_Vbus_1
1 2
RT64 0
RT65 0
ATE1_A
ATE2_A
HV_G
B10
EP
SENS
4
GND2
SN1
12
@
HV_G
A10
B9
A9
EN
ATE1
ATE2
SENS
HV_G
HV_G
VBUS
1
VBUS
2
VBUS
3
VBUS
4
VOUT
_3V3
LDO_
3V3
C_US
B_TP
C_US
B_TN
C_US
B_BP
C_US
B_BN
C_CC
1
C_CC
2
RPD_
G1
RPD_
G2
DEBU
G_CTL1
DEBU
G_CTL2
C_SB
U1
C_SB
U2
RESE
T_N
804044ZBHR_NFBGA96
3
RT10
0_0402_5%
H11
J10
J11
K11
H2
G1
K6
L6
K7
L7
L9
L10
K9
K10
E4
D5
K8
L8
F11
7
8
7
A
A
B
GND1
GND2
GND3
GND4
2
1
3
GND2
GND2
SSH7GND2
L1
H8
L11
1
2
1 2
+20V
_TBTA_Vbus_1
@
@
TBTA
TBTA
DP2_
DP2_
TBTA
_0402_5%@
_0402_5%@
+3.3
1
U_0402_25V6K
12
CT82
1 2
1 2
RT10
4
RT10
5
_DBG_CTL1
_DBG_CTL2
MIC_SBU1_R
MIC_SBU2_R
_RESET_N_EC_R
V_PDA_VOU T
1
CT83
2
+3.3
V_TBTA_FLASH
1
2
U_0201_6.3V6M
1
TBTA
_TOP_P [45]
TBTA
_TOP_N [4 5]
TBTA
_BOT_P [45]
TBTA
_BOT_N [4 5]
0_0402_5%
0_0402_5%
1 2
RT10
6 10K_0402_5%
1 2
RT10
7 10K_0402_5%
1 2
RT10
8
@
1 2
RT10
9
@
RT11
0 0_0402_5%@
CT84
0U_0402_6.3V6M
1
12
DELL
Secu
Secu
Secu
rity Classification
rity Classification
rity Classification
Issu
Issu
Issu
ed Date
ed Date
ed Date
THIS
THIS
THIS
SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
5
4
3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
2016
2016
2016
/01/01
/01/01
/01/01
Comp
Comp
Comp
2
al Secret Data
al Secret Data
al Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2017/01/01
2017/01/01
2017/01/01
CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Titl
Titl
Titl
e
e
e
[Type C]PD Controller TI
[Type C]PD Controller TI
[Type C]PD Controller TI
Size Document Number R ev
Size Document Number Rev
Size Document Number Rev
C
C
C
LA-G891P
LA-G891P
LA-G891P
Mond
Mond
Mond
ay, February 25, 2019
ay, February 25, 2019
ay, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
1
of
44 102
of
44 102
of
44 102
0.3
0.3
0.3
Page 45
5
4
3
2
1
For NON AR Config
D D
CT630~633 use SD043000080 (0 ohm) for CSLP3 build
+20
V_TBTA_VBUS
JUSB
C1
CONN@
A1
GND
USB
3_DP2_MTX_C_DRX_P1
USB
3_DP2_MTX_C_DRX_N1
12
CT9
9 0.01U_0201_25V6K
I@
RT1
23
RT1
22 0_0402_5%
I@
CT1
01 0.01U_0201_25V6K
TBT
12
12
DP2
12
TBT
TBT
C C
@EM
A_BOT_P[44]
@EM
A_BOT_N[44]
A_CC2[44]
0_0402_5%
_MIC_SBU2[44,46]
TBT
TBT
A_BOT_P_R
TBT
A_BOT_N_R
DP2
USB
3_DP2_MRX_C_DTX_N0
USB
3_DP2_MRX_C_DTX_P0
A_CC2
_MIC_SBU2
_1
A2
SST
XP1
A3
SST
XN1
A4
VBU
S_1
A
5
CC1
A
6
DP1
A
7
DN1
A8
SUB
1
A9
VBU
S_2
A10
SSR
XN2
A11
SSR
XP2
A12
GND
_2
1
GND
_5
2
GND
_6
5
GND
_9
7
NPT
H_1
JAE_DX07SD24JJ2R1300~D
TOP
Bottom
+20
V_TBTA_VBUS
B12
GND
_4
SSR
XP1
SSR
XN1
VBU
S_4
SBU
2
DN2
DP2
CC2
VBU
S_3
SST
XN2
SST
XP2
GND
_3
GND
_8
GND
_7
GND
_10
NPT
H_2
USB
B11
B10
B9
B8
B
7
B
6
B
5
B4
B3
B2
B1
4
3
6
8
3_DP2_MRX_C_DTX_P1
USB
3_DP2_MRX_C_DTX_N1
DP2
_MIC_SBU1
TBT
A_TOP_N_R
TBT
A_TOP_P_R
TBT
A_CC1
USB
3_DP2_MTX_C_DRX_N0
USB
3_DP2_MTX_C_DRX_P0
12
CT1
00 0.01U_0201_25V6K
DP2
_MIC_SBU1 [44,46]
0_0402_5%
0_0402_5%
TBT
A_CC1 [44]
12
CT1
02 0.01U_0201_25V6K
RF Request
+20
V_TBTA_VBUS
RT1
21
@EM
I@
12
12
RT1
TBT
A_TOP_N [44]
@EM
I@
20
TBT
A_TOP_P [44]
12P_0402_50V8J
RF@
82P_0402_50V8J
RF@
1
1
CT1
CT1
2
2
89
90
+20
V_TBTA_VBUS
3
2
DT4
L
30ESD24VC3-2_SOT23-3
1
ESD@
Link DX07SD24JJ2R1300 done 0123
Place holder for future VBUS-short
USB
USB
3_DP2_MRX_DTX_P0[46]
USB
3_DP2_MRX_DTX_N0[46]
USB
3_DP2_MTX_DRX_P0[46]
USB
3_DP2_MTX_DRX_N0[46]
USB
3_DP2_MRX_DTX_P1[46]
USB
3_DP2_MRX_DTX_N1[46]
USB
3_DP2_MTX_DRX_P1[46]
USB
3_DP2_MTX_DRX_N1[46]
B B
USB
3_DP2_MTX_C_DRX_P1
USB
3_DP2_MTX_C_DRX_N1
USB
3_DP2_MTX_C_DRX_P0
USB
3_DP2_MTX_C_DRX_N0
3_DP2_MRX_DTX_P0
USB
3_DP2_MRX_DTX_N0
USB
3_DP2_MTX_DRX_P0
USB
3_DP2_MTX_DRX_N0
USB
3_DP2_MRX_DTX_P1
USB
3_DP2_MRX_DTX_N1
USB
3_DP2_MTX_DRX_P1
USB
3_DP2_MTX_DRX_N1
1 2
RT4
91 221K _0201_1%
1 2
RT4
90 221K _0201_1%
1 2
RT4
88 221K _0201_1%
1 2
RT4
89 221K _0201_1%
fix (reduce current surge)
1 2
RT1
90 2.2_0201_1%
1 2
RT1
91 2.2_0201_1%
1 2
RT1
92 2.2_0201_1%
1 2
RT1
93 2.2_0201_1%
1 2
RT1
94 2.2_0201_1%
1 2
RT1
95 2.2_0201_1%
1 2
RT1
96 2.2_0201_1%
1 2
RT1
97 2.2_0201_1%
Discharge SSTX/SSRX resistors - must be
placed if 330nF cap is being used.
USB
3_DP2_MRX_C_DTX_P1
USB
3_DP2_MRX_C_DTX_N1
USB
3_DP2_MRX_C_DTX_P0
USB
3_DP2_MRX_C_DTX_N0
AC coupling is recommended for
VBUS-short protection on SSRX lines. If not
needed, place 0 Ohm resistor instead.
USB
3_DP2_MRX_R_DTX_P0
USB
3_DP2_MRX_R_DTX_N0
USB
3_DP2_MTX_R_DRX_P0
USB
3_DP2_MTX_R_DRX_N0
USB
3_DP2_MRX_R_DTX_P1
USB
3_DP2_MRX_R_DTX_N1
USB
3_DP2_MTX_R_DRX_P1
USB
3_DP2_MTX_R_DRX_N1
1 2
RT2
21 221K_0201_ 1%
1 2
RT2
22 221K_0201_ 1%
1 2
RT2
19 221K_0201_ 1%
1 2
RT2
20 221K_0201_ 1%
1 2
CT3
26 0.33U_0201_25V6K
1 2
CT3
27 0.33U_0201_25V6K
1 2
CT6
34 0.22U_0201_25V6K
1 2
CT6
35 0.22U_0201_25V6K
1 2
CT3
28 0.33U_0201_25V6K
1 2
CT3
29 0.33U_0201_25V6K
1 2
CT6
36 0.22U_0201_25V6K
1 2
CT6
37 0.22U_0201_25V6K
USB
3_DP2_MRX_C_DTX_P0
USB
3_DP2_MRX_C_DTX_N0
USB
3_DP2_MTX_C_DRX_P0
USB
3_DP2_MTX_C_DRX_N0
USB
3_DP2_MRX_C_DTX_P1
USB
3_DP2_MRX_C_DTX_N1
USB
3_DP2_MTX_C_DRX_P1
USB
3_DP2_MTX_C_DRX_N1
USB
3_DP2_MTX_R_DRX_P0
USB
3_DP2_MTX_R_DRX_N0
USB
3_DP2_MRX_R_DTX_P1
USB
3_DP2_MRX_R_DTX_N1
DT5
ESD@
1 2
DE
SD3V3Z1BCSF-7 X2-DSN0603-2
DT6
ESD@
1 2
DE
SD3V3Z1BCSF-7 X2-DSN0603-2
DT9
ESD@
1 2
DE
SD3V3Z1BCSF-7 X2-DSN0603-2
DT1
0
ESD@
1 2
DESD3V3Z1BCSF-7 X2-DSN0603-2
USB
3_DP2_MRX_R_DTX_P0
USB
3_DP2_MRX_R_DTX_N0
USB
3_DP2_MTX_R_DRX_P1
USB
3_DP2_MTX_R_DRX_N1
DT1
3
ESD@
1 2
DESD3V3Z1BCSF-7 X2-DSN0603-2
DT1
4
ESD@
1 2
DESD3V3Z1BCSF-7 X2-DSN0603-2
DT1
7
ESD@
1 2
DESD3V3Z1BCSF-7 X2-DSN0603-2
DT1
8
ESD@
1 2
DESD3V3Z1BCSF-7 X2-DSN0603-2
change typeC ESD part from SC40000AR00 to SC40000DF00
ESD@
DT3
DP2
_MIC_SBU2
DP2
A A
5
TBT
TBT
_MIC_SBU1
A_TOP_P_R
A_TOP_N_R
9
1
2
4
5
3
AZ1045-04F_DFN2510P10E-10-9
9
1
10
8
2
9
7
7
4
6
6
5
3
8
DP2
DP2
TBT
TBT
_MIC_SBU2
_MIC_SBU1
A_TOP_P_R
A_TOP_N_R
TBT
TBT
TBT
TBT
4
A_BOT_P_R
A_BOT_N_R
A_CC1
A_CC2
AZ1045-04F_DFN2510P10E-10-9
ESD@
DT4
0
TBT
1
1
2
2
4
4
5
5
3
3
8
A_BOT_P_R
9
10
TBT
A_BOT_N_R
8
9
TBT
A_CC1
7
7
TBT
A_CC2
6
6
DEL
Sec
Sec
Sec
urity Classification
urity Classification
urity Classification
Iss
Iss
Iss
ued Date
ued Date
ued Date
THIS
THIS
THIS
SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL
SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL
SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
201
201
201
6/01/01
6/01/01
6/01/01
Com
Com
Com
2
pal Secret Data
pal Secret Data
pal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2017/01/01
2017/01/01
2017/01/01
L CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Tit
Tit
Title
le
le
USB 3.0 CONN TYPE C
USB 3.0 CONN TYPE C
USB 3.0 CONN TYPE C
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
LA-G891P
LA-G891P
LA-G891P
Mon
Mon
Mon
day, February 25, 2019
day, February 25, 2019
day, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
1
of
45 10
of
45 10
of
45 10
0.3
0.3
0.3
2
2
2
Page 46
5
4
3
2
1
+3.3V_RUN_UT9 +3.3V_CPS
4
.7U_0402_6.3V6M
CT44
1
2
4
.7U_0402_6.3V6M
CT626
+1.2
USB3
_PRX_C_MTX_N1
USB3
_PRX_C_MTX_P1
USB3
_PTX_C_MRX_N1
USB3
_PTX_C_MRX_P1
CPU_
CPU_
CPU_
CPU_
CPU_
CPU_
CPU_
CPU_
CPU_
DP2_AUXP_C_MUX
CPU_
DP2_AUXN_C_MUX
+1.2V_VDD_R1+1.2V_RUN
0.
1U_0402_25V6
CT48
1
2
0.
1U_0402_25V6
CT45
1
2
V_VDD_DM_D1
DP2_P0_C
DP2_N0_C
DP2_P1_C
DP2_N1_C
DP2_P2_C
DP2_N2_C
DP2_P3_C
DP2_N3_C
0.
01UF_0402_25V7K
1
2
+1.2
CT46
1
2
V_VDD_A2
0.
01UF_0402_25V7K
1
10
16
38
6
7
13
47
30
11
12
14
15
1
7
1
8
2
0
2
1
2
3
2
4
2
5
2
6
3
1
3
2
50
51
1
2
UT9
VDD_
VDD_
VDD_
VDD_
VDD_
VDD_
VDD_
VDD_
VDD_
SSRX
SSRX
SSTX
SSTX
ML0p
ML0n
ML1p
ML1n
ML2p
ML2n
ML3p
ML3n
AUXp
AUXn
DCI_
DCI_
PS88
1
10
16
38
R1
R2
A1
A2
D1
n
p
n
p
CLK
DATA
02QFN52GTRA1_QFN52_6P5X4P5
change from SA0000AIM10(A1) to SA0000AIM20(A2)
1 2
LT11 BLM18KG331SN1D_2P
D D
+3.3V_RUN +3.3V_RUN_UT9
+1.2
1 2
RT39
+3.3
7 0_0603_5%@
RT39
8
@
V_RUN_UT9
4
.7K_0402_5%
@
RT135
1 2
4
@
12
.7K_0402_5%
RT136
1 2
4
.7K_0402_5%
@
RT137
1 2
4
@
12
.7K_0402_5%
RT138
0_0603_5%
4
.7K_0402_5%
@
RT139
1 2
@
4
12
.7K_0402_5%
RT140
4.7K_0402_5%
@
RT141
1 2
PS88
02_ADDR
PS88
02_DPEQ
PS88
02_CEQ
PS88
02_SSEQ
4.7K_0402_5%
@
12
RT142
+3.3
V_ALW
C C
B B
ADDR: I2C control bus address. Internally pull down at 150k, 3.3V I/O
L: Slave address 0x10-0x2F(default)
H: Slave address 0x30-0x4F
DPEQ:DP Receiver equalization setting; Internally pull down at 150k, 3.3V I/O
L: Compensation for channel loss up to 12dB(Default)
H: Compensation for channel loss up to 18dB
CEQ: USB Type-C connector facing Rx channel receiver equalization setting;
Internally pull down at 150k, 3.3V I/O.
L: Compensation for channel loss up to 16dB(Default)
H: Compensation for channel loss up to 18dB
SSEQ: USB Host facing Rx channel receiver equalization setting;
Internally pull down at 150k, 3.3V I/O.
L: Compensation for channel loss up to 12dB(Default)
H: Compensation for channel loss up to 18dB
A A
V_RUN
LT60
1
1 2
BLM18KG331SN1D_2P
0
4
.1U_0201_10V6K
.7U_0402_6.3V6M
CT118
1
12
CT117
2
+1.2
V_VDD_R2
0
0.
.01UF_0402_25V7K
1U_0402_25V6
4
.7U_0402_6.3V6M
CT610
1
CT47
1
1
CT629
2
USB3
USB3
USB3
USB3
_PRX_MTX_N1[10]
_PRX_MTX_P1[10]
CPU_
CPU_
2
2
CT11
_PTX_MRX_N1[10]
_PTX_MRX_P1[10]
CPU_
CPU_
CPU_
CPU_
CPU_
CPU_
CPU_
CPU_
DP2_AUXP[6,44]
DP2_AUXN[6,44]
CT11
CT11
CT11
DP2_P0[6]
CT10
DP2_N0[6]
CT10
DP2_P1[6]
CT10
DP2_N1[6]
CT10
DP2_P2[6]
CT10
DP2_N2[6]
CT10
DP2_P3[6]
CT10
DP2_N3[6]
CT11
CT11
5 0.1U_0402_25V6
CT11
6 0.1U_0402_25V6
LT602
1 2
BLM18KG331SN1D_2P
+1.2
V_RUN
LT60
3
1 2
BLM18KG331SN1D_2P
+1.2
V_VDD_R1
+1.2
V_VDD_R2
+1.2
V_VDD_A1
+1.2
V_VDD_A2
+1.2
V_VDD_DM_D1
1 2
1 2
1 0.22U_0402_10V6K
2 0.22U_0402_10V6K
1 2
1 2
3 0.22U_0402_10V6K
4 0.22U_0402_10V6K
1 2
1 2
3 0.22U_0402_10V6K
4 0.22U_0402_10V6K
1 2
1 2
5 0.22U_0402_10V6K
6 0.22U_0402_10V6K
1 2
1 2
7 0.22U_0402_10V6K
8 0.22U_0402_10V6K
1 2
1 2
9 0.22U_0402_10V6K
0 0.22U_0402_10V6K
1 2
1 2
CT625
+1.2V_RUN
+1.2
V_RUN
1 2
BLM18KG331SN1D_2P
LT605
1 2
BLM18KG331SN1D_2P
CT628
LT60
4
4
.7U_0402_6.3V6M
CT611
1
CT627
2
VDD3
VDD3
4
.7U_0402_6.3V6M
0
.1U_0402_25V6
VDD_
RESE
CE_U
CE_D
IN_H
1
2
3_27
3_52
ADDR
DPEQ
SBU1
SBU2
RX1p
RX1n
RX2n
RX2p
TX1p
TX1n
TX2n
TX2p
CSCL
CSDA
REXT
TEST
SSEQ
CEQ
ePAD
CT617
1
2
V_VDD_A1
1
2
27
52
49
1
9
2
2
43
3
3
3
4
2
3
8
9
4
1
4
2
4
4
4
5
2
8
2
9
35
36
3
7
40
3
9
4
5
4
6
48
5
3
0
.1U_0402_25V6
PS88
PS88
1
2
02_SBU1_R
02_SBU2_R
MUX1
MUX1
MUX1
PS88
0_0402_5%
PS88
0
.1U_0402_25V6
CT614
+3.3
_DP_SEL
_USB_SEL
_FLIP_SEL
02_HPD
02_REXT
0
.1U_0402_25V6
CT618
+1.2
0
.01UF_0402_25V7K
CT612
1
2
DCI
T#
P
SB
FLIP
PD
RSV
V_CPS
PS88
PS88
PS88
PS88
PS88
1
2
CT615
+3.3
02_SSEQ
02_CEQ
0
.01UF_0402_25V7K
V_VDD_DCI
02_ADDR
02_DPEQ
02_RST#
+1.2V_VDD_DM_D1
0
.01UF_0402_25V7K
CT616
1
1
2
2
+3.3
V_RUN_UT9
RT30
1 2
0_0402_5%
1 2
RT13
2@ 0_0402_5%
1 2
RT13
3@ 0_0402_5%
PS88
02_CSCL [44]
PS88
02_CSDA [44]
MUX1
_DP_SEL [44]
MUX1
_USB_SEL [44]
MUX1
_FLIP_SEL [44]
12
@
RT38
0
+3.3
V_VDD_DCI
3@
1
U_0201_6.3V6M
CT119
1
2
USB3
_DP2_MRX_DTX_P0 [45]
USB3
_DP2_MRX_DTX_N0 [45]
USB3
_DP2_MRX_DTX_N1 [45]
USB3
_DP2_MRX_DTX_P1 [45]
USB3
_DP2_MTX_DRX_P0 [45]
USB3
_DP2_MTX_DRX_N0 [45]
USB3
_DP2_MTX_DRX_N1 [45]
USB3
_DP2_MTX_DRX_P1 [45]
CPU_
4
.99K_0402_1%
12
RT300
DP2_
MIC_SBU1 [44,45]
DP2_
MIC_SBU2 [44,45]
DP2_HPD [6,44]
MUX1
_USB_SEL
PS88
02_CSCL
PS88
02_CSDA
CPU_
DP2_AUXN_C_MUX
CPU_
DP2_AUXP_C_MUX
PS88
PS88
02_SBU1_R
02_SBU2_R
1 2
RT30
8 4.7K_0402_5%
1 2
RT30
5 4.7K_0402_5%
1 2
RT30
4 4.7K_0402_5%
1 2
RT13
1 100K_0402_5%
1 2
RT13
0 100K_0402_5%
1 2
RT41
4 2M_0402_5%
1 2
RT41
5 2M_0402_5%
+3.3V_RUN_UT9
PS8802_RST#
12
1
2
+3.3
V_RUN_UT9
10K_0402_5%
RT246
CT12
2
1U_0201_6.3V6M
DELL
Secu
Secu
Secu
rity Classification
rity Classification
rity Classification
Issu
Issu
Issu
ed Date
ed Date
ed Date
THIS
THIS
THIS
SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2016
2016
2016
/01/01
/01/01
/01/01
Comp
Comp
Comp
al Secret Data
al Secret Data
al Secret Data
Deci
Deci
Deci
phered Date
phered Date
phered Date
2017/01/01
2017/01/01
2017/01/01
2
CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Titl
Titl
Title
e
e
DP/USB3 Re-timer PS8802
DP/USB3 Re-timer PS8802
DP/USB3 Re-timer PS8802
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
LA-G891P
LA-G891P
LA-G891P
Mond
Mond
Mond
ay, February 25, 2019
ay, February 25, 2019
ay, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
1
of
46 102
of
46 102
of
46 102
0.3
0.3
0.3
Page 47
5
D D
C C
4
3
2
1
Reserve
B B
A A
DEL
L CONFIDENTIAL/PROPRIETARY
Com
Com
pal Electronics, Inc.
Tit
Tit
Tit
le
le
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronics, Inc.
TYPE-C
TYPE-C
LA-
LA-
G891P
G891P
1
47 10
47 10
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
of
of
of
Page 48
5
D D
C C
4
3
2
1
Reserve
B B
A A
DELL
CONFIDENTIAL/PROPRIETARY
Comp
Comp
al Electronics, Inc.
Titl
Titl
Titl
e
e
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
e
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
TYPE-C
TYPE-C
LA-G
LA-G
891P
891P
1
0.3
48 102M
48 102M
of
of
of
0.3
Page 49
5
D D
C C
4
3
2
1
Reserve
B B
A A
DEL
L CONFIDENTIAL/PROPRIETARY
Com
Com
pal Electronics, Inc.
Tit
Tit
Tit
le
le
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronics, Inc.
TYPE-C
TYPE-C
LA-
LA-
G891P
G891P
1
49 10
49 10
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
of
of
of
Page 50
5
+5V_ALW
DT1
@
+5V_TBT_VBUS
D D
C C
1N4148WS-7-F_SOD323-2
1N4148WS-7-F_SOD323-2
1 2
1N
4148WS-7-F_SOD323-2
1U
@
_0201_10V6M
1
@
CT93
2
DT3
DT2
@
+5V_
TBTA_VBUS_D
12
12
+5V_PD_VDD
100K_0402_5%
12
@
RT393
@
UT8
VCC
3
VOUT
GND
AP
2204R-5.0TRG1_SOT89-3
1U
0.
1U_0201_10V6K
_0201_10V6M
1
1
@
@
CT89
CT88
2
2
1
2
1 2
@
RT111 100K_0402_5%
+20V_TBTA_Vbus_1
1U
_0402_25V6K
1
@
CT94
2
4
@
UT7
VCC1VOUT
2
GND
EN3ADJ/NC
AP2112K-3.3TRG1_SOT23-5
1
@
CT90
1U_0201_10V6M
2
3
+3.3V_TBTA_FLASH +3.3V_VDD_PIC
1 2
RT399 0_0402_5%
5
4
+3.3V_VDD_PIC_R
1 2
RT420 0_0402_5%@
0.
2.
1U_0402_25V6K
2U_0402_10V6M
1
12
@
@
CT92
CT91
2
2
1
place near UT7
B B
A A
DELL
Secu
Secu
Secu
rity Classification
rity Classification
rity Classification
Issu
Issu
Issu
ed Date
ed Date
ed Date
THIS
THIS
THIS
SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2017
2017
2017
/01/01
/01/01
/01/01
Comp
Comp
Comp
al Secret Data
al Secret Data
al Secret Data
Deci
Deci
Deci
phered Date
phered Date
phered Date
2018/01/01
2018/01/01
2018/01/01
2
CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Titl
Titl
Title
e
e
[Type C]PD Power
[Type C]PD Power
[Type C]PD Power
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
LA-G891P
LA-G891P
LA-G891P
Mond
Mond
Mond
ay, February 25, 2019
ay, February 25, 2019
ay, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
1
of
50 102
of
50 102
of
50 102
0.3
0.3
0.3
Page 51
5
+3.3V_LAN
RL1@ 10K_0402_5%
RL2@ 10K_0402_5%
RL4 4.7K_0402_5%@
D D
PM_LANPHY_ENABLE[11]
+0.
9V_LAN
0
22U_0603_6.3V6M
.1U_0201_10V6K
1
12
CL1
2
2
Note:
+1.0V_LAN will work at 0.95V to 1.15V
C C
LOM_
LOM
+3.
3V_LAN
12
RL2
B B
For WLAN can't recognize during enable
Unobtrusive mode(BITS152312)
A A
1M_0402_5%
LOM_
TP_LAN_JTAG_TMS
12
TP_LAN_JTAG_TCK
12
CLKREQ_PCIE#3
12
1 2
0
0.1U_0201_10V6K
0.1U_0201_10V6K
CL9
1
2
CONNLED_GRN#
_ACTLED_YEL#
9
CONNLED_GRN#
.1U_0201_10V6K
CL8
CL1
CL1
1
1
1
0
2
2
When LAN & WLAN are exist at the same time, WLAN will disable
@
RL2
0 0_0402_5%
L2N7002DW 1T1G_SC88-6
1
L2N7002DW 1T1G_SC88-6
@
RL70_0402_5%
12
12
QL1
A
LAN
_ACTLED_YEL#
6
2
LED
_MASK#
QL1
B
LED
34
5
LED
_MASK#
CLKREQ_PCIE#3[11]
PCIE_PRX_DTX_P9[10]
+3.3V_LAN
1
0K_0402_5%
1 2
1
0K_0402_5%
12
XTA
LO_R
2
5MHZ_20PF_XRCGB25M000F2P18R0
27P_0402_50V8J
CL1
3
LED
_GRN#
PCIE_PRX_DTX_N9[10]
PCIE_PTX_DRX_P9[10]
PCIE_PTX_DRX_N9[10]
RL5 @
SMBus Device Address 0xC8
RL9@
1 2
0_0402_5%
YL1
3
3
NC1
NC2
2
4
Can change to small package
LOM_
CABLE_DETECT# [58]
_MASK# [58,64]
PLTRST_LAN#[11]
CLK_PCIE_P3[11]
CLK_PCIE_N3[11]
SML0_SMBCLK[8]
SML0_SMBDATA[8]
LAN_WAKE#[11,58]
T315 PAD~D@
T88
T89
RL3
4
@
12
1
1
12
4
CLKREQ_PCIE#3
PCIE_PRX_C_DTX_P9
1 2
CL1 0.1U_0402_25V6
PCIE_PRX_C_DTX_N9
1 2
CL2 0.1U_0402_25V6
PCIE_PTX_C_DRX_P9
1 2
CL5 0.1U_0402_25V6
PCIE_PTX_C_DRX_N9
1 2
CL6 0.1U_0402_25V6
1
1
PAD~D@
1
PAD~D@
RL1
1
1M_0402_5%
27P_0402_50V8J
CL1
4
12
0.1U_0201_10V6K
12
CL1
6
0.1U_0201_10V6K
12
CL2
0
LAN_DISABLE#_R
LOM_ACTLED_YEL#
LOM_CONNLED_GRN#
LOM_LED2
TP_
LAN_JTAG_TDI
TP_
LAN_JTAG_TDO
TP_
LAN_JTAG_TMS
TP_
LAN_JTAG_TCK
XTA
XTA
LAN
_TEST_EN
RES
3.01K_0402_1%
1K_0402_5%
12
RL1
RL1
3
2
LAN
LAN
0.1U_0201_10V6K
LAN
12
CL1
7
LAN
LAN
LAN
0.1U_0201_10V6K
LAN
12
CL2
1
LAN
UL1
48
CLK_REQ_N
36
PE_RST_N
44
PE_CLKP
45
PE_CLKN
38
PETp
39
PETn
41
PERp
42
PERn
28
SMB_CLK
31
SMB_DATA
2
LANWAKE_N
3
LAN_DISABLE_N
26
LED0
27
LED1
25
LED2
32
JTA
G_TDI
34
JTA
G_TDO
33
JTA
G_TMS
35
JTA
G_TCK
9
LO
XTA
10
LI
XTA
30
TES
_BIAS
12
RBI
AS
NEED TO LINK
SA000081G1L--->SA000081G3L
_MDIP0_L
1
_MDIN0_L
2
3
4
_MDIP1_L
5
_MDIN1_L
6
_MDIP2_L
7
_MDIN2_L
8
9
10
_MDIP3_L
11
_MDIN3_L
12
E
MDI
PCI
US
RSVD1_VCC3P3
SMB
LED
G
JTA
L_OUT
L_IN
T_EN
WGI219LM-SLKJ3-A0_QFN48_6X6~D
TL1
TD1
+
TD1
-
TDC
T1
TDC
T2
TD2
+
TD2
-
TD3
+
TD3
-
TDC
T3
TDC
T4
TD4
+
TD4
-
M
HPC_NS692417
GND
GND
C
HASSIS
CHASSIS
3
VPRO@
13
MDI_PLUS0
14
MDI_MINUS0
17
MDI_PLUS1
18
MDI_MINUS1
20
MDI_PLUS2
21
MDI_MINUS2
23
MDI_PLUS3
24
MDI_MINUS3
6
SVR_EN_N
1
5
VDD3P3_IN
4
VDD3P3_4
15
VDD3P3_15
19
VDD3P3_19
29
VDD3P3_29
47
VDD
0P9_47
46
VDD
0P9_46
37
VDD
0P9_37
43
VDD
0P9_43
11
VDD
0P9_11
40
VDD
0P9_40
22
VDD
0P9_22
16
VDD
0P9_16
8
VDD
0P9_8
7
CTR
L0P9
.7UH +-20% MPB201210T-4R7M-NA2
49
VSS
_EPAD
Place CL3, CL4 and LL1 close to UL1
1:1
1:1
1:1
1:1
1 2
EMI
@
CL2
2 10P_1808_3KV8J
LAN_MDIP0
LAN_MDIN0
LAN_MDIP1
LAN_MDIN1
LAN_MDIP2
LAN_MDIN2
LAN_MDIP3
LAN_MDIN3
VCT_LAN_R1
+RSVD_VCC3P3_1
+3.3V_LAN_OUT
+0.9V_LAN
+RE
GCTL_PNP10
Layout Notice : Place bead as
close UL4 as possible
1 2
RL71 2.2_0603_5%
1 2
RL72 2.2_0603_5%
1 2
RL73 2.2_0603_5%
1 2
RL74 2.2_0603_5%
1 2
RL75 2.2_0603_5%
1 2
RL76 2.2_0603_5%
1 2
RL77 2.2_0603_5%
1 2
RL78 2.2_0603_5%
1 2
RL30_0402_5%
0
.1U_0201_10V6K
12
CL7
1 2
Idc_min=500mA
DCR=100mohm
TXC
TXC
TXC
TXC
LL14
RJ45
_MDIP0
24
TX1
+
RJ45
_MDIN0
23
TX1
-
22
T1
21
T2
RJ45
_MDIP1
20
TX2
+
RJ45
_MDIN1
19
TX2
-
RJ45
_MDIP2
18
TX3
+
RJ45
_MDIN2
17
TX3
-
16
T3
15
T4
RJ45
_MDIP3
14
TX4
+
RJ45
_MDIN3
13
TX4
-
+GN
D_CHASSIS
use 40mil trace if necessary
@
1 2
22U_0603_6.3V6M
0_0603_5%
1
CL2
Place CL28 close to UL1.5
8
2
+0.
9V_LAN
0
.1U_0201_10V6K
CL3
1
12
2
Z28
Z28
07
Z28
06
Z28
08
1
0U_0603_10V6M
@
05
1 2
CL4
12
5 75_0402_1%
RL1
2
LAN_MDIP0_L
LAN_MDIN0_L
LAN_MDIP1_L
LAN_MDIN1_L
LAN_MDIP2_L
LAN_MDIN2_L
LAN_MDIP3_L
LAN_MDIN3_L
RL64.7K_0402_5%
12
12
12
6 75_0402_1%
8 75_0402_1%
7 75_0402_1%
RL1
RL1
RL1
+3.3V_LAN
+3.3V_LAN
@
RL8
RF Request
+3.
3V_LAN_OUT
RF@
RF@
100P_0402_50V8J
100P_0402_50V8J
1
LAN
_ACTLED_YEL#
LED
_GRN#
1
CL2
2
2
9
RL1
4 150_0402_5%
RJ45
_MDIN3
RJ45
_MDIP3
RJ45
_MDIN1
RJ45
_MDIN2
RJ45
_MDIP2
RJ45
_MDIP1
RJ45
_MDIN0
RJ45
_MDIP0
1 2
RL1
9 150_0402_5%
CL3
0
1 2
12
LAN
LED
470P_0402_50V7K
0.1U_0201_10V6K
1
CL1
8
2
_ACTLED_YEL_R#
_GRN_R#
+3.
3V_LAN
CL1
9
1
JLO
M1
A2
Yel
low LED-
A1
Yel
low LED+
8
PR4
-
7
PR4
+
6
PR2
-
5
PR3
-
4
PR3
+
3
PR2
+
2
PR1
-
1
PR1
+
B2
Gre
en LED-
B1
Gre
en LED+
SINGA_2RJ3081-1C8211F
GND
GND
GND
GND
12
4
11
3
10
2
9
1
DEL
L CONFIDENTIAL/PROPRIETARY
Com
Com
Com
pal Electronics, Inc.
pal Electronics, Inc.
Tit
Tit
Tit
le
le
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronics, Inc.
LAN
LAN
LAN
Clarkvillie & RJ45
Clarkvillie & RJ45
Clarkvillie & RJ45
LA-
LA-
LA-
G891P
G891P
G891P
1
51 10
51 10
51 10
of
of
of
0.3
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
2Monday, February 25, 2019
Page 52
5
NGFF slot B Key B
W_DISABLE#
GPIO_9/DAS/DSS#
GP1O_7
GPIO_10
UIM-DATA
GNSS_SCL
GNSS_SDA
PERST#
CLKREQ#
PEWAKE#
SIM DETECT
SUSCLK
GND_
GND_
WWAN
_GPIO_PERST#[8]
GND1
GND2
GND3
GND4
GND5
GND6
GND7
NPTH
1
NPTH
2
+3.3V_WWAN
2
3.3V_2
4
3.3V_4
WWAN_ FULL_PW R_EN
6
WWAN_RADIO_DIS #_R
8
SLOT2_ SATA_L ED#
GPIO_5
GPIO_6
GPIO_8
GPIO_2
GPIO_3
GPIO_4
NC_48
NC_50
COEX3
COEX2
COEX1
3.3V
_62
3.3V
_64
3.3V
_66
@
RZ13
RZ14
10K_04 02_5%
3
4
5
6
7
8
9
10
11
68
69
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
69
94 0_0 402_5%
05
STATE #
RN101 0_0402 _5%@
GPS_DI SABLE# _R
UIM_RESET
UIM_CLK
UIM_DATA
ISH_I2C 2_SCL_ R
ISH_I2C 2_SDA_ R
WWAN_ PERST#
WWAN_ PEWAK E#
RZ1400 100K_0402 _5%
WWAN_COEX3
WWAN_COEX2
WWAN_COEX1
SIM_DET
12
PCIE
_WAKE #[52,59,68]
WWAN
_GPIO_ WAKE# _R
12
12
PCH_
WWAN
_GPIO_ PERST# _R
12
0_0402 _5%
RZ14
02
@
CONFIG_0 CONFIG_2 CONFIG_3 Module Type
GND
GND
14
HIGH
15
HIGH HIGH
JNGFF2
NGFF_CONFIG_3[58]
CLK_PC IE_N0[11]
CLK_PC IE_P0[11 ]
WWAN_BB_RST#[8]
NGFF
_CONFIG_1[58]
WWAN
_WAKE #[5 8]
2
1
2U_0402_6.3V6M
U_0201_6.3V6M
CZ18
CZ17
12
@ESD@
DZ13
DATA
1
CLK
2
21 9
RESET
4
4
DET
5
5
3
3
8
A
Z1045-0 4F_DFN2 510P10 E-10-9
NGFF_CONFIG_0[58]
RZ1476
@
RZ1477
@
CZ10 0.1U_0 402_25 V6
CZ11 0.1U_0 402_25 V6
NGFF
_CONFIG_2[58]
+3.3
V_ALW
12
1
0
00U_B2_6.3VM_R35M
.1U_0402_25V6
1
CZ19
1
+
2
2
10
7
6
D D
PCIE_PRX_DTX_P1 2[10]
PCIE_PRX_DTX_N12[10]
PCIE_PTX_DRX_N12[10]
PCIE_PTX_DRX_P1 2[10]
C C
+3.3
V_WWAN
1
2
DW5821e SPEC Request
UIM_
UIM_
UIM_
SIM_
B B
RF Request
UIM_
CLK
4
7P_0402_50V8J
@RF@
12
CZ38
@RF@
51_0402_5%
12
RZ33
4
12
12
1 2
1 2
RZ1393
@
RZ13
3
100K_0 402_5%
1 3
D
S
TR BSS1 38W 1N S OT-323-3
+3.3
V_WWAN
CZ20
12
UIM_
DATA
9
UIM_
CLK
8
UIM_
RESET
7
SIM_
DET
6
UIM_
DATA
USB20_P 7_L
USB20_N7 _L
WWAN_ WAKE# _D
RZ326 0_04 02_5%@R F@
USB3_PR X_L_DT X_N2
USB3_PR X_L_DT X_P2
USB3_PT X_L_DR X_N2
USB3_PTX_L_DRX_P2
PCIE_P RX_C_D TX_P12
PCIE_P RX_C_D TX_N12
0_0402 _5%
0_0402 _5%
PCIE_PTX_C_DRX_ N12
PCIE_PTX_C_DRX_ P12
WWAN_ BB_RST #_R WWAN_ ANT_CONF IG
12
0_0402 _5%
+1.8
V_PRIM
12
RZ13
10K_04 02_5%
2
G
S
QC8
WWANRF@
WWANRF@
8
1
.2P_0402_50V8D
00P_0402_50V8J
CZ23
CZ21
12
+SIM
+SIM
_PWR
@RF@
15K_0402_5%
12
RZ33
5
3
3P_0402_50V8J
@RF@
12
CZ39
1
3
7
9
11
13
1.8V
15
17
12
19
25
31
33
35
37
39
41
43
45
47
49
51
53
55
57
1.8V
59
61
63
65
67
70
71
2
@
WWAN
_WAKE #_D
WWANRF@
WWANRF@
WWANRF@
1
100P_0402_50V8J
100P_0402_50V8J
8P_0402_50V8J
CZ24
CZ25
CZ26
1
1
12
2
2
SIM
Card Push-Push
UIM_
DATA
_PWR
UIM_
CLK
UIM_
RESET
4
.7U_0402_6.3V6M
12
CZ37
SIM_
DET
UIM_
RESET
12
CONFIG_3
GND_3
GND_55FULL_CARD_POWER_OFF#
USB_D+
USB_DÂGND_11
CONFIG_0
GPIO_11
GPIO_12
GND_19
PERN1/USB3.0-RX-/SSIC-RXN21UIM-RESET
PERP1/USB3.0-RX+/SSIC-RXP23UIM-CLK
GND_25
PETN1/USB3.0-TX-/SSIC-TXN27UIM-PWR
PETP1/USB3.0-TX+/SSIC-TXP29DEVSLP
GND_31
PERN0/SATA-B+
PERP0/SATA-BÂGND_37
PETN0/SATA-AÂPETP0/SATA-A+
GND_43
REFCLKN
REFCLKP
GND_49
ANTCTL0
ANTCTL1
ANTCTL2
ANTCTL3
RESET#
CONF
IG1/PEDET_OC-PCIE/GND-SATA
GND_
63
GND_
65
CONF
IG2/USB3.0IND/GND-OTHER
GND_
70
GND_
71
BELLW _80149 -3221
CONN@
WWAN
_GPIO_ WAKE#[12]
JSIM1 CONN@
C
8
RFU1
C7
IO
C6
VPP
C5
GND
C
4
RFU2
C3
CLK
C2
RST
C1
VCC
1
DLSW
2
DTSW
JAE_
SF51S0 06V4DR 1000Q
Link SF51S006V4DR1000Q done
+SIM
_PWR
3
3P_0402_50V8J
WWANRF@
@RF@
0
.1U_0402_25V6
1
CZ40
CZ41
2
4
+3.3V_WWAN
WWAN_ FULL_PW R_EN
12
10K_04 02_5%
M3042_DEVSLP [10]
ISH_I2C2_SCL [9]
ISH_I2C2_SDA [9]
+3.3V_WWAN
WLAN_C OEX3
WLAN_C OEX2
WLAN_C OEX1
CNV_COE X1
CNV_
CNV_
+3.3
V_ALW_PCH
0.1U
_0201_10V6K
1
CZ21
2
6
5
WWAN
_PEWA KE#_R
4
B2
VCC
YC2B
GNDB1C
12
12
RB
RB
100P_0402_50V8J
WWANRF@
12
CZ19
8
CNV_
COEX2
CNV_
COEX3
CNV_
6
WWAN
_GPIO_ CTRL#
0_0402 _5%
0.1U
_0201_10V6K
1
CZ21
7
2
WWAN
_PERST #_R
0_0402 _5%
1 2
DZ5
751S40 T1G_SO D523-2
1 2
DZ6
751S40 T1G_SO D523-2
COEX1 [6]
COEX2 [6]
COEX3 [6]
1 2
WWAN
1 2
WWAN
_PEWA KE#
@
RZ13
95
_GPIO_CTRL[58]
RZ13
@
98
1 2
RZ14
WWAN
_PERST #
@
RZ14
01
WWAN
_RADIO_DIS#_R
GPS_
DISABLE#_R
RZ43
WWAN_FULL_PWR_EN [9]
1 2
+SIM_PWR
12
12
RZ76 0_04 02_5%@
RZ77 0_04 02_5%@
9/24: Reserve for embedded location ,refer Intel PDG 0.9
CLKREQ _PCIE# 0 [11 ]
1 2
1 2
RZ128 0_02 01_5%@RF@
1 2
RZ129 0_02 01_5%@RF@
1 2
RZ130 0_02 01_5%@RF@
1 2
RZ373 0_02 01_5%@RF@
1 2
RZ37
2 0_0201_5 %@RF @
1 2
RZ37
4 0_0201_5 %@RF @
0_0402_5%
@
RZ14
50
UZ51
1
B2
S
2
GND
VCC
B13A
S
N74LVC1 G3157D CKR_SC 70-6
12
RZ13
96 0_0402 _5%@
+3.3
V_RUN
12
RZ14
03 0_0402 _5%@
+3.3
V_ALW
12
RZ14
04 0_0402 _5%
UZ52
C1
A
PLTRST #_AND
A1
A2
S
N74AUP1T 97YZPR_ DSBGA6 ~D
RZ14
81 0_0402 _5%@
RZ14
80 0_0402 _5%@
WWAN
_RADIO_DIS#[58]
GPS_
DISABLE#[58]
RF Request
1 2
RI47 0
_0402_ 5%@RF@
LI8
WWANR F@
GND
GND
GNDHIGH
HIGH
HIGH
1 2
MC
M1012B9 00F06B P_4P
RI48 0
SSD-SATA
SSD-
PCIE(2 lane)
WWAN
HCA-PCIE(1 lane)
USB2
0_N7[10]
USB2
0_P7[10]
CONFIG_1 M3042_PCIE#_SATA
GND
GND
GND
HIGH
GND
GND
GND
HIGH
HIGH
1 2
NA
USB2
0_N7_L
USB2
0_P7_L
34
_0402_ 5%@RF@
High
Low
Low
Low
Low
USB3_PRX_DTX_P5[10]
USB3_PRX_DTX_N5[10]
USB3_PTX_DRX_P5[10]
CI30 0.1U_040 2_25V6
USB3_PTX_DRX_N5[10]
CI29 0.1U_040 2_25V6
WWAN
_GPIO_ CTRL#
WWAN
_GPIO_ CTRL_R
12
0_0402 _5%
10K_0402_5%
12
RZ13
99
062.2K_0 402_5%
AC B Y
0 0 0 0
1 0 1
0
1
010
1
0 0
1.8V
VGS 1.5V
+3.3
V_ALW
2
G
0
USB3_PTX_C_DRX_P5
12
USB3_PTX_C_DRX_N5
12
100K_0402_5%
RZ13
12
97
13
D
L
2N7002W T1G_S C-70-3
QZ19
S
3
1 2
RI27 0_0402 _5%@RF@
LI16
WWANR F@
1 2
HCM1012G H900BP_ 4P
1 2
RI28 0_04 02_5%@RF@
1 2
RI29 0_04 02_5%@RF@
LI17
WWANR F@
1 2
HCM1012G H900BP_ 4P
1 2
RI30 0_04 02_5%@RF@
0 0 0 X
0
1
1
USB3_PRX_L_DTX_P2
USB3_PRX_L_DTX_N2
34
USB3_PTX_L_DRX_P2
USB3_PTX_L_DRX_N2
34
B1A S B2
1 X 0
011 X
X 1
WLAN
2
1
NGFF slot E Key E
+3.3V_WLAN
JNGFF1
1
12
WLAN
21
21
GND_1
3
USB_D+
5
USB_D-
7
GND_2
9
SIDO_CLK
11
SDIO_CMD
13
SDO_DAT0
15
SDO_DAT1
17
SDO_DAT2
SDO_DAT319UART_WAKE#
SDIO_WAKE#21UART_RX
23
SDIO_RESET#
33
GND_4
35
PETP0
37
PETN0
39
GND_5
41
PERP0
43
PERN0
45
GND_6
47
REFCLKP0
REFCLKN049SUSCLK(32KHz)
51
GND_7
CLKEQ0#53W_DISABLE2#
PEWAKE0#55W_DISABLE1#
57
GND_8
RSRVD/PETP159I2C_CLK
61
RSRVD/PETN1
63
GND_9
RSRVD_2/PERP165RSVD_3
67
RSRVD_4/PERN1
69
GND_10
71
RSVD_7
73
RSVD
75
GND_
77
GND_
79
NPTH
LOTES_ APCI01 28-P005 A
RZ82
70_020 1_5% @
CNVI
_EN# [12]
_WIGIG60GHZ_DIS #_R
BT_R
ADIO_DIS#_R
USB20_P1 0_R
USB20_N10 _R
1.8V
VGS 1.5V
1 2
1 2
2
PCIE_P RX_DTX _P10[10]
PCIE_P RX_DTX _N10[10]
CLK_PC IE_P1[11 ]
CLK_PC IE_N1[11]
CLKREQ_ PCIE# 1[11 ]
PCIE_W AKE#[52,5 9,68]
G
CNV_PRX_ DTX_N1
CNV_PRX_ DTX_P 1
CNV_PRX_ DTX_N0
CNV_PRX_ DTX_P 0
CLK_CNV_ PRX_D TX_N
CLK_CNV_ PRX_D TX_P
CNV_PTX_ DRX_N1
CNV_PTX_ DRX_P 1
CNV_PTX_ DRX_N0
CNV_PTX_ DRX_P 0
CLK_CNV_ PTX_D RX_N
CLK_CNV_ PTX_D RX_P
+3.3
V_ALW
100K_0402_5%
RZ37
12
7
DVT2.0
1114 change CPN SB00001KM00
13
D
QZ17
P
JE138K _SOT52 3-3
S
DZ1
RB
751S40 T1G_SO D523-2
DZ2
RB
751S40 T1G_SO D523-2
PCIE_PTX_C_DRX_P 10
PCIE_PTX_C_DRX_N10
PCIE_W AKE#
CNV_PRX_ DTX_N1[6]
CNV_PRX_ DTX_P 1[6]
CNV_PRX_ DTX_N0[6]
CNV_PRX_ DTX_P 0[6]
CLK_CNV_ PRX_D TX_N[6 ]
CLK_CNV_ PRX_D TX_P[6]
CZ12 0.1U_0 402_25 V6
PCIE_P TX_DRX _P10[10]
CZ13 0.1U_0 402_25 V6
PCIE_P TX_DRX _N10[10]
CNV_PTX_ DRX_N1[6]
CNV_PTX_ DRX_P 1[6]
CNV_PTX_ DRX_N0[6]
CNV_PTX_ DRX_P 0[6]
CLK_CNV_ PTX_D RX_N[6 ]
CLK_
CNV_PTX _DRX_P[6]
CNV_
DET#_E C[58]
CNV_
RF_RESET#[12,52]
75K
PD at PCH side
WLAN
_WIGI G60GHZ_ DIS#[58]
BT_R
ADIO_D IS#[5 8]
CONN@
2
3.3VAUX_1
4
3.3VAUX_2
6
LED1#
8
PCM_CLK
PCM_SYNC
PCM_IN
PCM_OUT
UART_TX
UART_CTS
UART_RTS
CLink_RST
CLink_DATA
CLink_CLK
PERST0#
I2C_DATA
RSVD_1
RSVD_5
RSVD_6
3.3VAUX_3
3.3V
_8
11
13
_2
GND_
NPTH
P070011H00
GND_3
COEX3
COEX2
COEX1
ALERT
CNV_RF_R ESET#
1.8V
10
12
1.8V
14
16
LED2#
18
20
22
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
AUX_4
76
12
78
_1
5/25S
USB2
USB2
CNV_RF_RESET# [12,52 ]
CLKREQ_ CNV#_R
CNV_BRI_ PRX_D TX_R
CNV_RGI_ PTX_D RX_R
CNV_RGI_ PRX_D TX_R
CNV_BRI_ PTX_D RX_R
WLAN_CO EX3
WLAN_CO EX2
WLAN_CO EX1
WIGIG _32KHZ
PCH_PLTR ST#_A ND
BT_RADIO_DIS#_R
WLAN_WIGIG60GHZ_D IS#_R
ISH_UART0 _RXD_R
ISH_UART0 _TXD_R
ISH_UART0 _CTS#_ R
12
0_N10[10 ]
0_P10[1 0]
12
@
RZ1385 0_ 0201_ 5%
1 2
RZ1381 22_040 2_5%
1 2
RZ1383 22_040 2_5%
PCH_CL_R ST1# [8]
PCH_CL_D ATA1 [8]
PCH_CL_C LK1 [8]
RZ56 0_0201 _5%@
PCH_PLTR ST#_AND [11,38,6 8,70]
RZ78 0 _0201_ 5%@
RZ79 0 _0201_ 5%@
RZ80 0 _0201_ 5%@
9/24: Reserve for embedded location ,refer Intel PDG 0.9
10K_0402_5%
@
RZ75
2
+1.8
V_PRIM
+3.3
V_WLAN
0
1
0
.01UF_0402_25V7K
0U_0603_10V6M
.1U_0201_10V6K
1
1
12
CZ28
CZ30
2
2
RF Request
+3.3
V_WLAN
1
1
1
5P_0402_50V8J
00P_0402_50V8J
00P_0402_50V8J
RF@
RF@
RF@
12
12
12
CZ35
CZ34
CZ33
RF Request
1 2
LI12 B
LI9
1 2
MC
M1012B9 00F06B P_4P
1 2
LI13 B
CLKREQ_ CNV#
12
12
12
CZ27
Plac
1
5P_0402_50V8J
RF@
12
CZ36
@RF@
12
CLKREQ_CNV# [12]
SUSCLK [11,68]
REFCLK_ CNV_L [11]
@
12
RZ60
310K_0402 _5%
0
0
.01UF_0402_25V7K
.1U_0201_10V6K
1
12
CZ29
CZ31
2
e near JNGFF1 .2/JNGFF1 .4Place near JNGFF1.72 /JNGFF1.7 4
15P_0402_50V8J
15P_0402_50V8J
RF@
RF@
12
12
CZ20
4
LM15BB1 00SN1DRF@
34
LM15BB1 00SN1DRF @
CNV_BRI_ PRX_D TX [9]
CNV_RGI_ PTX_D RX_R [9 ]
CNV_RGI_ PRX_D TX [9]
CNV_BRI_ PTX_D RX_R [9 ]
CNV_
BRI_PT X_DRX_ R
1
0U_0402_6.3V6M
12
CZ32
100P_0402_50V8J~D
@RF@
100P_0402_50V8J~D
@RF@
1
12
CZ20
CZ20
CZ20
7
5
6
2
USB2
0_N10_R
USB2
0_P10_ R
A A
DELL
CONFIDENTIAL/PROPRIETARY
Comp
Comp
Comp
al Electronics, Inc.
al Electronics, Inc.
onday, February 25 , 2019
onday, February 25 , 2019
onday, February 25 , 2019
1
al Electronics, Inc.
NGFF
NGFF
NGFF
Card
Card
Card
LA-G
LA-G
LA-G
891P
891P
891P
0.3
0.3
0.3
52 1 02M
52 1 02M
52 1 02M
of
of
of
Titl
Titl
Title
e
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
e
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Page 53
5
D D
C C
4
3
2
1
Reserve
B B
A A
DEL
L CONFIDENTIAL/PROPRIETARY
Com
Com
pal Electronics, Inc.
Tit
Tit
Tit
le
le
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronics, Inc.
WIG
WIG
IG/WIDI
IG/WIDI
LA-
LA-
G891P
G891P
1
53 10
53 10
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
of
of
of
Page 54
5
D D
C C
4
3
2
1
RESERVE
B B
A A
DELL
CONFIDENTIAL/PROPRIETARY
Comp
Comp
al Electronics, Inc.
Titl
Titl
Titl
e
e
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
e
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
PCIE/SA
PCIE/SA
TA DEMUX
TA DEMUX
LA-G
LA-G
891P
891P
0.3
54 102M
54 102M
of
of
1
of
0.3
Page 55
5
D D
C C
4
3
2
1
Reserve
B B
A A
DEL
L CONFIDENTIAL/PROPRIETARY
Com
Com
pal Electronics, Inc.
Tit
Tit
Tit
le
le
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronics, Inc.
PCIE
PCIE
device
device
LA-
LA-
G891P
G891P
1
55 10
55 10
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
of
of
of
Page 56
5
1W x 1ch, 4ohm (Transducer spec is 8Ohm /0.5Watt per unit, there are two transd ucer units in one speaker box.)
Internal Speakers Header
40 mils trace keep 20 mil spacing
1 2
LA6 BLM15PX800SN1D_2 PEMI@
1 2
INT_SPK_R+
INT_SPK_R-
D D
1000P_0402_50V7K
12
LA7 BLM15PX800SN1D_2 PEMI@
1 2
LA8 BLM15PX800SN1D_2 PEMI@
1 2
LA9 BLM15PX800SN1D_2 PEMI@
EMI@
CA22@
EMI@
EMI@
EMI@
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
12
12
12
CA24@
CA23@
CA19@
INT_SPKR_L+INT_SPK_L+
INT_SPKR_L-INT_SPK_LÂINT_SPKR_R+
INT_SPKR_R-
AZ
5125-02S.R7G 3P C/A SOT23
2
3
2
@ESD@
DA6
1
1
CONN@
JSPK1
1
1
2
2
3
3
4
4
5
AZ
G1
6
5125-02S.R7G 3P C/A SOT23
3
G2
@ESD@
ACES_50278-00401-001
Link 50278-00401-001 DONE
DA7
Close to UA1
Close to UA1 pin5
HDA_
BIT_CLK_R
@
33_0402_5%
12
RA17RF
10P_0402_50V8J
@
12
C C
CA33RF
+3.3
Place closely to Pin 12.
AUD_HP_
NB_SENSE
V_RUN_AUDIO
12
12
DMIC
100P_0402_50V8J
@
12
CA54RF
place close to UA1 pin3
100K_0402_1%
RA59
AUD_SE
200K_0402_1%
RA60
_CLK0
NSE_A
12
+3.3
V_RUN_AUDIO
0
.1U_0402_25V6
@
CA41
Add for solve
pop noise and
detect issue
4
+3.3V_RUN_AUDIO
00K_0402_5%
0K_0402_5%
1
U_0201_6.3V6M
12
LA12 BLM15PX600SN1D_2 P
12
LA14 BLM15PX600SN1D_2 P
HDA_
SYNC_R[12]
HDA_
BIT_CLK_R[12]
HDA_
SDOUT_R[12]
HDA_
1 2
SDIN0[12]
RA521
DMIC
0[38]
DMIC
_CLK0[38]
12
PD#
RA181
12
CA31
0
1
.1U_0201_10V6K
0U_0603_10V6M
CA10
1
2
CA61
12
place close to pin1
HDA_
BIT_CLK_R
1 2
RA9 33
Place RA9 close to codec
DMIC
_CLK0
1 2
RA14E
MI@ 22_0402_5%
00K_0402_5%
0U_0603_10V6M
0U_0603_10V6M
0U_0603_10V6M
HDA_
HDA_
_0402_5%
DMIC
12
12
12
INT_
INT_
INT_
INT_
AUD_
1
2
SDOUT_R
SDIN0_R
_CLK_CODEC
12
RA441
CA511
CA521
CA531
SPK_L+
SPK_LÂSPK_RÂSPK_R+
SENSE_A
+3.3V_RUN_AUDIO_IO
0
.1U_0201_10V6K
CA55
3
+5V_RUN_PVDD_L
1
0U_0603_10V6M
CA56
12
place close to pin8
+3.3V_RUN_AUDIO_DVDD
1
8
20
29
33
34
UA1
9
SYNC
5
BIT-
CLK
4
SDAT
A-OUT
7
SDAT
A-IN
10
DC_D
ET
2
GPIO
0/DMIC-DATA12
3
GPIO
1/DMIC-CLK
40
PDB
21
LDO1
-CAP
32
LDO2
-CAP
6
LDO3
-CAP
35
SPK-
OUT-LP
36
SPK-
OUT-LN
37
SPK-
OUT-RN
38
SPK-
OUT-RP
12
HP/L
INE1_JD1
AL
C3204-CG_MQFN40_5X5
CBP
CBN
Place CA29/CA76 close to Codec
0809 change to 1U 0201*2 for MLCC shortage
only Samsung,Taiyo,Murata can use
39
1
2
1
2
-IO
DVDD
PVDD
DVDD
1
U_0201_6.3V6K
1
1
CA29
2
2
D
AVDD
AVDD
PVDD
CPVD
LINE
1-VREFO-L
MIC2
MIC2
MIC2
-R/SLEEVE
MIC2
HP-O
HP-O
THER
1
1
U_0201_6.3V6K
U_0201_6.3V6K
1
CA76
CA78
2
place close to pin39place close to pin34
1
0
0U_0603_10V6M
.1U_0201_10V6K
CA45
1
1
1
CA46
2
2
2
+VDDA_AVDD1
+1.8V_RUN_AUDIO
24
LINE1
23
+MIC
-VREFO
2
2
VREF
28
CBN
30
CBP
16
VD33
STB
27
CPVE
E
SLEEVE/RING2 please keep 40 mils trace width
13
RING
-L/RING2
14
SLEE
15
-CAP
LINE1
18
LINE
1-L
LINE1
17
LINE
1-R
AUD_PC_
11
PCBE
EP
HP_O
25
UT-L
HP_O
26
UT-R
19
AVSS
1
31
AVSS
2
41
MAL_PAD
CPVE
E
1
U_0201_6.3V6K
1
CA77
2
HCB2012KF-121T50_2P
1
0
.1U_0201_10V6K
0U_0603_10V6M
CA47
1
CA48
2
place close to pin20
place close to pin33
-VREFO
2-VREFO
1 2
CA35
2.2U_0201_6.3V6M
CBN
CBP
1 2
RA53 0
RA54
@
1 2
CPVE
E
2
VE
0U_0603_10V6M
_L
_R
0U_0603_10V6M
BEEP
0U_0603_10V6M
UT_L
UT_R
HP-Out-Left
2
LA13
1 2
10
U_0603_10V6M
12
1
0U_0603_10V6M
12
AUD_
.2_0402_1%
EMI@
3
30P_0402_50V8J
1
CA73
2
CA9
CA58
_0402_5%@
0
_0402_5%
PC_BEEP
1 2
1 2
1 2
600 Ohm/2A
0.
1U_0201_10V6K
CA8
1
2
0
0_0603_5%
.1U_0201_10V6K
CA57
1
2
CA251
1 2
3
30P_0402_50V8J
1
2
CA27 0
CA28 0
CA431
CA441
.2_0402_1%
0
.1U_0201_10V6K
1
2
LA5
1 2
BLM15PX600SN1D_2P
1 2
LINE1
-VREFO
Place CA29 close to Codec
+3.3
V_RTC_LDO
+RTC
_CELL
HP_O
HP_O
RA816
EMI@
CA74
Place near Codec
HP-Out-Right Nokia-MIC
CA60
1
2
12
12
.1U_0402_25V6
.1U_0402_25V6
UT_L
UT_R
1 2
+5V_RUN_AUDIO
1
0U_0603_10V6M
CA59
+5V_RUN_AUDIO
+1.8V_RUN
RA3
@
AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width
DA4
12
+LINE
1N4
148WS-L_SOD323-2
1N4
148WS-L_SOD323-2
RA716
1-VREFO-L
DA5
12
+LINE
1-VREFO-R
+MIC
2-VREFO
SPKR_
R
1 2
BEEP
_R
1 2
RA12 1
RA13 1
AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width
AUD_
HP_OUT_L
AUD_
HP_OUT_R
iPhone-MIC
SPKR_R
1 2
RA57 4
1 2
RA58 4
1 2
RA5 2.
1 2
RA6 2.
K_0402_5%
K_0402_5%
.7K_0402_5%
.7K_0402_5%
RING
2
2K_0402_5%
SLEE
VE
2K_0402_5%
SPKR
BEEP
1
1
00P_0402_50V8J
12
CA72@
[12]
[58]
12
1
0K_0402_5%
RA51
AUD_HP_
AUD_HP_
+1.8
OUT_L
OUT_R
V_RUN_AUDIO
RF@
3
3P_0402_50V8J
CA69
1
2
BEEP_R
1
00P_0402_50V8J
12
CA62@
RF Request
+5V_RUN_AUDIO
1
2P_0402_50V8J
1
2
RF Request
+1.8
V_RUN
1
2
RF Request
+3.3
V_RUN_AUDIO
1
2
1
0K_0402_5%
12
RA45
6
RF@
RF@
8P_0402_50V8J
1
CA64
CA63
2
6
1
RF@
RF@
8P_0402_50V8J
2P_0402_50V8J
1
CA66
CA65
2
RF@
RF@
1
6
2P_0402_50V8J
8P_0402_50V8J
1
CA67
CA68
2
Global Headset
CLASS-D POWER DOWN CONTROL CIRCUIT
B B
@
+5V_
RUN_AUDIO
RA48 0
DA8
@
RA50 0
@
12
CZ12
CZ12
@
CZ12
@
CZ12
place at AGND and DGND plane
_0402_5%
0
_0402_5%
0
_0402_5%
1 2
1 2
1 2
RA350
@
@
RA36
@
RA37
PJP1
1 2
PAD-OPEN1x1m
9
NB_M
UTE#[58]
HDA_
RST#_R[12]
HDA_
Link is 3.3V,no need level shift circu it
Power sequence +5V_RUN_AUDIO(501us) > +3.3V_RUN_AUDIO(1204 us) > +1.5V_RUN
Reserve for support D3 cold
+5V_
RUN
UZ5
@
1
VIN1
_1
2
VIN1
A A
5
AUD_
PWR_EN[12]
+5V_
ALW
+3.3
V_RUN
3
ON1
4
VBIA
5
ON2
6
VIN2
7
VIN2
EM
5209VF_SON14_2X3
_2
S
_1
_2
4
VOUT
VOUT
VOUT
VOUT
GND
GPAD
+5V_
RUN_AUDIO_UZ5
14
1_2
13
1_1
12
CT1
11
10
CT2
9
2_2
+3.3
V_RUN_AUDIO_UZ5
8
2_1
1
5
1 2
RB7
51S40T1G_SOD523-2
1 2
@JUMP@
PJP1
5
PAD-OPEN1x1m
1 2
5 0.1U_0201_10V6K@
1 2
6
1 2
7
PJP1
6@JUMP@
1 2
PAD-OPEN1x1m
1 2
8 0.1U_0201_10V6K@
_0402_5%
21
_0402_5%
+5V_
RUN
+3.3
V_RUN
220P_0402_50V7K
1000P_0402_50V7K
+3.3
PD#
RE313@one control line if DVDD is 3.3V
DE2@two control lines1
PJP1
7
1 2
+5V_
PAD-OPEN1x2m
PJP1
8
1 2
+3.3
PAD-OPEN1x1m
V_RUN_AUDIO
500mA
RUN_AUDIO
2.5A
V_RUN_AUDIO
3
RING
2
AUD_HP_
AUD_HP_
SLEE
LA10 B
OUT_R
LA15 B
LA16
EMI@
OUT_L
VE
LA11 B
If EMI changes value,
need to inform vendor first .
1 2
LM15PX330SN1D_2PESD@
1 2
LM15PX330SN1D_2PEMI@
1 2
B
LM15PX330SN1D_2P
1 2
LM15PX330SN1D_2PESD@
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Univ
ersal Jack
Add this Filter to avoid other
components/chips be infl uenced
RING
2_R
AUD_HP_
OUT_R1
AUD_HP_
OUT_L1
SLEE
VE_R
ESD@
22
0P_0402_50V7K
CA1
1
2
@ESD@
6
80P_0402_50V7K
1
CA13
2
AUD_HP_
NB_SENSE
ESD@
68
68
EMI@
EMI@
22
0P_0402_50V7K
0P_0402_50V7K
1
2
2
CA3
CA2
2
1
1
2
ESD@
0P_0402_50V7K
2
3
3
DA1
CA4
AZ51
23-02S.R7G_SOT23-3
1
1
ESD@
ESD@
2
3
2
DA3
DA2
AZ51
AZ51
23-02S.R7G_SOT23-3
25-02S.R7G 3P C/A SOT23
1
DELL
CONFIDENTIAL/PROPRIETARY
Titl
Titl
Titl
e
e
e
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
6
@ESD@
80P_0402_50V7K
1
CA12
2
Comp
Comp
Comp
onday, February 25, 2019
onday, February 25, 2019
onday, February 25, 2019
JHP1
CONN@
7
GND
4
#4 G
/M
2
#2 R
6
#6 A
GND
5
#5
1
#1 L
3
#3 M
/G
SI
NGA_2SJ3095-136111F~D
al Electronics, Inc.
al Electronics, Inc.
al Electronics, Inc.
Code
Code
Code
c ALC3204
c ALC3204
c ALC3204
LA-G8
LA-G8
LA-G8
1
91P
91P
91P
0.3
0.3
56 102M
56 102M
56 102M
0.3
of
of
of
Page 57
5
D D
C C
4
3
2
1
Reserve
B B
A A
DEL
L CONFIDENTIAL/PROPRIETARY
Com
Com
pal Electronics, Inc.
Tit
Tit
Tit
le
le
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronics, Inc.
Aud
Aud
io Amplifier
io Amplifier
LA-
LA-
G891P
G891P
1
57 10
57 10
of
of
of
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
Page 58
5
+RTC_CELL
+3.3V_ALW_UE1
+3.3V_ALW
+3.3V_ALW_UE1
D D
0
0
.1U_0201_10V6K
CE20
RF@
6
8P_0402_50V8J
1
CE60
2
PJP2
1 2
1
PAD-OPEN1x1m
CE22
0
.1U_0201_10V6K
2
+3.3
V_ALW
@
RE50
RE52
RE53
+1.8
V_ALW_VTR3
@
RE34
1 2
6 100K_0402_5%
1 2
7 100K_0402_5%
1 2
8 100K_0402_5%
+3.3
V_ALW
1
00K_0402_5%
RE63
1 2
JTAG
_RST#
1
1
12
00_0402_1%
U_0201_6.3V6M
1
RE65@
CE30
2
MEC_X
+3.3V_ALW_UE1
+3.3V_ALW_UE1
0
+1.8
1
0
.1U_0201_10V6K
Close to pin N5
2
12
5 100K_0402_5%
12
6 10K_040 2_5%@
12
2 4.7K_040 2_5%
1 2
0 10K_0402_5%
+3.3
V_ALW2
CV2_
ON_R
IMVP
_VR_ON_EC
RUN_ON_
EC
+1.8
TAL2_R
12
.1U_0201_10V6K
CE19
1
1
2
2
close to pin G8/M9
RF Request
+3.3
V_ALW
RF@
1
2P_0402_50V8J
1
CE59
2
+1.8
V_PRIM
C C
RE71
RE71
B B
A A
RE71
1
@SHORT PADS~D
JTAG
1
1 @
2
2
32 KHz Clock
YE1
MEC_
XTAL1
1
0P_0402_50V8J
32
12
CE28
MEC_
XTAL2
1 2
.768KHZ_9PF_X1A000141000200
12
5
10U_0402_6.3V6M
12
CE16
0.1U_0201_10V6K
1
2
Close to pin H1
SLP_
V_ALW_VTR3
CE21
LOM_
WWAN_
GPIO_CTRL
RE57 1
V_ALW_VTR3
12
RE54
9
100K_0402_5%
ENABL
12
RE55
0
@
100K_0402_5%
RE29
0
@
0_0402_5%
8/28 schematic review
1
0P_0402_50V8J
CE29
PJP22
1 2
PAD-OPEN1x1m
CE15
WLAN#_GATE[78]
CABLE_DETECT#
USH_DE
BCM58
82_ALERT#
E_DS#
1 2
RE32 0_0402_5%
@
0
.1U_0201_10V6K
1
2
12
RE314100_0 402_1%
1
2
+VSS_PLL
PCH_DPWROK[11]
SIO_
EXT_WAKE#[9]
SIO_
SLP_SUS#[11]
1 2
CNV_DE
+3.3
V_ALW
T#
12
K_0402_5%@
12
1
00K_0402_5%
SSD_
SCP_PWR_EN[78]
SYS_
PWROK[11,79]
DCIN
Deep Sleep support
non Deep Sleep
Deep Sleep10
For EMI request
ESPI
_CLK_5105
33_0402_5%
@EMI@
12
RE35
0
33P_0402_50V8J
@
EMI@
12
CE57
0
.1U_0201_10V6K
1
U_0201_6.3V6M
CE13
2
2U_0603_6.3V6M
@
CE17
CE23
1
1
CE14
2
2
0
.1U_0201_10V6K
1
CE18
2
1 2
RE536
DS3@
1 2
@
RE70
30_0402_5%
1 2
RE34
9 43K_0402_1%DS3@
FPR_
WLAN
@
RE55
20_0 402_5%
CLK_
DAT_
T#_EC[52]
12
RE36
2100K_0402_5%
WWAN
BC_D
RE60
2
@
@
RE54
8 0_0402_5%
@
RE60
0 0_0402_5%
CPU_
10K_0402_5%
FPR_
SCAN_INT#[66]
1 2
1 2
1 2
C10_GATE#[6,17,87]
RE70
VBUS
1_ECOK_R[82]
RE58
SYS_
PWROK
1_EN_R[8 2]
+3.3V_ALW_UE1
+1.8V_ALW_VTR3
0_0402_5%
RUN_ON_EC[59]
BT_R
ADIO_DIS#[52]
PBAT
_PRES#[83,84]
PANE
AC_P
RESENT[11]
SML1
_SMBDATA[8]
SML1
_SMBCLK[8]
WWAN
_WAKE#[52]
LOW_PWR_MODE#[66]
_WIGIG60GHZ_DIS#[52]
SIO_
PWRBTN#[11,79]
LID_
CL_SIO#[59]
TP_SIO_I2C_DAT[63]
TP_SIO_I2C_CLK[63]
JTAG
JTAG
JTAG
JTAG
TACH
LCD_
PWM_
PCH_
RSMRST#[6 3,79]
BIA_
PWM_EC[38]
HW_A
CAVIN_NB[82,84]
PANE
L_BKEN_EC[38]
56]
FPR_DE
BCM58
82_ALERT#[66]
MSDA
NB_M
UTE#[56]
EN_I
IMVP
_VR_ON_EC[59]
FPR_
UEFI_MGMT#[66]
M_BI
AC_D
USH_DE
_RADIO_DIS#[52]
AT_ECE1117[63]
BC_CLK
_ECE1117[63]
NGFF
_CONFIG_3[52]
ESPI
ESPI
WWAN
_GPIO_CTRL[52]
ESPI
_CLK_5105[8,79]
ESPI
ESPI
ESPI
ESPI
ESPI
+3.3
V_FPBTN
12
9
L_MONITOR[79]
_TDI[79]
_TDO[79]
_CLK[79]
_TMS[79]
_FAN1[77]
FAN1[77]
PS_I
BEEP[
AC_D
MSCL
NVPWR[38]
ST[79]
ISC#[82]
0_0402_5%
_RESET#[8,79]
_ALERT#[8]
_CS#[8,79]
_IO0[8,79]
_IO1[8,79]
_IO2[8,79]
_IO3[8,79]
FPR_S
TST[38]
T#[66]
IS[84]
TA[79]
T#[66]
4
D[82]
K[79]
+3.3
100K_0402_5%
2
CAN_INT#
4
+RTC_CELL_VBAT
0
.1U_0201_10V6K
CE11
1
2
+3.3V_EC_PLL
PCH_DPWROK_EC
SIO_EXT_WAKE#_EC
WLAN_
SLP_
LCD_TS
CPU_C1
SSD_S
CP_PWR_EN
V_ALW
RE82
@
8
1 2
CPU_
L2N7002DW1T1G_SC88-6
6
1
RE82
@
RUN_ON_EC
BT_RA
DIO_DIS#
SIO_
SLP_SUS#_R
PANEL
_MONITOR
WWAN_
WAKE#
FPR_L
OW_PWR_MODE#
WIGIG60GHZ_DIS#
WLAN#_GATE_R
JTAG
_TDI
JTAG
_TDO
JTAG
_CLK
JTAG
_TMS
JTAG
_RST#
T
CNV_DE
PCH_RSM
RST#
PS_I
D
FPR_S
CAN_INT#_EC
HW_A
CAVIN_NB
BEEP
FPR_DE
T#
AC_DIS
MSCL
K
MSDA
TA
EN_INV
PWR
RESE
T_IN#
IMVP
_VR_ON_EC
RTCRST
_ON
WWAN_
RADIO_DIS#
SYSP
WR_PRES
0_GATE#_Q
VBUS1
_ECOK
ESPI
_ALERT#
ENABL
E_DS#
RESE
T_OUT
DCIN1_
EN
MEC_
XTAL1
MEC_
XTAL2_R
C10_GATE
@
QE21
A
5
1 2
QE20
L
2N7002WT1G_SC-70-3
S
G
2
+3.3
V_FPBTN
T#_EC
D
13
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
5
0_0402_5%
FPR_S
A2
B7
K2
F1
H1
G8
M9
N5
F8
E8
M12
C2
F9
N4
M8
K8
E11
D8
M13
K12
L13
K11
K10
N11
E10
C12
E9
F6
C8
C5
G13
E3
D1
M2
L10
L11
M5
J8
N1
L8
N6
J9
H11
D9
H12
G10
H10
G9
A4
B2
C1
N7
K9
N8
F13
E13
C13
E12
F11
F12
D12
D13
F4
B1
K7
N3
K6
H7
K1
G7
H6
K5
L4
G6
L5
L2
M1
G4
L12
A1
A3
+1.8
V_ALW_VTR3
10K_0402_5%
@
RE82
9
CAN_INT#_EC
UE1
VBAT
VTR_ANALOG
VREF_ADC
VTR_PLL
VTR_REG
VTR1
VTR2
VTR3
GPIO020
GPIO045
GPIO
120
GPIO
166
GPIO
175
GPIO
230
GPIO
231
GPIO
233
GPIO
007/SMB03_DATA/PS2_CLK0B
GPIO
010/SMB03_CLK/PS2_DAT0B
GPIO
110/PS2_CLK2
GPIO
111/PS2_DAT2
GPIO
112/PS2_CLK1A
GPIO
113/PS2_DAT1A
GPIO
114/PS2_CLK0A/nEC_SCI
GPIO
115/PS2_DAT0A
GPIO
154/SMB02_DATA/PS2_CLK1B
GPIO
155/SMB02_CLK/PS2_DAT1B
GPIO
145/SMB09_DATA/JTAG_TDI
GPIO
146/SMB09_CLK/JTAG_TDO
GPIO
147/SMB08_DATA/JTAG_CLK
GPIO
150/SMB08_CLK/JTAG_TMS
JTAG
_RST#
GPIO
050/FAN_TACH0/GTACH0
GPIO
051/FAN_TACH1/GTACH1
GPIO
052/FAN_TACH2/LRESET#
GPIO
053/PWM0/GPWM0
GPIO
054/PWM1/GPWM1
GPIO
055/PWM2/SHD_CS#/(RSMRST#)
GPIO
056/PWM3/SHD_CLK
GPIO
001/PWM4
GPIO
002/PWM5
GPIO
014/PWM6/GPTP-IN6
GPIO
015/PWM7
GPIO
035/PWM8/CTOUT1
GPIO
133/PWM9
GPIO
134/PWM10/UART1_RTS#
GPIO
135/UART1_CTS#
GPIO
170/TFDP_CLK/UART1_TX
GPIO
171/TFDP_DATA/UART1_RX
GPIO
022/GPTP-IN0
GPIO
023/GPTP-IN1
GPIO
024/nRESETI
GPIO
031/GPTP-OUT1
GPIO
032/GPTP-OUT0
GPI0
040/GPTP-OUT2
GPIO
121/PVT_IO0
GPIO
124/GPTP-OUT6/PVT_CS#
GPIO
125/GPTP-OUT5/PVT_CLK
GPIO
126/PVT_IO3
GPIO
122/BCM0_DAT/PVT_IO1
GPIO
123/BCM0_CLK/PVT_IO2
GPIO
046/BCM1_DAT
GPIO
047/BCM1_CLK
GPIO
041/SYS_SHDN#
SYSP
WR_PRES
GPIO
011/nSMI
GPIO
021/LPCPD#
GPIO
061/LPCPD#/ESPI_RESET#
GPIO
063/SER_IRQ/ESPI_ALERT#
GPIO
064/LRESET#
GPIO
065/PCI_CLK/ESPI_CLK
GPIO
066/LFRAME#/ESPI_CS#
GPIO
070/LAD0/ESPI_IO0
GPIO
071/LAD1/ESPI_IO1
GPIO
072/LAD2/ESPI_IO2
GPIO
073/LAD3/ESPI_IO3
GPIO
067/CLKRUN#
GPIO
100/nEC_SCI
GPIO
106/PWROK
GPIO
107/nSMI
XTAL
1
XTAL
2
L2N7002DW1T1G_SC88-6
1 2
CPU_
C10_GATE#_Q
34
@
QE21
B
+3.3
V_ALW
12
RE82
10K_0402_5%
6
A
6
FPR_
SCAN_INT#_EC [66]
RUN_
3
TYPEC_ID
GPIO026/TIN1
GPIO027/TIN2
GPIO030/TIN3
017/GPTP-IN5
GPIO
151/ICT4
152/GPTP-OUT3
GPIO
156/LED0
GPIO
157/LED1
GPIO
153/LED2
GPIO
226/LED3
GPIO
200/ADC00
GPIO
201/ADC01
GPIO
202/ADC02
GPIO
203/ADC03
GPIO
204/ADC04
GPIO
205/ADC05
GPIO
206/ADC06
GPIO
207/ADC07
GPIO
210/ADC08
GPIO
211/ADC09
GPIO
212/ADC10
GPIO
213/ADC11
GPIO
214/ADC12
GPIO
215/ADC13
GPIO
216/ADC14
GPIO
217/ADC15
222/SER_IRQ
223/SHD_IO0
227/SHD_IO2
BGPO
VCI_
163/VCI_IN0#
162/VCI_IN1#
161/VCI_IN2#
000/VCI_IN3#
044/VREF_VTT
043/SB-TSI_CLK
DN1_
DP1A
DP1_
DN1A
DN2_
DP2A
DP2_
DN2A
DN3_
DP3A
DP3_
DN3A
DN4_
DP4A
DP4_
DN4A
VSET
THER
MTRIP1#
MEC51
05_WFBGA169_11X11
1
0K_0402_5%
L
2N7002DW1T1G_SC88-6
QE2B
F2
J10
J13
E7
D7
G3
H5
G11
G12
B13
F10
N13
N12
M11
H9
L9
M10
N9
C11
D10
D11
E1
E5
B3
M7
M4
M3
N2
N10
A12
B6
F7
B4
C3
J4
J5
J6
G2
H2
J2
J3
K3
D3
D2
E2
G5
F5
K4
L1
L3
H8
J7
L6
L7
M6
D6
0
C7
A5
OUT
D5
B5
D4
E4
C6
F3
J11
K13
J12
A8
A7
A10
A9
B9
B8
A11
B10
C1
VIN
C
B1
VCP
H3
B12
H13
L
2N7002WT1G_SC-70-3
SYSTEM_ID
BOARD_ID
UPD2_SMBDAT
UPD2_SMBCLK
RUNPWROK
GPS_DISABLE#
RTCRST_ON_POWER
UPD1_SMBINT#
PCIE_WAKE#_R
VGA_
IDENTIFY
VCCDSW_
EN
DGPU_
PWROK
PBAT
_CHARGER_SMBDAT
PBAT
_CHARGER_SMBCLK
LED_M
ASK#
UPD1_
SMBDAT
UPD1_
SMBCLK
I_BA
TT_R
I_SY
S_R
NB_M
ODE#
TOUCHPA
D_INTR#_R
USH_P
WR_STATE#_R
USB_
POWERSHARE_VBUS_E N
USB_
POWERSHARE_EN#
USB_
PWR_EN1#
USB_
PWR_EN2#
PRIVA
CY_ENABLE
DCIN2_
EN
CV2_
ON_R
3.3V
_TS_EN
PRIM_
PWRGD
VBUS2
_ECOK
BGPO
0
VCI_I
N1#
VCI_I
N2#
VCI_I
N3#
32KHZ
_OUT
+PECI
_VREF
PECI
_EC_R
M304
2_PCIE#_SATA
REM_
DIODE1_N
REM_
DIODE1_P
REM_
DIODE2_N
REM_
DIODE2_P
REM_
DIODE4_N
REM_
DIODE4_P
+VR_CA
P
0
VSET
_5105
9
1
THERMT
RIP2#
PROCHOT
#_R1
+RTC_CE
LL_PCH
1
CE63
1
U_0201_6.3V6M
2
QE17
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
GPIO033/RC_ID0
GPIO034/RC_ID1/SPI0_CLK
GPIO036/RC_ID2/SPI0_MISO
GPIO003/SMB00_DATA/SPI0_CS#
GPIO004/SMB00_CLK/SPI0_MOSI
GPIO057/VCC_PWRGD
GPIO060/KBRST/48MHZ_OUT
GPIO104/UART0_TX
GPIO105/UART0_RX
GPIO127/A20M/UART0_CTS#
GPIO225/UART0_RTS#
GPIO025/TIN0/nEM_INT/UART_CLK
GPIO
GPIO
GPIO
005/SMB01_DATA/GPTP-OUT4
GPIO
006/SMB01_CLK/GPTP-OUT7
GPIO
012/SMB07_DATA/TOUT3
GPIO
013/SMB07_CLK/TOUT2
GPIO
130/SMB10_DATA/TOUT1
GPIO
131/SMB10_CLK/TOUT0
GPIO
132/SMB06_DATA
GPIO
GPIO
141/SMB05_DATA/SPI1_CLK/UART0_DCD#
GPIO
142/SMB05_CLK/SPI1_MOSI/UART0_DSR#
GPIO
143/SMB04_DATA/SPI1_MISO/UART0_DTR#
GPIO
ADC
VSS1
VSS_
VSS2
VSS3
6
13
A
J1
E
H4
P
+VR_CA
+3.3
V_ALW
RE68
1 2
6
2
ON[17,59,78, 87]
1
140/SMB06_CLK/ICT5
144/SMB04_CLK/SPI1_CS#/UART0_RI#
GPIO
GPIO
GPIO
224/GPTP-IN4/SHD_IO1
GPIO
GPIO
016/GPTP-IN7/SHD_IO3/ICT3
GPIO
164/VCI_OVRD_IN
GPIO
GPIO
GPIO
GPIO
GPIO
165/32KHZ_IN/CTOUT0
GPIO
221/GPTP-IN3/32KHZ_OUT
GPIO
GPIO
042/PECI_DAT/SB-TSI_DAT
GPIO
GPIO
103/THERMTRIP2#
GPIO
160/PWM11/PROCHOT#
AP
PLL
ANALOG
VR_C
VSS_
VSS_
C4
G1
+VSS
_PLL
1
CE31
1
U_0201_6.3V6M
2
+3.3
V_RUN
RE67
1
00K_0402_5%
1 2
RUNP
WROK
34
RUN_
ON#
5
L
2N7002DW1T1G_SC88-6
QE2A
3
TYPEC_ID [59]
SYSTEM_ID [59]
BOARD_ID [59]
GPS_DISABLE# [52]
HOST_DEBUG_TX [79]
ME_FWP [79]
UPD1_SMBINT# [44]
PCIE_WAKE#_R [59]
TP_DISABLE# [63]
FPR_PWR_EN# [66]
FPR_SSO_EN# [66]
NGFF
NGFF
BREA
BAT1
BAT2
LCD_
USH_
USH_
VCCD
DGPU
PBAT
PBAT
NGFF
LED_
UPD1
UPD1
1 2
RE64 3
1 2
RE31
2 300_0402_5%
1
P
AD~D
@
RE31
8
1 2
RE60
8
@
USB_
USB_
AUX_
LOM_
BC_I
USB_
@
RE60
1 0_0402_5%
PCH_
LAN_
1 2
RE53
9 100_0402_5%
3.3V
SSD_
@
RE60
3 0_0402_5%
1
T341
@
P
AD~D
ACAV
ALWO
POWE
3.3V
_WWAN_EN [78]
1 2
CE54 1
1 2
RE60 4
1 2
CE24 2
1 2
CE26 2
1 2
CE27 2
VSET
I_AD
THER
1 2
RE28
8 100_0402_5%
10K_0402_5%
12
RE54
6
RB7
13
D
RTCRST
_ON_R
2
G
S
2
2P_0402_50V8J
12
_CONFIG_1 [52]
_CONFIG_0 [52]
TH_LED# [64]
_LED# [64]
_LED# [64]
VCC_TEST_EN [38]
EXPANDER_SMBDAT [66]
EXPANDER_SMBCLK [66]
SW_EN [11]
_PWROK [12]
_CHARGER_SMBDAT [83,84]
_CHARGER_SMBCLK [83,84]
_CONFIG_2 [52]
MASK# [51,64]
_SMBDAT [44]
_SMBCLK [44]
00_0402_5%
USB_
POWERSHARE_EN# [71]
PWR_EN1# [72]
EN_WOWL [78]
CABLE_DETECT# [51]
NT#_ECE1117 [63]
PWR_EN2# [72]
12
PCIE_WAKE# [11,59]
WAKE# [11,51]
_TS_EN [38]
SCP# [68]
0_0402_5%
_IN [79,84,91]
N [85]
R_SW_IN# [59,79]
0P_0402_50V8J@
3_0402_5%
200P_0402_50V7K
200P_0402_50V7K
200P_0402_50V7K
_5105 [59]
P [84]
MTRIP2# [59 ]
2 1
51S40T1G_SOD523-2
CE65
2
I_BA
TT [84]
I_SY
12
12
3
0_0402_5%
1 2
LP23
S [84,8 8]
TOUCHPA
PRIV
ACY_ENABLE [38]
DCIN
2_EN_R [82]
CV2_
@
RE36
1
VBUS
M304
QE15
01ALT1G_SOT23-3
123
D
S
G
100K_0402_5%
1 2
2
PECI
2_PCIE#_SATA [10]
RE54
1
T348
@
0_0402_5%
POWERSHARE_VBUS_EN [71]
DE2
RE54
1 2
1M_0402_5%
FPR_SSO_EN#
RE706 10K_0402_5%
FPR_UEFI_MGMT#
RE707 10K_0402_5%
FPR_LOW_PWR_ MODE#
RE708 10K_0402_5%
D_INTR# [14,63]
USH_
PVT
Add PRIVACY circuit
ON [66]
1.0V
2_ECOK_R [82]
RE59 close to UE2 at least 250mils
+PECI
_VREF
@
0
.1U_0201_10V6K
12
_EC [14]
PROC
HOT# [14,8 4,88]
+RTC_CE
@
RE56
0
.1U_0402_25V6
@
CE64
12
1 2
1 2
1 2
PWR_STATE# [66]
_PRIM_PWRGD [87]
RE59 0
CE25
REM_
DIODE1_N
REM_
DIODE1_P
REM_
DIODE2_N
REM_
DIODE2_P
REM_
DIODE4_N
REM_
DIODE4_P
LL
1 2
5 0_0402_5%
12
RTCRST
VCCDSW_
PRIM_
ACAV_
_0402_5%
+3.3V_FPBTN
PWRGD
IN
REM_
REM_
REM_
REM_
REM_
REM_
_ON_POWER
1
USB_
USB_
USB_
USB_
EN
0
.1U_0402_25V6
@
CE66
12
0
.1U_0402_25V6
@
CE68
12
0
.1U_0402_25V6
@
CE67
12
+1.0
V_VCCST
DIODE1_N [59]
DIODE1_P [59]
DIODE2_N [59]
DIODE2_P [59]
DIODE4_N [59]
DIODE4_P [59]
UPD1_SMBDAT
UPD1_SMBCLK
UPD1_SMBINT#
PRIVACY_ENABLE
PBAT_CHARGER_SMBDAT
PBAT_CHARGER_SMBCLK
SIO_SLP_SUS#_R
UPD2_SMBCLK
UPD2_SMBDAT
NGFF_CONFIG_1
NGFF_CONFIG_2
NGFF_CONFIG_0
NGFF_CONFIG_3
PWR_EN2#
POWERSHARE_EN#
PWR_EN1#
POWERSHARE_VBUS_E N
AC_DIS
GPS_
WLAN_
LED_M
SSD_S
PCIE_
FPR_P
BC_DAT
WWAN_
BT_RA
FPR_DE
TP_DI
VCI_I
VCI_I
VCI_I
3.3V
VGA_
VGA_
DISABLE#
WIGIG60GHZ_DIS#
ASK#
CP#
WAKE#_R
WR_EN#
_ECE1117
RADIO_DIS#
DIO_DIS#
T#
SABLE#
N1#
N2#
N3#
I_BA
TT_R
I_SY
S_R
PCH_RSM
SYS_
PWROK
I_SY
S_R
LCD_TS
T
EN_I
NVPWR
_TS_EN
IDENTIFY
IDENTIFY
RST#
RE302 2.2K_0402_5%
RE303 2.2K_0402_5%
RE91 100K_0402_5 %
RE92 100K_0402_5 %@
RE37 2.2K_0402_5%
RE43 2.2K_0402_5%
NDS3@
RE561 100K_0402_5%
RE721 2.2K_0402_5%
RE722 2.2K_0402_5%
RE723 100K_0402_5%
RE724 100K_0402_5%
RE72
RE72
RE72
RE72
RE72
RE73
RE83 1
RE12 1
RE8 10
RE21 1
RE82
@
RE35 1
RE70
RE36
RE10 1
RE11 1
RE60
RE60
1 2
RE50
7 100K_0402_5%
1 2
RE50
8 100K_0402_5%
1 2
RE82
2 100K_0402_5%
CE3 22
CE4 22
RE34
RE56 1
@
RE31
RE20 1
RE55 1
1 2
RE54
7 100K_0402_5%@
1 2
RE84 1
1 2
RE85 1
Discrete
+RTC_CE
LL_PCH
1 2
RE55
1 0_0402_5%
@
RE94
1 2
7
5_0402_5%
13
_ON
2
G
12
RE93
Comp
Comp
Comp
onday, February 25, 2019
onday, February 25, 2019
onday, February 25, 2019
D
QE12
L
2N7002WT1G_SC-70-3
S
al Electronics, Inc.
al Electronics, Inc.
al Electronics, Inc.
EC M
EC M
EC M
EC5105
EC5105
EC5105
LA-G8
LA-G8
LA-G8
1
RTCRST
1
00K_0201_5%
DELL
CONFIDENTIAL/PROPRIETARY
Titl
Titl
Titl
e
e
e
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
+3.3V_ALW
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
5 100K_0402_5%
6 100K_0402_5%
1 2
1 2
7 100K_0402_5%
1 2
8 100K_0402_5%
1 2
9 100K_0402_5%
0 100K_0402_5%
1 2
00K_0402_5%@
1 2
00K_0402_5%
1 2
0K_0402_5%
1 2
0K_0402_5%
1 2
1 100K_0402_5%
1 2
0K_0402_5%
1 2
4 10K_0402_5%
1 2
5 100K_0402_5%
1 2
00K_0402_5%
1 2
00K_0402_5%
1 2
6 100K_0402_5%
1 2
5 100K_0402_5%
1 2
1 2
1 2
2 10K_0402_5%
1 2
1 2
3
1 2
1 2
+RTC_CE
91P
91P
91P
00P_0402_50V7K
00P_0402_50V7K
0K_0402_5%
10K_
0402_5%
00K_0402_5%
00K_0402_5%
+3.3
00K_0402_5%
00K_0402_5%@
VGA_IDENTIFY
0
1UMA
LL
PCH_
RTCRST# [11,79]
58 102M
58 102M
58 102M
+RTC_CE
+3.3
V_RUN
of
of
of
V_ALW
LL
0.3
0.3
0.3
Page 59
5
4
3
2
1
For BR DSC
+RTC_CELL
100K_0402_5%
12
RE3
1
2.2U_0201_6.3V6M
12
@
CE6
CE1
9
2
100K_0402_5%
RE2
12
5
.
047U_0402_16V7K
12
9
1 2
RE33 1K_0 402_5%
RE2
6
12
10_0402_5%
CE8
L
MBT3904WT1G NPN SC70-3
C
QE4
2
B
E
3 1
QE1
1
1 3
1 2
2
G
D
POWER_SW_IN#[58,79]
LID
_CL_SIO#[58]
SIO
_SLP_S3# [11,17,59,79]
1 2
RE7
0 2.2K_04 02_5%
S
@
RE9
00_0 402_5%
2.2U_0201_6.3V6M
12
+3.3V_ALW
LID
_CL_SIO#
RE6
1 2
+3.
3V_ALW
8.2K_0402_5%
H_T
HERMTRIP#[14,23,24]
D D
C C
B B
+1.
0V_VCCST
+1.
0VS_VCCIO
@
L2N7002WT1G_SC-70-3
Thermal diode mapping
5085 Channel
DP1/DN1
DP2/DN2
DN2a/DP2a
DP3/DN3
DP4/DN4
DP4/DN4 for Skin on
100P_0402_50V8J
C
@
CE3
9
1 2
QE6, place QE6 close to
Vcore VR choke.
E
3 1
L
A A
5
Location
CPU (QE3)
M.2
DDR (QE7)
NA
CPU VR (QE6)
REM
2
B
QE6
MBT3904WT1G NPN SC70-3
REM
4
_DIODE4_P [58]
_DIODE4_N [58]
Place under CPU
Place CE35 close to the QE3 as possible
100P_0402_50V8J
C
2
CE3
B
1 2
5@
E
QE3
3 1
L
MBT3904WT1G NPN SC70-3
DP2/DN2 for WiGig on QE5, place QE5 close
to WiGig and CE37 close to QE5
DN2a/DP2a for DDR on QE7, place QE7 close
to DDR and CE46 close to QE7
100P_0402_50V8J
12
CE4
6@
100P_0402_50V8J
E
31
C
12
C
CE3
B
2
QE7
7@
E
3 1
MBT3904WT1G NPN SC70-3
L
REM
_DIODE1_P [58]
REM
_DIODE1_N [58]
2
B
QE5
L
MBT3904WT1G NPN SC70-3
LID
_CL# [64]
1
CE3
6
0.1U_0201_10V6K
2
REM
REM
CE10
@
1 2
0.1U_0201_10V6K
THE
RMTRIP2# [58]
_DIODE2_P [58]
_DIODE2_N [58]
3
POWER_SW#_ MB [66,77,79]
IMV
P_VR_ON_EC[58]
SIO
_SLP_S3#[11,17,59,79]
RF Request
+3.
3V_ALW
1
1
CE6
2
68P_0402_50V8J
RF@
RE343 CE62
240K 4700p
*
130K 4700p
62K
33K
8.2K
4.3K
2K
1K
TYP
4700p
4700p
4700p
4700p
4700p
4700p
RUN
EC_ID[58]
_ON_EC[58]
REV
Single Port ACE w/o AR
Single Port ACE w/AR
Dual Port ACE w/o AR
Dual Port ACE w/AR
Dual Port ACE (w/AR +w/o AR)
PD_ACE_DET# rise time is measured from 5%~68%.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
+3.
3V_ALW
PCIE_WAKE#_R[58]
IMV
P_VR_ON_EC
12
RE3
240K_0402_5%
12
CE6
4700P_0402_25V7K
@
Stuff RE275 and no stuff RE274 keep E5 desi gn
Stuff RE274 and no stuff RE275 to save two GPIOs on EC(PCH_PCIE_WA KE# should be output with OD)
SIO
_SLP_S3#
M
C74VHC1G08DFT2G SC70
RUN_O
N_EC
M
C74VHC1G08DFT2G SC70
43
2
12
RE275 0_0402_5%
12
@
RE3040_0402_5%
+3.3V_ALW
CE53
@
1 2
0.1U_0201_10V6K
5
1
P
B
4
O
2
A
G
UE3
3
1 2
@
RE2
12
@
RE2
+3.
3V_ALW
@
0.1U_0201_10V6K
5
1
P
B
O
2
A
G
UE5
3
BOA
RD_ID[58]
800_0402_5%
920_0402_5%
CE5
1 2
4
2
RE79 CE40
240K 4700p
130K 4700p
4700p
62K
4700p
33K
8.2K
4700p
4700p
4.3K
*
4700p
2K
4700p
1K
BOARD_ID rise time is measured from 5%~68%.
Rest=1.58K , Tp=96 degree???
Rest=1.33K , Tp=93 degree
2
VSE
T_5105
0.1U_0402_25V6
12
CE3
8
PCIE_WAKE# [52,68]
1 2
IMV
P_VR_ON
RE2740_0402_5% @
IMV
P_VR_ON [88]
PCH_PCIE_WAKE# [11,58]
UE4
1
NC
VCC
2
A
Y
3
GND
74AUP1G07GW_TSSOP5
5
4
+3.3V_ALW
VCC
ST_PWRGD [11,79]
6/8 Change to SA00007WE00 DII
RUN
_ON [17,58,78,87]
+3.
3V_ALW
12
RE3
33K_0402_5%
12
CE47RE300
240K 4700p
130K 4700p
4700p
62K
4700p33K
4700p8.2K
4.3K 4700p
4700p 15P
2K
4700p
1K
Com
Com
Com
pal Electronics, Inc.
pal Electronics, Inc.
pal Electronics, Inc.
MEC
MEC
MEC
5105 support
5105 support
5105 support
LA-G
LA-G
LA-G
891P
891P
891P
1
12
1.58K_0402_1%
+3.
3V_ALW
RE7
7
12
RE7
9
4.3K_0402_1%
12
CE4
0
4700P_0402_25V7K
REV
X00
X01
X02
X03
reserved
A00
VSE
SYS
TEM_ID[58]
*
T_5105 [58]
SYSTEM_ID rise time is measured from 5%~68%.
DEL
L CONFIDENTIAL/PROPRIETARY
Tit
Tit
Tit
le
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
00
CE4
7
4700P_0402_25V7K
PANEL SIZE
11"
12"
13"
14"
15"
17"
59 10
59 10
59 10
of
of
of
0.3
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
2Monday, February 25, 2019
Page 60
5
D D
C C
4
3
2
1
Reserve
B B
A A
DELL
CONFIDENTIAL/PROPRIETARY
Comp
Comp
al Electronics, Inc.
Titl
Titl
Titl
e
e
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
e
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
Secur
Secur
e & Reset IC
e & Reset IC
LA-G
LA-G
891P
891P
0.3
60 102M
60 102M
of
of
1
of
0.3
Page 61
5
CK14
CK15
MEM_SMBCLK
MEM_SMBDATA
PCH
D D
CM15
E11 D8
03
CN15
SML1_SMBDATA
SML1_SMBCLK
03
AY44
BB39
02
02
SML0_SMBCLK
SML0_SMBDATA
1K
1K
C12
E10
DAT_TP_SIO_I2C_CLK
CLK_TP_SIO_I2C_DAT
4
+3.3V_ALW_PCH
499
499
3
1K
1K
+3.3V_ALW_PCH
DMN66D0LDW-7
DMN66D0LDW-7
+3.3V_LAN
28
31
LOM
2.2K
2.2K
+3.3V_TP
9
TP
8
2.2K
2.2K
2
+3.3V_RUN
1
253
254
253
254
53
51
1
4
DIMMA
DIMMB
XDP
LNG2DMTR
2.2K
2.2K
B3
C C
01
01
00 D7
00
KBC
04
04
USH_EXPANDER_SMBCLK
USH_EXPANDER_SMBDAT
E5
E7
C3
UPD1_SMBCLK
UPD1_SMBDAT
B4
2.2K
2.2K
+3.3V_ALW
+3.3V_ALW
DMN66D0LDW-7
DMN66D0LDW-7
UPD
1_SMBCLK_Q
UPD1_SMBDAT_Q
@3.3K
@3.3K
11
USH
12
+3.3V_TBT_FLASH
USH/B
B5
A5
PD &
FW reflash
4.7K
+3
MEC 5105
4.7K
F7
PS8
B6
802_CSCL
PS8802_CSDA
05
05
.3V_RUN_UT9
B5
PS8
A5
802
A12
06
N10
B B
A A
5
06
07
F7
B6
07
C508
C8
08
F6
09
E9
09
10
N2
PBAT_CHARGER_SMBCLK
M3
10
PBAT_CHARGER_SMBDAT
4
2.2K
2.2K
+3.3V_ALW
100 ohm
100 ohm
Charger
7
BATTERY
6
CONN
Sec
Sec
Sec
urity Classification
urity Classification
urity Classification
Iss
Iss
Iss
ued Date
ued Date
ued Date
THI
THI
THI
S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
201
201
7/01/01
7/01/01
Com
Com
Com
pal Secret Data
pal Secret Data
pal Secret Data
Dec
Dec
Dec
iphered Date
iphered Date
iphered Date
2018/01/01
2018/01/01
2
DEL
L CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Compal Electronics, Inc.
Tit
Tit
Tit
le
le
le
SMbus Block Diagram
SMbus Block Diagram
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
LA-G891P
LA-G891P
Mon
Mon
day, February 25, 2019
day, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
1
of
61 10
of
61 10
of
2
2
0.3
0.3
Page 62
5
D D
C C
4
3
2
1
Reserve
B B
A A
DELL
CONFIDENTIAL/PROPRIETARY
Comp
Comp
al Electronics, Inc.
Titl
Titl
Titl
e
e
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
e
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
LED (
LED (
Controller)
Controller)
LA-G
LA-G
891P
891P
1
0.3
62 102M
62 102M
of
of
of
0.3
Page 63
5
Touch Pad
D D
DAT_TP_SIO_I2C_CLK[58]
CLK
_TP_SIO_I2C_DAT[58]
C C
I2C
1_SDA_TP[9]
I2C
1_SCK_TP[9]
I2C From CPU
Pl
an is for I2C to be driven by the EC for Win7 and Pre-OS (will utilize Intel I2C drivers for Win7)
For Win8.1 and 10 the EC will control TP over I2C Pre-OS and then the PCH will drive I2C when in Windows
Route PS2 from EC to the touch pad also for contingency plan if I2C has issues
10P_0402_50V8J
10P_0402_50V8J
12
12
CZ8
CZ8
0
1
+3.
3V_TP
12
4
RZ22 0_0402_5%@
RZ2
3 0_0402_5%@
RZ3
46
@
RZ3
47 0_0402_5%
@
2.2K_0402_5%
2.2K_0402_5%
12
RZ2
0
RZ2
1
12
12
12
0_0402_5%
12
0_0402_5%
+3.3V_TP
4.7K_0402_5%
12
1 2
1 2
4.7K_0402_5%
12
RZ1
RZ1
9
8
DAT_TP_SIO_R
CLK_TP_SIO_R
I2C From EC
I2C
RZ2
60_0402_5%
I2C
RZ2
9
I2C
1_SDA_TP_R
I2C
1_SCK_TP_R
1_SDA_TP_R
@
1_SCK_TP_R
@
PS2
12
3
+3.3V_RUN +3.3V_TP
PJP35
1 2
PAD-OPEN1x1m
Keyboard
KB_
DET#[12]
+3.
3V_TP
10K_0402_5%
10K_0402_5%
12
@
@
RZ1
16
RZ1
17
BC_
BC_
BC_
INT#_ECE1117[58]
DAT_ECE1117[58]
CLK_ECE1117[58]
TOU
TP_
DISABLE#[58]
+3.
3V_TP
CHPAD_INTR#[14,58]
+5V
+3.
_RUN
3V_ALW
RZ1
KB_
DET#
BC_
INT#_ECE1117
BC_
DAT_ECE1117
BC_
CLK_ECE1117
1 2
475
TP_
0_0201_5%@
DAT
CLK
I2C
1_SDA_TP_R
I2C
1_SCK_TP_R
2
DISABLE#_R
_TP_SIO_R
_TP_SIO_R
+3.3V_TP
1
CZ83
RF@
68P_0402_50V8J
2
CONN@
JKB
TP1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
GND
1
22
GND
2
HRS_TF31-20S-0P5SH-800
RF Request
KB_DET#
BC_INT#_ECE1117
BC_DAT_ECE1117
BC_CLK_ECE1117
DAT_TP_SIO_R
CLK_TP_SIO_R
+3.
+3.
3V_TP
0.1U_0201_10V6K
1
CZ9
0
2
Place close to JKBTP1
5/29
CZ84 68P_0402_50V8JRF@
CZ85 68P_0402_50V8J@RF@
CZ86 68P_0402_50V8J@RF@
CZ87 68P_0402_50V8J@RF@
CZ88 68P_0402_50V8J@RF@
CZ89 68P_0402_50V8J@RF@
@
1
1 2
1 2
1 2
1 2
1 2
1 2
3V_ALW
1
2
+5V
_RUN
0.1U_0201_10V6K
0.1U_0201_10V6K
1
@
@
CZ9
CZ9
2
1
2
Link HRS_TF31-20S-0P5SH-800 done 0313
B B
RSMRST circuit
PRO
M_BIOS_R [8]
1K_0402_5%
12
RZ4
MP
depop RZ401; MP RZ400 change to short pad
PCH
_RSMRST#[58,79]
ALW
_PWRGD_3V_5V[11,85]
A A
5
1 2
RZ4
00 10K_0402_5%
01
PRO
M_BIOS
4
+3.
3V_ALW
0.1U_0201_10V6K
5
1
P
B
O
2
A
G
3
MC74VHC1G08DFT2G SC70
CZ8
2
@
1 2
4
UZ4
1
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
PCH
_RSMRST#_AND [11,79]
3
DEL
L CONFIDENTIAL/PROPRIETARY
Com
Com
Com
pal Electronics, Inc.
pal Electronics, Inc.
Tit
Tit
Tit
le
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
pal Electronics, Inc.
Key
Key
Key
board
board
board
LA-
LA-
LA-
G891P
G891P
G891P
1
63 10
63 10
63 10
0.3
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
2Monday, February 25, 2019
of
of
of
Page 64
5
4
3
2
1
Battery LED
BAT2_LED#[58]
1 2
RZ361 470_0402_1%
BATT_WHITE#
BAT1_LED#[58]
D D
1 2
RZ28 330_0402_5%
BATT_YELLOW#
LED
P/N change to SC50000FL00 from SC50000BA00
Breath LED
+5V_
L
2N7002DW1T1G_SC88-6
QZ7A
BREA
TH_LED#[58]
C C
LED_
MASK#[51,58]
LID_
CL#[59,64]
1
2
1
+3.3
V_ALW
1 2
0
.1U_0201_10V6K
5
P
B
4
O
A
G
M
C74VHC1G08DFT2G SC70
3
@
UZ10
CZ93
2
MASK
MASK
6
_BASE_LEDS#
_BASE_LEDS#
+5V_
1 2
RZ32
ALW
BREA
TH_WHITE_LED_SNIFF#
1
K_0402_1%
LED board CONN
+3.3
V_ALW
LID_
CL#[59,64]
BATT
_WHITE#
BATT
BATT
_YELLOW#[79]
_YELLOW#
LED3
L
TW-C193DC-C_WHITE
21
Place LED3 close to SW3
CONN@
JLED
1
1
1
2
2
3
3
4
4
5
5
6
6
GND1
GND2
HRS_TF31-6S-0P5SH
HRS_TF31-6S-0P5SH
ALW
7
8
B B
LED Circuit Control Table
LED_MASK# LID_CL#
Mask All LEDs (Unobtrusive mode)
Mask Base MB LEDs (Lid Closed)
Do not Mask LEDs (Lid Opened) 11
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
0
1 0
3
X
DELL
CONFIDENTIAL/PROPRIETARY
Comp
Comp
Comp
al Electronics, Inc.
al Electronics, Inc.
Titl
Titl
Titl
e
e
e
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
2
Date: Sheet
al Electronics, Inc.
LED &
LED &
LED &
LID
LID
LID
LA-G
LA-G
LA-G
891P
891P
891P
64 102M
64 102M
64 102M
1
0.3
0.3
0.3
of
of
of
Page 65
5
D D
C C
4
3
2
1
Reserve
B B
A A
DEL
L CONFIDENTIAL/PROPRIETARY
Com
Com
pal Electronics, Inc.
Tit
Tit
Tit
le
le
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronics, Inc.
KB/
KB/
TP/LED/LID
TP/LED/LID
LA-
LA-
G891P
G891P
1
65 10
65 10
of
of
of
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
Page 66
5
4
3
2
1
For ST/Nuvoton TPM
+3.3V_ALW_PCH
+3.3V_ALW_PCH
D D
750@
750@
10
0.
1U_0201_10V6K
U_0402_6.3V6M
CZ75
1
1
2
2
place CZ50, CZ75 as close as UZ12.8 place CZ53,CZ54,CZ55 as close as UZ12.22
C C
USB2
USB2
place CZ51, CZ52 as close as UZ12.1
0_P9_FP
1 2
RZ138
0_N9_FP
1 2
RZ138
1 2
RZ351
1 2
RZ350
9 0_0201_5%@
8 0_0201_5%@
750@
10
U_0402_6.3V6M
CZ50
CZ52
1
2
0_0201_5%@
0_0201_5%@
750@
0.1U_0201_10V6K
1
CZ51
2
PCH_
SPI_CLK_R1[8]
1 2
RZ69 10K_0402_5%
PCH_
PCH_
PCH_
USB2
0_P9 [10]
USB2
0_N9 [10]
USB2
0_P9_USH [66]
USB2
0_N9_USH [66]
TPM_PIRQ#
+UZ12
_TPM
+3.3
V_ALW_UZ12
@
RZ61
SPI_CS#2[8]
SPI_D0_R1[8]
SPI_D1_R1[8]
RZ59 49
RZ58 49
RZ60 49
1 2
1 2
1 2
1 2
PLTR
0_
0402_5%
TPM_P
.9_0201_1%VPRO@
.9_0201_1%VPRO@
.9_0201_1%VPRO@
ST_TPM#[11]
PCH_
SPI_CS#2_R
IRQ#[9]
PCH_
SPI_D0_2_R
PCH_
SPI_D1_2_R
TPM_
GPIO0
PCH_
SPI_CLK_2_R
+3.3V_RUN
+3.3V_ALW
+3.3V_RUN
SIO_
SLP_S0#[9,11,17,79,87]
UZ12
8
NiC_
5
1
NiC_
1
20
SPI_
CS#
18
SPI_
PIRQ#
2
1
MOSI
2
4
MISO
6
GPIO
19
SPI_
CLK
7
PP
17
SPI_
RST#
ST
33HTPH2032AHC1_VQFN32_5X5
RZ1408
RZ1409 0_0402_5%750@
RZ89 0_0402_5%750@
RZ1410 0_0402_5%750@
1 2
RZ362 10K_0402_5%@
Link SA00009SO40 symbol done 0221
FP in PWR BUTTON connector
NEED CONFIRM MODULE PINDEFINE
JFPBT
N1
CONN@
B B
FOX_QT510166-L010-7H
Link FOX_QT510166-L010-7H done
A A
FPR_
DET#
1
1
2
2
3
3
USB2
0_P9_FP
4
4
5
5
USB2
0_N9_FP
6
6
7
7
8
8
9
9
10
FTPB
11
12
13
14
15
16
V_FPBTN
0
.1U_0201_10V6K
1
2
FPR_
FPR_
FPR_
FPR_
FPR_
@
CZ309
TN1.10
LOW_PWR_MODE#
RST#
UEFI_MGMT#
SCAN_INT#
SSO_EN#
FPR_
10
11
12
13
14
15
16
+3.3
+3.3
RST#
1
V_FPBTN
1 2
FPR_
P
AD~D
FPR_
FPR_
FPR_
+3.3
FPR_
FPR_
100K_0402_5%
RZ139
2
DET# [58]
T418
@
LOW_PWR_MODE# [58]
RST# [66]
UEFI_MGMT# [58]
V_FPBTN
SCAN_INT# [58]
SSO_EN# [58]
AZC
3
199-02SPR7G_SOT23-3
ESD@
223
DZ11
1
1
Compal
MB CONN Symbol
2
4
6
8
10
14
Signal
GND
USB DP(D+) 2
USB DM(D-)
GND
FP RESET#
+3.3V_FPBTN
FPR_SSO_EN#
FPR_SCAN_INT#
FPR Symbol
1
3
4
5RESERVED
612
7
816
915
1013 FPR_UEFI_MGMT#
1111 FPR_LOW_PWR_MODE#
9
12NA
137 NA
145 NA
3
15NA
FPR DET(GND)1 16
5
4
0_0402_5%@ST33@
1 2
1 2
1 2
7 0_0402_5%750@
+3.3
V_VPS_UZ12
TPM_
GPIO0_NU
+3.3
V_VPS_UZ12
1 2
1 0_0402_5%@
1 2
0 0_0402_5%@
QZ18
01ALT1G_SOT23-3
123
D
G
FPR_
0
.1U_0402_25V6K
12
+3.3V_VPS_UZ12
+UZ12_TPM
+3.3V_ALW_UZ12
TPM_
GPIO0
0
_0402_5%@ST33@
TPM_
S
PWR_EN#_R
RZ380
@
@
CZ200
1 2
1 2
1 2
RZ112
RZ140
22
VPS
31
NiC_
21
16
NiC_
13
27
NiC_
17
26
NiC_
16
25
NiC_
15
30
NiC_
20
29
NiC_
19
28
NiC_
18
14
NiC_
11
15
NiC_
12
13
NiC_
10
12
NiC_
9
11
NiC_
8
10
NiC_
7
5
NiC_
4
4
NiC_
3
3
NiC_
2
32
NiC_
22
23
NiC_
14
9
NC_6
2
GND0
33
THPA
D
For NPTC750
Depop RZ112, RZ1408
Pop RZ1407, RZ1409, RZ89, RZ1410, CZ50~CZ53, CZ75
PCH_
SPI_CLK_2_R
33
_0402_5%
@EMI@
RZ63
0.1U_0402_25V6
1 2
@E
12
CZ56
MI@
+3.3
V_FPBTN
RZ139
RZ139
LP23
GPIO0_NU
ST33@
0.
1U_0201_10V6K
1
CZ54
2
Close to UZ12
+3.3
V_RUN
1 2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
ST33@
10
U_0603_10V6M
1
CZ55
2
RF Request
+3.3
V_ALW
12
RF@
P_0402_50V8J
1
CZ57
2
+3.3
V_ALW
0
_0402_5%
1
2
0.
1U_0201_10V6K
1
2
750@
CZ53
68
RF@
P_0402_50V8J
CZ58
FPR_
AD~D@
PWR_EN# [58]
T422P
+3.3
V_RUN
+5V_
FPR_
DET#
1
FTPB
FPR_
LOW_PWR_MODE#
FPR_
RST#
USH_
EXPANDER_SMBCLK
USH_
EXPANDER_SMBDAT
RUN
TN1.10
FPR_
USH_
CONT
SCAN_INT#_EC[58]
PWR_STATE#[58]
+3.3V_ALW
POWE
R_SW#_MB[59,77,79]
USB2
0_N9_USH[66]
USB2
0_P9_USH[66]
ACTLESS_DET#[12]
@ESD@
DT41
1
1
2
4
5
3
A
Z1045-04F_DFN2510P10E-10-9
10
2
9
7
4
6
5
3
8
RF Request
1 2
CZ62 68
CZ63 68
1 2
2
P_0402_50V8J@RF@
P_0402_50V8J@RF@
RZ141
RZ141
@
1 2
12
RZ147
@
RZ87
DET#
1
TN1.10
LOW_PWR_MODE#
RST#
USH_EXPANDER_SMBCLK
USH_EXPANDER_SMBDAT
USH_PWR_STATE#
4 0_0402_5%@
1 0_0402_5%
USH_
USH_
1005KF-600T25RF@
1005KF-600T25RF@
0
_0402_5%
P
+5V_
1 2
RZ8 2.2K_0402_5%
1 2
RZ9 2.2K_0402_5%
1 2
RZ10 100K_0402_5%
FPR_
RST#[66]
CV2_
ON[58]
1 2
LZ4 HCB
1 2
LZ3 HCB
@
RZ114
DZ8
USH_
DET#[58]
FPR_
9
8
FTPB
FPR_
7
FPR_
6
USH CONN
CONN@
JUSH1
28
GND2
27
POWE
1 2
1 2
USB2
USB2
EXPANDER_SMBCLK[58]
EXPANDER_SMBDAT[58]
BCM58
82_ALERT#[58]
+3.3
+5V_
1 2
3 0_0402_5%@
0_
1 2
T421
@
AD~D
+5V_
ALW
1
2
ALW
68
@RF@
P_0402_50V8J
1
12
CZ69
CZ311
2
RF@
DELL
CONFIDENTIAL/PROPRIETARY
Titl
Titl
Titl
e
e
e
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
R_SW#_MB_USH
FPR_
RST#_USH
0_N8[10]
0_P8[10]
V_ALW
ALW
FPR_
SCAN_INT#_EC_R
CONT
ACTLESS_DET#_R
NFC_A
USH_
0402_5%
FPR_
UEFI_MGMT#
+3.3
V_FPBTN
FPR_
SCAN_INT#
FPR_
SSO_EN#
0.
1U_0201_10V6K
@
CZ64
+5V_
RUN
68
@RF@
P_0402_50V8J
1
12
CZ71
2
00P_0201_25V8J
1
Comp
Comp
Comp
onday, February 25, 2019
onday, February 25, 2019
onday, February 25, 2019
CTIVITY_STATUS#_R
DET#_R
@ESD@
DT42
1
1
2
2
4
4
5
5
3
3
8
A
Z1045-04F_DFN2510P10E-10-9
Close to JUSH1
+5V_
+3.3
V_RUN
1
CZ312
2
RF@
00P_0201_25V8J
1
al Electronics, Inc.
al Electronics, Inc.
al Electronics, Inc.
MEC51
MEC51
MEC51
LA-G
LA-G
LA-G
GND1
26
26
25
25
24
24
23
23
22
22
21
21
20
20
19
19
18
18
17
17
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
HRS_TF31C-26S-0P5SH-800
HRS_TF31C-26S-0P5SH-800
FPR_
9
10
+3.3
8
9
FPR_
7
7
FPR_
6
6
+3.3
V_RUN
RUN
0.
0.
1U_0201_10V6K
1U_0201_10V6K
1
1
@
CZ66
2
2
+3.3
V_ALW
68
P_0402_50V8J
1
RF@
1
12
CZ72
CZ313
2
RF@
00P_0201_25V8J
1
05 support
05 support
05 support
891P
891P
891P
68
P_0402_50V8J
66 102M
66 102M
66 102M
UEFI_MGMT#
V_FPBTN
SCAN_INT#
SSO_EN#
+3.3
V_ALW
1
@
CZ67
2
RF Request
@RF@
12
CZ73
CZ314
@RF@
of
of
of
0.
1U_0201_10V6K
@
CZ68
00P_0201_25V8J
1
0.3
0.3
0.3
Page 67
5
pin 3
pin 3
pin 3pin 3
pin 6
pin 6 pin 13
pin 13 pin 16
pin 16 pin 18
pin 6pin 6
pin 13pin 13
Pericom
Pericom
PericomPericom
*
TI
Parade
D D
SATA_PTX_DRX_P11[10]
SATA_PTX_DRX_N11[10]
SATA_PRX_DTX_N11[10]
SATA_PRX_DTX_P11[10]
Pericom PI3EQX6741ST
*
TDet_B#
GND
GND
NC
DEW2
REXT
TDet_A#
GND
B_EQ2
RN227 0_0402_5%@
1 2
CN12 0.01UF_0402_25V7K
1 2
CN13 0.01UF_0402_25V7K
1 2
CN14 0.01UF_0402_25V7K
1 2
CN15 0.01UF_0402_25V7K
TI SN75LVCP601 PD
C C
0
Main
*
Pericom
NC
1 1.5dB
0
2nd
TI
NC
1
pin 16pin 16
NC
DEW1
DEW
1 2
pin 18
pin 18pin 18
TDeT_EN
GND
A_EQ2
SATA Repeater
UN7
DEW2
DEW1
HDD_A_EQ HDD_B_EQ
HDD_A_PRE
HDD_UN7_EN_RHDD_UN7_EN
SATA_PTX_C_RD_DRX_P11
SATA_PTX_C_RD_DRX_N11
SATA_PRX_C_RD_DTX_N11
SATA_PRX_C_RD_DTX_P11
HDD_A_EQ
PIN17
PD
(RN11)
PD
(RN11)
PD
(RN11)
A_EQ
3dB
6dB
9dB
7dB
0dB
14dB 14dB
6
NC1
16
NC2
3
TDet_B#
17
A_EQ
9
A_EM
7
EN
1
AI+
2
AI-
4
BO-
5
BO+
2
1
GND
PI3EQX6741STZDEX_TQFN20_4X4
HDD_B_EQ
HDD_A_EQ2
PIN19
PIN18
PD
PD
(RN21)
(RN13)
PD
NC
(RN21)
PD
PD
(RN21)
(RN13)
B_EQ B_EM
3dB
NC
6dB
1
9dB
7dB
0
0dB
NC
1
4
+3.3V_HDD
0.1U_0201_10V6K
0.01UF_0402_25V7K
1
1
CN1
CN1
2
2
7
10
VDD1
20
VDD2
HDD_B_EQ2
13
TDet_A#
19
B_EQ
HDD_B_PRE
8
B_EM
HDD_A_EQ2
18
TDeT_EN
SATA_PTX_RD_DRX_P0
15
AO+
SATA_PTX_RD_DRX_N0
14
AO-
SATA_PRX_RD_DTX_N0
12
BI-
SATA_PRX_RD_DTX_P0
11
BI+
HDD_B_EQ2 DEW 2 HDD_A_PRE
(RN19)
(RN19)
(RN19)
DEW1
PIN16PIN13 PIN9 PIN8
PD
NC
(IPU)
PDParade PS8527C
NC
(1/2 VDD)
6
PIN6
NCNC
NC
(IPU)
PD
(RN15)
PD
(RN7)
PH
(RN6)
NC
(1/2 VDD)
A_EM
0dB0
0dB
1.5dB
0dB
-4dB
-2dB
0dB
-4dB
-2dB
HDD_DET#
HDD_B_PRE
PD
(RN9)
PH
(RN8)
NC
(1/2 VDD)
+3.3V_RUN
4.7K_0402_5%
@
RN2
26
2
G
12
HDD_UN7_EN
13
D
QN6
L2N7002W T1G_SC-70-3
S
3
2
1
For Breckenridge 12/14/15 UMA
+3.3V_HDD
@
@
4
HDD_A_PRE
HDD_B_PRE
HDD_A_EQ
HDD_B_EQ
DEW2
DEW
1
HDD
_B_EQ2
HDD
_A_EQ2
4
12
.7K_0402_5%
.7K_0402_5%
RN6
4
4
.7K_0402_5%
.7K_0402_5%
RN7
1 2
4.7K_0402_5%
4.7K_0402_5%
@
RN8
RN1
0
1 2
1 2
4.7K_0402_5%
4.7K_0402_5%
RN1
RN9
1
1 2
1 2
+3.
3V_RUN
12
4.7K_0402_5%
4.7K_0402_5%
12
12
@
@
RN1
RN1
4
2
7.87K_0402_1%
4.7K_0402_5%
@
RN1
RN1
5
3
1 2
1 2
0
1
.1U_0201_10V6K
0U_0603_10V6M
12
12
CN2
CN1
DDR
_XDP_WAN_SMBDAT[8,23,24,79]
DDR
_XDP_WAN_SMBCLK[8,23,24,79]
4.7K_0402_5%
4.7K_0402_5%
12
@
RN1
6
@
RN1
7
1 2
27P_0402_50V8J
RF@
CN7
5
12
12
@
@
RN2
RN1
0
8
4.7K_0402_5%
4.7K_0402_5%
12
12
RN1
RN2
9
1
0
.1U_0201_10V6K
12
CN3
Free Fall Sensor
LGA
1
LNG2DM
10
VDD
_IO
9
VDD
3
SDO
/SA0
4
SDA
/SDI/SDO
1
SCL
/SPC
2
CS
LNG2DMTR_LGA12_2X2
+3.3V_RUN
1
12
00K_0402_5%
RN2
6
FFS
_INT2
2
1
5
RES
12
INT
1
11
INT
2
6
GND
1
7
GND
2
8
GND
3
L2N7002DW1T1G_SC88-6
QN1
A
INT
1/IN2:Push-Pull,active high
FFS
_INT2
+5V_HDD
1
00K_0402_5%
5
12
RN1@
34
HDD
FFS
FFS_INT2_Q
L2N7002DW1T1G_SC88-6
QN1
B
_FALL_INT [9]
_INT2 [6]
EQ1EQ2 A_EMB_EQ B_EMA_EQ
(M = VDD/2)
M
0
3rd
Parade
0 0
0
M
B B
M 0
M 1
1 M
1 0
2.4dB
7.4dB
14.4dB
1
12.2dB
M
9.4dB
13.3dB
6.2dB
11.2dB
1 1
+5V_HDD source
+5V
_ALW
HDD
_EN
A A
5
5dB
1
2
3
4
@
UZ23
AOZ1
VOU
VIN
_1
VOU
VIN
_2
ON
VBI
AS
336_DFN8_2X2
2.4dB
7.4dB
14.4dB
12.2dB
9.4dB
13.3dB
6.2dB
11.2dB
5dB
T_1
T_2
CT
GND
1
GND
2
0dB
0
-3.5dB
M
-1.5dB
1
7
+5V
_HDD_UZ23
8
6
5
9
0dB
-3.5dB
-1.5dB
* red color is
current setting
Co-lay:
Short PJP32;Depop RZ102
@
RZ10
2
1 2
0.01_1206_1%
PJP
32
@JUMP@
1 2
PAD-OPEN1x1m
1 2
CZ12
9 0.1U_0201_10V6K@
1 2
CZ13
0 470P_0402_50V7K@
+5V
1.5A
_HDD
+3.
3V_HDD
HDD
0K_0402_5%
12
.01UF_0402_25V7K
12
.01UF_0402_25V7K
12
.01UF_0402_25V7K
12
.01UF_0402_25V7K
+5V
_HDD
_DEVSLP
+3.
3V_HDD
HDD
HDD
JSA
TA1
1
SAT
A_PTX_C_DRX_P0
SAT
A_PTX_C_DRX_N0
SAT
A_PRX_C_DTX_N0
SAT
A_PRX_C_DTX_P0
_DEVSLP[10]
_DET#[10]
FFS
_INT2_Q
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
GND
22
GND
23
GND
24
GND
GS12206-10100-7H
CONN@
1
2
3
4
1 2
RN3@ 1
+5V
_RUN
PAD-OPEN1x1m
+3.
3V_RUN
12
RN4
@
1
0K_0402_5%
HDD
PCH
_HDD_EN[9]
1 2
@
RZ14
8 0_0402_5%
_EN
12
RN5
@
1
0K_0402_5%
+5V
PJP
_HDD
33
12
+5V
_HDD
1
000P_0402_50V7K
CN8
12
SAT
A_PTX_RD_DRX_P0
SAT
A_PTX_RD_DRX_N0
SAT
A_PRX_RD_DTX_N0
SAT
A_PRX_RD_DTX_P0
+3.
3V_RUN
+3.
100P_0402_50V8J
0
.1U_0201_10V6K
CN9
12
12
CN7
8RF@
3V_HDD
0.1U_0201_10V6K
12
CN4 0
CN5 0
CN6 0
CN7 0
PJP
34
1 2
PAD-OPEN1x2m
12
@
CN1
0
0.1U_0201_10V6K
CN1
1
Place near HDD CONN
DEL
L CONFIDENTIAL/PROPRIETARY
Com
Com
Com
pal Electronics, Inc.
pal Electronics, Inc.
Tit
Tit
Tit
le
le
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronics, Inc.
SAT
SAT
SAT
A Repeater&HDD CONN
A Repeater&HDD CONN
A Repeater&HDD CONN
LA-
LA-
LA-
G891P
G891P
G891P
1
67 10
67 10
67 10
of
of
of
0.3
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
2Monday, February 25, 2019
Page 68
5
Add
Power Decoupling for support Intel Teton Glacier
4
3
2
1
+3.3V_HDD_M2
0
0
.01U_0402_16V7K
.1U_0402_10V7K
CN79
CN61
1
RF Request
+3.3V_HDD_M2
D D
@RF@
6
8P_0402_50V8J
1
CN60
2
1
2
12
2
+3.3V_HDD_M2
2
2U_0603_6.3V6M
CN77
0
.01U_0402_16V7K
CN80
1
2
0
0
.1U_0402_10V7K
.01U_0402_16V7K
CN86
1
CN81
1
2
12
2
2
2U_0603_6.3V6M
CN64
+3.3V_HDD_M2
0
.1U_0402_10V7K
CN62
1
2
+3.3V_HDD_M2
0
0
.01U_0402_16V7K
CN84
1
2
2
.01U_0402_16V7K
2U_0603_6.3V6M
CN63
CN82
1
12
2
2
RF@
2P_0402_50V8J
12
12
CN87
1
8
2P_0402_50V8J
RF@
RF@
00P_0402_50V8J
1
CN89
CN88
2
2.8A
+3.3
V_HDD_M2
+3.3V_SSD from SSD storage protection power gate control
+3.3V_SSD from SSD storage protection power gate control
+3.3V_SSD from SSD storage protection power gate control+3.3V_SSD from SSD storage protection power gate control
RF@
1 2
LC9 HCB1608KF-121T30
@JUMP@
PJP31
1 2
PAD-OPEN1x3m
1
2
20P_0402_50V7K
RF@
1
CN95
2
0
U_0402_25V6K
.1U_0402_10V7K
RF@
1
12
CN94
2
2
8
2P_0402_50V8J
RF@
RF@
12
CN91
RF@
2P_0402_50V8J
12
CN93
CN90
+3.3V_RUN
4
7P_0402_50V8J
RF@
1
CN92
2
2280 SSD
NGFF
PCIE
M228
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
0_PCIE_SATA#[10]
_PRX_C_DTX_N13
_PRX_C_DTX_P13
_PTX_C_DRX_N13
_PTX_C_DRX_P13
_PRX_C_DTX_N14
_PRX_C_DTX_P14
_PTX_C_DRX_N14
_PTX_C_DRX_P14
_PRX_C_DTX_N15
_PRX_C_DTX_P15
_PTX_C_DRX_N15
_PTX_C_DRX_P15
_PRX_C_DTX_P16
_PRX_C_DTX_N16
_PTX_C_DRX_N16
_PTX_C_DRX_P16
CLK_
PCIE_N2[11]
CLK_
PCIE_P2[11]
PCIE
_PRX_DTX_N13[10]
PCIE
_PRX_DTX_P13[10]
PCIE
_PTX_DRX_N13[10]
PCIE
_PTX_DRX_P13[10]
PCIE
C C
+3.3
V_HDD_M2
1 2
RN37@ 1
B B
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
PCIE
M228
0_DEVSLP
0K_0402_5%
_PRX_DTX_N14[10]
_PRX_DTX_P14[10]
_PTX_DRX_N14[10]
_PTX_DRX_P14[10]
_PRX_DTX_N15[10]
_PRX_DTX_P15[10]
_PTX_DRX_N15[10]
_PTX_DRX_P15[10]
_PRX_DTX_P16[10]
_PRX_DTX_N16[10]
_PTX_DRX_N16[10]
_PTX_DRX_P16[10]
if signal is PCIE GEN3/SATA GEN3 maybe change C value
or no need for DG0.9 SATA EXPRESS HDD
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0
_0402_5%
0
_0402_5%
0
_0402_5%
0
_0402_5%
CN65 0
CN66 0
CN67 0
CN68 0
CN69 0
CN70 0
CN71 0
CN72 0
12
RN12
7
12
RN12
8
12
.22U_0402_10V6K
12
.22U_0402_10V6K
12
RN12
5
12
RN12
6
12
.22U_0402_10V6K
12
.22U_0402_10V6K
12
RN82
12
RN81
12
.22U_0402_10V6K
12
.22U_0402_10V6K
12
RN77
12
RN78
12
.22U_0402_10V6K
12
.22U_0402_10V6K
@
@
@
@
@
@
@
@
slot C Key M
JNGF
F3
1
GND1
3
GND2
5
PERn
3
7
PERp
3
9
GND3
11
PETn
3
13
PETp
3
1
5
GND4
17
PERn
2
19
PERp
2
2
1
GND5
23
PETn
2
25
PETp
2
2
7
GND6
29
PERn
1
31
PERp
1
3
3
GND7
35
PETn
1
37
PETp
1
3
9
GND8
41
PERn
0/SATA-B+
43
PERp
0/SATA-B-
4
5
GND9
47
PETn
0/SATA-A-
49
PETp
0/SATA-A+
51
GND1
0
53
REFC
LKN
55
REFC
LKP
57
GND1
1
6
7
NC19
69
PEDE
T(NC-PCIE/GND-SATA)
71
GND1
2
73
GND1
3
75
GND1
4
77
GND1
6
79
NPTH
_2
LOTES_APCI0079-P005A
SUSC
CONN@
3P3V
AUX1
3P3V
AUX2
NC_1
NC_2
DAS/
DSS#
3P3V
AUX3
3P3V
AUX4
3P3V
AUX5
3P3V
AUX6
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_1
NC_1
DEVS
NC_1
NC_1
NC_1
NC_1
NC_1
PERS
CLKR
PEWa
NC_1
NC_1
LK(32kHz)
3P3V
AUX7
3P3V
AUX8
3P3V
AUX9
GND1
NPTH
EQ#
2.8A
2
4
6
8
NVME
PCIE
SUSC
_LED#
RN10
_WAKE#
LK_R
_0402_5%
0 0_0402_5%@
10
12
14
16
18
2
0
2
2
2
4
2
6
2
8
3
0
3
2
34
0
36
1
38
LP
40
2
42
3
44
4
46
5
48
6
50
T#
52
54
ke#
56
7
58
8
68
70
72
74
76
5
78
_1
1 2
PCIE
1 2
@
RN12
9 0_0402_5%
1 2
M228
0_DEVSLP [10]
PCH_
PLTRST#_AND [11,38,52,70]
CLKR
EQ_PCIE#2 [11]
_WAKE# [52,59]
RN990
1 2
RN13
1 0.01_0805_1%@
SSD_
SUSC
@
LK [11,52]
+3.3
SCP# [58]
V_SSD
LOTES_APCI0079-P005A
A A
DELL CONFIDENTIAL/PROPRIETARY
Comp
Comp
Comp
al Electronics, Inc.
al Electronics, Inc.
Titl
Titl
Titl
e
e
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
e
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
M2 2
M2 2
M2 2
280 Socket
280 Socket
280 Socket
LA-G
LA-G
LA-G
891P
891P
891P
0.3
0.3
68 102M
68 102M
68 102M
of
of
1
of
0.3
Page 69
5
D D
C C
4
3
2
1
Reserve
B B
A A
DEL
L CONFIDENTIAL/PROPRIETARY
Com
Com
pal Electronics, Inc.
Tit
Tit
Tit
le
le
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronics, Inc.
eMM
eMM
C/UFS
C/UFS
LA-
LA-
G891P
G891P
1
69 10
69 10
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
of
of
of
Page 70
5
4
3
2
1
+3.3V_MMI_AUX+3.3V_MMI_IN
RR20
MEDIACARD_IRQ#
12
0K_0402_5%
PCH_
CLKR
1 2
1 2
1 2
1 2
0.
1U_0201_10V6K
1
1
CR6
2
2
V_RUN_CARD
2
CR17
1
+3.3V_MMI_IN+3.3V_RUN
@
PLTRST#_AND[11,38,52,68]
EQ_PCIE#4[11]
CLK_
CLK_
.1U_0402_25V6
.1U_0402_25V6
.1U_0402_25V6
.1U_0402_25V6
MEDI
ACARD_IRQ#[8]
0.
1U_0201_10V6K
CR7
1 2
.1U_0201_10V6K
0
support D3 Hot(if D3 cold PIN11,PIN27 need Add MOS on/off 3V3AUX)
PCIE_P4[11]
PCIE_N4[11]
+1.8
CR18
0U_0402_6.3V6M
1
7/18
Vender suggest.
PCIE
PCIE
PCIE
PCIE
V_RUN_CARD
+1.8
V_RUN_CARD
_PTX_C_DRX_P8
_PTX_C_DRX_N8
_PRX_C_DTX_P8
_PRX_C_DTX_N8
SD/M
MCCD#
+RRE
12
RR4
2
CR19
1 2
1
.1U_0201_10V6K
0
1
2
1
2
5
6
3
4
7
8
32
31
30
1
0
14
13
9
F
2K_0402_1%
6.
CR20
0U_0402_6.3V6M
1
+3.3V_MMI_AUX
0.
4.
7U_0402_6.3V6M
1U_0201_10V6K
1
CR1
CR2
2
UR1
PERS
T#
CLK_
REQ#
REFC
LKP
REFC
LKN
HSIP
HSIN
HSOP
HSON
WAKE
#
MS_I
NS#
SD_C
D#
AV12
DV12
S
SD_V
DD2
RREF
11
27
ux
3V3a
RTS5242
D
E-PA
33
IN
3V3_
+3.3V_MMI_IN
0.
1U_0201_10V6K
1
CR3
2
CARD
DV33
SD_L
N1_P
SD_L
N1_M
SD_L
N0_P
SD_L
N0_M
SDRE
GPIO
RT
S5242-GR_QFN32_4X4
_3V3
SP1
SP2
SP3
SP4
SP5
SP6
SP7
_18
G2
10
U_0402_6.3V6M
CR4
1
2
12
18
15
16
17
19
20
21
29
22
23
26
25
24
2
8
+3.3
+1.8
+DV3
3_18
SD/M
MCDAT1/RCLK-
SD/M
MCDAT0/RCLK+
SD/M
MCCLK
SD/M
MCCMD
SD/M
MCDAT3
SD/M
MCDAT2
SDWP
SD_U
HS2_D1P
SD_U
HS2_D1N
SD_U
HS2_D0P
SD_U
HS2_D0N
+SDR
EG2
SD_G
PIO
K_0402_5%
V_RUN_CARD
V_RUN_CARD
+3.3
V_RUN_CARD
@
@
@EMI
@
@
@
@
7/18 Vender suggest
1 2
CR15
1
U_0201_6.3V6M
12
RR310
SD/M
SD/M
SD/M
SD/M
SD/M
SD/M
SD/M
SD_U
SD_U
SD_U
SD_U
1 2
RR9
1 2
RR10
1 2
RR5
1 2
RR6
1 2
RR7
1 2
RR8
+3.3
MCCMD_R
MCCLK_R
MCCD#
MCDAT0/RCLK+_R
MCDAT1/RCLK-_R
MCDAT2_R
MCDAT3_R
HS2_D0P
HS2_D0N
HS2_D1P
HS2_D1N
For PCIE Interface
1 2
CR22
1U_0201_6.3V6M
SD/M
MCDAT1/RCLK-_R
SD/M
0_
0
0_
0_
0_
0_
V_MMI_AUX
0402_5%
_0402_5%
0402_5%
0402_5%
0402_5%
0402_5%
MCDAT0/RCLK+_R
SD/M
MCCLK_R
SD/M
MCCMD_R
SD/M
MCDAT3_R
SD/M
MCDAT2_R
JSD1
CONN@
4
VDD1
1
5
VDD2
3
CMD
5
CLK
9
CD
1
6
SWIO
7
DAT0
/RCLK+
8
DAT1
/RCLK-
1
DAT2
2
CD/D
AT3
18
D0+
19
D0-
22
D1+
21
D1-
24
NPTH
1
6
VSS1
1
7
VSS2
2
0
VSS3
2
3
VSS4
T
-SOL_158-1240902600
@
EMI@
5P_0402_50V8C
12
CR21
EMI depop location
NPTH
GND1
GND2
GND3
GND4
GND5
25
2
1
0
1
1
1
2
1
3
1
4
PJP14
1 2
PAD-OPEN1x1m
1 2
0_0603_5%
RR19 1
CR11 0
CR12 0
CR13 0
CR14 0
+1.2
V_LDO
4.
7U_0402_6.3V6M
CR5
12
+3.3
82P_0201_50V8J
1
2
_SD_WP#[12]
RF Request
+3.3V_MMI_IN
@RF@
CR28
SDWP
@RF@
8
1
2P_0201_50V8J
2P_0201_50V8J
1
1
CR25
2
2
QR1
L2
N7002W T1G_SC-70-3
1 3
D
G
2
@RF@
CR26
S
+3.3V_MMI_AUX
PCIE
_PTX_DRX_P8[10]
PCIE
_PTX_DRX_N8[10]
PCIE
_PRX_DTX_P8[10]
PCIE
_PRX_DTX_N8[10]
+3.3V_MMI_AUX
D D
C C
B B
@RF@
1
2P_0201_50V8J
1
CR27
2
HOST
CR38,CR39 near JSD1.4 CR40,CR41 near JSD1.14
A A
DELL
CONFIDENTIAL/PROPRIETARY
Comp
Comp
Comp
al Electronics, Inc.
al Electronics, Inc.
Titl
Titl
Titl
e
e
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
e
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
Card
Card
Card
Reader RTS5242
Reader RTS5242
Reader RTS5242
LA-G
LA-G
LA-G
891P
891P
891P
0.3
0.3
70 102M
70 102M
70 102M
of
of
1
of
0.3
Page 71
5
D D
C C
+5V
B B
_ALW
RI1
3
USB3_PRX_DTX_N2[10]
USB3_PRX_DTX_P2[10]
USB3_PTX_DRX_N2[10]
USB3_PTX_DRX_P2[10]
ILI
M_SEL
12
10K_0402_5%
CI13 0.1U_0402_25V6
CI16 0.1U_0402_25V6
USB
_POWERSHARE_VBUS_EN[58]
USB
_POWERSHARE_EN#[58]
USB
USB
USB
4
ESD@
USB3_PRX_DTX_N2 USB3_PRX_DTX_N2
USB3_PRX_DTX_P2
12
12
20_N2[10]
20_P2[10]
_OC0#[10]
USB3_PTX_C_DRX_N2
USB3_PTX_C_DRX_P2
+5V
_ALW
ILI
M_SEL
DI4
1
1
2
2
4
4
5
5
3
3
8
AZ1045-04F_DFN2510P10E-10-9
UI3
1
VIN
2
DM_
OUT
3
DP_
OUT
13
FAU
LT#
4
ILI
M_SEL
5
EN
6
CTL
1
7
CTL
2
8
CTL
3
The
S
LGC55544CVTR_TQFN16_3X3
10
9
7
6
VOU
DP_
DM_
ILI
M_L
ILI
M_HI
GND
rmal Pad
9
8
7
6
T
IN
IN
NC
3
USB3_PRX_DTX_P2
USB3_PTX_C_DRX_N2
USB3_PTX_C_DRX_P2
+5V
_USB_CHG_PWR
12
SW_
USB20_P2
10
SW_
USB20_N2
11
15
16
RI1
4
9
1
4
17
SW_
USB20_N2
SW_
USB20_P2
12
22.1K_0402_1%
+5V_USB_CHG_PWR
150U_B2_6.3VM_R35M
@
1
CI3
+
2
2
LI7
EMI@
1
1
4
4
D
LM0NSN900HY2D_4P
2
A
ZC199-02SPR7G_SOT23-3
ESD@
223
DI5
USB20_N2_R
USB20_P2_R
USB3_PRX_DTX_N2
USB3_PRX_DTX_P2
USB3_PTX_C_DRX_N2
USB3_PTX_C_DRX_P2
100U_A_6.3VM_R70M
0.1U_0201_10V6K
CI1
1
+
2
2
3
CI1
1
4
7
USB
USB
3
1
1
20_N2_R
20_P2_R
2
2
3
1
JUSB1
1
VBUS
2
D-
3
D+
4
GND1
5
STDA_SSRX-
6
STDA_SSRX+
7
GND_DRAIN
8
STDA_SSTX-
9
STDA_SSTX+
C-K_26230A-8K1A-02~D
CONN@
GND2
GND3
GND4
GND5
C-K_26230A-8K1A-02~D
RF Request
+5V
_USB_CHG_PWR
12P_0402_50V8J
RF@
68P_0402_50V8J
1
2
RF@
1
CI4
CI4
3
4
2
10
11
12
13
Link Seligro SA000097E10 Done
MAIN:SLGC55544CVTR
+5V
_ALW
47U_0603_6.3V6M
47U_0603_6.3V6M
@
1
1
CI3
4
2
2
A A
5
@
CI3
3
Pla
4
100P_0402_50V8J
1
2
ce near UI3.1
0.1U_0201_10V6K
RF@
CI1
1
CI3
9
1
2
DEL
L CONFIDENTIAL/PROPRIETARY
Com
Com
Com
pal Electronics, Inc.
pal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Tit
Tit
Tit
le
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronics, Inc.
JUSB
JUSB
JUSB
1+PS
1+PS
1+PS
LA-
LA-
LA-
G891P
G891P
G891P
1
71 10
71 10
71 10
0.3
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
2Monday, February 25, 2019
of
of
of
Page 72
5
4
3
2
1
ESD@
USB3_PRX_DTX_N3[10]
USB3_PRX_DTX_P3[10]
USB3_PTX_DRX_N3[10]
D D
C C
USB3
USB3
USB3
USB3
B B
USB3_PTX_DRX_P3[10]
_PRX_DTX_N4[10]
_PRX_DTX_P4[10]
_PTX_DRX_N4[10]
_PTX_DRX_P4[10]
12
CI27 0
12
CI28 0
.1U_0402_25V6
.1U_0402_25V6
12
CI5 0.1U_0402_25V6
12
CI4 0.1U_0402_25V6
USB2
USB2
USB3
_PRX_DTX_N4
USB3
_PRX_DTX_P4
USB3
_PTX_C_DRX_N4
USB3
_PTX_C_DRX_P4
0_P3[10]
0_N3[10]
USB3_PRX_DTX_N3 USB3_PRX_DTX_N3
USB3_PRX_DTX_P3 USB3_PRX_DTX_P3
USB3_PTX_C_DRX_N3 USB3_PTX_C_DRX_N3
USB3_PTX_C_DRX_P3 USB3_PTX_C_DRX_P3
USB2
0_P3
USB2
0_N3
DFB
request:
main SM070003Z00 (INPAQ_MCM1012B900F06BP_4P)
Footprint use 2nd source SM070004400 (PANAS_EXC24CQ900U_4P)
Pitch change from 0.5mm to 0.55mm
ESD@
DI6
1
1
2
2
4
4
5
5
3
3
8
AZ
1045-04F_DFN2510P10E-10-9
DI1
1
1
2
2
4
4
5
5
3
3
8
AZ1045-04F_DFN2510P10E-10-9
LI3
EMI@
1
1
4
4
DL
9
10
8
9
7
7
6
6
2
3
M0NSN900HY2D_4P
USB3
_PRX_DTX_N4
USB3
_PRX_DTX_P4
USB3
_PTX_C_DRX_N4
USB3
_PTX_C_DRX_P4
9
10
8
9
7
7
6
6
USB2
USB2
0_P3_R
0_N3_R
RF Request
+USB
1
2
_EX3_PW R
1
RF@
2P_0402_50V8J
CI47
1
2
2
3
6
8P_0402_50V8J
RF@
1
CI48
2
RF Request
+USB_EX2_PWR
1
RF@
8P_0402_50V8J
1
CI50
2
RF@
RF@
1
6
2P_0402_50V8J
8P_0402_50V8J
1
1
CI45
+5V_
RF@
CI51
12
12
ALW
CI46
2
10
U_0603_10V6M
@
1
CI6
2
2
RF@
7P_0402_50V8J
CI52
2
1
00P_0402_50V8J
+USB_EX2_PWR
JUSB2
150U_B2_6.3VM_R35M
@
1
1
CI10
+
+
3
2
2
0.
1U_0201_10V6K
CI7
+USB
_EX3_PWR
150U_B2_6.3VM_R35M
@
1
1
CI10
+
+
4
2
2
0.
10
1U_0201_10V6K
0U_A_6.3VM_R70M
10
0U_A_6.3VM_R70M
CI3
CI1
1
2
223
1
USB_
PWR_EN1#[58]
0
.1U_0201_10V6K
CI8
CI10
1
2
223
1
AZ
C199-02SPR7G_SOT23-3
3
ESD@
DI2
1
AZ
C199-02SPR7G_SOT23-3
3
ESD@
DI3
1
USB20_N3_R
USB20_P3_R
USB3_PRX_DTX_N3
USB3_PRX_DTX_P3
USB3_PTX_C_DRX_N3
USB3_PTX_C_DRX_P3
UI1
5
IN
4
EN
SY
6288D20AAC_SOT23-5
USB2
0_N4_R
USB2
0_P4_R
USB3
_PRX_DTX_N4
USB3
_PRX_DTX_P4
USB3
_PTX_C_DRX_N4
USB3
_PTX_C_DRX_P4
1
VBUS
2
D-
3
D+
4
GND1
5
STDA_SSRX-
6
STDA_SSRX+
7
GND_DRAIN
8
STDA_SSTX-
9
STDA_SSTX+
C-K_26230A-8K1A-02~D
C-K_26230A-8K1A-02~D
+USB
_EX2_PWR
1
OUT
2
GND
3
OCB
JUSB
1
VBUS
2
D-
3
D+
4
GND1
5
STDA
6
STDA
7
GND_
8
STDA
9
STDA
C-K_26230A-8K1A-02~D
C-K_26230A-8K1A-02~D
3
_SSRXÂ_SSRX+
DRAIN
_SSTXÂ_SSTX+
USB_
CONN@
GND2
GND3
GND4
GND5
CONN@
GND2
GND3
GND4
GND5
10
11
12
13
OC1# [10]
1
0
1
1
1
2
1
3
+USB
1
OUT
2
GND
3
OCB
onday, February 25, 2019
onday, February 25, 2019
onday, February 25, 2019
_EX3_PWR
USB_
Comp
Comp
Comp
OC2# [10]
al Electronics, Inc.
al Electronics, Inc.
al Electronics, Inc.
JUSB2
JUSB2
JUSB2
&JUSB3
&JUSB3
&JUSB3
LA-G
LA-G
LA-G
891P
891P
891P
72 102M
72 102M
72 102M
1
0.3
0.3
0.3
of
of
of
LI4
USB2
USB2
0_N4
0_P4
4
USB2
0_N4[10]
USB2
0_P4[10]
A A
5
EMI@
1
1
4
4
DL
M0NSN900HY2D_4P
USB2
USB2
0_N4_R
0_P4_R
+5V_
ALW
1
0
0U_0603_10V6M
.1U_0201_10V6K
@
CI11
CI12
1
12
2
3
USB_
PWR_EN2#[58]
2
2
2
3
3
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
UI2
5
IN
4
EN
SY
6288D20AAC_SOT23-5
DELL
CONFIDENTIAL/PROPRIETARY
Titl
Titl
Titl
e
e
e
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Page 73
5
D D
C C
4
3
2
1
Reserve
B B
A A
DEL
L CONFIDENTIAL/PROPRIETARY
Com
Com
pal Electronics, Inc.
Tit
Tit
Tit
le
le
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronics, Inc.
USB2
USB2
/USB3 DB
/USB3 DB
LA-
LA-
G891P
G891P
1
73 10
73 10
of
of
of
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
Page 74
5
D D
C C
4
3
2
1
Reserve
B B
A A
DELL
CONFIDENTIAL/PROPRIETARY
Comp
Comp
al Electronics, Inc.
Titl
Titl
Titl
e
e
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
e
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
Dock
Dock
LA-G
LA-G
891P
891P
74 102M
74 102M
1
0.3
0.3
of
of
of
Page 75
5
D D
C C
4
3
2
1
Reserve
B B
A A
DEL
L CONFIDENTIAL/PROPRIETARY
Com
Com
pal Electronics, Inc.
Tit
Tit
Tit
le
le
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronics, Inc.
USB
USB
LA-
LA-
G891P
G891P
1
75 10
75 10
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
of
of
of
Page 76
5
D D
C C
4
3
2
1
Reserve
B B
A A
DELL
CONFIDENTIAL/PROPRIETARY
Comp
Comp
al Electronics, Inc.
Titl
Titl
Titl
e
e
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
e
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
USB
USB
LA-G
LA-G
891P
891P
76 102M
76 102M
1
0.3
0.3
of
of
of
Page 77
+3.3V_RUN
5
4
3
2
1
1 2
RE48 10K_0402_5%
1 2
RE51 10K_0402_5%
D D
JFAN1
1
2
3
4
GND
1
GND
ACES_50271-0040N-001
2
CONN@
PWM_FAN1
TACH_FAN1
1
ESD@
DE22
CEST523NC5VB_SOT-523-3
Near JFAN1
2
1
2
3
4
5
6
3
PWM
_FAN1
TAC
H_FAN1
10U_0402_6.3V6M
12
CE3
2
2 1
PWM
TAC
+5V
_RUN
@
DE1
BZV
55-B5V6_SOD80C2
_FAN1 [58]
H_FAN1 [58]
Link 50271-0040N-001 DONE
JFAN1 fan follow X9 project PIN DEFINE
C C
POWER & INSTANT ON SWITCH
TOP
POW
SW3
ER_SW#_MB[59,66,79]
2
4
S
KRBAAE010_4P
1
3
Fiducial Mark
FD1@
B B
A A
1
F
IDUCIAL MARK~D
FD2@
1
F
IDUCIAL MARK~D
FD3@
1
F
IDUCIAL MARK~D
FD4@
1
F
IDUCIAL MARK~D
EDP Standoff
H12
H11
H
H
_3P3
_3P3
1
1
FAN Standoff
H26@
H25@
H
H
_4P0
_4P0
1
1
H27@
H
_3P1X2P1N
1
CPU
H4@
H_
H14@
_4P0
H3@
H2@
4P0
1
1
H_
H_
4P0
4P0
1
1
H29@
H28@
H
H
_4P0
_4P0
1
H15
H16@
H
H
_3P3
_2P6
1
1
H30@
H
_2P6
1
H17
H
H
_3P8
1
H1@
H_
4P0
1
H13@
H
H
_3P0
1
5
1
H18@
_2P6
1
NGFF Standoff
H20@
H
_2P6
1
H_
H
H7
3P2
1
H21@
_2P1N
1
H8
H_
3P2
1
DEL
L CONFIDENTIAL/PROPRIETARY
Com
Com
Com
pal Electronics, Inc.
pal Electronics, Inc.
H22@
H
_5P0N
1
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Tit
Tit
Tit
le
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronics, Inc.
PAD,
PAD,
PAD,
LED
LED
LED
LA-
LA-
LA-
G891P
G891P
G891P
1
77 10
77 10
77 10
0.3
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
2Monday, February 25, 2019
of
of
of
Page 78
5
4
3
2
1
+3.3V_WWAN/+3.3V_LAN source
+3.3V_ALW
3.3V_WWAN_EN[58]
SIO_SLP_LAN#[11]
3.3V_WWAN_EN
+5V_ALW
3.3V_WWAN_EN
0.1U_0402_25V6
RF@
1
12
CZ320
2
D D
1 2
RZ40 100K_0402_5%
RF@
1U_0402_25V6K
CZ321
EM5209VF_SON14_2X3
6
5
4
3
2
1
100P_0402_50V8J
R
F@
12
CZ322
VIN2_27VOUT2_2
VIN2_1
VOUT2_1
ON2
VBIAS
ON1
VIN1_2
VOUT1_2
VIN1_1
VOUT1_1
UZ43
GPAD
GND
15
+3.3V_LAN_UZ43
8
9
10
CT2
11
12
CT1
13
14
+3.3V_WWAN_UZ43
+3.3V_ALW_PCH/+3.3V_RUN source
+3.3
V_ALW
UZ3
1
VIN1
VOUT
_1
2
VIN1
VOUT
0_
1 2
+5V_
RUN_
ALW
0402_5%
ON
@
PCH_
PRIM_EN[11,87]
C C
RZ64
3
ON1
4
VBIA
5
ON2
6
VIN2
7
VIN2
EM5
209VF_SON14_2X3
_2
S
VOUT
_1
VOUT
_2
GND
GPAD
+3.3
14
1_1
13
1_2
12
CT1
11
10
CT2
9
2_1
8
2_2
1
5
RF@
1 2
LC10 HCB1608KF-121T30
@JUMP@
1 2
PAD-OPEN1x1m
1 2
CZ310 0.1U_0201_10V6K
1 2
CZ110 470P_0402_50V7K
1 2
CZ109 470P_0402_50V7K
CZ119 0.1U_0201_10V6K
PJP41
1 2
PAD-OPEN1x3m
V_ALW_PCH_U44
+3.3
V_RUN_UZ44
@JUMP@
3.435A
PJP37
1 2
PJP3
1 2
PAD-OPEN1x1m
1 2
CZ316
1 2
CZ112
1 2
CZ113
1 2
CZ114
1 2
CZ115
1 2
CZ315
PJP3
1 2
PAD-OPEN1x3m
1 2
LC8 H
RF@
1 2
LC12
RF@
1A
+3.3V_LAN
+3.3V_WWAN
2.5A
0.63A
8
+3.3
V_ALW_PCH
100P_0402_50V8JRF@
0.1U_0201_10V6K
100P_0402_50V8J
1000P_0402_50V7K
0.1U_0201_10V6K
100P_0402_50V8JRF@
9
+3.3
CB1608KF-121T30
HCB1608KF-121T30
V_RUN
+3.3V_WWAN_UZ43
1
RF@
2200P_0402_50V7K
2
RF Request
CZ124
+1.8V_RUN source
1 2
RZ345
@
Reserve R/C for Audio power sequence, +5V->+3.3V->+1.8V
Reserve for SSD storage protection power gate control
Reserve for SSD storage protection power gate control
Reserve for SSD storage protection power gate control Reserve for SSD storage protection power gate control
1
2
RZ147
2
@
100K_0402_5%
1 2
SSD_
SCP_PWR_EN_D
RUN_
RUN_ON[17,58,59,78,87]
ON[17,58,59,78,87]
+3.3
INB
INA
1 2
RZ147
0_0402_5%
V_ALW
5
P
G
3
1 0_0201_5%@
+1.8V_PRIM
RUN_ON_1.8V
+5V_ALW
12
CZ197
@
470P_0402_50V7K
+3.3
UZ54
@
MC
74VHC1G32DFT2G_SC70-5~D
4
O
EC +1.8V to +3.3V Level Shift
EC +1.8V to +3.3V Level Shift
EC +1.8V to +3.3V Level ShiftEC +1.8V to +3.3V Level Shift
SSD_
+5V_
ALW
+3.3
V_ALW
UZ8
1
VIN1
2
VIN2
3
ON
4
VBIAS
AOZ1336_DFN8_2X2
V_ALW
1
2
EN
3
4
+1.8
V_PRIM
VOUT1
VOUT2
UZ53@
VIN1
VIN2
ON
VBIA
AOZ13
GND1
GND2
7
8
6
CT
5
9
VOUT
VOUT
CT
S
GND1
GND2
36_DFN8_2X2
+1.8V_RUN_UZ46
7
1
8
2
6
5
9
0.013A
PJP42
1 2
PAD-OPEN1x1m
1 2
CZ120 0.1U_0201_10V6K
1 2
CZ121 470P_0402_50V7K
CZ305
CZ306
+3.3
1 2
1 2
+1.8V_RUN
V_SSD
0.1U_0201_10V6K@
470P_0402_50V7K@
+5V_RUN/+3.3V_WLAN source
RZ147
4
@
100K_0402_5%
+3.3
V_ALW
12
2
1 3
D
QZ15
1 2
1
00K_0402_5%
RZ518
G
S
SSD_
+5V_
ALW
UZ47
1
VIN1
VOUT
_1
2
VIN1
VOUT
B B
RZ38 10
A A
1 2
RUN_
WLAN
0K_0402_5%
ON[17,58,59,78,87]
_PWR_EN
WLAN
_PWR_EN
+3.3
V_ALW
+3.3
3
ON1
4
VBIA
5
ON2
6
VIN2
7
VIN2
EM
V_WLAN_UZ47
_2
S
VOUT
_1
VOUT
_2
5209VF_DFN14_3X2
1 2
PAD-OPEN1x2m
GPAD
PJP3
GND
+5V_
RUN_UZ47
14
1_1
13
1_2
12
CT1
11
10
CT2
+3.3
V_WLAN_UZ47
9
2_1
8
2_2
1
5
6
+3.3
V_WLAN
1 2
CZ116
CZ117
CZ118
CZ122
@
1 2
0.
01_1206_1%
PAD-OPEN1x2m
1 2
1 2
1 2
1 2
RZ96
0.1U_0201_10V6K
470P_0402_50V7K
470P_0402_50V7K
0.1U_0201_10V6K
2A
+5V_
1
2
RUN
+3.3
V_WLAN
2
4
RF@
RF@
.2P_0402_50V8C
7P_0402_50V8J
0
RF@
.1U_0402_25V6
1
1
CZ319
CZ318
CZ317
2
2
SLP_
WLAN#_GATE[58]
SIO_
SLP_WLAN#[11]
3.076A
PJP4
0
SCP_PWR_EN_D
BS
S138W-7-F_SOT323-3
AUX_
EN_WOWL[58]
EC request to reserve OR gate for WLAN power enable
SLP_
WLAN#_M
2
G
1 3
D
S
QZ22
@
BS
S138W-7-F_SOT323-3
+3.3
V_ALW_PCH
SSD_
2
12
0K_0402_5%
@
SCP_PWR_EN
RZ379
RZ71 0_
3
2
BAT
54CW_SOT 323-3
@
RZ70 0_
+3.3
V_ALW
12
1 2
DZ9
1 2
SSD_
SCP_PWR_EN [58]
20K_0402_5%
RZ148
3
0402_5%@
1
0402_5%
WLAN
_PWR_EN
DELL
CONFIDENTIAL/PROPRIETARY
Comp
Comp
Comp
al Electronics, Inc.
al Electronics, Inc.
Titl
Titl
Title
e
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
e
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
Powe
Powe
Powe
r control
r control
r control
LA-G
LA-G
LA-G
891P
891P
891P
78 102M
78 102M
1
78 102M
0.3
0.3
0.3
of
of
of
Page 79
5
+3.3V_ALW_PCH
SIO_SLP_S3#[11,17,59]
+3.3V_ALW
SIO_SLP_S5#[11]
SIO_SLP_S4#[11,17,86,87]
SIO_SLP_A#[11]
+3.3V_ALW
PCH_RTCRST#[11,58]
POWER_SW#_MB[59,66,77]
SYS_RESET#[11]
1 2
RC2
16 0_0603_5%@
+1.
0V_PRIM_XDP
0.1U_0201_10V6K
0.1U_0201_10V6K
@
@
CC2
CC2
1
99
88
2
VCC
ST_PWRGD[11,59]
PCH
_RSMRST#_AND[11,63]
12
ESD
request,Place near JXDP1 side.
+1.
0VS_VCCIO
RC1
+1.
0V_VCCST
RC2
RC2
+3.
3V_RUN
0V_PRIM_XDP
RC1
SIO_SLP_S0#[9,11,17,66,87]
JXT_FP241AH-010GAAM LINK DONE
XDP
_OBS0_R[14]
XDP
_OBS1_R[14]
TDO
_XDP
0.1U_0402_25V6
@ESD@
CC3
06
32 150_0402_5%
35 150_0402_5%@
36 10K_0402_5%@
RC1
37 3K_0402_5%
38 51_0402_5%@
D D
C C
+1.
0V_PRIM
1
2
Place near
JXDP1
B B
A A
+1.
SIO_SLP_S3#
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_A#
PCH_RTCRST#
SYS_RESET#
SIO_SLP_S0#
11
GND
1
12
GND
2
JXT_FP241AH-010GAAM
CONN@
+1.
0V_PRIM_XDP
XDP
_OBS0_R
XDP
_OBS1_R
RC5 need to close to JCPU1
RC1
23 1K_0402_5%@
RC1
24
PCH
_SPI_DO_XDP[8]
SYS
_PWROK[11,58]
FIV
R_EN_R
12
FIV
R_EN
12
FIV
R_EN
12
XDP
_DBRESET#
12
CPU
_XDP_PREQ#
12
5
JDE
G1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
1 2
1 2
FIV
R_EN
CFG0
H_V
0.1U_0402_25V6
12
JAPS1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
GND1
20
GND2
CONN@
ACES_50506-01841-P01
10K_0402_5%
12
12
1
RE7
_DEBUG_VCC
JTA
G_TDI
JTA
G_TMS
JTA
G_CLK
JTA
G_TDO
10_0402_1%
DEB
UG_TX
+EC
CPU XDP conn
CPU
_XDP_PREQ#[14]
CPU
_XDP_PRDY#[14]
1 2
RC2
39 0_0402_5%@
1 2
RC2
40 0_0402_5%@
1K_0402_5%
1 2
RC2
17 0_0402_5%@
1 2
RC1
26 1K_0402_5%@
1 2
RC1
28 0_0402_5%@
1 2
RC1
29 0_0402_5%@
DDR
_XDP_WAN_SMBDAT[8,23,24,67]
DDR
_XDP_WAN_SMBCLK[8,23,24,67]
PCH
_JTAG_TCK[14]
CPU
CCST_PWRGD_XDP
@ESD@
CC307
_XDP_TCLK[14]
+3.
3V_ALW_PCH
33
RC1
1.5K_0402_5%
1 2
CXDP@
PCH
_SPI_DO_XDP
RES
ET_OUT#_R
0.1U_0402_25V6
12
CC3
34@
Place near JXDP1.47
11
GND1
12
GND2
JXT_FP241AH-010GAAM
CONN@
10K_0402_5%
10K_0402_5%
12
12
RE7
RE7
RE7
15
20
14
MSCL
K
MSDA
TA
HOS
T_DEBUG_TX
SBI
1 2
@
RE3
0 0_0402_5%
+1.
CPU
_XDP_PREQ#
CPU
_XDP_PRDY#
CFG
0
CFG
1
CFG
2
CFG
3
XDP
_OBS0
XDP
_OBS1
CFG
4
CFG
5
CFG
6
CFG
7
H_V
CCST_PWRGD_XDP
SIO
_PWRBTN#[11,58]
FIV
R_EN_R
RES
ET_OUT#_R
PCH
_JTAG_TCK
CPU
_XDP_TCLK
CPU
_XDP_TMS
RC1
CPU
_XDP_TDI
RC1
CPU
_XDP_TDO
RC1
CPU
_XDP_TRST#
RC1
CPU
_XDP_TCLK
RC1
Place near JXDP1.48
JESPI
1
2
3
4
5
6
7
8
9
10
12
OS_TX[6]
HOS
MSDA
MSCL
0V_PRIM_XDP
31 51_0402_5%@
34 51_0402_5%@
35 100_0402_5%
36@ 51_0402_5%
39 51_0402_5%
XDP
4
+3.3V_RUN
1
2
3
4
5
6
7
ESPI_RESET#_R ESPI_RESET#
8
9
10
1 2
RE560 0_0402_5%
@
JXT_FP241AH-010GAAM LINK DONE
+3.3V_ALW
10K_0402_5%
RE7
19
JTA
G_TDI [58]
JTA
G_TMS [58]
JTA
G_CLK [58]
JTA
G_TDO [58]
T_DEBUG_TX [58]
TA [58]
K [58]
CFG
[0..19][13]
XDP
_PRSNT_PIN1
RC1
JXD
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
61
6
2
JXT_FP270H-061G1AM
Link FP270H-061G1AM done 0131
1 2
1 2
1 2
1 2
1 2
_DBRESET#
0.1U_0402_25V6
12
4
1 2
RE3
@
0_0402_5%
1 2
21 0_0402_5%@
1 2
RC1
22 0_0402_5%@
CON
P1
112
334
556
778
9910
111112
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
595960
61
GND
+1.
0V_VCCSTG
@CXDP@
CC3
26
GND
10K_0402_5%
10K_0402_5%
12
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
6
3
PCH
PCH
PCH
12
RE7
3
CFG3
_JTAG_TDI
_JTAG_TDO
_JTAG_TMS
RE7
4
100K_0402_5%
12
RE7
5@
RE8
6
10K_0402_5%
1 2
+1.
0V_PRIM_XDP
1 2
RC5
69 51_0402_5%
1 2
RC5
68 100_0402_5%
1 2
RC1
30 51_0402_5%
10K_0402_5%
12
RE7
2
06
N@
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
Place near JXDP1.41
CFG
CFG
CFG
CFG
CFG
CFG
CFG
CFG
CFG
CFG
CFG
CFG
ITP
XDP
TDO
TRS
TDI
XDP
_PMODE
_DBRESET#
_XDP
T#_XDP
_XDP
_TMS
SIO
ESPI_IO0 [8,58]
ESPI_IO1 [8,58]
ESPI_IO2 [8,58]
ESPI_IO3 [8,58]
ESPI_CS# [8,58]
ESPI_RESET# [8,58]
ESPI_CLK_5105 [8,58]
17
16
8
9
10
11
19
18
12
13
14
15
+1.
+3.
3V_ALW_DSW
_PWRBTN#
CLK
_ITPXDP_P_R [11]
CLK
_ITPXDP_N_R [11]
ITP
_PMODE [13]
XDP
_DBRESET# [11]
PCH
_SPI_DO2_XDP [8]
0V_VCCSTG
1.5K_0402_5%
@
RC2
41
1 2
0.1U_0402_25V6
@
CC2
12
69
3
+BL_PWR_SRC
12
+LC
DVDD
0.1U_0402_25V6
12
0.1U_0402_25V6
CV6
34
CV6
52
2 1
DV11
RB751S40T1G_SOD523-2
2 1
DV1
2
RB751S40T1G_SOD523-2
12
200K_0402_5%
12
RV6
12
26
12
200K_0402_5%
12
RV6
12
29
2
10K_0402_5%
RV6
27
2200P_0402_50V7K
CV6
33
2
10K_0402_5%
RV6
31
2200P_0402_50V7K
CV6
51
2
+13.5VB
12
LC11
HCB1608KF-121T30
+13.5VB_L
QV18
1 3
MMBT3906H_SOT23-3
47K_0402_5%
12
RV6
25
BL_
PWR_MONITOR
LMBT3904W T1G NPN SC70-3
QV2
0
1 3
MMBT3906H_SOT23-3
47K_0402_5%
12
RV6
30
LCD
VDD_MONITOR
LMBT3904W T1G NPN SC70-3
M-BIST
DZ12
@
ACA
V_IN[58,84,91]
R
M_BI
ST[58]
+3.
3V_ALW
CPU
_XDP_TDO
CPU
_XDP_TDI
CPU
_XDP_TMS
CPU
_XDP_TRST#
_JTAG_TMS
_JTAG_TDI
_JTAG_TDO
RZ14
RZ14
POW
XDP
PCH
_RSMRST#[58,63]
CPU
TDO
TDI
XDP
TRS
_XDP_TCLK
_XDP
_XDP
_TMS
T#_XDP
XDP
TDI
TDO
3
1 2
RC3
28 0_0402_5%@
RC8
50 0_0201_5%@
RC8
51 0_0201_5%@
RC8
52 0_0201_5%@
RC8
53 0_0201_5%@
_TMS
1 2
RC7
35 0_0402_5%@
_XDP
1 2
RC7
36 0_0402_5%@
_XDP
1 2
RC7
37 0_0402_5%@
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
XDP
_JTAGX
12
12
12
12
PCH
PCH
PCH
21
B751S40T1G_SOD523-2
ER_SW_IN#[58,59]
_JTAGX [14]
RZ14
15 0_0402_5%@
1 2
82 1M_0402_5%
1 2
13 330K_0402_5%@
12
CZ21
8 2.2U_0603_10V6K
CPU
_XDP_TDO [14]
CPU
_XDP_TDI [14]
CPU
_XDP_TMS [14]
CPU
_XDP_TRST# [14]
PCH
_JTAG_TMS [14]
PCH
_JTAG_TDI [14]
PCH
_JTAG_TDO [14]
12
M_B
IST_R
L
MBT3904W T1G_SC70-3
2
RF@
+LCDVDD
C
2
B
E
QV1
9
3 1
+3.
3V_RUN
C
2
B
E
QV2
1
3 1
BAT
1_LED#_R
C
2
B
E
QZ21
3 1
Service Mode Switch:
Add a switch to ME_FWP signal to unlock the ME region and
allow the entire region of the SPI flash to be updated using FPT.
+3.
3V_ALW_PCH
1 2
ME_FWP PCH has internal 20K PD.
(suspend power rail)
FLASH DESCRIPTOR SECURITY OVERRIDE
LOW = ENABLE (DEFAULT) -->Pin1 & Pin3 short
HIGH = DISABLE (ME can update) -->Pin2 & Pin3 short
DEL
For BL_PWR_SRC & LCDVDD monitor
100K_0402_5%
12
RV6
23
PANEL_PWRGD
2
Double chceck footprint
ME_
@
RC2
22
1K_0402_5%
RV628
@
0.1U_0402_25V6
1M_0402_5%
12
CV6
12
RV6
32
24
R1=
10K;R2=10K
R2
R1
LM
UN5111T1G_SC70-3
QZ3
1 3
RZ25
FWP
1 2
@
RC2
21 0_0402_5%
PT,ST pop RC222 and SW1; MP pop RC221
ME_F
WP[58]
ME_F
ME_F
WP_PCH[12]
L CONFIDENTIAL/PROPRIETARY
Tit
Tit
Title
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
1 2
0_0402_5%
RF Request
+13
.5VB_L
47P_0402_50V8J
RF@
1
12
CV7
55
2
place as close as QV18
BAT
T_YELLOW#
1 2
150_0402_5%
ME_F
WP_PCH
SW1
@
1
A
2
B
WP_PCH
3
C
4
G1
5
G2
S
S3-CMFTQR9_3P
Com
Com
Com
pal Electronics, Inc.
pal Electronics, Inc.
pal Electronics, Inc.
XDP
XDP
XDP
/CMC/APS...debug
/CMC/APS...debug
/CMC/APS...debug
LA-
LA-
LA-
1
100P_0402_50V8J~D
RF@
CV7
56
G891P
G891P
G891P
1
PANEL_MONITOR [58]
BAT
T_YELLOW# [64]
79 10
79 10
79 10
of
of
of
0.3
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
2Monday, February 25, 2019
Page 80
5
D D
C C
4
3
2
1
Reserve
B B
A A
DELL
CONFIDENTIAL/PROPRIETARY
Comp
Comp
al Electronics, Inc.
Titl
Titl
Titl
e
e
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
e
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
Goog
Goog
le Debug
le Debug
LA-G
LA-G
891P
891P
1
0.3
80 102M
80 102M
of
of
of
0.3
Page 81
5
D D
C C
4
3
2
1
B B
A A
DEL
L CONFIDENTIAL/PROPRIETARY
Com
Com
pal Electronics, Inc.
Tit
Tit
Tit
le
le
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.
5
4
3
2
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronics, Inc.
PWR
PWR
-Block Diagram
-Block Diagram
LA-
LA-
893
893
1
81 10
81 10
of
of
of
0.1
0.1
1Monday, February 25, 2019
1Monday, February 25, 2019
Page 82
5
PL3
EMI@
+3.3
61
1_EN_R
V_VDD_DCIN
PR80
1K_0402_1%
HW_ACAV
3
PR82
3
A
PQ10
100K_0402_5%
2
1
V_VDD_DCIN
12
L2N7002DW1T1G 2N SC88-6
6
IN_NB
BLM15AG102SN1D_2P
PD4
@ESD@
AZ5125-02S.R7G_SOT23-3
12
PR31
M_0402_5%
1
12
PR32
1
M_0402_5%
PR33
34
00K_0402_5%
1
B
5
PQ10
L2N7002DW1T1G 2N SC88-6
12
12
PR28
5
00K_0402_5%
PR86
1
100K_0402_5%
+3.3
V_ALW
HW_A
<37,50,82,84>
+20V_TBTA_VBUS_1
+20V
_TBTA_VBUS_1
12
9
PC80
100P_0402_50V8J
EMI@
12
PQ11
G
2
S1_O
short pad
PQ8
L2
N7002WT1G 1N SC-70-3
D
S
13
G
2
12
5
PC86
0.1U_0402_25V6
+3.3
CAVIN_NB
NB_PSID PS_ID
D D
PL4
EMI@
FBMJ4516HS720NT_2P
1 2
CONN@
PJPD
C1
7
GND2
6
GND1
5
5
4
4
+19.
3
3
2
9
2
NPTH
2
1
8
1
NPTH
1
CVILU_CI0805M1HRC-NH
+3.3V_VDD_DCIN
HW_A
CAVIN_NB<37,50,82,84>
C C
+3.3
V_VDD_DCIN
+19.5V_DC_IN
B B
+3.3
+3.3
12
12
0
9
PR80
PR80
422K_0402_1%
102K_0402_1%
(>17.6V)
12
12
7
5
PR81
PR81
24.9K_0402_1%
37.4K_0402_1%
5V_DCIN_JACK
short pad
short pad
V_VDD_DCIN
V_VDD_PIC
0
PC80
short pad
12
100P_0402_50V8J
12
PC5
00P_0402_50V7K
EMI@
10
1 2
0
1 2
0
PC13
@
0
.1U_0402_10V7K
1 2
PR42
0
_0402_5%
1 2
1 2
PR44
0
_0402_5%
MC
74VHC1G08DFT2G_SC70-5
DCIN
_AC_Detector
0.01UF_0402_25V7K
PR86
0_0402_5%
1 2
@
3
2
BAT54CW_SOT323-3
12
4
PC80
220P_0402_50V8J
_0402_5%
PR47
_0402_5%
@
6
PR41
1 2
PD80
+20V_TBTA_VBUS
12
6
PC80
100P_0402_50V8J
@EMI@
1
2
PU3
@
PC80
PC7
@EMI@
5
P
B
A
G
3
1
0
1
3
+
2
-
EMI
EMI@
5A_Z80_20M_0805_2P
5A_Z80_20M_0805_2P
12
PC807
EMI@
1000P_0402_50V7K
12
0.1U_0402_25V6
4
O
1.8M_0402_1%
1 2
LM393_P
8
P
O
G
4
1 2
1 2
EMI@
Capacitor on +19.5V_DC_IC net need < 1000pF
12
PR13
4.7K_0805_5%
@
2
12
@0@
PR43
0
_0402_5%
12
<37>
PR45
@
DCIN
1
0K_0402_5%
+3.3
LM39
3_P
PR80
5
12
PU80
0A
AS393MMTR-G1 MSOP 8P OP
1
12
5
PC80
1200P_0402_50V7K
Part
PL80
1
PL80
0
12
12
PC808
0.1U_0402_25V6
@EMI@
+20V_TBTA_VBUS_1
+20V_VBUS_DC_SS
12
0
PR87
@
499K_0402_1%
A A
OVP setting:5.4V
12
1
PR83
499K_0402_1%
12
12
2
1
PR84
PC81
10U_0402_6.3V M
97.6K_0402_1%
L2N7002DW1T1G 2N SC88-6
5
+3.3
2
PR83
3
PR84
V_VDD_DCIN
12
102K_0402_1%
12
37.4K_0402_1%
PQ81
S1 OVP
SDMK0340L-7-F_SOD323-2
1 2
5
6
12
PC812
100P_0402_50V8J
61
3A
2
12
PR84
6
10K_0402_5%
PD80
2
LM39
3_P
LM393
8
P
+
O
-
G
4
HW_A
_P
PU80
0B
AS393MMTR-G1 MSOP 8P OP
7
EN_P
D_HV_1 <28,50,84>
CAVIN_NB<37,50,82,84>
12
PR83
5
47K_0402_1%
PR84
0
1 2
5
0_0402_5%
12
short pad
3
PC81
2.2U_0402_25V6M
12
S
D
1 3
O3409 P-CHANNEL SOT-23
A
12
VP <50>
L
13
D
S
short pad
PR22
1 2
0
_0402_5%
12
PR27
1
00K_0402_5%
V_VDD_DCIN
short pad
PR83
1 2
34
0_0402_5%
PQ81
3B
L2N7002DW1T1G 2N SC88-6
4
12
PR6
100K_0402_1%
12
PR8
15K_0402_1%
+19.5V_DC_IN
12
PC6
PR12
M_0402_5%
1
022U 25V K X7R 0402
0.
PR46
0
_0402_5%
PQ12
2N7002WT1G 1N SC-70-3
2
12
G
PR49
0
_0402_5%
VBUS
<37,50>
EN_P
D_HV_1
<28,50,84>
6
S1_O
VP
4
PR3
@0@
1 2
0_0402_5%
PSID circuit, it need with >6KV ESD
1 3
D
S
PQ2
FDV301N-G_SOT23-3
G
2
C
2
PQ3
B
LMBT3904WT1G NPN SC70-3
E
3 1
S1
PQ9
S TR EMZB08P03V 1P EDFN3X3-8
1
2
3 5
4
12
PR18
1
M_0402_5%
short pad
2_ECOK_R
13
D
2
PQ6
G
S
N7002WT1G 1N SC-70-3
L2
short pad
+3.3V_VDD_PIC
+3.3V_ALW2
short pad
S1_O
VP <82>
PR5
33_0402_5%
1 2
+19.5V_DC_IN_SS
PR85
0_0402_5%
1 2
PR85
0_0402_5%
1 2
PR86
@0@
0_0402_5%
1 2
1 2
PC81
@
PR85
0.1U_0402_10V7K
3
0_0402_5%
1 2
1 2
PR85
4
0_0402_5%
@
MC74VHC1G08DFT2G_SC70-5
PD5
2
3
S2
PQ4
EMZB08P03V_EDFN3X3-8-5
4
12
PR16
9.9K_0402_1%
4
13
D
2
PQ7
G
S
N7002WT1G 1N SC-70-3
L2
12
3
PQ80
G
2
12
1 2
61
0_0402_5%
2A
2
PQ80
L2N7002DW1T1G 2N SC88-6
L2N7002DW1T1G 2N SC88-6
PQ80
7
L2N7002WT1G 1N SC-70-3
S
G
2
12
1
PR82
100K_0402_5%
V_ALW
1
1
2
35
PR11
short pad
1 2
0
_0402_5%
S
D
1 3
PR85
short pad
D
13
2
PR82
100K_0402_5%
+3.3
V_VDD_PIC
3
PS_ID <37>
12
12
PC4
99K_0402_1%
4
PR20
12
3
PC80
0.47U 25V K X5R 0402
AO3409 P-CHANNEL SOT-23
8
13
D
L2N7002WT1G 1N SC-70-3
S
VBUS
<37,50>
1 2
3
+3.3V_VDD_DCIN
3
12
12
PC12
PC10
4.7U_0402_6.3V6M
2P_0402_50V8J
8
@RF@
12
PR10
300K_0402_5%
PQ5
S
G
2
12
D
1 3
PR15
022U 25V K X7R 0402
1
00K_0402_5%
0.
3409 P-CHANNEL SOT-23
AO
61
PQ1A
2N7002DW1T1G 2N SC88-6
L
VBUS
PR24
1
00K_0402_5%
S4 S5
PQ80
S TR EMZB08P03V 1P EDFN3X3-8
1
2
3 5
12
12
3
PR80
499K_0402_1%
1
short pad
PR81
PQ81
4
2
G
12
2
0_0402_5%
PR86
1
1_ECOK_R
PR81
8
1 2
0_0402_5%
short pad
EN_P
short pad
1 2
2
0
_0402_5%
1_ECOK_R <37,50>
0
4
12
61
49.9K_0402_1%
4A
PQ80
D_HV_1<28,50,84>
L2N7002DW1T1G 2N SC88-6
PR19
short pad
PR83
1 2
0_0402_5%
+3.3
V_VDD_DCIN
12
34
PQ1B
2N7002DW1T1G 2N SC88-6
L
+20V_VBUS_DC_SS
12
2
PR86
@
VBUS
4
PU2
VCC
VOUT
GND
RT9058-33GX_SOT89-3
+19.5V_SDC_IN
PR17
1
00K_0402_5%
short pad
1 2
5
0
_0402_5%
100K_0402_5%
2_ECOK_R<37,50>
+3.3
V_ALW
5
G
1
2
PR25
short pad
12
0_0402_5%
PR81
100K_0402_5%
VBUS
VBUS
12
PR83
3
100K_0402_5%
2
G
34
D
8B
PQ80
S
@0@
0_0402_5%
1 2
L2N7002DW1T1G 2N SC88-6
HW_A
CAVIN_NB<37,50,82,84>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPA
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+3.3V_ALW
PR4
2.2K_0402_5%
1 2
+5V_ALW
12
PR7
10K_0402_1%
S SCH DIO 5A 100V 15UA 0.88V TO227-3
12
12
PC8
PR14
U_0603_25V6M
00K_0402_5%
1
10
PR80
1
300K_0402_5%
+3.3
V_ALW
+3.3
V_VDD_PIC
PR80
7
100K_0402_5%
12
1
12
PR85
PR81
0
100K_0402_5%
@
100K_0402_5%
EN_PD_
7
9
0
4
5
1
P
B
O
2
A
G
3
PU80
1
HV_1#
34
2B
5
PQ80
12
@0@
PR85
6
0_0402_5%
4
12
PR85
5
@
10K_0402_5%
DCIN
2_EN_R<37>
+3.3
2
PR892
PD803
22_0805_5%
1 2
1
1
2
35
PR81
2
49.9K_0402_1%
4B
PQ80
L2N7002DW1T1G 2N SC88-6
+3.3
5
G
2
1
BAT54CW_SOT323-3
12
12
4
PR80
499K_0402_1%
V_ALW
12
PR82
@
100K_0402_5%
2
G
+3.3
V_ALW
12
PR83
100K_0402_5%
34
D
PQ80
L2N7002DW1T1G 2N SC88-6
S
@0@
2
3
2
PC80
4
61
S
9
9B
1 2
PR84
0_0402_5%
1500P_0402_50V7K
D
2
G
PR893
22_0805_5%
1 2
AO3409 P-CHANNEL SOT-23
+3.3
0A
PQ81
5
+20V_LDO_input
1
000P_0402_50V7K
PC11
12
HW_A
CAVIN_NB <37,50,82,84>
PD80
1
S SCH DIO 5A 100V 15UA 0.88V TO227-3
2
3
PQ80
1
EMZB08P03V_EDFN3X3-8-5
4
12
34
PR81
6
5
1 2
9
short pad
PR82
6 0_0402_5%
1 2
1_ECOK_R<37,82>
1 2
2_ECOK_R<37,50>
PR82
7 0_0402_5%
+3.3
V_ALW
12
PR83
0
100K_0402_5%
61
D
8A
PQ80
S
L2N7002DW1T1G 2N SC88-6
PR84
1
PR84
4
1 2
0_0402_5%
short pad
RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
S
PQ80
G
2
D
1 3
6B
PQ80
L2N7002DW1T1G 2N SC88-6
V_ALW
12
PR82
@
100K_0402_5%
5
G
+3.3
V_ALW
12
L2N7002DW1T1G 2N SC88-6
PR83
100K_0402_5%
61
D
PQ80
L2N7002DW1T1G 2N SC88-6
S
12
12
34
5
8
PR80
300K_0402_5%
PR80
100K_0402_5%
34
D
S
9A
+19.5V_DC_IN
+20V_TBTA_VBUS_1
2
8
5
1 2
PR81
0_0402_5%
short pad
+3.3
<37>
AC_D
ISC#
0B
PQ81
12
L2N7002DW1T1G 2N SC88-6
0
PC81
@
4
V_ALW
12
61
D
S
1500P_0402_50V7K
PR82
8
100K_0402_5%
1 2
0_0402_5%
1A
PQ81
L2N7002DW1T1G 2N SC88-6
+3.3
V_VDD_PIC
12
61
6A
PQ80
L2N7002DW1T1G 2N SC88-6
PR82
9
short pad
2
G
1
+19.5V_SDC_IN
+3.3
V_ALW
12
PR85
2
@
PR81
3
100K_0402_5%
100K_0402_5%
PR82
0
2
1 2
EN_P
D_HV_1 <28,50,84>
0_0402_5%
short pad
CMOU
T <84>
34
D
5
1B
G
PQ81
S
L2N7002DW1T1G 2N SC88-6
PROC
HOT#_CHG <84>
13
D
2
2
G
PQ81
S
L2N7002WT1G 1N SC-70-3
DELL
CONFIDENTIAL/PROPRIETARY
Comp
Comp
Comp
Titl
Titl
Title
e
e
DC C
DC C
DC C
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
1
al Electronics, Inc.
al Electronics, Inc.
al Electronics, Inc.
onnector/1Type-C PD Selector
onnector/1Type-C PD Selector
onnector/1Type-C PD Selector
LA-8
LA-8
LA-8
91
91
91
82 101M
82 101M
82 101M
of
of
of
0.3
0.3
0.3
Page 83
5
4
3
2
1
+COINCELL
12
PR2
1K_0402_5%
D D
+RTC_CELL
12
PC3
1
U_0402_25V6K
12
PR9
10M_0402_5%
+COINCELL
1
PD1
ESD@
CEST523NC5VB_SOT-523-3
2
Primary Battery Connector
CON
N@
PBA
TT1
1
1
2
2
3
3
4
4
5
5
12
PC1
EMI@
200P_0402_50V7K
2
C C
6
6
7
7
8
8
9
9
10
10
11
GND
1
12
GND
2
DEREN_40-42251-01001RHF
PBA
PBA
PBA
T_SMBCLK_C
T_SMBDAT_C
T_PRES#_C
GND
1 2
PR3
100_0402_5%
1 2
PR3
100_0402_5%
1 2
PR4
100_0402_5%
3
8
9
0
1
ESD@
CEST523NC5VB_SOT-523-3
2
3
PD2
+13
.2VB_PBATT_C
PBA
T_CHARGER_SMBCLK <37,84>
PBA
T_CHARGER_SMBDAT <37,84>
PL1
EMI@
FBMJ4516HS720NT_2P
1 2
PL2
EMI@
F
BMJ4516HS720NT_2P
1 2
+13.2VB_BATT
+3.3V_ALW
12
PR1
1
00K_0402_5%
PBA
T_PRES# <37,84>
+3.3V_RTC_LDO
PD3
B
AS40CW_SOT323-3
012
+Z4
2
3
1
13
D
2
G
S
CONN@
1
ACES_50271-0020N-001
JRT
1
22G2
RTC_DET#
<37,50,82,84>
3
PQ1
C1
G1
L2N7002WT1G 1N SC-70-3
3
4
COIN RTC Battery
B B
A A
DELL CO
NFIDENTIAL/PROPRIETARY
Comp
Comp
Comp
al Electronics, Inc.
al Electronics, Inc.
Tit
Tit
Title
le
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
Bat
Bat
Bat
tery Connector/ RTC
tery Connector/ RTC
tery Connector/ RTC
LA-
LA-
LA-
891
891
891
1
83 10
83 10
83 10
of
of
of
0.3
0.3
0.3
1Monda y, February 25, 2019
1Monda y, February 25, 2019
1Monda y, February 25, 2019
Page 84
A
+19.5V_SDC_IN
1 1
Not to change short pad
+19.
PD70
5V_SDC_IN
0
+19.5V_DC_IN_SS
+19.5V_DC_IN_SS
+19.5V_DC_IN_SS+19.5V_DC_IN_SS
SDMK0340 L-7-F_SOD323-2~D
2 2
+13.5VB
+13.5VB
+13.5VB+13.5VB
SDMK0340 L-7-F_SOD323-2~D
+20V_VBUS_DC_SS
+20V_VBUS_DC_SS
+20V_VBUS_DC_SS+20V_VBUS_DC_SS
ACAV
_IN1<9 1>
AC_D
IS<37>
3 3
4 4
12
PD70
2
12
PD70
4
2 1
RB520SM-3 0T2R_EMD2-2
PC73
7
2.2U_040 2_25V6 M
1 2
4.7U_040 2_6.3V6M
PQ70
3
13
D
2
154K_04 02_1%
G
12
S
2N7002KW 1N SOT323-3
PR72
0
1M_0402_1%
1 2
PC73
PR71
12
9
6
PR70
8
1_0805_ 5%
12
0.1U_040 2_25V6
1 2
PBAT
_PRES#<37,83>
PC73
VDD_
PR71
0
100K_04 02_1%
PBAT
_CHARGER_ SMBDAT<37,83>
PBAT
_CHARGER_ SMBCLK<37,83>
PROC
6
CHG
HW_A
PROC
HOT#_CHG<68>
100K_0402_1%
1 2
12
12
12
CAVIN_NB
short pad
HOT#<13,19,37,6 5>
PR72
4
PR70
5
442K_04 02_1%
ACIN
PR70
6
100K_04 02_5%
@0@
1 2
PR70
1 2
0_0402_ 5%
@0@
PR70
0_0603_ 5%
1 2
_CHG
PR74
0_0402_ 5%
9
short pad
PR71
2
0_0402_ 5%
1 2
1 2
PR71
1 2
PR71
1 2
PR71
0_0402_ 5%
1 2
PR72
2
0_0402_ 5%
PR72
@
100K_04 02_1%
1 2
+3.3
short pad
3
6
DCIN
VDD_
ACIN
OTGE
3 0_0402_5%
5 0_0402_5%
PROC
9
ACOK
3
V_ALW
CMOU
T<50>
PROC
HOT#
_CHG
CHG
_CHG<37>
N/CMIN_CHG
SDA_
CHG
SCL_
CHG
HOT#_CHG
_CHG
PC74
10P_040 2_50V8 J
1 2
BATG
1 2
@0@
PR74
1 2
12
8
PR72
499_0402_1%
12
1
PC75
0.01UF_0402_25V7K
100K_04 02_1%
1 2
1
2
_CHG_R
CSIP
12
PR701
1_0603_ 1%
4.7U_040 2_6.3V6M
12
5
PC72
1U_0402_25V6K
ADP_
CHG
1
7
DCIN
18
VDD
1
9
ACIN
20
OTGE
N/CMIN
21
SDA
22
SCL
23
PROC
HOT#
2
4
ACOK
4
ONE_CHG
PR72
6
PR72
70_ 0402_5 %
5
0_0402_ 5%
short pad
12
9
9
PC74
@
PR72
560P_0402_50V7K
Clos
e to EC ADP_I pin
PR700
0.01_12 06_1%
PC71
1 2
CSIP
_CHG
5
16
1
ADP
CSIP
/CMOUT
NE
BATGO
OTGPG
25
26
G/CMOUT_CHG
OTGP
12
0_0402_5%
I_BA
TT
TT
I_BA
9
CSIN
_CHG
4
1
7
2
_CHG
PROG
12
5
PR72
3
PR74
<37>
+19.5V_AC
4
3
13
TE
CSIN
ASGA
CMOP
PROG
8
2
_CHG
COMP
105K_0402_1%
12
0_0402_5%
I_AD
P
P
I_AD
_CHG_R
CSIN
12
PR702
1_0603_ 1%
12
PC72
0.47U 25V K X5R 0402
_CHG_R
BST1
12
PR70
3.3_060 3_1%
BOOT
UG1_
CHG
1_CHG
2
1
11
1
BOOT1
UGATE
/BMON
AMON
PSYS
0
29
3
_CHG
PSYS
/BMON_CHG
AMON
12
0
PC75
0.1U_0402_25V6
short pad
<37>
B
EMI@
1UH_PCMB0 51H-1R0MS _8A_20 %
1 2
1 2
PAD-OPEN 4x4m
@JUMP@
12
1
PD70
SMF4L22A_SOD123FL2
12
7
4
LX1_
LG1_
CHG
CHG
PU70
33
10
9
ISL9538 HRTZ-TS2778 TQFN 32P CHARGER
1
E1
PAD
8
LGATE
PHAS
VDDP
7
LGAT
E2
6
PHAS
E2
5
UGAT
E2
4
BOOT
2
3
VSYS
2
CSOP
1
CSON
VBAT
BGATE
1
2
3
3
1_CHG
E_CHG
VBAT
BGAT
P
P
P
P
S
S
S
S
Y
Y
Y
Y
S
S
S
S
R
R
R
R
o
o
o
o
12
n
n
n
n
C
C
C
C
1
P
P
P
P
U
U
U
U
C
C
C
C
PR73
o
o
o
o
n
n
0_0402_5%
n
n
t
t
t
t
r
r
r
r
o
o
o
o
l
l
l
l
l
l
l
l
e
e
e
e
r
r
r
r
s
s
s
s
i
i
i
i
t
t
t
t
e
e
e
e
S
I_SY
<37,88>
PL700
PJP700
6
PC72
1U_0402_25V6K
0
12
LG2_
LX2_
UG2_
BOOT
VSYS
CSOP
CSON
VDDP
@
PR70
7
4.7_060 3_5%
1 2
_CHG
CHG
CHG
CHG
0.47U 25V K X5R 0402
2_CHG
1 2
_CHG
_CHG
_CHG
1 2
PR73
100_040 2_5%
PC75
5
0.1U_040 2_25V6
0
1
12
PC70
PC70
0.1U_0402_25V6
2200P_0402_50V7K
@EMI@
@EMI@
VDD_
CHG
1 2
PC73
8
4.7U_040 2_6.3V6M
PC74
0
BST2
_CHG_R
PR72
1 2
0_0402_ 5%
8
6
12
PC75
RF@
100P_0402_50V8J
1 2
1
1 2
PC74
@
0.1U_040 2_25V6
+13.
2VB_BATT
2
12
PC70
10U_0805_25VAK
12
6
PC70
10U_0805_25VAK
PR71
4
4.7_060 3_5%
short pad
5
12
12
12
3
PC70
10U_0805_25VAK
12
6
PC71
10U_0805_25VAK
UG1_
LX1_
+13.
5VB
1U_0402 _25V6K
1 2
PC75
2
1U_0402 _25V6K
1 2
0.22U_04 02_25V 6K
4
PC70
10U_0805_25VAK
7
PC71
CHG
CHG
PQ700
AOE6
PC74
@
1 2
PR73
3
1_0603_ 1%
PR73
4
1_0603_ 1%
1 2
PC75
3
HW_A
+19.5V_CHARGER
12
12
10U_0805_25VAK
1
G1
2
S1/D
2
3
D1_1
4
D1_2
936_DFN5X6E8-10
8
EN_P
D_HV_1<28,50,84>
CAVIN_NB<37,50,82,84>
9
D2/S
D2/S
D2/S
10
D1_3
S2
G2
1_3
1_2
1_1
short pad
8
7
6
5
CSON
CSOP
LG1_
6
PC74
680P_0402_50V7K
EMI@
_CHG_R
_CHG_R
1 2
0_0402_ 5%
1 2
0_0402_ 5%
C
LG2_
CHG
2.2UH_PCMB103T-2R2MS_13A_2 0%
LX1_
12
1_CHG
SNUB
12
PR73
PR73
BAT54CW_SOT323-3
PL70
1
1 2
CHG
7
PR71
4.7_1206_5%
EMI@
6
3
7
2
PD70
CHG
LX2_
CHG
12
8
PR71
4.7_1206_5%
EMI@
2_CHG
SNUB
12
7
PC74
680P_0402_50V7K
EMI@
1
5
D
+13.5VB
12
7
PC70
10U_0603_25V6M
12
12
1
0
PC72
@EMI@
9
8
G2
7
D2/S
6
D2/S
5
D2/S
1
G1
D1_3
2
S1/D
1_3
2
3
D1_1
1_2
4
D1_2
1_1
S2
10
PQ701
AOE6
936_DFN5X6E8-10
@0@
12
9
ACAV
_IN1
PR73
100K_0402_1%
PC72
0.1U_0402_25V6
@EMI@
UG2_
LX2_
CHG
PR73
0_0402_ 5%
1 2
0.1U_040 2_10V7 K
1 2
PR74
0_0402_ 5%
2200P_0402_50V7K
CHG
5
PC75
1 2
1
+13.
4
5VB
12
12
8
9
PC72
PC72
0.1U_0201_25V6K
0.1U_0201_25V6K
RF@
RF@
PR71
1
0.005_1 206_1%
1
4
3
2
LM39
3_P
5
1
2
PR74
P
IN1
1 2
4
O
IN2
G
0_0402_ 5%
PU70
1
3
MC74VHC1G 08DFT2G_S C70-5
12
0
PC73
0.1U_0201_25V6K
RF@
short pad
0
12
8
PC70
10U_0603_25V6M
12
1
PC73
82P_0201_50V8J
RF@
+13.
5VB_VCHGR
12
1
PC74
10U_0603_25V6M
12
9
PC70
10U_0603_25V6M
12
2
PC73
82P_0201_50V8J
RF@
12
2
PC74
10U_0603_25V6M
100K_0402_1%
12
PR74
4
short pad
1
12
0
+
5
PC71
PC71
2
10U_0603_25V6M
15U_B2_25VM_R100M
12
12
4
3
PC73
PC73
82P_0201_50V8J
RF@
RF@
22P 16V K X7R 0201
PQ70
EMZB08P0 3V_EDFN3 X3-8-5
1
2
3 5
ACAV
_IN <37>
12
5
PC73
RF@
2200P 16V K X7R 0201
2
4
12
3
PC74
@
4700P_0402_25V7K
12
12
1
0
PC76
PC76
18p_0402_50V6
100P_0402_50V8J
RF@
RF@
+13.
2VB_BATT
BGAT
E_CHG
For IT8010 voltage leakage issue
Comp
Comp
Comp
al Electronics, Inc.
al Electronics, Inc.
DELL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND C ONTAINS CONFIDENTIAL
AND
TRADE SECRET INFORMATION. T HIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.
CONFIDENTIAL/PROPRIETARY
C
Titl
Titl
Title
e
e
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
M
M
M
onday, February 25, 2019
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
Char
Char
Char
ger
ger
ger
LA-8
LA-8
LA-8
91
91
91
D
0.3
0.3
84
84
84
0.3
of
101
of
101
of
101
Page 85
A
B
C
D
E
short pad
PR119
PGOOD_3V
PGOOD_5V
1 1
0_0402_5%
1 2
1 2
PR120
0_0402_5%
ALW_PWRGD_3V_5V <19,47>
12
12
08
PC1
22U_0603_6.3V6M
+3.
+5V
12
21
22
PC1
PC1
22U_0603_6.3V6M
22U_0603_6.3V6M
5VALWP
TDC 7.54 A
Peak Current 7.9A
OCP Current 11.5 A
+13.5VB
3VALWP
TDC 6.51A
Peak Current 9.3 A
OCP Current 11.5 A
+3.
3V_ALWP
12
12
12
09
10
PC1
PC1
22U_0603_6.3V6M
22U_0603_6.3V6M
3V_ALWP
_ALWP
12
12
23
24
PC1
PC1
22U_0603_6.3V6M
DEL
Tit
Tit
Title
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
12
62
29
PC1
12
22U_0603_6.3V6M
61
PC1
@
22U_0603_6.3V6M
PJP1
112
JUMP_43X118
PJP1
112
JUMP_43X118
30
PC1
22U_0603_6.3V6M
35
36
12
PC1
@
22U_0603_6.3V6M
02
2
03
2
12
@
12
PC1
PC1
22U_0603_6.3V6M
27P_0402_50V8J
RF@
RF@
100P_0402_50V8J
+3.
+5V
12
37
64
63
PC1
22U_0603_6.3V6M
12
PC1
PC1
@
22U_0603_6.3V6M
RF@
L CONFIDENTIAL/PROPRIETARY
Com
Com
Com
pal Electronics, Inc.
pal Electronics, Inc.
pal Electronics, Inc.
+5V
+5V
+5V
_ALW/3.3V_ALW
_ALW/3.3V_ALW
_ALW/3.3V_ALW
LA-
LA-
LA-
891
891
891
E
3V_ALW
_ALW
+5V
_ALWP
38
45
12
12
PC1
PC1
RF@
RF@
100P_0402_50V8J
100P_0402_50V8J
85 10
85 10
85 10
of
of
of
100P_0402_50V8J
0.3
0.3
0.3
1Monday, February 25, 2019
1Monday, February 25, 2019
1Monday, February 25, 2019
+13.5VB
PJP1
00
21
PAD-OPEN 1x2m~D
03
41
12
PC1
1U_0402_25V6K
RF@
2 2
+13
.5VB
46
12
PC1
3 3
ALW
4 4
22P_0402_50V8J
RF@
ON<37>
PAD-OPEN 1x2m~D
12
42
PC1
1U_0402_25V6K
RF@
Not to change short pad
1 2
PR1
0_0402_5%
PJP1
14
A
00
12
12
PC1
PC1
PC143
0.1U_0402_25V6
RF@
RF@
RF@
100P_0402_50V8J
+3.
3V_ALW
01
21
PC115
RF@
+13
16
12
12
PC1
0.1U_0402_25V6
RF@
2200P_0402_50V7K
+3.
12
12
16
PR1
1M_0402_1%
EN1 and EN2 dont't floating
31
12
PC1
82P_0402_50V8J
RF@
100P_0402_50V8J
PR1
07
100K_0402_5%
1 2
PGO
.5VB_5V
39
32
12
PC1
PC1
82P_0402_50V8J
RF@
RF@
3V_ALW
3V5
V_EN
PC1
28
4.7U_0402_6.3V6M
+13
.5VB_3V
33
12
PC1
RF@
OD_3V
40
12
PC1
100P_0402_50V8J
PR1
@
100K_0402_5%
1 2
2
5
PU1
LX_
3V
3V5
V_EN
PU1
LX_
5V
6
7
8
9
1
0
00
6
LX1
7
GND
1
8
SY8288BRAC_QFN20_3X3
GND
2
9
PG
1
0
NC1
EN1
EN2
2
1
1
1
DO_3V5V
ENL
5
02
LX1
GND
GND
PG
NC1
IN23IN34IN4
1
SYV828CRAC_QFN20_3X3
2
EN1
EN2
FF13OUT
2
1
1
1
V_EN
DO_3V5V
3V5
ENL
IN1
IN23IN34IN4
FF13OUT
4
1
PC1
1000P_0402_50V7K
FB_
3V
2
IN1
4
1
34
12
PC1
100P_0402_50V8J
17
12
PC1
RF@
100P_0402_50V8J
13
PGO
12
RF@
10U_0603_25V6M
OD_5V
04
05
PC1
PC1
10U_0603_25V6M
10U_0603_25V6M
100P_0402_50V8J
12
12
18
PC1
10U_0603_25V6M
B
12
12
1
BS
LX3
LX2
GND
4
LDO
NC3
GND
3
NC2
5
1
13
1 2
BST
1
BS
2
0
LX3
1
9
LX2
18
GND
4
1
7
VCC
1
6
NC2
21
GND
3
LDO
5
1
12
PC1
26
4.7U_0402_6.3V6M
PC1
27
1000P_0402_50V7K
FB_
5V
BST
2
0
1
9
18
1
7
1
6
21
_5V
+5V
1 2
short pad
PR100
_3V
1 2
0_0603_5%
LX_
PR1
04 0_0402_5%
LDO
_3V
1 2
1 2
PR1
05
0_0402_5%
3.3V LDO 150mA~300mA
PC1
11
4.7U_0402_6.3V6M
1 2
PR1
08
1K_0402_5%
1 2
BST
3V
_3V_R
short pad
+3.
3V_ALW2
+3.
3V_RTC_LDO
short pad
PC1
02
1 2
0.1U_0402_25V6
06
PR1
12
@EMI@
4.7_1206_5%
B_3V
SNU
12
12
PC1
680P_0402_50V7K
@EMI@
1.5UH_9A_20%_7X7X3_M
1 2
ENLDO_3V5V
03
PR1
PL1
00
short pad
PR1
11
BST
1 2
0_0603_5%
LX_
5V
1 2
PC1
19
2.2U 6.3V M X5R 0402
5V LDO 150mA~300mA
_ALW2
PR1
17
1K_0402_5%
1 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
_5V_R
C
PC1
14
1 2
0.1U_0402_25V6
PL1
01
1.5UH_9A_20%_7X7X3_M
1 2
12
12
PR1
@EMI@
B_5V
4.7_1206_5%
SNU
12
25
PC1
680P_0402_50V7K
@EMI@
PR102
499K_0402_1%
1 2
12
499K_0402_1%
12
12
07
06
PC1
PC1
22U_0603_6.3V6M
22U_0603_6.3V6M
Vout is 3.234V~3.366V
12
12
20
PC1
22U_0603_6.3V6M
D
Page 86
5
D D
+13.
5VB
PJP2
02
21
PAD-OPEN 1x2m~D
C C
12
0
PC201
PC20
10U_0603_25V6M
10U_0603_25V6M
82P_0402_50V8J
0.1U_0402_25V6
12
12
12
PC20
PC20
2
3
RF@
RF@
+3.3
1U_0201_6.3V6M
PC22
12
12
6
+3.3V_ALW
12
PR20
5
@0@
12
@0@
0_0402_5%
ILMT
_DDR
PR20
0_0402_5%
7
The
current limit is
set to 8A, 12A or 16A
when this pin is pull
low, floating or pull
high
+1.2V_DDR OCP set 12A
short pad
SIO_
B B
SLP_S4#<12,18,37,86>
1 2
PR20
8
0_0402_5%
short pad
0.6V
_DDR_VTT_ON<21>
1 2
PR21
0
0_0402_5%
+13.
V_ALW
9
PR20
@
5VB_DDR
1U_0201_6.3V6M
PC20
6
12
1M_0402_5%
4
PU20
0
10
IN
13
VCC_
2.2U 6.3V M X5R 0402
12
12
PC20
7
8
22P 16V K X7R 0201
PC22
ILMT
RF@
12
2
PR21
1M_0402_5%
_DDR
SLP_S4#_R
SIO_
_DDR_VTT_ON_R
0.6V
12
1
PC22
@
0.1U_0402_10V7K
12
2
PC22
@
0.1U_0402_10V7K
BYP
DDR
14
VCC
4
VTTG
ND
9
PGND
1
5
SGND
1
7
ILMT
1
S5
2
S3
SY8210AQVC_QFN19_4X3
VDDQ
VLDO
VTTS
VTTR
Layout for Pin4,9,15
VTTGND , PGND seperate GND via
PGNE Cin_cap shape GND via
SGND alone GND
Mode S3 S5 VOUT VTT
Normal H H on on
Stadby L H on off
Shutdown L L off off
SNS
VTT
3
OT
18
PG
12
BS
11
LX
16
FB
8
7
IN
6
5
NS
3
EF
BS_D
PR20
0_0603_5%
DR
1 2
LX_D
FB_D
+1.2
V_DDRP
VTTR
EF_DDR
3
DR
DR
0.1U_0402_25V6
BS_D
DR_R
1U_0201_6.3V6M
PC22
12
7
PC20
1 2
12
short pad
19
RF@
PR20
2
4.7_1206_5%
1 2
5
PL20
1 2
1UH_PCMB063T-1R0MS_12A_20%
PC20
9
22U_0603_6.3V6M
1 2
+0.6
VSP
22U_0603_6.3V6M
1U_0201_6.3V6M
PC21
12
PC21
8
9
1
+1.2
+1.2V_DDR
TDC 5.433A
Peak Current 7.761A
OCP Current 12A Fix by IC
SNUB
_DDR
V_DDRP
2
RF@
PC20
4
680P_0402_50V7K
1 2
330P_0402_50V7K
PC20
12
8
R1
R2
PJP2
JUMP_43X118
112
1
+1.2
V_DDRP
102K_0402_1%
12
PR20
4
100K_0402_1%
12
PR20
6
+1.2
V_MEM
00
2
22U_0603_6.3V6M
22U_0603_6.3V6M
PC21
PC21
12
12
1
0
+0.6
22U_0603_6.3V6M
22U_0603_6.3V6M
PC21
PC21
12
12
3
2
VSP
10U_0603_10V6M
PC21
12
4
PJP2
JUMP_43X39
112
10U_0603_10V6M
PC22
12
3
4
PC22
RF@
+0.6
01
V_DDR_VTT
2
15P_0402_50V8J
15P_0402_50V8J
RF@
RF@
12
12
PC21
PC21
7
6
5
12
12
PC22
RF@
100P_0402_50V8J
100P_0402_50V8J
0.6Volt +/- 5%
TDC 1.05A
Peak Current 1.5A
OCP Current 2A (fix)
Note: S3 - sleep ; S5 - power off
A A
DELL
CONFIDENTIAL/PROPRIETARY
Comp
Comp
Comp
al Electronics, Inc.
al Electronics, Inc.
Titl
Titl
Titl
e
e
e
+1.2
+1.2
THIS
SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
+1.2
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
V_MEN/+0.6V_DDR_VTT
V_MEN/+0.6V_DDR_VTT
V_MEN/+0.6V_DDR_VTT
LA-8
LA-8
LA-8
91
91
91
86 101M
86 101M
86 101M
1
0.3
0.3
0.3
of
of
of
Page 87
5
RF@
RF@
RF@
38
39
PC3
1 2
+13.5VB
12
12
12
12
15
34
16
17
PC3
PC3
PC3
PC3
18p_0402_50V6
1U_0402_25V6K
RF@
RF@
RF@
100P_0402_50V8J
0.1U_0402_25V6
RF@
D D
12
35
PC3
0.1U_0402_25V6
RF@
The current limit is set to 6A, 9A or 12A when this pin
is pull low, floating or pull high
0.1U_0402_25V6
PJP301
21
PAD-OPEN 1x2m~D
12
12
32
PC3
RF@
100P_0402_50V8J
PCH_PRIM_EN<11,17,47,87>
33
PC3
RF@
1U_0402_25V6K
1 2
+3.3V_ALW
12
@0@
PR3
0_0402_5%
12
@0@
PR3
0_0402_5%
PR312
22K_0402_1%
1M_0402_1%
07
ILM
T_1.05VALWP
10
12
30
PC3
@RF@
120P_0402_50V8J
PR302
PC336
PC3
1 2
1 2
1 2
37
0.1U_0402_25V6
1U_0402_25V6K
PC3
RF@
0.1U_0402_25V6
PU301
+13.5VB_1.05VALWP
2
IN1
12
12
12
31
PC3
03 100P_0402_50V8JRF@
01 18P 50V K NPO 0402RF@
10U_0603_25V6M
PC3
PC3
@RF@
100P_0402_50V8J
EN_1.05VALWP
12
12
60
+3.3V_ALW
PC3
0.1U_0402_25V6
3
12
12
IN2
4
PC305
IN3
PC306
5
IN4
10U_0603_25V6M
7
GND1
8
GND2
18
GND3
11
EN
13
ILMT
15
BYP
14
SY8286RAC_QFN20_3X3
PC3
PC312
1 2
1 2
1U_0201_6.3V6M
1U_0201_6.3V6M
+1.0V_PRIM
TDC 3.642A
Peak Current 5.203A
OCP Current 9 A Fix by IC
TYP MAX
Choke DCR 11.0mohm , 12.0mohm
PR313
1 2
100K_0402_5%
PC350
@
1 2
0.022U_ 0402_25V7K
9
PG
BST_1.05VALWP BST_1.05VALWP_R
1
BS
LX_1.05VALWP
6
LX1
19
LX2
20
LX3
14
FB
VCC_1.05VALWP
17
VCC
10
NC1
12
NC2
16
NC3
21
PAD
PR304
0_0603_5%
1 2
12
PC313
2.2U 6.3V M X5R 0402
+3.3V_ALW
1.0V_PRIM_PWRGD
short pad
<35>
PC304
0.1U_0402_25V6
1 2
FB_1.05VALWP
4
PR303
RF@
4.7_1206_5%
1 2
PL301
0.68UH_7.9A_20%_5X5X3_M
1 2
SNUB_1.05VALWP
12
06
PR3
22.1K_0402_1%
12
PR311
29.4K_0402_1%
RF@
PC302
680P_0402_50V7K
1 2
12
12
08
PR3
1K_0402_5%
+1.05VALWP
12
07
PC3
330P_0402_50V7K
3
short pad
PR429
+3.3V_ALW
1 2
CPU_C10_GATE#<6,87>
PJP302
2
+1.0V_PRIM
112
JUMP_43X118
+1.05VALWP
12
12
12
12
10
09
08
PC3
PC3
PC3
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
12
12
19
18
20
11
PC3
PC3
PC3
PC3
1U_0402_25V6K
RF@
RF@
27P_0402_50V8J
RF@
100P_0402_50V8J
22U_0603_6.3V6M
12
12
+5V_ALW
+3.3V_ALW
PR413
@
10K_0402_1%
PR4
15
10K_0402_1%
12
12
PR414
10K_0402_1%
PR4
@
10K_0402_1%
VID0_1VS_VCCIO
VID
Vin=3~17V
12
10
PC4
RF@
1U_0402_25V6K
1_1VS_VCCIO
16
12
12
14
16
PC4
PC4
100P_0402_50V8J
0.1U_0402_25V6
RF@
RF@
12
08
PC4
0.1U_0402_25V6
@EMI@
PL405
@
3A_Z120_40M_0603_2P
1 2
PJP403
1 2
PAD-OPEN1x1m
12
09
PC4
100P_0402_50V8J
RF@
short pad
RUN_ON<17,34,35,47,87>
03
PC4
0_0402_5%
1 2
SIO_SLP_S0#<11,17,36,87>
PR425
@0@
0_0402_5%
PR402
1 2
0_0402_5%
12
12
02
PR403
1M_0402_1%
PC4
1VS_VCCIO
@
EN_
0.1U_0402_25V6
13
PU401
12
11
10
short pad
9
PVIN2
PVIN1
AVIN
VID0
8
PR4
0_0402_5%
EN
SY8057BQDC_QFN16_3X3
1
VID
27
VIN_1VS_VCCIO
12
12
04
PC4
10U_0603_10V6M
10U_0603_10V6M
VID0_1VS_VCCIO
VID
1_1VS_VCCIO
2
12
@0@
PR404
0_0402_5%
+1VS_VCCIOP + 1.0VS_VCCIO
_1VS_VCCIO
LPM
4
16
15
1
17
D2
D1
TP
LPM
PGN
PGN
1
VOS
SW1
SW2
D
FBS5AGN
SS
6
7
1VS_VCCIO
_1VS_VCCIO
SS_
FBS
12
+1VS_VCCIOP
1UH_1277AS-H-1R0N-P2_3.3A_30%
LX_1VS_VCCIO
2
3
12
4
PG
@EMI@
4.7_0603_5%
B_1VS_VCCIO
SNU
12
@EMI@
470P_0402_50V7K
Not to change short pad
PL402
1 2
PR405
PC4
01
Not
to change short pad
1 2
PR4
0_0402_5%
PJP401
JUMP_43X79
2
112
12
12
06
07
PC4
PC4
22U_0603_6.3V6M
+1V
S_VCCIOP
12
PR4
21
@0@
0_0402_5%
1 2
VCC
IO_SENSE
PR4
22
0_0402_5%
VSS
12
IO_SENSE <17>
+1VS_VCCIOP
12
12
26
25
PC4
PC4
10U_0402_6.3V6M
10U_0402_6.3V6M
22U_0603_6.3V6M
<17>
Sense net-name follow HW sit e (Need to che ck)
1
VID1 LOGIC
LPM LOGIC OUTPUT VOLTAGE
0
SY8057BQDC 1 0
X
0
1
1
1
1
1
+1.0VS_VCCIO
TDC 2.1 A
Peak Current 4 A
OCP Current 6 A Fix by IC
TYP MAX
Choke DCR 48.0mohm
VID0 LOGIC
X
0
1
0
1 1.05
0(LPM)
0.80
0.95
1.00
+1.8V_PRIM
TDC 1.56 A
Peak Current 2.229 A
OCP Current 3.2 A fix by IC
C C
+3.
3V_ALW
PCH
_PRIM_EN<11,17,47,87>
B B
A A
PL5
02
@
3A_Z120_40M_0603_2P
1 2
PJP
501
VIN
short pad
PR5
1 2
0_0402_5%
PAD-OPEN1x1m
PR5
1 2
100K_0402_5%
1.0
V_PRIM_PWRGD
04
1M_0402_1%
11
1M_0402_1%
PJP
1 2
PAD-OPEN1x1m
PR5
05
PJP
503
PR5
09
505
short pad
0_0402_5%
1 2
@
12
12
PR5
@
1M_0402_1%
short pad
12
13
PR5
_1.8VALW
14
PR3
0_0402_5%
1 2
12
VIN
_1.2V_RUN
12
12
VIN
_2.5V_MEM
12
12
14
@
.1U_0402_16V7K
12
07
PC5
@
4.7U_0402_6.3V6M
EN_
0.1U_0402_25V6
14
PC5
4.7U_0402_6.3V6M
1 2
PAD-OPEN1x1m
Note:
When design Vi n=5V, please s tuff snubber
to prevent Vin damage
+3.
3V_RUN
RUN
_ON<23>
+3.
3V_ALW
SIO
_SLP_S4#<11,17,34,86,87>
PJP
12
30
PC5
22U_0603_6.3V6M
PU5
01
4
IN
5
PG
FB6EN
RT8097ALGE SOT23-6
EN_
1.8VALW
PC5
05
+1.
8VALWP
Imax= 2A, Ipea k= 3A
FB=0.6V
1UH_1277AS-H-1R0N-P2_3.3A_30%
LX_
1.8VALW
3
LX
12
2
GND
@EMI@
1
4.7_0603_5%
B_1.8VALW
SNU
12
@EMI@
680P_0402_50V7K
Vout=0.6V* (1+ Rup/Rdown)
PU5
02
S IC EM1109V-AD DFN3308 8P LDO
08
9
GND
2
8
7
6
5
PU5
S IC EM1109V-AD DFN3308 8P LDO
9
8
7
6
5
13
1
OUT
IN
NC1
NC3
ADJ
/NC
NC2
GND
1
EN
03
GND
2
OUT
IN
NC1
NC3
ADJ
/NC
NC2
GND
1
EN
12
2
ADJ
_1.2V_RUN
3
PR5
12
4
5.1K_0402_1%
12
PR5
10.2K_0402_1%
1
2
PR5
3
21.5K_0402_1%
4
ADJ
_2.5V_MEM
PC5
4.7U_0402_6.3V6M
1.2V_RUN
PC5
10
12
17
PC5
@
4.7U_0402_6.3V6M
EN_
2.5V_MEM
12
PC5
@
.1U_0402_16V7K
502
1 2
PAD-OPEN1x1m
PL5
01
1 2
PR5
02
PR5
01
20K_0402_1%
PC5
06
FB_
1.8VALW
PR5
06
10K_0402_1%
+1.2V_RUN
TDC 0.152A
Peak Current 0.218 A
OCP Current 1.5 A fix by IC
VOU
T_1.2V_RUN
12
12
PC5
09
22U_0603_6.3V6M
PC5
0.01UF_0402_25V7K
10
+2.5V_MEN
TDC 0.645A by power budget
AP7361 U-DFN3030-8 Pd limit=1.7W
Peak loading=0.921A.
Pd=(3.3-2.5)*0.921=0.7368W < 1.7W
OCP Current 1.5 A fix by IC
VOU
T_2.5V_MEM
12
12
PC5
15
15
0.01UF_0402_25V7K
12
PR5
16
10K_0402_1%
12
Rup
12
Rdown
PJP
1 2
PAD-OPEN1x1m
11
03
PC5
504
12
68P_0402_50V8J
12
+1.
12
1 2
PAD-OPEN1x1m
PC5
16
22U_0603_6.3V6M
8V_PRIM
01
PC5
22U_0603_6.3V6M
+1.
PJP
12
2V_RUN
506
PCH
_PRIM_EN<11,17,47,87>
+1.
8VALWP
04
PC5
22U_0603_6.3V6M
+2.
5V_MEM
12
12
10K_0402_1%
@
10K_0402_1%
+3.3V_ALW
PR4
17
PR4
19
12
10K_0402_1%
12
@
10K_0402_1%
PR4
PR4
18
VID
VID
20
V
+3.3V_ALW
0_1V_PRIM_CORE
1_1V_PRIM_CORE
in=3~17V
17
PC4
@EMI@
12
0.1U_0402_25V6
PL4
06
@
3A_Z120_40M_0603_2P
1 2
1 2
PJP
PAD-OPEN1x1m
12
18
PC4
2200P_0402_50V7K
@EMI@
404
12
20
PC4
22P_0402_50V8J
RF@
COR
E_VID0<18>
COR
E_VID1<18>
not to short pad
1 2
VR_
LPM_R#<6,87>
PR4
0_0402_5%
PR4
06
1 2
22K_0402_1%
PR4
07
@
1M_0402_1%
VIN
_1V_PRIM_CORE
12
12
13
12
PC4
PC4
10U_0603_10V6M
10U_0603_10V6M
12
21
PC4
0.1U_0402_25V6
RF@
PR4
08
@0@
0_0402_5%
1 2
PR4
11
@0@
0_0402_5%
1 2
+3.3V_ALW
30
12
12
PR4
10
@
10K_0402_1%
VID0 LOGIC
VID1 LOGIC
PJP
402
JUMP_43X79
2
+1.
12
11
_1V_PRIM_CORE
PC4
1V_PRIM_CORE
LPM
EN_
0.1U_0402_25V6
4
16
15
13
1
PU4
02
D1
EN
LPM
PGN
12
PVI
N2
11
PVI
N1
SY8057CQDC_QFN16_3X3
10
AVI
N
9
VID
0
D
1
VID
SS
7
8
0_1V_PRIM_CORE
VID
6
1V_PRIM_CORE
1_1V_PRIM_CORE
SS_
VID
12
28
PR4
@
1M_0402_1%
0V_PRIM_COREP
17
D2
TP
PGN
1
VOS
+1.0V_PRIM_COREP
1UH_1277AS-H-1R0N-P2_3.3A_30%
LX_
1V_PRIM_CORE
2
3
short pad
4
1 2
12
RF@
12
4.7_0603_5%
0_0402_5%
PR3
15
B_1V_PRIM_CORE
SNU
12
RF@
680P_0402_50V7K
short pad
V_PRIM_PWRGD
1.0
PR4
1 2
0_0402_5%
12
PR4
24
@
100K_0402_1%
SW1
SW2
PG
FBS5AGN
_1V_PRIM_CORE
FBS
112
+1.
0V_PRIM_CORE
PL4
04
12
12
15
24
Rup
PR4
09
PC4
19
23
PC4
PC4
22U_0603_6.3V6M
12
22U_0603_6.3V6M
12
27
28
PC4
PC4
10U_0402_6.3V6M
10U_0402_6.3V6M
+1.0V_PRIM_COREP
LPM LOGIC OUTPUT VOLTAGE
0
1 0
SY8057CQDC
1
1
1
Follow WHL
(576715_WHL_U_DDR4_HDK_HW_Design_Kit_Rev0p5)
+1.0V_PRIM_CORE
TDC 2.237 A
Peak Current 3.195A
OCP Current 6.8 A Fix by IC
TYP MAX
Choke DCR 48.0mohm
X
0
1
0
1 1.05
0.75(LPM)
0.9
0.95
1.00
X
0
1
1
DEL
L CONFIDENTIAL/PROPRIETARY
Com
Com
Com
pal Electronics, Inc.
pal Electronics, Inc.
pal Electronics, Inc.
Tit
Tit
Title
le
le
+1V
+1V
+1V
ALWP/VCCIO/PRIM_CORE/1.8V/2.5V/1.2V
ALWP/VCCIO/PRIM_CORE/1.8V/2.5V/1.2V
THI
S SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEP
5
4
3
ARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
2
ALWP/VCCIO/PRIM_CORE/1.8V/2.5V/1.2V
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
LA-
LA-
LA-
891
891
891
87 10
87 10
87 10
of
of
Date: Sh eet
Date: Sh eet
Date: Sh eet
1
of
0.3
0.3
0.3
1Monday, February 25, 2019
1Monday, February 25, 2019
1Monday, February 25, 2019
Page 88
5
4
3
2
1
+1.0V_VCCST
short pad
PR602
0_0402_5%
12
3
PC60
4.7U_0402_6.3V6M
1
PWM_
30
C
FCCM
29
ISUM
28
27
26
C
FB_C
2
5
COMP
24
IMON
23
22
A
21
0
PC63
4
PR64
PC64
2
0.068U_0402_16V7K
1 2
PC64
6
6800P 50V K X7R 0402
1 2
PR65
6
11K_0402_1%
1 2
7
1 2
3
12
ISUM
P_GT <89>
3
1 2
PR603
0_0402_5%
1 2
4
PC60
1U_0402_25V6K
C_SA
_C_SA
N_C_SA
_SA
_C_SA
_C_SA
PWM_
A_GT<89>
FCCM
_A_GT<89>
12
12
0
PR64
2200P_0402_50V7K
1K_0402_1%
PH60
10K_0402_5%_B25/50 4250K
374_0402_1%
12
12
5
PC64
.1U_0402_16V7K
5
+5V_ALW
+13.5VB_CPU
1
12
PC61
0.22U 25V K X5R 0402
12
C_SA
PWM_
8
PC62
ISUM
N_GT <89>
BST_
PWM_
0_0402_5%
PR60
6
12
33P_0402_50V8J
12
3
PC64
330P_0402_50V7K
BST_
SA_R
PU61
4
ISL95808HRZ-TS2778_DFN8_2X2~D
1
UGAT
SA
2
BOOT
SA
3
PWM
GND4LGAT
short pad
12
0
PR63
2.49K_0402_1%
12
1
4700P_0402_25V7K
PC63
12
1
12
PR65
39.2K_0402_1%
12
UG_S
PR61
1 2
E
TP
9
+5V_
PC63
1000P_0402_50V7K
PR64
1 2
316_0402_1%
2
PR65
2K_0402_1%
@
1
PC60
@
680P_0402_50V7K
2
A
9 2.2_0603_5%
8
PHAS
E
7
FCCM
6
VCC
5
E
ALW
1 2
PR63
1 2
2
6
PR64
1 2
1.62K_0402_1%
FCCM
_SA
LG_S
12
0_0402_5%
PR67
12
5
_C_SA
PC68
short pad
FCCM
4.7U_0402_6.3V6M
6 634_0402_1%
1 2
1K_0402_1%
PC64
0
1 2
2200P_0402_50V7K
9
+13.5VB_VCCSA
4
3
D1_3
D1_2
D110D2/S
S2_2
S2_1
A
6
5
9
PR64
1
12
12
12
1
PR60
@
5
7
45.3_0402_1%
+3.3V_RUN
<34,84>
+5V_
ALW
VCC_
<16>
PCH_PWROK<11>
I_SY
SENSE_GT
VIDSCLK<15>
<15>
D D
C C
B B
PROCHOT#<12,34,84>
470K_0402_5%_B25/50 4700K
VCC_
SENSE_IA<15>
VSS_
SENSE_IA<15>
Loca
l sense put on HW site
ISUM
P_IA<89>
PR65
@
20M_0402_5%
ISUM
N_IA<89>
PH60
1 2
1 2
PR63
27.4K_0402_1%
2200P_0402_50V7K
330P_0402_50V7K
0.01UF_0402_25V7K
12
8
1 2
12
2
PH60
10K_0402_5%_B25/50 4250K
1 2
PC605 47P_0402_50V8J
1
1
PC61
1 2
PC61
@
1 2
PC61
9
1 2
8
PR62
1
PC64
4
8
12
4.99K_0402_1%
12
.1U_0402_16V7K
1 2
PR61
10K_0402_1%
1 2
PR61
7
4.3K_0402_1%
1 2
PC61
6
@
68P 50V J NPO 0402
1 2
12
3
PR63
11K_0402_1%
PC63
U42@
0.022U_0402_16V7K
1 2
PC63
U42@
0.022U_0402_16V7K
1 2
PR678
100_0402_1%
0
@
PC624
@
5
8
ISEN
ISEN
VIDALERT_N
VIDSOUT<15>
PR61
3
@
97.6K_0402_1%
1 2
PC61
3
330P_0402_50V7K
1 2
PR62
@
1200P_0402_50V7K
12
@
PC620
680P_0402_50V7K
0.082U_0402_16V7K
12
@
0.022U_0402_25V7K
1_IA<89>
2_IA<89>
PC62
6
PC62
PC61
1 2
0.1U_0402_25V6
7
2.49K_0402_1%
1
1 2
1K_0402_1%
@
1 2
PR62
@
1 2
1 2
PR63
2
1 2
@
523_0402_1%
1 2
ISEN
ISEN
U22@
1
316_0402_1%
2
PR62
3
2K_0402_1%
PR63
8
1_IA
2_IA
PR63
0_0402_5%
1 2
1 2
U22@
0_0402_5%
PC62
2200P_0402_50V7K
1 2
4
PR61
no short pad and depop 0ohm for PR615,PR634
Local sense put on HW site
A A
VSS_
SENSE_GT<16>
5
4
12
5
4
PR60
PR60
75_0402_1%
100_0402_1%
short pad
PR612 1.91K_0402_1%
IMVP_VR_ON<35>
PR614 0_0402_5%
PR616 0_0402_5%
short pad
PR62
0
0_0402_5%
1 2
S
PR69
3
11.8K_0402_1%
1 2
IMON
NTC_
COMP
FB_B
ISUM
N_B_IA
FCCM
_B_IA<89>
<89>
PWM1
_B_IA
PWM2
_B_IA<89>
PH60
3
470K_0402_5%_B25/50 4700K
1 2
PR64
7
27.4K_0402_1%
1 2
PC62
2200P_0402_50V7K
1 2
33P_0402_50V8J
PC63
9
1500P_0402_50V7K
1 2
1 2
PR64
1.91K_0402_1%
PC65
@
1 2
330P_0402_50V7K
PC65
4
1 2
0.01UF_0402_25V7K
2
PC60
0.1U_0402_25V6
1 2
1 2
1 2
1 2
1 2
short pad
_CPU_CORE
PSYS
_B_IA
B_IA
_B_IA
_IA
10
4
330P_0402_50V7K
86.6K_0402_1%
1 2
9
3.09K_0402_1%
1 2
PC63
6
1 2
8
1
1 2
PR625
PU60
2
1
PSYS
2
IMON
3
NTC_
4
COMP
5
FB_B
6
RTN_
7
ISUM
8
ISUM
9
ISEN
ISEN
1
AGND
PC62
5
1 2
PR62
9
1 2
PR63
10K_0402_1%
PR63
9
PR64
5
316_0402_1%
1 2
PR62610_0402_1%
_B
B
B
P_B
N_B
1_B
2_B
PR61849.9_0402_1%
_B
5
0_0402_5%
NABLE_CPU_CORE
VR_E
40
11
12
12
3
PC65
@
12
1 2
PR608
100K_0402_5%
1 2
PR61
9.31K_0402_1%
CPU_CORE
2_CPU_CORE
1_CPU_CORE
CPU_CORE
EADY_CPU_CORE
OT#_CPU_CORE
_DAT_PWR_CPU
_ALERT#_PWR_CPU
_CLK_PWR_CPU
VIN_
VCC_
PROG
SVID
SVID
PROG
VR_R
VR_H
SVID
7
3
35
34
33
31
32
36
38
39
EADY
NABLE
VR_R
VR_E
_B
_B
FCCM
PWM1
12
13
0
PR65
PC64
680P_0402_50V7K
12
2
1
T#
VIN
OT#
SDA
VCC
SCLK
PROG
PROG
ALER
VR_H
_B
PWM2
14
_A_GT
IMON
2K_0402_1%
0.082U_0402_16V7K
PWM_
FCCM
_C
ISUM
N_C
ISUM
P_C
RTN_
FB_C
COMP
_C
IMON
_C
PWM_
FCCM
_A
_A
A
A
_A
P_A
N_A
FB_A
IMON
NTC_
COMP
RTN_
ISUM
ISUM
7
15
16
18
19
20
1
ISL95857CHRTZ-T_TQFN40_5X5
_A_GT
A_GT
_GT
N_A_GT
FB_A
NTC_
COMP
ISUM
7
PR65
4.42K_0402_1%
1 2
PR65
@
20M_0402_5%
THIS
SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VCC_SA U42
TDC 4.0A
Peak Current 6A
OCP current 10A
Choke DCR 6.2 m ohm
PJP603
1 2
PAD-OPEN1x1m
+13.5VB
+13.5VB_VCCSA
12
12
2
8
PC61
PC60
10U 25V M X5R 0603 ZRB
10U 25V M X5R 0603 ZRB
2
1
PQ614
AONH
36334 2N DFN3X3A
G1
D1_1
LX_S
A
9
1
RF@
7
PC63
0.033U_0402_25V7K
PC64
1 2
PC65
@
Compa
Compa
Compa
4
0
CPU_C
CPU_C
CPU_C
12
7
PR62
4.7_1206_5%
_SA
SNUB
12
2
PC62
RF@
680P_0402_50V7K
12
12
l Electronics, Inc.
l Electronics, Inc.
l Electronics, Inc.
LA-8
LA-8
LA-8
S2_3
G2
7
8
12
.1U_0402_16V7K
0.082U_0402_16V7K
DELL
CONFIDENTIAL/PROPRIETARY
Titl
Titl
Title
e
e
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
12
P_SA
ISUM
3
PC63
4700P 25V K X7R 0402
PC64
0.01UF_0402_25V7K
330P_0402_50V7K
ORE
ORE
ORE
91
91
91
1
PR62
12
1 2
@
1 2
PL61
4
0.47UH_MMD05CZR47M_12A_20%
1
4
3
3.65K_0603_1%
3
PR64
9
PC65
+VCC
2
4
N_SA
ISUM
ISUM
P_SA
12
2
PR64
2.61K_0402_1%
12
10KB_0402_5%
11K_0402_1%
4
PH60
ISUM
N_SA
VSS_
SENSE_SA
2
VCC_
SENSE_SA
88 101M
88 101M
88 101M
of
of
of
_SA
<17>
<17>
0.3
0.3
0.3
Page 89
5
PJP601
1 2
+13.5VB_CPU
RF@
12
12
+5V
+5V
_ALW
_ALW
82
PC6
10U 25V M X5R 0603 ZRB
1_0603_ 5%
1 2
FCC
PWM
83
PC6
U42@
10U 25V M X5R 0603 ZRB
D D
C C
B B
A A
PR6
M_B_IA<88,89>
12
<88,89>
12
56
PC6
88
1_B_IA<88,89>
10U 25V M X5R 0603 ZRB
12
84
PC6
U42@
FCC
PWM
57
PC6
86
PC6
12
12
10U 25V M X5R 0603 ZRB
12
U42@
1_0603_ 5%
1 2
M_B_IA<88,89>
2_B_IA
10U 25V M X5R 0603 ZRB
0.1U_0402_25V6
76
PC6
72
PC6
U42@
10U 25V M X5R 0603 ZRB
88
PC6
U42@
PR6
58
PC6
10U 25V M X5R 0603 ZRB
BST1_IA_R
4.7U_0402_6.3V6M
PR6
0_0402_ 5%
1 2
PR6
0_0402_ 5%
1 2
12
PC673
U42@
0.1U_0402_25V6
91
12
59
87
12
10U 25V M X5R 0603 ZRB
12
PC677
U42@
0_0402_ 5%
1 2
0_0402_ 5%
1 2
short pad
RF@
59
PC6
0.1U_0402_25V6
PC6
55
1 2
0.22U_04 02_25V 6K
1 2
PR6
60
3.9_060 3_1%
short pad
94
12
PC693
PC6
18P 50V K 0402
RF@
RF@
100P_0402_50V8J
PC6
71
U42@
1 2
0.22U_04 02_25V 6K
1 2
BST2_IA_R
U42@
PR6
3.9_060 3_1%
4.7U_0402_6.3V6M
PR6
71
PR6
92
12
12
72
1
06
12
60
PC6
2
PC6
100U_D_20VM_R55M
2200P_0402_50V7K
PU6
10
PGN
9
VIN
8
VIN
7
PHA
6
NC1
BST
1_IA
5
BOO
4
AGN
VCC
1_IA
3
VCC
FCC
M1_IA
2
FCC
PWM
1_IA
1
PWM
FDMF3035 PQFN31 DR MOS D/CAFTER1835
10
9
8
7
6
BST
2_IA
5
4
VCC
2_IA
3
FCC
M2_IA
2
PWM
2_IA
1
PAD-OPEN 4x4m
PL602
@EMI@
1 2
9A Z80 10M 1812_2P
1
1
+
10
D1
2
1
SE
T
D1
M
U42@
PGN
VIN
VIN
PHA
NC1
BOO
AGN
VCC
FCC
PWM
FDMF3035 PQFN31 DR MOS D/CAFTER1835
+
+
07
627
PC6
PC1
2
2
@
68U_D_20VM_R55M
100U_D_20VM_R55M
1
1
SW1
1
2
SW2
1
3
GL1
14
PGN
D2
15
PVC
C
1
6
NC2
1
7
NC3
1
9
GL2
18
AGN
D2
PU6
13
1
1
SW1
D1
1
2
SW2
2
1
3
GL1
1
14
PGN
SE
D2
15
PVC
C
1
6
NC2
T
1
7
NC3
D1
1
9
GL2
M
18
AGN
D2
+13.5VB
89
PC6
RF@
LX1
4
100P_0402_50V8J
+5V
12
_IA
12
90
PC6
RF@
_ALW
61
PC6
LX2
+5V
12
_IA
100P_0402_50V8J
4.7U_0402_6.3V6M
12
_ALW
97
PC6
U42@
4.7U_0402_6.3V6M
3
VCC_core (U42)
TDC 48A
Peak Current 70A
OCP current 84A
92
12
12
91
PC6
1U_0402_25V6K
RF@
RF@
63
PR6
Choke DCR 0.9 +-7%m ohm
PC6
Follow as below
22P_0402_50V8J
RF@
WHL U42 15W, Core (IA) VR TDC value has been increased from 42A to 48A.
This new value will be reflected in WHL PDG/Power Map document next release
in WW13 (IBP# 575412).
PL610
0.15UH_MMD-06CZER15 MEX5L__ 35A_20 %
1
4
PR6
67
ISE
N1_IA<88>
ISE
N2N_IA
<88,89>
U42@
3.65K_0 603_1%
1 2
<88>
MP_IA
<88,89>
ISU
3
N1P_IA
PR6
68
U42@
ISE
1 2
100K_04 02_1%
1 2
PR6
70
@
100K_04 02_1%
U42@
PL6
13
0.15UH_MMD-06CZER15 MEX5L__ 35A_20 %
4
3
N2P_IA
74
N2_IA
N1N_IA
U42@
ISE
1 2
100K_04 02_1%
@
1 2
100K_04 02_1%
PR6
PR6
77
PR6
ISE
ISE
12
3.65K_0 603_1%
1 2
4.7_1206_5%
B1_IA
SNU
12
62
MP_IA
PC6
ISU
RF@
680P_0402_50V7K
12
76
PR6
4.7_1206_5%
U42@
RF@
B2_IA
SNU
78
12
PC6
680P_0402_50V7K
RF@U42@
+VC
ISE
N1N_IA
PR6
10_0402 _1%
<88,89>
1
2
66
ISE
12
MN_IA
ISU
N2N_IA
U42@
10_0402 _1%
<88,89>
C_CORE
PR6
73
2
12
MN_IA
ISU
75
+VC
C_CORE
+5V
_ALW
75
PC6
10U 25V M X5R 0603 ZRB
12
74
PC6
10U 25V M X5R 0603 ZRB
12
87
PC6
0.1U_0402_25V6
PR6
80
1_0603_ 5%
1 2
FCC
PWM
12
12
12
65
64
PC6
PC6
10U 25V M X5R 0603 ZRB
10U 25V M X5R 0603 ZRB
12
69
PC6
4.7U_0402_6.3V6M
short pad
PR6
0_0402_ 5%
1 2
M_A_GT<88,89 >
_A_GT<88,8 9>
PR6
0_0402_ 5%
1 2
67
PC6
RF@
_GT_R
0.22U_04 02_25V 6K
1 2
BST
3.9_060 3_1%
62
64
2
+13
.5VB_VCCGT
12
66
PC6
1U_0402_25V6K
RF@
100P_0402_50V8J
PC6
63
1 2
PR6
65
12
+13
.5VB_VCCGT
PU6
12
10
PGN
9
VIN
2
8
VIN
1
7
PHA
SE
6
NC1
BST
_GT
5
BOO
4
AGN
VCC
_GT
3
VCC
FCC
M_GT
2
FCC
PWM
M
_GT
1
PWM
FDMF3035 PQFN31 DR MOS D/CAFTER1835
1
VCC_GT (U42)
TDC 18A
Peak Current 31A
OCP current 37.2A
Choke DCR 0.9 +-7%m ohm
PJP
602
21
+13
PR6
_ALW
68
PC6
4.7U_0402_6.3V6M
.5VB_CPU
69
EMI@
SNU
B_GT
PL6
0.15UH_MMD-06CZER15 MEX5L__ 35A_20 %
4
3
12
PR6
61
3.65K_0 603_1%
<88>
MP_GT
ISU
PC6
70
680P_04 02_50V 7K
1 2
12
1
2
+VC
C_GT
<88>
MN_GT
ISU
PAD-OPEN 1x2m~D
EMI@
4.7_120 6_5%
1 2
LX_
GT
1
1
SW1
D1
1
2
SW2
1
3
GL1
14
PGN
D2
15
PVC
C
1
6
NC2
T
1
7
NC3
D1
1
9
GL2
18
AGN
D2
+5V
12
DEL
L CONFIDENTIAL/PROPRIETARY
THI
S SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS
5
4
3
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRON ICS, INC.
2
Com
Com
Com
pal Electronics, Inc.
pal Electronics, Inc.
Tit
Tit
Title
le
le
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronics, Inc.
CPU
CPU
CPU
_CORE
_CORE
_CORE
LA-
LA-
LA-
891
891
891
1
89 10
89 10
89 10
of
of
of
0.3
0.3
0.3
1Monday, February 25, 2019
1Monday, February 25, 2019
1Monday, February 25, 2019
Page 90
A
B
C
D
E
+VCC_CORE
12
12
00
PC10
1 1
2 2
22U_0603_6.3V6M
12
12
11
PC10
22U_0603_6.3V6M
12
12
31
PC10
1U_0201_6.3V6M
12
12
51
PC10
1U_0201_6.3V6M
12
12
PC1001
22U_0603_6.3V6M
12
PC1012
22U_0603_6.3V6M
12
PC1032
1U_0201_6.3V6M
12
PC1052
1U_0201_6.3V6M
12
12
03
02
PC10
22U_0603_6.3V6M
13
PC10
22U_0603_6.3V6M
33
PC10
1U_0201_6.3V6M
53
PC10
1U_0201_6.3V6M
04
PC10
PC10
22U_0603_6.3V6M
22U_0603_6.3V6M
12
12
12
14
15
PC10
PC10
22U_0603_6.3V6M
22U_0603_6.3V6M
12
12
12
12
35
34
PC10
PC10
1U_0201_6.3V6M
1U_0201_6.3V6M
12
12
55
54
PC10
PC10
1U_0201_6.3V6M
1U_0201_6.3V6M
12
12
06
05
PC10
PC10
22U_0603_6.3V6M
22U_0603_6.3V6M
12
12
16
17
PC10
PC10
22U_0603_6.3V6M
22U_0603_6.3V6M
12
12
36
37
PC10
PC10
1U_0201_6.3V6M
1U_0201_6.3V6M
12
12
56
57
PC10
PC10
1U_0201_6.3V6M
1U_0201_6.3V6M
12
12
07
PC10
22U_0603_6.3V6M
18
PC10
22U_0603_6.3V6M
38
PC10
1U_0201_6.3V6M
58
PC10
1U_0201_6.3V6M
09
08
PC10
PC10
22U_0603_6.3V6M
22U_0603_6.3V6M
12
12
19
20
PC10
PC10
22U_0603_6.3V6M
22U_0603_6.3V6M
12
12
12
39
40
PC10
PC10
1U_0201_6.3V6M
1U_0201_6.3V6M
12
12
12
59
60
PC10
PC10
1U_0201_6.3V6M
1U_0201_6.3V6M
+VCC_CORE Place on CPU:
22U_0603 *20 pcs
1U_0201 *42 pcs
47U_0603 *10 pcs +reserve 8 pcs
330u_D2 *1 pcs
330u_D3 *3pcs
12
12
12
41
PC10
1U_0201_6.3V6M
61
PC10
1U_0201_6.3V6M
43
42
PC10
PC10
1U_0201_6.3V6M
1U_0201_6.3V6M
12
12
12
63
62
PC10
PC10
1U_0201_6.3V6M
1U_0201_6.3V6M
12
12
44
PC10
1U_0201_6.3V6M
12
64
PC10
1U_0201_6.3V6M
12
46
45
PC10
PC10
1U_0201_6.3V6M
1U_0201_6.3V6M
12
12
66
65
PC10
PC10
1U_0201_6.3V6M
1U_0201_6.3V6M
12
12
48
47
PC10
1U_0201_6.3V6M
67
PC10
1U_0201_6.3V6M
49
PC10
PC10
1U_0201_6.3V6M
1U_0201_6.3V6M
12
12
69
68
PC10
PC10
1U_0201_6.3V6M
1U_0201_6.3V6M
+VCC_GT
12
12
12
12
50
PC10
1U_0201_6.3V6M
12
70
PC10
1U_0201_6.3V6M
12
1
+
2
12
02
01
PC11
PC11
22U_0603_6.3V6M
22U_0603_6.3V6M
12
12
16
17
PC11
PC11
22U_0603_6.3V6M
22U_0603_6.3V6M
12
12
31
32
PC11
PC11
1U_0201_6.3V6M
1U_0201_6.3V6M
1
+
42
43
PC11
PC11
2
330U_D3_2.5VY_R6M
330U_D3_2.5VY_R6M
12
12
03
PC11
22U_0603_6.3V6M
12
18
PC11
22U_0603_6.3V6M
12
33
PC11
1U_0201_6.3V6M
12
05
04
PC11
PC11
22U_0603_6.3V6M
22U_0603_6.3V6M
12
12
19
20
PC11
PC11
22U_0603_6.3V6M
22U_0603_6.3V6M
12
12
34
35
PC11
PC11
1U_0201_6.3V6M
1U_0201_6.3V6M
46
12
12
PC11
100P_0201_25V8J
@RF@
12
12
06
07
PC11
PC11
22U_0603_6.3V6M
22U_0603_6.3V6M
12
12
22
21
PC11
PC11
22U_0603_6.3V6M
22U_0603_6.3V6M
12
12
36
37
PC11
PC11
1U_0201_6.3V6M
1U_0201_6.3V6M
47
PC11
100P_0201_25V8J
@RF@
12
12
08
PC11
22U_0603_6.3V6M
23
PC11
22U_0603_6.3V6M
12
38
PC11
1U_0201_6.3V6M
12
10
09
PC11
PC11
22U_0603_6.3V6M
22U_0603_6.3V6M
12
12
39
40
PC11
PC11
1U_0201_6.3V6M
1U_0201_6.3V6M
+VCC_GT Place on CPU:
22U_0603 *23 pcs
1U_0201 *11 pcs
330u_D3 *2 pcs
12
11
PC11
22U_0603_6.3V6M
41
PC11
1U_0201_6.3V6M
12
12
12
PC11
22U_0603_6.3V6M
12
14
13
PC11
22U_0603_6.3V6M
15
PC11
PC11
22U_0603_6.3V6M
22U_0603_6.3V6M
12
3 3
12
4 4
A
12
12
71
PC10
47U_0603_6.3V6M
12
89
PC10
1U_0201_6.3V6M
12
12
73
74
PC10
PC1072
47U_0603_6.3V6M
PC1090
1U_0201_6.3V6M
PC10
47U_0603_6.3V6M
47U_0603_6.3V6M
1
1
+
+
91
PC10
2
2
330U_D2_2.5VM_R9M
12
12
76
75
PC10
PC10
47U_0603_6.3V6M
47U_0603_6.3V6M
1
1
93
+
+
92
PC10
PC10
2
2
330U_D3_2.5VY_R6M
330U_D3_2.5VY_R6M
12
12
77
78
PC10
PC10
47U_0603_6.3V6M
47U_0603_6.3V6M
94
PC10
330U_D3_2.5VY_R6M
U42@
12
12
79
80
PC10
PC10
47U_0603_6.3V6M
47U_0603_6.3V6M
96
12
12
PC10
100P_0201_25V8J
@RF@
B
12
12
81
PC10
22U_0603_6.3V6M
@
97
12
PC10
100P_0201_25V8J
@RF@
12
83
82
PC10
PC10
22U_0603_6.3V6M
22U_0603_6.3V6M
@
@
99
98
12
12
PC10
PC10
RF@
RF@
100P_0201_25V8J
100P_0201_25V8J
12
12
84
85
PC10
PC10
22U_0603_6.3V6M
22U_0603_6.3V6M
@
@
00
12
12
00
PC11
PC12
RF@
100P_0201_25V8J
RF@
1000P_0402_50V7K
THIS
SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
12
12
88
87
86
PC10
PC10
PC10
22U_0603_6.3V6M
@
12
01
PC12
0.1U_0402_25V6
RF@
22U_0603_6.3V6M
22U_0603_6.3V6M
@
@
02
PC12
18p_0402_50V6
RF@
C
+VCC
_SA
12
12
51
PC11
22U_0603_6.3V6M
66
12
12
PC11
100P_0201_25V8J
@RF@
12
12
12
53
52
PC11
PC11
22U_0603_6.3V6M
22U_0603_6.3V6M
67
68
12
12
PC11
PC11
RF@
100P_0201_25V8J
100P_0201_25V8J
@RF@
12
54
55
PC11
PC11
22U_0603_6.3V6M
22U_0603_6.3V6M
69
70
12
12
PC11
PC11
18p_0402_50V6
RF@
22P_0402_50V8J
RF@
DELL
Titl
Titl
Titl
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
D
Date: Sheet
12
12
56
57
PC11
PC11
22U_0603_6.3V6M
22U_0603_6.3V6M
71
+VCC_SA Place on CPU
22U_0603 *11 pcs
PC11
0.1U_0402_25V6
RF@
12
12
58
PC11
22U_0603_6.3V6M
12
60
59
PC11
22U_0603_6.3V6M
61
PC11
PC11
22U_0603_6.3V6M
22U_0603_6.3V6M
CONFIDENTIAL/PROPRIETARY
Comp
Comp
Comp
al Electronics, Inc.
al Electronics, Inc.
e
e
e
onday, February 25, 2019
onday, February 25, 2019
onday, February 25, 2019
al Electronics, Inc.
CPU
CPU
CPU
Decoupling CAP
Decoupling CAP
Decoupling CAP
LA-8
LA-8
LA-8
91
91
91
E
90 101M
90 101M
90 101M
0.3
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D D
C C
Vf 1.9056V-1.98V-2.0544V
B B
VIN 4.9952V-5.19V-5.3848V
P3000 Vf = 0.32V @1mA
A A
5
4
+13
+3.
3V_VDD_DCIN
4
.5VB
+VC
PR3
006
@0@
0_0402_5%
1 2
PD3
3
2
BAT54CW_SOT323-3
C_CORE
000
1
PR3
002
200K_0402_1%
1 2
PR3
003
300K_0402_1%
1 2
PC3
001
@
82P_0201_50V8J
1 2
PR3
004
200K_0402_1%
1 2
PR3
005
402K_0402_1%
1 2
PC3
003
@
82P_0201_50V8J
1 2
PR3
007
237K_0402_1%
1 2
PR3
008
43.2K_0402_1%
1 2
PC3
@
82P_0201_50V8J
1 2
+3.
3V_VDD_DCIN
004
3
PC3
0.01UF 25V +-10% X7R 0402
1 2
AZV
Icc=12uA_max
Vout=3.15V@Vcc=3.3V and Io=3mA
PU3000
AZV
3002RL-7_U-FLGA8_1P65X1P65
8
2
IN-
3
IN+
6
IN-
5
IN+
VCC
-
1
1
2
2
OUT
+
-
OUT
+
VEE
4
Vref 0.72V-0.75V-0.78V
PR3
009
@
14.7K_0402_1%
1 2
PR3
010
147K_0402_1%
1 2
PR3
3
011
43.2K_0402_1%
1 2
PC3
005
1 2
0.22U_0402_10V K
3.3V+-4%
002
3002
1
2
ACA
ACA
1
7
V_IN1
V_IN
PR3
012
1K_0201_1%
1 2
1 2
PR3
013
1K_0201_1%
2
PD3
001
RB520SM-30T2R_EMD2-2
2 1
NO_
SMOKE_OVP
1U_0201_6.3V6M
12
RB520SM
Vf =0.29V@1mA
Ir =1uA @Vr=10V
1U_0201_6.3V6M
12
PC3
PC3
008
009
NO_
SMOKE_UVP
1U_0201_6.3V6M
12
21
2
PC3
010
PD3
002
RB520SM-30T2R_EMD2-2
1
not to short pad
PR3
001
0_0402_5%
1 2
34
5
000B
PQ3
61
2
1U_0201_6.3V6M
12
PC3
011
Tit
Tit
Title
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
000A
PQ3
Compa
Compa
Compa
Char
Char
Char
L2N7002DW1T1G 2N SC88-6
L2N7002DW1T1G 2N SC88-6
l Electronics, Inc.
l Electronics, Inc.
l Electronics, Inc.
ger UVP/VCORE OVP
ger UVP/VCORE OVP
ger UVP/VCORE OVP
LA-
LA-
LA-
891
891
891
ACI
N_CHG
91 10
91 10
91 10
1
of
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of
0.3
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0.3
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CONFIDENTIAL/PROPRIETARY
Comp
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THIS
SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D
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onday, February 25, 2019
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al Electronics, Inc.
rve for PWR
rve for PWR
DB-2
DB-2
283P
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92 101M
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Com
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Res
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pal Electronics, Inc.
DB-
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2283P
2283P
93 10
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1
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1Monday, February 25, 2019
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S SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D
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CONFIDENTIAL/PROPRIETARY
Comp
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al Electronics, Inc.
Titl
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Rese
THIS
SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITH ER THIS SHEET NOR THE IN FORMATION IT CONTAINS
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Size Document Number Rev
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onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
rve for PWR
rve for PWR
DB-2
DB-2
283P
283P
1
0.1
94 101M
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Res
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pal Electronics, Inc.
DB-
DB-
2283P
2283P
95 10
95 10
1
0.1
0.1
1Monday, February 25, 2019
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of
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THI
S SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D
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C C
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THIS
SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D
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Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
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Date: Sheet
Date: Sheet
al Electronics, Inc.
rve for PWR
rve for PWR
DB-2
DB-2
283P
283P
1
0.1
96 101M
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Res
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erve for PWR
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pal Electronics, Inc.
DB-
DB-
2283P
2283P
97 10
97 10
1
0.1
0.1
1Monday, February 25, 2019
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of
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THI
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AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D
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THIS
SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF TH E COMPETENT DIVISION OF R&D
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al Electronics, Inc.
rve for PWR
rve for PWR
DB-2
DB-2
283P
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1
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U42
PC626 U42@
PR613 U42@
PR621 U42@
PC624 U42@
PC621 U42@
D D
0.1U_0402_10%
97.6K_0402_1%
PR622 U42@
2.49K_0402_1%
316 _0402_1%
PC616 U42@
68P_0402_5%
0.022U_0402_10%
PC617 U42@
1200P_0402_10%
680P_0402_10%
U22
26 U22@
38 U22@
PR6
84.
5K_0402_1%
PR6
1.6
PC6
0.0
47U_0402_10%
PR6
412
_0402_1%
C C
13 U22@
22 U22@
5K_0402_1%
PR6
316
PC6
33P
21 U22@
_0402_1%
16 U22@
_0402_5%
PC6
24 U22@
0.0
33U_0402_10%
PC6
17 U22@
120
0P_0402_10%
PC6
21 U22@
820
P_0402_10%
B B
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Res
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Res
erve for PWR
erve for PWR
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pal Electronics, Inc.
LA-
LA-
LA-
891
891
891
100 1
100 1
100 1
1
0.3
0.3
0.3
01Monday, February 25, 2019
01Monday, February 25, 2019
01Monday, February 25, 2019
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of
of
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Version Change List ( P. I. R. List )
Version Change List ( P. I. R. List )
Version Change List ( P. I. R. List )Version Change List ( P. I. R. List )
Item
Item
Page#
Page#
ItemItem
Page#Page#
1
P089
P082
P086
2
P088
D D
P089
P090
3
P088
P099
4
Date
Date Solution Description
DateDate
06/04
06/08
07/02
07/12
07/13
Fairchild & AOS Dr.MOS vendor remove PVCC reserved resistor
Change to common PN
Merion Top side Z-height limitation
CPU tune value by intersil
4
Issue Description
Issue Description
Issue DescriptionIssue Description
3
Delete reserved PR686/PR689/PR681 on PVCC side
1. PC624 change to SE076223K80 (S CER CAP 0.022U 16V K X7R 0402)
2. PC804 change to SE074221K80 (S CER CAP 220P 50V K X7R 0402)
3. PC633 change to SE075472K80 (S CER CAP 4700P 25V K X7R 0402)
4. PL201 change to SH00000YE00 (common P/N)
5. PL614 change to SH00001ED00 (common P/N)
1. Un-stuff PC1094 (U42@)
2. Add stuff PC1095 - 330uF (Bottom side)
1. Change the PR636 from 665 Ohm to 634 Ohm. - (VCCSA Ri)
-> SD00000Z280, S RES 1/16W 634 +-1% 0402
2. Change the PR640 from 374 Ohm to 365 Ohm. - (VCCGT Ri)
-> SD034365080, S RES 1/16W 365 +-1% 0402
3. Change the PC646 from 0.047uF to 0.0022uF. - (VCCGT RC)
-> SE075222K80, S CER CAP 2200P 25V K X7R 0402
4. Change the PC642 from 0.033uF to 0.068uF. - (VCCGT RC)
-> SE000003J80, S CER CAP 0.068U 16V K X7R 0402
5. Change the PC621 from 680pF to 820pF. - (VCCIA FB RC).
-> SE000008980, S CER CAP 820P 25V K X7R 0402
6. Change the PR611 from 1.87kOhm to 9.31kOhm. - (PROG2)
-> SD034931180, S RES 1/16W 9.31K +-1% 0402
2
Solution Description
Solution DescriptionSolution Description
1
Rev.
Rev.
Rev.Rev.
X01
X01
X01
X01
P082
5
P083
P082
6
P082
7
P082
8
C C
07/20 X01
07/30
07/30
08/10
LPS function test fail on G3 mode. Need to return LDO(PU2) design circuit.
PQ8 gate for non-Backdrive issue Add R/C delay PR865/PC865 : 100K(SD028100380) and 0.1uF_0402_25V(SE00000G880)
LM393 resistor value fine tune
9
10
11
P082
P083
12
P082
P083
13
14
B B
P083 08/21
15
16
P082 X01
17
18
19
P089
P090 08/22
20
P089 X01
21
22
A A
23
08/10ALL
08/15
08/15
08/15P087
08/20 X01
08/22
09/11
08/22
08/23P087
5
Intel validation tune value by Intersil FAE
Check and modify connector P/N PJPDC1 - SP02001A500
R/C delay fine tune for WHL bring up sequence
RTC issue
Smokeless circuit for Vcore
LPS function modify
Modify 1 barrel / 1 Type-C External LDO circuit for No Smoke design
CPU VR input Low noise MLCC PCB footprint update : C_0603-S3
Un-stuffed CPU +VCC_CORE output MLCC change value Change reserve location from 47uF to 22uF (Keep un-stuff) PC1081 / PC1082 / PC1083 / PC1084 / PC1085 / PC1086 / PC1087 / PC1088 X01
Remove double net name Remove PU610 / PU612 / PU613 Dr.MOS pin 15(PVCC) double net name
Change PU301, PU501 powergood connection netname Change connection to 1.0V_PRIM_PWRGD from 1.8V_PRIM_PWRGD (PU301, PU501)
R/C for WHL sequence
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
PD1, PD2, change to SCA00002A00 for ESD demandESD request
Need stuff item : PU2/ PC10/ PC11/ PR47/ PR33/ PR27/ PR17/ PD800 / PR806 / PR809/ PR832/ PR859 / PR810 / PR813
Need delete location : PR48 / PR34 / PR35 / PR36 / PR37/ PR847 / PR848 / PR849/ PR850
Need un-stuff item : PR851 / PR860 / PR852
PR800 change to 422K_0402_1% (SD034422380)
PR815 change to 37.4K_0402_1% (SD034374280)
PR832 change to 102K_0402_1% (SD028102380)
PR843 change to 37.4K_0402_1% (SD034374280)
PR831 change to 1M_0402_1% (SD034100480)
PR842 change to 191K_0402_1% (SD034191380)
PR651 value change to 39.2K for ISL95857CISL95857C solution08/10P088 X01
Change the PR629 from 90.9kOhm to 86.6kOhm. IMON of GT
Change the PR636 from 665 Ohm to 634 Ohm. Ri of SA
Change the PR651 from 78.7kOhm to 39.2kOhm. IMON of SA.
Change the PR611 from 1.87kOhm to 9.31kOhm. PROG2
Change the PC646 from 2200pF to 6800pF. Cn of GT.
Re-define the RTC/DCIN/Battery connector from @ to CONN@.Follow Schematic naming rule
PBATT1 - SP02001A700
JRTC1 - SP02000RO00
1. Modify PR312 / PR406 value from 0 ohm to 22K_0402_1% (SD034220280)
2. PC411 change to stuff
3. Add PC360 : 0.1uF_0402_25V (SE00000G880)
Un-stuff PR505 / PR407P091 Remove double pull down resistor
Add RTC detect circuit
1. Add PR9 10Mohm
2. Add PQ13 MOS
Add smokeless circuit for Vcore X01P091 08/22
1. Add un-stuff PR870 and pull up source is +20V_VBUS_DC_SS ; 499K_0402_1% (SD034499380)
2. Modify PR831 value to 499K_0402_1% (SD034499380) and pull up source change to +20V_TBTA_VBUS_1
3. Modify PR842 value to 97.6K_0402_1% (SD034976280)
4. PC811 change to SE00000UD00 (10U 6.3V M X5R 0402)
1. PD800 change to un-stuff
2. Add PR866 0_0402_5%
3. Add PD803 (BAT54CW_SOT323-3)
4. Add un-stuff PR868 0_0603_5%
IA input : PC658 / PC657 / PC656 / PC682 / PC683 / PC684 / PC672 / PC673
GT input : PC675 / PC674 / PC664 / PC665
SA input : PC612 / PC608
IA output : PC1071 / PC1072 / PC1073 / PC1074 / PC1075/ PC1076 / PC1077 / PC1078 / PC1079 / PC1080
1. Add PR313 : 100K_0402_5%
2. Add PR314 / PR315 : 0 ohm
3. Reserve PC350 footprint to PG (1.0V_PRIM_PWRGD) signal
DELL
CONFIDENTIAL/PROPRIETARY
Comp
Comp
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Date: Sheet
Date: Sheet
2
Date: Sheet
al Electronics, Inc.
PWR
PWR
P.I.R
P.I.R
1
100 10
100 10
X01
X01
X01
X01
X01
X01
X01
X01
X0108/22P082
X0108/22P088
X01
X01P087 08/28
0.3
0.3
6Monday, February 25, 2019
6Monday, February 25, 2019
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