DELL EDC41 Schematics
5
4
3
2
1
COMPAL CONFIDENTIAL
MODEL NAME :EDC41
D D
PCB NO :LA-G891P
14 WHL-U UMA(non TBT)
BOM P/N :XXXXX
Whiskey Lake U42
2019-02-12
REV : 1.0 (A00)
@ : Nopop Component
EMI@ : EMI Component
@EMI@ : EMI Nopop Component
C C
B B
ESD@ : ESDComponent
@ESD@ : ESD Nopop Component
RF@ : RF Component
@RF@ : RF Nopop Component
CONN@ : Connector Component
DS3@ : Deep sleep support
NDS3@ : non Deep sleep support
CXDP@ : XDP Component
RTD3@ : RTD Component
NRTD3@ : RTD Component
ST33@ : ST TPM Component
Par
t Number
Description
DA8001GT000
A A
COPYRIGHT 2017
ALL RIGHT RESERVED
REV:X00
PWB:
PCB 2FB LA-G891P REV0 MB UU NAR 1
Layout Dell logo
Power CKT :
5
GPIO map :
NORTHBAY 14UU_WHL_PWR_0128
X10
_CSLP GPIO map Rev1.3_20180529
4
750@ : NUVOTON TPM Component
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
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Tit
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Size Document Number Rev
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Date: Sheet
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Date: Sheet
pal Electronics, Inc.
Cov
Cov
Cov
er Sheet
er Sheet
er Sheet
LA-
LA-
LA-
G891P
G891P
G891P
1
1 10
1 10
1 10
0.3
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
2Monday, February 25, 2019
of
of
of
5
www.schematic-x.blogspot.com
4
3
2
1
Northbay 15U UMA_NAR Block Diagram
Memory BUS (DDR4)
DDR4 2400MHz for WHL-U
Up to 2x16GB Modules
D D
TX/RX
Type C CONN.
CC
P45
Card reader
RTS5242
uSD4.0
PCIE[8]
P70
P70
C C
PCIE[9]
Intel Jacksonville
WGI219(LM/V)
Transformer
RJ45
P51
P51
P51
HDMI
CONN
DP SWITCH RETIMER
PS8802
PD Solution
TPS65982DD
P44
Micro SIM
P52
P40
P46
M.2,3042 Key B
WWAN/LTE/HCA
USB3.0 [5]
HDMI
SMBUS from EC
USB2.0[1]
SMBUS from EC
EDP CONN
PCIE[12]
P52
USB2.0[7]
P38
HDMI 1.4
Active LS
PS8407
2-Lane eDP1.3
PCIE[10]
M.2,2230 Key E
WLAN+BT/CNVi
P40
CNVi
P52
USB2.0[10]
DDI[1]
DDI[2]
INTEL
WHL-U 42
PAGE 6~19
USB
USB2.0[2]
SLGC55544CVTR
USB POWER SHARE
USB3.0[2] USB3.0[2]
DDR4-SO-DIMM X2
BANK 0, 1, 2, 3
P20~21
I2C[0]
USB2.0[6]
USB2.0[2]_PS
P71
USB2.0[3]
USB3.0[3]
USB2.0[4]
USB3.0[4]
LCD Touch
Camera
USB3.0 Conn
PS(Ext Port 1)
USB3.0 Conn
(Ext Port 2)
USB3.0 Conn
(Ext Port 3)
P38
P38
Through eDP Cable
P71
P72
P72
PCIE[13][14][15][16]
B B
Smart Card
USH
A A
5
TDA8034HN
RFID/NFC
Fingerprint
CONN
USH
BCM58202
USB/SPI FOR FIPS FPR
USB2[8]
SMSC KBC
MEC5106
4
SPI
SATA[0]
vPro
W25Q256JVEIQ
32MB 4K sector WSON8
ESPI
P58-59
Non-vPro
W25Q64JVZEIQ
8MB 4K sector WSON8 P8
Non-vPro
W25Q128JVSIQ
16MB 4K sector SOP8 P8
TPM2.0
ST33HTPH2E32AHC1
KB/TP CONN
FAN CONN
3
P66
SATA REPEATER
PI3EQX6741STZDEX
P65
SATA HDD
P77
Conn
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
P67
HD Audio I/F
P67
HDA Codec
ALC3204
M.2 2280 Key M
SSD Conn
2
P56
P68
INT.Speaker
Universal Jack
Dig. MIC
P56
P56
P38
Through eDP Cable
DELL
CONFIDENTIAL/PROPRIETARY
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LID SWITCH for
Laptop mode
FP in PBTN CONN
CPU&PCH XDP Port
AUTOMATIC POWER
SWITCH(APS)
Free Fall sensor
DC/DC Interface
POWER ON/OFF
SW & LED
Comp
Comp
Bloc
Bloc
onday, February 25, 2019
onday, February 25, 2019
1
USH CONN
P14 & 79
al Electronics, Inc.
al Electronics, Inc.
k Diagram
k Diagram
LA-G8
LA-G8
91P
91P
2 102M
2 102M
P64
P66
P66
P11
P67
P78
P64
of
of
of
0.3
0.3
5
POW
ER STATES
Signal
State
S0 (Full ON) / M0
D D
S0ix/Moff LOW HIGH HIGH ON ON ON OFF
S4 (Suspend to DISK) / M3 ON ON OFF
S5 (SOFT OFF) / M3 ON ON OFFLOW HIGHLOW
S0ix (Suspend to RAM) / M-OFF
S4 (Suspend to DISK) / M-OFF HIGH
S5 (SOFT OFF) / M-OFF
C C
SLP
S3#
HIGH
LOW HIGH HIGH
LOW HIGH HIGH LOW ON ONOFF OFF OFF
LOW LOW LOW ON OFF OFF OFF OFF
LOW LOW LOW LOW ON OFF OFF OFF OFF
SLP
SLP
S5#
S4#
HIGH HIGH
LOW
LOW
SLP
A#
HIGH
HIGH
ALWAYS
PLANE
ON
4
M
PLANE
ON
SUS
PLANE
RUN
PLANE
ON ON ON
OFF
OFF
CLOCKS
OFF
OFF
OFF
3
USB3.0
USB3.0-1
USB3.0-2
USB3.0-3
USB3.0-4
USB3.0-5
USB3.0-6
2
PCIEGbE
PCIE-1
PCIE-2
PCIE-3
PCIE-4
PCIE-5
PCIE-6
SATA
Type-C
JUSB1
JUSB2
JUSB3
M.2 3042(LTE)
NA
PCIE-7
PCIE-8
PCIE-9
PCIE-10 M.2 2230(BT)
PCIE-11
PCIE-12
SATA-0
SATA-1
Card Reader
LOM
M.2 2230(WLAN)
HDD
M.2 3042(LTE)
USB PORT#DESTINATION
1
2
3
4
5
6
7
8
9
10
1
DESTINATION
Type-C
JUSB1
JUSB2
JUSB3
NA
Camera
M2 3042(WWAN)
USH
FPR in PB
PCIE-13
PCIE-14
PCIE-15
PCIE-16
SATA-1*
SATA-2
M.2 2280 SSD
(PCIex4 or SATA)
PM TABLE
+5V_ALW
+3.3V_ALW
power
plane
B B
State
S0
S0ix
S5 S4/AC
S5 S4/AC doesn't exist
A A
5
+3.3V_ALW_DSW
+3.3V_ALW_PCH
+RTC_CELL
+1.8V_PRIM
+5V_ALW2
+3.3V_ALW2
+3.3V_RTC_LDO
+1V_PRIM
ON
ON
+3.3V_CV2
+1.2V_MEM
+2.5V_MEM
ON ON
ON
OFF
OFFOFF
+5V_RUN
+3.3V_RUN
+0.6V_DDR_VTT
+1.8V_RUN
+1.2V_RUN
OFFON
OFF
OFF
4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
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Port
Port
assignment
assignment
LA-
LA-
G891P
G891P
1
3 10
3 10
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
of
of
of
5
Barrel
ADAPTER
D D
CHARGER
ISL9538
(PU700)
Type-C
ADAPTER
+
PWR_SRC
BATTERY
C C
SY8210A
(PU200)
SYX198D
(PU301)
SY8288C
(PU102)
SY8288B
(PU100)
4
SIO_SLP_S4#
0.6V_DDR_VTT_ON
PCH_PRIM_EN
(SIO_SLP_SUS#)
ALWON
ALWON
+1.2V_MEM
+0.6V_DDR_VTT
+1.0V_PRIM
+5V_ALW
+5V_ALW2
+3.3V_RTC_LDO
+3.3V_ALW2
+3.3V_ALW
TPS22961
(UZ27)
3
SIO_SLP_S3#
SIO_SLP_S0#
VCCSTG_EN
+VCC_SFR_OC
SY8057B
(PU401)
SY8057C
(PU402)
EM5209
(UZ47)
SLGC55544C
(UI3)
SY6288
(UI1)
SY6288
(UI2)
RUN_ON
PCH_PRIM_EN
(SIO_SLP_SUS#)
RUN_ON
USB_POWERSHARE_VBUS_EN
USB_PWR_EN1#
USB_PWR_EN2#
+1.0VS_VCCIO
+1.0V_PRIM_CORE
+USB_EX2_PWR
+USB_EX3_PWR
TPS22961
(UZ19)
TPS22961
(UZ21)
+5V_RUN
+5V_USB_CHG_PWR
2
1
CPU PWR
PCH PWR
GT3 PWR
RUN_ON
SIO_SLP_S0#
RUN ON
LP2301
(QV8)
EM5209
(@UZ5)
+1.0V_VCCSTG
+1.0V_VCCST
3.3V_TS_EN
@PCH_3.3V_TS_EN
AUD_PWR_EN
Peripheral Device PWR
TYPE-C Power
GPU PWR
+5V_TSP
+5V_RUN_AUDIO
RUN_ON
RUN_ON
3.3V_CAM_EN#
AUD_PWR_EN
+1.8V_RUN
+1.2V_RUN
+3.3V_CAM
+3.3V_RUN_AUDIO
9
PCH_PRIM_EN
SIO_SLP_LAN#
PCH_PRIM_EN
RUN_ON
WLAN_PWR_EN
LCD_VCC_TEST_EN
ENVDD_PCH
3.3V_WWAN_EN
CV2_ON
SIO_SLP_S4#
+1.8V_PRIM
+3.3V_LAN
+3.3V_ALW_PCH
+3.3V_RUN
+3.3V_WLAN
+LCDVDD
+3.3V_WWAN
+3.3V_CV2
+2.5V_MEM
for DDR4
USH/B
RT8097A
FDMF3
035
ISL95857
(PU602)
VR_ON
B B
IMVP_
+VCC_SA
FDMF3035
(PU612)
IMVP_VR_ON
+VCC_GT
(PU610)
FDMF3035
(PU613)
U42@
IMVP_VR_ON
+VCC_CORE
AO6405
(QV1)
+BL_
NVPWR
EN_I
PWR_SRC
TYPE-C
+5V_ALW
+TBTA_VBUS(5V~20V)
A A
AP2204
(UT8)
+5V_ALW
+5V_TBT_VBUS
TPS65982D\
(UT5)
AP2112K
(UT7)
+20V_TBTA_VBUS_1(5V~20V)
+3.3V_VDD_PIC_R
(PU501)
EM5209
(UZ43)
EM5209
(UZ3)
EM520
(UZ47)
G524B1T11U
(UV24)
EM5209
(UZ43)
TPS22967
(UZ18)
AP7361C
(PU503)
AOZ1336
(UZ8)
AP7361
(PU502)
LP2301A
(QZ1)
EM5209
(@UZ5)
DELL CONFIDENTIAL/PROPRIETARY
Comp
Comp
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Titl
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PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
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Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
Powe
Powe
r rails
r rails
LA-G
LA-G
891P
891P
1
0.3
4 102M
4 102M
0.3
of
of
of
5
Timing Diagram for S5 to S0 mode
D D
6
C C
B B
+3.3V_WLAN
11
A A
VCCST_PWRGD
12
H_CPUPWRGD
15
PCH_PLTRST#
17
0.6V_DDR_VTT_ON
12
+1.
0V_PRIM_CORE
+1.8V_PRIM
6
+1.0V_PRIM SY8286
+3.
3V_ALW
EM5
209VF
6
SLP
11
_WLAN#_GATE
OR
Gate
CPU
VCCST_PWRGD
PROCPWRGD
PLTRST#
DDR_VTT_CNTL
+PWR_SRC
TPS
62134
+3.3V_ALW
RT8097
+PWR_SRC
SIO
_SLP_WLAN#
SIO_SLP_WLAN#
NMO
AUX_EN_WOWL
VDDQ
VDDQC
VCCPLL_OC
S
4
+VCC_CORE
VCC
+1.0VS_VCCIO
VCCIO SYS_PWROK
+VCC_GT
VCCGT
+1.2V_MEM
VCCST
VCCSTG
VCCPLL
VCC
SA
+1.
0V_VCCST
+VCC_SA
11
+1.0V_PRIM
TPS22961
SIO
+LCDVDD
SIO
_SLP_SUS#
11
+5V_TSP
EC
5105
11
+5V
RUN_ON
11
3.3
V_WWAN_EN
_ALW
EM5
209VF
+3.
3V_ALW
EM5209VF
+1.
8V_PRIM
EM5
209VF +1.8V_RUN
+PWR_SRC
TLV
62130
+3.
3V_ALW
EM5209VF
+5V_RUN
+3.
+1.
+3.3V_WWAN
+3.3V_ALW
3
+3.3V_SPI
_SLP_S4#
3V_RUN
0VS_VCCIO
LP2
LP2301ALT1G+3.3V_CAM
13
3
+1.0V_MPHYGT
+3.3V_ALW_DSW
+3.3V_ALW_PCH
5
6
+1.0V_PRIM_CORE
6
17
4
+3.3V_ALW
G52
4B1T11
+3.3V_ALW
EM5209VF+3.3V_LAN
+5V
_RUN
301ALT1G
+3.
3V_RUN
+3.
3V_HDD_M2
+VCC_SA
+VCC_CORE
+VCC_GT
+1.0V_PRIM
+1.8V_PRIM
+RTC_CELL
PCH_PLTRST#
PCH_DPWROK
ENV
DD_PCH
SIO_SLP_LAN#
@PC
H_3.3V_TS_EN
3.3
V_TS_EN (EC)
3.3
V_CAM_EN#
10
+PW
ISL
PCH_PWROK
VCCPRIM_1P0
VCCPRIM_CORE
DCPDSW_1P0
VCCMPHYAON_1P0
VCCAPLL_1P0
VCCCLK1~6
VCCMPHYGT_1P0
VCCSRAM_1P0
VCCAMPHYPLL_1P0
VCCAPLLEBB
VCCDSW_3P3
VCCHDA
VCCSPI
VCCPRIM_3P3
VCCPGPPA~E
VCCRTCPRIM
VCCPGPPG
VCCATS
VCCRTC
VCC
PRIM_CORE
PLTRST#
DSW_PWROK
EDP
_VDDEN
SLP_LAN#
GPP_B21
GPD7
ADA
PTER
BATTERY
PCH
7
PCH_DPWROK
4
RES
16
SIO_SLP_SUS#
5
SIO_SLP_S4#
SIO_SLP_S5#
9
SIO
SIO_SLP_S3#
11
SIO_SLP_A#
R_SRC
95857
PCH
SLP_WLAN#/GPD9
VCCST_PWRGD
_RSMRST#
ET_OUT#
_SLP_LAN#
12
IMV
P_VR_ON
PWRBTN#
RSMRST#
SLP_SUS#
SLP_LAN#
PCH_PWROK
PROCPWRGD
14
SLP_S5#
SLP_S4#
SLP_S3#
SLP_A#
BAT
2
Pow
SIO_PWRBTN#
PCH_RSMRST#
SIO_SLP_SUS#
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_S3#
SIO_SLP_A#
SIO_SLP_LAN#
SIO_SLP_WLAN#
RESET_OUT#
PCH_PWROK
VCCST_PWRGD
H_CPUPWRGD
er Button
2AC1
ALW
ON
5
PCH_PRIM_EN
EN_INVPWR
10
SIO_SLP_S4#
0.6
V_DDR_VTT_ON
8
7
5
9
10
11
16
14
12
15
+PWR_SRC
SYV
828EC 5105
+PWR_SRC
SY8288
+3.
EM5209VF
+PWR_SRC
3V_ALW
AO6
405
+PWR_SRC
SY8
210
+5V_ALW2
+5V_ALW
+3.3V_RTC_LDO
+3.3V_ALW2
+3.3V_ALW
+3.3V_ALW_PCH
+BL_PWR_SRC
+1.
2V_MEM
+0.6V_DDR_VTT
12
1
1BAT
2AC
5
18
VDD
Q
DDR
VTT
DEL
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PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
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le
Size Document Numb er Rev
Size Document Numb er Rev
Size Document Numb er Rev
Date: Sheet
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Date: Sheet
pal Electronics, Inc.
Pow
Pow
er Sequence
er Sequence
LA-
LA-
G891P
G891P
1
5 10
5 10
of
of
of
0.3
0.3
2Monday, February 25 , 2019
2Monday, February 25 , 2019
5
4
3
2
1
For 2LANE EDP
+3.3V_RUN
RC503 2.2K_0402_5%
RC178 2.2K_0402_5%
RC176 2.2K_0402_5%
D D
C C
B B
RC502 2.2K_0402_5%
RC438 2.2K_0402_5%@
RC437 2.2K_0402_5%@
Jony_01/16 : Refer RVP new adds
575962_WHL-U_DDR4_RVP_Sch_Rev0p5.pdf
All VREF traces should
have 10 mil trace width
TYPE
12
12
12
12
12
12
C_CON_SEL1
CPU_DP1_CTRL_CLK
CPU_DP1_CTRL_DATA
CPU_DP2_CTRL_CLK
CPU_DP2_CTRL_DATA
CPU_DDPD_CTRL_CLK
CPU_DDPD_CTRL_DATA
COMP
ENSATION PU FOR eDP
CAD Note:
Trace width=5 mils
Isolation Spacing=25mil,
Max length=100 mils.
+3.3
V_ALW_PCH
RC74
4
@
10K_0402_5%
1 2
TYPE
RC74
5
@
10K_0402_5%
C_CON_SEL2
12
+3.3
V_ALW_PCH
@
10K_0402_5%
1 2
12
@
1
RC74
3
RC63
0K_0402_5%
HDMI
TYPE-C
+1.0
VS_VCCIO
CPU_DP1_N0[40]
CPU_DP1_P0[40]
CPU_DP1_N1[40]
CPU_DP1_P1[40]
CPU_DP1_N2[40]
CPU_DP1_P2[40]
CPU_DP1_N3[40]
CPU_DP1_P3[40]
CPU_DP2_N0[46]
CPU_DP2_P0[46]
CPU_DP2_N1[46]
CPU_DP2_P1[46]
CPU_DP2_N2[46]
CPU_DP2_P2[46]
CPU_DP2_N3[46]
CPU_DP2_P3[46]
RC8 24
CPU_
DP1_CTRL_CLK[40]
CPU_
DP1_CTRL_DATA[40]
+3.3
V_ALW_PCH
1 2
@
1 2
RC10
1
GPP_
20K_0402_5%
CNV_
CNV_
CNV_
CNV_
CNV_
CNV_
CNV_
CNV_
CLK_
CNV_PRX_DTX_N[52]
CLK_
CNV_PRX_DTX_P[52]
CLK_
CNV_PTX_DRX_N[52]
CLK_
CNV_PTX_DRX_P[52]
.9_0402_1%
CPU_
CPU_
CPU_
CPU_
CPU_
CPU_
H17
PRX_DTX_N0[52]
PRX_DTX_P0[52]
PRX_DTX_N1[52]
PRX_DTX_P1[52]
PTX_DRX_N0[52]
PTX_DRX_P0[52]
PTX_DRX_N1[52]
PTX_DRX_P1[52]
150_0402_1%
EDP_
COMP
DP1_CTRL_CLK
DP1_CTRL_DATA
DP2_CTRL_CLK
DP2_CTRL_DATA
DDPD_CTRL_CLK
DDPD_CTRL_DATA
GPP_
H17
1 2
CNV_
T406
PAD~D@
T407
PAD~D@
SBIO
CNV_
CNV_
UC1A
AL5
DDI1_TXN_0
AL6
DDI1_TXP_0
AJ5
DDI1_TXN_1
AJ6
DDI1_TXP_1
AF6
DDI1_TXN_2
AF5
DDI1_TXP_2
AE5
DDI1_TXN_3
AE6
DDI1_TXP_3
AC4
DDI2_TXN_0
AC3
DDI2_TXP_0
AC1
DDI2_TXN_1
AC2
DDI2_TXP_1
AE4
DDI2_TXN_2
AE3
DDI2_TXP_2
AE1
DDI2_TXN_3
AE2
DDI2_TXP_3
AM6
DISP
_RCOMP
CC8
GPP_
E18/DPPB_CTRLCLK/CNV_BT_HOST_WAKE#
CC9
GPP_
E19/DPPB_CTRLDATA
CH4
GPP_
E20/DPPC_CTRLCLK
CH3
GPP_
E21/DPPC_CTRLDATA
CP4
GPP_
E22/DPPD_CTRLCLK
CN4
GPP_
E23/DPPD_CTRLDATA
CR26
GPP_
H16/DDPF_CTRLCLK
CP26
GPP_
H17/DDPF_CTRLDATA
WHL-U42_BGA1528
CNV_
PRX_DTX_N0
CNV_
PRX_DTX_P0
CNV_
PRX_DTX_N1
CNV_
PRX_DTX_P1
CNV_
PTX_DRX_N0
CNV_
PTX_DRX_P0
CNV_
PTX_DRX_N1
CNV_
PTX_DRX_P1
CLK_
CNV_PRX_DTX_N
CLK_
CNV_PRX_DTX_P
CLK_
CNV_PTX_DRX_N
CLK_
CNV_PTX_DRX_P
CNV_
WT_RCOMP
RC44
8
CNV_
COEX3[52]
COEX2[52]
COEX1[52]
COEX3
DDR_
CHA_EN
1
DDR_
CHB_EN
1
SBIO
S_TX
S_TX[79]
TYPE
C_CON_SEL1
TYPE
C_CON_SEL2
CNV_
COEX2
CNV_
COEX1
DDI
DISPLAY SIDEBANDS
UC1I
CR30
CNV_
CP30
CNV_
CM30
CNV_
CN30
CNV_
CN32
CNV_
CM32
CNV_
CP33
CNV_
CN33
CNV_
CN31
CNV_
CP31
CNV_
CP34
CNV_
CN34
CNV_
CP32
CNV_
CR32
CNV_
CP20
GPP_
CK19
GPP_
CG17
GPP_
CR14
GPP_
CP14
GPP_
CN14
GPP_
CM14
GPP_
CJ17
GPP_
CH17
GPP_
CF17
GPP_
W
HL-U42_BGA1528
C
NVio
WR_D0N
WR_D0P
WR_D1N
WR_D1P
WT_D0N
WT_D0P
WT_D1N
WT_D1P
WR_CLKN
WR_CLKP
WT_CLKN
WT_CLKP
WT_RCOMP_0
WT_RCOMP_1
F0/CNV_PA_BLANKING
F1
F2
C8/UART0_RXD
C9/UART0_TXD
C10/UART0_RTS#
C11/UART0_CTS#
F8/CNV_MFUART2_RXD
F9/CNV_MFUART2_TXD
F23/A4WP_PRESENT
1 of
20
GPP_
EMMC
9 of
20
EDP
GPP_
E13/DDPB_HPD0/DISP_MISC0
GPP_
E14/DDPC_HPD1/DISP_MISC1
GPP_
E15/DPPD_HPD2/DISP_MISC2
GPP_
E16/DPPE_HPD3/DISP_MISC3
GPP_
GPP_
H18/CPU_C10_GATE#
GPP_
H19/TIMESYNC_0
GPP_
H21/XTAL_FREQ_SELECT
D4/IMGCLKOUT0/BK4/SBK4
GPP_
H20/IMGCLKOUT_1
GPP_
F12/EMMC_DATA0
GPP_
F13/EMMC_DATA1
GPP_
F14/EMMC_DATA2
GPP_
F15/EMMC_DATA3
GPP_
F16/EMMC_DATA4
GPP_
F17/EMMC_DATA5
GPP_
F18/EMMC_DATA6
GPP_
F19/EMMC_DATA7
GPP_
F20/EMMC_RCLK
GPP_
F21/EMMC_CLK
GPP_
F11/EMMC_CMD
GPP_
F22/EMMC_RESET#
EMMC
E17/EDP_HPD/DISP_MISC4
GPP_
H22
GPP_
H23
GPP_
F10
GPD7
GPP_
F3
_RCOMP
AG4
EDP_TXN_0
AG3
EDP_TXP_0
AG2
EDP_TXN_1
AG1
EDP_TXP_1
AJ4
EDP_TXN_2
AJ3
EDP_TXP_2
AJ2
EDP_TXN_3
AJ1
EDP_TXP_3
AH4
EDP_AUX_N
AH3
EDP_AUX_P
AM7
DISP_UTILS
AC7
DDI1_AUX_N
AC6
DDI1_AUX_P
DDI2_AUX_N
DDI2_AUX_P
DDI3
DDI3
EDP_
EDP_
EDP_
BKLTCTL
CN27
CM27
CF25
CN26
CM26
CK17
B
V35
CN20
CG25
CH25
CR20
CM20
CN19
CM19
CN18
CR18
CP18
CM18
CM16
CP16
CR16
CN16
CK15
_AUX_N
_AUX_P
BKLTEN
VDDEN
CPU_
GPP_
GPP_
GPD7
CPU_DP2_AUXN
AD4
CPU_DP2_AUXP
AD3
CPU_DP3_AUXN
AG7
CPU_
AG6
CN6
CM6
CP7
CP6
CM7
CK11
CG11
CH11
This strap should sample HIGH.
There should NOT be any on-board device
driving it to opposite direction during strap sampling.
C10_GATE#
H21
H23
EMMC
DP3_AUXP
HDMI
_DP1_HPD
CPU_
DP2_HPD
FFS_
INT2
EDP_
HPD
CPU_
C10_GATE# [17,58,87]
Jony_01/16 : CK15 - Keep 200 ohm
575962_WHL-U_DDR4_RVP_Sch_Rev0p5.pdf
_RCOMP
1 2
RC10 2
00_0402_1%
EDP_TXN0 [38]
EDP_TXP0 [38]
EDP_TXN1 [38]
EDP_TXP1 [38]
EDP_AUXN [38]
EDP_AUXP [38]
CPU_DP2_AUXN [44,46]
CPU_DP2_AUXP [44,46]
1
@
PAD
~D
1
@
PAD
~D
HDMI
_DP1_HPD [40]
CPU_
DP2_HPD [44,46]
FFS_
INT2 [67]
EDP_
HPD [38]
PANE
L_BKLEN [38]
ENVD
D_PCH [38]
EDP_
BIA_PWM [38]
+3.3V_RUN
CPU_DP2_AUXN
FFS_INT2
CPU_DP2_AUXP
T1
T2
EDP_HPD
CPU_
DP2_HPD
GPD7
RC44
4.7K_0402_5%
RC44
@
20K_0402_5%
@
RC53
4.7K_0402_5%
RC44
@
20K_0402_5%
0K_0402_5%@
1
00K_0402_5%
20K_0402_5%
+3.3
V_ALW_PCH
3
4
+3.3
V_ALW_PCH
7
6
@
12
RC731100K_0402_5% @
12
RC72610K_0402_5%
12
RC732100K_0402_5% @
12
RC2100K_0402_5%
12
RC610
+3.3
V_ALW_PCH
RC95
1 2
RC45
4
1 2
1 2
GPP_
H21
LOW: 38.4/19.2MHZ (DEFAULT)
HIGH: 24MHZ
1 2
0 = Master Attached Flash Sharing
(MAFS) enabled. (Default)
1 = Slave Attached Flash Sharing
(SAFS) enabled.
1 2
GPP_
H23
1 2
A A
Vend
or TBDTBDFOXCONJAE
TYPEC_CON_SEL1 LOW
TYPEC_CON_SEL2
5
LOW
HIGH LOW
LOW
HIGHHIGH
HIGH
DELL
CONFIDENTIAL/PROPRIETARY
Comp
Comp
Comp
al Electronics, Inc.
al Electronics, Inc.
Titl
Titl
Title
e
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
4
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
e
P07-
P07-
P07-
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
MCP(1/14)DDI,EDP,CSI2,EMMC
MCP(1/14)DDI,EDP,CSI2,EMMC
MCP(1/14)DDI,EDP,CSI2,EMMC
LA-G
LA-G
LA-G
891P
891P
891P
6 102M
6 102M
6 102M
of
of
1
of
0.3
0.3
0.3
5
DDR4, Ballout for side by side(Non-Interleave)
4
3
2
1
CPU Need update CIS
DDR_A_DQS#[0..7][23]
DDR_A_D[0..63][23]
DDR_A_DQS[0..7][23]
DDR_A_MA[0..16][23]
D D
UC1B
_A_D5
_A_D6
_A_D7
_A_D8
_A_D9
_A_D10
_A_D11
_A_D12
_A_D13
_A_D14
_A_D15
_A_D32
_A_D33
_A_D34
_A_D35
_A_D36
_A_D37
_A_D38
_A_D39
_A_D40
_A_D41
_A_D42
_A_D43
_A_D44
_A_D45
_A_D46
_A_D47
_B_D0
_B_D1
_B_D2
_B_D3
_B_D4
_B_D5
_B_D6
_B_D7
_B_D8
_B_D9
_B_D10
_B_D11
_B_D12
_B_D13
_B_D14
_B_D15
_B_D32
_B_D33
_B_D34
_B_D35
_B_D36
_B_D37
_B_D38
_B_D39
_B_D40
_B_D41
_B_D42
_B_D43
_B_D44
_B_D45
_B_D46
_B_D47
Interleave / Non-Interleaved
A26
DDR0_DQ_0/DDR0_DQ_0
D26
DDR0_DQ_1/DDR0_DQ_1
D28
DDR0_DQ_2/DDR0_DQ_2
C28
DDR0_DQ_3/DDR0_DQ_3
B26
DDR
C26
DDR
B28
DDR
A28
DDR
B30
DDR
D30
DDR
B33
DDR
D32
DDR
A30
DDR
C30
DDR
B32
DDR
C32
DDR
H37
DDR
H34
DDR
K34
DDR
K35
DDR
H36
DDR
H35
DDR
K36
DDR
K37
DDR
N36
DDR
N34
DDR
R37
DDR
R34
DDR
N37
DDR
N35
DDR
R36
DDR
R35
DDR
AN35
DDR
AN34
DDR
AR35
DDR
AR34
DDR
AN37
DDR
AN36
DDR
AR36
DDR
AR37
DDR
AU35
DDR
AU34
DDR
AW35
DDR
AW34
DDR
AU37
DDR
AU36
DDR
AW36
DDR
AW37
DDR
BA35
DDR
BA34
DDR
BC35
DDR
BC34
DDR
BA37
DDR
BA36
DDR
BC36
DDR
BC37
DDR
BE35
DDR
BE34
DDR
BG35
DDR
BG34
DDR
BE37
DDR
BE36
DDR
BG36
DDR
BG37
DDR
WHL-U42 _BGA1528
0_DQ_4/DDR0_DQ_4
0_DQ_5/DDR0_DQ_5
0_DQ_6/DDR0_DQ_6
0_DQ_7/DDR0_DQ_7
0_DQ_8/DDR0_DQ_8
0_DQ_9/DDR0_DQ_9
0_DQ_10/DDR0_DQ_10
0_DQ_11/DDR0_DQ_11
0_DQ_12/DDR0_DQ_12
0_DQ_13/DDR0_DQ_13
0_DQ_14/DDR0_DQ_14
0_DQ_15/DDR0_DQ_15
0_DQ_16/DDR0_DQ_32
0_DQ_17/DDR0_DQ_33
0_DQ_18/DDR0_DQ_34
0_DQ_19/DDR0_DQ_35
0_DQ_20/DDR0_DQ_36
0_DQ_21/DDR0_DQ_37
0_DQ_22/DDR0_DQ_38
0_DQ_23/DDR0_DQ_39
0_DQ_24/DDR0_DQ_40
0_DQ_25/DDR0_DQ_41
0_DQ_26/DDR0_DQ_42
0_DQ_27/DDR0_DQ_43
0_DQ_28/DDR0_DQ_44
0_DQ_29/DDR0_DQ_45
0_DQ_30/DDR0_DQ_46
0_DQ_31/DDR0_DQ_47
0_DQ_32/DDR1_DQ_0
0_DQ_33/DDR1_DQ_1
0_DQ_34/DDR1_DQ_2
0_DQ_35/DDR1_DQ_3
0_DQ_36/DDR1_DQ_4
0_DQ_37/DDR1_DQ_5
0_DQ_38/DDR1_DQ_6
0_DQ_39/DDR1_DQ_7
0_DQ_40/DDR1_DQ_8
0_DQ_41/DDR1_DQ_9
0_DQ_42/DDR1_DQ_10
0_DQ_43/DDR1_DQ_11
0_DQ_44/DDR1_DQ_12
0_DQ_45/DDR1_DQ_13
0_DQ_46/DDR1_DQ_14
0_DQ_47/DDR1_DQ_15
0_DQ_48/DDR1_DQ_32
0_DQ_49/DDR1_DQ_33
0_DQ_50/DDR1_DQ_34
0_DQ_51/DDR1_DQ_35
0_DQ_52/DDR1_DQ_36
0_DQ_53/DDR1_DQ_37
0_DQ_54/DDR1_DQ_38
0_DQ_55/DDR1_DQ_39
0_DQ_56/DDR1_DQ_40
0_DQ_57/DDR1_DQ_41
0_DQ_58/DDR1_DQ_42
0_DQ_59/DDR1_DQ_43
0_DQ_60/DDR1_DQ_44
0_DQ_61/DDR1_DQ_45
0_DQ_62/DDR1_DQ_46
0_DQ_63/DDR1_DQ_47
2 o
f 20
DDR0_CKN_0/DDR0_CKN_0
DDR0_CKP_0/DDR0_CKP_0
DDR0_CKN_1/DDR0_CKN_1
DDR
0_CKP_1/DDR0_CKP_1
DDR
0_CKE_0/DDR0_CKE_0
DDR
0_CKE_1/DDR0_CKE_1
DDR
0_CKE_2/NC
DDR
0_CKE_3/NC
DDR
0_CS#_0/DDR0_CS#_0
DDR
0_CS#_1/DDR0_CS#_1
DDR
0_ODT_0/DDR0_ODT_0
NC/
DDR0_ODT_1
DDR
0_CAB_9/DDR0_MA_0
DDR
0_CAB_8/DDR0_MA_1
DDR
0_CAB_5/DDR0_MA_2
NC/
DDR0_MA_3
NC/
DDR0_MA_4
DDR
0_CAA_0/DDR0_MA_5
DDR
0_CAA_2/DDR0_MA_6
DDR
0_CAA_4/DDR0_MA_7
DDR
0_CAA_3/DDR0_MA_8
DDR
0_CAA_1/DDR0_MA_9
DDR
0_CAB_7/DDR0_MA_10
DDR
0_CAA_7/DDR0_MA_11
DDR
0_CAA_6/DDR0_MA_12
DDR
0_CAB_0/DDR0_MA_13
DDR
0_CAB_2/DDR0_MA_14
DDR
0_CAB_1/DDR0_MA_15
DDR
0_CAB_3/DDR0_MA_16
DDR
0_CAB_4/DDR0_BA_0
DDR
0_CAB_6/DDR0_BA_1
DDR
0_CAA_5/DDR0_BG_0
DDR
0_CAA_8/DDR0_ACT#
DDR
0_CAA_9/DDR0_BG_1
Interleave / Non-Interleaved
DDR
0_DQSN_0/DDR0_DQSN_0
DDR
0_DQSP_0/DDR0_DQSP_0
DDR
0_DQSN_1/DDR0_DQSN_1
DDR
0_DQSP_1/DDR0_DQSP_1
DDR
0_DQSN_2/DDR0_DQSN_4
DDR
0_DQSP_2/DDR0_DQSP_4
DDR
0_DQSN_3/DDR0_DQSN_5
DDR
0_DQSP_3/DDR0_DQSP_5
DDR
0_DQSN_4/DDR1_DQSN_0
DDR
0_DQSP_4/DDR1_DQSP_0
DDR
0_DQSN_5/DDR1_DQSN_1
DDR
0_DQSP_5/DDR1_DQSP_1
DDR
0_DQSN_6/DDR1_DQSN_4
DDR
0_DQSP_6/DDR1_DQSP_4
DDR
0_DQSN_7/DDR1_DQSN_5
DDR
0_DQSP_7/DDR1_DQSP_5
NC/
DDR0_ALERT#
NC/
DDR
DDR
0_VREF_DQ_0
DDR
0_VREF_DQ_1
DDR
1_VREF_DQ
DDR
LPDDR3 / DDR4
LPDDR3 / DDR4
DDR0_PAR
_VREF_CA
_VTT_CTL
V32
V31
T32
T31
U36
U37
U34
U35
AE32
AF32
AE31
AF31
AC37
AC36
AC34
AC35
AA35
AB35
AA37
AA36
AB34
W36
Y31
W34
AA34
AC32
AC31
AB32
Y32
W32
AB31
V34
V35
W35
C27
D27
D31
C31
J35
J34
P34
P35
AP35
AP34
AV34
AV35
BB35
BB34
BF34
BF35
W37
W31
F36
D35
D37
E36
C35
DDR_A_CLK#0
DDR_A_CLK0
DDR_A_CLK#1
DDR_A_CLK1
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
_A_MA0
DDR
_A_MA1
DDR
_A_MA2
DDR
_A_MA3
DDR
_A_MA4
DDR
_A_MA5
DDR
_A_MA6
DDR
_A_MA7
DDR
_A_MA8
DDR
_A_MA9
DDR
_A_MA10
DDR
_A_MA11
DDR
_A_MA12
DDR
_A_MA13
DDR
_A_MA14
DDR
_A_MA15
DDR
_A_MA16
DDR
_A_DQS#0
DDR
_A_DQS0
DDR
_A_DQS#1
DDR
_A_DQS1
DDR
_A_DQS#4
DDR
_A_DQS4
DDR
_A_DQS#5
DDR
_A_DQS5
DDR
_B_DQS#0
DDR
_B_DQS0
DDR
_B_DQS#1
DDR
_B_DQS1
DDR
_B_DQS#4
DDR
_B_DQS4
DDR
_B_DQS#5
DDR
_B_DQS5
_A_CKE0
_A_CKE1
_A_CKE2
_A_CKE3
_A_CS#0
_A_CS#1
_A_ODT0
_A_ODT1
DDR_A_CLK#0 [23]
DDR_A_CLK0 [23]
DDR_A_CLK#1 [23]
DDR
_A_CLK1 [23]
DDR
_A_CKE0 [23]
DDR
_A_CKE1 [23]
1
PAD~D
1
PAD~D
DDR
_A_CS#0 [23]
DDR
_A_CS#1 [23]
DDR
_A_ODT0 [23]
DDR
_A_ODT1 [23]
DDR
_A_BA0 [23]
DDR
_A_BA1 [23]
DDR
_A_BG0 [23]
DDR
_A_ACT# [23]
DDR
_A_BG1 [23]
DDR
_A_ALERT# [23]
DDR
_A_PARITY [23]
DDR
_VTT_CTRL [23]
@
T35
1
@
T35
0
+DD
+DD
DDR0_PAR,DDR0_ALERT#
for DDR4
R_VREF_CA
R_VREF_B_DQ
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
C C
B B
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
_A_D20
_A_D21
_A_D22
_A_D23
_A_D24
_A_D25
_A_D26
_A_D27
_A_D28
_A_D29
_A_D30
_A_D31
_A_D48
_A_D49
_A_D50
_A_D51
_A_D52
_A_D53
_A_D54
_A_D55
_A_D56
_A_D57
_A_D58
_A_D59
_A_D60
_A_D61
_A_D62
_A_D63
_B_D16
_B_D17
_B_D18
_B_D19
_B_D20
_B_D21
_B_D22
_B_D23
_B_D24
_B_D25
_B_D26
_B_D27
_B_D28
_B_D29
_B_D30
_B_D31
_B_D48
_B_D49
_B_D50
_B_D51
_B_D52
_B_D53
_B_D54
_B_D55
_B_D56
_B_D57
_B_D58
_B_D59
_B_D60
_B_D61
_B_D62
_B_D63
UC1C
lnterleave /
Non-lnterleaved
J22
DDR1_DQ_0/DDR0_DQ_16
H25
DDR1_DQ_1/DDR0_DQ_17
G22
DDR1_DQ_2/DDR0_DQ_18
H22
DDR
1_DQ_3/DDR0_DQ_19
F25
DDR
1_DQ_4/DDR0_DQ_20
J25
DDR
1_DQ_5/DDR0_DQ_21
G25
DDR
1_DQ_6/DDR0_DQ_22
F22
DDR
1_DQ_7/DDR0_DQ_23
D22
DDR
1_DQ_8/DDR0_DQ_24
C22
DDR
1_DQ_9/DDR0_DQ_25
C24
DDR
1_DQ_10/DDR0_DQ_26
D24
DDR
1_DQ_11/DDR0_DQ_27
A22
DDR
1_DQ_12/DDR0_DQ_28
B22
DDR
1_DQ_13/DDR0_DQ_29
A24
DDR
1_DQ_14/DDR0_DQ_30
B24
DDR
1_DQ_15/DDR0_DQ_31
G31
DDR
1_DQ_16/DDR0_DQ_48
G32
DDR
1_DQ_17/DDR0_DQ_49
H29
DDR
1_DQ_18/DDR0_DQ_50
H28
DDR
1_DQ_19/DDR0_DQ_51
G28
DDR
1_DQ_20/DDR0_DQ_52
G29
DDR
1_DQ_21/DDR0_DQ_53
H31
DDR
1_DQ_22/DDR0_DQ_54
H32
DDR
1_DQ_23/DDR0_DQ_55
L31
DDR
1_DQ_24/DDR0_DQ_56
L32
DDR
1_DQ_25/DDR0_DQ_57
N29
DDR
1_DQ_26/DDR0_DQ_58
N28
DDR
1_DQ_27/DDR0_DQ_59
L28
DDR
1_DQ_28/DDR0_DQ_60
L29
DDR
1_DQ_29/DDR0_DQ_61
N31
DDR
1_DQ_30/DDR0_DQ_62
N32
DDR
1_DQ_31/DDR0_DQ_63
AJ29
DDR
1_DQ_32/DDR1_DQ_16
AJ30
DDR
1_DQ_33/DDR1_DQ_17
AM32
DDR
1_DQ_34/DDR1_DQ_18
AM31
DDR
1_DQ_35/DDR1_DQ_19
AM30
DDR
1_DQ_36/DDR1_DQ_20
AM29
DDR
1_DQ_37/DDR1_DQ_21
AJ31
DDR
1_DQ_38/DDR1_DQ_22
AJ32
DDR
1_DQ_39/DDR1_DQ_23
AR31
DDR
1_DQ_40/DDR1_DQ_24
AR32
DDR
1_DQ_41/DDR1_DQ_25
AV30
DDR
1_DQ_42/DDR1_DQ_26
AV29
DDR
1_DQ_43/DDR1_DQ_27
AR30
DDR
1_DQ_44/DDR1_DQ_28
AR29
DDR
1_DQ_45/DDR1_DQ_29
AV32
DDR
1_DQ_46/DDR1_DQ_30
AV31
DDR
1_DQ_47/DDR1_DQ_31
BA32
DDR
1_DQ_48/DDR1_DQ_48
BA31
DDR
1_DQ_49/DDR1_DQ_49
BD31
DDR
1_DQ_50/DDR1_DQ_50
BD32
DDR
1_DQ_51/DDR1_DQ_51
BA30
DDR
1_DQ_52/DDR1_DQ_52
BA29
DDR
1_DQ_53/DDR1_DQ_53
BD29
DDR
1_DQ_54/DDR1_DQ_54
BD30
DDR
1_DQ_55/DDR1_DQ_55
BG31
DDR
1_DQ_56/DDR1_DQ_56
BG32
DDR
1_DQ_57/DDR1_DQ_57
BK32
DDR
1_DQ_58/DDR1_DQ_58
BK31
DDR
1_DQ_59/DDR1_DQ_59
BG29
DDR
1_DQ_60/DDR1_DQ_60
BG30
DDR
1_DQ_61/DDR1_DQ_61
BK30
DDR
1_DQ_62/DDR1_DQ_62
BK29
DDR
1_DQ_63/DDR1_DQ_63
WHL-U42 _BGA1528
3 o
f 20
DDR1_CKN_0/DDR1_CKN_0
DDR1_CKP_0/DDR1_CKP_0
DDR1_CKN_1/DDR1_CKN_1
DDR
1_CKP_1/DDR1_CKP_1
DDR
1_CKE_0/DDR1_CKE_0
DDR
1_CKE_1/DDR1_CKE_1
DDR
1_CKE_2/NC
DDR
1_CKE_3/NC
DDR
1_CS#_0/DDR1_CS#_0
DDR
1_CS#_1/DDR1_CS#_1
DDR
1_ODT_0/DDR1_ODT_0
NC/
DDR1_ODT_1
DDR
1_CAB_9/DDR1_MA_0
DDR
1_CAB_8/DDR1_MA_1
DDR
1_CAB_5/DDR1_MA_2
NC/
DDR1_MA_3
NC/
DDR1_MA_4
DDR
1_CAA_0/DDR1_MA_5
DDR
1_CAA_2/DDR1_MA_6
DDR
1_CAA_4/DDR1_MA_7
DDR
1_CAA_3/DDR1_MA_8
DDR
1_CAA_1/DDR1_MA_9
DDR
1_CAB_7/DDR1_MA_10
DDR
1_CAA_7/DDR1_MA_11
DDR
1_CAA_6/DDR1_MA_12
DDR
1_CAB_0/DDR1_MA_13
DDR
1_CAB_2/DDR1_MA_14
DDR
1_CAB_1/DDR1_MA_15
DDR
1_CAB_3/DDR1_MA_16
DDR
1_CAB_4/DDR1_BA_0
DDR
1_CAB_6/DDR1_BA_1
DDR
1_CAA_5/DDR1_BG_0
DDR
1_CAA_9/DDR1_BG_1
DDR
1_CAA_8/DDR1_ACT#
lnt
erleave / Non-lnterleaved
DDR
1_DQSN_0/DDR0_DQSN_2
DDR
1_DQSP_0/DDR0_DQSP_2
DDR
1_DQSN_1/DDR0_DQSN_3
DDR
1_DQSP_1/DDR0_DQSP_3
DDR
1_DQSN_2/DDR0_DQSN_6
DDR
1_DQSP_2/DDR0_DQSP_6
DDR
1_DQSN_3/DDR0_DQSN_7
DDR
1_DQSP_3/DDR0_DQSP_7
DDR
1_DQSN_4/DDR1_DQSN_2
DDR
1_DQSP_4/DDR1_DQSP_2
DDR
1_DQSN_5/DDR1_DQSN_3
DDR
1_DQSP_5/DDR1_DQSP_3
DDR
1_DQSN_6/DDR1_DQSN_6
DDR
1_DQSP_6/DDR1_DQSP_6
DDR
1_DQSN_7/DDR1_DQSN_7
DDR
1_DQSP_7/DDR1_DQSP_7
NC/
DDR1_ALERT#
NC/
DRA
DDR
DDR
DDR
LPDDR3 / DDR4
DDR1_PAR
M_RESET#
_RCOMP_0
_RCOMP_1
_RCOMP_2
AF28
AF29
AE28
AE29
T28
T29
V28
V29
AL37
AL35
AL36
AL34
AG36
AG35
AF34
AG37
AE35
AF35
AE37
AC29
AE36
AB29
AG34
AC28
AB28
AK35
AJ35
AK34
AJ34
AJ37
AJ36
W29
Y28
W28
H24
G24
C23
D23
G30
H30
L30
N30
AL31
AL30
AU31
AU30
BC31
BC30
BH31
BH30
Y29
AE34
BU31
BN28
BN27
BN29
DDR_B_CLK#0
DDR_B_CLK0
DDR_B_CLK#1
DDR_B_CLK1
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
_A_DQS#2
DDR
_A_DQS2
DDR
_A_DQS#3
DDR
_A_DQS3
DDR
_A_DQS#6
DDR
_A_DQS6
DDR
_A_DQS#7
DDR
_A_DQS7
DDR
_B_DQS#2
DDR
_B_DQS2
DDR
_B_DQS#3
DDR
_B_DQS3
DDR
_B_DQS#6
DDR
_B_DQS6
DDR
_B_DQS#7
DDR
_B_DQS7
DDR
_B_ALERT#
DDR
_B_PARITY
DDR
_DRAMRST#
SM_
SM_
SM_
_B_CKE0
_B_CKE1
_B_CS#0
_B_CS#1
_B_ODT0
_B_ODT1
_B_MA0
_B_MA1
_B_MA2
_B_MA3
_B_MA4
_B_MA5
_B_MA6
_B_MA7
_B_MA8
_B_MA9
_B_MA10
_B_MA11
_B_MA12
_B_MA13
_B_MA14
_B_MA15
_B_MA16
RCOMP0
RCOMP1
RCOMP2
DDR_B_DQS#[0..7][24]
DDR_B_D[0..63][24]
DDR_B_DQS[0..7][24]
DDR_B_MA[0..16][24]
DDR_B_CLK#0 [24]
DDR_B_CLK0 [24]
DDR_B_CLK#1 [24]
DDR
_B_CLK1 [24]
DDR
_B_CKE0 [24]
DDR
_B_CKE1 [24]
1
PAD~D
1
PAD~D
DDR
_B_CS#0 [24]
DDR
_B_CS#1 [24]
DDR
_B_ODT0 [24]
DDR
_B_ODT1 [24]
DDR
_B_BA0 [24]
DDR
_B_BA1 [24]
DDR
_B_BG0 [24]
DDR
_B_BG1 [24]
DDR
_B_ACT# [24]
DDR
_B_ALERT# [24]
DDR
_B_PARITY [24]
DDR
_DRAMRST# [23]
@
T35
3
@
T35
4
DDR1_PAR,DDR1_ALERT#
for DDR4
Hank3/5:575962_WHL_DDR4_RVP_RN_TDK_Rev0p7.pdf page12,keep setting
DDR4 COMPENSATION SIGNALS
SM_
RCOMP0
1 2
RC5 1
SM_
RCOMP1
RC5
SM_
RCOMP2
RC7 1
CAD Note:
Trace width=12~15 mil, Spacing=20 mils
Max trace length= 500 mil
A A
21_0402_1%
1 2
04 80.6_0402_1 %
1 2
00_0402_1%
DELL CONFIDENTIAL/PROPRIETARY
Com
Com
Com
pal Electronics, Inc.
pal Electronics, Inc.
Tit
Tit
Tit
le
le
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
le
Size Docum ent Numbe r Rev
Size Docum ent Numbe r Rev
Size Docum ent Numbe r Rev
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronics, Inc.
P08
P08
P08
-MCP(2/14)DDR4
-MCP(2/14)DDR4
-MCP(2/14)DDR4
LA-G
LA-G
LA-G
891P
891P
891P
1
7 10
7 10
7 10
of
of
of
0.3
0.3
0.3
2Mond ay, February 25, 2 019
2Mond ay, February 25, 2 019
2Mond ay, February 25, 2 019
5
SPI_MOSI= SPI_IO0
SPI_MISO= SPI_IO1
PCH EDS R0.7 p.235~236
PCH_SPI_CLK
PCH_SPI_D1
PCH_CL_CLK1[52]
PCH_CL_DATA1[52]
PCH_CL_RST1#[52]
ESPI
WWAN_B B_RST#
WWAN_GPIO_PERST#
_ALERT#[58]
PCH_SPI_D0
PCH_SPI_D2
PCH_SPI_D3
PCH_SPI_CS#0
PCH_SPI_CS#1
PCH_SPI_CS#2
ESPI_ALERT#
1 2
0K_0402_1%
12
12
WWAN_
12
RC7561
@
00K_0402_5%@
0K_0402_5%
RC505 1K_0402_1%CXDP@
RC11 1K_0402_1%CXDP@
ESPI
_ALERT#
GPIO_PERST#
ESPI
PCH_SP
1 2
WWAN_GPIO_PERST#[52]
_RESET#
I_CLK
PCH_SPI_CS#2[66]
RTC_DET#[83]
WWAN_BB _RST#[52]
MEDIACARD_IRQ#[70]
PCH_SPI_DO_XDP[79]
PCH_SPI_DO2_XDP[79]
D D
+1.8
V_PRIM
1 2
RC244 1
0K_0402_5%
C C
RC833 1
RC96 10
For
signal deglitch, refer to 575412_WHL_U_PDG rev0p8
Strap pin
Strap pin
Strap pin
1.8V
1.8V
CH37
CF37
CF36
CF34
CG34
CG36
CG35
CH34
CF20
CG22
CF22
CG23
CH23
CG20
BV29
BV28
CH7
CH8
CH9
UC1E
SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0#
SPI0_CS1#
SPI0_CS2#
GPP_D1/SPI1_CLK/BK1/SBK1
GPP_D2/SPI1_MISO_IO1/BK2/SBK2
GPP_D3/SPI1_MOSI_IO0/BK3/SBK3
GPP_D21/SPI1_IO2
GPP_D22/SPI1_IO3
GPP_D0/SPI1_CS0#/BK0/SBK0
CL_CLK
CL_DATA
CL_RST#
GPP_A0/RCIN#/TIME_SYNC1
GPP_
A6/SERIRQ
WHL-U42_BGA1528
SPI - FLASH
4
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C5/SML0ALERT#
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_B23/SML1ALERT#/PCHHOT#
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME#/ESPI_CS#
GPP_A14/SUS_STAT#/ESPI_RESET#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_A10/CLKOUT_LPC1
GPP_A8/CLKRUN#
+3.3
V_ALW_PCH
12
RC94
10
0K_0402_5%
PCH_SP
I_D0
12
RC518
@
4
.7K_0402_5%
Disabled
Enabled
V_ALW_PCH
12
RC62
10
0K_0402_5%
PCH_SP
I_D3
12
RC515
@
4
.7K_0402_5%
PLACE RC62 AND RC515 CLOS
TO THE SPI SIGNAL TO AVOID STUB
Disabled
Enabled
SPI - TOUCH
C LINK
SMBUS , SMLINK
LPC , ESPI
5 of
20
WEAK INTERNAL PU WEAK INTERNAL PU
BOOT HALT
HIGH
LOW
+3.3
WEAK INTERNAL PU
A0 PERSONALITY STRAP
HIGH
LOW
3
MEM_SMBCLK
CK14
MEM_SMBDATA
CH15
PCH_SMB_ALERT#
CJ15
Strap pin
SML0_SMBCLK
CH14
SML0_SMBDATA
CF15
GPP_C5
Strap pin
CG15
SML1_SMBCLK
CN15
SML1_SMBDATA
CM15
GPP_B23
CC34
ESPI_IO0_R
1.8V
CA29
ESPI_IO1_R
1.8V
BY29
ESPI_IO2_R
1.8V
BY27
ESPI_IO3_R
1.8V
BV27
CA28
1.8V
1.8V
CA27
ESPI_CLK
BV32
BV30
GPP_A8
BY30
566439_CNL_PCH_UY_EDS_Vol_1_Rev_1.1.pdf
External pull-up is required. Recommend 100K if pulled
up to 3.3V or 75K if pulled up to 1.8V. This strap should sample HIGH.
There should NOT be any on-board device driving it to opposite direction
during strap sampling.
SML0_SMBCLK [51]
SML0_SMBDATA [51]
SML1_SMBCLK [58]
SML1_SMBDATA [58]
1 2
RC366 15_0402_5%
1 2
RC367 15_0402_5%
1 2
RC368 15_0402_5%
1 2
RC369 15_0402_5%
ESPI_CS# [58,79]
ESPI_RESET# [58,79]
1 2
RC19 33_0402_5% EMI@
+3.3
V_ALW_PCH
12
RC61
10
0K_0402_5%
PCH_SP
12
RC519
@
4
.7K_0402_5%
PLACE RC61 AND RC519 CLOS
CONSENT STRAP
HIGH
LOW
TO THE SPI SIGNAL TO AVOID STUB
Disabled
Enabled
I_D2
ESPI_IO0 [58,79]
ESPI_IO1 [58,79]
ESPI_IO2 [58,79]
ESPI_IO3 [58,79]
RVP 15 ohm
575962_WHL-U_DDR4_RVP_Sch_Rev0p5.pdf
ESPI_CLK_5105 [58,79]
ESPI
_CLK_5105
SML0
_SMBCLK
SML1
_SMBCLK
MEM_
2
RF Request
1 2
CC316@
RF@ 33P_0402_50V8J
1 2
CC318@
RF@ 33P_0402_50V8J
1 2
CC319@
RF@ 33P_0402_50V8J
SMBCLK
1 2
CC320@
RF@ 33P_0402_50V8J
MEM_SMBCLK
MEM_SMBDATA
Place close CPU side
+3.3V_RUN
6
5
L2N7002DW1T1G_SC88-6
3 4
QC2B
L2N7002DW1T1G_SC88-6
2
1
DDR_XDP_WAN_SMBCLK [23,24,67,79]
QC2A
DDR_XDP_WAN_SMBDAT [23,24,67,79]
DDR_
XDP_WAN_SMBDAT
DDR_
XDP_WAN_SMBCLK
GPP_
MEM_
SMBCLK
MEM_
SMBDATA
SML1
_SMBCLK
SML1
_SMBDATA
SML0
_SMBCLK
SML0
_SMBDATA
RTC_DE
T#
SML0
_SMBCLK
SML0
_SMBDATA
RC318 2
RC319 2
A8
1
1 2
1 2
1 2
RC849
1 2
RC12 1K
1 2
RC14 1K
1 2
RC15 1K
1 2
RC507
1 2
RC347
1 2
RC348
1 2
RC866
1 2
RC506
1 2
RC20 49
+3.3
.2K_0402_5%
.2K_0402_5%
8.2K_0402_5%@
+3.3
_0402_5%
_0402_5%
_0402_5%
1K_0402_5%
499_0402_1%
499_0402_1%
1
0K_0402_5%
+3.3
499_0402_1%@
9_0402_1%@
V_RUN
V_ALW_PCH
V_LAN
+3.3
V_ALW_PCH
PCH_SM
B_ALERT#
1 2
RC266 4
.7K_0402_5%
B B
PCH_SP
I_D1_R1[66]
PCH_SP
I_D0_R1[66]
PCH_SP
I_CLK_R1[66]
PCH_
SPI_CLK_1_R
33_0402_5%
@
12
EMI@
RC289
A A
33P_0402_50V8J
12
CC145
2
5
PCH_
SPI_CLK_0_R
33_0402_5%
@
12
EMI@
RC299
@EMI@
33P_0402_50V8J
@EMI@
12
CC145
3
PCH_
PCH_
PCH_
PCH_
SPI_CS#0_R1
SPI_D2_R1
SPI_CS#1_R1
SPI_D2_R1
4
RC32 0_
@
1 2
1 2
RC33 49
VPRO@
NVPRO@
1 2
RC302 0
1 2
RC35 33
NVPRO@
0201_5%
.9_0201_1%
_0201_5%
_0201_1%
PCH_
PCH_
PCH_
PCH_
PCH_
PCH_
SPI_CS#0_R2
SPI_D1_0_R
SPI_D2_0_R
SPI_CS#1_R2
SPI_D1_1_R
SPI_D2_1_R
SOFTWARE TAA
VPRO PDG P.296 R1 50 ohm
PCH_
SPI_D1_R1
RC734 4
PCH_
SPI_D0_R1
RC570 4
PCH_
SPI_CLK_R1
RC571 4
PCH_
SPI_D3_R1
RC572 4
NVPRO follow PDG P.298 R1 33 oh m
PCH_
SPI_D1_R1
RC573 3
PCH_
SPI_D0_R1
RC574 3
PCH_
SPI_CLK_R1
RC575 3
PCH_
SPI_D3_R1
RC576 3
PDG SPI0 2 resistor 50ohm, SPI0 3 resistor 33ohm
CLOSEED TO ROM
Please place close for future replace to RP
For vPro
32MB WSON8 Flash ROM
For Non-vPro
8MB WSON8 Flash ROM
UC5VPRO@
1
CS#
2
DO
3
IO2
4
GND
W25Q
256JVEIQ_WSON8_8X6
For Non-vPro
16MB SOP8 Flash ROM
UC6NVPRO@
1
CS#
2
DO(I
3
IO2
4
GND
W25Q
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
Them
VCC
O1)
CLK
DI(I
O0)
128JVSIQ_SO8
PCH_
SPI_D1_0_R
9.9_0201_1%VPRO@
PCH_
SPI_D0_0_R
9.9_0201_1%VPRO@
PCH_
SPI_CLK_0_R
9.9_0201_1%VPRO@
PCH_
SPI_D3_0_R
9.9_0201_1%VPRO@
PCH_
SPI_D1_1_R
3_0201_1%NVPRO@
PCH_
SPI_D0_1_R
3_0201_1%NVPRO@
PCH_
SPI_CLK_1_R
3_0201_1%NVPRO@
PCH_
SPI_D3_1_R
3_0201_1%NVPRO@
+3.3
V_SPI
0.1
U_0201_10V6K
8
VCC
PCH_
SPI_D3_0_R
7
IO3
PCH_
SPI_CLK_0_R
6
CLK
PCH_
SPI_D0_0_R
5
DI
9
alPad
+3.3
V_SPI
0.
8
7
IO
6
5
1U_0201_10V6K
PCH_
SPI_D3_1_R
PCH_
SPI_CLK_1_R
PCH_
SPI_D0_1_R
3
CC9
1 2
NVPRO@
CC10
1 2
VPRO
PDG P.296 R2 5 ohm
NVPRO PDG P.298 R2 10 ohm
1 2
NVPRO@
RC24 0_
1 2
RC25 4.
VPRO@
1 2
RC26 4.
VPRO@
1 2
RC27 4.
VPRO@
1 2
RC28
@
1 2
RC29 4.
VPRO@
1 2
RC30 4.
VPRO@
+3.3
V_SPI
+3.3
V_ALW_PCH
@
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
RC31
DC4
PROM_
1 2
RB52
PCH_SP
PCH_SP
0201_5%
PCH_SP
99_0201_1%
PCH_SP
PCH_SP
PCH_SP
99_0201_1%
PCH_SP
99_0201_1%
PCH_SP
PCH_SP
PCH_SP
0_
0201_5%
PCH_SP
99_0201_1%
PCH_SP
PCH_SP
99_0201_1%
PCH_SP
BIOS_R[63]
0_
0402_5%
21
1CM-30T2R_SOD923-2
I_CS#1_R1
I_D0_R1
I_D1_R1
I_CLK_R1
I_CS#0_R1
I_D2_R1
I_D3_R1
JSPI
1
CONN@
1
I_CS#1
I_D0
I_D1
I_CLK
I_CS#0
I_D2
I_D3
2
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
2
1
GND1
2
2
GND2
ACES_50506-02041-P01
TLS CONFIDENTIALITY
HIGH
LOW(DEFAULT)
GPP_
C5
GPP_
C5
EC interface
HIGH
LOW (DEFAULT)
GPP_
ENABLE
DISABLE
1 2
RC277
@
1 2
RC397 2
ESPI
LPC
B23
1 2
RC317 1
for DCI-OOB
EXI BOOT STALL BYPASS
HIGH
LOW(DEFAULT)
WEAK
INTERNAL PD
ENABLED
DIABLED
+3.3
4
.7K_0402_5%
0K_0402_5%
+3.3
50K_0402_5%
V_ALW_PCH
V_ALW_PCH
DELL CONFIDENTIAL/PROPRIETARY
Comp
Comp
Comp
al Electronics, Inc.
al Electronics, Inc.
Titl
Titl
Titl
e
e
e
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
P09-M
P09-M
P09-M
CP(3/14)SPI,SMB,LPC
CP(3/14)SPI,SMB,LPC
CP(3/14)SPI,SMB,LPC
LA-G8
LA-G8
LA-G8
91P
91P
91P
1
8 102M
8 102M
8 102M
of
of
of
0.3
0.3
0.3
5
D D
HDD_FALL_INT[67]
T12
PCH_3.3V_TS_EN[38]
CNV_BRI_PRX_DTX[52]
CNV
_RGI_PTX_DRX_R[52]
CNV
_BRI_PTX_DRX_R[52]
CNV
_RGI_PRX_DTX[52]
PU OPTION TO AVOID RSP SIGNALS
+1.
C C
B B
FROM FLOATING IN CASE INTERNAL PUS NOT ENABLED IN A0
8V_PRIM
12
12
+3.
3V_RUN
12
RC5
12
12
RC8
@
CNV
_BRI_PRX_DTX
RC7
2420K_0402_5% @
CNV
_RGI_PRX_DTX
RC7
3320K_0402_5% @
HDD
_FALL_INT
810K_0402_5%
PCH
_3.3V_TS_EN
RC7
47100K_0402_5% @
GPP
_A7
4110K_0402_5%
1 2
RC7
10 33_0402_5%
1 2
RC7
11 33_0402_5%
@
T39
9
PAD~D
@
T40
0
PAD~D
TS
TP
T38
T38
T37
T37
add I2C3 TP for for sensor IC(Reserved)
add I2C3_ANT TP for ACTIVE STEERING ANT for MERION 14"
TS_
TS_
@
PAD~D
TPM_PIRQ#[66]
I2C_SDA[38]
I2C_SCL[38]
I2C
I2C
@
8
@
9
@
8
@
9
1
1
PAD~D
PAD~D
PAD~D
PAD~D
P_S
TS_
INT#[38]
1_SDA_TP[63]
1_SCK_TP[63]
4
PRIM_CORE_OPT_DIS
GPP_A7
ONE_DIMM#
NRB_BIT
HDD_FALL_INT
1
PME#
TPM_PIRQ#
PCH_3.3V_TS_EN
GPP_B22
CNV_BRI_PRX_DTX
CNV
_RGI_PTX_DRX
CNV
_BRI_PTX_DRX
CNV
_RGI_PRX_DTX
3MM
_CAM_DET#
ENSOR_PWR_SAVE#
TS_
INT#
I2C
2_SDA_ALS
1
I2C
2_SCL_ALS
1
I2C
3_ANT_SDA
1
I2C
3_ANT_SCL
1
UC1F
CC27
GPP_B15/GSPI0_CS0#
CC32
GPP_A7/PIRQA#/GSPI0_CS1#
CE28
GPP_B16/GSPI0_CLK
CE27
GPP_B17/GSPI0_MISO
CE29
GPP_B18/GSPI0_MOSI
CA31
GPP_B19/GSPI1_CS0#
CA32
GPP_A11/PME#/GSPI1_CS1#/SD_VDD2_PWR_EN#
CC29
GPP_B20/GSPI1_CLK
CC30
GPP_B21/GSPI1_MISO
CA30
GPP_B22/GSPI1_MOSI
CK20
GPP_F5/CNV_BRI_RSP
CG19
GPP
_F6/CNV_RGI_DT
CJ20
GPP
_F4/CNV_BRI_DT
CH19
GPP
_F7/CNV_RGI_RSP
CR12
GPP
_C20/UART2_RXD
CP12
GPP
_C21/UART2_TXD
CN12
GPP
_C22/UART2_RTS#
CM12
GPP
CM11
CN11
CK12
CJ12
CF27
CF29
CH27
CH28
CJ30
CJ31
WHL-U42_BGA1528
+1.
8V_PRIM
1 2
12
_C23/UART2_CTS#
GPP
_C16/I2C0_SDA
GPP
_C17/I2C0_SCL
GPP
_C18/I2C1_SDA
GPP
_C19/I2C1_SCL
GPP
_H4/I2C2_SDA
GPP
_H5/I2C2_SCL
GPP
_H6/I2C3_SDA
GPP
_H7/I2C3_SCL
GPP
_H8/I2C4_SDA
GPP
_H9/I2C4_SCL
20K_0402_5%
RC8
42
CNV
4.7K_0402_5%
@
RC8
32
_RGI_PTX_DRX_R
I2C
, UART
3
ISH
6 o
f 20
GPP_D11/ISH_SPI_MISO/GSPI2_MISO
GPP_D12/ISH_SPI_MOSI/GSPI2_MOSI
GPP
GPP
_D16/ISH_UART0_CTS#/SML0BALERT#
GPP
GPP
GPP
_C14/UART1_RTS#/ISH_UART1_RTS#
GPP
_C15/UART1_CTS#/ISH_UART1_CTS#
GPP
_A12/ISH_GP6/BM_BUSY#/SX_EXIT_HOLDOFF#
GPP_D9/ISH_SPI_CS#/GSPI2_CS0#
GPP_D10/ISH_SPI_CLK/GSPI2_CLK
GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL
GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL
GPP
_H10/I2C5_SDA/ISH_I2C2_SDA
GPP
_H11/I2C5_SCL/ISH_I2C2_SCL
GPP
_D13/ISH_UART0_RXD
GPP
_D14/ISH_UART0_TXD
_D15/ISH_UART0_RTS#/GSPI2_CS1#
_C12/UART1_RXD/ISH_UART1_RXD
_C13/UART1_TXD/ISH_UART1_TXD
GPP
_A18/ISH_GP0
GPP
_A19/ISH_GP1
GPP
_A20/ISH_GP2
GPP
_A21/ISH_GP3
GPP
_A22/ISH_GP4
GPP
_A23/ISH_GP5
2
IR_CAM_DET#
CN22
CR22
TBT_DET#
CM22
GPP_D12
CP22
ISH_I2C0_ACC_SDA
CK22
ISH_I2C0_ACC_SCL
CH20
ISH_I2C1_ALS_SDA
CH22
ISH_I2C1_ALS_SCL
CJ22
ISH
CJ27
ISH
CJ29
SML0
CM24
SML0
CN23
WWA
CM23
CR24
SIO
CG12
CH12
LCD
CF12
PCH
CG14
ISH
BW35
ISH
BW34
ISH
CA37
ISH
CA36
ISH
CA35
ISH
CA34
ISH
BW37
NB_MODE for NB13/Bandon
LID_CL#_NB for NB13/Bandon
LID_CL#_TAB for NB13/Bandon
ISH
_I2C2_SDA
ISH
_I2C2_SCL
1
1
1
1
_I2C2_SDA
_I2C2_SCL
B_SMBDATA
B_SMBCLK
N_FULL_PWR_EN
_EXT_WAKE#
_CBL_DET#
_HDD_EN
_ACC1
1
_ACC2
1
_TABLE_MODE#
1
_ALS
1
_NB_MODE
1
_LID_CL#_NB
1
_LID_CL#_TAB
1
5/23 Fibocom recommend to PH 1.8V.
1 2
RC3
63 1K_0402_5%
1 2
RC3
62 1K_0402_5%
IR_CAM_DET# [38]
@
T415
PAD~D
@
T416
PAD~D
@
T401
PAD~D
@
T402
PAD~D
ISH
_I2C2_SDA [52]
ISH
_I2C2_SCL [52]
RESERVE
WWA
N_FULL_PWR_EN [52]
SIO
_EXT_WAKE# [58]
LCD
_CBL_DET# [38]
PCH
_HDD_EN [67]
@
T39
5
PAD~D
@
T39
6
PAD~D
@
T39
7
PAD~D
@
T39
8
PAD~D
@
T37
5
PAD~D
@
T37
6
PAD~D
@
T37
7
PAD~D
+3.
3V_RUN
SML
0B_SMBCLK
PRI
M_CORE_OPT_DIS
SIO
_EXT_WAKE#
SML0
B_SMBCLK
SML0
B_SMBDATA
GPP
_D12
LCD
_CBL_DET#
IR_
CAM_DET#
TBT_DET#
RF Request
RC8
RC7
RC8
RC8
RC8
RC7
RC3
1
+3.3V_ALW_PCH
RC400
10K_0402_5%
1 2
12
10K_0402_5%
RC401
@
1 2
CC1
476@RF@ 33P_0402_50V8J
Place close CPU side
+3.
1 2
62 10K_0402_5%
1 2
48 10K_0402_5%
1 2
29 1K_0402_5%@
1 2
30 1K_0402_5%@
1 2
47 100K_0402_5%
1 2
49 100K_0402_5%
12
45 100K_0402_5%
3V_ALW_PCH
+3.
3V_RUN
AR_DET#
HIGH NON AR
LOW A
R
M.2
CNVI MODES
0 = Integrated CNVi enable.
1 = Integrated CNVi disable. (Disable CNVi for bring up)
4
WEAK INTERNAL PU
DIMM Detect
HIGH
LOW
+3.
3V_ALW_PCH
5
PRI
M_CORE_OPT_DIS
SIO
SIO
_SLP_S0#[11,17,66,79,87]
ONE
_DIMM#
10K_0402_5%
12
RC5
3
1 DIMM
2 DIMM
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
_SLP_S0#
1
2
1 2
RC8
67 0_0201_5%@
RC6
INB
INA
3
1 2
60 0_0201_5%@
UC9
M
C74VHC1G32DFT2G_SC70-5~D
P
4
O
G
2
RES
ERVE FOR WAKE ON VOICE
VR_
LPM_R# [87]
DEL
Tit
Tit
Tit
le
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
L CONFIDENTIAL/PROPRIETARY
Com
Com
Com
pal Electronics, Inc.
pal Electronics, Inc.
pal Electronics, Inc.
P10
P10
P10
-MCP(4/14)GSPI,I2C,UART,ISH
-MCP(4/14)GSPI,I2C,UART,ISH
-MCP(4/14)GSPI,I2C,UART,ISH
LA-
LA-
LA-
G891P
G891P
G891P
1
9 10
9 10
9 10
of
of
of
2Monday, February 25, 2019
2Monday, February 25, 2019
2Monday, February 25, 2019
0.3
0.3
0.3
+3.
3V_ALW_PCH
NRB
1 2
RC8
31 4.7K_0402_5%
_BIT
NO REBOOT STRAP
2.2K_0402_5%
RC4
6
_B22
No REBOOT
REBOOT ENABLE
HIGH
LOW(DEFAULT)
Weak IPD
+3.
3V_ALW_PCH
A A
12
@
GPP
BOOT BIOS Destination(Bit 6)
HIGH
LOW(DEFAULT)
5
LPC
SPI
5
4
3
2
1
AR,NB_Bandon DSC(follow WHL 180306C port map)
D D
M.2 3042 (LTE) --->
Card Reader RTS5242--->
10/100/1G LAN --->
M.2 2230(WLAN) --->
C C
Spindel HDD--->
M.2 3042(SATA Cache
or/HCA)--->
M2 2280 SSD --->
B B
USB3_PRX_DTX_N5[52]
USB3_PRX_DTX_P5[52]
USB3_PTX_DRX_N5[52]
USB3_PTX_DRX_P5[52]
PCIE
_PRX_DTX_N8[70]
PCIE
_PRX_DTX_P8[70]
PCIE
_PTX_DRX_N8[70]
PCIE
_PTX_DRX_P8[70]
PCIE
_PRX_DTX_N9[51]
PCIE
_PRX_DTX_P9[51]
PCIE
_PTX_DRX_N9[51]
PCIE
_PTX_DRX_P9[51]
PCIE
_PRX_DTX_N10[52]
PCIE
_PRX_DTX_P10[52]
PCIE
_PTX_DRX_N10[52]
PCIE
_PTX_DRX_P10[52]
SATA
_PRX_DTX_N11[67]
SATA
_PRX_DTX_P11[67]
SATA
_PTX_DRX_N11[67]
SATA
_PTX_DRX_P11[67]
PCIE
_PRX_DTX_N12[52]
PCIE
_PRX_DTX_P12[52]
PCIE
_PTX_DRX_N12[52]
PCIE
_PTX_DRX_P12[52]
PCIE
_PRX_DTX_N13[68]
PCIE
_PRX_DTX_P13[68]
PCIE
_PTX_DRX_N13[68]
PCIE
_PTX_DRX_P13[68]
PCIE
_PRX_DTX_N14[68]
PCIE
_PRX_DTX_P14[68]
PCIE
_PTX_DRX_N14[68]
PCIE
_PTX_DRX_P14[68]
PCIE
_PRX_DTX_N15[68]
PCIE
_PRX_DTX_P15[68]
PCIE
_PTX_DRX_N15[68]
PCIE
_PTX_DRX_P15[68]
PCIE
_PRX_DTX_N16[68]
PCIE
_PRX_DTX_P16[68]
PCIE
_PTX_DRX_N16[68]
PCIE
_PTX_DRX_P16[68]
1 2
RC50 1
Jony _12/21: Refer RVP keep it setting
570990_CFL_U_DDR4_RVP_CRB_Sch_Rev0p8.pdf
00_0402_1%
PCIE
PCIE
_RCOMPN
_RCOMPP
UC1H
BW9
PCIE5_RXN/USB31_5_RXN
BW8
PCIE5_RXP/USB31_5_RXP
BW4
PCIE5_TXN/USB31_5_TXN
BW3
PCIE5_TXP/USB31_5_TXP
BU6
PCIE6_RXN/USB31_6_RXN
BU5
PCIE6_RXP/USB31_6_RXP
BU4
PCIE6_TXN/USB31_6_TXN
BU3
PCIE6_TXP/USB31_6_TXP
BT7
PCIE
7_RXN
BT6
PCIE
7_RXP
BU2
PCIE
7_TXN
BU1
PCIE
7_TXP
BU9
PCIE
8_RXN
BU8
PCIE
8_RXP
BT4
PCIE
8_TXN
BT3
PCIE
8_TXP
BP5
PCIE
9_RXN
BP6
PCIE
9_RXP
BR2
PCIE
9_TXN
BR1
PCIE
9_TXP
BN6
PCIE
10_RXN
BN5
PCIE
10_RXP
BR4
PCIE
10_TXN
BR3
PCIE
10_TXP
BN10
PCIE
11_RXN/SATA0_RXN
BN8
PCIE
11_RXP/SATA0_RXP
BN4
PCIE
11_TXN/SATA0_TXN
BN3
PCIE
11_TXP/SATA0_TXP
BL6
PCIE
12_RXN/SATA1A_RXN
BL5
PCIE
12_RXP/SATA1A_RXP
BN2
PCIE
12_TXN/SATA1A_TXN
BN1
PCIE
12_TXP/SATA1A_TXP
BK6
PCIE
13_RXN
BK5
PCIE
13_RXP
BM4
PCIE
13_TXN
BM3
PCIE
13_TXP
BJ6
PCIE
14_RXN
BJ5
PCIE
14_RXP
BL2
PCIE
14_TXN
BL1
PCIE
14_TXP
BG5
PCIE
15_RXN/SATA1B_RXN
BG6
PCIE
15_RXP/SATA1B_RXP
BL4
PCIE
15_TXN/SATA1B_TXN
BL3
PCIE
15_TXP/SATA1B_TXP
BE5
PCIE
16_RXN/SATA2_RXN
BE6
PCIE
16_RXP/SATA2_RXP
BJ4
PCIE
16_TXN/SATA2_TXN
BJ3
PCIE
16_TXP/SATA2_TXP
CE6
PCIE
_RCOMP_N
CE5
PCIE
_RCOMP_P
CR28
GPP_
CP28
GPP_
CN28
GPP_
CM28
GPP_
WHL-U42_BGA1528
H12/M2_SKT2_CFG_0
H13/M2_SKT2_CFG_1
H14/M2_SKT2_CFG_2
H15/M2_SKT2_CFG_3
USB_
OC3#
USB_
OC0#
USB_
OC1#
USB_
OC2#
PCIE / USB3.1 / SATA
8 of
1 2
RC75
7 20K_0402_5%@
1 2
RC75
8 20K_0402_5%@
1 2
RC75
9 20K_0402_5%@
1 2
RC76
0 20K_0402_5%@
PCIE1_RXN/USB31_1_RXN
PCIE1_RXP/USB31_1_RXP
PCIE1_TXN/USB31_1_TXN
PCIE1_TXP/USB31_1_TXP
PCIE2_RXN/USB31_2_RXN/SSIC_1_RXN
PCIE2_RXP/USB31_2_RXP/SSIC_1_RXP
PCIE2_TXN/USB31_2_TXN/SSIC_1_TXN
PCIE2_TXP/USB31_2_TXP/SSIC_1_TXP
PCIE3_RXN/USB31_3_RXN
PCIE
3_RXP/USB31_3_RXP
PCIE
3_TXN/USB31_3_TXN
PCIE
3_TXP/USB31_3_TXP
PCIE
4_RXN/USB31_4_RXN
PCIE
4_RXP/USB31_4_RXP
PCIE
4_TXN/USB31_4_TXN
PCIE
4_TXP/USB31_4_TXP
USB2
.0
USB2
USB2
GPP_
E9/USB2_OC0#/GP_BSSB_CLK
GPP_
E10/USB2_OC1#/GP_BSSB_DI
GPP_
GPP_
GPP_
GPP_
20
_VBUSSENSE
GPP_
E11/USB2_OC2#
GPP_
E12/USB2_OC3#
GPP_
GPP_
GPP_
E0/SATAXPCIE0/SATAGP0
E1/SATAXPCIE1/SATAGP1
E2/SATAXPCIE2/SATAGP2
E8/SATALED#/SPI1_CS1#
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
_10N
USB2
_10P
_COMP
USB2
E4/DEVSLP0
E5/DEVSLP1
E6/DEVSLP2
RSVD
CB5
CB6
CA4
CA3
BY8
BY9
CA2
CA1
BY7
BY6
BY4
BY3
BW6
BW5
BW2
BW1
CE3
_1N
CE4
_1P
CE1
_2N
CE2
_2P
CG3
_3N
CG4
_3P
CD3
_4N
CD4
_4P
CG5
_5N
CG6
_5P
CC1
_6N
CC2
_6P
CG8
_7N
CG9
_7P
CB8
_8N
CB9
_8P
CH5
_9N
CH6
_9P
CC3
CC4
CC5
CE8
_ID
CC6
CK6
CK5
CK8
CK9
CP8
CR8
CM8
CN8
CM10
CP10
CN7
AR3
_69
USB2
M304
M228
USBC
USB2
_ID
VBUS
USB_
OC3#
HDD_
DEVSLP
HDD_
DET#
M304
2_PCIE#_SATA
M228
0_PCIE_SATA#
HDD_DET#_reserve and HDD_DEVSLP is reserve for HDD SATA direct connect to PCH
_ID
2_PCIE#_SATA
0_PCIE_SATA#
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
USB2
OMP
RC47 1
SENSE
RC49 1
Reser
ve
HDD_
@
RC33
7
1 2
1 2
RC52
1 1K_0402_5%@
1 2
RC73
0 1K_0402_5%@
USB3_PRX_MTX_N1 [46]
USB3_PRX_MTX_P1 [46]
USB3_PTX_MRX_N1 [46]
USB3_PTX_MRX_P1 [46]
USB3_PRX_DTX_N2 [71]
USB3_PRX_DTX_P2 [71]
USB3_PTX_DRX_N2 [71]
USB3_PTX_DRX_P2 [71]
USB3_PRX_DTX_N3 [72]
USB3
_PRX_DTX_P3 [72]
USB3
_PTX_DRX_N3 [72]
USB3
_PTX_DRX_P3 [72]
USB3
_PRX_DTX_N4 [72]
USB3
_PRX_DTX_P4 [72]
USB3
_PTX_DRX_N4 [72]
USB3
_PTX_DRX_P4 [72]
0_N1 [44]
0_P1 [44]
0_N2 [71]
0_P2 [71]
0_N3 [72]
0_P3 [72]
0_N4 [72]
0_P4 [72]
0_N6 [38]
0_P6 [38]
0_N7 [52]
0_P7 [52]
0_N8 [66]
0_P8 [66]
0_N9 [66]
0_P9 [66]
0_N10 [52]
0_P10 [52]
1 2
1 2
USB_
USB_
USB_
HDD_
M304
M228
M304
M228
13_0402_1%
USB2
_ID [44]
K_0402_5%
OC0# [71]
OC1# [72]
OC2# [72]
DEVSLP [67]
2_DEVSLP [52]
0_DEVSLP [68]
DET# [67]
2_PCIE#_SATA [58]
0_PCIE_SATA# [68]
0_0402_5%
-----> TYPE-C (GEN2)
-----> Ext USB3 Port 1 Charge
-----> Ext USB3 Port 2
-----> Ext USB3 Port 3
Typce-C(NON AR)
Ext
USB Port 1 Charge
Ext USB Port 2
Ext
USB Port 3
Camera
M.2
3042 (WWAN)
USH
FPR in PB
M.2 2230 (BT)
M228
0_PCIE_SATA#
2_PCIE#_SATA
DET#
DET#
@
RC76
RC76
RC76
RC52
M304
HDD_
HDD_
12
4 10K_0402_5%
12
6 10K_0402_5%
12
5 10K_0402_5%
1 2
0
1K_0402_5%
+3.3
+3.3
V_RUN
V_ALW_PCH
USB_
OC3#
RC83
USB_
USB_
USB_
M304
A A
2_DEVSLP
6
OC0#
RC83
7 10K_0402_5%
OC1#
RC83
9 10K_0402_5%
OC2#
RC83
8 10K_0402_5%
RC86
5 10K_0402_5%
10K_0402_5%
12
12
12
12
12
DELL CONFIDENTIAL/PROPRIETARY
Comp
Comp
Comp
al Electronics, Inc.
al Electronics, Inc.
Titl
Titl
Title
e
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
e
P11-
P11-
P11-
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
MCP(5/14)PCIE,USB,SATA
MCP(5/14)PCIE,USB,SATA
MCP(5/14)PCIE,USB,SATA
LA-G
LA-G
LA-G
891P
891P
891P
10 102M
10 102M
10 102M
of
of
1
of
0.3
0.3
0.3
5
CLK_PCIE_N0[52]
M.2 3042 WWAN--->
M.2 2230 WLAN--->
D D
M.2 2280 SSD--->
LAN--->
Card Reader --->
+3.
3V_LAN
RL7
0 10K_0402_5%@
+3.
3V_ALW_DSW
RC3
23 10K_0402_5 %
RC6
+1.
0V_VCCST
7 1K_0402_5%
RC7
1 1K_040 2_5%
RC5
36 10K_040 2_5%@
C C
PCH GLITCH ISSUE MITIGATION(PDG p.130)
B B
+3.
3V_ALW_PCH
A A
H_C
PUPWR GD
100P_0402_50V8J
12
CC30
0ESD@
ESD Request:place near CPU side
CLK_PCIE_P0[52]
CLKREQ_PCIE#0[52]
+3.3V_RUN
CLK_PCIE_N1[52]
CLK_PCIE_P1[52]
CLKREQ_PCIE#1[52]
+3.3V_RUN
CLK_PCIE_N2[68]
CLK_PCIE_P2[68]
CLKREQ_PCIE#2[68]
+3.3V_RUN
CLK_PCIE_N3[51]
CLK_PCIE_P3[51]
CLKREQ_PCIE#3[51]
+3.3V_RUN
CLK_PCIE_N4[70]
CLK_PCIE_P4[70]
CLKREQ_PCIE#4[70]
+3.3V_RUN
LAN
_WAKE#
12
12
PCH
_PCIE_W AKE#
12
VCC
ST_PWRGD
12
PCH
_PWROK
12
SIO
_SLP_SUS #
12
RC2
29100K_0 402_5%
12
CC1
4650.33U_0402_ 10V6K~D @
SIO
_SLP_S4#
12
RC2
32100K_0 402_5%
12
CC1
4670.33U_0402_ 10V6K~D @
SIO
_SLP_S3#
12
RC2
31100K_0 402_5%
12
CC1
4680.33U_0402_ 10V6K~D @
SIO
_SLP_A#
12
RC2
33100K_0 402_5%
12
CC1
4690.33U_0402_ 10V6K~D @
SIO
_SLP_W LAN#
12
RC2
34100K_0 402_5%
12
CC1
4700.33U_0402_ 10V6K~D @
SIO
_SLP_LAN#
12
RC7
61100K_0 402_5%
12
CC1
4710.33U_0402_ 10V6K~D @
SIO
_SLP_S5#
12
RC2
30100K_0 402_5% @
PCH
_PLTRST#
12
RC2
37100K_0 402_5%
@
SIO
_SLP_S0#
12
RC7
63100K_0 402_5%
VCC
ST_PWRGD
100P_0402_50V8J
12
CC30
1ESD@
5
RC297 0_020 1_5%
1 2
@RF@
RC189 10K_0402_5 %
RC526 0_0402_5%
@RF@
RC522 10K_0402_5 %
RC727 0_0402_5%
@RF@
RC525 10K_0402_5 %
RC527 0_0402_5%
@RF@
RC523 10K_0402_5 %
RC528 0_0402_5%
@RF@
RC51 10K_0402 _5%
1 2
1 2
1 2
1 2
PCH
_PLTRST#
12
12
12
12
12
M
C74VHC1G08D FT2G SC70
S4 power side PD need @,need check
RC215
POP
NO Support Deep sleep
DE-POP
Support Deep sleep
PCH
_DPWR OK
1 2
RC2
15 0_0402_5%
@NDS3@
0.01UF_0402_25V7K
100K_0402_1%
12
1
@
CC26
RC22
6
0
2
RC7
@
UC7
PCH
_RSMRST#_AN D
CLKREQ_PC IE#0_R
CLKREQ_PC IE#1_R
CLKREQ_PC IE#2_R
CLKREQ_PC IE#3_R
CLKREQ_PC IE#4_R
1 2
39
+3.
3V_ALW_PCH
1
B
2
A
@
T35
5
1
12
0K_0402_5%
5
3
PAD~D
0_0402_5%
P
PCH
4
O
12
G
1
VCC
RC75
AW2
CF32
CE32
CF30
CE31
CE30
CF31
PLT
RST_LAN# [51]
_PLTRST#_AND
@
RC6
5
100K_0402_ 5%
PCH
_RSMRST#_AND[63,79]
H_C
PUPWR GD_R
ST_PWRGD[59,79]
ME_
SUS_PWR_ACK is for LPC use only
SUSA
CK# is for LPC use only
4
CPU@
UC1J
CLKOUT_PCIE_N_0
AY3
CLKOUT_PCIE_P_0
GPP_B5/SRCCLKREQ0#
BC1
CLKOUT_PCIE_N_1
BC2
CLKOUT_PCIE_P_1
GPP_B6/SRCCLKREQ1#
BD3
CLKOUT_PCIE_N_2
BC3
CLKOUT_PCIE_P_2
GPP_B7/SRCCLKREQ2#
BH3
CLKOUT_PCIE_N_3
BH4
CLKOUT_PCIE_P_3
GPP_B8/SRCCLKREQ3#
BA1
CLKOUT_PCIE_N_4
BA2
CLKOUT_PCIE_P_4
GPP_B9/SRCCLKREQ4#
BE1
CLKOUT_PCIE_N_5
BE2
CLK
OUT_PCIE_P_5
GPP
_B10/SRCCLKREQ5#
WHL-U42 _BGA1528
PCH
_PLTRST#_AND [38,52,68,70]
SYS
_RESET#[79]
1 2
RC7
7 1K_0402_5%@
1 2
RC7
8 62_0402_5%
SYS
PCH
PCH
T38
0
T38
1
PCH
_PCIE_WAKE#[58,59]
PM_
LANPHY_ENABLE[51]
PCH
_PLTRST#_AND
.047U_0402_16V7K
12
CC19
6ESD@
For ESD solution
4
3
CLOCK SINGNALS
10
of 20
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
GPD8/SUSCLK
XTAL_OUT
XCLK_BIASREF
CLKIN_XTAL
SRTCRST#
RTCRST#
XTAL_IN
RTCX1
RTCX2
AU1
AU2
BT32
CK3
CK2
CJ1
CM3
BN31
BN32
BR37
BR34
CLK_ITPXDP_N
CLK_ITPXDP_P
SUSCLK
XTAL24_IN_CPU
XTAL24_OUT_CPU
XCLK_BIASR EF
REFCLK_CNV
PCH_RTCX1
PCH_RTCX2
SRTCRST#
PCH_RTCRST#
1 2
RC530 0_0402_5%@
1 2
RC298 0_0402_5%@
@
1 2
RC402 60.4_040 2_1%
1 2
LC5 BLM15BD121S N1D_2P~DESD@
LC5 place near CPU side
ESD Request
0419 ESD YuHeng: follow Intel recomme ndation
RC56 20K_0402 _5%
CC24 1U_0 201_6.3V6M
PCH_RTCRST# [58,79]
RC57 20K_0402 _5%
CC25 1U_0 201_6.3V6M
1
SUSCLK [52,68]
12
CC93 0.1U 16V K X5R 020 1
1 2
1 2
1 2
1 2
2
1
2
CMO
S1 SHORT PADS~D@
CLK_ITPXDP_N_R [79]
CLK_ITPXDP_P_R [79]
REFCLK_CNV_L [52]
+RTC_CELL_PCH
CMOS1 must take care short & touch risk on layout placement
PCH
_PLTRST#
PCH
_PLTRST#_AND
Support DS3
No Support DS3
1 2
RC6
0 0_0402_5%@
1 2
RC7
38 0_0402_5 %@
RC439
RC440RE536 RC215 RC441RC442
V V V
X X
PLT
RST_TPM# [66]
X
X
V V V
X
VCC
DSW_EN_GPIO[18]
VCC
DSW_EN[58]
X
@
ALW
_PWRGD_3V_5V[63,85]
'V' mean POP, 'X' mean DE-POP
UC1
PCH
_PLTRST#
SYS
_RESET#
PCH
_RSMRST#_AN D
H_C
PUPWR GD
VCC
ST_PWRGD _CPU
_PWROK[58,79]
_PWROK[88 ]
_DPWROK[58]
LAN
GPP
_A13
1
@
PAD~D
GPP
_A15
1
@
PAD~D
_WAKE#[51,58]
K
BJ35
GPP
_B13/PLTRST#
CN10
SYS
_RESET#
BR36
RSM
RST#
AR2
PRO
CPWRGD
BJ2
VCC
ST_PWRGOOD
CR10
SYS
_PWROK
BP31
PCH
_PWROK
BP30
DSW
_PWROK
BV34
GPP
_A13/SUSWARN#/SUSPWRDACK
BY32
GPP
_A15/SUSACK#
BU30
WAK
E#
BU32
GPD
2/LAN_WAKE#
BU34
GPD
11/LANPHYPC
WHL-U42 _BGA1528
XDP
_DBRESET#[79]
SYSTEM POWER MANAGEMENT
GPP
11
of 20
+3.
3V_ALW_PCH
RC2
48
@
2.2K_0402_ 5%
1 2
@
RC2
1
CC7
0.1U_0402_2 5V6
2
GPP
_B12/SLP_S0#
GPD
GPD
GPD
GPD
9/SPL_WLAN#
GPD
GPD
3/PWRBTN#
GPD
1/ACPRESENT
GPD
INT
_B11/EXT_PWR_GATE#
GPP
_B2/VRALERT#
INP
1 2
43
8
4/SLP_S3#
5/SLP_S4#
10/SLP_S5#
SLP
_SUS#
SLP
_LAN#
6/SLP_A#
0/BATLOW#
RUDER#
UT3VSEL
SYS
0_0402_5%
BJ37
BU36
BU27
BT29
BU29
BT31
BT30
BU37
BU28
BU35
BV36
BR35
CC37
CC36
BT27
_RESET#
ESD Request:place near CPU side
SIO
SIO
SIO
PCH
INT
3.3
VRA
INP
12
_SLP_S0#
_SLP_S5#
_SLP_A#
_BATLOW#
RUDER#
V_CAM_EN #
LERT#
UT3VSEL
SYS
_RESET#
0.1U_0402_25V6
@ESD@
CC30
2
SIO
_SLP_S0# [9, 17,66,79,87]
SIO
_SLP_S3# [17 ,59,79]
SIO
_SLP_S4# [17 ,79,86,87]
SIO
_SLP_S5# [79 ]
SIO
_SLP_SUS# [58]
SIO
_SLP_LAN# [78]
SIO
_SLP_WLAN# [78]
SIO
_SLP_A# [79]
SIO
_PWRBTN# [58,79]
AC_
PRESENT [58]
3.3
V_CAM_EN# [38]
ESD Request
0419 ESD YuHeng: follow Intel recomme ndation
2
XTAL24_IN_CPU
XTAL24_OUT_CPU
PCH_RTCX2
1 2
RC4
45
0_0402_5%
+3.
3V_ALW_PCH
RC4
51
@
20K_0402_5 %
RC4
52
4.7K_0402_ 5%
REF
CLK_CNV
4.7P_0402_50V8C
ESD@
1
CC14
2
77
ESD Request:place near CPU side
Jony_1221: Refer RVP is 200 K ohm
570990_CFL_U_DDR4_RVP_CRB_Sch_Rev0p8.pdf
RECOMMENDED BY EMI
1 2
RC728 33_0402_5%
1 2
RC729 33_0402_5%
0_0402_5%
1 2
RC403
@
RC404
@
NDS3
R
B751540_S OD523
NDS3
R
B751540_S OD523
For deglitch,
refer to 575412_WHL_U_PDG rev0p8
0 = 3.3V supply is 3.3V +/- 5% (3.3V for bring up)
1 = 3.3V supply is 3.0V +/- 5%
1 2
INP
UT3VSEL
1 2
DC1
@
2 1
@
0_0402_5%
SIO
_SLP_SUS #
VCC
DSW_E N_Q
DC2
21
1 2
2
00K_0402_1%
XTAL24_IN
1 2
XTAL24_OUT
PCH_RTCX1_RPCH_RTCX1
PCH_RTCX2_R
@
RC531 0_0402_5%
RC5
@
REF
CLK_CNV
SUS
CLK
RC4
41
DS3@
1 2
0_0402_5%
RC4
42
@NDS3@
1 2
0_0402_5%
3.3
V_CAM_EN #
8/21 can change to 10K for merge to RP
PCH
_BATLOW#
AC_
PRESENT
INT
RUDER#
VRA
LERT#
SIO
_SLP_LAN#
RC59
XTAL24_OUT_R
1 2
RC66
10M_0402_5 %
1 2
1 2
32
0_0402_5%
RC7
51 10K_0402_5 %
1 2
RC4
8 1K_0 402_5%@
PCH
1 2
RC8
34 100K_040 2_5%
1 2
RC7
2 10K_ 0402_5%
1 2
RC5
55 10K_0402_5%
1 2
RC6
9 1M_0402_5%
1 2
RC7
3 10K _0402_5%
1 2
RC3
44 10K_0402_5 %@
1 2
RC6
8 10K _0402_5%@
1
15P_0402_5 0V8J
3
4
YC1
24MHZ_12PF_ 8Y24000034
1
2
15P_0402_5 0V8J
12
YC2
32.768KHZ_1 2.5PF_9H032 00042
ESR MAX=50k ohm
RTC
X2
12
_PRIM_EN [78,87]
+3.
3V_ALW_PCH
+3.
+RT
C_CELL_PCH
+3.
3V_ALW_PCH
+3.
CC21
1 2
CC22
1 2
CC23
1 2
15P_0402_5 0V8J
CC26
1 2
15P_0402_5 0V8J
3V_ALW_DSW
3V_ALW
DELL CONFIDENTIAL/PROPRIETARY
Com
Com
Com
pal Electronics, Inc.
pal Electronics, Inc.
Tit
Tit
Tit
le
le
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
le
P12
P12
P12
Size Docum ent Numbe r Rev
Size Docum ent Numbe r Rev
Size Docum ent Numbe r Rev
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronics, Inc.
-MCP(6/14)CLK,PM,RTC
-MCP(6/14)CLK,PM,RTC
-MCP(6/14)CLK,PM,RTC
LA-G
LA-G
LA-G
891P
891P
891P
1
11 10
11 10
11 10
of
of
of
0.3
0.3
0.3
2Mond ay, February 25, 2 019
2Mond ay, February 25, 2 019
2Mond ay, February 25, 2 019
5
4
3
2
1
UC1G
BN34
HDA_SYNC/I2S0_SFRM
BN37
HDA_BCLK/I2S0_SCLK
BN36
HDA_SDO/I2S0_TXD
BN35
HDA_SDI0/I2S0_RXD
BL36
HDA_SDI1/I2S1_RXD/SNDW1_DATA
BL35
HDA_RST#/I2S1_SCLK/SNDW1_CLK
CK23
GPP_D23/I2S_MCLK
BL37
I2S1_SFRM/SNDW2_CLK
BL34
I2S1_TXD/SNDW2_DATA
1.8V
CJ32
GPP_H1/I2S2_SFRM/CNV_BT_I2S_BCLK/CNV_RF_RESET#
CH32
GPP_H0/I2S2_SCLK/CNV_BT_I2S_SCLK
1.8V
CH29
GPP_H2/I2S2_TXD/CNV_BT_I2S_SDI/MODEM_CLKREQ
CH30
GPP_
H3/I2S2_RXD/CNV_BT_I2S_SDO
CP24
GPP_
D19/DMIC_CLK0/SNDW4_CLK
CN24
GPP_
D20/DMIC_DATA0/SNDW4_DATA
CK25
GPP_
D17/DMIC_CLK1/SNDW3_CLK
CJ25
GPP_
D18/DMIC_DATA1/SNDW3_DATA
CF35
GPP_
B14/SPKR
WHL-U42_BGA1528
12
ENABLE
DISABLE
SPKR
3 2.2K_0402_5%@
AUDIO SDIO / SDXC
GPP_
A17/SD_VDD1_PWR_EN#/ISH_GP7
7 of
20
GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
GPP_G5/SD_CD#
GPP_G6/SD_CLK
GPP_G7/SD_WP
GPP_
A16/SD_1P8_SEL
SD_1
P8_RCOMP
SD_3
P3_RCOMP
RF Request. Place near CPU side (Intel MOW)
HDA_
RST#
1
1
2
CC33
2.2P_0402_50V8C
@RF@
HDA_
SDIN0
1
2
2
CC33
2.2P_0402_50V8C
@RF@
HDA_
SDOUT
1
3
2
CC33
2.2P_0402_50V8C
@RF@
CH36
CL35
CL36
CPU_GC6_FB_EN
CM35
CONTACTLESS_DET#
CN35
HOST_SD_WP#
CH35
AUD_PWR_EN
CK36
SKP_DET#
CK34
ISH_
BW36
BY31
CK33
SD_R
CM34
P_SENSOR_INT#
COMP
1
PAD~D
1
PAD~D
1
P
AD~D
1 2
RC11
6 200_0402_1%
CAM_MIC_CBL_DET# [38]
T383
@
CONTACTLESS_DET# [66]
HOST_SD_WP# [70]
AUD_PWR_EN [56]
@
T384
@
T385
CNVI
HDA_SDIN0[56]
_EN#[52]
ET#[63]
HDA_SYNC
HDA_BIT_CLK
HDA_SDOUT
HDA_RST#
WWAN_GPIO_WAKE#
CNV_RF_RESET#
CLKREQ_CNV#
CNVI
_EN#
KB_D
ET#
DGPU
_PWROK
SPKR
+3.3
V_ALW_PCH
RC18
TOP SWAP STRAP
HIGH
LOW(DEFAULT)
Inte
rnal 20k PD
1 2
HDA_SYNC_R[56]
HDA_BIT_CLK_R[56]
HDA_SDOUT_R[56]
47P_0402_50V8J
Close
+3.3
V_ALW_PCH
+3.3
V_RUN
ME_FWP_PCH[79]
RF@
to RC93
RC27
RC27
RC29
D D
C C
B B
ME_FWP_PCH
HDA_RST#_R[56]
HDA_BIT_CLK_R
1
CC27
2
RC72
5 10K_0402_5%
RC84
0 10K_0402_5%
8 10K_0402_5%
9 10K_0402_5%
2 10K_0402_5%
RC92 33_0402_5%
RC93 33_0402_5%EMI@
RC561 33_0402_5%
RC562 1K_0402_5%
RC560 33_0402_5%
CAM_
MIC_CBL_DET#
12
WWAN
_GPIO_WAKE#
12
CONT
ACTLESS_DET#
12
AUD_
PWR_EN
12
HOST
_SD_WP#
12
1 2
1 2
1 2
1 2
WWAN_GPIO_WAKE#[52]
CNV_RF_RESET#[52]
CLKREQ_CNV#[52]
DVT2.0
1210 Add CNVI_EN#
KB_D
DGPU
_PWROK[58]
SPKR[
56]
+3.3
V_ALW_PCH
KB_D
ET#
RC28
A A
12
8 10K_0402_5%
CLKR
12
RC75
2 71.5K_0402_1%
1 2
RC64
0 75K_0402_5%
1 2
RC86
8 75K_0402_5%
5
CNV_
CNVI
EQ_CNV#
RF_RESET#
_EN#
+3.3
V_ALW_PCH
HDA_
SDOUT
RC18
12
7 4.7K_0402_5%@
Flash Descriptor Security override
HIGH
LOW(DEFAULT)
4
DISABLE
ENABLE
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
DELL
CONFIDENTIAL/PROPRIETARY
Comp
Comp
Comp
al Electronics, Inc.
al Electronics, Inc.
Titl
Titl
Titl
e
e
e
P13-
P13-
P13-
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
MCP(7/14)MISC,JTAG,HDA,SDIO
MCP(7/14)MISC,JTAG,HDA,SDIO
MCP(7/14)MISC,JTAG,HDA,SDIO
LA-G
LA-G
LA-G
891P
891P
891P
1
0.3
0.3
12 102M
12 102M
12 102M
0.3
of
of
of
5
4
3
2
1
1 2
RC120 1K_0402_1%@
EAR-STALL/NOT STALL RESET
SEQUENCE AFTER PCU PLL IS LOCKED
D D
CFG0
1 2
RC405 1K_0402_1%@
PCH/ PCH LESS MODE SELECTION
CFG1
1 2
RC4
06 1K_0402_1%@
PCI EXPRESS STATIC LANE REVERSAL
FOR ALL PEG PORTS
CFG2
C C
1 2
RC4
07 1K_0402_1%@
PCH/ PCH LESS MODE SELECTION
CFG3
1 2
RC7
23
0: AN EXTERNAL DISPLAY PORT DEVICE PORT IS CONNECTED TO THE EMBEDDED PORT
1: NO PHYSICAL DISPLAY PORT ATTACHED TO EMBEDDED DISPLAY PORT
DISPLAY PORT PRESENCE STRAP
CFG4
B B
RC4
RC4
1 2
09 1K_0402_1%@
1 2
10 1K_0402_1%@
CFG0
1:(DEFAULT)NORMAL OPERATION; NO STALL
0:STALL
CFG1
1: (DEFAULT) NORMAL OPERATION
0: PCH-LESS MODE
CFG
2
1: (DEFAULT)NORMAL OPERATION
0: LANE REVERSAL
CFG
3
1:(DEFAULT) NORMAL OPERATION
0: PCH-LESS MODE
CFG
4
1K_0402_5%
0: ENABLED
1: DISABLED;
CFG
5
CFG
6
1 2
RC411 1K_0402_1%@
PEG DEFER TRAINING
CFG7
1 2
RC412 1K_0402_1%@
ALLOW THE USE OF CFG ON LOCKED UNITS
1: DISABLED(DEFAULT); IN THIS CASE, CFG WILL BE
DISABLED IN LOCKED UNITS AND ENABLED IN UN-LOCKED UNITS AND
CFG8
0: EENABLED; CFG WILL BE
AVAILABLE REGARDLESS OF THE LOCKING OF THE UNIT
1 2
RC4
13 1K_0402_1%@
NO SVID PROTOCOL CAPABLE VR CONNECTED
CFG9
1 2
RC4
14 1K_0402_1%@
SAFE MODE BOOT
1: POWER FEATURES ACTIVATED DURING RESET
CFG10
0: POWER FEATURES (ESPECIALLY CLOCK GATINE ARE NOT ACTIVATED
1 2
RC4
15 1K_0402_1%@
DMI AC COUPLING - JUST A PLACE HOLDER.
NOT APPLICABLE FOR ULX-ULT
1:(DEFULT)
DMI WILL BE CONFIGURED AS HALF SWING DC COUPLED
CFG11
0:DMI WILL BE CONFIGURED AS FULL SWING AC COUPLED
1 2
RC4
16 1K_0402_1%@
PM SYNC LEGACY
CFG12
PCIE PORT BIFURCATION STRAPS
11: DEVICE1 FUNTION 1, DEVICE 1 FUNCTION2 DISABLED
10: DEVICE1 FUNTION 1, ENABLED DEVICE 1 FUNCTION2 DISABLED
RC4
1 2
17 1K_0402_1%@
CFG7
1: (DEFAULT) PEG TRAIN IMMEDIATELY
FOLLOWING XXRESETB DE ASSERTION
0: PEG WAIT FOR BIOS FOR TRAINING
CFG8
CFG
9
1:VRS SUPPORTING SVID PROTOCOL ARE PRESENT
0: NO VR SUPPORTING SVID
CFG
10
CFG
11
CFG
12
1: (DEFAULT) PMSYNC 2.0
0 : LEGACY
CFG
13
CFG[0..19][79]
Refer RVP CFG_RCOMP Keep 49.9 ohm to GND
570990_CFL_U_DDR4_RVP_CRB_Sch_Rev0p8.pdf
+1.
0V_PRIM_XDP
Refer RVP CFG_RCOMP Keep 1.5K to 1.0 VA
570990_CFL_U_DDR4_RVP_CRB_Sch_Rev0p8.pdf
nee
RC6
24 49.9_0402_1%
RC1
25 1.5K_0402_5%
ITP
_PMODE[79]
d check
UC1
Q
RES
_0
_1
_2
_3
_4
_5
_6
_7
_8
_9
_10
_11
_12
_13
_14
_15
_16
_18
_17
_19
_RCOMP
_PMODE
D25
D24
D34
D33
D22
D23
D66
D67
D17
D16
D35
D7
D6
D1
D30
D32
D31
ERVED SIGNALS
20
of 20
T4
CFG
0
CFG
R4
CFG
1
CFG
T3
CFG
2
CFG
R3
CFG
3
CFG
J4
CFG
4
CFG
M4
CFG
5
CFG
J3
CFG
6
CFG
M3
CFG
7
CFG
R2
CFG
8
CFG
N2
CFG
9
CFG
R1
CFG
10
CFG
N1
CFG
11
CFG
J2
CFG
12
CFG
L2
CFG
13
CFG
J1
CFG
14
CFG
L1
CFG
15
CFG
L3
CFG
16
CFG
N3
CFG
18
CFG
L4
CFG
17
CFG
N4
CFG
19
CFG
CFG
_RCOMP
12
ITP
_PMODE
12
AB5
CFG
W4
ITP
CG2
RSV
CG1
RSV
H4
RSV
H3
RSV
BV24
RSV
BV25
RSV
G3
RSV
G4
RSV
BK36
RSV
BK35
RSV
W3
RSV
AM4
RSV
AM3
RSV
A35
RSV
D34
RSV
G2
RSV
G1
RSV
WHL-U42_BGA1528
RSV
RSV
RSV
RSV
RSV
SKT
F37
D_TP5
F34
D_TP4
CP36
IST
_TRIG
CN36
D_TP3
BJ36
RSV
D15
BJ34
RSV
D14
BK34
TP_
1
BR18
TP_
2
BT9
RSV
D21
BT8
RSV
D20
BP8
RSV
D18
BP9
RSV
D19
CR4
RSV
D29
CP3
RSV
D26
CR3
RSV
D27
BP36
VSS
_434
AT3
RSV
D12
AU3
RSV
D13
AN1
RSV
D8
AN2
RSV
D9
AN4
RSV
D11
AN3
RSV
D10
AL2
RSV
D72
AL1
RSV
D73
AL4
RSV
D74
AL3
RSV
D75
BP34
TP_
4
BP35
TP_
3
C34
RSV
D68
A34
D_TP1
B35
D_TP2
CR35
RSV
D28
AH26
RSV
D36
AJ27
RSV
D37
E1
OCC#
SKT
@
RC4
OCC#
1
P
AD~D
1
P
AD~D
1
P
AD~D
1
P
AD~D
1
P
AD~D
1
P
AD~D
1
PAD~D
RC8
48 0_0201_5%
1
PAD~D
1
PAD~D
@
20
1
PAD~D
1
PAD~D
1
PAD~D
1
PAD~D
1 2
RC5
@
64 0_0402_5%
1 2
RC5
@
65 0_0402_5%
@
T16
@
T17
@
T18
@
T19
@
T20
@
T21
@
T36
12
@
T36
@
T36
0_0201_5%
12
@
T36
@
T36
@
T42
@
T41
0
1
3
+1.
0V_VCCSTG
4
5
3
9
12
36
RC4
100_0402_1%
@
CFG5,6
PCH/ PCH LESS MODE SELECTION
01: DEVICE1 FUNTION 1, DISABLED, DEVICE 1 FUNCTION2 ENABLED
00: DEVICE 1 FUNCTION 1 ENABLED, DEVICE 1 FUNCTION 2 ENABLED
PMSYNC AYNC MODE- PM SYNC
1: (DEFAULT)SYNCHCRONOUS (1 24 MHZ CYCLE PER BIT)
CFG13
0: ASYNC - 4-24MHZ CYCLES PER BIT
A A
RC4
1 2
18 1K_0402_1%@
CFG
14
RC4
1 2
19 1K_0402_1%@
CFG
15
DELL CONFIDENTIAL/PROPRIETARY
Com
Com
Com
pal Electronics, Inc.
pal Electronics, Inc.
CFG14 CFG15
5
Tit
Tit
Tit
le
le
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronics, Inc.
P14
P14
P14
-MCP(8/14)CFG,RSVD
-MCP(8/14)CFG,RSVD
-MCP(8/14)CFG,RSVD
LA-
LA-
LA-
G891P
G891P
G891P
1
13 10
13 10
13 10
of
of
of
0.3
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
2Monday, February 25, 2019
5
+1.0V_VCCST
1 2
RC218 1K_0402 _1%
1 2
RC219 49.9_0402_1%@
1 2
CC1481 100P_0 201_50 V8JRF@
+1.0V_VCCSTG
1 2
RC558 1K_0402 _1%
D D
+3.3V_RUN
1 2
RC82 10K_0201_5%@
12
RC567 1 0K_040 2_5%
H_THERMTRIP#_R
H_CATERR#
PROCHOT#
TOUCH_SCREEN_PD#
TOUCHPAD_INTR#
PECI_EC[58]
PROCHOT#[58,84,88]
H_THERMTRIP#[23,24,59]
PROCHOT#
TOUCH_SCREEN_DET#[38]
@
TOUCHPAD_INTR#[58,63]
4
1 2
RC84 4 99_040 2_1%
1 2
RC559
0_0402_ 5%
XDP_OBS0_R[79]
XDP_OBS1_R[79]
12
12
6
7
RC10
RC10
49.9_0402_1%
CB34
CC35
BP27
BW25
AA4
AR1
Y4
BJ1
U1
U2
U3
U4
CE9
CN3
L5
N5
UC1D
CATERR#
PECI
PROCHOT#
THRMTRIP#
BPM#_0
BPM#_1
BPM#_2
BPM#_3
GPP_E3/ CPU_GP0
GPP_E7/ CPU_GP1
GPP_B3/ CPU_GP2
GPP_B4/ CPU_GP3
PROC_POP IRCOMP
PCH_OPIRCOMP
RSVD
RSVD
WHL-U42_BGA1528
H_CATERR#
PROCHOT#_R
H_THERMTRIP#_R
XDP_OBS0_R
XDP_OBS1_R
MEM_INTERLE AVED
TOUCH_SCREEN_PD#
TOUCHPAD_INTR#
CPU_POPIRCOMP
PCH_POPIRCOMP
EDRAM_OPIO_RCOMP
EOPI
O_RCOMP
12
12
9
8
RC10
RC10
49.9_0402_1%
@
@
49.9_0402_1%
49.9_0402_1%
need check
RC10
8,RC109
This is applicable only for CFL U43e. These pins are
RSVD in WHL and hence can be left unconnected
3
CPU_XDP_TCLK
T6
PROC_TCK
CPU MISC
70
71
4 of
PROC_TDI
JTAG
PROC_TDO
PROC_TMS
PROC_TRST#
PCH_TCK
PCH_TDI
PCH_TDO
PCH_TMS
PCH_TRST#
PCH_JTAGX
PROC_PREQ#
PROC_PRDY#
20
U6
Y5
T5
AB6
W6
U5
W5
P5
Y6
P6
W2
W1
CPU_XDP_TDI
CPU_XDP_TDO
CPU_XDP_TMS
CPU_XDP_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
CPU_XDP_TRST#
RC87 1 K_0201 _5%@
CPU_XDP_PREQ#
CPU_XDP_PRDY#
1 2
CPU_XDP_TCLK [79]
CPU_XDP_TDI [79]
CPU_XDP_TDO [79]
CPU_XDP_TMS [79]
1 2
RC86 51_0402_5%@
PCH_JTAG_TCK [79]
PCH_JTAG_TDI [79]
PCH_JTAG_TDO [79]
PCH_JTAG_TMS [79]
CPU_XDP_TRST# [79]
XDP_JTAGX [79]
+1.0V_VCCSTG
CPU_XDP_PREQ# [79]
CPU_XDP_PRDY# [79]
2
TOUCH_SCREE N_PD#
TOUCH_SCREEN_PD# don't move to RPC,
TOUCH_SCREE N_PD
TOUCH_SCREE N_PD#
L2N7002 DW1T1G_ SC88-6
Rese
rve for Panel side TS PH voltage problem
1 2
RC566 0_0402_ 5%@
+3.3V_RUN
12
RC104
10K_040 2_5%
6
2
QC4A
@
1
MEM_
INTERLEAVE D
TOUCH_SCREEN_PD#_R
@
+3.3
1
34
@
L2N7002 DW1T1G_ SC88-6
5
V_ALW_PCH
@
10K_040 2_5%
RC84
1 2
TOUCH_SCREEN_PD#_R [38]
QC4B
3
C C
B B
PCH_
JTAG_TDO
0.1U_0402_25V6
@ESD@
12
CC30
3
A A
PCH_
JTAG_TDI
0.1U_0402_25V6
@ESD@
12
CC30
4
ESD request,Place near CPU side.
XDP_
JTAGX
0.1U_0402_25V6
@ESD@
12
CC30
5
CPU_
XDP_TRST#
0.1U_0402_25V6
@ESD@
12
CC30
8
ESD request,Place near UC8 side.
1 2
10K_040 2_5%
RC84
4
DIMM TYPE
HIGH Interleave
Non-InterleaveLOW
DELL
CONFIDENTIAL/PROPRIETARY
Titl
Titl
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
Titl
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
e
e
e
onday, February 25, 2019
onday, February 25, 2019
onday, February 25, 2019
Comp
Comp
Comp
al Electronics, Inc.
al Electronics, Inc.
al Electronics, Inc.
P15-
P15-
P15-
MCP(9/14)XDP
MCP(9/14)XDP
MCP(9/14)XDP
LA-G8
LA-G8
LA-G8
1
91P
91P
91P
0.3
0.3
14 102M
14 102M
14 102M
0.3
of
of
of
5
PSC(Primary side cap) : Place as close to the package as possible
BSC(Backside cap) : Place on secondary side, underneath the package
Component placement order:
Package edge > 0402 caps > 0805 caps > Bulk caps >Power source
+VCC_CORE: 0.55~1.5V, 29A
D D
+VCC_EDRAM: 1V, 2.5A
+V1.8S_EDRAM: 1.8V, 50mA - REMOVE
+VCC_EOPIO: 0.8~1V, 2A - REMOVE
UC1
O
K12
K14
K15
K17
K18
K20
L25
M24
M26
P24
P26
R24
R25
R26
W25
V24
C C
Y25
Y24
RESERVED SIGNALS
RSV
D48
RSV
D49
RSV
D50
RSV
D51
RSV
D52
RSV
D53
RSV
D54
RSV
D55
RSV
D56
RSV
D57
RSV
D58
RSV
D59
RSV
D60
RSV
D61
RSV
D62
RSV
D63
RSV
D64
RSV
D65
WHL-U42_BGA1528
15
of 20
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
RSV
4
AA24
D38
AA26
D39
AB25
D40
AC24
D41
AC25
D42
AC26
D43
AD24
D44
AD26
D45
D46
D47
VCC
V25
T25
EOPIO_SENSE
VSS
EOPIO_SENSE
1
@
T36
8
PAD~D
1
@
T36
9
PAD~D
@
T37
1
PAD~D
@
T37
2
PAD~D
@
T37
3
PAD~D
@
T37
4
PAD~D
1
1
1
1
+VC
+VC
+VC
+VC
3
C_CORE_G0
C_CORE_G1
C_CORE_G2
C_CORE_G3
+VCC_CORE
2
UC1L
AN9
VCCCORE5
AN10
VCCCORE1
AN24
VCCCORE2
AN26
VCCCORE3
AN27
VCCCORE4
AP2
VCCCORE6
AP9
VCCCORE9
AP24
VCCCORE7
AP26
VCCCORE8
AR5
VCCCORE13
AR6
VCCCORE14
AR7
VCCCORE15
AR8
VCCCORE16
AR10
VCCCORE10
AR25
VCCCORE11
AR27
VCCCORE12
AT9
VCCCORE19
AT24
VCC
AT26
VCC
AU5
VCC
AU6
VCC
AU7
VCC
AU8
VCC
AU9
VCC
AU24
VCC
AU25
VCC
AU26
VCC
AU27
VCC
AV2
VCC
AV5
VCC
AV7
VCC
AV10
VCC
AV27
VCC
AW5
VCC
AW6
VCC
AW7
VCC
AW8
VCC
AW9
VCC
AW10
VCC
BB9
RSV
BC24
RSV
AY9
RSV
BB24
RSV
WHL-U42_BGA1528
VCCOPC,VCCOPC_1P8,VCCEOPIO for SKYLAKE-U 2+3e
(w/ on package cache)
CORE17
CORE18
CORE24
CORE25
CORE26
CORE27
CORE28
CORE20
CORE21
CORE22
CORE23
CORE30
CORE32
CORE33
CORE29
CORE31
CORE39
CORE40
CORE41
CORE42
CORE43
CORE34
D3
D4
D1
D2
CPU POWER 1 OF 4
12
of 20
VCCCORE35
VCCCORE36
VCCCORE37
VCCCORE38
VCCCORE44
VCCCORE45
VCCCORE48
VCCCORE49
VCCCORE50
VCCCORE46
VCCCORE47
VCCCORE51
VCCCORE52
VCCCORE56
VCCCORE57
VCCCORE58
VCCCORE59
VCC
CORE53
VCC
CORE54
VCC
CORE55
VCC
CORE63
VCC
CORE64
VCC
CORE60
VCC
CORE61
VCC
CORE62
VCC
CORE69
VCC
CORE65
VCC
CORE66
VCC
CORE67
VCC
CORE68
VCC
CORE70
VCC
CORE73
VCC
CORE71
VCC
CORE72
VCC
CORE74
VCC
VSS
VID
VID
VCC
_SENSE
_SENSE
ALERT#
VID
SCK
SOUT
RSV
STG1
1
+VCC_CORE
AW24
AW25
AW26
AW27
AY24
AY26
BA5
BA7
BA8
BA25
BA27
BB2
BB26
BC5
BC6
BC7
BC9
BC10
BC26
BC27
BD5
BD8
BD10
BD25
BD27
BE9
BE24
BE25
BE26
BE27
BF2
BF9
BF24
BF26
BG27
AN6
AN5
AA3
AA1
AA2
Y3
D5
BG3
H_C
PU_SVIDALRT#
VID
SCLK_R
VID
SOUT_R
+1.
0V_VCCSTG_R
VCC
VSS
SENSE_R
SENSE_R
RC1
53
@
0_0402_5%
@
RC4
30
1 2
1 2
0_0402_5%
@
RC4
29
12
+VC
C_CORE
0_0603_5%
12
12
50
RC1
100_0402_1%
51
RC1
100_0402_1%
1V@
Close CPU
+1.
0V_VCCSTG
0.05A
VCC
_SENSE_IA [88]
VSS
_SENSE_IA [88]
+1.
SVID ALERT
B B
VID
ALERT_N[88]
SVID DATA
VID
SOUT[88]
SVID CLK
VID
A A
SCLK[88]
0V_VCCST
+1.
0V_VCCST
+1.
0V_VCCST
56_0402_1%
12
RC1
54
100_0402_1%
12
RC1
56
@
RC1
43_0402_5%
@
12
RC1
58
@
RC1
CAD Note: Place the PU resistors close to CPU
RC154 close to CPU 1000 - 1500mils
H_C
PU_SVIDALRT#
12
RC1
55220_0402_5%
CAD Note: Place the PU resistors close to CPU
RC156close to CPU 1000 - 1500mils
57
59
0_0402_5%
VID
VID
SOUT_R
SCLK_R
12
CAD Note: Place the PU resistors close to CPU
RC158close to CPU 1000 - 1500mils
0_0402_5%
12
DELL CONFIDENTIAL/PROPRIETARY
Com
Com
Com
pal Electronics, Inc.
pal Electronics, Inc.
Tit
Tit
Title
le
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Monday, February 25, 2019
Monday, February 25, 2019
Monday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronics, Inc.
P16
P16
P16
-MCP(10/14)PWR-VCC CORE
-MCP(10/14)PWR-VCC CORE
-MCP(10/14)PWR-VCC CORE
LA-
LA-
LA-
G891P
G891P
G891P
15
15
15
1
0.3
0.3
0.3
of
of
of
10
10
10
2
2
2
5
4
3
2
1
THE BALLOUT ONLY FOR WHL ES2 CPU
D D
+VCCGT: 0.55~1.5V, 54A
+VCCGTX : 0.55~1.5V, 7A
+VCC_GT+VCC_GT+VCC_CORE
1.5V@54A
UC1M
A5
A6
A8
A11
A12
A14
A15
A17
A18
A20
AA9
AB2
AB8
AB9
AB10
AC8
AD9
AE8
AE9
AE10
C C
B B
AF10
AJ10
AL10
AF2
AF8
AG8
AG9
AH9
AK2
AK9
AM8
C11
C12
C14
C15
C17
C18
C20
D11
D12
D14
AJ8
AL8
AL9
V2
Y10
Y8
B3
B4
B6
B8
B11
B14
B17
B20
C2
C3
C6
C7
C8
D4
D7
CPU POWER 2 OF 4
VCCG
T8
VCCG
T9
VCCG
T10
VCCG
T1
VCCG
T2
VCCG
T3
VCCG
T4
VCCG
T5
VCCG
T6
VCCG
T7
ES1/
ES2
VCCG
T11/VCCCORE75
VCCG
T13/VCCCORE76
VCCG
T14/VCCCORE77
VCCG
T15/VCCCORE78
VCCG
T12/VCCCORE79
VCCG
T16/VCCCORE80
VCCG
T17/VCCCORE81
VCCG
T19/VCCCORE82
VCCG
T20/VCCCORE83
VCCG
T18/VCCCORE84
VCCG
T22/VCCCORE85
VCCG
T23/VCCCORE86
VCCG
T21/VCCCORE87
VCCG
T24/VCCCORE88
VCCG
T25/VCCCORE89
VCCG
T26/VCCCORE90
VCCG
T28/VCCCORE91
VCCG
T27/VCCCORE92
VCCG
T29//VCCCORE93
VCCG
T30/VCCCORE94
VCCG
T32/VCCCORE95
VCCG
T33/VCCCORE96
VCCG
T31/VCCCORE97
VCCG
T34/VCCCORE98
VCCG
T115/VCCCORE99
VCCG
T119/VCCCORE100
VCCG
T120/VCCCORE101
VCCG
T39
VCCG
T40
VCCG
T41
VCCG
T42
VCCG
T35
VCCG
T36
VCCG
T37
VCCG
T38
VCCG
T49
VCCG
T51
VCCG
T52
VCCG
T53
VCCG
T54
VCCG
T43
VCCG
T44
VCCG
T45
VCCG
T46
VCCG
T47
VCCG
T48
VCCG
T50
VCCG
T62
VCCG
T63
VCCG
T55
VCCG
T56
VCCG
T57
WHL-U42_BGA1528
D15
VCCG
T58
D17
VCCG
T59
D18
VCCG
T60
D20
VCCG
T61
E4
VCCG
T64
F5
VCCG
T69
F6
VCCG
T70
F7
VCCG
T71
F8
VCCG
T72
F11
VCCG
T65
F14
VCCG
T66
F17
VCCG
T67
F20
VCCG
T68
G11
VCCG
T73
G12
VCCG
T74
G14
VCCG
T75
G15
VCCG
T76
G17
VCCG
T77
G18
VCCG
T78
G20
VCCG
T79
H5
VCCG
T87
H6
VCCG
T88
H7
VCCG
T89
H8
VCCG
T90
H11
VCCG
T80
H12
VCCG
T81
H14
VCCG
T82
H15
VCCG
T83
H17
VCCG
T84
H18
VCCG
T85
H20
VCCG
T86
J7
VCCG
T95
J8
VCCG
T96
J11
VCCG
T91
J14
VCCG
T92
J17
VCCG
T93
J20
VCCG
T94
K2
VCCG
T98
K11
VCCG
T97
L7
VCCG
T100
L8
VCCG
T101
L10
VCCG
T99
M9
VCCG
T102
N7
VCCG
T104
N8
VCCG
T105
N9
VCCG
T106
N10
VCCG
T103
P2
VCCG
T107
P8
VCCG
T108
R9
VCCG
T109
T8
VCCG
T111
T9
VCCG
T112
T10
VCCG
T110
U8
VCCG
T114
U10
VCCG
T113
V9
VCCG
T116
W8
VCCG
T117
W9
VCCG
T118
VCCG
T_SENSE
T_SENSE
E3
D2
VCCG
VSSG
13 o
f 20
VSSG
T_SENSE_R
T_SENSE_R
1 2
1 2
RC63
@
2
@
RC63
1 0_0402_5%
0_0402_5%
+VCC
_GT
12
0
Clos
e CPU
RC16
100_0402_1%
VCC_
SENSE_GT [88]
VSS_
SENSE_GT [88]
12
1
RC16
100_0402_1%
A A
DELL CONFIDENTIAL/PROPRIETARY
Comp
Comp
Comp
al Electronics, Inc.
al Electronics, Inc.
Titl
Titl
Title
e
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
e
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
P17-
P17-
P17-
MCP(11/14)PWR-VCCGT
MCP(11/14)PWR-VCCGT
MCP(11/14)PWR-VCCGT
LA-G
LA-G
LA-G
891P
891P
891P
1
0.3
0.3
16 102M
16 102M
16 102M
0.3
of
of
of
5
4
3
2
1
+1.2V_DDR: 1.2V, 3.5A
+1.0V_VCCST: 1V, 120mA; VCCPLL: 1V, 120mA
+1.0V_VCCSTG: 1V, 40mA
+VCCPLL_OC: 1.2V, 260mA
+1.0VS_VCCIO: 0.85~0.95V, 3.1A
+VCC_SA: 1.15V, 5.1A
D D
+VCCPLL_OC source
CZ1
02 1U_0201_6.3V 6M
VCC
STG_EN
SIO
_SLP_S3#[11,17,59,79]
SIO
_SLP_S0#[9 ,11,66,79,87]
C C
Follow 575962 RVP V0P7,VCCSFR_OC enable gated by VCCSTG_EN
1 2
@
RZ1
20 0_0402_5%
1 2
RZ1
418 0_0402_5%@
1 2
RZ1
419 0_0402_5%@
+1.2V_MEM +VCCPLL_OC
1 2
@
RZ1
19 0_040 2_5%
UZ27
1
VIN
PLL_EN
2
7
3
4
VIN
VIN
VBI
ON
EM5
1
2
thermal
AS
201V DFN3X3
12
+5V
_ALW
VCC
6
VOU
T
5
GND
+1.
0V_VCCSTG
2
CZ3
0.1U_0201_1 0V6K
1
+1.0V_VCCSTG source
+1.
0V_PRIM
+3.
3V_RUN
RZ1
422
1 2
CPU
_C10_GATE#[6,58,87]
RUN
B B
1 2
420
0_0402_5%
MC74VHC1G0 8DFT2G SC70
1 2
RZ3
20 0_040 2_5%@
RZ1
@
_ON[17,58,59,78,87]
100K_0402_5%
UZ3
5
12
CZ1
05 1U_02 01_6.3V6M
+5V
_ALW
+3.
3V_ALW
5
1
P
B
O
2
A
G
3
VCC
4
UZ19
1
VIN
2
VIN
7
VIN
3
VBI
4
ON
EM5
201V DFN3X3
4.4mohm/6A
TR=12.5us@Vin=1.05V
STG_EN
1
2
thermal
AS
Follow 575962 RVP V0P7,VCCSTG RAIL design
12
PJP
2
PAD-OPEN1x1m
+1.
0V_VCCSTG_C
6
VOU
T
5
GND
+1.0V_VCCST source
+1.
0V_PRIM
VCC
ST_EN
UZ21
1
VIN
1
2
VIN
2
7
VIN
thermal
3
VBI
AS
4
ON
EM5
201V DFN3X3
4.4mohm/6A
TR=12.5us@Vin=1.05V
+1.
0V_VCCST_C
6
VOU
T
5
GND
12
CZ1
00 1U_0201_6.3V 6M
+5V
_ALW
RZ1
RZ1
@
RZ1
_ON[17,58,59,78,87]
1 2
416 0_0402_5%@
1 2
417 0_0402_5%@
423 0_ 0402_5%
1 2
SIO
_SLP_S3#[11,17,59,79]
SIO
_SLP_S4#[11,79,86,87]
RUN
A A
Follow 575962 V0p7 PDG page519,Premium design Vccst gated by RUN_ON
PJP
1
PAD-OPEN1x1m
1 2
CZ1
01 0.1U_ 0201_10V6K
12
03
RZ1
1 2
51 0_060 3_5%@
+1.
pop option with UZ19
1 2
CZ1
06
0.1U_0201_1 0V6K
+1.
0V_VCCST
RF Request
0V_VCCST
+1.2V_MEM
RF@
1200P_0402_50V7K
1
CC14
78
2
place as close as CPU
RF@
680P_0402_50V7K
1
CC14
79
2
+1.0V_VCCST
PSC
1V@0.12A
0814 Confirmed with
Intel can change to 0201
CC28
U_0201_6.3V6M
1
PDG P.479 0402
+1.
0V_VCCSTG
close to package
+1.
0V_VCCSTG
1
2
1V@0.04A
1
0814 Confirmed with
PDG P.479 0402
+1.
2V_MEM
Primary Side
Secondary Side
Intel can change to 0201
CC29
2
U_0201_6.3V6M
1
+VC
CPLL_OC
PSC
1.2V@0.26A
close to package
1
1
2
CC32
RF@
2.2P_0402_50V8C
1
2
0U_0402_6.3V6M
1
1
2
0U_0402_6.3V6M
1
PDG P.479 0402
CC34
0U_0402_6.3V6M
1
CC46
0U_0402_6.3V6M
1
0
CC43
2
1U_0201_6.3V6M
0814 Confirmed with
Intel can change to 0201
1
1
CC35
CC36
2
2
0U_0402_6.3V6M
1
1
1
5
55
CC19
CC14
2
2
1U_0201_6.3V6M
2
RF Request
WHL
_U PDG rev0.8 P.479
VDDQ:
Primary Side cap
1x 22uF 0603 + 6x 10uF 0402
Secondary Side cap
4x 1uF 0402/0201 + 3x 10uF 0402
PDG P.479 22U 0603,10U 0402
1
1
CC32
CC33
2
2
2U_0603_6.3V6M
2
PDG P.479 1U 0402/0201,10U 0402
1
1
54
CC45
CC14
2
2
10U_0402_6.3V6M
Follow RVP rev1.0
1
80
CC14
2
PDG P.479 0805
Reserve
0.1U_0201_10V6K
1
1
CC37
2
2
0U_0402_6.3V6M
0U_0402_6.3V6M
1
1
1
1
56
CC14
2
2
1U_0201_6.3V6M
1U_0201_6.3V6M
+1.2V_MEM
AD36
1.2V@3.5A
AH32
AH36
AM36
AN32
AW32
AY36
BE32
BH36
R32
Y36
BC28
BP11
BP2
BG1
BG2
BL27
BM26
BR11
BT11
+1.
0V_VCCST_R
1V@0.12A
close to package
1
1
CC31
CC96
2
2
U_0201_6.3V6M
2U_0603_6.3V6M
1
2
PDG P.479 0402
PSC
Reserve for BSOD issue
0814 Confirmed with
Intel can change to 0201
CC38
0U_0402_6.3V6M
1
57
CC14
1U_0201_6.3V6M
UC1N
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDD
Q10
VDD
Q11
RSV
D1
VCC
ST1
VCC
ST2
VCC
STG1
VCC
STG2
VCC
PLL_OC1
VCC
PLL_OC2
VCC
PLL1
VCC
PLL2
WHL-U42 _BGA1528
@
0_0603_5%
1 2
1
PDG P.479 0201
62
CC14
2
0.1U_0201_10V6K
CPU POWER 3 OF 4
14
of 20
+1.
0V_VCCST
RC8
64
VCC
VSS
VCC
VSS
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
IO_SENSE
IO_SENSE
SA_SENSE
SA_SENSE
+VC
IO11
IO12
IO13
IO14
IO15
IO16
SA2
SA1
SA3
SA5
SA6
SA4
SA9
SA7
SA8
SA13
SA14
SA10
SA11
SA12
SA15
SA16
C_SA
+1.
0VS_VCCIO
+1.0VS_VCCIO
AK24
0.95V@3.1A
AK26
AL24
AL25
AL26
AL27
AM25
AM27
BH24
BH25
BH26
BH27
BJ24
BJ26
BP16
BP18
BG8
BG10
BH9
BJ8
BJ9
BJ10
BK8
BK25
BK27
BL8
BL9
BL10
BL24
BL26
BM24
BN25
BP28
BP29
BE7
BG7
RC1
Primary Side
VCC
IO_SENSE
VSS
IO_SENSE
@
RC4
25 0_040 2_5%
1 2
RC4
26
@
1 2
1 2
66 100_0402_1 %
PDG P.479 0201
1
1
58
CC14
2
2
1U_0201_6.3V6M
1.15V@5.1A
59
CC14
Primary or Secondary Side
1
1
4
5
CC23
CC23
2
2
10U_0402_6.3V6M
PDG P.479 0402
Placeholder
1
1
CC39
CC40
2
2
@
@
0U_0402_6.3V6M
1
0_0402_5%
1
2
1U_0201_6.3V6M
1
2
10U_0402_6.3V6M
1
2
0U_0402_6.3V6M
1
+VC
C_SA
12
4
RC16
100_0402_1%
WHL
VCCIO:
Primary Side cap
4x 1uF 0201
Primary or Secondary Side
6x 10uF 0402
Placeholder Only
1
4x 10uF 0402
61
60
CC14
CC14
2
1U_0201_6.3V6M
1U_0201_6.3V6M
PDG P.479 0402
1
1
6
7
CC51
CC23
CC23
2
2
0U_0402_6.3V6M
1
10U_0402_6.3V6M
10U_0402_6.3V6M
1
CC41
CC42
2
@
@
0U_0402_6.3V6M
0U_0402_6.3V6M
1
1
+1.
0VS_VCCIO
Clo
se CPU
12
RC1
63
100_0402_1 %
VCC
IO_SENSE [87]
VSS
IO_SENSE [87]
12
@
RC1
65
0_0201_5%
VSS
_SENSE_SA [88]
VCC
_SENSE_SA [88]
_U PDG rev0.8 P.479
1
CC52
2
0U_0402_6.3V6M
1
DEL
L CONFIDENTIAL/PROPRIETARY
Tit
Tit
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
Tit
Size Docum ent Numbe r Rev
Size Docum ent Numbe r Rev
Size Docum ent Numbe r Rev
Date: Sheet
Date: Sheet
Date: Sheet
Com
Com
Com
pal Electronics, Inc.
pal Electronics, Inc.
le
le
le
pal Electronics, Inc.
P18
P18
P18
-MCP(12/14)PWR-VCCIO,MEM
-MCP(12/14)PWR-VCCIO,MEM
-MCP(12/14)PWR-VCCIO,MEM
LA-G
LA-G
LA-G
1
891P
891P
891P
17 10
17 10
17 10
of
of
of
0.3
0.3
0.3
2Mond ay, February 25, 2 019
2Mond ay, February 25, 2 019
2Mond ay, February 25, 2 019
5
4
3
2
1
close UC1 <100mil
1 2
LC1 LQM18PN2R2NC0L_2P~D
RC422
@
0.01_0603_1%
D D
+1.0
C C
1 2
0809 BSOD
Pop LC2 INDUCTOR,CC100 22U_0603
V_PRIM
depop RC175
Add CC103 22U_0603
1 2
LC2 LQ
RC17
5
@
0.01_0603_1%
1 2
+1.0
V_PRIM
M18PN2R2NC0L_2P~D
PJP3
1 2
P
AD-OPEN1x3m
1
2
+1.0V_MPHYGT source
close UC1 <120mil
0809 BSOD
Pop LC3 INDUCTOR,CC102 22U_0603
+1.0
V_MPHYGT
depop RC173
Add CC104 22U_0603
1 2
LC3 LQ
@
0.01_0603_1%
1 2
B B
A A
Support DS3
No Support DS3
'V' mean POP, 'X' mean DE-POP
RC17
M18PN2R2NC0L_2P~D
3
+3.3
V_ALW_DSW
22U_0603_6.3V6M
1
2
RC43
V V V
X X
5
1
1
2
2
CC104
22U_0603_6.3V6M
RC44
RC21
@
22U_0603_6.3V6M
@
CC27
CC280
1
9
2
9
RC440RE536RC215RC441 RC442
X
V V V
+1.0V_APLL+1.0V_PRIM
1
1
CC85
CC86
2
2
@
@
2U_0603_6.3V6M
22U_0603_6.3V6M
2
+1.0
V_CLK
1
1
1
0
CC83
2
2
2
CC10
CC103
22U_0603_6.3V6M
+1.0
CC102
CC10
PDG0.8 P.505 0402
0801 Confirmed with
Intel can change to 0201*2
1 2
0 0_0402_5%@NDS3@
1 2
4 0_0402_5%@
RC43
U_0201_6.3V6M
1
22U_0603_6.3V6M
CC10
3/CC83/CC70 close to CP5
PDG0.8 P.505 0402
0801 Confirmed with
Intel can change to 0201*2
V_MPHYGT
+1.0
V_AMPHYPLL
1
1
CC80
CC69
2
2
U_0201_6.3V6M
U_0201_6.3V6M
1
22U_0603_6.3V6M
1
4/CC80/CC69 close to BV2
+3.3
+3.3
1 2
9 0_0402_5%DS3@
X
X
CC70
U_0201_6.3V6M
1
PDG
rev0.8 P.509
Place an 22uF edge cap not more than
12 mm away measuring from package edge.
+3.3
V_ALW_PCH
LP23
V_ALW_DSW_R
12
DS3@
X
L2
N7002WT1G_SC-70-3
QC6
V_ALW_PCH
LC4
BL
M18EG221TN1D_2P~D
1 2
PDG P.505 no decoup.
12
@RF@
0_0402_5%
RC84
5
1
CC77
RF@
2
.2P_0201_25V
2
QC7DS3@
01ALT1G_SOT23-3
123
D
S
G
DS3@
49.9K_0402_1%
0.1U_0402_25V6K
RC43
12
@
CC34
3
0
13
D
2
G
S
+1.0
CC89 close to CP17
PCH Internal VRM
close to BT24
PDG P.505 0402
V_MPHYGT
1.05V@2.878A
2
1
+3.3
V_ALW
DS3@
499K_0402_1%
12
RC43
2
100K_0402_5%
1 2
4
+1.8V_PRIM
1.8V@0.696A
1
PDG P.505 0402
CC98
2
U_0201_6.3V6M
0814 Confirmed with
Intel can change to 0201
1
0814 Confirmed with
Intel can change to 0201
PDG P.504 0402 reserve
+VCC
PDSW_1P05
1.05V@0.024A
1
0814 Confirmed with
Intel can change to 0201
CC65
2
U_0201_6.3V6M
1
1
PDG P.504 0603
CC71
2
PDG P.505 no decoup.
RF@
2
.2P_0201_25V
RC43
1
VCCD
2U_0603_6.3V6M
2
VCCH
CC95
+1.0
V_MPHYGT
SW_EN_GPIO [11]
+1.0
+3.3
V_AMPHYPLL
+1.0
+1.0
V_ALW_DSW
DA
+3.3
V_ALW_PCH
+1.0
V_PRIM
+1.0
V_APLL
+1.0V_PRIM
1.05V@1.625A
CC67/CC68 close to BP20
1
CC68
2
+3.3
V_ALW_PCH
3.3V@0.199A
+1.0
V_PRIM_CORE
1.05V@4.26A
CC66
close to BV18
1
CC66
@
2
U_0201_6.3V6M
1
+1.0
V_APLL
1.05V@0.102A
1.05V@0.152A
1.05V@0.102A
1.05V@0.129A
3.3V@0.001A
3.3V@0.006A
V_PRIM
3.3V@0.002A
V_PRIM
0814 Confirmed with
Intel can change to 0201
1
CC67
2
U_0201_6.3V6M
U_0201_6.3V6M
1
1
BP20
BW16
BW18
BW19
BY16
CA14
CC15
CD15
CD16
CP17
CB22
CB23
CC22
CC23
CD22
CD23
CP29
BU15
BU22
BV15
BV16
BV18
BV19
BV20
BV22
BW20
BW22
CA12
CA16
CA18
CA19
CA20
CB12
CB14
CB15
BT24
BU14
BV12
BW12
BW14
BY12
BY14
BR15
CC12
BR24
BT20
BV23
BT18
BT19
BU18
BU19
BT22
BP22
BV14
BV2
3
UC1P
VCCPRIM_1P05_1
VCCPRIM_1P05_9
VCCPRIM_1P05_10
VCCPRIM_1P05_11
VCCPRIM_1P05_12
VCCPRIM_1P05_14
VCCPRIM_1P8_1
VCCPRIM_1P8_4
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCD
VCCA
VCCP
VCCP
VCCP
VCCP
VCCP
VCCA
VCCA
VCCD
VCCD
VCCH
VCCS
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
WHL-U42_BGA1528
CPU POWER 4 OF 4
RIM_1P8_5
RIM_1P8_8
RIM_3P3_4
RIM_3P3_5
RIM_3P3_6
RIM_3P3_7
RIM_3P3_8
RIM_3P3_9
RIM_3P3_10
RIM_CORE1
RIM_CORE2
RIM_CORE3
RIM_CORE4
RIM_CORE5
RIM_CORE6
RIM_CORE7
RIM_CORE8
RIM_CORE9
RIM_CORE10
RIM_CORE11
RIM_CORE12
RIM_CORE13
RIM_CORE14
RIM_CORE15
RIM_CORE16
RIM_CORE17
RIM_CORE18
SW_1P05
PLL_1P05_4
RIM_MPHY_1P05_1
RIM_MPHY_1P05_3
RIM_MPHY_1P05_4
RIM_MPHY_1P05_5
RIM_MPHY_1P05_6
MPHYPLL_1P05
PLL_1P05_2
USB_1P05
SW_3P3_1
DA
PI
RIM_1P05_4
RIM_1P05_5
RIM_1P05_7
RIM_1P05_8
RIM_1P05_6
RIM_1P05_2
RIM_MPHY_1P05_2
16 o
f 20
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
VCCPRIM_3P3_3
VCCPRIM_1P05_13
VCCP
VCCA
VCCA
VCCA
VCCA
VCCA
VCCD
VCCD
VCCD
VCCD
VCCD
VCCD
VCCA
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
GPP_
GPP_
VCCRTC
DCPRTC
RIM_1P05_3
PLL_1P05_3
_BCLK_1P05
PLL_1P05_1
_SRC_1P05
_XTAL_1P05
PHY_1P24_2
PHY_1P24_4
PHY_1P24_1
PHY_1P24_3
PHY_1P24_5
SW_3P3_2
_19P2_1P05
RIM_1P8_2
RIM_1P8_3
RIM_1P8_6
RIM_1P8_7
RIM_1P8_9
RIM_3P3_2
RIM_3P3_1
B0/CORE_VID0
B1/CORE_VID1
CB16
BR23
BY20
BP24
BR20
BT12
BP14
BR14
BU12
CP5
BY24
CA24
BY23
CA23
CP25
BT23
BR12
CC18
CC19
CD18
CD19
CP23
BW23
BP23
CB36
CB35
1.05V@0.009A
1.05V@0.102A
1.05V@0.034A
1.05V@0.034A
1.24V@0.61A
PCH Internal VRM
1.05V@0.027A
3.3V@0.199A
PDG P.505 0402 reserve
3.3V@0.199A
3.3V@0.199A
2
+3.3V_ALW_PCH
1
CC75
2
@
+1.0V_PRIM
PDG P.505 0201 reserve
+1.0
V_PRIM
+1.0
V_APLL
+1.0
V_PRIM
+1.0
V_APLL
+1.0
V_PRIM
+1.0
V_CLK
+VCC
+1.0
V_PRIM
+3.3
+3.3
CORE
_VID0 [87]
CORE
_VID1 [87]
0814 Confirmed with
Intel can change to 0201
CC74/CC75close to CP29
U_0201_6.3V6M
1
DCPRTC
PCH
close to BP24
LDOSRAM_1P24
1.8V@0.696A
V_ALW_PCH
V_ALW_PCH
DELL
CONFIDENTIAL/PROPRIETARY
+RTC_CELL_PCH
3.0V@0.002A
PDG P.505 0402
1
CC76
2
@
U_0201_6.3V6M
1
Internal VRM
CAD NOTE: CAPs
+VCC
DPHY_1P24
1
CC72
2
1
CC84
2
.7U_0402_6.3V6M
4
CC72/CC73 close to CP29
1
CC73
2
PDG P.505 0402
0814 Confirmed with
Intel can change to 0201
U_0201_6.3V6M
1
.1U_0201_6.3V6K
0
PCH Internal VRM
close to CP25
PDG P.505 0402
+3.3
V_ALW_DSW
3.3V@0.199A
1
63
+1.8
V_PRIM
1
64
2
CC1464 close to CP23
CC14
PDG P.505 0402 reserve
@
1U_0201_6.3V6M
0814 Confirmed with
Intel can change to 0201
Comp
Comp
Titl
Titl
Titl
e
e
e
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Comp
P19-
P19-
P19-
onday, February 25, 2019
onday, February 25, 2019
onday, February 25, 2019
CC1463 close to BR24
CC14
2
PDG P.505 0402 reserve
@
0814 Confirmed with
1U_0201_6.3V6M
Intel can change to 0201
al Electronics, Inc.
al Electronics, Inc.
al Electronics, Inc.
MCP(13/14)PCH PWR
MCP(13/14)PCH PWR
MCP(13/14)PCH PWR
LA-G
LA-G
LA-G
891P
891P
891P
18 102M
18 102M
1
18 102M
0.3
0.3
0.3
of
of
of
5
4
3
2
1
D D
C C
B B
CR34
BT5
BY5
CP35
CM37
CK37
AW1
CM1
BD6
AY4
B34
E35
A4
AE24
AE26
AF25
AG24
AG26
AH24
AH25
B2
B36
C36
C37
CN1
CN2
CN37
CP2
D1
A32
F33
A3
BJ7
CJ36
A36
BK10
CJ4
AB27
BK2
CK1
AB3
BK28
AB30
BK3
CK4
AB33
BK33
CK7
AB36
BK4
CL2
AB4
BK7
CM13
AB7
BL25
CM17
AC10
BL28
CM21
AC27
BL29
CM25
AC30
BL30
CM29
BL31
CM31
AD33
BL32
CM33
AD35
WHL-U42_BGA1528
UC1R
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GND 1 OF 3
_10
_11
_12
_13
_14
_15
_16
_17
_18
_19
_20
_21
_22
_23
_24
_25
_26
_27
_28
_29
_30
_31
_32
_33
_34
_35
_36
_37
_38
_39
_40
_41
_42
_43
_44
_45
_46
_47
_48
_49
_50
_51
_52
_53
_54
_55
_56
_57
_58
_59
_60
_61
_62
_63
_64
_65
_66
_67
_68
_69
_70
_71
_72
17
of 20
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
_100
_101
_102
_103
_104
_105
_106
_107
_108
_109
_110
_111
_112
_113
_114
_115
_116
_117
_118
_119
_120
_121
_122
_123
_124
_125
_126
_127
_128
_129
_130
_131
_132
_133
_134
_135
_136
_137
_138
_139
_140
_141
_142
_143
_144
BL7
AE25
BM33
CM5
AE27
BM35
CM9
AE30
BM36
CN13
_82
AE7
_83
BM9
_84
CN17
_85
AF27
_86
BN30
_87
CN21
_88
AF3
_89
BN7
_90
CN25
_91
AF30
_92
CN29
_93
AF33
_94
BP15
_95
AF36
_96
AF4
_97
CN5
_98
AF7
_99
BP25
CN9
AG10
BP3
CP1
BP32
CP11
AH27
BP33
CP13
AH28
BP4
CP15
AH29
BP7
CP19
AH30
CP21
AH31
BR19
CP27
AH33
BR25
AH35
CP37
AJ25
BT15
AJ28
BT16
CP9
AJ7
CR2
AK3
CR36
AK33
D21
AK36
BT25
D25
AK4
BT28
AL28
BT33
D5
AL29
BT35
D6
AL32
BT36
D8
AL7
D9
AM10
BU11
E23
AM28
E27
AM33
BU23
E29
AM35
BU24
E31
BU25
E33
AN25
BU7
E9
AN28
BV11
F12
AN29
F15
AN30
F18
AN31
BV3
F2
AN7
BV31
F21
AN8
BV33
F24
BV4
F3
AP3
BW11
F4
AP33
BW15
G21
AP36
G27
AP4
G33
AR28
G35
G36
AT33
BW24
G9
AT35
H21
AT36
BW7
H27
AT4
BY11
AU10
BY15
H9
AU28
BY22
J12
AU29
J15
WHL-U42_BGA1528
UC1S
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS
_154
VSS
_155
VSS
_156
VSS
_157
VSS
_158
VSS
_159
VSS
_160
VSS
_161
VSS
_162
VSS
_163
VSS
_164
VSS
_165
VSS
_166
VSS
_167
VSS
_168
VSS
_169
VSS
_170
VSS
_171
VSS
_172
VSS
_173
VSS
_174
VSS
_175
VSS
_176
VSS
_177
VSS
_178
VSS
_179
VSS
_180
VSS
_181
VSS
_182
VSS
_183
VSS
_184
VSS
_185
VSS
_186
VSS
_187
VSS
_188
VSS
_189
VSS
_190
VSS
_191
VSS
_192
VSS
_193
VSS
_194
VSS
_195
VSS
_196
VSS
_197
VSS
_198
VSS
_199
VSS
_200
VSS
_201
VSS
_202
VSS
_203
VSS
_204
VSS
_205
VSS
_206
VSS
_207
VSS
_208
VSS
_209
VSS
_210
VSS
_211
VSS
_212
VSS
_213
VSS
_214
VSS
_215
VSS
_216
GND 2 OF 3
18
BY25
VSS_217
J18
VSS_218
AU32
VSS_219
BY28
VSS_220
J21
VSS_221
AV25
VSS_222
BY33
VSS_223
J24
VSS_224
AV28
VSS_225
BY35
VSS
_226
J33
VSS
_227
AV3
VSS
_228
BY36
VSS
_229
J36
VSS
_230
AV33
VSS
_231
J6
VSS
_232
AV36
VSS
_233
C1
VSS
_234
K21
VSS
_235
AV4
VSS
_236
C21
VSS
_237
K22
VSS
_238
AV6
VSS
_239
C25
VSS
_240
K24
VSS
_241
AV8
VSS
_242
C29
VSS
_243
K25
VSS
_244
AW28
VSS
_245
C33
VSS
_246
K27
VSS
_247
AW29
VSS
_248
C4
VSS
_249
K28
VSS
_250
AW3
VSS
_251
C9
VSS
_252
K29
VSS
_253
AW30
VSS
_254
CA11
VSS
_255
K3
VSS
_256
AW31
VSS
_257
CA15
VSS
_258
K30
VSS
_259
AY33
VSS
_260
CA22
VSS
_261
K31
VSS
_262
AY35
VSS
_263
K32
VSS
_264
B12
VSS
_265
K4
VSS
_266
B15
VSS
_267
CA25
VSS
_268
K9
VSS
_269
B18
VSS
_270
CB11
VSS
_271
L27
VSS
_272
B21
VSS
_273
L33
VSS
_274
B23
VSS
_275
L35
VSS
_276
B25
VSS
_277
CB18
VSS
_278
L36
VSS
_279
B27
VSS
_280
CB19
VSS
_281
L6
VSS
_282
B29
VSS
_283
CB2
VSS
_284
N25
VSS
_285
B31
VSS
_286
CB20
VSS
_287
N27
VSS
_288
CB25
VSS
_289
of 20
N6
VSS_290
B37
VSS_291
CB3
VSS_292
P10
VSS_293
B5
VSS_294
CB33
VSS_295
P3
VSS_296
B7
VSS_297
CB4
VSS
P33
VSS
B9
VSS
CB7
VSS
P36
VSS
BA10
VSS
CC11
VSS
P4
VSS
BA28
VSS
P7
VSS
BA3
VSS
CC20
VSS
R27
VSS
BB3
VSS
CC25
VSS
R28
VSS
BB33
VSS
CC28
VSS
R29
VSS
BB36
VSS
CC31
VSS
R30
VSS
BB4
VSS
CC7
VSS
R31
VSS
BC25
VSS
CD11
VSS
T27
VSS
CD12
VSS
T30
VSS
BC29
VSS
CD14
VSS
T33
VSS
T35
VSS
BC32
VSS
CD24
VSS
T36
VSS
CD25
VSS
T7
VSS
BC8
VSS
CE33
VSS
U26
VSS
BD28
VSS
CE35
VSS
U7
VSS
BD33
VSS
CE36
VSS
V26
VSS
BD35
VSS
CE7
VSS
V27
VSS
BD36
VSS
CF11
VSS
V3
VSS
BE10
VSS
CF14
VSS
V30
VSS
BE28
VSS
CF19
VSS
V33
VSS
BE29
VSS
CF2
VSS
V36
VSS
BE3
VSS
WHL-U42_BGA1528
UC1T
_298
_299
_300
_301
_302
_303
_304
_305
_306
_307
_308
_309
_310
_311
_312
_313
_314
_315
_316
_317
_318
_319
_320
_321
_322
_323
_324
_325
_326
_327
_328
_329
_330
_331
_332
_333
_334
_335
_336
_337
_338
_339
_340
_341
_342
_343
_344
_345
_346
_347
_348
_349
_350
_351
_352
_353
_354
_355
_356
_357
_358
_359
_360
_361
GND 3 OF 3
19
CF23
VSS_362
V4
VSS_363
BE30
VSS_364
CF28
VSS_365
W10
VSS_366
BE31
VSS_367
CF3
VSS_368
W27
VSS_369
CF4
VSS
_370
W30
VSS
_371
BF3
VSS
_372
CG33
VSS
_373
W7
VSS
_374
BF33
VSS
_375
CG7
VSS
_376
BF36
VSS
_377
Y26
VSS
_378
BF4
VSS
_379
CH31
VSS
_380
Y27
VSS
_381
BG25
VSS
_382
Y30
VSS
_383
BG28
VSS
_384
CJ11
VSS
_385
Y33
VSS
_386
CJ14
VSS
_387
Y35
VSS
_388
BH28
VSS
_389
CJ19
VSS
_390
Y7
VSS
_391
BH29
VSS
_392
CJ23
VSS
_393
BH32
VSS
_394
CJ28
VSS
_395
BH33
VSS
_396
CJ33
VSS
_397
BH35
VSS
_398
CJ35
VSS
_399
BP19
VSS
_400
BR16
VSS
_401
BY18
VSS
_402
BY19
VSS
_403
CC16
VSS
_404
BU16
VSS
_405
CC14
VSS
_406
BR22
VSS
_407
BU20
VSS
_408
CD20
VSS
_409
BT14
VSS
_410
BP12
VSS
_411
CB24
VSS
_412
CC24
VSS
_413
J5
VSS
_414
U24
VSS
_415
BD7
VSS
_416
AR4
VSS
_417
AU4
VSS
_418
AW4
VSS
_419
BA6
VSS
_420
BC4
VSS
_421
BE4
VSS
_422
BE8
VSS
_423
BA4
VSS
_424
BD4
VSS
_425
BG4
VSS
_426
CJ2
VSS
_427
CJ3
VSS
_428
AM5
VSS
_429
CM4
VSS
_430
AC5
VSS
_431
AG5
VSS
_432
CR6
VSS
_433
of 20
A A
DEL
L CONFIDENTIAL/PROPRIETARY
Com
Com
Com
pal Electronics, Inc.
pal Electronics, Inc.
Tit
Tit
Tit
le
le
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronics, Inc.
P20
P20
P20
-MCP(14/14)VSS
-MCP(14/14)VSS
-MCP(14/14)VSS
LA-
LA-
LA-
G891P
G891P
G891P
1
19 10
19 10
19 10
of
of
of
0.3
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
2Monday, February 25, 2019
5
D D
C C
4
3
2
1
Reserve
B B
A A
DELL
CONFIDENTIAL/PROPRIETARY
Comp
Comp
al Electronics, Inc.
Titl
Titl
Titl
e
e
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
e
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
SOC o
SOC o
r PCH / FCH
r PCH / FCH
LA-G
LA-G
891P
891P
0.3
20 102M
20 102M
of
of
of
1
0.3
5
D D
C C
4
3
2
1
Reserve
B B
A A
DEL
L CONFIDENTIAL/PROPRIETARY
Com
Com
pal Electronics, Inc.
Tit
Tit
Tit
le
le
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronics, Inc.
SOC
SOC
or PCH / FCH
or PCH / FCH
LA-
LA-
G891P
G891P
21 10
21 10
of
of
of
1
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
5
D D
C C
4
3
2
1
Reserve
B B
A A
DELL
CONFIDENTIAL/PROPRIETARY
Comp
Comp
al Electronics, Inc.
Titl
Titl
Titl
e
e
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
e
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
SOC o
SOC o
r PCH / FCH
r PCH / FCH
LA-G
LA-G
891P
891P
0.3
22 102M
22 102M
of
of
of
1
0.3
5
DDR_A_DQS#[0..7][7]
DDR_A_D[0..63][7]
DDR_A_DQS[0..7][7]
DDR_A_MA[0..16][7]
Layout Note:
Place near JDIMM1
D D
C C
B B
A A
+1.2V_MEM
+1.
0814 Confirmed with
Intel can change to 0201
+0.
6V_DDR_VTT
10P_0402_50V8J
12
*
10
10
U_0603_10V6M
U_0603_10V6M
CD2
CD1
12
12
12
2V_MEM
1U_
1
U_0201_6.3V6M
0201_6.3V6M
12
12
12
CD9
CD10
Layout Note:
Place near
JDIMM1.258
Refence WHL RVP rev0.7
Refence WHL RVP rev0.7
Refence WHL RVP rev0.7Refence WHL RVP rev0.7
1
0U_0603_10V6M
@
@
CD63
12
12
CD76RF
DIMM Select
SA01SA1
0
DIMM1
DIMM2
1
0
DIMM3
1
DIMM4
10U_0603_10V6M
10
10
U_0603_10V6M
U_0603_10V6M
CD4
CD3
12
12
1
1U_0201_6.3V6M
1
U_0201_6.3V6M
U_0201_6.3V6M
12
12
CD12
CD11
1
1
1U_0201_6.3V6M
U_0201_6.3V6M
0U_0603_10V6M
CD23
CD22
CD24
1
1
2
2
0814 Confirmed with
Intel can change to 0201
SA2
0
0
0
0
0
0
1
Refence WHL RVP rev0.7
Refence WHL RVP rev0.7
Refence WHL RVP rev0.7Refence WHL RVP rev0.7
10
10U_0603_10V6M
U_0603_10V6M
CD5
CD7
CD6
12
12
12
1
1U_0201_6.3V6M
U_0201_6.3V6M
12
12
12
CD15
CD13
CD14
WHL_U PDG rev0.8 P.92
VTT:
Place on VTT plane close to SODIMM
2x 10uF 0603(1 cap stuffed, 1 placeholder)
4x 1uF 0402
VDDSPD:
Place close to DIMM
2x 0.1uF 0402
2x 2.2uF 0402
1U_0201_6.3V6M
1
U_0201_6.3V6M
CD69
CD70
1
1
2
2
+3.
+3.
3V_RUN
3V_RUN
12
RD4
@
0
_0402_5%
12
0
_0402_5%
@
RD5
WHL
VDDQ:
4 near each side of the DIMM
3
10
30U_D3_2.5VY_R6M
connector close to VDD pins
U_0603_10V6M
16x 10uF 0603
@
12
16x 1uF 0402
CD17
CD8
+
Placeholder
1x 330uF 7343
VPP:
DIMM pin side, 1 per DIMM
2x 10uF 0603
2x 1uF 0402
+2.
1
U_0201_6.3V6M
CD16
0814 Confirmed with
Intel can change to 0201
+3.
3V_RUN
12
@
RD1
0_0603_5%
2
.2U_0402_6.3V6M
1
CD27
2
+3.
3V_RUN
12
12
12
@
0
_0402_5%
0
_0402_5%
@
RD8
RD6
@
0
_0402_5%
DIM
M1_SA0
DIM
M1_SA1
DIM
M1_SA2
12
0
_0402_5%
@
RD9
RD7
_U PDG rev0.8 P.92
5V_MEM
1
1
U_0201_6.3V6M
U_0201_6.3V6M
1
1
1
CD18
CD19
2
2
2
0
+3.
3V_RUN_DIMM 1
0
1
5P_0402_50V8J
.1U_0201_10V6K
RF@
1
CD28
12
CD73
2
+DD
R_VREF_A_ CA
4
3
2
1
For DDR4
Link LOTES_ADDR0206-P001A02 done 0410
CONN@
DDR_A_CLK 1[7]
DDR_A_CKE 1[7]
DDR
AD~D @
AD~D @
DDR
DDR
DDR
_A_ALERT#[7]
DDR_A_CLK 0
DDR_A_CLK #0
DDR_A_CLK 1
DDR_A_CLK #1
DDR_A_CKE 0
DDR_A_CKE1
DDR
_A_CS#0[ 7]
_A_CS#1[ 7]
_A_ODT0[7]
_A_ODT1[7]
_A_BG0[7]
_A_BG1[7]
_A_ACT#[7]
_A_PARITY[7]
12
_A_CS#0
DDR
_A_CS#1
1
T50P
1
T51P
DDR
_A_ODT0
DDR
_A_ODT1
DDR
_A_BG0
DDR
_A_BG1
DDR
_A_BA0
_A_BA0[7]
DDR
_A_BA1
_A_BA1[7]
DDR
_A_MA0
DDR
_A_MA1
DDR
_A_MA2
DDR
_A_MA3
DDR
_A_MA4
DDR
_A_MA5
DDR
_A_MA6
DDR
_A_MA7
DDR
_A_MA8
DDR
_A_MA9
DDR
_A_MA10
DDR
_A_MA11
DDR
_A_MA12
DDR
_A_MA13
DDR
_A_MA14
DDR
_A_MA15
DDR
_A_MA16
DDR
_A_ACT#
DDR
_A_PARITY
DDR
_A_ALERT#
JDI
MM1_EVEN T#
DDR
_DRAMRST#_R
DIM
M1_SA2
DIM
M1_SA1
DIM
M1_SA0
+1.
2V_MEM
4
70_0402_1%
RD11
DDR
_DRAMRST#
DDR_A_CLK 0[7]
DDR_A_CLK #0[7]
DDR_A_CLK #1[7]
DDR_A_CKE 0[7]
DDR
DDR
DDR
DDR
DDR
DDR
_XDP_W AN_SMBD AT[8,24,67,79]
_XDP_W AN_SMBC LK[8,24,67,79]
0_0402_5%
+1.
DDR
DDR
DDR
2V_MEM
1
1
0U_0603_10V6M
0U_0603_10V6M
1
CD21
CD20
2
1
CD2
9
@
0.1U_0402_2 5V6
0
.1U_0201_6.3V6K
1
1
CD25
2
2
DDR
_DRAMRST#_R[24]
2
2
.2U_0402_6.3V6M
CD26
1 2
@
RD1
2
137
139
138
140
109
110
1
49
1
57
162
165
155
161
1
15
1
13
1
50
1
45
14
13
13
13
12
12
12
12
12
12
146
1
20
1
19
1
58
151
156
152
114
143
116
134
108
2
54
2
53
1
66
2
60
2
56
92
91
101
105
88
87
100
104
97
95
12
33
54
75
178
199
220
241
96
DDR
_DRAMRST# [7]
JDIMM1A
REVERSE
CK0(T)
CK0#(C)
CK1(T)
CK1#(C)
CKE0
CKE1
S0#
S1#
S2#
/C0
S3#
/C1
ODT
0
ODT
1
BG0
BG1
BA0
BA1
4
A0
3
A1
2
A2
1
A3
8
A4
6
A5
7
A6
2
A7
5
A8
1
A9
A10
_AP
A11
A12
A13
A14
_WE#
A15
_CAS#
A16
_RAS#
ACT
#
PAR
ITY
ALE
RT#
EVE
NT#
RES
ET#
SDA
SCL
SA2
SA1
SA0
CB0
_NC
CB1
_NC
CB2
_NC
CB3
_NC
CB4
_NC
CB5
_NC
CB6
_NC
CB7
_NC
DQS
8(T)
DQS
8#(C)
DM0
#/DBI0#
DM1
#/DBI1#
DM2
#/DBI2#
DM3
#/DBI3#
DM4
#/DBI4#
DM5
#/DBI5#
DM6
#/DBI6#
DM7
#/DBI7#
DM8
#/DBI8#
LOTES_ADDR02 06-P001A
8
DQ0
7
DQ1
20
DQ2
21
DQ3
4
DQ4
3
DQ5
16
DQ6
1
7
DQ7
13
DQS
0(T)
11
DQS
0#(C)
2
8
DQ8
2
9
DQ9
41
DQ1
0
42
DQ1
1
24
DQ1
2
25
DQ1
3
38
DQ1
4
37
DQ1
5
34
DQS
1(T)
32
DQS
1#(C)
50
DQ1
6
49
DQ1
7
62
DQ1
8
63
DQ1
9
46
DQ2
0
45
DQ2
1
58
DQ2
2
59
DQ2
3
55
DQS
2(T)
53
DQS
2#(C)
70
DQ2
4
71
DQ2
5
83
DQ2
6
84
DQ2
7
66
DQ2
8
67
DQ2
9
79
DQ3
0
80
DQ3
1
76
DQS
3(T)
74
DQS
3#(C)
174
DQ3
2
173
DQ3
3
187
DQ3
4
186
DQ3
5
170
DQ3
6
169
DQ3
7
183
DQ3
8
182
DQ3
9
179
DQS
4(T)
177
DQS
4#(C)
195
DQ4
0
194
DQ4
1
207
DQ4
2
208
DQ4
3
191
DQ4
4
190
DQ4
5
203
DQ4
6
204
DQ4
7
200
DQS
5(T)
198
DQS
5#(C)
216
DQ4
8
215
DQ4
9
228
DQ5
0
229
DQ5
1
211
DQ5
2
212
DQ5
3
224
DQ5
4
225
DQ5
5
221
DQS
6(T)
219
DQS
6#(C)
237
DQ5
6
236
DQ5
7
249
DQ5
8
250
DQ5
9
232
DQ6
0
233
DQ6
1
245
DQ6
2
246
DQ6
3
242
DQS
7(T)
240
DQS
7#(C)
DDR
_VTT_CTRL[7]
DDR_A_D2
DDR_A_D5
DDR_A_D1
DDR_A_D7
DDR_A_D0
DDR_A_D4
DDR_A_D6
DDR_A_D3
DDR
_A_DQS0
DDR
_A_DQS#0
DDR
_A_D8
DDR
_A_D13
DDR
_A_D15
DDR
_A_D11
DDR
_A_D12
DDR
_A_D10
DDR
_A_D9
DDR
_A_D14
DDR
_A_DQS1
DDR
_A_DQS#1
DDR
_A_D32
DDR
_A_D36
DDR
_A_D34
DDR
_A_D35
DDR
_A_D37
DDR
_A_D33
DDR
_A_D39
DDR
_A_D38
DDR
_A_DQS4
DDR
_A_DQS#4
DDR
_A_D41
DDR
_A_D45
DDR
_A_D46
DDR
_A_D43
DDR
_A_D40
DDR
_A_D44
DDR
_A_D42
DDR
_A_D47
DDR
_A_DQS5
DDR
_A_DQS#5
DDR
_A_D29
DDR
_A_D25
DDR
_A_D30
DDR
_A_D26
DDR
_A_D28
DDR
_A_D24
DDR
_A_D27
DDR
_A_D31
DDR
_A_DQS3
DDR
_A_DQS#3
DDR
_A_D23
DDR
_A_D16
DDR
_A_D22
DDR
_A_D20
DDR
_A_D18
DDR
_A_D19
DDR
_A_D17
DDR
_A_D21
DDR
_A_DQS2
DDR
_A_DQS#2
DDR
_A_D52
DDR
_A_D49
DDR
_A_D55
DDR
_A_D51
DDR
_A_D48
DDR
_A_D53
DDR
_A_D54
DDR
_A_D50
DDR
_A_DQS6
DDR
_A_DQS#6
DDR
_A_D57
DDR
_A_D60
DDR
_A_D62
DDR
_A_D59
DDR
_A_D61
DDR
_A_D56
DDR
_A_D63
DDR
_A_D58
DDR
_A_DQS7
DDR
_A_DQS#7
1
NC
2
A
3
GND
7
4AUP1G07GW _TSSOP5
+DD
R_VREF_A_ CA
+1.
UD1
2V_MEM
5
Y
4
1 2
CD3
2@ 0.1U_0201_10V6 K
1 2
RD1
9 100K_0402_5 %
VCC
+3.
3V_RUN_DIMM 1
+DD
R_VREF_A_ CA
+1.2V_ME M
+DD
0.6
V_DDR_VTT_ON [86]
+3.
3V_RUN
CONN@
JDIMM1B
111
VDD1
112
VDD2
117
VDD3
118
VDD4
123
VDD
124
VDD
129
VDD
130
VDD
135
VDD
136
VDD
255
VDD
164
VRE
1
VSS
2
VSS
5
VSS
6
VSS
9
VSS
10
VSS
14
VSS
15
VSS
18
VSS
19
VSS
22
VSS
23
VSS
26
VSS
27
VSS
30
VSS
31
VSS
35
VSS
36
VSS
39
VSS
40
VSS
43
VSS
44
VSS
47
VSS
48
VSS
51
VSS
52
VSS
56
VSS
57
VSS
60
VSS
61
VSS
64
VSS
65
VSS
68
VSS
69
VSS
72
VSS
73
VSS
77
VSS
78
VSS
81
VSS
82
VSS
85
VSS
86
VSS
89
VSS
90
VSS
93
VSS
94
VSS
98
VSS
262
GND
264
NPT
LOTES_ADDR02 06-P001A
JDI
MM1_EVEN T#
R_VREF_A_CA
5
6
7
8
9
10
SPD
FCA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
1
H2
REVERSE
RD1
4 1K_0 402_5%@
6/8 Change to SA00007WE00 DII
VDD11
VDD12
VDD13
VDD14
VDD
VDD
VDD
VDD
VDD
VPP
VPP
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GND
NPT
1 2
+1.
2V_MEM
12
12
VTT
1
K_0402_1%
1
K_0402_1%
+1.2V_ME M
141
142
147
148
153
15
154
16
159
17
160
18
163
19
2
58
257
1
259
2
99
48
102
49
103
50
106
51
107
52
167
53
168
54
171
55
172
56
175
57
176
58
180
59
181
60
184
61
185
62
188
63
189
64
192
65
193
66
196
67
197
68
201
69
202
70
205
71
206
72
209
73
210
74
213
75
214
76
217
77
218
78
222
79
223
80
226
81
227
82
230
83
231
84
234
85
235
86
238
87
239
88
243
89
244
90
247
91
248
92
251
93
252
94
261
2
263
H1
RD15
1 2
RD1
7 2_0402_1%
RD16
12
2
12
4.9_0402_1%
RD18
+0.
6V_DDR_VTT
+2.
5V_MEM
H_T
HERMTRIP# [14,24,59]
+DD
R_VREF_CA
0
.022U_0402_16V7K
CD31
DEL
L CONFIDENTIAL/PROPRIETARY
Tit
Tit
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
Tit
Size Docum ent Numbe r Rev
Size Docum ent Numbe r Rev
Size Docum ent Numbe r Rev
Date: Sheet
Date: Sheet
Date: Sheet
Com
Com
Com
pal Electronics, Inc.
pal Electronics, Inc.
le
le
le
pal Electronics, Inc.
DDR
DDR
DDR
4 DIMMA
4 DIMMA
4 DIMMA
LA-G
LA-G
LA-G
891P
891P
891P
23 10
23 10
1
23 10
0.3
0.3
0.3
2Mond ay, February 25, 2 019
2Mond ay, February 25, 2 019
2Mond ay, February 25, 2 019
of
of
of
5
DDR_B_DQS#[0..7][7]
DDR_B_D[0..63][7]
DDR_B_DQS[0..7][7]
DDR_B_MA[0..16][7]
4
3
2
1
For DDR4
Link LOTES_ADDR0206-P001A02 done 0410
CONN@
Layout Note:
D D
+1.2V_MEM
10
10
10
U_0603_10V6M
CD33
12
12
+1.2
V_MEM
1U_
0201_6.3V6M
12
12
CD41
0814 Confirmed with
Intel can change to 0201
C C
+0.6
V_DDR_VTT
10
1
RF@
0P_0402_50V8J
U_0603_10V6M
@
CD66
12
12
CD77
B B
10
U_0603_10V6M
U_0603_10V6M
U_0603_10V6M
CD34
CD35
CD36
12
12
1U_
1U_
1U_
0201_6.3V6M
0201_6.3V6M
0201_6.3V6M
12
12
CD42
CD43
CD44
Layout Note:
Place near
JDIMM2.258
Refence WHL RVP rev0.7
Refence WHL RVP rev0.7
Refence WHL RVP rev0.7Refence WHL RVP rev0.7
1U_
10
U_0603_10V6M
0201_6.3V6M
CD55
CD54
1
12
2
0814 Confirmed with
Intel can change to 0201
1
2
DIMM Select
SA2
SA01SA1
DIMM1
DIMM2
DIMM3
*
DIMM4
0
0
0
0
0
1
0
0
0
1
1
Place near JDIMM2
Refence WHL RVP rev0.7
Refence WHL RVP rev0.7
Refence WHL RVP rev0.7Refence WHL RVP rev0.7
10
10U_0603_10V6M
U_0603_10V6M
CD37
CD38
12
12
12
1U_
1U_0201_6.3V6M
0201_6.3V6M
12
12
12
CD45
CD46
1U_
1U_0201_6.3V6M
0201_6.3V6M
CD56
CD71
1
1
2
2
+3.3
+3.3
V_RUN
12
RD20
@
0
_0402_5%
12
0
_0402_5%
@
RD21
WHL_
U PDG rev0.8 P.92
VDDQ:
10
U_0603_10V6M
CD39
12
1U_
0201_6.3V6M
12
CD47
WHL_U PDG rev0.8 P.92
VTT:
Place on VTT plane close to SODIMM
2x 10uF 0603(1 cap stuffed, 1 placeholder)
4x 1uF 0402
VDDSPD:
Place close to DIMM
2x 0.1uF 0402
2x 2.2uF 0402
1U_0201_6.3V6M
CD72
V_RUN
12
0
_0402_5%
@
RD22
12
RD23
@
0
_0402_5%
4 near each side of the DIMM
10
33
U_0603_10V6M
0U_D3_2.5VY_R6M
connector close to VDD pins
@
16x 10uF 0603(2 DIMMS TOTAL)
12
CD40
CD49
+
16x 1uF 0402(2 DIMMS TOTAL)
Placeholder
1x 330uF 7343
VPP:
DIMM pin side, 1 per DIMM
2x 10uF 0603
2x 1uF 0402
+2.5
V_MEM
1U_
0201_6.3V6M
1
CD48
2
0814 Confirmed with
Intel can change to 0201
+3.3
V_RUN
12
12
0
1U_
0201_6.3V6M
CD50
RD24
@
0
_0402_5%
DIMM
DIMM
DIMM
_0402_5%
RD25
@
2_SA0
2_SA1
2_SA2
10
15
RF@
RF@
P_0402_50V8J
P_0402_50V8J
12
12
CD74
CD75
+3.3
V_RUN
12
12
1
2
@
0
_0603_5%
+DDR
1U_
0201_6.3V6M
CD51
RD26
2.
2U_0402_6.3V6M
CD59
_VREF_B_C A
1
2
+3.3
1
2
10
U_0603_10V6M
1
CD52
2
V_RUN_DIMM2
0.
1U_0201_10V6K
CD60
0.
1U_0201_6.3V6K
CD57
1
2
10
U_0603_10V6M
CD53
DDR_
DRAMRST#_R[23]
0
2.
2U_0402_6.3V6M
CD58
1
2
CD61
.1U_0402_25 V6
1
@
2
DDR_
DDR_
DDR_B_CLK 0[7]
DDR_B_CLK #0[7]
DDR_B_CLK 1[7]
DDR_B_CLK #1[7]
DDR_B_CKE 0[7]
DDR_B_CKE 1[7]
DDR_B_CS# 0[7]
DDR_B_CS# 1[7]
DDR_B_ODT0[7]
DDR_B_ODT1[7]
DDR_B_BG0[7]
DDR_
DDR_
DDR_
DDR_
DDR_
DDR_
XDP_W AN_SMBDA T[8,23,67,79]
XDP_W AN_SMBCL K[8,23,67,79 ]
DDR_B_CLK 0
DDR_B_CLK #0
DDR_B_CLK 1
DDR_B_CLK #1
DDR_B_CKE 0
DDR_B_CKE 1
DDR_B_CS# 0
DDR_B_CS# 1
T54PAD~D @
T55PAD~D @
DDR_B_ODT0
DDR_B_ODT1
DDR_B_BG0
DDR_B_BG1
B_BG1[7]
DDR_
B_BA0[7]
B_BA1[7]
B_PARITY[7]
B_ALERT#[7]
B_BA0
DDR_
B_BA1
DDR_
B_MA0
DDR_
B_MA1
DDR_
B_MA2
DDR_
B_MA3
DDR_
B_MA4
DDR_
B_MA5
DDR_
B_MA6
DDR_
B_MA7
DDR_
B_MA8
DDR_
B_MA9
DDR_
B_MA10
DDR_
B_MA11
DDR_
B_MA12
DDR_
B_MA13
DDR_
B_MA14
DDR_
B_MA15
DDR_
B_MA16
DDR_
B_ACT#
B_ACT#[7]
DDR_
B_PARITY
DDR_
B_ALERT#
JDIM
M2_EVENT#
DDR_
DRAMRST#_R
DIMM
2_SA2
DIMM
2_SA1
DIMM
2_SA0
+1.2
V_MEM
JDIM
M2_EVENT#
1 2
RD27 1
JDIMM2A
REVERSE
137
CK0(T)
139
CK0#(C)
138
CK1(T)
140
CK1#(C)
109
CKE0
110
CKE1
149
S0#
157
S1#
162
1
S2#/C0
1
165
S3#/C1
155
ODT0
161
ODT1
115
BG0
11
3
BG1
15
0
BA0
14
5
BA1
144
A0
133
A1
132
A2
131
A3
128
A4
126
A5
127
A6
122
A7
125
A8
121
A9
146
A10_
AP
12
0
A11
11
9
A12
15
8
A13
151
A14_
WE#
156
A15_
CAS#
152
A16_
RAS#
1
14
ACT#
143
PARI
TY
116
ALER
T#
134
EVEN
T#
108
RESE
T#
25
4
SDA
25
3
SCL
16
6
SA2
26
0
SA1
25
6
SA0
92
CB0_
NC
91
CB1_
NC
101
CB2_
NC
105
CB3_
NC
88
CB4_
NC
87
CB5_
NC
100
CB6_
NC
104
CB7_
NC
97
DQS8
(T)
95
DQS8
#(C)
12
DM0#
/DBI0#
33
DM1#
/DBI1#
54
DM2#
/DBI2#
75
DM3#
/DBI3#
178
DM4#
/DBI4#
199
DM5#
/DBI5#
220
DM6#
/DBI6#
241
DM7#
/DBI7#
96
DM8#
/DBI8#
LOTES_ADDR02 06-P001A
K_0402_5%@
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS0(T)
DQS0#(C)
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS1
(T)
DQS1
#(C)
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS2
(T)
DQS2
#(C)
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS3
(T)
DQS3
#(C)
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS4
(T)
DQS4
#(C)
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS5
(T)
DQS5
#(C)
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS6
(T)
DQS6
#(C)
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS7
(T)
DQS7
#(C)
H_TH
ERMTRIP# [14,23,59]
8
7
20
21
4
3
16
17
13
11
28
29
41
42
24
25
3
8
3
7
34
32
5
0
4
9
6
2
6
3
4
6
4
5
5
8
5
9
55
53
7
0
7
1
8
3
8
4
6
6
6
7
7
9
8
0
76
74
1
74
1
73
1
87
1
86
1
70
1
69
1
83
1
82
179
177
1
95
1
94
2
07
2
08
1
91
1
90
2
03
2
04
200
198
2
16
2
15
2
28
2
29
2
11
2
12
2
24
2
25
221
219
2
37
2
36
2
49
2
50
2
32
2
33
2
45
2
46
242
240
DDR_B_D1
DDR_B_D4
DDR_B_D6
DDR_B_D7
DDR_B_D0
DDR_B_D5
DDR_B_D3
DDR_B_D2
DDR_B_DQS0
DDR_B_DQS# 0
DDR_B_D13
DDR_B_D11
DDR_B_D14
DDR_B_D10
DDR_B_D9
DDR_B_D8
DDR_B_D12
DDR_
B_D15
DDR_
B_DQS1
DDR_
B_DQS#1
DDR_
B_D32
DDR_
B_D37
DDR_
B_D38
DDR_
B_D35
DDR_
B_D36
DDR_
B_D33
DDR_
B_D34
DDR_
B_D39
DDR_
B_DQS4
DDR_
B_DQS#4
DDR_
B_D41
DDR_
B_D47
DDR_
B_D43
DDR_
B_D42
DDR_
B_D45
DDR_
B_D46
DDR_
B_D40
DDR_
B_D44
DDR_
B_DQS5
DDR_
B_DQS#5
DDR_
B_D17
DDR_
B_D20
DDR_
B_D22
DDR_
B_D19
DDR_
B_D16
DDR_
B_D21
DDR_
B_D23
DDR_
B_D18
DDR_
B_DQS2
DDR_
B_DQS#2
DDR_
B_D25
DDR_
B_D29
DDR_
B_D27
DDR_
B_D30
DDR_
B_D24
DDR_
B_D28
DDR_
B_D26
DDR_
B_D31
DDR_
B_DQS3
DDR_
B_DQS#3
DDR_
B_D48
DDR_
B_D49
DDR_
B_D51
DDR_
B_D54
DDR_
B_D52
DDR_
B_D53
DDR_
B_D50
DDR_
B_D55
DDR_
B_DQS6
DDR_
B_DQS#6
DDR_
B_D57
DDR_
B_D60
DDR_
B_D59
DDR_
B_D63
DDR_
B_D61
DDR_
B_D56
DDR_
B_D58
DDR_
B_D62
DDR_
B_DQS7
DDR_
B_DQS#7
+DDR_VREF _B_CA
+3.3V_RUN_ DIMM2
+DDR_VREF _B_CA
+DDR
_VREF_B_CA
CONN@
JDIMM2B
REVERSE
111
VDD1
112
VDD2
117
VDD3
118
VDD4
123
VDD5
124
VDD6
129
VDD7
130
VDD8
135
VDD9
136
VDD10
255
VDDSPD
164
VREF
CA
1
VSS1
2
VSS2
5
VSS3
6
VSS4
9
VSS5
1
0
VSS6
1
4
VSS7
1
5
VSS8
1
8
VSS9
19
VSS1
0
22
VSS1
1
23
VSS1
2
26
VSS1
3
27
VSS1
4
30
VSS1
5
31
VSS1
6
35
VSS1
7
36
VSS1
8
39
VSS1
9
40
VSS2
0
43
VSS2
1
44
VSS2
2
47
VSS2
3
48
VSS2
4
51
VSS2
5
52
VSS2
6
56
VSS2
7
57
VSS2
8
60
VSS2
9
61
VSS3
0
64
VSS3
1
65
VSS3
2
68
VSS3
3
69
VSS3
4
72
VSS3
5
73
VSS3
6
77
VSS3
7
78
VSS3
8
81
VSS3
9
82
VSS4
0
85
VSS4
1
86
VSS4
2
89
VSS4
3
90
VSS4
4
93
VSS4
5
94
VSS4
6
98
VSS4
7
2
62
GND1
264
NPTH
2
LOTES_ADDR02 06-P001A
+1.2
V_MEM
1K
12
_0402_1%
RD28
RD30 2
1K
_0402_1%
12
RD29
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VTT
VPP1
VPP2
VSS4
VSS4
VSS5
VSS5
VSS5
VSS5
VSS5
VSS5
VSS5
VSS5
VSS5
VSS5
VSS6
VSS6
VSS6
VSS6
VSS6
VSS6
VSS6
VSS6
VSS6
VSS6
VSS7
VSS7
VSS7
VSS7
VSS7
VSS7
VSS7
VSS7
VSS7
VSS7
VSS8
VSS8
VSS8
VSS8
VSS8
VSS8
VSS8
VSS8
VSS8
VSS8
VSS9
VSS9
VSS9
VSS9
VSS9
GND2
NPTH
1 2
+1.2V_ME M+1.2V_ME M
141
142
147
148
153
154
159
160
163
258
2
57
2
59
99
8
102
9
103
0
106
1
107
2
167
3
168
4
171
5
172
6
175
7
176
8
180
9
181
0
184
1
185
2
188
3
189
4
192
5
193
6
196
7
197
8
201
9
202
0
205
1
206
2
209
3
210
4
213
5
214
6
217
7
218
8
222
9
223
0
226
1
227
2
230
3
231
4
234
5
235
6
238
7
239
8
243
9
244
0
247
1
248
2
251
3
252
4
2
61
263
1
_0402_1%
12
24
.9_0402_1%
12
RD31
+0.6V_DDR_ VTT
+2.5
V_MEM
+DDR
_VREF_B_DQ
0.
022U_0402_16V7K
CD62
A A
DELL
CONFIDENTIAL/PROPRIETARY
Comp
Comp
Comp
al Electronics, Inc.
al Electronics, Inc.
Titl
Titl
Title
e
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
5
4
3
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
e
Size Docum ent Numbe r Rev
Size Docum ent Numbe r Rev
Size Docum ent Numbe r Rev
onday, February 2 5, 2019
onday, February 2 5, 2019
onday, February 2 5, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
DDR4
DDR4
DDR4
DIMMB
DIMMB
DIMMB
LA-G8
LA-G8
LA-G8
91P
91P
91P
1
0.3
0.3
24 102M
24 102M
24 102M
0.3
of
of
of
5
D D
C C
4
3
2
1
Reserve
B B
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
DEL
L CONFIDENTIAL/PROPRIETARY
Com
Com
pal Electronics, Inc.
Tit
Tit
Tit
le
le
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronics, Inc.
DDR
DDR
LA-
LA-
G891P
G891P
25 10
25 10
1
of
of
of
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
5
D D
C C
4
3
2
1
Reserve
B B
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
DELL
CONFIDENTIAL/PROPRIETARY
Comp
Comp
al Electronics, Inc.
Titl
Titl
Titl
e
e
e
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
DDR
DDR
LA-G
LA-G
891P
891P
26 102M
26 102M
1
of
of
of
0.3
0.3
5
D D
C C
4
3
2
1
Reserve
B B
A A
DEL
L CONFIDENTIAL/PROPRIETARY
Com
Com
pal Electronics, Inc.
Tit
Tit
Tit
le
le
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronics, Inc.
DGPU
DGPU
LA-
LA-
G891P
G891P
1
27 10
27 10
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
of
of
of
5
D D
C C
4
3
2
1
Reserve
B B
A A
DELL
CONFIDENTIAL/PROPRIETARY
Comp
Comp
al Electronics, Inc.
Titl
Titl
Titl
e
e
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
e
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
DGPU
DGPU
LA-G
LA-G
891P
891P
28 102M
28 102M
1
0.3
0.3
of
of
of
5
D D
C C
4
3
2
1
Reserve
B B
A A
DEL
L CONFIDENTIAL/PROPRIETARY
Com
Com
pal Electronics, Inc.
Tit
Tit
Tit
le
le
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
le
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
pal Electronics, Inc.
DGPU
DGPU
LA-
LA-
G891P
G891P
1
29 10
29 10
0.3
0.3
2Monday, February 25, 2019
2Monday, February 25, 2019
of
of
of
5
D D
C C
4
3
2
1
Reserve
B B
A A
DELL
CONFIDENTIAL/PROPRIETARY
Comp
Comp
al Electronics, Inc.
Titl
Titl
Titl
e
e
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
e
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
onday, February 25, 2019
onday, February 25, 2019
Date: Sheet
Date: Sheet
Date: Sheet
al Electronics, Inc.
DGPU
DGPU
LA-G
LA-G
891P
891P
30 102M
30 102M
1
0.3
0.3
of
of
of
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