Dell DB13 DIS Schematics

5

4

3

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1

DB13 DIS Schematics Document

D D

Sandy Bridge

Intel PCH

C C

2010-11-25 REV : X00

B B

DY :None Installed PSL: KBC795 PSL circuit for 10mW solution installed. 10mW: External circuit for 10mW solution installed. GSONSOR_ST: Stuff for ST G-Sensor GSENSOR_ADI: Stuff for ADI G-Sensor

A A

5

4

http://hobi-elektronika.net

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Cover

DB13 DIS

1 105Friday, November 26, 2010

of

1

of

X00

5

##OnMainBoard

4

VRAM

512MB/1GB Colay

D D

88,89

4

gDDR3 800MHz

NVIDIA N12P-GV

83.84,85,86,87

C C

HDMI

Display Port

LCD

SD/SDIO/SDHC /SDXC/MS/MS Pro MSXC/MMC/xD

51

52

49

74

LVDS(Dual Channel)

Card Reader

RTS5209

PCIE x 1

32

(9 in 1)

CAMERA

B B

w/ Digital MIC

49

USB 2.0 x 1

CODEC

HP

58

MIC IN

58

A A

2CH SPEAKER (2W/4ohm)

5

58

IDT 92HD87B1

4

3

DB13 DIS Block Diagram

Intel CPU

DDRIII 1066/1333 Channel A

Sandy Bridge

PCIe x 16

(Discrete only)

PCIE x 1 USB2.0 x 1

HDA

29

4

BGA Type

4,5,6,7,8,9,10,11,12,13

FDIx4x2

(UMA only)

PCH Cougar Point

14 USB 2.0/1.1 ports

ETHERNET (10/100/1000Mb)

High Definition Audio

SATA ports (6)

PCIE ports (8)

17,18,19,20,21,22,23,24,25,26

SPI

Flash ROM

4MB

27

Touch PAD

60

NUVOTON

NPCE795PA

69 69

DMIx4

Intel

LPC I/F

ACPI 1.1

SMBus

LPC Bus

KBC

ADC

PWM

Int. KB

http://hobi-elektronika.net

DDRIII 1066/1333 Channel B

PCIE x 1

PCIE x 1,USB2.0 x 1

SATA x 2

Free Fall Sensor

Thermal Sensor

Main:ENEP2800

PWM x 1

3

79

28

25

Project Code: 91.4NY01.001 PCB P/N :48.4NY02.0SA Revision : 10320-SA

10/100/1000 LOM

Realtek

RTL8111E-VB

USB3.0 Controller

TI TUSB7320RKM (NEC uPD720200F1)

(On Daughter Board)

Mini-Card

WWAN

Mini-Card

802.11a/b/g + BT version 3.0

PWM Fan

28

DDRIII 1066/1333

31

66

65

2

Slot 1

14

Slot 2

15

RJ45 CONN

35

(On Daughter Board)

HDD

ODD

USB3.0 x 2

SIM

56

2

1

CPU DC/DC

VT1316+VT1317

INPUTS

DCBATOUT

SYSTEM DC/DC

VT1316+VT1317

INPUTS

DCBATOUT

SYSTEM DC/DC

TPS51461

INPUTS

DCBATOUT

SYSTEM DC/DC

INPUTS

VT358

DCBATOUT

SYSTEM DC/DC

VT357

INPUTS

DCBATOUT

TI CHARGER

59

BQ24745

INPUTS

+DC_IN_S5

SYSTEM DC/DC

62

TPS51427

INPUTS

DCBATOUT 5V_S5

26

SYSTEM DC/DC

TPS51311

INPUTS

3D3V_S5

Switches

INPUTS OUTPUTS

1D5V_S3 5V_S5

PCB LAYER

DIS

L1:Top L2:GND L3:Signal L4:Signal L5:VCC L6:Signal L7:GND L8:Bottom

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Friday, November 26, 2010

Taipei Hsien 221, Taiwan, R.O.C.

Block Diagram

DB13 DIS

1

OUTPUTS

VCC_CORE

OUTPUTS

VCC_GFXCORE

OUTPUTS

0D85V_S0

OUTPUTS

1D5V_S3 0D75V_S0 DDR_VREF_S3

OUTPUTS

1D05V_VTT

OUTPUTS

DCBATOUT+PBATT

OUTPUTS

5V_AUX_S5 3D3V_AUX_S5

3D3V_S5 15V_S5

OUTPUTS

1D8V_S0

1D5V_S0 5V_S0 3D3V_S03D3V_S5

of

2 105

42

44

48

46

45

40

41

47

36

X00

5

PCH Strapping

Huron River Schematic Checklist Rev.1_0

Name Schematics Notes

SPKR

INIT3_3V# Weak internal pull-up. This signal should not be pulled low. Leave as "No Connect".

GNT3#/GPIO55

D D

GNT2#/GPIO53 GNT1#/GPIO51

INTVRMEN

DF_TVS

SATA1GP /GPIO19

C C

HDA_SDO

HDA_SYNC

GPIO15

DSWVRMEN

B B

GPIO28

Reboot option at power-up

Internal weak Pull-down.

Default Mode:

Enable when Pull-up.

No Reboot Mode with TCO Disabled:

GNT[3:0]# functionality is not available on Mobile. Mobile: Used as GPIO only Pull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc3_3 power rail.

Integrated 1.05 V VRM Enable / Disable

Integrated 1.05 V VRMs is enabled when high. This signal should always be pulled high

DMI and FDI Tx/Rx Termination Voltage

Weak internal pull-down. It needs to be connected to PROC_SELECT with a 1K±5% pull-up resistor to PCH VCCPNAND rail and a 4.7K±5% series resistor.

Boot BIOS Strap bit 0

This Signal has a weak internal pull-up. Note: This field determines the destination of accesses to the BIOS memory range. This strap is used in conjunction with Boot BIOS Destination Selection 1 strap. Bit11 Bit 10 Boot BIOS Destination 0 1 Reserved 1 0 PCI 1 1 SPI 0 0 LPC

Signal has a weak internal pull-down. Default: the security measures defined in the Flash Descriptor will be in effect. Pull-up: the Flash Descriptor Security will be overridden. This strap should only be asserted high via external pull-up in manufacturing or debug environments ONLY.

On-Die PLL Voltage Regulator Voltage Select

This signal has a weak internal pull-down. On Die PLL VR is supplied by 1.5 V when sampled high, 1.8 V when sampled low. Needs to be pulled High for Huron River platform.

TLS Confidentiality

Low - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no confidentiality High - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality This signal has a weak internal pull-down.



NOTE: A strong pull-up may be needed for GPIO functionality

Deep S4/S5 Well On-Die Voltage Regulator Enable

This signal enables the internal Deep Sleep 1.05 V regulators. This signal must be always pulled-up to VccRTC.

On-Die PLL Voltage Regulator

This signal has a weak internal pull-up. The On-Die PLL voltage regulator is enabled when sampled high. When sampled low the On-Die PLL Voltage Regulator is disabled. If not used, 8.2-kȍ to 10-kȍ pull-up to +V3.3A power-rail.

4

3

Processor Strapping

Pin Name Strap Description Configuration (Default value for each bit is

CFG[2]

CFG[4]

CFG[6:5]

CFG[7]

POWER PLANE

5V_S0 3D3V_S0 1D8V_S0 1D5V_S0 1D05V_VTT 0D85V_S0 0D75V_S0 VCC_CORE VCC_GFXCORE

5V_USBX_S3 1D5V_S3 DDR_VREF_S3

BT+ DCBATOUT 5V_S5 5V_AUX_S5 3D3V_S5 3D3V_AUX_S5

3D3V_AUX_KBC

3D3V_AUX_S5

PCI-Express Static Lane Reversal

Display Port Presence strap

PCI-Express Port Bifurcation Straps

PEG DEFER TRAINING

VOLTAGE DESCRIPTION

5V

3.3V

1.8V

1.5V

1.05V

0.95 - 0.85V

0.75V

0.35V to 1.5V

0.4 to 1.25V

5V

1.5V

0.75V

6V-14.1V 6V-14.1V 5V 5V

3.3V

3.3V3D3V_LAN_S5

3.3V

1 unless specified otherwise)

1:

Normal Operation. Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

0:

Disabled - No Physical Display Port attached to

1:

Embedded Display Port.

Enabled - An external Display Port device is

0:

connectd to the Embedded Display Port

11 : x16 - Device 1 functions 1 and 2 disabled 10 : x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01 : Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00 : x8, x4, x4 - Device 1 functions 1 and 2 enabled

1:

PEG Train immediately following xxRESETB de assertion PEG Wait for BIOS for training

0:

Voltage Rails

ACTIVE IN

S0

S3

All S states

WOL_EN

DSW, Sx ON for supporting Deep Sleep states

G3, Sx

2

Huron River Schematic Checklist Rev.1_0

CPU Core Rail Graphics Core Rail

AC Brick Mode only

Legacy WOL

Powered by Li Coin Cell in G3 and +V3ALW in Sx

Default Value

0

1

11

1

USB Table

PCIE Routing

LANE1

LANE2

LANE3

LANE4

A A

LANE5

LANE6

LANE7

X

LAN (I/O Board)

Mini Card2(WWAN)

Mini Card1(WLAN)

USB3.0

Card Reader

X

SATA Table

SATA

Pair

0

1

2

3

4

5

Device

HDD1

N/A

ODD

N/A

LANE8 X

Pair

0

1

2

3

4

5

6

7

8

9

10

11

12

13

5

4

Device

X

Mini Card2 (WWAN)

X

Mini Card1 (WLAN)

CAMERA

X

http://hobi-elektronika.net

SMBus ADDRESSES

2

I C / SMBus Addresses

Device

EC SMBus 1 Battery Capacity Board

EC SMBus 2 PCH MXM LCD Thermal Sensor

PCH SMBus CK505 Clock Generator SO-DIMMA (SPD) SO-DIMMB (SPD) Digital Pot

3

HURON RIVER ORB

Address Hex Bus Ref Des

KBC_SDA1/KBC_SCL1 KBC_SDA1/KBC_SCL1

KBC_SDA2/KBC_SCL2 KBC_SDA2/KBC_SCL2 KBC_SDA2/KBC_SCL2 KBC_SDA2/KBC_SCL2

PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK PCH_SMBDATA/PCH_SMBCLK

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Table of Content

DB13 DIS

3 105Friday, November 26, 2010

1

of

X00

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3

2

1

SSID = CPU

Signal Routing Guideline: PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.

1 OF 9

CPU1A

D D

C C

Note: Intel DMI supports both Lane Reversal and polarity inversion but only at PCH side. This is enabled via a soft strap.

Note: Intel FDI supports both Lane Reversal and polarity inversion but only at PCH side. This is enabled via a soft strap.

Note: Lane reversal does not apply to FDI sideband signals.

1D05V_VTT

DMI_TXN[3:0](19)

DMI_TXP[3:0](19)

DMI_RXN[3:0](19)

DMI_RXP[3:0](19)

FDI_TXN[7:0](19)

FDI_TXP[7:0](19)

FDI_FSYNC0(19) FDI_FSYNC1(19)

FDI_INT(19)

FDI_LSYNC0(19) FDI_LSYNC1(19)

R402 24D9R2F-L-GPR402 24D9R2F-L-GP

1 2

X00 1111 Del R403

B B

NOTE. Processor strap CFG[4] should be pulled low to enable Embedded DisplayPort.

Signal Routing Guideline: EDP_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils. EDP_COMPIO keep W/S=4/15 mils and routing length less than 500 mils.

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3

DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3

DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7

FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7

DP_COMP

M2

DMI_RX#0

P6

DMI_RX#1

P1

DMI_RX#2

P10

DMI_RX#3

N3

DMI_RX0

P7

DMI_RX1

P3

DMI_RX2

P11

DMI_RX3

K1

DMI_TX#0

M8

DMI_TX#1

N4

DMI_TX#2

R2

DMI_TX#3

K3

DMI_TX0

M7

DMI_TX1

P4

DMI_TX2

T3

DMI_TX3

U7

FDI0_TX#0

W11

FDI0_TX#1

W1

FDI0_TX#2

AA6

FDI0_TX#3

W6

FDI1_TX#0

V4

FDI1_TX#1

Y2

FDI1_TX#2

AC9

FDI1_TX#3

U6

FDI0_TX0

W10

FDI0_TX1

W3

FDI0_TX2

AA7

FDI0_TX3

W7

FDI1_TX0

T4

FDI1_TX1

AA3

FDI1_TX2

AC8

FDI1_TX3

AA11

FDI0_FSYNC

AC12

FDI1_FSYNC

U11

FDI_INT

AA10

FDI0_LSYNC

AG8

FDI1_LSYNC

AF3

EDP_COMPIO

AD2

EDP_ICOMPO

AG11

EDP_HPD

AG4

EDP_AUX#

AF4

EDP_AUX

AC3

EDP_TX#0

AC4

EDP_TX#1

AE11

EDP_TX#2

AE7

EDP_TX#3

AC1

EDP_TX0

AA4

EDP_TX1

AE10

EDP_TX2

AE6

EDP_TX3

SANDYBRIDGE-1-GP-U-NF

DMI

Intel(R) FDI

DP

1 OF 9

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8

PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15

SANDYBRIDGE

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8

PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15

PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9

PEG_TX#10 PEG_TX#11 PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15

PCI EXPRESS -- GRAPHICS

PEG_TX0

PEG_TX1

PEG_TX2

PEG_TX3

PEG_TX4

PEG_TX5

PEG_TX6

PEG_TX7

PEG_TX8

PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

G3 G1 G4

H22 J21 B22 D21 A19 D17 B14 D13 A11 B10 G8 A8 B6 H8 E5 K7

K22 K19 C21 D19 C19 D16 C13 D12 C11 C9 F8 C8 C5 H6 F6 K6

G22 C23 D23 F21 H19 C17 K15 F17 F14 A15 J14 H13 M10 F10 D9 J4

F22 A23 D24 E21 G19 B18 K17 G17 E14 C15 K13 G13 K10 G10 D8 K4

PEG_IRCOMP_R

PEG_RXN15 PEG_RXN14 PEG_RXN13 PEG_RXN12 PEG_RXN11 PEG_RXN10 PEG_RXN9 PEG_RXN8 PEG_RXN7 PEG_RXN6 PEG_RXN5 PEG_RXN4 PEG_RXN3 PEG_RXN2 PEG_RXN1 PEG_RXN0

PEG_RXP15 PEG_RXP14 PEG_RXP13 PEG_RXP12 PEG_RXP11 PEG_RXP10 PEG_RXP9 PEG_RXP8 PEG_RXP7 PEG_RXP6 PEG_RXP5 PEG_RXP4 PEG_RXP3 PEG_RXP2 PEG_RXP1 PEG_RXP0

PEG_C_TXN15 PEG_C_TXN14 PEG_C_TXN13 PEG_C_TXN12 PEG_C_TXN11 PEG_C_TXN10 PEG_C_TXN9 PEG_C_TXN8 PEG_C_TXN7 PEG_C_TXN6 PEG_C_TXN5 PEG_C_TXN4 PEG_C_TXN3 PEG_C_TXN2 PEG_C_TXN1 PEG_C_TXN0

PEG_C_TXP15 PEG_C_TXP14 PEG_C_TXP13 PEG_C_TXP12 PEG_C_TXP11 PEG_C_TXP10 PEG_C_TXP9 PEG_C_TXP8 PEG_C_TXP7 PEG_C_TXP6 PEG_C_TXP5 PEG_C_TXP4 PEG_C_TXP3 PEG_C_TXP2 PEG_C_TXP1 PEG_C_TXP0

R401 24D9R2F-L-GPR401 24D9R2F-L-GP

1 2

PEG_RXN[0..15]

PEG_RXP[0..15]

C401 SCD22U10V2KX-1GPC401 SCD22U10V2KX-1GP

1 2

C402 SCD22U10V2KX-1GPC402 SCD22U10V2KX-1GP

1 2

C403 SCD22U10V2KX-1GPC403 SCD22U10V2KX-1GP

1 2

C404 SCD22U10V2KX-1GPC404 SCD22U10V2KX-1GP

1 2

C405 SCD22U10V2KX-1GPC405 SCD22U10V2KX-1GP

1 2

C406 SCD22U10V2KX-1GPC406 SCD22U10V2KX-1GP

1 2

C407 SCD22U10V2KX-1GPC407 SCD22U10V2KX-1GP

1 2

C408 SCD22U10V2KX-1GPC408 SCD22U10V2KX-1GP

1 2

C409 SCD22U10V2KX-1GPC409 SCD22U10V2KX-1GP

1 2

C410 SCD22U10V2KX-1GPC410 SCD22U10V2KX-1GP

1 2

C411 SCD22U10V2KX-1GPC411 SCD22U10V2KX-1GP

1 2

C412 SCD22U10V2KX-1GPC412 SCD22U10V2KX-1GP

1 2

C413 SCD22U10V2KX-1GPC413 SCD22U10V2KX-1GP

1 2

C414 SCD22U10V2KX-1GPC414 SCD22U10V2KX-1GP

1 2

C415 SCD22U10V2KX-1GPC415 SCD22U10V2KX-1GP

1 2

C416 SCD22U10V2KX-1GPC416 SCD22U10V2KX-1GP

1 2

C417 SCD22U10V2KX-1GPC417 SCD22U10V2KX-1GP

1 2

C418 SCD22U10V2KX-1GPC418 SCD22U10V2KX-1GP

1 2

C419 SCD22U10V2KX-1GPC419 SCD22U10V2KX-1GP

1 2

C420 SCD22U10V2KX-1GPC420 SCD22U10V2KX-1GP

1 2

C421 SCD22U10V2KX-1GPC421 SCD22U10V2KX-1GP

1 2

C422 SCD22U10V2KX-1GPC422 SCD22U10V2KX-1GP

1 2

C423 SCD22U10V2KX-1GPC423 SCD22U10V2KX-1GP

1 2

C424 SCD22U10V2KX-1GPC424 SCD22U10V2KX-1GP

1 2

C425 SCD22U10V2KX-1GPC425 SCD22U10V2KX-1GP

1 2

C426 SCD22U10V2KX-1GPC426 SCD22U10V2KX-1GP

1 2

C427 SCD22U10V2KX-1GPC427 SCD22U10V2KX-1GP

1 2

C428 SCD22U10V2KX-1GPC428 SCD22U10V2KX-1GP

1 2

C429 SCD22U10V2KX-1GPC429 SCD22U10V2KX-1GP

1 2

C430 SCD22U10V2KX-1GPC430 SCD22U10V2KX-1GP

1 2

C431 SCD22U10V2KX-1GPC431 SCD22U10V2KX-1GP

1 2

C432 SCD22U10V2KX-1GPC432 SCD22U10V2KX-1GP

1 2

1D05V_VTT

PEG_RXN[0..15] (83)

PEG_RXP[0..15] (83)

NOTE. If PEG is not implemented, the RX&TX pairs can be left as No Connect

PEG_TXN[0..15]

PEG_TXN15 PEG_TXN14 PEG_TXN13 PEG_TXN12 PEG_TXN11 PEG_TXN10 PEG_TXN9 PEG_TXN8 PEG_TXN7 PEG_TXN6 PEG_TXN5 PEG_TXN4 PEG_TXN3 PEG_TXN2 PEG_TXN1 PEG_TXN0

PEG_TXP15 PEG_TXP14 PEG_TXP13 PEG_TXP12 PEG_TXP11 PEG_TXP10 PEG_TXP9 PEG_TXP8 PEG_TXP7 PEG_TXP6 PEG_TXP5 PEG_TXP4 PEG_TXP3 PEG_TXP2 PEG_TXP1 PEG_TXP0

PEG_TXP[0..15]

PEG_TXN[0..15] (83)

PEG_TXP[0..15] (83)

Stuff to disable internal graphics function for power saving.

A A

http://hobi-elektronika.net

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU 1/7(PEG/DMI/FDI/eDP)

Size Document Number Rev

Date: Sheet

CPU 1/7(PEG/DMI/FDI/eDP)

Taipei Hsien 221, Taiwan, R.O.C.

DB13 DIS

of

4 105Friday, November 26, 2010

of

4 105Friday, November 26, 2010

of

4 105Friday, November 26, 2010

X00

5

SSID = CPU

1D05V_VTT

R501

D D

C C

7,31,32,35,65,66,71,83)

R501

1 2

62R2J-GP

H_PROCHOT#

CRB : 47pf CEKLT:43pf

R503

1 2

PLT_RST#

12

C502

C502 SC47P50V2JN-3GP

SC47P50V2JN-3GP

Connect EC to PROCHOT# through inverting OD buffer.

10KR2J-3-GP

1 2

1K5R2F-2-GP

EDS R1.5: BGA have different name with rPGA

X00 1008

H_SNB_IVB#(18)

TP501TPAD14-GP TP501TPAD14-GP

TP502TPAD14-GP TP502TPAD14-GP

H_PECI(22,27)

H_PROCHOT#(27,40,42)

H_THERMTRIP#(22,36)

H_CPUPWRGD_R

H_PM_SYNC(19)

H_CPUPWRGD(22,36)

PM_DRAM_PWRGD(19,37)

VDDPWRGOOD(37)

R510

12

R509

R509 750R2F-GP

750R2F-GP

1

R513

1 2

56R2J-4-GP

20100923 X01 Modify: Change R504 to 0R0402 short pad from 0ohm.

R504

1 2

0R0402-PAD

R505

1 2

DY

12

C501

DY

SC220P50V2KX-3GP

SKTOCC#_R

H_CATERR#

H_PROCHOT#_R

H_CPUPWRGD_R

VDDPWRGOOD

0R2J-2-GP

BUF_CPU_RST#

4

CPU1B

MISC

F49

PROC_SELECT#

C57

PROC_DETECT#

C49

CATERR#

A48

PECI

C45

PROCHOT#

D45

THERMTRIP#

C48

PM_SYNC

B46

UNCOREPWRGOOD

BE45

SM_DRAMPWROK

D44

RESET#

SANDYBRIDGE-1-GP-U-NF

THERMAL

SANDYBRIDGE

PWR MANAGEMENT

3

2 OF 9

BCLK

BCLK#

DPLL_REF_CLK

DPLL_REF_CLK#

MISC

BCLK_ITP

BCLK_ITP#

SM_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

PRDY# PREQ#

TCK TMS

TRST#

TDO

DBR#

BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

TDI

CLOCKS

DDR3

JTAG & BPM

J3 H2

AG3 AG1

N59 N58

AT30

BF44 BE43 BG43

N53 N55

L56 L55 J58

M60 L59

K58

G58 E55 E59 G55 G59 H60 J59 J61

CLK_DP_P_R CLK_DP_N_R

TEST_ITP TEST_ITP#

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

XDP_PRDY# XDP_PREQ#

XDP_TCLK XDP_TMS XDP_TRST#

XDP_TDI XDP_TDO

XDP_DBRESET#

XDP_BPM0 XDP_BPM1 XDP_BPM2 XDP_BPM3 XDP_BPM4 XDP_BPM5 XDP_BPM6 XDP_BPM7

R512

1 2

1KR2J-1-GP

R514

1 2

1KR2J-1-GP

1

TP513 TPAD14-GPTP513 TPAD14-GP

1

TP514 TPAD14-GPTP514 TPAD14-GP

R502

1 2

4K99R2F-L-GP

R506 140R2F-GPR506 140R2F-GP

1 2

R507 25D5R2F-GPR507 25D5R2F-GP

1 2

R508 200R2F-L-GPR508 200R2F-L-GP

1 2

1

TP511 TPAD14-GPTP511 TPAD14-GP

1

TP512 TPAD14-GPTP512 TPAD14-GP

XDP_DBRESET# (19)

1 1 1 1 1 1 1 1

2

CLK_EXP_P (20) CLK_EXP_N (20)

1D05V_VTT

X00 1011

SM_DRAMRST# (37)

TP503 TPAD14-GPTP503 TPAD14-GP TP504 TPAD14-GPTP504 TPAD14-GP TP505 TPAD14-GPTP505 TPAD14-GP TP506 TPAD14-GPTP506 TPAD14-GP TP507 TPAD14-GPTP507 TPAD14-GP TP508 TPAD14-GPTP508 TPAD14-GP TP509 TPAD14-GPTP509 TPAD14-GP TP510 TPAD14-GPTP510 TPAD14-GP

Disabling Guidelines: If motherboard only supports external graphics: Connect DPLL_REF_SSCLK on Processor to GND through 1K +/- 5% resistor. Connect DPLL_REF_SSCLK# on Processor to VCCP through 1K +/- 5% resistorpower (~15 mW) may be wasted.

Signal Routing Guideline: SM_RCOMP keep routing length less than 500 mils.

1

X00 1011

XDP_TDI XDP_TMS XDP_TDO XDP_TCLK

XDP_TRST#

RN501

1

8

2

7

3

6

4 5

SRN51J-1-GP

R511 51R2J-2-GPR511 51R2J-2-GP

1 2

1D05V_VTT

3D3V_S0

XDP_DBRESET#

B B

DY

VCC

1D05V_VTT

DY

5

4

12

R518

R518 75R2J-1-GP

75R2J-1-GP

3D3V_S0

12

C503

DY

SCD1U10V2KX-5GP

1 2

DY

R517 43R2J-GP

DY

12

0R2J-2-GP

BUF_CPU_RST#BUFO_CPU_RST#

R515

0617 Modify:Joseph Removed U501 Buffer reset to CPU circuit. 2010/07/19 Add buffer for PLT_RST# based on Intel review. 2010/07/20 DY buffer circuit and add R510, R509 and C501

2010/07/20 Change U501 to 73.01G09.AAH

Buffered reset to CPU

U501

1

IN B

A A

PLT_RST#(18,27,31,32,35,65,66,71,83)

2

IN A

GND3OUT Y

74VHC1G09DFT2G-GP

73.01G09.AAH

http://hobi-elektronika.net

For XDP connector no enough space 6/28

Title

CPU 2/7(THERMAL/CLOCK/PM )

Size Document Number Rev

Date: Sheet

1 2

20100722 Modify: Change R516 10K from 1K

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

DB13 DIS

R516

R516 10KR2J-3-GP

10KR2J-3-GP

5 105Friday, November 26, 2010

X00

of

X00

5

SSID = CPU

4

3

2

1

3 OF 9

CPU1C

M_A_DQ[63:0](14)

D D

C C

B B

M_A_DQ[63:0]

M_A_BS0(14) M_A_BS1(14) M_A_BS2(14)

M_A_CAS#(14) M_A_RAS#(14) M_A_WE#(14)

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

AG6

AP11

AJ10

AR11

AP6 AU6 AV9 AR6 AP8

AT13

AU13

BC7

BB7 BA13 BB11

BA7

BA9

BB9 AY13 AV14 AR14 AY17 AR19 BA14 AU14 BB14 BB17 BA45 AR43

AW48

BC48 BC45 AR45

AT48 AY48 BA49 AV49 BB51 AY53 BB49 AU49 BA53 BB55 BA55 AV56 AP50 AP53 AV54

AT54 AP56 AP52 AN57 AN53 AG56 AG53 AN55 AN52 AG55 AK56

BD37

BF36 BA28

BE39 BD39

AT41

CPU1C

SA_DQ0

AJ6

SA_DQ1 SA_DQ2

AL6

SA_DQ3 SA_DQ4

AJ8

SA_DQ5

AL8

SA_DQ6

AL7

SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

SA_BS0 SA_BS1 SA_BS2

SA_CAS# SA_RAS# SA_WE#

SANDYBRIDGE

DDR SYSTEM MEMORY A

3 OF 9

SA_CLK0

SA_CLK#0

SA_CKE0

SA_CLK1

SA_CLK#1

SA_CKE1

SA_CS#0 SA_CS#1

SA_ODT0 SA_ODT1

SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

AU36 AV36 AY26

AT40 AU40 BB26

BB40 BC41

AY40 BA41

AL11 AR8 AV11 AT17 AV45 AY51 AT55 AK55

AJ11 AR10 AY11 AU17 AW45 AV51 AT56 AK54

BG35 BB34 BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32 BE37 BA30 BC30 AW41 AY28 AU26

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DIM0_CLK_DDR0 (14) M_A_DIM0_CLK_DDR#0 (14) M_A_DIM0_CKE0 (14)

M_A_DIM0_CLK_DDR1 (14) M_A_DIM0_CLK_DDR#1 (14) M_A_DIM0_CKE1 (14)

M_A_DIM0_CS#0 (14) M_A_DIM0_CS#1 (14)

M_A_DIM0_ODT0 (14) M_A_DIM0_ODT1 (14)

M_A_DQS#[7:0] (14)

M_A_DQS[7:0] (14)

M_A_A[15:0] (14)

M_B_DQ[63:0](15)

M_B_DQ[63:0]

M_B_BS0(15) M_B_BS1(15) M_B_BS2(15)

M_B_CAS#(15) M_B_RAS#(15) M_B_WE#(15)

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

AN3 AR4 AK4 AK3 AN4 AR1 AU4 AT2 AV4 BA4 AU3 AR3 AY2 BA3 BE9 BD9

BD13

BF12

BF8 BD10 BD14 BE13

BF16 BE17 BE18 BE21 BE14 BG14 BG18

BF19 BD50

BF48 BD53

BF52 BD49 BE49 BD54 BE53

BF56 BE57 BC59 AY60 BE54 BG54 BA58

AW59 AW58

AU58 AN61 AN59 AU59 AU61 AN58 AR58 AK58

AL58 AG58 AG59 AM60

AL59

AF61 AH60

BG39 BD42

AT22

AV43

BF40 BD45

4 OF 9

CPU1D

AL4

SB_DQ0

AL1

SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_BS0 SB_BS1 SB_BS2

SB_CAS# SB_RAS# SB_WE#

SANDYBRIDGE

DDR SYSTEM MEMORY B

4 OF 9

SB_CLK0

SB_CLK#0

SB_CKE0

SB_CLK1

SB_CLK#1

SB_CKE1

SB_CS#0 SB_CS#1

SB_ODT0 SB_ODT1

SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7

SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8

SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

BA34 AY34 AR22

BA36 BB36 BF27

BE41 BE47

AT43 BG47

AL3 AV3 BG11 BD17 BG51 BA59 AT60 AK59

AM2 AV1 BE11 BD18 BE51 BA61 AR59 AK61

BF32 BE33 BD33 AU30 BD30 AV30 BG30 BD29 BE30 BE28 BD43 AT28 AV28 BD46 AT26 AU22

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DIM0_CLK_DDR0 (15) M_B_DIM0_CLK_DDR#0 (15) M_B_DIM0_CKE0 (15)

M_B_DIM0_CLK_DDR1 (15) M_B_DIM0_CLK_DDR#1 (15) M_B_DIM0_CKE1 (15)

M_B_DIM0_CS#0 (15) M_B_DIM0_CS#1 (15)

M_B_DIM0_ODT0 (15) M_B_DIM0_ODT1 (15)

M_B_DQS#[7:0] (15)

M_B_DQS[7:0] (15)

M_B_A[15:0] (15)

SANDYBRIDGE-1-GP-U-NF

A A

5

4

http://hobi-elektronika.net

3

SANDYBRIDGE-1-GP-U-NF

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

CPU 3/7(DDR)

DB13 DIS

1

of

6 105Friday, November 26, 2010

of

6 105Friday, November 26, 2010

of

6 105Friday, November 26, 2010

X00

5

4

3

2

1

SSID = CPU

BGA pin out modify

5 OF 9

CPU1E

X00 1011

CFG2

CFG4 CFG5

D D

C C

CFG6

Remove to Page 8, BGA pin out

X00 1011

CPU1E

B50

CFG0

C51

CFG1

B54

CFG2

D53

CFG3

A51

CFG4

C53

CFG5

C55

CFG6

H49

CFG7

A55

CFG8

H51

CFG9

K49

CFG10

K53

CFG11

F53

CFG12

G53

CFG13

L51

CFG14

F51

CFG15

D52

CFG16

L53

CFG17

H43

VCC_VAL_SENSE

K43

VSS_VAL_SENSE

H45

VAXG_VAL_SENSE

K45

VSSAXG_VAL_SENSE

F48

VCC_DIE_SENSE

H48

RSVD#H48

K48

RSVD#K48

BA19

RSVD#BA19

AV19

RSVD#AV19

AT21

RSVD#AT21

BB21

RSVD#BB21

BB19

RSVD#BB19

AY21

RSVD#AY21

BA22

RSVD#BA22

AY22

RSVD#AY22

AU19

RSVD#AU19

AU21

RSVD#AU21

BD21

RSVD#BD21

BD22

RSVD#BD22

BD25

RSVD#BD25

BD26

RSVD#BD26

BG22

RSVD#BG22

BE22

RSVD#BE22

BG26

RSVD#BG26

BE26

RSVD#BE26

BF23

RSVD#BF23

BE24

RSVD#BE24

SANDYBRIDGE

RESERVED

5 OF 9

RSVD#BE7

RSVD#BG7

RSVD#N42

RSVD#L42 RSVD#L45 RSVD#L47

RSVD#M13 RSVD#M14 RSVD#U14

RSVD#W14

RSVD#P13

RSVD#AT49

RSVD#K24

RSVD#AH2 RSVD#AG13 RSVD#AM14 RSVD#AM15

RSVD#N50

DC_TEST_A4 DC_TEST_C4 DC_TEST_D3 DC_TEST_D1

DC_TEST_A58 DC_TEST_A59

DC_TEST_C59

DC_TEST_A61 DC_TEST_C61 DC_TEST_D61

DC_TEST_BD61 DC_TEST_BE61 DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58

DC_TEST_BG4 DC_TEST_BG3

DC_TEST_BE3

DC_TEST_BG1

DC_TEST_BE1 DC_TEST_BD1

X00 1116 remove M3

M_VREF_DQ_DIMM0_C

BE7

M_VREF_DQ_DIMM1_C

BG7

N42 L42 L45 L47

M13 M14 U14 W14 P13

AT49 K24

AH2 AG13 AM14 AM15

N50

A4

DC_TEST_C4D3

C4 D3 D1 A58

DC_TEST_A59C59

A59 C59

DC_TEST_A61C61

A61 C61 D61 BD61

DC_TEST_BE61BE59

BE61 BE59

DC_TEST_BG61BG59

BG61 BG59 BG58 BG4

DC_TEST_BG3BE3

BG3 BE3

DC_TEST_BE1BG1

BG1 BE1 BD1

CFG5

CFG6

CFG4

CFG2

DY

12

R701

DY

1KR2J-1-GP

12

DY

12

R702

R702 1KR2J-1-GP

1KR2J-1-GP

R703

R703 3K3R2F-2-GP

3K3R2F-2-GP

PEG Static Lane Reversal

CFG2

PCIE Port Bifurcation Straps

R704

1KR2J-1-GP

CFG[6:5]

11: x16 - Device 1 functions 1 and 2 disabled

10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

PEG DEFER TRAINING

CFG7

1: PEG Train immediately following xxRESETB de assertion

0: PEG Wait for BIOS for training

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

Display Port Presence Strap

CFG4

1: Disabled; No Physical Display Port attached to Embedded Display Port

0: Enabled; An external Display Port device is connected to the Embedded Display Port

SANDYBRIDGE-1-GP-U-NF

B B

Intel CRB

X00 1011

X00 2010-11-16 Remove M3 - Processor Generated SO-DIMM VREF_DQ

A A

5

4

http://hobi-elektronika.net

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

CPU 4/7(RESERVED)

Size Document Number Rev

Date: Sheet

CPU 4/7(RESERVED)

DB13 DIS

Taipei Hsien 221, Taiwan, R.O.C.

of

7 105Friday, November 26, 2010

of

7 105Friday, November 26, 2010

of

7 105Friday, November 26, 2010

1

X00

5

4

3

2

1

SSID = CPU

D D

X00 1008

VCCIO Output Decoupling Recommendation:

Modify VCCCORE Cap

X00 1011

VCC_CORE

PROCESSOR CORE POWER: 53A

12

C801

SC10U6D3V5KX-1GP

12

C818

C C

SC10U6D3V5KX-1GP

12

C822

C821

SC2D2U6D3V2CX-LL-GP

12

C858

C856

SC2D2U6D3V2CX-LL-GP

12

C802

SC10U6D3V5KX-1GP

Layout Note: 10u Cap place during CPU & IMVP

C819

SC10U6D3V5KX-1GP

12

SC2D2U6D3V2CX-LL-GP

12

SC2D2U6D3V2CX-LL-GP

C804

C803

SC10U6D3V5KX-1GP

12

C847

C849

SC10U6D3V5KX-1GP

12

C823

C824

SC2D2U6D3V2CX-LL-GP

Layout Note: 2.2u Cap place under CPU

12

C851

C861

SC2D2U6D3V2CX-LL-GP

POP rule: 1. MLCC number * 0.8

2. 22u-->10u

12

C811

SC10U6D3V5KX-1GP

12

C817

SC10U6D3V5KX-1GP

12

C826

C825

SC2D2U6D3V2CX-LL-GP

12

C853

C855

SC2D2U6D3V2CX-LL-GP

C814

C813

SC10U6D3V5KX-1GP

12

C837

C836

SC10U6D3V5KX-1GP

12

C828

C827

SC2D2U6D3V2CX-LL-GP

12

C859

C862

SC2D2U6D3V2CX-LL-GP

VCC_CORE

12

C815

C816

C812

SC10U6D3V5KX-1GP

12

SC10U6D3V5KX-1GP

12

C831

SC2D2U6D3V2CX-LL-GP

C852

SC2D2U6D3V2CX-LL-GP

12

C820

C846

SC10U6D3V5KX-1GP

12

C820

C848

SC10U6D3V5KX-1GP

12

C832

C833

SC2D2U6D3V2CX-LL-GP

12

C857

C854

SC2D2U6D3V2CX-LL-GP

C850

C835

C834

SC2D2U6D3V2CX-LL-GP

12

C863

C864

C860

SC2D2U6D3V2CX-LL-GP

VCC Output Decoupling CAP Recommendation:

1. 1.9m ohm loadline design:(for SV) 4 x 470 uF

B B

A A

25 x 22 uF 35 x 2.2uF

2. 2.9m ohm loadline design: (for ULV/LV) 3 x 330uF 12 x 22uF 16 x 2.2uF

Revised VCC decoupling Cap list

X00 1011

5

4

CPU1F

A26

VCC

A29

VCC

A31

VCC

A34

VCC

A35

VCC

A38

VCC

A39

VCC

A42

VCC

C26

VCC

C27

VCC

C32

VCC

C34

VCC

C37

VCC

C39

VCC

C42

VCC

D27

VCC

D32

VCC

D34

VCC

D37

VCC

D39

VCC

D42

VCC

E26

VCC

E28

VCC

E32

VCC

E34

VCC

E37

VCC

E38

VCC

F25

VCC

F26

VCC

F28

VCC

F32

VCC

F34

VCC

F37

VCC

F38

VCC

F42

VCC

G42

VCC

H25

VCC

H26

VCC

H28

VCC

H29

VCC

H32

VCC

H34

VCC

H35

VCC

H37

VCC

H38

VCC

H40

VCC

J25

VCC

J26

VCC

J28

VCC

J29

VCC

J32

VCC

J34

VCC

J35

VCC

J37

VCC

J38

VCC

J40

VCC

J42

VCC

K26

VCC

K27

VCC

K29

VCC

K32

VCC

K34

VCC

K35

VCC

K37

VCC

K39

VCC

K42

VCC

L25

VCC

L28

VCC

L33

VCC

L36

VCC

L40

VCC

N26

VCC

N30

VCC

N34

VCC

N38

VCC

SANDYBRIDGE-1-GP-U-NF

SANDYBRIDGE

CORE SUPPLY

POWER

6 OF 9

AF46

VCCIO

AG48

VCCIO

AG50

VCCIO

AG51

VCCIO

AJ17

VCCIO

AJ21

VCCIO

AJ25

VCCIO

AJ43

VCCIO

AJ47

VCCIO

AK50

VCCIO

AK51

VCCIO

AL14

VCCIO

AL15

VCCIO

AL16

VCCIO

AL20

VCCIO

AL22

VCCIO

AL26

VCCIO

AL45

VCCIO

AL48

VCCIO

AM16

VCCIO

AM17

VCCIO

AM21

VCCIO

AM43

VCCIO

AM47

VCCIO

AN20

VCCIO

AN42

VCCIO

AN45

VCCIO

AN48

VCCIO

AA14

VCCIO

AA15

VCCIO

AB17

VCCIO

AB20

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

VCCIO VCCIO

VCCIO_SEL

VCCPQE VCCPQE

VIDALERT#

VIDSCLK VIDSOUT

VCC_SENSE VSS_SENSE

VCCIO_SENSE

AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15

W16 W17

BC22

AM25 AN22

A44 B43 C44

F43 G43

AN16 AN17

H_VCCP_SEL

X00 1008

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

PEG AND DDR

SVID QUIET RAILS

VSS_SENSE_VCCIO

SENSE LINES

http://hobi-elektronika.net

2 x 330 uF (3 x 330 uF for 2012 capable designs) 5 x 22 uF & 5 x 0805 no-stuff at Bottom 7 x 22 uF & 2 x 0805 no-stuff at Top

12

C871

12

C872

SC10U6D3V3MX-GP

+V1.05S_VCCP_DDR_R

12

C865

C866

SC10U6D3V3MX-GP

PROCESSOR VCCIO: 8.5A

12

C869

C867

C868

SC10U6D3V3MX-GP

12

C870

SC10U6D3V3MX-GP

Layout Note: 10u Cap place during CPU & VR

No-stuff sites outside the socket may be removed. No-stuff sites inside the socket cavity need to remain.

+V1.05S_VCCP_DDR_R

12

VCCPQE

12

C877

C888

C892

SC1U10V2KX-1GP

Layout Note: 1u Cap place under CPU

12

C875

C876

C874

SC1U10V2KX-1GP

PROCESSOR 1.05V Quiet rail for DDR block (BGA only)

+V1.05S_VCCPQE should be short to +V1.05S_VCCP_DDR_R on board

R807 0R2J-2-GP

1 2

DY

+V1.05S_VCCP_DDR_R

R808

1 2

0R2J-2-GP

C927

SC1U10V2KX-1GP

R803 43R2J-GPR803 43R2J-GP

1 2

VCCIO_SENSE (45) VSSIO_SENSE (45)

12

C885

C890

SC1U10V2KX-1GP

12

C880

C878

SC1U10V2KX-1GP

12

C891

C873

C879

SC1U10V2KX-1GP

12

C883

C882

C881

SC1U10V2KX-1GP

X00 1011

+V1.05S_VCCP_DDR_R 1D05V_VTT

VR_SVID_ALERT# (42)

H_CPU_SVIDCLK (42)

H_CPU_SVIDDAT (42)

VCC_CORE

12

R801

R801 100R2F-L1-GP-U

100R2F-L1-GP-U

R802

R802 100R2F-L1-GP-U

100R2F-L1-GP-U

For CRB VIDSOUT need to pull high 130 ohm closr to CPU and IMVP7 For CRB VIDALERT# need to pull high 75 ohm close to CPU

Place near processor

3

X00 1008

X00 1011

12

C887

C889

SC1U10V2KX-1GP

12

C886

C884

SC1U10V2KX-1GP

1 2

R809 D01RL0816F-L-GPR809 D01RL0816F- L-GP

1 2

R810 D01RL0816F-L-GPR810 D01RL0816F- L-GP

VCCSENSE (42) VSSSENSE (42)

These resistors need to close to power IC.

1D05V_VTT

X00 1125

2

VR_SVID_ALERT#

H_CPU_SVIDDAT

R805 75R2J-1-GPR805 75R2J-1-GP

1 2

R804 130R2F-1-GPR804 130R2F-1-GP

1 2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

Title

Size Document Number Rev

Date: Sheet

Taipei Hsien 221, Taiw an, R.O.C.

CPU 5/7(VCC_CORE)

DB13 DIS

1

8 105Friday, Novemb er 26, 2010

of

X00

5

SSID = CPU

D D

X00 1011

VCC_GFXCORE

12

C901

12

C906

X00 1011

VAXG Output Decoupling CAP Recommendation:

1. 3.9m ohm loadline design:(for GT2) 2 x 470 uF 6 x 22 uF (0805) 6 x 10 uF (0603) 11 x 1 uF (0402)

2. 4.6m ohm loadline design:(for GT1) 2 x 330 uF 5 x 22 uF (0805) 6 x 10 uF (0603) 6 x 1 uF (0402)

C C

12

C921

12

C920

SC1U10V2KX-1GP

X00 1011

Disabling Guidelines for External Graphics Designs: Can connect to GND if motherboard only supports external graphics and if GFX VR is not stuffed. Can be left floating (Gfx VR keeps VAXG rail from floating) if the VR is stuffed

VCC_AXG_SENSE(42)

B B

VCCPLL Output Decoupling Recommendation: 1 x 330 uF 2 x 1 uF 1 x 10 uF

A A

VCCSA Output Decoupling Recommendation: 1 x 330 uF 5 x 10 uF (0603) 5 x 1uF (0402)

5

VSS_AXG_SENSE(42)

X00 1011

1D8V_S0

0D85V_S0

12

C938

Layout Note: Place under CPU

12

C940

4

PROCESSOR VAXG: 33A (for GT2)

12

C902

SC10U6D3V5KX-1GP

12

C908

SC10U6D3V3MX-GP

12

C929

C928

SC1U10V2KX-1GP

VCC_AXG_SENSE VSS_AXG_SENSE

12

C931

VCC_GFXCORE

C903

SC10U6D3V5KX-1GP

12

C934

C935

SC10U6D3V3MX-GP

12

C930

SC1U10V2KX-1GP

12

R906

R906 10R2F-N1-GP

10R2F-N1-GP

12

R907

R907 10R2F-N1-GP

10R2F-N1-GP

C904

SC10U6D3V5KX-1GP

12

SC10U6D3V3MX-GP

12

C933

SC1U10V2KX-1GP

12

PROCESSOR VCCPLL: 1.2A

12

C923

SC10U6D3V5KX-1GP

12

C922

SC1U10V2KX-1GP

C924

SC1U10V2KX-1GP

PROCESSOR VCCSA: 6A

12

C937

SC10U6D3V3MX-GP

12

C942

SC1U10V2KX-1GP

4

12

C939

SC10U6D3V3MX-GP

12

C943

SC1U10V2KX-1GP

12

C941

SC10U6D3V3MX-GP

12

C944

SC1U10V2KX-1GP

C905

SC10U6D3V5KX-1GP

C936

SC10U6D3V3MX-GP

12

C932

SC1U10V2KX-1GP

3

CPU1G

AA46

VAXG

AB47

VAXG

AB50

VAXG

AB51

VAXG

AB52

VAXG

AB53

VAXG

AB55

VAXG

AB56

VAXG

AB58

VAXG

AB59

VAXG

AC61

VAXG

AD47

VAXG

AD48

VAXG

AD50

VAXG

AD51

VAXG

AD52

VAXG

AD53

VAXG

AD55

VAXG

AD56

VAXG

AD58

VAXG

AD59

VAXG

AE46

VAXG

N45

VAXG

P47

VAXG

P48

VAXG

P50

VAXG

P51

VAXG

P52

VAXG

P53

VAXG

P55

VAXG

P56

VAXG

P61

VAXG

T48

VAXG

T58

VAXG

T59

VAXG

T61

VAXG

U46

VAXG

V47

VAXG

V48

VAXG

V50

VAXG

V51

VAXG

V52

VAXG

V53

VAXG

V55

VAXG

V56

VAXG

V58

VAXG

V59

VAXG

W50

VAXG

W51

VAXG

W52

VAXG

W53

VAXG

W55

VAXG

W56

VAXG

W61

VAXG

Y48

VAXG

Y61

VAXG

F45

VAXG_SENSE

G45

VSSAXG_SENSE

BB3

VCCPLL

BC1

VCCPLL

BC4

VCCPLL

L17

VCCSA

L21

VCCSA

N16

VCCSA

N20

VCCSA

N22

VCCSA

P17

VCCSA

P20

VCCSA

R16

VCCSA

R18

VCCSA

R21

VCCSA

U15

VCCSA

V16

VCCSA

V17

VCCSA

V18

VCCSA

V21

VCCSA

W20

VCCSA

SANDYBRIDGE-1-GP-U-NF

http://hobi-elektronika.net

SANDYBRIDGE

GRAPHICS

SENSE

LINES

SENSE

LINES

1.8V RAIL

SA RAIL

3

POWER

SENSE LINES

SM_VREF

DDR3 - 1.5V RAILS

QUIET RAILS

VDDQ_SENSE

VSS_SENSE_VDDQ

VCCSA_SENSE

VCCSA_VID VCCSA_VID

EDS R1.5: rPGA988 PinC22 BGA1023 PinD48

2

Refer to the latest Huron River Mainstream PDG (Doc# 436735) for more details on S3 power

7 OF 9

reduction implementation.

+V_SM_VREF_CNT should have 20 mil trace width 20 mil spacing

X00 1008

+V_SM_VREF_CNT

12

C958

SC10U6D3V3MX-GP

Layout Note: Place during CPU & VR

Layout Note: Place under CPU

12

C952

SC1U10V2KX-1GP

TacomaFalls_Schm_Rev0p5

R901

1 2

0R2J-2-GP

12

C926

SC1U10V2KX-1GP

0R2J-2-GP

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VCCDQ VCCDQ

AY43

AJ28 AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33

AM28 AN26

PROCESSOR DDR 1.5V QUIET RAIL (BGA only)

+V1.5S_VCCD_Q should be short to +V1.5S_VCCDDQ on board

TP_VDDQ_SENSE

BC43

TP_VDDQ_VSS

BA43

U10

D48 D49

1 1

VCCUSA_SENSE

H_FC_C22 VCCSA_SEL

TP901 TPAD14-GPTP901 TPAD14-GP TP902 TPAD14-GPTP902 TPAD14-GP

1

23

RN901

RN901 SRN1KJ-7-GP

SRN1KJ-7-GP

4

H_FC_C22 (48) VCCSA_SEL (48)

2

+V_SM_VREF_CNT (37)

12

C954

C953

SC10U6D3V3MX-GP

12

C945

SC1U10V2KX-1GP

1D5V_S01D5V_VCCDQ

X00 1007

1

Routing Guideline: Power from DDR_VREF_S3 and +V_SM_VREF_CNT should have 10 mils trace width.

X00 1124

PROCESSOR VDDQ: 10A

12

C955

C956

SC10U6D3V3MX-GP

12

C946

SC1U10V2KX-1GP

C948

SC1U10V2KX-1GP

C947

S3 power reduction 1.5V power plan; stitching Cap

VCCUSA_SENSE (48)

Title

CPU 6/7(VCC_GFX_CORE)

Size Document Number Rev

Date: Sheet

CPU 6/7(VCC_GFX_CORE)

1D5V_S0

12

SC10U6D3V3MX-GP

12

SC1U10V2KX-1GP

VDDQ Output Decoupling Recommendation: 1 x 330 uF 6 x 10 uF

C907 SCD1U10V2KX-5GP

1 2

C918 SCD1U10V2KX-5GP

1 2

C919 SCD1U10V2KX-5GP

1 2

C925 SCD1U10V2KX-5GP

1 2

DB13 DIS

12

C957

TC901

TC901 ST330U2VDM-4-GP

ST330U2VDM-4-GP

SC10U6D3V3MX-GP

Layout Note: Place near SM_VREF pin

12

C950

SC1U10V2KX-1GP

DY

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

C951

C949

SC1U10V2KX-1GP

1D5V_S31D5V_S0

1

SC1U10V2KX-1GP

9 105Friday, November 26, 2010

X00 1011

of

X00

5

4

3

2

1

SSID = CPU

D D

C C

B B

A A

5

CPU1H

A13

VSS

A17

VSS

A21

VSS

A25

VSS

A28

VSS

A33

VSS

A37

VSS

A40

VSS

A45

VSS

A49

VSS

A53

VSS

A9

VSS

AA1

VSS

AA13

VSS

AA50

VSS

AA51

VSS

AA52

VSS

AA53

VSS

AA55

VSS

AA56

VSS

AA8

VSS

AB16

VSS

AB18

VSS

AB21

VSS

AB48

VSS

AB61

VSS

AC10

VSS

AC14

VSS

AC46

VSS

AC6

VSS

AD17

VSS

AD20

VSS

AD4

VSS

AD61

VSS

AE13

VSS

AE8

VSS

AF1

VSS

AF17

VSS

AF21

VSS

AF47

VSS

AF48

VSS

AF50

VSS

AF51

VSS

AF52

VSS

AF53

VSS

AF55

VSS

AF56

VSS

AF58

VSS

AF59

VSS

AG10

VSS

AG14

VSS

AG18

VSS

AG47

VSS

AG52

VSS

AG61

VSS

AG7

VSS

AH4

VSS

AH58

VSS

AJ13

VSS

AJ16

VSS

AJ20

VSS

AJ22

VSS

AJ26

VSS

AJ30

VSS

AJ34

VSS

AJ38

VSS

AJ42

VSS

AJ45

VSS

AJ48

VSS

AJ7

VSS

AK1

VSS

AK52

VSS

AL10

VSS

AL13

VSS

AL17

VSS

AL21

VSS

AL25

VSS

AL28

VSS

AL33

VSS

AL36

VSS

AL40

VSS

AL43

VSS

AL47

VSS

AL61

VSS

AM13

VSS

AM20

VSS

AM22

VSS

AM26

VSS

AM30

VSS

AM34

VSS

SANDYBRIDGE-1-GP-U-NF

SANDYBRIDGE

VSS

4

8 OF 9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AM38 AM4 AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP10 AP51 AP55 AP7 AR13 AR17 AR21 AR41 AR48 AR61 AR7 AT14 AT19 AT36 AT4 AT45 AT52 AT58 AU1 AU11 AU28 AU32 AU51 AU7 AV17 AV21 AV22 AV34 AV40 AV48 AV55 AW13 AW43 AW61 AW7 AY14 AY19 AY30 AY36 AY4 AY41 AY45 AY49 AY55 AY58 AY9 BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53 BC13 BC5 BC57 BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56 BD8 BE5 BG13

http://hobi-elektronika.net

3

CPU1I

BG17

VSS

BG21

VSS

BG24

VSS

BG28

VSS

BG37

VSS

BG41

VSS

BG45

VSS

BG49

VSS

BG53

VSS

BG9

VSS

C29

VSS

C35

VSS

C40

VSS

D10

VSS

D14

VSS

D18

VSS

D22

VSS

D26

VSS

D29

VSS

D35

VSS

D4

VSS

D40

VSS

D43

VSS

D46

VSS

D50

VSS

D54

VSS

D58

VSS

D6

VSS

E25

VSS

E29

VSS

E3

VSS

E35

VSS

E40

VSS

F13

VSS

F15

VSS

F19

VSS

F29

VSS

F35

VSS

F40

VSS

F55

VSS

G48

VSS

G51

VSS

G6

VSS

G61

VSS

H10

VSS

H14

VSS

H17

VSS

H21

VSS

H4

VSS

H53

VSS

H58

VSS

J1

VSS

J49

VSS

J55

VSS

K11

VSS

K21

VSS

K51

VSS

K8

VSS

L16

VSS

L20

VSS

L22

VSS

L26

VSS

L30

VSS

L34

VSS

L38

VSS

L43

VSS

L48

VSS

L61

VSS

M11

VSS

M15

VSS

SANDYBRIDGE-1-GP-U-NF

SANDYBRIDGE

VSS

NCTF_VSS_NCTF#A5

NCTF_VSS_NCTF#A57

NCTF_VSS_NCTF#BC61

VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF

NCTF_VSS_NCTF#BG5

NCTF_VSS_NCTF#BG57

NCTF_VSS_NCTF#C3

NCTF

NCTF TEST PIN:

A5,A57,BC61,BG5,BG57,C3,E1,E61

NCTF TEST PIN:

A5,A57,BC61,BG5,BG57,C3,E1,E61

2

VSS_NCTF VSS_NCTF

NCTF_VSS_NCTF#E1

NCTF_VSS_NCTF#E61

9 OF 9

M4

VSS

M58

VSS

M6

VSS

N1

VSS

N17

VSS

N21

VSS

N25

VSS

N28

VSS

N33

VSS

N36

VSS

N40

VSS

N43

VSS

N47

VSS

N48

VSS

N51

VSS

N52

VSS

N56

VSS

N61

VSS

P14

VSS

P16

VSS

P18

VSS

P21

VSS

P58

VSS

P59

VSS

P9

VSS

R17

VSS

R20

VSS

R4

VSS

R46

VSS

T1

VSS

T47

VSS

T50

VSS

T51

VSS

T52

VSS

T53

VSS

T55

VSS

T56

VSS

U13

VSS

U8

VSS

V20

VSS

V61

VSS

W13

VSS

W15

VSS

W18

VSS

W21

VSS

W46

VSS

W8

VSS

Y4

VSS

Y47

VSS

Y58

VSS

Y59

VSS

TP_NCTP_A5

A5 A57 BC61 BD3 BD59 BE4 BE58 BG5 BG57 C3 C58 D59 E1 E61

TP_NCTP_BC61

TP_NCTP_BG5

TP_NCTP_E61

1

TP1001 TPAD14-GPTP1001 TPAD14-GP

1

TP1002 TPAD14-GPTP1002 TPAD14-GP

1

TP1003 TPAD14-GPTP1003 TPAD14-GP

1

TP1004 TPAD14-GPTP1004 TPAD14-GP

Add NCTF test pin X00 1011

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

CPU 7/7(VSS)

DB13 DIS

1

10 105Friday, November 26, 2010

X00

of

X00

5

D D

C C

4

3

2

1

B B

A A

5

4

http://hobi-elektronika.net

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Size Document Number Rev A3

A3

Friday, November 26, 2010

Date: Sheet

XDP

DB13 DIS

Taipei Hsien 221, Taiwan, R.O.C.

11 105

of

1

of

X00

5

D D

C C

4

3

2

1

B B

A A

5

4

http://hobi-elektronika.net

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

DB13 DIS

12 105Friday, November 26, 2010

of

1

of

X00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

http://hobi-elektronika.net

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

DB13 DIS

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

13 105Friday, November 26, 2010

of

X00

5

4

3

2

1

SSID = MEMORY

X00 1111 Change to 62.10024.E21

DM1

H=4.0mm

DM1

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P-135-GP

62.10024.E21

RAS#

CAS#

CS0# CS1#

CKE0 CKE1

CK0#

CK1#

EVENT#

VDDSPD

NC#1 NC#2

NC#/TEST

VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

NP1

NP2

110 113

WE#

115

114 121

73 74

101

CK0

103

102

CK1

104

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

200

SDA

202

SCL

198

199

SA0_DIM0

197

SA0

SA1_DIM0

201

SA1

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

1D5V_S3

M_A_RAS# (6) M_A_WE# (6) M_A_CAS# (6)

M_A_DIM0_CS#0 (6) M_A_DIM0_CS#1 (6)

M_A_DIM0_CKE0 (6) M_A_DIM0_CKE1 (6)

M_A_DIM0_CLK_DDR0 (6) M_A_DIM0_CLK_DDR#0 (6)

M_A_DIM0_CLK_DDR1 (6) M_A_DIM0_CLK_DDR#1 (6)

PCH_SMBDATA (15,20,65,66,79) PCH_SMBCLK (15,20,65,66,79)

TS#_DIMM0_1 (15)

Layout Note: Place these Caps near SO-DIMMA.

PART NUMBER

62.10017.W01

SCD1U10V2KX-5GP

12

C1401

X00 1116 remove M3 circuit

DDR_VREF_S3

D D

12

C1423

SCD1U10V2KX-5GP

12

C1424

C1425

DY

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

M_A_BS2(6)

M_A_BS0(6) M_A_BS1(6)

M_A_DQ[63:0](6)

M_A_A[15:0] (6)

X00 1116 remove M3 circuit

DDR_VREF_S3

12

C1411

C C

SCD1U10V2KX-5GP

0D75V_S0

12

B B

C1412

DY

SC2D2U10V3KX-1GP

Place these caps close to VTT1 and VTT2.

12

C1419

DY

SC1U6D3V2KX-GP

12

C1413

12

C1420

SC1U6D3V2KX-GP

X00 1123

SCD1U10V2KX-5GP

C1421

12

C1422

C1418

DY

SC1U6D3V2KX-GP

SC10U6D3V5KX-1GP

M_A_DQS#[7:0] (6)

M_A_DQS[7:0] (6)

M_A_DIM0_ODT0(6) M_A_DIM0_ODT1(6)

DDR_VREF_S3 DDR_VREF_S3

DDR3_DRAMRST#(15,37)

0D75V_S0

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

X00 1123

SA1_DIM0 SA0_DIM0

12

C1402

DY

1D5V_S3

SC2D2U10V3KX-1GP

Height TYPE

4.0mm

3D3V_S0

12

TC1401

DY

ST330U2VDM-4-GP

12

RN1401

2 3 1

SRN10KJ-5-GP

SODIMM A DECO UPLING

12

C1403

DY

SC10U6D3V5KX-1GP

12

C1415

C1414

SC1U6D3V2KX-GP

4

Note: If SA0 DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30

If SA0 DIM0 = 1, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA2 SO-DIMMA TS Address is 0x32

Thermal EVENT

TS#_DIMM0_1

12

C1405

C1404

DY

SC10U10V5ZY-1GP

SC10U6D3V5KX-1GP

12

C1416

C1417

SC1U6D3V2KX-GP

C1406

12

C1407

DY

SC10U6D3V5KX-1GP

R1403

1 2

C1408

DY

SC10U10V5ZY-1GP

10KR2J-3-GP

12

C1409

SC10U6D3V5KX-1GP

3D3V_S0

12

DY

C1410

SC10U6D3V5KX-1GP

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

Title

Size Document Number Rev

Date: Sheet

5

4

http://hobi-elektronika.net

3

2

Date: Sheet

Taipei Hsien 221, Taiw an, R.O.C.

DDR3-DIMM1 SOCKET1

DB13 DIS

1

of

14 105Friday, November 26, 2010

of

14 105Friday, November 26, 2010

of

14 105Friday, November 26, 2010

X00

5

SSID = MEMORY

M_B_A[15:0] (6)

C1522

SCD1U10V2KX-5GP

12

M_B_BS2(6)

M_B_BS0(6) M_B_BS1(6)

M_B_DQ[63:0](6)

SCD1U10V2KX-5GP

C1521

SC1U6D3V2KX-GP

M_B_DQS#[7:0] (6)

M_B_DQS[7:0] (6)

M_B_DIM0_ODT0(6) M_B_DIM0_ODT1(6)

DDR_VREF_S3 DDR_VREF_S3

DDR3_DRAMRST#(14,37)

0D75V_S0

D D

C C

B B

X00 1116 remove M3 circuit

DDR_VREF_S3

12

C1523

SCD1U10V2KX-5GP

12

DY

DDR_VREF_S3

12

C1515

SCD1U10V2KX-5GP

Place these caps close to VTT1 and VTT2.

12

C1518

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

X00 1116 remove M3 circuit

0D75V_S0

DY

C1519

12

C1524

DY

SC2D2U10V3KX-1GP

12

C1517

C1516

SC2D2U10V3KX-1GP

12

C1520

DY

SC1U6D3V2KX-GP

X00 1123

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

H=5.2mm

4

DM2

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12

119

A13

80

A14

78

A15

79

A16/BA2

109

BA0

108

BA1

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

116

ODT0

120

ODT1

126

VREF_CA

1

VREF_DQ

30

RESET#

203

VTT1

204

VTT2

DDR3-204P-108-GP

62.10017.X41

RAS#

CAS#

CS0#

CS1#

CKE0

CKE1

CK0#

CK1#

EVENT#

VDDSPD

NC#1

NC#2

NC#/TEST

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

VDD7

VDD8

VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18

3

NP1

NP2

110 113

WE#

115

114 121

73 74

101

CK0

103

102

CK1

104

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

200

SDA

202

SCL

198

199

SA0_DIM1

197

SA0

SA1_DIM1

201

SA1

77 122 125

75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124

2

VSS

3

VSS

8

VSS

9

VSS

13

VSS

14

VSS

19

VSS

20

VSS

25

VSS

26

VSS

31

VSS

32

VSS

37

VSS

38

VSS

43

VSS

44

VSS

48

VSS

49

VSS

54

VSS

55

VSS

60

VSS

61

VSS

65

VSS

66

VSS

71

VSS

72

VSS

127

VSS

128

VSS

133

VSS

134

VSS

138

VSS

139

VSS

144

VSS

145

VSS

150

VSS

151

VSS

155

VSS

156

VSS

161

VSS

162

VSS

167

VSS

168

VSS

172

VSS

173

VSS

178

VSS

179

VSS

184

VSS

185

VSS

189

VSS

190

VSS

195

VSS

196

VSS

205

VSS

206

VSS

1D5V_S3

M_B_RAS# (6) M_B_WE# (6) M_B_CAS# (6)

M_B_DIM0_CS#0 (6) M_B_DIM0_CS#1 (6)

M_B_DIM0_CKE0 (6) M_B_DIM0_CKE1 (6)

M_B_DIM0_CLK_DDR0 (6) M_B_DIM0_CLK_DDR#0 (6)

M_B_DIM0_CLK_DDR1 (6) M_B_DIM0_CLK_DDR#1 (6)

PCH_SMBDATA (14,20,65,66,79) PCH_SMBCLK (14,20,65,66,79)

TS#_DIMM0_1 (14)

PART NUMBER

20.F1207.204

12

C1501

C1502

DY

SCD1U10V2KX-5GP

SC2D2U10V3KX-1GP

Layout Note: Place these Caps near SO-DIMMB.

Height TYPE

4.0mm

3D3V_S0

1D5V_S3

3D3V_S0

12

SA1_DIM1

SA0_DIM1

12

SODIMM B DECO UPLING

12

DY

12

R1501

R1501 10KR2J-3-GP

10KR2J-3-GP

R1502

R1502 10KR2J-3-GP

10KR2J-3-GP

12

C1503

DY

SC10U10V5ZY-1GP

12

C1511

SCD1U10V2KX-5GP

Note: SO-DIMMB SPD Address is 0xA4 SO-DIMMB TS Address is 0x34

SO-DIMMB is pl aced farther from the Processor than SO-DIMM A

12

C1505

C1504

SC10U10V5ZY-1GP

SC10U6D3V5KX-1GP

12

C1512

C1513

SC1U6D3V2KX-GP

C1506

C1514

2

12

C1507

DY

SC10U6D3V5KX-1GP

SC1U6D3V2KX-GP

C1508

12

C1509

C1510

DY

SC10U10V5ZY-1GP

SC10U6D3V5KX-1GP

1

A A

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

Title

Size Document Number Rev

Date: Sheet

5

4

http://hobi-elektronika.net

3

2

Date: Sheet

Taipei Hsien 221, Taiw an, R.O.C.

DDR3-DIMM2 SOCKET2

DB13 DIS

1

of

15 105Friday, November 26, 2010

of

15 105Friday, November 26, 2010

of

15 105Friday, November 26, 2010

X00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

http://hobi-elektronika.net

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

DB13 DIS

16 105Friday, November 26, 2010

of

1

of

X00

5

3D3V_S0

RN1701

1 2 3

SRN2K2J-1-GP

D D

R1703

1 2

100KR2J-1-GP

4

L_CTRL_DATA L_CTRL_CLK

L_BKLT_EN

L_DDC_DATA(PAGE17): This signal is on the LVDS interface. This signal needs to be left NC if eDP is used for the local flat panel display

X00 1122

Place near PCH

Impedance:90 ohm

C C

X00 20101111

X00 1015

B B

12

R1701

R1701 2K37R2F-GP

2K37R2F-GP

Notes:

4

L_BKLT_EN(27)

LVDS_VDD_EN(49)

L_BKLT_CTRL(49)

LVDS_DDC_CLK_R(49) LVDS_DDC_DATA_R(49)

TP1701TPAD14-GP TP1701TPAD14-GP

RN1704

1 2 3

SRN0J-6-GP

LVDSA_CLK#(49)

LVDSA_CLK(49)

LVDSA_DATA0#(49)

LVDSA_DATA1#(49)

LVDSA_DATA2#(49)

LVDSA_DATA0(49)

LVDSA_DATA1(49)

LVDSA_DATA2(49)

LVDSB_CLK#(49)

LVDSB_CLK(49)

LVDSB_DATA0#(49)

LVDSB_DATA1#(49)

LVDSB_DATA2#(49)

LVDSB_DATA0(49)

LVDSB_DATA1(49)

LVDSB_DATA2(49)

SRN0J-6-GP

LVDS_DDC_CLK_R LVDS_DDC_DATA_R

L_CTRL_CLK L_CTRL_DATA

LVDS_IBG LVDS_VBG

1

LVDS_VREFH

4

LVDS_VREFL

X00 1015

DAC_IREF_R

12

R1702

1KR2D-1-GP

PCH1D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

COUGAR-GP-U2-NF

3

4 OF 10

DDPB_HPD

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_HPD

DDPC_0N

DDPC_0P

DDPC_1N

DDPC_1P

DDPC_2N

DDPC_2P

DDPC_3N

DDPC_3P

DDPD_HPD

DDPD_0N

DDPD_0P

DDPD_1N

DDPD_1P

DDPD_2N

DDPD_2P

DDPD_3N

DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

P38 M39

AT49 AT47 AT40

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

X00 1014

Cougar

Cougar Point

Point

LVDS

CRT

SDVO_TVCLKINN

SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN DDPB_AUXP

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN DDPD_AUXP

2

1103 Remove HDMI from PCH.

DP_PCH_DET_R

R5205 0R2J-2-GPR5205 0R2J-2-GP

1 2

1

PCH_DP_AUXN PCH_DP_AUXP

3D3V_S0

RN1702

1 2 3

SRN2K2J-1-GP

PCH_DP_AUXN (52) PCH_DP_AUXP (52) DP_PCH_DET (52)

PCH_DP_C0# (52) PCH_DP_C0 (52) PCH_DP_C1# (52) PCH_DP_C1 (52) PCH_DP_C2# (52) PCH_DP_C2 (52) PCH_DP_C3# (52) PCH_DP_C3 (52)

4

1K 0.5% 0402.

A A

5

4

http://hobi-elektronika.net

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet

PCH 1/9(LVDS/CRT/DDI)

Taipei Hsien 221, Taiwan, R.O.C.

DB13 DIS

of

17 105Friday, November 26, 2010

of

17 105Friday, November 26, 2010

of

17 105Friday, November 26, 2010

1

X00

5

4

3

2

1

SSID = PCH

RN1801

D D

3D3V_S0

INT_PIRQB# SATA_ODD_DA# INT_PIRQA#

R1801 4K7R2J-2-GP

A16 swap override Strap/Top-Block Swap Override jumper

PCI_GNT#3 Low = A16 swap

C C

GNT1#/GPIO51 BOOT BIOS LocationSATA1GP/GPIO19

0 0 LPC

0 1 Reserved

B B

A A

PLT_RST#7,31,32,35,65,66,71,83)

RN1801

1 2 3 4 5 6

SRN8K2J-2-GP-U

12

DY

override/Top-Block Swap Override enabled High = Default

R1802

1 2

DY

1KR2J-1-GP

R1803

1 2

DY

1KR2J-1-GP

BOOT BIOS Strap

11

12

R1816

DY

100KR2J-1-GP

5

10

INT_PIRQD#

9

HDD_FALL_INT1

8

INT_PIRQC#

7

USB30_SMI#

PCI_GNT3#

BBS_BIT1

BBS_BIT0

Reserved 01

SPI(Default)

R1807

1 2

0R2J-2-GP

12

C1801

DY

SC220P50V2KX-3GP

3D3V_S0

RN1803

DGPU_HOLD_RST# DGPU_PWR_EN#

BBS_BIT0 (21)

DGPU_HOLD_RST#(83)

DGPU_PWR_EN#(93)

TP1806TPAD14-GP TP1806TPAD14-GP

TP1807TPAD14-GP TP1807TPAD14-GP

DGPU_PWM_SELECT#

1

X00 1116 remove short pad

HDD_FALL_INT1(79)

SATA_ODD_DA#(56)

USB30_SMI#(35)

KB_LED_BL_DET(69)

20100923 X01 Modify: Change R1812,R1813,R1815,R1817 to 0R0402 short pad from 0ohm.

CLK_PCI_LPC(71) CLK_PCI_FB(20) CLK_PCI_KBC(27)

EC1802

1 2

DY

PCI_PLTRST#

4

R1804 22R2J-2-GPR1804 22R2J-2-GP

1 2

R1805 22R2J-2-GPR1805 22R2J-2-GP

1 2

R1806 22R2J-2-GPR1806 22R2J-2-GP

1 2

EC1801

1 2

DY

SC4D7P50V2CN-1GP

RN1803

1

4

2 3

SRN10KJ-5-GP

3D3V_S0

INT_PIRQA#

R1814

8K2R2J-3-GP

1 2

DGPU_HOLD_RST# DGPU_SELECT#

1

DGPU_PWR_EN#

TP1801TPAD14-GP TP1801TPAD14-GP

TP1802TPAD14-GP TP1802TPAD14-GP

INT_PIRQB# INT_PIRQC# INT_PIRQD#

BBS_BIT1

PCI_GNT3#

1

PCI_PME#

1

PCI_PLTRST#

CLK_PCI_LPC_R CLK_PCI_FB_R CLK_PCI_KBC_R

KBC CLK EMI

SC4D7P50V2CN-1GP

20100908 X01 Modify: Add R1818 10K PL on FFS_INT2_R(GPIO14)

R1818 10KR2J-3-GPR1818 10KR2J-3-GP

1 2

FFS_INT2_R

3D3V_S5

USB_OC#2_3

http://hobi-elektronika.net

PCH1E

Cougar

BG26

BJ26

BH25

BJ16 BG16 AH38 AH37 AK43 AK45

C18 N30

AH12

AM4 AM5

AB46 AB45

M20 AY16 BG46

BE28 BC30 BE32

BJ32 BC28 BE30

BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28

AW30

Y13 K24 L24

B21

K40 K38 H38 G38

C46 C44 E40

D47 E42 F46

G42 G40 C42 D44

K10

H49 H43

K42 H40

H3

C6

J48

Cougar

TP1

Point

TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20

TP21 TP22 TP23 TP24

TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP35 TP36 TP37 TP38 TP39 TP40

PIRQA# PIRQB# PIRQC# PIRQD#

REQ1#/GPIO50 REQ2#/GPIO52 REQ3#/GPIO54

GNT1#/GPIO51 GNT2#/GPIO53 GNT3#/GPIO55

PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO 5

PME#

PLTRST#

CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4

COUGAR-GP-U2-NF

OC[3:0]# for Device 29 (Ports 0-7) OC[7:4]# for Device 26 (Ports 8-13)

RN1802

1 2 3 4 5 6

SRN8K2J-2-GP-U

3

RSVD

PCI

NVRAM

USB

10 9 8 7

USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

USBRBIAS#

USBRBIAS

OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43

OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14

USB_OC#12_13 USB_OC#8_9USB_OC#6_7 USB_OC#10_11USB_OC#0_1 USB_OC#4_5

5 OF 10

RSVD RSVD RSVD RSVD

RSVD RSVD

RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

RSVD

DF_TVS

RSVD

RSVD RSVD

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P

AY7 AV7 AU3 BG4

AT10 BC8

AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6

NV_ALE

AV5

NV_CLE

AY1

NV_RCOMP

AV10

AT8

AY5 BA2

AT12

USB Ext. port 1 (HS)

BF3

External debug port use on Huron river platform

C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

USB_RBIAS

C33

B33

USB_OC#0_1

A14

USB_OC#2_3

K20

USB_OC#4_5

B17

USB_OC#6_7

C16

USB_OC#8_9

L16

USB_OC#10_11

A16

USB_OC#12_13

D14 C14

3D3V_S5

TP1803 TPAD14-GPTP1803 TPAD14-GP

1

X00 1027

USB_PN4 (66) USB_PP4 (66)

USB_PN11 (65) USB_PP11 (65) USB_PN12 (49) USB_PP12 (49)

1 2

R1811

R1811 22D6R2F-L1-GP

22D6R2F-L1-GP

X00 1027

FFS_INT2_R (79)

2

Title

Size Document Number Rev

Date: Sheet

NV_CLE

DMI & FDI Termination Voltage

NV_CLE

Danbury Technology: Disabled when Low. Enable when High.

USB Table

Pair

X

0

X

1

X

2

X

3

Mini Card2 (WWAN)

4

X

5

X

6

X

7

X

8

X

9

X

10

Mini Card1 (WLAN)

11

CAMERA

12

X

13

PCH 2/9(PCI/USB/NVRAM)

DB13 DIS

1D8V_S0

12

R1808

R1808 2K2R2J-2-GP

2K2R2J-2-GP

R1809

1 2

1KR2J-1-GP

H_SNB_IVB# (5)

Set to Vss when LOW

Set to Vcc when HIGH

1D8V_S0

12

R1810

R1810 1KR2J-1-GP

1KR2J-1-GP

DY

NV_ALE

Device

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

of

18 105Friday, November 26, 2010

of

18 105Friday, November 26, 2010

of

18 105Friday, November 26, 2010

1

X00

5

4

3

2

1

SSID = PCH

Signal Routing Guideline:

D D

DMI_ZCOMP keep W=4 mils and routing length less than 500 mils. DMI_IRCOMP keep W=4 mils and routing length less than 500 mils.

1D05V_VTT

R1901 49D9R2F-GPR1901 49D9R2F-GP

R1902 750R2F-GPR1902 750R2F-GP

SYS_PWROK

R1926

1 2

10KR2J-3-GP

C C

S0_PWR_GOOD after PM_SLP_S3# delay 200 ms

B B

A A

1 2

100KR2J-1-GP

PM_DRAM_PWRGD(5,37)

SUS_PWR_ACK(27)

AC_PRESENT(27,86)

R1926

DY

XDP_DBRESET#(5 )

SYS_PWROK(36)

X00 1116 remove short pad

S0_PWR_GOOD(27,36)

PM_PWRBTN#(27)

3D3V_S5

R1904

S0_PWR_GOOD

SUS_PWR_ACK

5

RN1901

8 7 6

SRN10KJ-6-GP

R1921

100KR2J-1-GP

R1922 10KR2J-3-GP

R1922 10KR2J-3-GP R1920 10KR2J-3-GP

R1920 10KR2J-3-GP

DY

DY DY

DY

R1908

10KR2J-3-GP

DMI_RXN[3:0](4)

DMI_RXP[3:0](4)

DMI_TXN[3:0](4)

DMI_TXP[3:0](4)

DMI_RXN0(4) DMI_RXN1(4) DMI_RXN2(4) DMI_RXN3(4)

DMI_RXP0(4) DMI_RXP1(4) DMI_RXP2(4) DMI_RXP3(4)

DMI_TXN0(4) DMI_TXN1(4) DMI_TXN2(4) DMI_TXN3(4)

DMI_TXP0(4) DMI_TXP1(4) DMI_TXP2(4) DMI_TXP3(4)

1 2

20100923 X01 Modify: Change R1903,R1906,R1924,R1925 to 0R0402 short pad from 0ohm.

DMI_COMP_R

RBIAS_CPY

X00 1116 remove short pad

X00 1123

RSMRST#_KBC

BATLOW#

PM_RI#

20100921 X01 Modify: Move PCH_WAKE# to RN1901 pin3 Change R1921 to 100k ohm PH on AC_PRESENT.

BATLOW#

1

PM_RI#

2

PCH_WAKE#

3

SUS_PWR_ACK

45

AC_PRESENT

12

12 12

12

PM_PWRBTN# PM_SLP_LAN#

RSMRST#_KBC

X00 1123

PCH1C

BC24

DMI0RXN

Cougar

BE20 BG18 BG20

BE24 BC20

BJ18 BJ20

AW24 AW20

BB18 AV18

AY24 AY20 AY18 AU18

BJ24

BG25

BH21

C12

K3

P12

L22

X00 1116 remove short pad

L10

B13

C21

K16

E20

H20

E10

A10

COUGAR-GP-U2-NF

4

Cougar

DMI1RXN

Point

DMI2RXN DMI3RXN

DMI0RXP DMI1RXP DMI2RXP DMI3RXP

DMI0TXN DMI1TXN DMI2TXN DMI3TXN

DMI0TXP DMI1TXP DMI2TXP DMI3TXP

DMI_ZCOMP

DMI_IRCOMP

DMI2RBIAS

SUSACK#

SYS_RESET#

SYS_PWROK

PWROK

APWROK

DRAMPWROK

RSMRST#

SUSWARN#/SUSPW RDNACK/GPIO30

PWRBTN#

ACPRESENT/GPIO31

BATLOW#/GPI O72

RI#

3 OF 10

BJ14

FDI_RXN0

AY14

FDI_RXN1

BE14

FDI_RXN2

BH13

FDI_RXN3

BC12

FDI_RXN4

BJ12

FDI_RXN5

BG10

FDI_RXN6

BG9

FDI_RXN7

BG14

FDI_RXP0

BB14

FDI_RXP1

BF14

FDI_RXP2

BG13

FDI_RXP3

BE12

FDI_RXP4

BG12

FDI_RXP5

BJ10

DMI

System Power Management

FDI_RXP6

FDI

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

CLKRUN#/GPIO32

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

SLP_LAN#/GPIO29

http://hobi-elektronika.net

FDI_RXP7

FDI_INT

DPWROK

WAKE#

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

BH9

AW16

AV12

BC10

AV14

BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

DSWODVREN

PM_SUS_STAT#

PCH_SUSCLK_KBC_R

PM_SLP_S5#

PM_SLP_A#

PM_SLP_SUS#

H_PM_SYNC

PM_SLP_LAN#

3

FDI_TXN[7:0] (4) FDI_TXP[7:0] (4)

FDI_TXN0 (4) FDI_TXN1 (4) FDI_TXN2 (4) FDI_TXN3 (4) FDI_TXN4 (4) FDI_TXN5 (4) FDI_TXN6 (4) FDI_TXN7 (4)

FDI_TXP0 (4) FDI_TXP1 (4) FDI_TXP2 (4) FDI_TXP3 (4) FDI_TXP4 (4) FDI_TXP5 (4) FDI_TXP6 (4) FDI_TXP7 (4)

FDI_INT (4)

FDI_FSYNC0 (4)

FDI_FSYNC1 (4)

FDI_LSYNC0 (4)

FDI_LSYNC1 (4)

20100923 X01 Modify: Change R1910,R1912,R1913 to 0R0402 short pad from 0ohm.

PCH_WAKE# (27)

TP1901 TPAD14-GPTP1901 TPAD14-GP

1

TP1902 TPAD14-GPTP1902 TPAD14-GP

1

TP1903TPAD14-GPTP1903TPAD14-GP

1

TP1904TPAD14-GPTP1904TPAD14-GP

PM_CLKRUN# (27)

R1903

0R2J-2-GP

H_PM_SYNC (5)

For platforms not supporting Deep S4/S5

1.VccSUS3_3 and VccDSW3_3 will rise at the same time (connected on board)

2.DPWROK and RSMRST# will rise at the same time (connected on board)

3.SLP_SUS# and SUSACK# are left as ‘no connect’

4.SUSWARN# used as SUSPWRDNACK/GPIO30

X00 1123

RSMRST#_KBC (27)

X00 1123 close to PCH

12

X00 1123

PCH_SUSCLK_KBC

EC1901

1 2

DY

SC4D7P50V2CN-1GP

PCH_SUSCLK_KBC (27)

PM_SLP_S4# (27,46)

PM_SLP_S3# (27,36,37,47)

2

DSWODVREN - On Die DSW VR Enable

HIGH Enabled (DEFAULT)

LOW Disabled

R1917 330KR2J-L1-GPR1917 330KR2J-L1-GP

1 2

DSWODVREN

PM_CLKRUN#

Title

Size Document Number Rev

Date: Sheet

R1918 330KR2J-L1-GP

1 2

DY

R1919 8K2R2J-3-GPR1919 8K2R2J-3-GP

1 2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

PCH 3/9(DM I/FDI/PM)

DB13 DIS

19 105Friday, November 26, 2010

1

RTC_AUX_S5

3D3V_S0

of

X00

5

SSID = PCH

X00 1118 remove 0ohm

D D

C C

::$1&/.

:/$1&/.

&$5'&/.

B B

86%&/.

A A

PCIE_RXN2(31)

PCIE_RXP2(31) PCIE_TXN2(31) PCIE_TXP2(31)

PCIE_RXN3(66)

PCIE_RXP3(66) PCIE_TXN3(66) PCIE_TXP3(66)

PCIE_RXN4(65)

PCIE_RXP4(65) PCIE_TXN4(65) PCIE_TXP4(65)

PCIE_RXN5(35)

PCIE_RXP5(35) PCIE_TXN5(35) PCIE_TXP5(35)

PCIE_RXN6(32)

PCIE_RXP6(32) PCIE_TXN6(32) PCIE_TXP6(32)

C2001 SCD1U10V2KX-5GPC2001 SCD1U10V2KX-5GP

1 2

C2002 SCD1U10V2KX-5GPC2002 SCD1U10V2KX-5GP

1 2

C2003 SCD1U10V2KX-5GPC2003 SCD1U10V2KX-5GP

1 2

C2004 SCD1U10V2KX-5GPC2004 SCD1U10V2KX-5GP

1 2

C2005 SCD1U10V2KX-5GPC2005 SCD1U10V2KX-5GP

1 2

C2006 SCD1U10V2KX-5GPC2006 SCD1U10V2KX-5GP

1 2

C2009 SCD1U10V2KX-5GPC2009 SCD1U10V2KX-5GP

1 2

C2010 SCD1U10V2KX-5GPC2010 SCD1U10V2KX-5GP

1 2

C2011 SCD1U10V2KX-5GPC2011 SCD1U10V2KX-5GP

1 2

C2012 SCD1U10V2KX-5GPC2012 SCD1U10V2KX-5GP

1 2

PCIE_TXN2_C PCIE_TXP2_C

PCIE_TXN3_C PCIE_TXP3_C

PCIE_TXN4_C PCIE_TXP4_C

PCIE_TXN5_C PCIE_TXP5_C

PCIE_TXN6_C PCIE_TXP6_C

X00 1118

X00 1116 remove 0ohm

CLK_PCIE_WWAN#(66) CLK_PCIE_WWAN(66)

CLK_PCIE_WWAN_REQ#(66)

CLK_PCIE_WLAN#(65) CLK_PCIE_WLAN(65)

CLK_PCIE_WLAN_REQ#(65)

CLK_PCIE_CARD#(32) CLK_PCIE_CARD(32)

X00 1018

/$1&/.

3D3V_S0

PCIECLKRQ1# and PCIECLKRQ2# Support S0 power only

PCIE_CLK_CARD_REQ#(32)

CLK_PCIE_LAN#(31) CLK_PCIE_LAN(31)

PCIE_CLK_LAN_REQ#(31)

CLK_PCIE_USB3#(35)

RN2018

1 2 3

SRN10KJ-5-GP

CLK_PCIE_USB3(35)

USB3_PEGB_CLKREQ#(35)

X00 1018

PCIE_CLK_CARD_REQ#

4

CLK_PCIE_WLAN_REQ#

PCIE_CLK_REQ5#

PEG_B_CLKRQ#

PCIE_CLK_REQ6#

CLK_PCIE_NEW_REQ#

ITPXDP_N

1

TP2005TPAD14-GP TP2005TPAD14-GP TP2006TPAD14-GP TP2006TPAD14-GP

ITPXDP_P

1

Remove the XDP connector for space saving 6/28

5

4

PCH1B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0#/GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1#/GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2#/GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3#/GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4#/GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5#/GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ#/GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6#/GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7#/GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

COUGAR-GP-U2-NF

4

3

2 OF 10

Cougar

Cougar Point

Point

LAN

WWAN/WLAN

WLAN

USB3.0

PCI-E*

Card Reader

Dock

SMBALERT#/GPIO11

SMBDATA

SML0ALERT#/GPIO60

SMBUSController

SML1ALERT#/PCHHOT#/GPI O74

Link

SML0DATA

SML1CLK/GPIO58

SML1DATA/GPIO75

CL_DATA1

CL_RST1#

SMBCLK

SML0CLK

CL_CLK1

EC_SWI#

E12

SMB_CLK

H14

SMB_DATA

C9

DRAMRST_CNTRL_PCH

A12

SML0_CLK

C8

SML0_DATA

G12

PCH_GPIO74

C13

SML1_CLK

E14

SML1_DATA

M16

CL_CLK

M7

CL_DATA

T11

CL_RST#

P10

1

TP2001 TPAD14-GPTP2001 TPAD14-GP

1

TP2002 TPAD14-GPTP2002 TPAD14-GP

1

TP2003 TPAD14-GPTP2003 TPAD14-GP

NEW CARD

For DIS_PX mode or MXM mode.

CLK_BUF_EXP_N CLK_BUF_EXP_P

CLK_BUF_CPYCLK_N CLK_BUF_CPYCLK_P

CLK_BUF_DOT96_N CLK_BUF_DOT96_P

CLK_BUF_CKSSCD_N CLK_BUF_CKSSCD_P

CLK_BUF_REF14

CLK_PCI_FB

XTAL25_IN XTAL25_OUT

R2007

XCLK_RCOMP

1 2

90D9R2F-1-GP

CLK_48_USB30

DGPU_PRSNT#

1 2

XTAL25_IN

M10

AB37 AB38

AV22 AU22

AM12 AM13

BF18 BE18

BJ30 BG30

G24 E24

AK7 AK5

K45

H45

V47 V49

Y47

K43

F47

H47

K49

3

PEG_A_CLKRQ#/GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_PCILOOPBACK

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

FLEX CLOCKS

CLKOUT_DMI_P

CLKOUT_DP_N

CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_SATA_N CLKIN_SATA_P

REFCLK14IN

XTAL25_OUT

XCLK_RCOMP

CLOCKS

– Prioritize 27/14/24/48/25-MHz FLEX on FLEX1 and FLEX3 – Do not configure 27/14/24/48/25-MHz FLEX clock on FLEX0 and FLEX2 if more than 2 PCI clocks + PCI loopback are routed.

http://hobi-elektronika.net

2

1120

20100830 X01 Modify: R2004 dummy field set to for UMA only. R2005 dummy field set to for MUXLESS only.

EC_SWI# (27)

DRAMRST_CNTRL_PCH (37)

SML1_CLK (27,86)

SML1_DATA (27,86)

X00 1116 remove 0ohm

RN2008

2 3 1

SRN10KJ-5-GP

PL 10K FOR Integrated CLOCK GEN mode.

CLK_BUF_CKSSCD_N

CLK_PCI_FB (18)

+VCCDIFFCLKN

R2016

R2016 22R2J-2-GP

22R2J-2-GP

CLK_BUF_CKSSCD_P

CLK_BUF_EXP_N CLK_BUF_EXP_P

CLK_BUF_REF14

CLK_PCH_48M (97)

PEG_CLKREQ#

SMB_DATA

SMB_CLK

PEG_CLKREQ# (83)

CLK_PCIE_VGA# (83) CLK_PCIE_VGA (83)

CLK_EXP_N (5) CLK_EXP_P (5)

4

CLK_BUF_DOT96_N CLK_BUF_DOT96_P

RN2020 SRN10KJ-5-GPRN2020 SRN10KJ-5-GP

1 2 3

2 3 1

SRN10KJ-5-GP

RN2019 SRN10KJ-5-GPRN2019 SRN10KJ-5-GP

1 2 3

need very close to PCH

For RTS5138

2

3D3V_S5

1120

RN2021

R2008

1 2

10KR2J-3-GP

DY

4

1

12

R2004

R2004 10KR2J-3-GP

10KR2J-3-GP

12

R2005

R2005 10KR2J-3-GP

10KR2J-3-GP

3D3V_S0

RN2007

2 3 1

SRN2K2J-1-GP

2nd = 84.DM601.03F

84.2N702.A3F

2N7002KDW-GP

6

5

Q2001

XTAL25_IN

XTAL25_OUT

3D3V_S0 3D3V_S0

12

R2012

DY

12

R2010

Title

Size Document Number Rev

Date: Sheet

SMB_CLK SMB_DATA

SML0_DATA SML0_CLK

SML1_CLK SML1_DATA

PCIE_CLK_REQ6# PCH_GPIO74

DRAMRST_CNTRL_PCH

4

1

2

34

R2006

R2006 1M1R2J-GP

1M1R2J-GP

1 2

X00 1124

12

R2013

UMA_DIS# DGPU_PRSNT#

10KR2J-3-GP

12

R2011

DY

10KR2J-3-GP

3D3V_S5

PCH 4/9(PCI-E/SMBUS/CLOCK/CL)

DB13 DIS

4

2 3 1

1 2 3

R2009

1 2

1KR2J-1-GP

PCH_SMBDATA (14,15,65,66,79)

PCH_SMBCLK (14,15,65,66,79)

SC12P50V2JN-3GP

X2001

X2001 XTAL-25MHZ-102-GP

XTAL-25MHZ-102-GP

1 2

82.30020.851

2nd = 82.30020.791

SC12P50V2JN-3GP

UMA_DISCRETE# UMA: 1 1 DIS :0 1 SG(PX) : 0 0 ATI(Muxless) : 1 0

UMA_DIS# (22)

RN2001

1

8

2

7

3

6

4 5

SRN10KJ-6-GP

SRN10KJ-6-GP RN2002

RN2002

1

8

2

7

3

6

4 5

SRN10KJ-6-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

1

3D3V_S5

RN2003

1

SRN2K2J-1-GP

23

RN2004

23

SRN2K2J-1-GP

1

RN2005

RN2005 SRN2K2J-1-GP

SRN2K2J-1-GP

4

RN2006

4

SRN10KJ-5-GP

C2008

12

C2007

12

CLK_PCIE_WWAN_REQ#

PCIE_CLK_LAN_REQ# USB3_PEGB_CLKREQ#

EC_SWI# PCIE_CLK_REQ5# CLK_PCIE_NEW_REQ# PEG_B_CLKRQ#

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20 105Friday, November 26, 2010

of

20 105Friday, November 26, 2010

of

20 105Friday, November 26, 2010

X00

5

4

3

2

1

SSID = PCH

20100818 Sourcer suggest: Change X2101 as below.

RTC_X1

1 2

R2101 10MR2J-L-GPR2101 10MR2J-L-GP

D D

12

C2101

SC15P50V2JN-2-GP

C C

+3VS_+1.5VS_HDA_IO

3D3V_S0

+3VS_+1.5VS_HDA_IO

B B

This signal has a weak internal pull down. On Die PLL VR is supplied by 1.5V when sampled high, 1.8 V when sampled low. Needs to be pulled High for Huron River platform. co-operate with R2310

X2101

1 4

X-32D768KHZ-67-GP

82.30001.A81

2nd = 82.30001.691

3rd = 82.30001.861

HDA_CODEC_SYNC(29) HDA_CODEC_SDOUT(29)

HDA_CODEC_RST#(29) HDA_CODEC_BITCLK(29)

DY

R2102 1KR2J-1-GP

1 2

NO REBOOT STRAP

DY

R2106 1KR2J-1-GP

1 2

32

1 2

PLL ODVR VOLTAGE

HDA_SYNC

RUN_ENABLE

A A

1 2

Low = 1.8V (Default) High = 1.5V

2N7002K-2-GP

G

S

Q2101

R2117

84.2N702.J31

100KR2J-1-GP

2ND = 84.2N702.031

20100906 X01 Modify: Change all of single 2N7002 to 84.2N702.J31 from 84.2N702.D31 due to 84.2N702.D31 will EOL.

RTC_X2

12

C2102

C2102 SC15P50V2JN-2-GP

SC15P50V2JN-2-GP

1 2 3

Flash Descriptor Security Overide

HDA_SDO UT

HDA_SDOUT

HDA_SPKR

R2103 1KR2J-1-GPR2103 1KR2J-1-GP

D

5

12

DY

12

RN2102

4

SRN33J-5-GP-U

No Reboot Strap

HDA_SYNC

33R2J-2-GP

RTC_AUX_S5

HDA_SYNC

R212233R2J-2-GP

HDA_SDOUT

R212333R2J-2-GP R212333R2J-2-GP

HDA_RST# HDA_BITCLK

Low = Default High = Enable

Low = Default High = No Reboot

R2124

HDA_SYNCHDA_SYNC_R

12

X00 1123

RN2115

1 2 3

SRN20KJ-GP-U

SC1U6D3V2KX-GP

4

C2104

12

C2103

C2103 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

21

G2101

12

GAP-OPEN

INTVRMEN- Integrated SUS

1.05V VRM Enable High - Enable internal VRs Low - Enable external VRs

RTC_AUX_S5

HDA_SPKR(29)

HDA_SDIN0(29)

1M1R2J-GP

R2104

1 2

R2105

330KR2F-L-GP

RTC_X1

RTC_X2

RTC_RST#

SRTC_RST#

SM_INTRUDER#

12

PCH_INTVRMEN

HDA_BITCLK

HDA_SYNC

HDA_RST#

Notes: ME_UNLOCK (HDA_SDO) connect to EC. Make sure EC drive this pin "low" all the time.

R2107 1KR2J-1-GPR2107 1KR2J-1-GP

ME_UNLOCK(27)

20100721 Modify: Remove TP2105 and change PCH_GPIO33 to CE.

HDA_SYNC: This strap is sampled on rising edge of RSMRST# and is used to sample 1.5V VccVRM supply mode. 1K external pull-up resistor is required on this signal on the board. Signal may have leakage paths via powered off devices (Audio Codec) and hence contend with the external pull-up. A blocking FET is recommended in such a case to isolate HDA_SYNC from the Audio Codec device until after the Strap sampling is complete.

HDA_CODEC_BITCLK

EC2102

1 2

DY

SC4D7P50V2CN-1GP

HDA_CODEC_SDOUT

1 2

DY

4

EC2103

SC4D7P50V2CN-1GP

1 2

SPI_CLK_R(27,60)

SPI_CS0#_R(27,60)

SPI_SI_R(27,60)

SPI_SO_R(27,60)

SPI_CS0#_RHDA_CODEC_SYNC

EC2101

1 2

DY

HDA_SDOUT

CE(49)

TP2101TPAD14-GP TP2101TPAD14-GP

TP2102TPAD14-GP TP2102TPAD14-GP

TP2103TPAD14-GP TP2103TPAD14-GP

TP2104TPAD14-GP TP2104TPAD14-GP

1 2

R2108 33R2J-2-GPR2108 33R2J-2-GP

1 2

R2109 33R2J-2-GPR2109 33R2J-2-GP

1 2

R2110 33R2J-2-GPR2110 33R2J-2-GP

SC4D7P50V2CN-1GP

http://hobi-elektronika.net

PCH_JTAG_TCK_BUF

1

PCH_JTAG_TMS

1

PCH_JTAG_TDI

1

PCH_JTAG_TDO

1

PCH_SPI_CLK

PCH_SPI_CS0#

PCH_SPI_SI

1 OF 10

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

LPC

FWH4/LFRAME#

LDRQ1#/GPIO23

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1RXN SATA1RXP

SATA 6G

SATA1TXN SATA1TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN

SATA

SATA4TXP

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#

SATA0GP/GPIO21

SATA1GP/GPIO19

3D3V_S0

8 7 6

1 OF 10

LDRQ0#

SERIRQ

C38 A38 B37 C37

D36

E36 K36

V5

AM3 AM1 AP7 AP5

AM10 AM8 AP11 AP10

AD7 AD5 AH5 AH4

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11

Y10

AB12

AB13

AH1

P3

V14

P1

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

SATA_DET#0

BBS_BIT0

PCH1A

A20

C20

D20

G22

K22

C17

N34

L34

T10

K34

E34

G34

C34

A34

A36

CE

PSW_CLR#(22)

S_GPIO(22)

C36

N32

J3

H7

K5

H1

T3

Y14

T1

V4

U3

COUGAR-GP-U2-NF

Cougar

RTCX1

Point

RTCX2

RTCRST#

SRTCRST#

INTRUDER#

INTVRMEN

HDA_BCLK

HDA_SYNC

SPKR

HDA_RST#

HDA_SDIN0

HDA_SDIN1

HDA_SDIN2

HDA_SDIN3

HDA_SDO

HDA_DOCK_EN#/GPIO33

HDA_DOCK_RST#/GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

SPI_CLK

SPI_CS0#

SPI_CS1#

SPI_MOSI

SPI_MISO

20100917 X01: Add RN2104 10K instead of R2111 10K. Move EC_SCI#,DBC_EN to RN2201. Remove RN2202. Change RN2103 to 10k array resistor to follow the standard schematics. Move S_GPIO to RN2103. Move PSW_CLR# to RN2104. 20100921 X01: Swap SATA_DET#0 and INT_SERIRQ.

SATA_DET#0 INT_SERIRQ

RTCIHDA

JTAG

SPI

RN2103

1 2 3 4 5

SRN10KJ-6-GP

X00 1123

3

2

LPC_AD[0..3]

SATA_COMP

SATA3_COMP

RBIAS_SATA3

LPC_AD[0..3] (27,71)

LPC_FRAME# (27,71)

KB_DET# (69)

INT_SERIRQ (27)

SATA_RXN0 (56) SATA_RXP0 (56) SATA_TXN0 (56) SATA_TXP0 (56)

HDD1

HDD2

SATA_RXN4 (56) SATA_RXP4 (56) SATA_TXN4 (56) SATA_TXP4 (56)

1D05V_VTT

R2112 37D4R2F-GPR2112 37D4R2F-GP

1 2

R2113 49D9R2F-GPR2113 49D9R2F-GP

1 2

R2114 750R2F-GPR2114 750R2F-GP

1 2

BBS_BIT0 (18)

Title

PCH 5/9(SPI/RTC/LPC/SATA/IHDA)

Size Document Number Rev

Date: Sheet

1D05V_VTT

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

DB13 DIS

1

ODD

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21 105Friday, November 26, 2010

of

21 105Friday, November 26, 2010

of

21 105Friday, November 26, 2010

X00

5

3D3V_S0

R2202

1 2

100KR2J-1-GP

3D3V_S0

RN2203

1

4

D D

GPIO27 has a weak[20K] internal pull up. To enable on-die PLL Voltage regurator, should not place external pull down.

C C

SRN10KJ-5-GP

3D3V_S0

R2220

1 2

10KR2J-3-GP

PCH_TEMP_ALERT#

MFG_MODE

X00 1123

EC_SCI# DGPU_HPD_INTR# FP_DET# EC_SMI#

DBC_EN

2 3

PCH_GPIO48

R2222 10KR2J-3-GPR2222 10KR2J-3-GP

1 2

R2223 10KR2J-3-GPR2223 10KR2J-3-GP

1 2

RN2201

1 2 3 4 5

SRN10KJ-6-GP

SRN10KJ-6-GP R2214 10KR2J-3-GP

R2214 10KR2J-3-GP

1 2

DY

20100923 X01: Separate DBC_EN from RN2201 to R2214, un-stuff R2214.

X00 1122

RTC_DET# USB3_PWR_ON

PCH_GPIO15

3G_EN

B B

A A

4

1 2

5

SATA_ODD_PRSNT#

H_A20GATE

H_RCIN#

20100908 X01 Modify: Change FFS_INT2_R from PCH GPIO48 to GPIO14 Keep PCH_GPIO15 PH R2201,PCH_GPIO48 PH R2220. 20100928 X01 modify: Change R2220 to 10k.

3D3V_S0

8 7 6

3D3V_S5

RN2204

1 23

SRN10KJ-5-GP

R2201

1KR2J-1-GP

R2221

10KR2J-3-GP

20100908 X01: Add R2201 PH for PCH_GPIO15.

Note: For PCH debug with XDP, need to NO STUFF R2218

20100908 X01: Add R2201 PH for PCH_GPIO15.

X00 1120

PSW_CLR#(21)

4

SSID = PCH

S_GPIO GPIO0_R

R2218

1 2

R2213 0R0402-PADR2213 0R0402-PAD

TP2203

1

PSW_CLR#

1

1 2

100R2J-2-GP

EC_SMI#

DGPU_HPD_INTR# VRAM_SIZE1

EC_SCI#

ICC_EN#

PCH_GPIO15

PCH_GPIO16

DGPU_PWROK

DBC_EN

3G_EN

PCH_GPIO27

PLL_ODVR_EN

FP_DET#

DMI_OVRVLTG

FDI_OVRVLTG

MFG_MODE

GFX_CRB_DET

PCH_GPIO48

PCH_TEMP_ALERT#

PCH_NCTF_1

PCH_NCTF_2

PCH_NCTF_3

PCH_NCTF_4

S_GPIO(21)

EC_SMI#(27)

EC_SCI#(27)

X00 1122

RTC_DET#(60)

SATA_ODD_PRSNT#(56)

DGPU_PWROK(83,87,92,93)

DBC_EN(49)

3G_EN(66)

TPAD14-GP

GAP-OPEN

21

G2201

USB3_PWR_ON(35,62)

TP2206TPAD14-GP TP2206TPAD14-GP

TP2207TPAD14-GP TP2207TPAD14-GP

TP2208TPAD14-GP TP2208TPAD14-GP

TP2209TPAD14-GP TP2209TPAD14-GP

[VRAM_SIZE1:VRAM_SIZE2] LL=512M / HL=1G / LH=2G

4

3

PCH1F

T7

BMBUSY#/GPIO0

A42

TACH1/GPIO1

H36

TACH2/GPIO6

E38

TACH3/GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL/G PIO12

G2

GPIO15

U2

SATA4GP/GPIO16

D40

TACH0/GPIO17

T5

SCLOCK/GPIO22

E8

GPIO24/MEM_LED

E16

GPIO27

P8

GPIO28

K1

STP_PCI#/GPIO34

K4

GPIO35

V8

SATA2GP/GPIO36

M5

SATA3GP/GPIO37

N2

SLOAD/GPIO38

M3

SDATAOUT0/GPIO39

V13

SDATAOUT1/GPIO48

V3

SATA5GP/GPIO49

D6

GPIO57

A4

NCTF_VSS#A4

A44

NCTF_VSS#A44

A45

NCTF_VSS#A45

A46

NCTF_VSS#A46

A5

NCTF_VSS#A5

A6

NCTF_VSS#A6

B3

NCTF_VSS#B3

B47

NCTF_VSS#B47

BD1

NCTF_VSS#BD1

BD49

NCTF_VSS#BD49

BE1

NCTF_VSS#BE1

BE49

NCTF_VSS#BE49

BF1

NCTF_VSS#BF1

BF49

NCTF_VSS#BF49

COUGAR-GP-U2-NF

Cougar

Cougar Point

Point

NCTF TEST PIN:

A4,A44,A45,A46,A5,A6,B3,B47,BD1,BD49,BE1,BE49,BF1,BF49

BG2,BG48,BH3,BH47,BJ4,BJ44,BJ45,BJ46,BJ5,BJ6,C2,C48

TACH4/GPIO68

TACH5/GPIO69

TACH6/GPIO70

TACH7/GPIO71

PROCPWRGD

GPIO

CPU/MISC

NCTF_VSS#BG2

NCTF_VSS#BG48

NCTF_VSS#BH3

NCTF_VSS#BH47

NCTF_VSS#BJ4

NCTF_VSS#BJ44

NCTF_VSS#BJ45

NCTF_VSS#BJ46

NCTF_VSS#BJ5

NCTF

NCTF_VSS#BJ6

NCTF_VSS#C2

NCTF_VSS#C48

NCTF_VSS#D1

NCTF_VSS#D49

NCTF_VSS#E1

NCTF_VSS#E49

NCTF_VSS#F1

D1,D49,E1,E49,F1,F49

NCTF_VSS#F49

PLL ON DIE VR ENABLE



NOTE:This signal has a weak internal pull-up 20K ENABLED -- HIGH (R2212 UNSTUFFED) DEFAULT DISABLED -- LOW (R2212 STUFFED)

PLL_ODVR_EN

http://hobi-elektronika.net

3

6 OF 10

A20GATE

PECI

RCIN#

THRMTRIP#

INIT3_3V#

TS_VSS1

TS_VSS2

TS_VSS3

TS_VSS4

NC_1

C40

B41

C41

A40

P4

AU16

P5

AY11

AY10

T14

AH8

AK11

AH10

AK10

P37

BG2

BG48

BH3

BH47

BJ4

BJ44

BJ45

BJ46

BJ5

BJ6

C2

C48

D1

D49

E1

E49

F1

F49

R2212

1 2

DY

UMA_DIS#

VRAM_SIZE2

H_PECI_R

PCH_THERMTRIP_R

INIT3_3V#

X00 1123

20100923 X01 Modify: Change R2219 to 0R0402 short pad from 0ohm.

3D3V_S0

12

DY

12

3D3V_S0

12

DY

12

ICC_EN#

1 2

1KR2J-1-GP

2

SATA_ODD_PWRGT (56)

UMA_DIS# (20)

TP2204

TPAD14-GP

1

R2207

R2207 10KR2J-3-GP

10KR2J-3-GP

FDI_OVRVLTG

R2208

R2208 10KR2J-3-GP

10KR2J-3-GP

R2209

R2209 10KR2J-3-GP

10KR2J-3-GP

DMI_OVRVLTG

R2210

R2210 10KR2J-3-GP

10KR2J-3-GP

R2211

TPAD14-GP

TP2205

TPAD14-GP

H_A20GATE (27)

1 2

DY

H_RCIN# (27)

H_CPUPWRGD (5,36)

R2204 390R2J-1-GPR2204 390R2J-1-GP

1 2

TP2201

1

1KR2J-1-GP

2

1

GSENSOR_ADI GSENSOR_ST

R2205 DY 10K

R2206 100K DY

3D3V_S0

12

GSENSOR_ST

GFX_CRB_DET

R2203

0R2J-2-GP

TPAD14-GP

TS Signal Disable Guideline: TS_VSS1, TS_VSS2, TS_VSS3 and TS_VSS4 should not float on the motherboar d. They s hould be tied to GND directly.

H_PECI (5,27)

H_THERMTRIP# (5,36)

20100927 X01 Modify: Change R2205 dummy field for ADI-GSENSOR only Change R2206 dummy field for ST-GSENSOR only.

12

GSENSOR_ADI

FDI TERMINATION VOLTAGE OVERRIDE

GPIO37 (FDI_OVRVLTG)

LOW - Tx, Rx terminated to same voltage (DC Coupling Model DEFAULT)

DMI TERMINATION VOLTAGE OVERRIDE

GPIO36 (DMI_OVRVLTG)

Integrated Clock Enable functionality is achieved via soft-strap. The default is integrated clock enable.

LOW - Tx, Rx terminated to same voltage (DC Coupling Model DEFAULT)

Integrated Clock Chip Enable

ICC_EN#

HIGH (R2211 DY)- DISABLED [DEFAULT]

LOW (R2211)- ENABLED

GPIO8 has a weak[20K] internal pull up.

Integrated Clock Enable functionality is achieved via soft-strap. The default is integrated clock enable.

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet

PCH 6/9(GPIO/CPU)

DB13 DIS

Taipei Hsien 221, Taiwan, R.O.C.

of

22 105Friday, November 26, 2010

of

22 105Friday, November 26, 2010

of

22 105Friday, November 26, 2010

1

R2205

10KR2J-3-GP

R2206

100KR2J-1-GP

X00

5

4

3

2

1

SSID = PCH

D D

C C

B B

VCCVRM(Internal PLL and VRMs): A.1.5V for Mobile B.1.8 V for Desktop

(1uFx3)

(10uFx1_0603)

(1uF x4)

0.159A(Totally current of VCCVRM)

6A

1D05V_VTT

2.925A(Total current of VCCIO)

12

C2305

0.266A (Totally VCC3_3 current)

0.042A (Totally current of VCCDMI)

1.3A

12

C2301

SC10U6D3V5KX-1GP

12

C2306

SC1U6D3V2KX-GP

SC10U6D3V5KX-1GP

(0.1uF x1)

1D5V_S0

12

C2302

TP2301TPAD14-GP TP2301TPAD14-GP

12

C2307

TP2302TPAD14-GP TP2302TPAD14-GP

1D05V_VTT

12

C2303

SC1U6D3V2KX-GP

1D05V_VTT

1

(10uF x1)

12

C2308

SC1U6D3V2KX-GP

3D3V_S0

1

12

C2304

SC1U6D3V2KX-GP

VCCAPLLEXP

12

C2309

SC1U6D3V2KX-GP

12

C2310

C2310 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

VCCFDIPLL

+1.05VS_VCC_DMI

PCH1G

AA23

VCCCORE

AC23

VCCCORE

AD21

VCCCORE

AD23

VCCCORE

AF21

VCCCORE

AF23

VCCCORE

AG21

VCCCORE

AG23

VCCCORE

AG24

VCCCORE

AG26

VCCCORE

AG27

VCCCORE

AG29

VCCCORE

AJ23

VCCCORE

AJ26

VCCCORE

AJ27

VCCCORE

AJ29

VCCCORE

AJ31

VCCCORE

AN19

VCCIO

BJ22

VCCAPLLEXP

AN16

VCCIO

AN17

VCCIO

AN21

VCCIO

AN26

VCCIO

AN27

VCCIO

AP21

VCCIO

AP23

VCCIO

AP24

VCCIO

AP26

VCCIO

AT24

VCCIO

AN33

VCCIO

AN34

VCCIO

BH29

VCC3_3

AP16

VCCVRM

BG6

VCCAFDIPLL

AP17

VCCIO

AU20

VCCDMI

COUGAR-GP-U2-NF

POWER

Cougar

Cougar Point

Point

VCC CORE

VCCIO

FDI

CRTLVDS

DMI

NAND / SPI HVCMOS

7 OF 10

VCCADAC

VSSADAC

VCCALVDS

VSSALVDS

VCCTX_LVDS

VCC3_3

VCCVRM

VCCDMI

VCCCLKDMI

VccDFTERM

VCCSPI

0.001A

U48

U47

0.001A

+3VS_VCCA_LVDS

AK36

AK37

AM37

AM38

AP36

AP37

V33

V34

0.16A

AT16

0.042A

+1.05VS_VCC_DMI

AT20

AB36

0.02A

+1.05VS_VCC_DMI_CCI

AG16

AG17

AJ16

AJ17

V1

(0.1uF/0.01uF x1) (10uF x1_0603)

+VCCA_DAC_1_2

12

C2313

0.06A

+1.8VS_VCCTX_LVDS

0.266A

12

0.19A

12

C2322

C2322 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

0.02A

12

C2314

SCD01U16V2KX-3GP

SCD1U10V2KX-5GP

12

C2316

SCD01U16V2KX-3GP

(0.1uFx1)

C2319

C2319 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

R2306

1 2

C2320

C2320 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

0.02A

R2307

1 2

C2321

C2321 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C2323

C2323 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

0.06A

0R2J-2-GP

0.19A

0.02A

12

C2315

0.001A

SC10U6D3V5KX-1GP

12

C2317

SCD01U16V2KX-3GP

3D3V_S0

1D5V_S0

1D05V_VTT

(1uF x1)

1D05V_VTT

(1uFx1) (10uFx1)

1D8V_S0

(0.1uFx1)

3D3V_S5

(1uFx1)

X00 1015

12

C2318

SC10U6D3V5KX-1GP

R2308

R2308 0R3J-0-U-GP

0R3J-0-U-GP

R2304

R2305

1 2

3D3V_S0

12

3D3V_S0

12

0R3J-0-U-GP

1D8V_S0

0R5J-5-GP

(0.01uF x2) (22uF x1)

A A

5

4

0617 Modify: Joseph Removed R2311&R2310 1.5V and 1.8V co-lay. and rename all of 1D5V_S0_1D8V_S0 to 1D5V_S0 for VCCVRM.

http://hobi-elektronika.net

3

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

PCH 7/9(POWER1)

Taipei Hsien 221, Taiwan, R.O.C.

DB13 DIS

X00

of

23 105Friday, November 26, 2010

of

23 105Friday, November 26, 2010

of

23 105Friday, November 26, 2010

1

X00

5

4

3

2

1

SSID = PCH

1

TP2405TPAD14-GP TP2405TPAD14-GP

1

(10uFx1)

1

12

C2415

12

(1uFx1)

TP2406TPAD14-GP TP2406TPAD14-GP

VCCACLK

+VCCPDSW

DCPSUSBYP

1

+V3.3S_VCC_CLKF33

+VCCAPLL_CPY_PCH

+VCCSUS1

12

C2408

C2407

SC1U6D3V2KX-GP

1D5V_S0

+1.05VS_VCCA_A_DPL

+1.05VS_VCCA_B_DPL

+VCCDIFFCLK

0.095A

+V1.05S_SSCVCC

(1uFx1)

+VCCSST

12

DCPSUS

1

C2418

SCD1U10V2KX-5GP

12

C2421

C2422

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

TP2401TPAD14-GP TP2401TPAD14-GP

R2403

0.002A

3D3V_S0

20100906 X01 Modify: Add 2nd source 68.10090.10B on L2401,L2402,L2403 sync with Annie.

D D

C C

1D05V_VTT

B B

1D05V_VTT

A A

L2401

1 2

IND-10UH-218-GP

68.10050.10Y

2nd = 68.10090.10B

L2402

L2403

0.08A

R2404

12

0R2J-2-GP

R2405

12

0R2J-2-GP

1 2

IND-10UH-218-GP

68.10050.10Y

2nd = 68.10090.10B

1 2

IND-10UH-218-GP

68.10050.10Y

2nd = 68.10090.10B

+1.05VS_VCCA_A_DPL

12

C2443

DY

+1.05VS_VCCA_B_DPL

12

C2444

DY

+VCCDIFFCLK

12

SC1U6D3V2KX-GP

+V1.05S_SSCVCC

12

SC1U6D3V2KX-GP

5

(10uFx1) (1uFx1)

+V3.3S_VCC_CLKF33

C2401

12

(22uFx2_0603) (1uFx3)

(1uFx1) (220uFx1)

12

SC10U6D3V3MX-GP

12

SC10U6D3V3MX-GP

C2412

C2413

12

C2402

C2402 SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC10U6D3V5KX-1GP

1D05V_VTT

C2409

C2409 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

(1uFx1) (220uFx1)

C2410

C2410 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

1D05V_VTT

(1uFx1)

3D3V_S5

(0.1uFx1)

C2403

12

DY

SC10U6D3V5KX-1GP

12

C2411

R2406

0R3J-0-U-GP

SC1U6D3V2KX-GP

(0.1uFx1)

(1uFx1)

1D05V_VTT

0.001A

(0.1uFx2) (4.7uFx1_0603)

SC4D7U6D3V3KX-GP

RTC_AUX_S5

6uA

(0.1uFx2) (1uFx1)

1.01A (Total current of VCCASW)

C2404

SC10U6D3V5KX-1GP

+VCCRTCEXT

(0.1uFx1)

12

C2414

C2417

R2403

1 2

0R3J-0-U-GP

TP2404TPAD14-GP TP2404TPAD14-GP

1D05V_VTT

TP2402TPAD14-GP TP2402TPAD14-GP

12

C2406

SC1U6D3V2KX-GP

0.16A (Totally current of VCCVRM

+VCCDIFFCLKN

0.055A

12

SCD1U10V2KX-5GP

12

4

PCH1J

AD49

VCCACLK

T16

VCCDSW3_3

V12

DCPSUSBYP

T38

VCC3_3

BH23

VCCAPLLDMI2

AL29

VCCIO

AL24

DCPSUS

AA19

VCCASW

AA21

VCCASW

AA24

VCCASW

AA26

VCCASW

AA27

VCCASW

AA29

VCCASW

AA31

VCCASW

AC26

VCCASW

AC27

VCCASW

AC29

VCCASW

AC31

VCCASW

AD29

VCCASW

AD31

VCCASW

W21

VCCASW

W23

VCCASW

W24

VCCASW

W26

VCCASW

W29

VCCASW

W31

VCCASW

W33

VCCASW

N16

DCPRTC

Y49

VCCVRM

BD47

VCCADPLLA

BF47

VCCADPLLB

AF17

VCCIO

AF33

VCCDIFFCLKN

AF34

VCCDIFFCLKN

AG34

VCCDIFFCLKN

AG33

VCCSSC

V16

DCPSST

T17

DCPSUS

V19

DCPSUS

BJ8

V_PROC_IO

A22

VCCRTC

COUGAR-GP-U2-NF

http://hobi-elektronika.net

POWER

Cougar

Cougar Point

Point

Clock and Miscellaneous

PCI/GPIO/LPCMISC

SATA USB

CPURTC

HDA

3

10 OF 10

VCCIO

VCCSUS3_3

VCCIO

V5REF_SUS

DCPSUS

VCCSUS3_3

V5REF

VCCSUS3_3

VCC3_3

VCCIO

VCCAPLLSATA

VCCVRM

VCCIO

VCCASW

VCCSUSHDA

N26

P26

P28

T27

T29

0.097A (Totally current of VCCSUS3_3)

T23

T24

V23

V24

P24

T26

M26

AN23

AN24

P34

N20

N22

P20

P22

AA16

W16

T34

AJ2

AF13

AH13

AH14

AF14

AK1

AF11

AC16

AC17

AD17

T21

V21

T19

P32

1D05V_VTT

+5VA_PCH_VCC5REFSUS

+VCCA_USBSUS

+5VS_PCH_VCC5REF

SC1U6D3V2KX-GP

SCD1U10V2KX-5GP

SC1U6D3V2KX-GP

+V1.05S_VCCAPLL_SATA3

1D5V_S0

1D05V_VTT

SC1U6D3V2KX-GP

0.01A

C2433

SCD1U10V2KX-5GP

C2433

3D3V_S5

12

DY

12

C2428

12

C2430

12

C2429

12

C2432

12

C2435

+3VS_+1.5VS_HDA_IO

(0.1uFx1)

12

C2424

C2424 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

C2434

DY

C2423

C2423 SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C2425

C2425 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

1

C2437

C2437 SC1U10V2KX-1GP

SC1U10V2KX-1GP

SC10U6D3V5KX-1GP

2

(1uFx1)

(0.1uFx1)

TP2403 TPAD14-GPTP2403 TPAD14-GP

0.001A

3D3V_S5

(1uFx1)

12

C2431

C2431 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

(0.1uFx1)

R2411

1 2

DY

0R3J-0-U-GP

1D05V_VTT

(1uFx1)

1D05V_VTT

3D3V_S5

2nd = 83.R2004.B8F

21

D2401

D2401 CH751H-40PT-GP

CH751H-40PT-GP

83.R0304.A8F

1 2

10R2J-2-GP

12

C2426

C2426 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

R2408

(0.1uFx1)

0.001A

3D3V_S0

21

D2402

D2402 CH751H-40PT-GP

CH751H-40PT-GP

83.R0304.A8F

2nd = 83.R2004.B8F

3D3V_S0

(0.1uFx2)

3D3V_S0

1D05V_VTT

(1uFx1)

1D05V_VTT

(10uFx1)

+3VS_+1.5VS_HDA_IO

Title

Size Document Number Rev

Date: Sheet

83.R0304.A8F

R2407

1 2

(1uFx1)

10R2J-2-GP

12

C2427

C2427 SC1U10V2KX-1GP

SC1U10V2KX-1GP

R2409

1 2

0R3J-0-U-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

PCH 8/9(POWER2)

DB13 DIS

1

5V_S5

5V_S0

3D3V_S5

X00

of

24 105Friday, November 26, 2010

of

24 105Friday, November 26, 2010

of

24 105Friday, November 26, 2010

X00

5

4

3

2

1

SSID = PCHSSID = PCH

D D

C C

B B

A A

5

PCH1H

H5

VSS

AA17

VSS

AA2

VSS

AA3

VSS

AA33

VSS

AA34

VSS

AB11

VSS

AB14

VSS

AB39

VSS

AB4

VSS

AB43

VSS

AB5

VSS

AB7

VSS

AC19

VSS

AC2

VSS

AC21

VSS

AC24

VSS

AC33

VSS

AC34

VSS

AC48

VSS

AD10

VSS

AD11

VSS

AD12

VSS

AD13

VSS

AD19

VSS

AD24

VSS

AD26

VSS

AD27

VSS

AD33

VSS

AD34

VSS

AD36

VSS

AD37

VSS

AD38

VSS

AD39

VSS

AD4

VSS

AD40

VSS

AD42

VSS

AD43

VSS

AD45

VSS

AD46

VSS

AD8

VSS

AE2

VSS

AE3

VSS

AF10

VSS

AF12

VSS

AD14

VSS

AD16

VSS

AF16

VSS

AF19

VSS

AF24

VSS

AF26

VSS

AF27

VSS

AF29

VSS

AF31

VSS

AF38

VSS

AF4

VSS

AF42

VSS

AF46

VSS

AF5

VSS

AF7

VSS

AF8

VSS

AG19

VSS

AG2

VSS

AG31

VSS

AG48

VSS

AH11

VSS

AH3

VSS

AH36

VSS

AH39

VSS

AH40

VSS

AH42

VSS

AH46

VSS

AH7

VSS

AJ19

VSS

AJ21

VSS

AJ24

VSS

AJ33

VSS

AJ34

VSS

AK12

VSS

AK3

VSS

COUGAR-GP-U2-NF

Cougar

Cougar Point

Point

8 OF 10

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28

4

http://hobi-elektronika.net

PCH1I

AY4

VSS

AY42

VSS

AY46

VSS

AY8

VSS

B11

VSS

B15

VSS

B19

VSS

B23

VSS

B27

VSS

B31

VSS

B35

VSS

B39

VSS

B7

VSS

F45

VSS

BB12

VSS

BB16

VSS

BB20

VSS

BB22

VSS

BB24

VSS

BB28

VSS

BB30

VSS

BB38

VSS

BB4

VSS

BB46

VSS

BC14

VSS

BC18

VSS

BC2

VSS

BC22

VSS

BC26

VSS

BC32

VSS

BC34

VSS

BC36

VSS

BC40

VSS

BC42

VSS

BC48

VSS

BD46

VSS

BD5

VSS

BE22

VSS

BE26

VSS

BE40

VSS

BF10

VSS

BF12

VSS

BF16

VSS

BF20

VSS

BF22

VSS

BF24

VSS

BF26

VSS

BF28

VSS

BD3

VSS

BF30

VSS

BF38

VSS

BF40

VSS

BF8

VSS

BG17

VSS

BG21

VSS

BG33

VSS

BG44

VSS

BG8

VSS

BH11

VSS

BH15

VSS

BH17

VSS

BH19

VSS

H10

VSS

BH27

VSS

BH31

VSS

BH33

VSS

BH35

VSS

BH39

VSS

BH43

VSS

BH7

VSS

D3

VSS

D12

VSS

D16

VSS

D18

VSS

D22

VSS

D24

VSS

D26

VSS

D30

VSS

D32

VSS

D34

VSS

D38

VSS

D42

VSS

D8

VSS

E18

VSS

E26

VSS

G18

VSS

G20

VSS

G26

VSS

G28

VSS

G36

VSS

G48

VSS

H12

VSS

H18

VSS

H22

VSS

H24

VSS

H26

VSS

H30

VSS

H32

VSS

H34

VSS

F3

VSS

COUGAR-GP-U2-NF

3

Cougar

Cougar Point

Point

9 OF 10

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

Date: Sheet

2

Date: Sheet

Taipei Hsien 221, Taiwan, R.O.C.

PCH 9/9(VSS)

DB13 DIS

1

X00

of

25 105Friday, November 26, 2010

of

25 105Friday, November 26, 2010

of

25 105Friday, November 26, 2010

X00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

http://hobi-elektronika.net

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

DB13 DIS

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

26 105Friday, November 26, 2010

of

X00

5

SSID = KBC

3D3V_AUX_KBC

1 2

12

D D

X00 20101111 Add VGA_THRM

C C

AFTP2703AFTP2703

20100909 X01: PSE suggest: Add AFTP2701~AFTP2703 at USB_PWR_EN#, AC_PRESENT, and E51_TxD.

R2771

R2771 2D2R3-1-U-GP

2D2R3-1-U-GP

12

C2701

SC2D2U10V3KX-1GP

R2702

1 2

0R0603-PAD

20100923 X01 Modify: Change R2702 to 0R0603 short pad from 0ohm.

12

C2704

C2705

C2706

DY

SCD1U10V2KX-5GP

EC_AGND

E51_TxD

1

12

C2708

C2707

SCD1U10V2KX-5GP

AD_IA(40)

C2714 SCD1U10V2KX-5GPC2714 SCD1U10V2KX-5GP

1 2

PSID_EC(38)

CPU_THRM(28)

PWM_FAN(28)

LCD_TST(49)

SUS_PWR_ACK(19)

SYS_THRM(28)

BATT_WHITE_LED#(68)

CAP_LED(69)

S5_ENABLE(36)

BAT_IN#(39)

LID_CLOSE#(70)

RSMRST#_KBC(19)

PM_SLP_S4#( 19,46)

ME_UNLOCK(21)

WIFI_RF_EN(65,66) BLUETOOTH_EN(65,66) S0_PWR_GOOD(19,36)

AC_PRESENT(19,86)

IMVP_PWRGD(36,42)

12

C2709

SC2D2U10V3KX-1GP

EC_AGND

KBC_VCORF

12

C2712

C2712 SC1U10V3ZY-6GP

SC1U10V3ZY-6GP

12

C2710

SCD1U10V2KX-5GP

PCB_VER_AD

PSL_IN2 MODEL_ID_DET

ECSMI#_KBC

PSL_IN1 PSL_OUT EC_GPIO72

3D3V_AUX_KBC_VCC

U2701A

104

VREF

97

GPIO90/AD0

98

GPIO91/AD1

99

GPIO92/AD2

100

GPIO93/AD3

101

GPIO94/DA0

105

GPIO95/DA1

106

GPIO96/DA2

79

GPIO2

95

GPIO3/AD6

96

GPIO4/AD5

108

GPIO5/AD4

93

PSL_IN2#_GPIO6

94

GPIO7/AD7

114

GPIO16

6

GPIO24

109

GPIO30

14

GPIO34/CIRRXL

15

GPIO36

80

GPIO41

17

GPIO42/TCK

20

GPIO43/TMS

21

GPIO44/TDI

23

GPIO46/CIRRXM/TRST#

26

GPIO51

73

PSL_IN1_GPIO70

74

PSL_OUT_GPIO71

75

VBKUP

82

GPIO75

83

GPO76/SHBM

84

GPIO77

91

GPIO81

110

GPO82/IOX_LDSH/TEST#

112

GPIO84/IOX_SCLK/XORTR#

107

GPIO97

44

VCORF

NPCE795PA0DX-GP-U

VCC19VCC46VCC76VCC88VCC

GND18GND45GND78GND89GND

115

GND

5

116

ROSA Multi GPIO setting

R2711 0R0402-PADR2711 0R0402-PAD

20100923 X01 Modify: Change R2711 to 0R0402

C2719 SCD1U10V2KX-5GP

CPU_THRM

SYS_THRM

B B

12

DY

C2721 SCD1U10V2KX-5GP

12

DY

EC_AGND

short pad from 0ohm.

VBAT

102

AVCC

GPIO11/CLKRUN#

GPIO67/PWUREQ#

GPIO52/PSDAT3/RDY#

GPIO50/PSCLK3/TDO

F_SDIO/F_SDIO0

1 2

4

20100824 X01 Modify: Change R2724 to 20K 0402 from 10K for X01 stage. 20100928 X01: Change R2739 to 100K 1% from 5% Resistor. Change R2726 to 100K 1% from 5% Resistor. Stuff C2717,C2718 to reduce noise.

3D3V_S0

12

C2702

SCD1U10V2KX-5GP

4

1 OF 2

VDD

LRESET#

LCLK

LFRAME#

LAD3 LAD2 LAD1 LAD0

SERIRQ

GPIO65/SMI#

ECSCI#/GPIO54

GPIO10/LPCPD#

GPIO85/GA20

KBRST#/GPIO86

GPIO27/PSDAT2

GPIO26/PSCLK2

GPIO35/PSDAT1

GPIO37/PSCLK1

GPIO17/SCL1 GPIO22/SDA1 GPIO73/SCL2 GPIO74/SDA2 GPIO23/SCL3 GPIO31/SDA3 GPIO47/SCL4 GPIO53/SDA4

F_CS0#

F_SCK

F_SDI/F_SDIO1

AGND

103

EC_AGND

C2702

7 2 3 1 128 127 126 125 8 9 29 124 123 121 122

27 25 11 10 71 72

70 69 67 68 119 120 24 28

90 92 86 87

C2703

DY

SC2D2U10V3KX-1GP

C2711

1 2

SC220P50V2KX-3GP

R2735

PLT_RST#_EC

1 2

LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

ECSCI#_KBC

ECSWI#_KBC

AD_IA_HW2

EC_ENABLE#_1

PROCHOT_EC

EC_SPI_CS#_C EC_SPI_CLK_C EC_SPI_DI_C

EC_SPI_DO_C

NOTE: Locate resistors R2719 and R2722 close to the NPCE791L.

NOTE: Connect GND and AGND planes via either 0R resistor or one point layout connect ion.

EC_GPIO47 High Active

PROCHOT_EC

12

R2732

100KR2J-1-GP

PCB_VER_AD

SCD1U10V2KX-5GP

DY

0R2J-2-GP

CLK_PCI_KBC (18)

LPC_FRAME# (21,71)

LPC_AD[0..3] (21,71)

INT_S ERIRQ (21 ) PM_CLKRUN# (19) L_BKLT_EN (17)

HDMI_ IN# (51)

H_A20GATE ( 22) H_RCIN# (22)

BLON_OUT (49)

AD_IA_HW2 (40)

PCH_WAKE# (19)

TPDATA (69) TPCLK (69)

<------ TP

BAT_SCL (39,40) BAT_SDA (39,40) SML1_CLK (20,86) SML1_DATA (20,86)

PM_LAN_ENABLE (31)

LCD_TST_EN (49)

33R2J-2-GPR2736 33R2J-2-GPR2736

12

33R2J-2-GPR2719 33R2J-2-GPR2719

12

R2737 0R2J-2-GPR2737 0R2J-2-GP

12

R2722 33R2J-2-GPR2722 33R2J-2-GP

12

Q2702

G

S

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

3

3D3V_AUX_KBC

X00 1025

12

C2717

DY

1 2

EC_AGND

PLT_RST# (5,18,31,32,35,65,66,71,83)

PCB VERSION A/D(PIN98) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

R2724

R2724 10KR2F-2-GP

10KR2F-2-GP

R2726

R2726 100KR2F-L1-GP

100KR2F-L1-GP

NOTES: The NPCE795P GPIO/PWM outputs that are connected to LEDs have high drive buffers (20mA) and can be connected directly to the LEDs.

X00 1123

20100917 X01 Modify: Rename PCIEST# to AD_IA_HW2 on KBC GPIO50 for power Tom suggest.

<------ BATTERY / CHARGER <------PCH / eDP

SPI_CS0#_R (21,60) SPI_CLK_R (21,60) SPI_SO_R (21,60)

SPI_SI_R (21,60)

EC_SPI_DI_C

12

R2773

R2773 100KR2J-1-GP

100KR2J-1-GP

20100906 X01 Modify: Change all of single 2N7002 to 84.2N702.J31 from 84.2N702.D31 due to 84.2N702.D31 will EOL.

20100923 X01 Modify: Change R2733 to 0R0402

D

short pad from 0ohm.

ECRST#

R2720

R2720 0R2J-2-GP

0R2J-2-GP

3D3V_AUX_S5

12

C2716

10.0K

20.0K

33.0K

47.0K

64.9K

76.8

100.0K

143.0K100.0K 1.358VReserved

174.0KReserved 100.0K

PECI

EC_VTT

12

SCD1U16V2KX-3GP

R2705

R2705 10KR2J-3-GP

10KR2J-3-GP

U2701B

31

GPIO56/TA1

117

GPIO20/TA2

63

GPIO14/TB1

64

GPIO01/TB2

32

GPIO15/A_PWM

118

GPIO21/B_PWM

62

GPIO13/C_PWM

65

GPIO32/D_PWM

81

GPIO66/G_PWM

66

GPIO33/H_PWM

22

GPIO45/E_PWM

16

GPIO40/F_PWM

85

VCC_POR#

113

GPIO87/CIRRXM/SIN_CR

111

GPIO83/SOUT_CR/TRIST#

30

GPIO55/CLKOUT/IOX_DIN_DIO

77

GPIO00/EXTCLK

13

PECI

12

VTT

NPCE795PA0DX-GP-U

B

100.0KX00

X01

X02

A00

Reserved

Reserved 1.65V

100.0K

Reserved 100.0K 215.0K 1.048V

FAN_TACH1(28)

PM_PWRBTN#(19)

PCIE_WAKE#(31,35,66) PM_SLP_S3#(19,36,37,47)

CHG_AMBER_LED#(68)

KBC_BEEP(29)

KB_BL_CTRL(69)

AD_IA_HW(40)

PWRLED#(68)

E51_RxD(65,66)

E51_TxD(65,66)

AMP_MUTE#(29)

PCH_SUSCLK_KBC(19)

R2721 43R2J-GPR2721 43R2J- GP

H_PECI(5,22)

1D05V_VTT

1 2 1 2

Need very close to EC

PURE_HW_SHUTDOWN#(28,36,86)

H_PROCHOT # (5,40,42)

2

3.0V

2.75V

2.48V

2.24V

2.0V

1.87V

1.204V

KBSOUT15/GPIO61/XOR_OUT

ECRST#

12

E

C2715

MMBT3906-4-GP

DY

Q2701

C

84.T3906.A11

2nd = 84.03906.F11

MODEL_ID_DET

C2718

DY

1 2

SCD1U10V2KX-5GP

2 OF 2

KBSOUT0/JENK#

KBSOUT1/TCK KBSOUT2/TMS

KBSOUT3/TDI

KBSOUT4/JEN0#

KBSOUT5/TDO

KBSOUT6/RDY#

KBSOUT7 KBSOUT8

KBSOUT9/SDP_VIS# KBSOUT10/P80_CLK KBSOUT11/P80_DAT

KBSOUT12/GPIO64 KBSOUT13/GPIO63 KBSOUT14/GPIO62

GPIO60/KBSOUT16 GPIO57/KBSOUT17

KBSIN0 KBSIN1 KBSIN2 KBSIN3 KBSIN4 KBSIN5 KBSIN6 KBSIN7

SC1U6D3V2KX-GP

3D3V_AUX_KBC

12

R2710

R2710 143KR2F-GP

143KR2F-GP

12

R2739

R2739 100KR2F-L1-GP

100KR2F-L1-GP

EC_AGND

53 52 51 50 49 48 47 43 42 41 40 39 38 37 36 35 34 33

54 55 56 57 58 59 60 61

ECRST# (66)

1

MODEL_ID_DET(GPIO07)

DQ15_ATI

DQ15_NVIDIA

DN15_UMA

DN15_ATI

DQ13_UMA

DQ13_ATI

DN13_UMA

DN13_ATI

DQ15_Ventura

PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE

100.0KDQ15_UMA 3.0V

100.0K

100.0K 215.0K 1.048V

10.0K

20.0K

33.0K

47.0K(63.47334.1DL)

64.9K(64.64925.6DL)

76.8K

100.0K

143.0K100.0K 1.358V

174.0K100.0K

Notes: The total SPI interface signal between EC and PCH can’t not exceed 6500mil. The mismatch between SPI signal must be within 500mil

KCOL0 KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16

KROW0 KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7

KCOL[0..16] (69)

KROW[0..7] (69)

EC_SWI#(20)

EC_SCI#(22)

EC_SMI#(22)

X00 1111

ECSWI#_KBC

R2758

1 2

0R2J-2-GP

ECSCI#_KBC

R2759

1 2

0R2J-2-GP

ECSMI#_KBC

R2760

1 2

0R2J-2-GP

MEDIA BUTTON CONTROL

3D3V_AUX_KBC

2.75V100.0K

2.48V100.0K

2.24V

2.0V

1.87V

1.65V

1.204V

EC GPIO standard PH/PL

20100929 X01:

PSL_IN2

BAT54CPT-GP

KBC_PWRBTN#(68)

A A

3

D2702

2ND = 83.00054.Q81

83.R2003.E81

AC_IN#_KBC

20100906 X01 Modify: Add C2722 0.1uF between Q2703 G&S pin for fixed leakage voltage to 3D3V_AUX_KBC under DC mode. 20100917 X01: Add Q2706 2N7002 to avoid leakage loop from 3D3V_S5 to 3D3V_AUX_KBC issue when 10mW latched fail timing. Un-stuff C2713 to follow the standard schematics.

1 2

1

83.R2003.E81

2ND = 83.00054.Q81

2

KBC_ON#

D2703

2

10mW

1

BAT54CPT-GP

5

R2704

3

EC_GPIO72

330KR2J-L1-GP

KBC_ON#_R

AC_IN# (40)

3D3V_AUX_S5 3D 3V_AUX_S5

RN2706

1

4

KBC_ON#_GATE

23

SRN10KJ-5-GP

C2713

SCD1U10V2KX-5GP

G

S

C2722

1 2

SCD1U10V2KX-5GP

S

G

D

12

D

DY

3D3V_AUX_KBC

2N7002K-2-GP

S5_ENABLE

D

Q2706

84.2N702.J31

2ND = 84.2N702.031

Q2703

Q2703 DMP2130L-7-GP

DMP2130L-7-GP

2ND = 84.03413.A31

84.02130.031

Stuff R2756 and un-stuff R2734 to Keep KBC data under DC mode.

PWR_CHG_ACOK(40)

NOTES: Please make sure there's no pull-down resistor on USB_PWR_EN#,AC_PRESENT,E51_TXD.

4

PSL SOLUTION

1 2

PSL_OUT

G

S

2ND = 84.2N702.031

1 2

DY

R2767

PSL

2N7002K-2-GP

84.2N702.J31

R2756

EC_GPIO72

0R2J-2-GP

PSL_IN1

R2768

PSL

0R2J-2-GP

0R2J-2-GP Q2705

Q2705

12

PSL

KBC_ON#_R

D

http://hobi-elektronika.net

R2769

R2769 100KR2J-1-GP

100KR2J-1-GP

3D3V_AUX_KBC

3D3V_AUX_KBCRTC_AU X_S5

AC_IN#_KBC

EC_ENABLE#_1

10mW SOLUTION

VBACKUP

EC_GPIO72

R2734

1 2

0R2J-2-GP

DY

PSL_IN1

R2763

1 2

0R2J-2-GP

10mW

G

2ND = 84.2N702.031

R2766

1 2

10mW

3

10mW

S

2N7002K-2-GP

84.2N702.J31

Q2704

0R2J-2-GP

KBC_ON#_RKBC_ON#

PSL_IN1

PSL_OUT

D

KBC_ON#

FAN_TACH1(28)

BAT_SCL BAT_SDA

BAT_IN# AC_IN#_KBC

S5_ENABLE ECRST#

EC_ENABLE#_1

E51_RxD

BLUETOOTH_EN

FAN_TACH1

4

8 7 6

2

RN2701

SRN4K7J-8-GP

RN2703

SRN100KJ-6-GP

RN2705

SRN10KJ-6-GP

1 2

23 1

1 23

1 2 3 45

R2712 10KR 2J-3-GPR2712 10KR 2J-3-GP

DY

R2708 10KR 2J-3-GP

DY

R2709 10KR 2J-3-GP

3D3V_AUX_KBC

3D3V_S0

PCIE_WAKE#

Title

KBC Nuvoton NPCE785P

Size Document Number Rev

A2

Date: Sheet

1 2

R2776 100KR2J-1-GPR2776 100KR2J- 1-GP

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiw an, R.O.C.

Taipei Hsien 221, Taiw an, R.O.C.

DB13 DIS

1

27 105Frid ay, November 26, 2010

of

X00

5

4

3

2

1

SSID = Thermal

Thermal sensor P2800

3D3V_LDO_S0

X00 1123

12

R2803

ADJ

R2803 118KR2F-1-GP

118KR2F-1-GP

12

96.3 Degree

12

C2805

SCD1U10V2KX-5GP

P2800EA1-GP

5

VCC

6 7 8

1.H/W T8 Shutdown

TDR

DXP

TDL

DXN

GND

OTZ

ADJ

U2801

74.02800.A71

4 3 2

ADJ

1

20100906 X01 Modify: Change U2801,U2803 to 74.02800.A71 from

74.02800.071 from vender updated parts. Change R2803&R2817 to 107K from 499K, R2804&R2818 to 226K from 102K base on updated ADJ Table.

SYS_THRM (27) CPU_THRM (27)

5V_S0

THERM_SYS_SHDN# THERM_SYS_SHDN#_1

Layout note: 15 mil; at least

83.R5003.C8F

2ND = 83.R5003.H8H

3rd = 83.5R003.08F

R2812

12

DY

0R2J-2-GP

21

CH551H-30PT-GP

D2802

DY

12

waiting for confirm

PURE_HW_SHUTDOW N#(27,36,86)

R2806

24K3R2F-1-GP

1 2

THERM_SYS_SHDN#_1

20101019 X01: Reserve U2804 for PURE_HW_SHUTDOWN# test. 20101020 X01: Reserve R2810 to 3D3V_S0 and R2811 to GND for HYST.

X00 1123

FAN_TACH1(27)

PWM_FAN(27)

C2810

SC2200P50V2KX-2GP

20101110

U2804_1

PWM FAN CONN

AFTP2802AFTP2802 AFTP2801AFTP2801 AFTP2803AFTP2803

12

C2811

DY

U2804

1

SET

2

GND OUT#3HYST

G709T1UF-GP

74.00709.A7F

5V_S0

1

FAN_TACH1_C

1

PWM_FAN_R

1

Q2802

D

2N7002K-2-GP

84.2N702.J31

2ND = 84.2N702.031

20100906 X01 Modify: Change all of single 2N7002 to 84.2N702.J31 from 84.2N702.D31 due to 84.2N702.D31 will EOL.

SCD1U10V2KX-5GP

VCC

X00 1112 Remove R2802,change FAN_PWM1 to PWM_FAN FAN_TACH1 from FAN1 PIN3 change to PIN2 FAN3 change to GND

RN2807

1 2 3

5

4

4

SRN100J-3-GP

THERM_SYS_SHDN#_1

S

G

0629 Modify

U2804_5

12

C2817

C2817 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

U2804_4

R2811

0R2J-2-GP

FAN_TACH1_C

PWM_FAN_R

20.F0765.004

3D3V_S0

R2801

150R2F-1-GP

R2810

DY

0R2J-2-GP

12

X00 1118

AFTP2804AFTP2804

3D3V_S0

3D3V_LDO_S0

12

3D3V_LDO_S0

12

FAN1

4 3 2

1

ACES-CON4-4-GP

12

R2809

R2809 100KR2J-1-GP

100KR2J-1-GP

5V_S0

12

C2808

C2809

5 6

SC4D7U6D3V3KX-GP

SCD1U10V2KX-5GP

D D

C C

B B

3D3V_LDO_S0

Layout notice : Both DXN and DXP routing 10 mil trace width and 10 mil spacing.

X00 1123

2ND = 84.03904.P11

3

84.03904.L06

Q2801

2.System Sensor, Put on palm rest

20100906 X01 Modify: Updated P2800 ADJ Table from data sheet.

1

PMBS3904-1-GP

2

12

C2802

C2802 SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

P2800_DXP

12

C2806

C2806 SC470P50V3JN-2GP

SC470P50V3JN-2GP

P2800_DXN

R2804

R2804 226KR2F-GP

226KR2F-GP

12

C2807

C2807 SC2200P50V2KX-2GP

SC2200P50V2KX-2GP

THERM_SYS_SHDN#

X00 1123

3D3V_S05V_S5 3D3V_LDO_S0 3D3V_S0

U2802

1

VIN

2

GND EN3NC#4

G9091-330T11U-GP

74.09091.J3F

2nd = 74.09198.G7F

A A

20100621 V1.2

Current Limit=360mA

5

VOUT

4

R2813

DY

0R2J-2-GP

12

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

THERMAL P2800 / Fan control

Size Document Number Rev

A3

5

4

http://hobi-elektronika.net

3

2

A3

Date: Sheet

THERMAL P2800 / Fan control

Taipei Hsien 221, Taiwan, R.O.C.

DB13 DIS

X00

of

28 105Friday, November 26, 2010

1

X00

5

SSID = AUDIO

For EMI

AUD_DMIC_CLK AUD_DMIC_IN0

EC2901

EC2902

D D

3D3V_S0

1 2

DY

SC4D7P50V2CN-1GP

Close to codec

12

C2904

C2903

1 2

SC1U6D3V2KX-GP

C C

3D3V_S0

12

R2908

R2908 10KR2J-3-GP

10KR2J-3-GP

AMP_MUTE#

AUD_VREFOUT_B

12

C2923

SC1U10V2KX-1GP

B B

C2902

1 2

SCD1U10V2KX-5GP

1123

EC2902

1 2

DY

SC4D7P50V2CN-1GP

0625 Modify: AUD_DMIC_CLK&AUD_DMIC_IN0 connector to LVDS pin define.

AUD_DMIC_CLK(49) AUD_DMIC_IN0(49)

HDA_CODEC_SDOUT(21) HDA_CODEC_BITCLK(21)

HDA_SDIN0(21)

HDA_CODEC_SYNC(21) HDA_CODEC_RST#(21)

R2920 0R2J-2-GPR2920 0R2J-2-GP R2921 0R2J-2-GPR2921 0R2J-2-GP

AUD_PC_BEEP Trace width>15 mils

4

AMP_MUTE#(27)

Close to codec

AUD_DVDDCORE

12

C2901

C2901 SC10U6D3V5MX-3GP

SC10U6D3V5MX-3GP

1 2 1 2

R2901

1 2

33R2J-2-GP

0707 Modify: updated U2901 part number from data base.

AUD_DMIC_CLK_R

AUD_DMIC_IN0_R HDA_CODEC_SDOUT HDA_CODEC_BITCLK AUD_HP1_JACK_R HDA_CODEC_SDIN0

HDA_CODEC_SYNC HDA_CODEC_RST# AUD_PC_BEEP

2010/06/30 Change to 92HD87 (71.92H87.A03)

AUD_PC_BEEP

C2912 SCD1U10V2KX-5GPC2912 SCD1U10V2KX-5GP

C2913 SCD1U10V2KX-5GPC2913 SCD1U10V2KX-5GP

AMP_MUTE#

U2901

1

DVDD_LV

2

DMIC_CLK/GPIO_1

3

DMIC_0/GPIO_2

4

SDATA_OUT

5

BITCLK

6

SDATA_IN

7

DVDD

8

SYNC

9

RESET#

10

PCBEEP

92HD87B1A5NDGXTBX8-GP

SB_SPKR_R

12

G2903

DUMMY-C2

1 2

+PVDD

41

39

40

EAPD

PVDD

THERMAL_PAD

71.92H87.A03

SENSE_A11SENSE_B12PORTF_L13PORTF_R14PORTC_L15PORTC_R16VREFFILT17CAP218VREFOUT_A19VREFOUT_C

AUD_SENSE_A

AUD_SENSE_B

SB_SPKR_R

KBC_BEEP_R

G2902

DUMMY-C2

1 2

3

AUD_SPK_R+ AUD_SPK_RAUD_SPK_LAUD_SPK_L+

+AVDD

AUD_VREG

34

37

33

36

35

38

32

31

PVSS

PVDD

AVDD2

PORTD_-L

PORTD_-R

PORTD_+L

PORTD_+R

AUD_PC_BEEP

120KR2J-L-GP

R2910 470KR2J-2-GPR2910 470KR2J-2-GP

AUD_CAP2

AUD_VREFFLT

R2909

1 2

VREG/+2_5V

20

AUD_VREFOUT_B

AUD_AGND

CAP+

CAP-

AVSS2

PORTB_R

PORTB_L

AVSS2

PORTA_R

PORTA_L

AVDD1

From SB

From EC

AUD_SPK_R+ (58)

AUD_SPK_R- (58)

AUD_SPK_L- (58)

AUD_SPK_L+ (58)

30 29 28

V-

27 26 25 24 23 22 21

HDA_SPKR (21)

KBC_BEEP (27)

2

+AVDD

R2902

1 2

0R0603-PAD

C2906

SC1U10V2KX-1GP

12 12

0R0603-PAD

PUMP_CAPP

PUMP_CAPN AUD_V_B

AUD_HP1_JACK_L

AUD_EXT_MIC_R AUD_EXT_MIC_L

+AVDD

12

C2905

1 2

SCD1U10V2KX-5GP

AUD_AGND

CLOSE TO CODEC

C2914

C2914 SC2D2U10V3KX-1GP

SC2D2U10V3KX-1GP

1 2

R2906 60D4R2F-GPR2906 60D4R2F-GP

1 2

R2905 60D4R2F-GPR2905 60D4R2F-GP

1 2

C2922 SC1U10V3KX-3GPC2922 SC1U10V3KX-3GP C2921 SC1U10V3KX-3GPC2921 SC1U10V3KX-3GP

Put C2921 and C2922 close to codec

0707 Modify: Change R2911,R2914,R2917 change to 0ohm 0603 from short pad. 0726 Modify: Removed all of AUD_AGND and R2911,R2914,R2917.

R2911

0R3J-0-U-GP

12

R2914

0R3J-0-U-GP

12

R2917

0R3J-0-U-GP

12

1

5V_S0 +PVDD

R2903

1 2

0R0603-PAD

12

C2909

C2908

1 2

SCD1U10V2KX-5GP

AUD_HP1_JACK_R2 (58)

AUD_HP1_JACK_L2 (58)

AUD_AGND

MIC_IN_R (58) MIC_IN_L (58)

AUD_CAP2

AUD_VREFFLT

AUD_V_B

AUD_VREG

AUD_AGND AUD_AGNDAUD_AGND AUD_AGND

C2910

SC1U10V2KX-1GP

AUD_AGND

12

C2917

SC4D7U6D3V3KX-GP

R2904

1 2

0R0603-PAD

SC10U6D3V5MX-3GP

12

C2918

SC10U6D3V5MX-3GP

Close to codec

0719 Modify: Move RN2901 to closed AUDIO CODEC from speaker connector.

0,&,1

AUD_VREFOUT_B

1

23

RN2901

SRN4K7J-8-GP

4

5V_S0

12

C2915

C2916

SC10U6D3V5MX-3GP

SC1U6D3V2KX-GP

$]DOLD,)(0,

HDA_CODEC_BITCLK

12

R2912

R2912 47R2J-2-GP

47R2J-2-GP

DY

HDA_CODEC_BITCLK_R

A A

12

C2920

DY

SCD1U10V2KX-5GP

5

AUD_SENSE_A

+AVDD

12

AUD_AGND

R2915

R2915 2K49R2F-GP

2K49R2F-GP

C2919

C2919 SC1000P50V3JN-GP-U

SC1000P50V3JN-GP-U

Close to Pin13

4

R2913

1 2

20KR2F-L-GP

R2919

39K2R2F-L-GP

AUD_HP1_JD# (58)

12

EXT_MIC_JD# (58)

http://hobi-elektronika.net

3

AUD_SENSE_B

Close to Pin14

+AVDD

12

AUD_AGND

R2916

R2916 2K49R2F-GP

2K49R2F-GP

R2918

R2918 20KR2F-L-GP

20KR2F-L-GP

AUD_AGND

2

MIC_IN_L(58)

MIC_IN_R(58)

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

Audio Codec 92HD87B1

Taipei Hsien 221, Taiwan, R.O.C.

DB13 DIS

29 105Friday, November 26, 2010

of

1

of

X00

5

D D

C C

4

3

2

1

(Blanking)

B B

A A

5

4

http://hobi-elektronika.net

3

2

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

Taipei Hsien 221, Taiwan, R.O.C.

Title

Size Document Number Rev

A3

Date: Sheet

DB13 DIS

Taipei Hsien 221, Taiwan, R.O.C.

Reserved

1

30 105Friday, November 26, 2010

of

X00