Dell D630 Schematics REV 0.4
A
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B
COMPAL CONFIDENTIAL
C
D
E
1 1
PCB NO :
BOM P/N :
2 2
LA-3302P ( DAA00000K0L)
45144731L01
MODEL NAME :
IBQ00
M08 (DIS) Briscoe
uFCPGA Mobile Merom
Intel Crestline + ICH8M
2007-03-07
3 3
REV : 0.4 (X03)
@ : Nopop Component
1@ : Populate for G72MV
2@ : Populate for G86MV
45144731L01 pop for G86MV
45144XXXXX pop for G72MV
4 4
MB PCB
Part Number Description
DAA00000K0L
A
PCB ZGX LA-3302P
REV0 M/B DIS
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
B
C
D
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Cover Sheet
LA-3302P
166Wednesday, March 07, 2007
E
of
0.4
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B
C
D
E
Block Diagram
Compal confidential
Model : IBQ01
FAN
1 1
+FAN1_VOUT
RGB
DVI
TV
page 18
LVDS CONN
+INV_PWR_SRC
+LCDVDD
page 19
Thermal
GUARDIAN III
EMC4001
+3.3V_SUS
CRT CONN
+5V_RUN
NV G86
+1.25V_GFX_PCIE
+GPU_CORE(1.1V)
page 51,52,53,54,55,56,57
page 20
page 18
PCI-E 16X
Pentium-M
Merom -4MB (Socket P)
+1.05V_VCCP
+VCC_CORE
H_A#(3..35) H_D#(0..63)
uFCPGA CPU
478pin
System Bus
FSB 800 MHz
page 7,8,9
INTEL
+1.25V_RUN
+1.5V_RUN
+1.8V_SUS
+1.05V_VCCP
+3.3V_RUN
+1.8V_RUN
Crestline
1299pin BGA
page 10,11,12,13,14,15
Memory BUS
(DDR2)
+1.8V_SUS 533 / 667MHz
USB[4]
CPU ITP Port
+1.05V_VCCP
Smart Card
OZ77CR6
+5V_RUN
page 31
Clock Generator
CK505
+3.3V_M
DDRII-DIMM X2
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 ,8
+0.9V_DDR_VTT
+1.8V_SUS
page6page 7
page 16,17
SLOT
2 2
PCI BUS
DOCKING
PORT
DOCK LPC BUS
PCI_PIRQA#
REQ#0
GNT#0
DOCKING
BUFFER
+5V_RUN
page 36 page 30
USB[8]
page 35
IDSEL:AD17
(PIRQD#,GNT#1,REQ#1)
CardBus
OZ711 LQFP
+3.3V_RUN
USB[6]
PCI Express BUS
Mini Card2
WLAN
3 3
+3.3V_WLAN
Mini Card 1
WWAN
+3.3V_RUN
+1.5V_RUN+1.5V_RUN
page 34page 34
USB[9]
PWR Sequence
page 42
ME & LED
page 43
DC IN
4 4
Battery IN
page 44
page 44
3V / 5V /15V
page 45
1.8V / 0.9V/1.25V
page 46
1.5V / 1.05V
page 47
Vccore
page 48
Charger
page 49
Battery Select
page 50
A
GIGA Enthernet
BCM5755M
+3.3V_LAN
+2.5V_LAN
+1.2V_LAN
RJ45
IO/B
page 28,29
B
(+3VRUN 33MHz)
IEEE1394
page 30
(+1.5V_RUN 100MHz)
DOCK LPC BUS
COM
+3.3V_SUS
page 37
Bluetooth
+3.3V_RUN
USB[7]
+3.3V_ALW
DMI
+1.5V_RUN
100MHz
+1.25V_RUN
+RTC_CELL
+3.3V_RUN
+3.3V_SUS
+1.5V_RUN
+1.05V_VCCP
+3VRUN
33MHz
SMSC SIO
ECE5028
page 38
ECE1077
+3.3V_ALW
page 37
Int.KBD &
Stick
page 40
Trough Cable
INTEL
ICH8-M
676pin BGA
page 21,22,23,24
page 21,22,23,24
LPC BUS
MEC5025
+RTC_CELL
+3.3V_ALW
page 40
Stick
Touch Pad
+5V_RUN
C
SPI
page 39
page 40
48MHz
SATA
S-HDD
+5V_HDD
SPI
ST M25P16
+3.3V_SUS
+3.3V_RUN
USB[5]
USB[2,3]
USB[0,1] SIDE
Azalia I/F
PATA
page 25 page 25 page 26
page 39
Biometric
page 40
REAR
USB Ports X2
+5V_SUS
page 32
USB Ports X2
+5V_SUS
IO/Board
SC_USB
D Moudle
+5V_MOD
AMP & INT.
Speaker
+5V_RUN +3.3V_RUN
Azalia Codec
STAC9205
+3.3V_RUN
+VDDA
INT MIC
+VDDA
page 27 page 27
page 27
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
D
Date: Sheet
USB2 : Rear Left as viewed from the back,
USB3 Rear Right as viewed from the back
USB0 : side pair top,
USB1 : side pair bottom
MDC
+3.3V_SUS
page 33
Cable
RJ11
IO/B
HeadPhone
& MIC Jack
Compal Electronics, Inc.
Block Diagram
LA-3302P
266Monday, February 26, 2007
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3
2
1
POWER STATES
State
D D
S0 (Full ON) / M0
S3 (Suspend to RAM) / M1 LOW HIGH HIGH HIGH ON ON ON ONOFF
S4 (Suspend to DISK) / M1 ON ON ON ONOFF
S5 (SOFT OFF) / M1 ON ON ON ONOFFLOW HIGH LOW HIGHLOW
S3 (Suspend to RAM) / M-OFF
S4 (Suspend to DISK) / M-OFF HIGH
S5 (SOFT OFF) / M-OFF
Signal
SLP
SLP
S3#
S4#
HIGH HIGH HIGH
HIGH
LOW HIGH HIGH HIGHLOW
LOW HIGH HIGH HIGH LOW ON ONOFF OFF OFF
LOW LOW LOW LOW ON OFF OFF OFF OFF
LOW LOW LOW LOW LOW ON OFF OFF OFF OFF
SLP
S5#
S4
STATE#
SLP
M#
HIGH
HIGH
ALWAYS
PLANE
ON
M
PLANE
ON
SUS
RUN
PLANE
PLANE
ON ON ON
CLOCKS
ICH8-M
USB PORT#
0
1
2
3
4
5
6
7
DESTINATION
Side Top
Side Bottom
Rear Left
Rear Right
Smart Card
Biometric
Card Bus
Bluetooth
C C
B B
PM TABLE
State
S0
S3
S5 S4/AC
S5 S4/AC don't exist
power
plane
+15V_ALW
+5V_ALW
+3.3V_ALW +1.8V_SUS
+3.3V_RTC_LDO
ON
ON
+5V_SUS
+3.3V_SUS
ON ON
ON
OFF
OFFOFF
+5V_RUN
+3.3V_RUN
+2.5V_RUN
+1.8V_RUN
+1.5V_RUN
+VCC_+1P2V_GPU_CORE
+0.9V_DDR_VTT
+GPU_CORE
+VCC_CORE
+1.05V_VCCP
OFFON
OFF
OFF
+3.3V_M +1.25V_M
+1.25V_M
+1.05V_M +1.05V_M
ON
ON
ON
+3.3V_M
(M-OFF)
ON
OFF
OFF
OFFOFF
ECE 5028
PCI EXPRESS
Lane 1
Lane 2
MINI CARD-1 WWAN
MINI CARD-2 WLAN
8
9
1
2
3
4
DESTINATION
Docking
WWAN
None
None
None
None
PCI TABLE
Lane 3
PCI DEVICE IDSEL
OZ711
REQ#/GNT#
REQ#1 / GNT#1AD17 PIRQD
PIRQ
Lane 4
Lane 5
Lane 6
A A
AD24 REQ#0 / GNT#0
PIRQADocking
None
None
None
GIGA LAN
5
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
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Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Index and Config.
LA-3302P
366Monday, February 26, 2007
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4
3
2
1
RUN_ON
ADAPTER
D D
+PWR_SRC
FDS4435
(Q24)
ISL6236
(PU25)
M_ON
GFX_CORE_ON
+INV_PWR_SRC
+1.25V_M
+GPU_CORE
RUN_ON
MAX1510E
(PU26)
MAX1510E
(PU26)
+1.25V_RUN
+1.05V_M
BATTERY
RUN_ON
SI4810DY
(Q58)
+15V_ALW
+5V_RUNSI4810DY
(Q52)
M_ON
SI4800BDY
(Q67)
CHARGER
ISL6260
C C
SUS_ON
+5V_SUS
+3.3V_SUS
(PU11) (PU6)
RUNPWROK
+VCC_CORE
ISlL88550_AVDD
+1.8V_SUS +0.9V_DDR_VTT
ISL88550A
DDR_ON
ISL6236
(PU21)
1.05V_RUN_ON
1.5V_RUN_ON
ISL6236
(PU20)
+1.05V_VCCP +1.5V_RUN
ALWON
ALWON
+5V_ALW
+3.3V_ALW
ENAB_3VLAN
SI3456BDV
RUN_ON
(Q44)
RUN_ON
B B
MAX9789A
AUDIO_AVDD_ON
SI3456BDV
(Q54)
HDDC_EN#
SI3456SI3456BDV
(Q48)(Q56) (U37)
MODC_EN#
+3.3V_LAN
CTRL_18
+3.3V_RUN
CTRL_10
+3.3V_M
BCP69 BCP69
+5V_HDD
+5V_MOD
(Q45)
+VDDA
(Q46)
+1.8VRUN
A A
+1.8V_LAN +1.0V_LAN
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Power Rail
LA-3302P
466Monday, February 26, 2007
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AJ26
ICH_SMBCLK
ICH_SMBDATA
ICH8-M
D D
AD19
2.2K
2.2K
4
+3.3V_SUS
WWAN
SMBUS Address [TBD]
3
3032
C8C7
Intel LAN
SMBUS Address [TBD]
32 30
2N7002
2N7002
2N7002
2N7002
WLAN_SMBCLK
WLAN_SMBDATA
2.2K
2.2K
2
MEM_SCLK
MEM_SDATA
+3.3V_WLAN
WLAN
2.2K
2.2K
@ 0
+3.3V_RUN
197
195
DIMMA
197
195
DIMMB
CLK_SCLK@ 0
CLK_SDATA
1
SMBUS Address [TBD]
SMBUS Address [TBD]
SMBUS Address [TBD]
8.2K
8.2K
8
LCD_SMBCLK
7
C C
LCD_SMDATA
4.7K
4.7K
100
THRM_SMBCLK
99
THRM_SMBDAT
+3.3V_ALW
+3.3V_ALW
6
5
10
9
12
11
INVERTER
(JLVDS)
Charger
EMC4001
SMBUS Address [TBD]
SMBUS Address [TBD]
SMBUS Address [TBD]
2.2K
SBAT_SMBCLK
10
SBAT_SMBDAT
SIO
9
2.2K
2.2K
111
PBAT_SMBCLK
PBAT_SMBDAT
112
B B
2.2K
+3.3V_ALW
100 ohm
100 ohm
+3.3V_ALW
100 ohm
100 ohm
3
4
3
4
9
10
2'nd
BATTERY
BATTERY
CONN
CHARGER
SMBUS Address [TBD]
SMBUS Address [TBD]
SMBUS Address [TBD]
8.2K
+5V_ALW
6
5
DOCKING
SMBUS Address [TBD]
MEC 5025
6
5
8.2K
DOCK_SMB_CLK
DOCK_SMB_DAT
2.2K
2.2K
CKG_SMBDAT
12
CKG_SMBCLK
13
2N7002
2N7002
+3.3V_RUN
CLK_SDATA
CLK_SCLK
17
16
CLK GEN
SMBUS Address [TBD]
A A
Compal Electronics, Inc.
SMBUS TOPOLOGY
LA-3302P
566Monday, February 26, 2007
1
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Title
Size Document Number Rev
4
3
2
Date: Sheet
5
+3.3V_RUN
R435
@
1 2
0_0402_5%~D
CKG_SMBDAT39
D D
+3.3V_RUN
CKG_SMBCLK39
FSC FSB FSA CPU
CLKSEL2 CLKSEL0CLKSEL1
1 3
1 3
1 2
R440
@
0_0402_5%~D
000
1
00
1
0
*
0
1
C C
1
1
11
0
11
00
1
0
1
0
1
R265
D
S
Q34
2N7002W-7-F_SOT323-3~D
G
2
2
G
Q35
2N7002W-7-F_SOT323-3~D
D
S
SRC
MHz
MHz
100
266
100
133
100
200
100
166
100
333
100
100
100
400
200 100 33.3
Table : ICS954305AK
CPU_BSEL CPU_BSEL2(FSC) CPU_BSEL1(FSB)
133
166
+3.3V_RUN
R290
B B
10K_0402_5%~D
1 2
PCI_PCM
+3.3V_RUN
12
R304
10K_0402_5%~D
PCI_ICH
0
0
CLK_NV_27M52
84.5_0402_1%~D
Populate R697,R833 for G72MV
Populate R286 for G86MV.
R833,R286 place overlap
PGMODE
ITP_EN
+3.3V_RUN +3.3V_RUN
12
R318
10K_0402_5%~D
A A
PCI_LOM
12
R319
@
10K_0402_5%~D
12
R329
@
10K_0402_5%~D
FSA
12
R391
@
10K_0402_5%~D
*
TME
*
FCTSEL1 PIN43 PIN44 PIN47 PIN48
0=UMA
*
0=UMA
1=DIS
12
12
R266
2.2K_0402_5%~D
2.2K_0402_5%~D
CLK_SDATA
CLK_SCLK
PCI
MHz
33.3
33.3
33.3
33.3
33.3
33.3
Place crystal within
33.3
500 mils of CK410
CLK_ICH_48M23
CLK_SMC_48M31
CPU_MCH_BSEL08,10
CPU_MCH_BSEL18,10
CPU_MCH_BSEL28,10
CLK_PCI_TPM28
0
1
R697
1@
0
1
0
1
Normal Operation
0
Trusted Mode Enabled
1
CLK_PCI_DOCK36
CLK_PCI_PCM30
CLK_PCI_502539
CLK_PCI_501838
CLK_ICH_14M23
CLK_SIO_14M38
CLK_NVSS_27M52
12
CLK_PCI_ICH21
CLK_PWRGD23
PIN 9
VTT_PWRGD#/PD
CKPWRGD/PD#
PIN 37
Pin 5/6 as SRC_10
Pin 5/6 as CPU_ITP
PIN 32
DOT96T DOT96C 96/100M_T 96/100M_C
27M_out 27M SSout SRCT0 SRC C0
1=Disc. GRFX down
5
+CK_VDD_48
1
C99
2
4.7U_0603_6.3V4Z~D
1
C708
2
3.3P_0402_50V8C~D
C483
27P_0402_50V8J~D
C484
33P_0402_50V8J~D
CLK_NVSS_27M
4
1
C471
2
0.1U_0402_16V4Z~D
1
C799
2
0.047U_0402_16V4Z~D
CLK_SMC_48MCLK_ICH_48M
1
2
X1
14.31818MHz_20P_1BX14318CC1A~D
12
12
12
CLK_ICH_48M
CLK_SMC_48M
CLK_PCI_TPM
CLK_PCI_DOCK
CLK_PCI_PCM
CLK_PCI_5025
CLK_PCI_5018
CLK_ICH_14M
CLK_SIO_14M
CLK_NV_27M
CLK_PCI_ICH
CLK_PWRGD
+3.3V_RUN
4
1 2
L28
BLM21PG600SN1D_0805~D
L87
0.047U_0402_16V4Z~D
0_0402_5%~D
1 2
R298
CLK_SCLK34
CLK_SDATA34
R271
12
12
12
12
12
12
+CK_VDD_MAIN2
1 2
BLM21PG600SN1D_0805~D
+CK_VDD_REF
1
C189
2
C774
3.3P_0402_50V8C~D
R273 15_0402_5%~D
R275 15_0402_5%~D
1 2
R309 2.2K_0402_5%~D
1 2
R314 8.2K_0402_5%~D
1 2
R277 33_0402_5%~D
R596 33_0402_5%~D
R280 33_0402_5%~D
R282 15_0402_5%~D
R333 15_0402_5%~D
1 2
R284 15_0402_5%~D
1 2
R285 15_0402_5%~D
1 2
R286 33_0402_5%~D 2@
1 2
R833 147_0402_1%~D1@
1 2
R287 33_0402_5%~D
1 2
R291 33_0402_5%~D
R295
@
10K_0402_5%~D
1 2
@
1 2
10K_0402_5%~D
R760
1 2
1 2
R758 2.2_0603_5%~D
+CK_VDD_MAIN+3.3V_RUN
1_0603_5%~D
CLK_XTAL_IN
CLK_XTAL_OUT
FSA
FSC
PCI_LOM
PCI_DOCK
PCI_PCM
PCI_SIO
CLKREF
DOT96
CLK_NVSS
PCI_ICH
PGMODE
CLK_SCLK
CLK_SDATA
3
+CK_VDD_MAIN
1
1
1
C474
C473
C472
2
10U_0805_10V4Z~D
1
C480
2
10U_0805_10V4Z~D
R759
1 2
2.2_0603_5%~D
U28
1
49
54
65
30
36
+CK_VDD_REF
+CK_VDD_48
12
18
40
20
19
41
45
23
34
33
32
27
22
43
44
37
39
9
16
17
4
15
21
31
35
42
68
73
74
75
76
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
2
1
2
VDD_SRC
VDD_SRC
VDD_SRC
VDD_SRC
VDD_PCI
VDD_PCI
VDD_CPU
VDD_REF
VDD_48
XTAL_IN
XTAL_OUT
USB_48MHz/FSLA
FSL_B/TEST_MODE
REF_0/FSL_C/TEST_SEL
PCICLK4/FCT_SEL
PCICLK3
PCICLK2/TME
PCICLK1
REF_1
DOT_96/27M
DOT_96#/27M_SS
PCICLK_F0/ITP_EN
CKPWRGD/PD#
PGMODE
SMBCLK
SMBDAT
VSS_SRC
VSS_CPU
VSS_REF
VSS_PCI
VSS_PCI
VSS_48
VSS_SRC
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
0.1U_0402_16V4Z~D
1
C481
2
0.1U_0402_16V4Z~D
SLG8LP550
C482
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
C475
2
2
0.1U_0402_16V4Z~D
+CK_VDD_A
VDD_A
VSS_A
PCI_STP#
CPU_STP#
CPU_1
CPU_1#
CPU_0
CPU_0#
CPU_ITP/SRC_10
CPU_ITP#/SRC_10#
SRC_9
SRC_9#
CLKREQ_9#
SRC_8
SRC_8#
CLKREQ_8#
SRC_7
SRC_7#
CLKREQ_7#
SRC_6
SRC_6#
CLKREQ_6#
SRC_5
SRC_5#
CLKREQ_5#
SRC_4
SRC_4#
CLKREQ_4#
SRC_3
SRC_3#
CLKREQ_3#
SRC_2
SRC_2#
CLKREQ_2#
SRC_1/SATA
SRC_1#/SATA#
CLKREQ_1#
LCD_CLK/SRC_0
LCD_CLK#/SRC_0#
SLG8LP550_QFN72~D
1
C476
2
0.1U_0402_16V4Z~D
7
8
25
24
11
10
14
13
6
5
3
2
72
70
69
71
66
67
38
63
64
62
60
61
29
58
59
57
55
56
28
52
53
26
50
51
46
47
48
C477
0.1U_0402_16V4Z~D
H_STP_PCI#
H_STP_CPU#
MCH_BCLK
MCH_BCLK#
CPU_BCLK
CPU_BCLK#
CPU_ITP
CPU_ITP#
PCIE_MINI1
PCIE_MINI1#
PCIE_MINI2
PCIE_MINI2#
PCIE_ICH
PCIE_ICH#
PCIE_LOM
PCIE_LOM#
PCIE_VGA
PCIE_VGA#
MCH_3GPLL
MCH_3GPLL#
PCIE_SATA
PCIE_SATA#
2
1
1
C478
2
2
4.7U_0603_6.3V4Z~D
1 2
R267 33_0402_5%~D
1 2
R268 33_0402_5%~D
1 2
R269 33_0402_5%~D
1 2
R270 33_0402_5%~D
1 2
R272 33_0402_5%~D
1 2
R274 33_0402_5%~D
1 2
R311 33_0402_5%~D
1 2
R313 33_0402_5%~D
1 2
R306 33_0402_5%~D
1 2
R307 33_0402_5%~D
1 2
R288 33_0402_5%~D
1 2
R289 33_0402_5%~D
1 2
R302 33_0402_5%~D
1 2
R303 33_0402_5%~D
1 2
R299 33_0402_5%~D
1 2
R168 33_0402_5%~D
1 2
R293 33_0402_5%~D
1 2
R294 33_0402_5%~D
1 2
R419 475_0402_1%~D
1 2
R279 33_0402_5%~D
1 2
R281 33_0402_5%~D
2
C479
0.047U_0402_16V4Z~D
1
+3.3V_RUN
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_CPU_ITP
CLK_CPU_ITP#
CLK_PCIE_MINI1
CLK_PCIE_MINI1#
CLK_PCIE_MINI2
CLK_PCIE_MINI2#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_PCIE_LOM
CLK_PCIE_LOM#
CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_SATA
CLK_PCIE_SATA#
MINI1CLK_REQ#
MINI2CLK_REQ#
CLK_3GPLLREQ#
SATA_CLKREQ#
LOM_CLKREQ#
H_STP_PCI# 23
H_STP_CPU# 23
CLK_MCH_BCLK 10
CLK_MCH_BCLK# 10
CLK_CPU_BCLK 7
CLK_CPU_BCLK# 7
CLK_CPU_ITP 7
CLK_CPU_ITP# 7
CLK_PCIE_MINI1 34
CLK_PCIE_MINI1# 34
MINI1CLK_REQ# 34
CLK_PCIE_MINI2 34
CLK_PCIE_MINI2# 34
MINI2CLK_REQ# 34
CLK_PCIE_ICH 23
CLK_PCIE_ICH# 23
CLK_PCIE_LOM 28
CLK_PCIE_LOM# 28
LOM_CLKREQ# 28
CLK_PCIE_VGA 52
CLK_PCIE_VGA# 52
CLK_MCH_3GPLL 10
CLK_MCH_3GPLL# 10
CLK_3GPLLREQ# 10
CLK_PCIE_SATA 22
CLK_PCIE_SATA# 22
SATA_CLKREQ# 23
1 2
R315 10K_0402_5%~D
1 2
R310 10K_0402_5%~D
R297 10K_0402_5%~D
R283 10K_0402_5%~D
R301 10K_0402_5%~D
1 2
1 2
1 2
CLK_ICH_14M
1
2
CLK_SIO_14M
1
2
CLK_PCI_TPM
1
2
CLK_PCI_DOCK
1
2
CLK_PCI_PCM
1
2
CLK_PCI_5025
1
2
CLK_PCI_5018
1
2
CLK_PCI_ICH
1
2
C775
3.3P_0402_50V8C~D
@
C776
3.3P_0402_50V8C~D
@
C777
3.3P_0402_50V8C~D
@
C778
3.3P_0402_50V8C~D
@
C779
3.3P_0402_50V8C~D
@
C780
3.3P_0402_50V8C~D
@
C781
3.3P_0402_50V8C~D
@
C785
3.3P_0402_50V8C~D
@
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Clock Generator
LA-3302P
1
666Thursday, March 01, 2007
0.4
of
5
hexainf@hotmail.com
GRATIS - FOR FREE
4
3
2
1
H_A#[3..35]10
D D
H_ADSTB#010
H_REQ#010
H_REQ#110
H_REQ#210
H_REQ#310
H_REQ#410
C C
H_ADSTB#110
H_A20M#22
H_FERR#22
H_IGNNE#22
H_STPCLK#22
H_INTR22
H_NMI22
H_SMI#22
B B
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1
H_A20M#
H_FERR#
H_IGNNE#
H_STPCLK#
H_INTR
H_NMI
H_SMI#
JCPUA
J4
A[3]#
L5
A[4]#
L4
A[5]#
K5
A[6]#
M3
A[7]#
N2
A[8]#
J1
A[9]#
N3
A[10]#
P5
A[11]#
P2
A[12]#
L2
A[13]#
P4
A[14]#
P1
A[15]#
R1
A[16]#
M1
ADSTB[0]#
K3
REQ[0]#
H2
REQ[1]#
K2
REQ[2]#
J3
REQ[3]#
L1
REQ[4]#
Y2
A[17]#
U5
A[18]#
R3
A[19]#
W6
A[20]#
U4
A[21]#
Y5
A[22]#
U1
A[23]#
R4
A[24]#
T5
A[25]#
T3
A[26]#
W2
A[27]#
W5
A[28]#
Y4
A[29]#
U2
A[30]#
V4
A[31]#
W3
A[32]#
AA4
A[33]#
AB2
A[34]#
AA3
A[35]#
V1
ADSTB[1]#
A6
A20M#
A5
FERR#
C4
IGNNE#
D5
STPCLK#
C6
LINT0
B4
LINT1
A3
SMI#
M4
RSVD[01]
N5
RSVD[02]
T2
RSVD[03]
V3
RSVD[04]
B2
RSVD[05]
C3
RSVD[06]
D2
RSVD[07]
D22
RSVD[08]
D3
RSVD[09]
F6
RSVD[10]
TYCO_1-1674770-2_Merom~D
ADDR GROUP 0
ADDR GROUP 1
ICH
+1.05V_VCCP
DEFER#
DRDY#
DBSY#
LOCK#
RESET#
CONTROLXDP/ITP SIGNALS
TRDY#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
THERMAL
PROCHOT#
THERMDA
THERMDC
THERMTRIP#
H CLK
BCLK[0]
BCLK[1]
RESERVED
ADS#
BNR#
BPRI#
BR0#
IERR#
INIT#
RS[0]#
RS[1]#
RS[2]#
HIT#
HITM#
TCK
TDI
TDO
TMS
TRST#
DBR#
R327
56_0402_5%~D
1 2
H1
E2
G5
H5
F21
E1
F1
D20
B3
H4
C1
F3
F4
G3
G2
G6
E4
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
D21
A24
B25
C7
A22
A21
H_ADS#
H_BNR#
H_BPRI#
H_DEFER#
H_DRDY#
H_DBSY#
H_BR0#
H_IERR#
H_INIT#
H_LOCK#
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
H_HIT#
H_HITM#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
ITP_DBRESET#
H_THERMTRIP#
CLK_CPU_BCLK
CLK_CPU_BCLK#
H_THERMTRIP#
H_INIT# 22
H_LOCK# 10
H_RESET# 10
H_RS#0 10
H_RS#1 10
H_RS#2 10
H_TRDY# 10
T47 PAD~D
T48 PAD~D
T49 PAD~D
T50 PAD~D
T51 PAD~D
T52 PAD~D
ITP_DBRESET# 23,38
EC_CPU_PROCHOT#
H_THERMDA
H_THERMDC
1
2
H_ADS# 10
H_BNR# 10
H_BPRI# 10
H_DEFER# 10
H_DRDY# 10
H_DBSY# 10
H_BR0# 10
H_HIT# 10
H_HITM# 10
C417
2200P_0402_50V7K~D
H_THERMTRIP# 18
CLK_CPU_BCLK 6
CLK_CPU_BCLK# 6
R320
12
56_0402_5%~D
+1.05V_VCCP
H_RESET#
+1.05V_VCCP
12
R323
56_0402_5%~D
EC_CPU_PROCHOT# 39
H_THERMDA 18
H_THERMDC 18
H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil
R321
22.6_0402_1%~D
1 2
CLK_CPU_ITP6
CLK_CPU_ITP#6
+1.05V_VCCP
ITP_DBRESET#
CLK_CPU_ITP
CLK_CPU_ITP#
+1.05V_VCCP
+3.3V_SUS
+1.05V_VCCP
@
0.1U_0402_16V4Z~D
1
1
C486
C485
2
2
Place near JITP
R324
150_0402_5%~D
1 2
R325
51_0402_5%~D
R326
51_0402_1%~D
R328
39_0402_1%~D
R330
150_0402_5%~D
This shall place near CPU
R331
649_0402_1%~D
1 2
R332
27_0402_1%~D
JITP
28
VTT1
27
VTT0
26
VTAP
25
DBR#
24
DBA#
23
BPM0#
22
GND5
21
BPM1#
20
GND4
19
BPM2#
18
GND3
17
BPM3#
16
GND2
15
BPM4#
14
GND1
13
BPM5#
12
RESET#
11
FBO
10
GND0
9
BCLKP
8
BCLKN
7
TDO
6
NC2
5
TCK
4
NC1
3
TRST#
2
TMS
1
TDI
@
0.1U_0402_16V4Z~D
ITP_DBRESET#
ITP_TDO
H_RESET#
ITP_TMS
ITP_TDI
ITP_TRST#
ITP_TCK
29
30
GND6
GND7
JCPUD
A4
VSS[001]
A8
VSS[002]
A11
VSS[003]
A14
VSS[004]
A16
VSS[005]
A19
VSS[006]
A23
VSS[007]
AF2
VSS[008]
B6
VSS[009]
B8
VSS[010]
B11
VSS[011]
B13
VSS[012]
B16
VSS[013]
B19
VSS[014]
B21
VSS[015]
B24
VSS[016]
C5
VSS[017]
C8
VSS[018]
C11
VSS[019]
C14
VSS[020]
C16
VSS[021]
C19
VSS[022]
C2
VSS[023]
C22
VSS[024]
C25
VSS[025]
D1
MOLEX_52435-2891_28P~D@
VSS[026]
D4
VSS[027]
D8
VSS[028]
D11
VSS[029]
D13
VSS[030]
D16
VSS[031]
D19
VSS[032]
D23
VSS[033]
D26
VSS[034]
E3
VSS[035]
E6
VSS[036]
E8
VSS[037]
E11
VSS[038]
E14
VSS[039]
E16
VSS[040]
E19
VSS[041]
E21
VSS[042]
E24
VSS[043]
F5
VSS[044]
F8
VSS[045]
F11
VSS[046]
F13
VSS[047]
F16
VSS[048]
F19
VSS[049]
F2
VSS[050]
F22
VSS[051]
F25
VSS[052]
G4
VSS[053]
G1
VSS[054]
G23
VSS[055]
G26
VSS[056]
H3
VSS[057]
H6
VSS[058]
H21
VSS[059]
H24
VSS[060]
J2
VSS[061]
J5
VSS[062]
J22
VSS[063]
J25
VSS[064]
K1
VSS[065]
K4
VSS[066]
K23
VSS[067]
K26
VSS[068]
L3
VSS[069]
L6
VSS[070]
L21
VSS[071]
L24
VSS[072]
M2
VSS[073]
M5
VSS[074]
M22
VSS[075]
M25
VSS[076]
N1
VSS[077]
N4
VSS[078]
N23
VSS[079]
N26
VSS[080]
P3
VSS[081]
TYCO_1-1674770-2_Merom~D
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Merom Processor(1/2)
LA-3302P
766Thursday, March 01, 2007
1
0.4
of
5
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
Size Document Number Rev
Date: Sheet
5
4
3
2
1
+VCC_CORE +VCC_CORE
D D
C C
B B
R335
@
1 2
1K_0402_5%~D
A A
H_D#[0..63]10
H_DSTBN#010
H_DSTBP#010
H_DINV#010
H_DSTBN#110
H_DSTBP#110
H_DINV#110
V_CPU_GTLREF
CPU_MCH_BSEL06,10
CPU_MCH_BSEL16,10
CPU_MCH_BSEL26,10
TEST1
TEST2
TEST4
TEST6
2
R394
C490
R336
@
1 2
1K_0402_5%~D
Place C490 close to the
CPU_TEST4 pin. Make sure
CPU_TEST4 routing is
reference to GND and away
from other noisy signal.
@
@
1
0_0402_5%~D
1 2
0.1U_0402_16V4Z~D
5
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
CPU_MCH_BSEL0
CPU_MCH_BSEL1
CPU_MCH_BSEL2
For the purpose of testability, route these signals
through a ground referenced Z0 = 55ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope connection.
FSB
533
667
800
JCPUB
E22
D[0]#
F24
D[1]#
E26
D[2]#
G22
D[3]#
F23
D[4]#
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25
N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24
AD26
C23
D25
C24
AF26
AF1
A26
B22
B23
C21
T30PAD~D
T31PAD~D
DATA GRP 0 DATA GRP 1
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
GTLREF
MISC
TSET1
TEST2
TEST3
TEST4
TEST5
TEST6
BSEL[0]
BSEL[1]
BSEL[2]
TYCO_1-1674770-2_Merom~D
TEST3
TEST5
DATA GRP 2DATA GRP 3
DSTBN[2]#
DSTBP[2]#
DINV[2]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
COMP[0]
COMP[1]
COMP[2]
COMP[3]
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
BCLK BSEL2 BSEL 1 BSEL0
133
001
166
200
100
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
SLP#
PSI#
4
Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
R26
U26
AA1
Y1
E5
B5
D24
D6
D7
AE6
110
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3
COMP0
COMP1
COMP2
COMP3
H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#
V_CPU_GTLREF
+1.05V_VCCP
12
R341
1K_0402_1%~D
12
R344
2K_0402_1%~D
H_DPRSTP# 10,22,48
H_DPSLP# 22
H_DPWR# 10
H_PWRGOOD 22
H_CPUSLP# 10
H_PSI# 48
Layout close CPU PIN AD26
55 ohm, 0.5 inch (max)
H_DSTBN#2 10
H_DSTBP#2 10
H_DINV#2 10
H_DSTBN#3 10
H_DSTBP#3 10
H_DINV#3 10
27.4_0402_1%~D
54.9_0402_1%~D
12
12
R338
R337
Resistor placed within 0.5" of
CPU pin.Trace should be at least
25 mils away from any other
toggling signal. COMP0, COMP2
trace should be 27.4 ohm.
COMP1, COMP3 should be 55
ohm.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
12
R339
27.4_0402_1%~D
54.9_0402_1%~D
12
R340
JCPUC
A7
VCC[001]
A9
VCC[002]
A10
VCC[003]
A12
VCC[004]
A13
VCC[005]
A15
VCC[006]
A17
VCC[007]
A18
VCC[008]
A20
VCC[009]
B7
VCC[010]
B9
VCC[011]
B10
VCC[012]
B12
VCC[013]
B14
VCC[014]
B15
VCC[015]
B17
VCC[016]
B18
VCC[017]
B20
VCC[018]
C9
VCC[019]
C10
VCC[020]
C12
VCC[021]
C13
VCC[022]
C15
VCC[023]
C17
VCC[024]
C18
VCC[025]
D9
VCC[026]
D10
VCC[027]
D12
VCC[028]
D14
VCC[029]
D15
VCC[030]
D17
VCC[031]
D18
VCC[032]
E7
VCC[033]
E9
VCC[034]
E10
VCC[035]
E12
VCC[036]
E13
VCC[037]
E15
VCC[038]
E17
VCC[039]
E18
VCC[040]
E20
VCC[041]
F7
VCC[042]
F9
VCC[043]
F10
VCC[044]
F12
VCC[045]
F14
VCC[046]
F15
VCC[047]
F17
VCC[048]
F18
VCC[049]
F20
VCC[050]
AA7
VCC[051]
AA9
VCC[052]
AA10
VCC[053]
AA12
VCC[054]
AA13
VCC[055]
AA15
VCC[056]
AA17
VCC[057]
AA18
VCC[058]
AA20
VCC[059]
AB9
VCC[060]
AC10
VCC[061]
AB10
VCC[062]
AB12
VCC[063]
AB14
VCC[064]
AB15
VCC[065]
AB17
VCC[066]
AB18
VCC[067]
TYCO_1-1674770-2_Merom~D
2
AB20
VCC[068]
AB7
VCC[069]
AC7
VCC[070]
AC9
VCC[071]
AC12
VCC[072]
AC13
VCC[073]
AC15
VCC[074]
AC17
VCC[075]
AC18
VCC[076]
AD7
VCC[077]
AD9
VCC[078]
AD10
VCC[079]
AD12
VCC[080]
AD14
VCC[081]
AD15
VCC[082]
AD17
VCC[083]
AD18
VCC[084]
AE9
VCC[085]
AE10
VCC[086]
AE12
VCC[087]
AE13
VCC[088]
AE15
VCC[089]
AE17
VCC[090]
AE18
VCC[091]
AE20
VCC[092]
AF9
VCC[093]
AF10
VCC[094]
AF12
VCC[095]
AF14
VCC[096]
AF15
VCC[097]
AF17
VCC[098]
AF18
VCC[099]
AF20
VCC[100]
G21
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
VCCA[1]
VCCA[2]
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
B26
C26
AD6
AF5
AE5
AF4
AE3
AF3
AE2
AF7
AE7
VCCSENSE
VSSSENSE
VID0
VID1
VID2
VID3
VID4
VID5
VID6
220U_D2_4VY_R15M~D
1
C487
+
2
Length match within 25 mils, Z0=27.4 ohm
Place R342 and R343 near CPU
+VCC_CORE
R342
R343
VCCSENSE
VSSSENSE
1 2
100_0402_1%~D
1 2
100_0402_1%~D
Route VCCSENSE and VSSSENSE trace at
27.4 ohms, 7 mils spaci n g and 1 inch (max)
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
+1.05V_VCCP
CRB was 270uF
10U_0805_10V4Z~D
0.01U_0402_16V7K~D
VID0 48
VID1 48
VID2 48
VID3 48
VID4 48
VID5 48
VID6 48
VCCSENSE 48
VSSSENSE 48
C488
1
2
Compal Electronics, Inc.
Merom Processor(2/2)
LA-3302P
1
+1.5V_RUN
C489
1
2
866Thursday, March 01, 2007
0.4
of
5
hexainf@hotmail.com
GRATIS - FOR FREE
+VCC_CORE
Place these inside
socket cavity on L8
(North side
Secondary)
D D
Place these inside
socket cavity on L8
(Sorth side
Secondary)
Place these inside
socket cavity on L8
(North side
Primary)
Place these inside
socket cavity on L8
(Sorth side
Primary)
C C
1
2
+VCC_CORE
1
2
+VCC_CORE
1
2
+VCC_CORE
1
2
C329
10U_0805_4VAM~D
C222
10U_0805_4VAM~D
C363
10U_0805_4VAM~D
C364
10U_0805_4VAM~D
1
C330
10U_0805_4VAM~D
2
1
C223
10U_0805_4VAM~D
2
1
C64
10U_0805_4VAM~D
2
1
C50
10U_0805_4VAM~D
2
1
C331
10U_0805_4VAM~D
2
1
C224
10U_0805_4VAM~D
2
1
C65
10U_0805_4VAM~D
2
1
C51
10U_0805_4VAM~D
2
1
C332
10U_0805_4VAM~D
2
1
C225
10U_0805_4VAM~D
2
1
C66
10U_0805_4VAM~D
2
1
C52
10U_0805_4VAM~D
2
4
1
2
1
2
1
2
1
2
C333
10U_0805_4VAM~D
C227
10U_0805_4VAM~D
C67
10U_0805_4VAM~D
C53
10U_0805_4VAM~D
1
C334
10U_0805_4VAM~D
2
1
C226
10U_0805_4VAM~D
2
1
C68
10U_0805_4VAM~D
2
1
C54
10U_0805_4VAM~D
2
1
C335
10U_0805_4VAM~D
2
1
C228
10U_0805_4VAM~D
2
10uF 0805 X6S -> 85 degree C
3
1
C336
10U_0805_4VAM~D
2
1
C229
10U_0805_4VAM~D
2
1
C55
10U_0805_4VAM~D
2
1
C69
10U_0805_4VAM~D
2
1
C190
10U_0805_4VAM~D
2
1
C185
10U_0805_4VAM~D
2
2
1
High Frequence Decoupling
Near VCORE regulator.
+VCC_CORE +VCC_CORE
South Side Secondary
C177
B B
220U_X_2VM_R7M~D
1
1
+
+
C179
C178
2
2
@
220U_X_2VM_R7M~D
220U_X_2VM_R7M~D
1
1
+
+
C338
C366
2
2
@
220U_X_2VM_R7M~D
220U_X_2VM_R7M~D
1
+
2
North Side Secondary
1
+
C365
2
220U_X_2VM_R7M~D
ESR <= 1.5m ohm
Capacitor > 1980uF
1
C870
0.1U_0402_10V7K~D
2
@
1
C871
0.1U_0402_10V7K~D
2
@
1
C872
0.1U_0402_10V7K~D
2
@
1
C873
0.1U_0402_10V7K~D
2
@
BITs WI97837
+1.05V_VCCP
1
C312
0.1U_0402_10V7K~D
2
A A
1
C256
0.1U_0402_10V7K~D
2
1
C293
0.1U_0402_10V7K~D
2
1
C250
0.1U_0402_10V7K~D
2
1
C310
0.1U_0402_10V7K~D
2
1
C264
0.1U_0402_10V7K~D
2
Place these inside
socket cavity on L8
(North side
Secondary)
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
CPU Bypass
LA-3302P
966Monday, February 26, 2007
1
0.4
of
5
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
Size Document Number Rev
Date: Sheet
5
54.9_0402_1%~D
+1.05V_VCCP
12
R347
24.9_0402_1%~D
H_D#[0..63]8
12
R348
54.9_0402_1%~D
R350
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_SWNG
H_RCOMP
H_SCOMP
H_SCOMP#
H_RESET#7
H_CPUSLP#8
12
5
H_RESET#
H_CPUSLP#
H_VREF
H_VREF
2K_0402_1%~D
U29A
E2
H_D#_0
G2
H_D#_1
G7
H_D#_2
M6
H_D#_3
H7
H_D#_4
H3
H_D#_5
G4
H_D#_6
F3
H_D#_7
N8
H_D#_8
H2
H_D#_9
M10
H_D#_10
N12
H_D#_11
N9
H_D#_12
H5
H_D#_13
P13
H_D#_14
K9
H_D#_15
M2
H_D#_16
W10
H_D#_17
Y8
H_D#_18
V4
H_D#_19
M3
H_D#_20
J1
H_D#_21
N5
H_D#_22
N3
H_D#_23
W6
H_D#_24
W9
H_D#_25
N2
H_D#_26
Y7
H_D#_27
Y9
H_D#_28
P4
H_D#_29
W3
H_D#_30
N1
H_D#_31
AD12
H_D#_32
AE3
H_D#_33
AD9
H_D#_34
AC9
H_D#_35
AC7
H_D#_36
AC14
H_D#_37
AD11
H_D#_38
AC11
H_D#_39
AB2
H_D#_40
AD7
H_D#_41
AB1
H_D#_42
Y3
H_D#_43
AC6
H_D#_44
AE2
H_D#_45
AC5
H_D#_46
AG3
H_D#_47
AJ9
H_D#_48
AH8
H_D#_49
AJ14
H_D#_50
AE9
H_D#_51
AE11
H_D#_52
AH12
H_D#_53
AJ5
H_D#_54
AH5
H_D#_55
AJ6
H_D#_56
AE7
H_D#_57
AJ7
H_D#_58
AJ2
H_D#_59
AE5
H_D#_60
AJ3
H_D#_61
AH2
H_D#_62
AH13
H_D#_63
B3
H_SWING
C2
H_RCOMP
W1
H_SCOMP
W2
H_SCOMP#
B6
H_CPURST#
E5
H_CPUSLP#
B9
H_AVREF
A9
H_DVREF
LE88CLPM A0 QM21_FCBGA1299~D
12
R355
1K_0402_1%~D
0.1U_0402_16V4Z~D
12
1
R361
2
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
H_ADSTB#_0
H_ADSTB#_1
H_BPRI#
HOST
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HITM#
H_LOCK#
H_TRDY#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_RS#_0
H_RS#_1
H_RS#_2
+1.05V_VCCP+1.05V_VCCP
H_SWNG
100_0402_1%~D
C496
R362
D D
C C
B B
Layout Note:
H_RCOMP tr ace width
and spacing is 10/20
A A
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_ADS#
H_BNR#
H_HIT#
12
R356
221_0402_1%~D
12
4
H_A#3
J13
H_A#4
B11
H_A#5
C11
H_A#6
M11
H_A#7
C15
H_A#8
F16
H_A#9
L13
H_A#10
G17
H_A#11
C14
H_A#12
K16
H_A#13
B13
H_A#14
L16
H_A#15
J17
H_A#16
B14
H_A#17
K19
H_A#18
P15
H_A#19
R17
H_A#20
B16
H_A#21
H20
H_A#22
L19
H_A#23
D17
H_A#24
M17
H_A#25
N16
H_A#26
J19
H_A#27
B18
H_A#28
E19
H_A#29
B17
H_A#30
B15
H_A#31
E17
H_A#32
C18
H_A#33
A19
H_A#34
B19
H_A#35
N19
H_ADS#
G12
H_ADSTB#0
H17
H_ADSTB#1
G20
H_BNR#
C8
H_BPRI#
E8
H_BR0#
F12
H_DEFER#
D6
H_DBSY#
C10
CLK_MCH_BCLK
AM5
CLK_MCH_BCLK#
AM7
H_DPWR#
H8
H_DRDY#
K7
H_HIT#
E4
H_HITM#
C6
H_LOCK#
G10
H_TRDY#
B7
H_DINV#0
K5
H_DINV#1
L2
H_DINV#2
AD13
H_DINV#3
AE13
H_DSTBN#0
M7
H_DSTBN#1
K3
H_DSTBN#2
AD2
H_DSTBN#3
AH11
H_DSTBP#0
L7
H_DSTBP#1
K2
H_DSTBP#2
AC2
H_DSTBP#3
AJ10
H_REQ#0
M14
H_REQ#1
E13
H_REQ#2
A11
H_REQ#3
H13
H_REQ#4
B12
H_RS#0
E12
H_RS#1
D7
H_RS#2
D8
+1.8V_SUS
R359
3.01K_0402_1%~D
0.1U_0402_16V4Z~D
1
C497
2
4
1K_0402_1%~D
R363
H_A#[3..35] 7
H_ADS# 7
H_ADSTB#0 7
H_ADSTB#1 7
H_BNR# 7
H_BPRI# 7
H_BR0# 7
H_DEFER# 7
H_DBSY# 7
CLK_MCH_BCLK 6
CLK_MCH_BCLK# 6
H_DPWR# 8
H_DRDY# 7
H_HIT# 7
H_HITM# 7
H_LOCK# 7
H_TRDY# 7
H_DINV#0 8
H_DINV#1 8
H_DINV#2 8
H_DINV#3 8
H_DSTBN#0 8
H_DSTBN#1 8
H_DSTBN#2 8
H_DSTBN#3 8
H_DSTBP#0 8
H_DSTBP#1 8
H_DSTBP#2 8
H_DSTBP#3 8
H_REQ#0 7
H_REQ#1 7
H_REQ#2 7
H_REQ#3 7
H_REQ#4 7
H_RS#0 7
H_RS#1 7
H_RS#2 7
12
R353
1K_0402_1%~D
SMRCOMP_VOH
1
12
12
C494
2
SMRCOMP_VOL
1
C498
2
+1.8V_SUS
V_DDR_MCH_REF
1K_0402_1%~D
392_0402_1~D
1
C495
2
2.2U_0603_6.3V6K~D
0.01U_0402_16V7K~D
1
C499
2
2.2U_0603_6.3V6K~D
0.01U_0402_16V7K~D
C491
+1.25V_RUN
R349
R351
3
M_ODT016
M_ODT116
M_ODT217
M_ODT317
T42PAD~D
T43PAD~D
T44PAD~D
T45PAD~D
T46PAD~D
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
M_ODT0
M_ODT1
M_ODT2
M_ODT3
SMRCOMP
SMRCOMP#
SMRCOMP_VOH
SMRCOMP_VOL
V_DDR_MCH_REF
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
DMI_MRX_ITX_N0
DMI_MRX_ITX_N1
DMI_MRX_ITX_N2
DMI_MRX_ITX_N3
DMI_MRX_ITX_P0
DMI_MRX_ITX_P1
DMI_MRX_ITX_P2
DMI_MRX_ITX_P3
DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3
DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3
CL_CLK0
CL_DATA0
ICH_CL_PWROK
CL_RST0#
CL_VREF
CLK_3GPLLREQ#
MCH_ICH_SYNC#
R774 0_0402_5%~D
R357
20K_0402_5%~D
M_CLK_DDR016
M_CLK_DDR116
M_CLK_DDR217
M_CLK_DDR317
M_CLK_DDR#016
M_CLK_DDR#116
M_CLK_DDR#217
M_CLK_DDR#317
DDR_CKE0_DIMMA16
DDR_CKE1_DIMMA16
DDR_CKE2_DIMMB17
DDR_CKE3_DIMMB17
DDR_CS0_DIMMA#16
DDR_CS1_DIMMA#16
DDR_CS2_DIMMB#17
DDR_CS3_DIMMB#17
R345
20_0402_1%~D
1 2
1 2
R346
20_0402_1%~D
1
1
C492
2
2
CLK_MCH_3GPLL6
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
12
12
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1
C493
0.1U_0402_16V4Z~D
2
3
CLK_MCH_3GPLL#6
DMI_MRX_ITX_N023
DMI_MRX_ITX_N123
DMI_MRX_ITX_N223
DMI_MRX_ITX_N323
DMI_MRX_ITX_P023
DMI_MRX_ITX_P123
DMI_MRX_ITX_P223
DMI_MRX_ITX_P323
DMI_MTX_IRX_N023
DMI_MTX_IRX_N123
DMI_MTX_IRX_N223
DMI_MTX_IRX_N323
DMI_MTX_IRX_P023
DMI_MTX_IRX_P123
DMI_MTX_IRX_P223
DMI_MTX_IRX_P323
CL_CLK023
CL_DATA023
ICH_CL_PWROK23,39
CL_RST0#23
CLK_3GPLLREQ#6
MCH_ICH_SYNC#23
AV29
SM_CK_0
BB23
SM_CK_1
BA25
SM_CK_3
AV23
SM_CK_4
AW30
SM_CK#_0
BA23
SM_CK#_1
AW25
SM_CK#_3
AW23
SM_CK#_4
BE29
SM_CKE_0
AY32
SM_CKE_1
BD39
SM_CKE_3
BG37
SM_CKE_4
BG20
SM_CS#_0
BK16
SM_CS#_1
BG16
SM_CS#_2
BE13
SM_CS#_3
BH18
SM_ODT_0
BJ15
SM_ODT_1
BJ14
SM_ODT_2
BE16
SM_ODT_3
BL15
SM_RCOMP
BK14
SM_RCOMP#
BK31
SM_RCOMP_VOH
BL31
SM_RCOMP_VOL
AR49
SM_VREF_0
AW4
SM_VREF_1
B42
DPLL_REF_CLK
C42
DPLL_REF_CLK#
H48
DPLL_REF_SSCLK
H47
DPLL_REF_SSCLK#
K44
PEG_CLK
K45
PEG_CLK#
AN47
DMI_RXN_0
AJ38
DMI_RXN_1
AN42
DMI_RXN_2
AN46
DMI_RXN_3
AM47
DMI_RXP_0
AJ39
DMI_RXP_1
AN41
DMI_RXP_2
AN45
DMI_RXP_3
AJ46
DMI_TXN_0
AJ41
DMI_TXN_1
AM40
DMI_TXN_2
AM44
DMI_TXN_3
AJ47
DMI_TXP_0
AJ42
DMI_TXP_1
AM39
DMI_TXP_2
AM43
DMI_TXP_3
E35
GFX_VID_0
A39
GFX_VID_1
C38
GFX_VID_2
B39
GFX_VID_3
E36
GFX_VR_EN
AM49
CL_CLK
AK50
CL_DATA
AT43
CL_PWROK
AN49
CL_RST#
AM50
CL_VREF
H35
SDVO_CTRL_CLK
K36
SDVO_CTRL_DATA
G39
CLK_REQ#
G40
ICH_SYNC#
A37
12
12
TEST_1
R32
TEST_2
THERMTRIP_MCH#
2
R358
56_0402_5%~D
2
1 2
U29B
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD CFG PM NC
DDR MUXINGCLKDMIGRAPHICS VIDMEMISC
LE88CLPM A0 QM21_FCBGA1299~D
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
PM_BM_BUSY#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
THERMTRIP#
DPRSLPVR
+1.05V_VCCP
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
RSTIN#
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
1
P36
P37
R35
N35
AR12
AR13
AM12
AN13
J12
AR37
AM36
AL36
AM37
D20
H10
B51
BJ20
BK22
BF19
BH20
BK18
BJ18
BF23
BG23
BC23
BD24
BH39
AW20
BK20
C48
D47
B44
C44
A35
B37
B36
B34
C34
P27
N27
N24
C21
C23
F23
N23
G23
J20
C20
R24
L23
J23
E23
E20
K23
M20
M24
L32
N33
L35
G41
L39
L36
J36
AW49
AV20
N20
G36
BJ51
BK51
BK50
BL50
BL49
BL3
BL2
BK1
BJ1
E1
A5
C51
B50
A50
A49
BK2
100_0402_5%~D
CFG5
CFG9
CFG16
CFG19
CFG20
PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
ICH_PWRGD
PLTRST1#_R
THERMTRIP_MCH#
DPRSLPVR
R36
1 2
T63 PAD~D
T64 PAD~D
T65 PAD~D
T66 PAD~D
T67 PAD~D
T68 PAD~D
T69 PAD~D
T70 PAD~D
T71 PAD~D
T72 PAD~D
T73 PAD~D
T74 PAD~D
T75 PAD~D
0_0402_5%~D@
0_0402_5%~D
CPU_MCH_BSEL0 6,8
CPU_MCH_BSEL1 6,8
CPU_MCH_BSEL2 6,8
CFG5 12
CFG9 12
CFG16 12
CFG19 12
CFG20 12
PM_BMBUSY# 23
H_DPRSTP# 8,22,48
PM_EXTTS#0 16
PM_EXTTS#1 17
ICH_PWRGD 23,42
THERMTRIP_MCH# 18
DPRSLPVR 23,48
PM_EXTTS#0
PM_EXTTS#1
R589
12
R583
PLTRST1#PLTRST1#_R
12
+3.3V_RUN
R352
10K_0402_5%~D
12
R354
10K_0402_5%~D
12
SB_NB_PCIE_RST# 21
PLTRST1# 21
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Crestline(1 of 6)
LA-3302P
10 66Thursday, March 01, 2007
1
of
0.4
5
hexainf@hotmail.com
GRATIS - FOR FREE
D D
4
3
2
1
DDR_A_BS016
DDR_A_BS116
DDR_A_BS216
DDR_A_DM[0..7]16
DDR_A_DQS[0..7]16
C C
DDR_A_DQS#[0..7]16
DDR_A_MA[0..14]16
B B
DDR_A_CAS#16
DDR_A_RAS#16
DDR_A_WE#16
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14 DDR_B_MA14
DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
T10
BB19
BK19
BF29
AT45
BD44
BD42
AW38
AW13
AT46
BE48
BB43
BC37
BB16
AT47
BD47
BC41
BA37
BA16
BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16
BJ29
BL17
BE18
BA19
AY20
BG8
AY5
AN6
BH6
BB2
AP3
BH7
BC1
AP2
SA_BS_0
SA_BS_1
SA_BS_2
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
SA_CAS#
SA_RAS#
SA_WE#
SA_RCVEN#
DDR SYSTEM MEMORY A
LE88CLPM A0 QM21_FCBGA1299~D
U29D
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
DDR_A_D0
AR43
DDR_A_D1 DDR_B_BS1
AW44
DDR_A_D2
BA45
DDR_A_D3
AY46
DDR_A_D4
AR41
DDR_A_D5
AR45
DDR_A_D6
AT42
DDR_A_D7
AW47
DDR_A_D8
BB45
DDR_A_D9
BF48
DDR_A_D10
BG47
DDR_A_D11
BJ45
DDR_A_D12
BB47
DDR_A_D13
BG50
DDR_A_D14
BH49
DDR_A_D15
BE45
DDR_A_D16
AW43
DDR_A_D17
BE44
DDR_A_D18
BG42
DDR_A_D19
BE40
DDR_A_D20
BF44
DDR_A_D21
BH45
DDR_A_D22
BG40
DDR_A_D23
BF40
DDR_A_D24
AR40
DDR_A_D25
AW40
DDR_A_D26
AT39
DDR_A_D27
AW36
DDR_A_D28
AW41
DDR_A_D29
AY41
DDR_A_D30
AV38
DDR_A_D31
AT38
DDR_A_D32
AV13
DDR_A_D33
AT13
DDR_A_D34
AW11
DDR_A_D35
AV11
DDR_A_D36
AU15
DDR_A_D37
AT11
DDR_A_D38
BA13
DDR_A_D39
BA11
DDR_A_D40
BE10
DDR_A_D41
BD10
DDR_A_D42
BD8
DDR_A_D43
AY9
DDR_A_D44
BG10
DDR_A_D45
AW9
DDR_A_D46
BD7
DDR_A_D47
BB9
DDR_A_D48
BB5
DDR_A_D49
AY7
DDR_A_D50
AT5
DDR_A_D51
AT7
DDR_A_D52
AY6
DDR_A_D53
BB7
DDR_A_D54
AR5
DDR_A_D55
AR8
DDR_A_D56
AR9
DDR_A_D57
AN3
DDR_A_D58
AM8
DDR_A_D59
AN10
DDR_A_D60
AT9
DDR_A_D61
AN9
DDR_A_D62
AM9
DDR_A_D63
AN11
DDR_B_BS017
DDR_B_BS117
DDR_B_BS217
DDR_B_DM[0..7]17
DDR_B_DQS[0..7]17
DDR_B_DQS#[0..7]17
DDR_B_MA[0..14]17
DDR_B_CAS#17
DDR_B_RAS#17
DDR_B_WE#17
T11
DDR_B_BS0
DDR_B_BS2
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
SB_RCVEN#SA_RCVEN#
AY17
BG18
BG36
AR50
BD49
BK45
BL39
BH12
AW2
AT50
BD50
BK46
BK39
BJ12
AU50
BC50
BL45
BK38
BK12
BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13
BE24
BE17
AV16
BC17
AY18
BJ7
BF3
BL7
BE2
AV2
BK7
BF2
AV3
SB_BS_0
SB_BS_1
SB_BS_2
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
SB_CAS#
SB_RAS#
SB_WE#
SB_RCVEN#
DDR SYSTEM MEMORY B
LE88CLPM A0 QM21_FCBGA1299~D
U29E
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
AP49
AR51
AW50
AW51
AN51
AN50
AV50
AV49
BA50
BB50
BA49
BE50
BA51
AY49
BF50
BF49
BJ50
BJ44
BJ43
BL43
BK47
BK49
BK43
BK42
BJ41
BL41
BJ37
BJ36
BK41
BJ40
BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12
BJ10
BL9
BK5
BL5
BK9
BK10
BJ8
BJ6
BF4
BH5
BG1
BC2
BK3
BE4
BD3
BJ2
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
DDR_B_D[0..63] 17DDR_A_D[0..63] 16
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Crestline(2 of 6)
LA-3302P
11 66Thursday, March 01, 2007
1
0.4
of
5
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
Size Document Number Rev
Date: Sheet
5
4
+VCC_PEG
3
2
1
R366
U29C
J40
L_BKLT_CTRL
H39
L_BKLT_EN
E39
D D
C C
B B
A A
5
E40
C37
D35
K40
L41
L43
N41
N40
D46
C45
D44
E42
G51
E51
F49
G50
E50
F48
G44
B47
B45
E44
A47
A45
E27
G27
K27
F27
J27
L27
M35
P33
H32
G32
K29
J29
F29
E29
K33
G35
F33
E33
C32
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK
LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
TVA_DAC
TVB_DAC
TVC_DAC
TVA_RTN
TVB_RTN
TVC_RTN
TV_DCONSEL_0
TV_DCONSEL_1
CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_VSYNC
CRT_TVO_IREF
LVDS TV VGA
LE88CLPM A0 QM21_FCBGA1299~D
PEG_COMPI
PEG_COMPO
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PCI-EXPRESS GRAPHICS
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
4
PEGCOMP
N43
M43
J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41
J50
L50
M47
U44
T49
T41
W45
W41
AB50
Y48
AC45
AC41
AH47
AG49
AH45
AG42
N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44
M45
T38
T46
N50
R51
U43
W42
Y47
Y39
AC38
AD47
AC50
AD43
AG39
AE50
AH43
24.9_0402_1%~D
1 2
PEG_MRX_GTX_N0
PEG_MRX_GTX_N1
PEG_MRX_GTX_N2
PEG_MRX_GTX_N3
PEG_MRX_GTX_N4
PEG_MRX_GTX_N5
PEG_MRX_GTX_N6
PEG_MRX_GTX_N7
PEG_MRX_GTX_N8
PEG_MRX_GTX_N9
PEG_MRX_GTX_N10
PEG_MRX_GTX_N11
PEG_MRX_GTX_N12
PEG_MRX_GTX_N13
PEG_MRX_GTX_N14
PEG_MRX_GTX_N15
PEG_MRX_GTX_P0
PEG_MRX_GTX_P1
PEG_MRX_GTX_P2
PEG_MRX_GTX_P3
PEG_MRX_GTX_P4
PEG_MRX_GTX_P5
PEG_MRX_GTX_P6
PEG_MRX_GTX_P7
PEG_MRX_GTX_P8
PEG_MRX_GTX_P9
PEG_MRX_GTX_P10
PEG_MRX_GTX_P11
PEG_MRX_GTX_P12
PEG_MRX_GTX_P13
PEG_MRX_GTX_P14
PEG_MRX_GTX_P15
PEG_MTX_GRX_C_N0
PEG_MTX_GRX_C_N1
PEG_MTX_GRX_C_N2
PEG_MTX_GRX_C_N3
PEG_MTX_GRX_C_N4
PEG_MTX_GRX_C_N5
PEG_MTX_GRX_C_N6
PEG_MTX_GRX_C_N7
PEG_MTX_GRX_C_N8
PEG_MTX_GRX_C_N9
PEG_MTX_GRX_C_N10
PEG_MTX_GRX_C_N11
PEG_MTX_GRX_C_N12
PEG_MTX_GRX_C_N13
PEG_MTX_GRX_C_N14
PEG_MTX_GRX_C_N15
PEG_MTX_GRX_C_P0
PEG_MTX_GRX_C_P1
PEG_MTX_GRX_C_P2
PEG_MTX_GRX_C_P3
PEG_MTX_GRX_C_P4
PEG_MTX_GRX_C_P5
PEG_MTX_GRX_C_P6
PEG_MTX_GRX_C_P7
PEG_MTX_GRX_C_P8
PEG_MTX_GRX_C_P9
PEG_MTX_GRX_C_P10
PEG_MTX_GRX_C_P11
PEG_MTX_GRX_C_P12
PEG_MTX_GRX_C_P13
PEG_MTX_GRX_C_P14
PEG_MTX_GRX_C_P15
CFG5 DMI X2 Select
PEG_MRX_GTX_N[0..15] 52
CFG16
CFG19
PEG_MRX_GTX_P[0..15] 52
CFG20
SDVO_CRTL_DATA
PEG_MTX_GRX_P[0..15]
PEG_MTX_GRX_N[0..15]
PEG_MTX_GRX_C_P0
PEG_MTX_GRX_C_N0
PEG_MTX_GRX_C_P1
PEG_MTX_GRX_C_N1
PEG_MTX_GRX_C_P2
PEG_MTX_GRX_C_P3
PEG_MTX_GRX_C_N3
PEG_MTX_GRX_C_P4 PEG_MTX_GRX_P4
PEG_MTX_GRX_C_N4
PEG_MTX_GRX_C_P5
PEG_MTX_GRX_C_N5
PEG_MTX_GRX_C_P6
PEG_MTX_GRX_C_N6
PEG_MTX_GRX_C_P7
PEG_MTX_GRX_C_N7
PEG_MTX_GRX_C_P8
PEG_MTX_GRX_C_N8
PEG_MTX_GRX_C_P9
PEG_MTX_GRX_C_N9
PEG_MTX_GRX_C_P10
PEG_MTX_GRX_C_N10
PEG_MTX_GRX_C_P11
PEG_MTX_GRX_C_N11
PEG_MTX_GRX_C_P12
PEG_MTX_GRX_C_N12
PEG_MTX_GRX_C_P13
PEG_MTX_GRX_C_N13
PEG_MTX_GRX_C_P14
PEG_MTX_GRX_C_N14
PEG_MTX_GRX_C_P15
PEG_MTX_GRX_C_N15
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
PEG_MTX_GRX_P[0..15] 52
PEG_MTX_GRX_N[0..15] 52
3
C500 0.1U_0402_10V7K~D
1 2
C501 0.1U_0402_10V7K~D
C502 0.1U_0402_10V7K~D
1 2
C504 0.1U_0402_10V7K~D
1 2
C506 0.1U_0402_10V7K~D
1 2
C508 0.1U_0402_10V7K~D
1 2
C510 0.1U_0402_10V7K~D
1 2
C512 0.1U_0402_10V7K~D
1 2
C514 0.1U_0402_10V7K~D
1 2
C516 0.1U_0402_10V7K~D
1 2
C518 0.1U_0402_10V7K~D
1 2
C520 0.1U_0402_10V7K~D
1 2
C522 0.1U_0402_10V7K~D
1 2
C524 0.1U_0402_10V7K~D
1 2
C526 0.1U_0402_10V7K~D
1 2
C528 0.1U_0402_10V7K~D
1 2
C530 0.1U_0402_10V7K~D
1 2
1 2
C503 0.1U_0402_10V7K~D
1 2
C505 0.1U_0402_10V7K~D
1 2
C507 0.1U_0402_10V7K~D
1 2
C509 0.1U_0402_10V7K~D
1 2
C511 0.1U_0402_10V7K~D
1 2
C513 0.1U_0402_10V7K~D
1 2
C515 0.1U_0402_10V7K~D
1 2
C517 0.1U_0402_10V7K~D
1 2
C519 0.1U_0402_10V7K~D
1 2
C521 0.1U_0402_10V7K~D
1 2
C523 0.1U_0402_10V7K~D
1 2
C525 0.1U_0402_10V7K~D
1 2
C527 0.1U_0402_10V7K~D
1 2
C529 0.1U_0402_10V7K~D
1 2
C531 0.1U_0402_10V7K~D
1 2
Strap Pin Table
PCI Express
Graphic Lane
FSB Dynamic
ODT
DMI Lane
Reversal
SDVO/PCIE
Concurrent
Operation
PEG_MTX_GRX_P0
PEG_MTX_GRX_N0
PEG_MTX_GRX_P1
PEG_MTX_GRX_N1
PEG_MTX_GRX_P2
PEG_MTX_GRX_N2PEG_MTX_GRX_C_N2
PEG_MTX_GRX_P3
PEG_MTX_GRX_N3
PEG_MTX_GRX_N4
PEG_MTX_GRX_P5
PEG_MTX_GRX_N5
PEG_MTX_GRX_P6
PEG_MTX_GRX_N6
PEG_MTX_GRX_P7
PEG_MTX_GRX_N7
PEG_MTX_GRX_P8
PEG_MTX_GRX_N8
PEG_MTX_GRX_P9
PEG_MTX_GRX_N9
PEG_MTX_GRX_P10
PEG_MTX_GRX_N10
PEG_MTX_GRX_P11
PEG_MTX_GRX_N11
PEG_MTX_GRX_P12
PEG_MTX_GRX_N12
PEG_MTX_GRX_P13
PEG_MTX_GRX_N13
PEG_MTX_GRX_P14
PEG_MTX_GRX_N14
PEG_MTX_GRX_P15
PEG_MTX_GRX_N15
Low = DMI x 2
High = DMI x 4 (Default)
Low = Reverse LaneCFG9
High = Normal O p e r a t i o n ( Default)
Low=Dynamic O D T Disable
High=Dynamic ODT Enable(default)
Low=Normal (default)
High=Lane Reversed
Low=Only SDVO or PCIEx1 is
operational (defaults)
High=SDVO and P C I E x 1 a r e o p e rating
simultaneously via PEG port
Low=No SDVO Device Present
(default)
High=SDVO Dev i ce Present
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
2
Date: Sheet
R365 4.02K_0402_1%~D@
CFG510
R368 4.02K_0402_1%~D@
CFG910
R372 4.02K_0402_1%~D@
CFG1610
CFG[3:17] have internal pullup
R373 4.02K_0402_1%~D@
CFG1910
R374 4.02K_0402_1%~D@
CFG2010
CFG[18:19] have internal pulldown
Compal Electronics, Inc.
Crestline(3 of 6)
LA-3302P
1 2
1 2
1 2
1 2
1 2
1
+3.3V_RUN
12 66Thursday, March 01, 2007
0.4
of
5
hexainf@hotmail.com
GRATIS - FOR FREE
4
3
2
1
+1.05V_VCCP
CRB 270uF
220U_D2_4VY_R15M~D
1
C535
1
+
C537
2
2
D D
C C
B B
A A
+1.25V_RUN
+1.25V_RUN
+3.3V_RUN
4.7U_0603_6.3V6M~D
1
2
BLM18AG121SN1D_0603~D
1
2
0.1U_0402_16V4Z~D
1
2
C542
22U_0805_6.3V6M~D
C591
+VCC_RXR_DMI
0.47U_0402_10V4Z~D
2.2U_0603_6.3V6K~D
4.7U_0603_6.3V6M~D
C543
1
1
2
2
+1.25V_RUN_AXD
L33
12
1U_0603_10V4Z~D
C552
C551
1
2
+1.8V_SM_CK
1
2
0.1U_0402_16V4Z~D
C597
1
2
0.47U_0402_10V4Z~D
C577
C576
1
1
2
2
+1.25V_RUN
1U_0603_10V4Z~D
C589
Place caps close
to VCC_AXF (Pin
A21, B21, B23)
0.47U_0402_10V4Z~D
C544
+1.25V_RUN
+VCC_PEG
0.47U_0402_10V4Z~D
C578
1
2
5
10U_0805_4VAM~D
C590
AT23
AU28
AU24
AT29
AT25
AT30
AR29
AJ50
BK24
BK23
BJ24
BJ23
AD51
W50
W51
AH50
AH51
AH1
U13
U12
U11
T13
T11
T10
B23
B21
A21
A43
C40
B40
V49
V50
VTT_1
VTT_2
VTT_3
U9
VTT_4
U8
VTT_5
U7
VTT_6
U5
VTT_7
U3
VTT_8
U2
VTT_9
U1
VTT_10
VTT_11
VTT_12
VTT_13
T9
VTT_14
T7
VTT_15
T6
VTT_16
T5
VTT_17
T3
VTT_18
T2
VTT_19
R3
VTT_20
R2
VTT_21
R1
VTT_22
VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5
VCC_AXD_6
VCC_AXD_NCTF
VCC_AXF_1
VCC_AXF_2
VCC_AXF_3
VCC_DMI
VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4
VCC_TX_LVDS
VCC_HV_1
VCC_HV_2
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5
VCC_RXR_DMI_1
VCC_RXR_DMI_2
A7
VTTLF1
F2
VTTLF2
VTTLF3
LE88CLPM A0 QM21_FCBGA1299~D
1
2
VTT
AXD
AXF
POWER
PEG
VTTLF
VCCA_CRT_DAC_1
VCCA_CRT_DAC_2
CRT
VCCA_DAC_BG
VSSA_DAC_BG
PLL
LVDS PEG
VCCA_PEG_BG
VSSA_PEG_BG
VCCA_PEG_PLL
SM
VCCA_SM_10
VCCA_SM_11
CLK
VCCA_SM_NCTF_1
VCCA_SM_NCTF_2
VCCA_SM_CK_1
VCCA_SM_CK_2
VCCA_TVA_DAC_1
VCCA_TVA_DAC_2
TV
VCCA_TVB_DAC_1
VCCA_TVB_DAC_2
VCCA_TVC_DAC_1
VCCA_TVC_DAC_2
TV/CRT
VCCD_TVDAC
DMI
VCCD_PEG_PLL
LVDS
VCCD_LVDS_1
VCCD_LVDS_2
+1.05V_VCCP
U29H
VCCSYNC
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL
VCCA_LVDS
VSSA_LVDS
VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCCD_CRT
VCCD_QDAC
VCCD_HPLL
2 1
D16
RB751V_SOD323~D
J32
A33
B33
A30
B32
B49
H49
AL2
AM2
A41
B41
K50
K49
U51
AW18
AV19
AU19
AU18
AU17
AT22
AT21
AT19
AT18
AT17
AR17
AR16
BC29
BB29
C25
B25
C27
B27
B28
A28
M32
L29
N28
AN2
U48
J41
H42
+1.25V_RUN_HPLL
+1.25V_RUN_MPLL
+VCCA_SM
+VCCA_SM_CK
1
2
1 2
R417
10_0603_5%~D
+1.25V_RUN_PEGPLL
4.7U_0603_6.3V6M~D
1U_0603_10V4Z~D
0.1U_0402_16V4Z~D
C563
+1.25V_RUN_PEGPLL
0.1U_0402_16V4Z~D
C554
BLM18AG121SN1D_0603~D
+3.3V_RUN
4
22U_0805_6.3V6M~D
C560
1
1
1U_0603_10V4Z~D
C594
C565
1
2
2
1
2
C642
L41
12
1
C561
2
1U_0603_10V4Z~D
C566
+1.25V_RUN
0.1U_0402_16V4Z~D
12
1
C559
2
2
22U_0805_6.3V6M~D
C564
1
1
2
2
+1.8V_SUS +1.8V_SM_CK
10U_0805_4VAM~D
+3.3V_RUN
1 2
22U_0805_6.3V6M~D
0_0805_5%~D
C562
1 2
1
2
1_0603_5%~D
12
0.1U_0402_16V4Z~D
1
C550
2
R406
R408
0_0603_5%~D
1
C582
2
10U_0805_4VAM~D
0.1U_0402_16V4Z~D
R416
+1.25V_RUN
1
+
2
1
2
C592
1
2
+VCC_PEG
1
1
+
2
2
+VCC_RXR_DMI
1
1
+
2
2
220U_D2_4VY_R15M~D
L35
BLM21PG221SN1D_0805~D
1 2
12
1_0402_5%~D
C549
R409
10U_0805_4VAM~D
C557
10U_0805_4VAM~D
220U_D2_4VY_R15M~D
C548
C556
C558
100U_D2E_6.3VM_R18M~D
+1.25V_RUN
C567
10U_0805_4VAM~D
0.1U_0402_16V4Z~D
+1.5V_RUN
C584
1
C583
2
0.022U_0402_16V7K~D
1
C593
2
22U_0805_6.3V6M~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
L32
BLM18PG181SN1_0603~D
BLM18PG181SN1_0603~D
0.1U_0402_16V4Z~D
12
L34
12
+1.25V_RUN_PEGPLL+1.25V_RUN
0.1U_0402_16V4Z~D
+1.25V_RUN_HPLL
C571
1
2
C568
1
2
+1.05V_VCCP
+1.05V_VCCP
BLM18AG121SN1D_0603~D
1
C572
2
22U_0805_6.3VAM~D
+1.25V_RUN
L37
12
1
C573
0.1U_0402_16V4Z~D
2
+1.25V_RUN_MPLL
45mA Max.45mA Max.
C574
0.1U_0402_16V4Z~D
1
2
BLM18AG121SN1D_0603~D
1
C575
22U_0805_6.3VAM~D
2
+1.25V_RUN
L38
12
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
2
Date: Sheet
Compal Electronics, Inc.
Crestline(4 of 6)
LA-3302P
13 66Monday, February 26, 2007
1
0.4
of
5
4
3
2
1
+1.05V_VCCP
+3.3V_RUN
+1.05V_VCCP
D D
22U_0805_6.3VAM~D
220U_D2_4VY_R15M~D
1
C602
+
2
Layout Note:
370 mils from edge
C C
Layout Note:
Inside GMCH cavity.
+1.05V_VCCP
22U_0805_6.3V6M~D
C615
1
2
B B
Layout Note: Place
close to GMCH edge.
0.1U_0402_10V7K~D
C618
1
2
0.22U_0402_10V4Z~D
C603
1
2
1
2
C604
1
1
2
2
0.22U_0402_10V4Z~D
0.1U_0402_10V7K~D
C613
C614
1
1
2
2
0.22U_0402_10V4Z~D
0.22U_0402_10V4Z~D
C617
C616
1
2
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
C619
C620
1
2
AB33
AB36
AB37
AC33
AC35
AC36
AD35
AD36
AF33
AF36
AH33
AH35
AH36
AH37
AJ33
AJ35
AK33
AK35
AK36
AK37
AD33
AJ36
AM35
AL33
AL35
AA33
AA35
AA36
AP35
AP36
AR35
AR36
AL24
AL26
AL28
AM26
AM28
AM29
AM31
AM32
AM33
AP29
AP31
AP32
AP33
AL29
AL31
AL32
AR31
AR32
AR33
Y32
Y33
Y35
Y36
Y37
T30
T34
T35
U29
U31
U32
U33
U35
U36
V32
V33
V36
V37
U29F
VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
VCC_NCTF_45
VCC_NCTF_46
VCC_NCTF_47
VCC_NCTF_48
VCC_NCTF_49
VCC_NCTF_50
VCC_AXM_NCTF_1
VCC_AXM_NCTF_2
VCC_AXM_NCTF_3
VCC_AXM_NCTF_4
VCC_AXM_NCTF_5
VCC_AXM_NCTF_6
VCC_AXM_NCTF_7
VCC_AXM_NCTF_8
VCC_AXM_NCTF_9
VCC_AXM_NCTF_10
VCC_AXM_NCTF_11
VCC_AXM_NCTF_12
VCC_AXM_NCTF_13
VCC_AXM_NCTF_14
VCC_AXM_NCTF_15
VCC_AXM_NCTF_16
VCC_AXM_NCTF_17
VCC_AXM_NCTF_18
VCC_AXM_NCTF_19
POWER
LE88CLPM A0 QM21_FCBGA1299~D
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6
VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_6
VCC_AXM_5
VCC_AXM_7
T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28
A3
B2
C1
BL1
BL51
A51
AT33
AT31
AK29
AK24
AK23
AJ26
AJ23
+1.05V_VCCP
R420
10_0603_5%~D
1 2
D17
2
1
3
BAT54CW_SOT323~D
+1.8V_SUS
0.1U_0402_10V7K~D
2
C608
1
Layout Note:
Place C901 where
LVDS and DDR2 taps.
330U_D2E_2.5VM~D
1
C605
+
2
Layout Note: Inside GMCH cavity.
+1.05V_VCCP
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
1
1
C606
C607
2
2
Layout Note:
Place on the edge
AT35
AT34
AH28
AC32
AC31
AK32
AJ31
AJ28
AH32
AH31
AH29
AF32
R30
AU32
AU33
AU35
AV33
AW33
AW35
AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35
BJ32
BJ33
BJ34
BK32
BK33
BK34
BK35
BL33
AU30
R20
W13
W14
AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31
AJ20
AN14
T14
Y12
U29G
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36
VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC CORE
POWER
VCC SM
VCC GFX
LE88CLPM A0 QM21_FCBGA1299~D
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC GFX NCTFVCC SM LF
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31
VCCSM_LF1
AW45
VCCSM_LF2
BC39
VCCSM_LF3
BE39
VCCSM_LF4
BD17
VCCSM_LF5
BD4
VCCSM_LF6
AW8
AT6
VCCSM_LF7
0.22U_0402_10V4Z~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
C623
C622
C621
1
2
1
1
2
2
0.22U_0402_10V4Z~D
0.47U_0402_10V4Z~D
C624
1
1
2
2
1U_0402_6.3V4Z~D
1U_0402_6.3V4Z~D
C625
C627
C626
1
1
2
2
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
Crestline(5 of 6)
LA-3302P
14 66Monday, February 26, 2007
1
0.4
of
5
hexainf@hotmail.com
GRATIS - FOR FREE
U29I
A13
VSS_1
A15
VSS_2
A17
VSS_3
A24
VSS_4
AA21
VSS_5
AA24
VSS_6
AA29
VSS_7
AB20
VSS_8
AB23
D D
C C
B B
AB26
AB28
AB31
AC10
AC13
AC39
AC43
AC47
AD21
AD26
AD29
AD41
AD45
AD49
AD50
AE10
AE14
AF20
AF23
AF24
AF31
AG2
AG38
AG43
AG47
AG50
AH40
AH41
AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45
AJ49
AK20
AK21
AK26
AK28
AK31
AK51
AM11
AM13
AM3
AM4
AM41
AM45
AN38
AN39
AN43
AP48
AP50
AR11
AR39
AR44
AR47
AT10
AT14
AT41
AT49
AU23
AU29
AU36
AU49
AU51
AV39
AV48
AW1
AW12
AW16
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
AC3
VSS_15
VSS_16
VSS_17
VSS_18
AD1
VSS_19
VSS_20
VSS_21
VSS_22
AD3
VSS_23
VSS_24
VSS_25
VSS_26
AD5
VSS_27
VSS_28
AD8
VSS_29
VSS_30
VSS_31
AE6
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
AH3
VSS_42
VSS_43
VSS_44
AH7
VSS_45
AH9
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
AL1
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
AN1
VSS_69
VSS_70
VSS_71
VSS_72
AN5
VSS_73
AN7
VSS_74
AP4
VSS_75
VSS_76
VSS_77
VSS_78
AR2
VSS_79
VSS_80
VSS_81
VSS_82
AR7
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
AU1
VSS_88
VSS_89
VSS_90
AU3
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS
LE88CLPM A0 QM21_FCBGA1299~D
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41
4
U29J
C46
VSS_199
C50
VSS_200
C7
VSS_201
D13
VSS_202
D24
VSS_203
D3
VSS_204
D32
VSS_205
D39
VSS_206
D45
VSS_207
D49
VSS_208
E10
VSS_209
E16
VSS_210
E24
VSS_211
E28
VSS_212
E32
VSS_213
E47
VSS_214
F19
VSS_215
F36
VSS_216
F4
VSS_217
F40
VSS_218
F50
VSS_219
G1
VSS_220
G13
VSS_221
G16
VSS_222
G19
VSS_223
G24
VSS_224
G28
VSS_225
G29
VSS_226
G33
VSS_227
G42
VSS_228
G45
VSS_229
G48
VSS_230
G8
VSS_231
H24
VSS_232
H28
VSS_233
H4
VSS_234
H45
VSS_235
J11
VSS_236
J16
VSS_237
J2
VSS_238
J24
VSS_239
J28
VSS_240
J33
VSS_241
J35
VSS_242
J39
VSS_243
K12
VSS_245
K47
VSS_246
K8
VSS_247
L1
VSS_248
L17
VSS_249
L20
VSS_250
L24
VSS_251
L28
VSS_252
L3
VSS_253
L33
VSS_254
L49
VSS_255
M28
VSS_256
M42
VSS_257
M46
VSS_258
M49
VSS_259
M5
VSS_260
M50
VSS_261
M9
VSS_262
N11
VSS_263
N14
VSS_264
N17
VSS_265
N29
VSS_266
N32
VSS_267
N36
VSS_268
N39
VSS_269
N44
VSS_270
N49
VSS_271
N7
VSS_272
P19
VSS_273
P2
VSS_274
P23
VSS_275
P3
VSS_276
P50
VSS_277
R49
VSS_278
T39
VSS_279
T43
VSS_280
T47
VSS_281
U41
VSS_282
U45
VSS_283
U50
VSS_284
V2
VSS_285
V3
VSS_286
LE88CLPM A0 QM21_FCBGA1299~D
VSS
3
W11
VSS_287
W39
VSS_288
W43
VSS_289
W47
VSS_290
W5
VSS_291
W7
VSS_292
Y13
VSS_293
Y2
VSS_294
Y41
VSS_295
Y45
VSS_296
Y49
VSS_297
Y5
VSS_298
Y50
VSS_299
Y11
VSS_300
P29
VSS_301
T29
VSS_302
T31
VSS_303
T33
VSS_304
R28
VSS_305
AA32
VSS_306
AB32
VSS_307
AD32
VSS_308
AF28
VSS_309
AF29
VSS_310
AT27
VSS_311
AV25
VSS_312
H50
VSS_313
2
1
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Crestline(6 of 6)
LA-3302P
15 66Monday, February 26, 2007
1
0.4
of
5
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
Size Document Number Rev
Date: Sheet
5
DDR_A_DQS#[0..7]11
DDR_A_D[0..63]11
DDR_A_DM[0..7]11
DDR_A_DQS[0..7]11
DDR_A_MA[0..14]11
D D
+1.8V_SUS
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
1
2
1
2
C141
C119
RN6
RN12
RN5
RN11
RN10
RN8
RN13
C117
1
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
2
C104
2.2U_0603_6.3V6K~D
1
2
14
23
56_0404_4P2R_5%~D
14
23
56_0404_4P2R_5%~D
14
23
56_0404_4P2R_5%~D
14
23
56_0404_4P2R_5%~D
14
23
56_0404_4P2R_5%~D
14
23
56_0404_4P2R_5%~D
14
23
56_0404_4P2R_5%~D
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
C133
1
2
0.1U_0402_16V4Z~D
C130
1
2
C C
+0.9V_DDR_VTT
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
2
B B
A A
C136
DDR_A_MA1
DDR_A_MA3
56_0404_4P2R_5%~D
DDR_A_BS0
DDR_A_MA10
56_0404_4P2R_5%~D
DDR_A_RAS#
DDR_CS0_DIMMA#
56_0404_4P2R_5%~D
DDR_A_CAS#
DDR_A_WE#
56_0404_4P2R_5%~D
M_ODT1
DDR_CS1_DIMMA#
56_0404_4P2R_5%~D
DDR_CKE1_DIMMA
DDR_CKE0_DIMMA
DDR_A_BS2
56_0404_4P2R_5%~D
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
2
2
C138
C137
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
R223
56_0402_5%~D
2 3
1 4
5
1
2
1
2
RN4
RN3
RN9
RN2
RN1
RN7
C132
0.1U_0402_16V4Z~D
C139
C437
1
2
0.1U_0402_16V4Z~D
C131
1
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
2
C140
+0.9V_DDR_VTT
12
C116
1
2
C118
0.1U_0402_16V4Z~D
1
2
C105
DDR_A_MA9
DDR_A_MA12
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA8
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS1
M_ODT0
DDR_A_MA13
DDR_A_MA14
DDR_A_MA11
0.1U_0402_16V4Z~D
Layout Note:
Place near JDIM1
0.1U_0402_16V4Z~D
1
1
2
2
C106
C107
4
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
2
2
C109
C108
Layout Note:
Place these resistor
closely DIMM0,all
trace length<750 mil
Layout Note:
Place these resistor
closely DIMM0,all
trace length
Max=1.3"
4
3
+1.8V_SUS +1.8V_SUS
ON TOP SIDE
JDIM2
1
VREF
3
2.2U_0603_6.3V6K~D
C115
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
201
GND
TYCO_1470815-2~D
RESERVE
DDR_A_D0
DDR_A_D5
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D3
DDR_A_D7
DDR_A_D13
DDR_A_D12
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D17
DDR_A_D21
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D22
DDR_A_D23
DDR_A_D29
DDR_A_DM3
DDR_A_D27
DDR_A_D30
DDR_CKE0_DIMMA10
DDR_A_BS211
DDR_A_BS011
DDR_A_WE#11
DDR_A_CAS#11
DDR_CS1_DIMMA#10
M_ODT110
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
2
2
C110
C707
MEM_SDATA17,23
MEM_SCLK17,23
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
DDR_CKE0_DIMMA
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9 DDR_A_MA7
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_CS1_DIMMA#
M_ODT1
DDR_A_D33
DDR_A_D32
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D39
DDR_A_D41
DDR_A_D40
DDR_A_DM5
DDR_A_D46
DDR_A_D43 DDR_A_D47
DDR_A_D49 DDR_A_D48
DDR_A_D52
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D51
DDR_A_D60
DDR_A_D56
DDR_A_DM7
DDR_A_D58
MEM_SDATA
MEM_SCLK
+3.3V_RUN
0.1U_0402_16V4Z~D
C113
1
1
2
2
NC/CKE1
DIMMA
2
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
VDD
NC/A15
NC/A14
VDD
VDD
VDD
RAS#
VDD
ODT0
NC/A13
VDD
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
GND
2
1
V_DDR_MCH_REF
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
CK0
32
34
36
38
40
42
44
46
48
50
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
A11
92
A7
94
A6
96
98
A4
100
A2
102
A0
104
106
BA1
108
110
S0#
112
114
116
118
120
NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
CK1
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
SA1
202
DDR_A_D4
DDR_A_D6
DDR_A_DM0
DDR_A_D1
DDR_A_D2
DDR_A_D9
DDR_A_D8
DDR_A_DM1
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_D15
DDR_A_D14DDR_A_D11
DDR_A_D20
DDR_A_D16
PM_EXTTS#0
DDR_A_DM2
DDR_A_D18
DDR_A_D19
DDR_A_D28
DDR_A_D24DDR_A_D25
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D26
DDR_A_D31
DDR_CKE1_DIMMA
DDR_A_MA14
DDR_A_MA11
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
DDR_A_MA13
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D35
DDR_A_D38
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D42
DDR_A_D53
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_DM6
DDR_A_D50
DDR_A_D55DDR_A_D54
DDR_A_D61
DDR_A_D57
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D59DDR_A_D62
DDR_A_D63
R122 10K_0402_5%~D
1 2
R127 10K_0402_5%~D
1 2
V_DDR_MCH_REF
2.2U_0603_6.3V6K~D
1
C114
2
M_CLK_DDR0 10
M_CLK_DDR#0 10
PM_EXTTS#0 10
DDR_CKE1_DIMMA 10
DDR_A_BS1 11
DDR_A_RAS# 11
DDR_CS0_DIMMA# 10
M_ODT0 10
M_CLK_DDR1 10
M_CLK_DDR#1 10
0.1U_0402_16V4Z~D
1
C112
2
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
DDRII-SODIMM SLOT1
LA-3302P
16 66Thursday, March 01, 2007
1
0.4
of
5
hexainf@hotmail.com
GRATIS - FOR FREE
DDR_B_DQS#[0..7]11
DDR_B_D[0..63]11
DDR_B_DM[0..7]11
DDR_B_DQS[0..7]11
DDR_B_MA[0..14]11
D D
C C
B B
A A
+1.8V_SUS
+0.9V_DDR_VTT
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
2
C456
DDR_B_MA1
DDR_B_MA3
56_0404_4P2R_5%~D
DDR_B_BS0
DDR_B_MA10
56_0404_4P2R_5%~D
DDR_B_MA0
DDR_B_BS1
56_0404_4P2R_5%~D
DDR_B_RAS#
DDR_CS2_DIMMB#
56_0404_4P2R_5%~D
DDR_B_CAS#
DDR_B_WE#
56_0404_4P2R_5%~D
DDR_CKE3_DIMMB
DDR_CS3_DIMMB#
M_ODT3
56_0404_4P2R_5%~D
2.2U_0603_6.3V6K~D
1
2
0.1U_0402_16V4Z~D
C433
RN21
RN14
RN22
RN15
RN16
RN19
RN20
C412
1
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
2
C452
2.2U_0603_6.3V6K~D
1
2
C413
1
2
1
2
C451
DDR_B_MA9
14
DDR_B_MA12
23
56_0404_4P2R_5%~D
DDR_B_MA14
14
DDR_B_MA11
23
56_0404_4P2R_5%~D
DDR_B_MA5
14
DDR_B_MA8
23
56_0404_4P2R_5%~D
DDR_B_MA7
14
DDR_B_MA6
23
56_0404_4P2R_5%~D
DDR_B_MA4
14
DDR_B_MA2
23
56_0404_4P2R_5%~D
M_ODT2
14
DDR_B_MA13
23
56_0404_4P2R_5%~D
DDR_B_BS2
14
DDR_CKE2_DIMMB
23
56_0404_4P2R_5%~D
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
1
2
C455
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
1 4
2 3
R312
56_0402_5%~D
2 3
1 4
C440
C439
1
1
2
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C434
1
2
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
2
2
C454
C453
+0.9V_DDR_VTT
RN23
RN24
RN17
RN18
RN25
12
RN26
5
2.2U_0603_6.3V6K~D
C438
1
2
0.1U_0402_16V4Z~D
C414
1
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
2
C450
Layout Note:
Place near JDIM2
C411
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
2
2
C410
C409
4
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
1
2
2
2
C408
Layout Note:
Place these resistor
closely DIMM0,all
trace length<750 mil
Layout Note:
Place these resistor
closely DIMM0,all
trace length
Max=1.3"
C406
C407
4
3
ON BOTTOM SIDE
DDR_B_D0
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D21
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D19
DDR_B_D18
DDR_B_D24 DDR_B_D28
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
DDR_CKE2_DIMMB10
DDR_B_BS211
DDR_B_BS011
DDR_B_WE#11
DDR_B_CAS#11
DDR_CS3_DIMMB#10
1
2
C405
M_ODT310
MEM_SDATA16,23
MEM_SCLK16,23
DDR_CKE2_DIMMB
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_CS3_DIMMB#
M_ODT3
DDR_B_D36
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D53
DDR_B_D49 DDR_B_D48
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D55
DDR_B_D50
DDR_B_D56
DDR_B_D60
DDR_B_DM7
DDR_B_D58
DDR_B_D59
MEM_SDATA
MEM_SCLK
+3.3V_RUN
0.1U_0402_16V4Z~D
2.2U_0603_6.3V6K~D
C431
1
1
2
2
C429
JDIM1
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
201
GND
TYCO_1565917-4~D
DIMMB
STANDARD
DQ4
DQ5
DM0
DQ6
DQ7
DQ12
DQ13
DM1
CK0#
DQ14
DQ15
DQ20
DQ21
DM2
DQ22
DQ23
DQ28
DQ29
DQS3#
DQS3
DQ30
DQ31
NC/CKE1
VDD
NC/A15
NC/A14
VDD
VDD
VDD
RAS#
VDD
ODT0
NC/A13
VDD
DQ36
DQ37
DM4
DQ38
DQ39
DQ44
DQ45
DQS5#
DQS5
DQ46
DQ47
DQ52
DQ53
CK1#
DM6
DQ54
DQ55
DQ60
DQ61
DQS7#
DQS7
DQ62
DQ63
SAO
GND
VSS
VSS
VSS
VSS
VSS
VSS
CK0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BA1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CK1
VSS
VSS
VSS
VSS
VSS
VSS
SA1
NC
A11
A7
A6
A4
A2
A0
S0#
NC
2
+1.8V_SUS+1.8V_SUS V_DDR_MCH_REF
2
DDR_B_D5
4
DDR_B_D4DDR_B_D1
6
8
DDR_B_DM0
10
12
DDR_B_D2
14
DDR_B_D3
16
18
DDR_B_D13
20
DDR_B_D12
22
24
DDR_B_DM1
26
28
M_CLK_DDR2
30
M_CLK_DDR#2
32
34
DDR_B_D10
36
DDR_B_D11
38
40
42
DDR_B_D20
44
DDR_B_D17
46
48
PM_EXTTS#1
50
DDR_B_DM2
52
54
DDR_B_D22
56
DDR_B_D23
58
60
62
DDR_B_D29
64
66
DDR_B_DQS#3
68
DDR_B_DQS3
70
72
DDR_B_D30
74
DDR_B_D31
76
78
DDR_CKE3_DIMMB
80
82
84
DDR_B_MA14
86
88
DDR_B_MA11
90
DDR_B_MA7
92
DDR_B_MA6
94
96
DDR_B_MA4
98
DDR_B_MA2
100
DDR_B_MA0
102
104
DDR_B_BS1
106
DDR_B_RAS#
108
DDR_CS2_DIMMB#
110
112
M_ODT2
114
DDR_B_MA13
116
118
120
122
DDR_B_D33DDR_B_D32
124
DDR_B_D37
126
128
DDR_B_DM4
130
132
DDR_B_D38
134
DDR_B_D39DDR_B_D35
136
138
DDR_B_D44
140
DDR_B_D45
142
144
DDR_B_DQS#5
146
DDR_B_DQS5
148
150
DDR_B_D43DDR_B_D46
152
DDR_B_D47
154
156
DDR_B_D52
158
160
162
M_CLK_DDR3
164
M_CLK_DDR#3
166
168
DDR_B_DM6
170
172
DDR_B_D54
174
DDR_B_D51
176
178
DDR_B_D57
180
DDR_B_D61
182
184
DDR_B_DQS#7
186
DDR_B_DQS7
188
190
DDR_B_D62
192
DDR_B_D63
194
196
198
200
202
10K_0402_5%~D
12
M_CLK_DDR2 10
M_CLK_DDR#2 10
PM_EXTTS#1 10
DDR_CKE3_DIMMB 10
DDR_B_BS1 11
DDR_B_RAS# 11
DDR_CS2_DIMMB# 10
M_ODT2 10
M_CLK_DDR3 10
M_CLK_DDR#3 10
R243
10K_0402_5%~D
R241
V_DDR_MCH_REF
2.2U_0603_6.3V6K~D
1
C447
2
+3.3V_RUN
12
1
0.1U_0402_16V4Z~D
1
C436
2
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
DDRII-SODIMM SLOT2
LA-3302P
17 66Thursday, March 01, 2007
1
0.4
of
5
+3.3V_SUS
12
R423
8.2K_0402_5%~D
2
Q38
2
Q39
B
+3.3V_SUS
B
C
E
3 1
12
C
E
3 1
THERMATRIP1#
1
C628
0.1U_0402_16V4Z~D
2
R426
8.2K_0402_5%~D
THERMATRIP2#
1
C632
0.1U_0402_16V4Z~D
2
+1.05V_VCCP
R425
D D
H_THERMTRIP#7
THERMTRIP_MCH#10
2.2K_0402_5%~D
1 2
MMST3904-7-F_SOT323-3~D
+1.05V_VCCP
R427
2.2K_0402_5%~D
1 2
MMST3904-7-F_SOT323-3~D
Place under CPU
C C
C633
@
2200P_0402_50V7K~D
Place C633 close to the Q40 as possible
Place C636 close to the Guardian pins as possible
H_THERMDA7
470P_0402_50V7K~D
H_THERMDC7
+3.3V_SUS
0.1U_0402_16V4Z~D
12
R186
8.2K_0402_5%~D
+3.3V_SUS
B B
+3.3V_SUS
R196
@
1 2
10K_0402_5%~D
@
1 2
10K_0402_5%~D
A A
R194
MDC_RST_DIS#
SIO_GFX_PWR
+3.3V_RUN
THERMTRIP_VGA#52
5
R428
1 2
49.9_0603_1%~D
1
C639
2
C100
2200P_0402_50V7K~D
12
2
1
C636
1
C637
0.1U_0402_16V4Z~D
2
2
1
R187
2.2K_0402_5%~D
2@
THERM_B3
C
+3.3V_SUS
2
B
4
RB751S40T1_SOD523-2~D
E
3 1
+RTC_CELL
E
@
2
B
Q40
MMST3904-7-F_SOT323-3~D
1
2
12
R436
332K_0402_1%~D
12
R438
118K_0402_1%~D
12
R433
8.2K_0402_5%~D
THERMATRIP3#
C
Q76
MMST3904-7-F_SOT323-3~D
2@
3 1
4
D19
2 1
+3VSUS_THRM
1
C638
2
0.1U_0402_16V4Z~D
1
C630
2
22U_0805_6.3VAM~D
2200P_0402_50V7K~D
2
C634
1
SUSPWROK42
ICH_PWRGD#42
R437
1 2
1K_0402_5%~D
MDC_RST_DIS#33
AUDIO_AVDD_ON27
1
C203
0.1U_0402_16V4Z~D
2
2@
3
FAN1 Control and Tachometer
+3.3V_RUN
12
R424
10K_0402_5%~D
12
R414
0_0402_5%~D
+FAN1_VOUT
FAN1_TACH_FB
Place C634 close to the
Guardian pins as possible
THRM_SMBDAT39,49
THRM_SMBCLK39,49
REM_DIODE1_P
REM_DIODE1_N
1 2
R429 1K_0402_5%~D
1 2
R432 1K_0402_5%~D
THERMATRIP1#
THERMATRIP2#
THERMATRIP3#
MDC_RST_DIS#
SIO_GFX_PWR
5V_CAL_SIO#
AUDIO_AVDD_ON
FAN1_TACH 39
JFAN1
1
1
2
2
3
3
MOLEX_53398-0371~D
Discrete
VGA_THERMDP
1
C706
470P_0402_50V7K~D
3
2
U31
11
SMDATA
12
SMBCLK
38
DP1
37
DN1
41
DP2
40
DN2
35
3V_SUS
21
RTC_PWR3V
23
VSUS_PWRGD
16
3V_PWROK#
17
THERMTRIP1#
18
THERMTRIP2#
19
THERMTRIP3#
42
VSET
26
XEN
34
VSS
7
FAN_OUT
8
FAN_OUT
39
FAN_DAC1
10
GPIO1
13
GPIO2
14
GPIO3
15
GPIO4
22
GPIO5
36
GPIO6/FAN_DAC2
49
PAD_GND
VGA_THERMDN
Place Capacitor close to Guardian Chip
+FAN1_VOUT
SMBUS ADDRESS : 2F
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
VGA_THERMDP 53
VGA_THERMDN 53
VCP1
VCP2
ATF_INT#
POWER_SW#
ACAVAIL_CLR
THERMTRIP_SIO
SYS_SHDN#
LDO_SHDN#/ADDR
LDO_POK
LDO_SET
LDO_OUT
LDO_OUT
LDO_IN
LDO_IN
VDD_3V
VDD_5V
VDD_5V
EMC4001_QFN48~D
1
C645
2
10U_0805_10V4Z~D
DP3
DN3
DP4
DN4
DP5
DN5
43
46
45
44
48
47
2
1
20
3
4
25
24
27
33
28
32
31
30
29
9
5
6
1
C646
2
VCP2
VCP2
REM_DIODE3_P
REM_DIODE3_N
REM_DIODE4_P
REM_DIODE4_N
VGA_THERMDP
VGA_THERMDN
7.5K_0402_5%~D
LDO_SET
+3V_LDOIN
+5V_RUN
0.1U_0402_16V4Z~D
2
+5V_SUS
12
R771
2.21K_0603_1%~D
1
C750
2
2200P_0402_50V7K~D
PWR_MON 48
Place C649 close to the
Guardian pins as possible.
1
2
Diode circuit at DP 4/ DN 4 is used for skin temp
sensor (plac e d o p ti m a l l y between CPU, MCH and GPU).
1
2
ATF_INT#
ATF_INT# 38
POWER_SW# 39,40
ACAV_IN 39,49,50
R434
12
+3.3V_SUS
1
1
C640
2
2
1@
10U_0805_10V4Z~D
1
1
C643
2
2
1U_0603_10V4Z~D
1
1
C647
2
2
10U_0805_10V4Z~D
2
VSET=
R436+R438
VSET =
12
R772
10K_0603_1%_TSM1A103F34D3RZ~D
Q102
13
D
2N7002W-7-F_SOT323-3~D
2
G
S
C649
2200P_0402_50V7K~D
Q41 Place near the
bottom SODIMM
C418
2200P_0402_50V7K~D
C648
0.1U_0402_16V4Z~D
R96
10K_0402_5%~D
+2.5V_RUN
C641
0.1U_0402_16V4Z~D
@
R439
12
0_1210_5%~D
C644
0.1U_0402_16V4Z~D
+3.3V_RUN
DELL CONFIDENTIAL/PROPRIETARY
Title
Size Document Number Rev
Date: Sheet
1
R438
Tp-70
x 3.3V
=0.865V
=> Tp = 88.2 C
21
+3.3V_SUS
12
R773
10K_0402_5%~D
5V_CAL_SIO#
This thermistor circuit is located near
Top side DDR connector.
REM_DIODE3_N, REM_DIODE3_P routing together.
Trace width / Spacing = 10 / 10 mil
C
Q41
2
B
MMST3904-7-F_SOT323-3~D
E
3 1
C
Q19
2
B
MMST3904-7-F_SOT323-3~D
E
3 1
12
R430
10K_0402_5%~D
R431
@
10K_0402_5%~D
+3.3V_RUN
12
12
+3.3V_SUS
+3.3V_ALW
+RTC_CELL
THERMTRIP_SIO
THERM_STP# 45
2.5V_RUN_PWRGD 42
1
C650
2200P_0402_50V7K~D
2
@
Place C650
close to Q41
1
C904
2200P_0402_50V7K~D
2
@
C418 close to Guardian and
C904 close to diode Q19.
+2.5V_RUN
31.6K_0402_1%~D
@
12
R485
LDO_SET
Voltage margining
circuit for LDO output.
For Vmargin, stuff
Ra=31.6K and Rb=30K.
Rb=1K for production
1K_0402_1%~D
12
R441
Compal Electronics, Inc.
FAN & Thermal Sensor
LA-3302P
18 66Thursday, March 01, 2007
1
Ra
Rb
0.4
of
5
hexainf@hotmail.com
GRATIS - FOR FREE
D D
JLVDS
45
MGND1
46
MGND2
47
MGND3
48
MGND4
49
MGND5
50
MGND6
51
MGND7
52
MGND8
53
MGND9
54
MGND10
55
MGND11
56
NC
57
C C
TXLCLKOUT-
NC
TXLCLKOUT+
PANEL_I2C_CLK
PANEL_I2C_DAT
PNL_SLFTST
LCDPWR_SRC
LCDPWR_SRC
LCDPWR_SRC
PBAT_SMBCLK
PBAT_SMBDAT
LAMP_START
IPEX_20330-044E-11F~D
TXUCLKUT-
TXUCLKUT+
GND1
TXUOUT2-
TXUOUT2+
GND2
TXUOUT1-
TXUOUT1+
GND3
TXUOUT0-
TXUOUT0+
GND4
GND5
TXLOUT2TXLOUT2+
GND6
TXLOUT1TXLOUT1+
GND7
TXLOUT0TXLOUT0+
GND8
GND9
VEDID
GND10
LCDVDD1
LCDVDD2
GND11
FPBACK
GND12
GND13
+5V_ALWF
GND14
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LCD_BCLKLCD_BCLK+
LCD_B2LCD_B2+
LCD_B1LCD_B1+
LCD_B0LCD_B0+
LCD_ACLKLCD_ACLK+
LCD_A2LCD_A2+
LCD_A1LCD_A1+
LCD_A0LCD_A0+
LCD_DDCCLK
LCD_DDCDATA
LCD_TST
LAMP_STAT#
LCD_TST 38
4
LCD_BCLK- 53
LCD_BCLK+ 53
LCD_B2- 53
LCD_B2+ 53
LCD_B1- 53
LCD_B1+ 53
LCD_B0- 53
LCD_B0+ 53
LCD_ACLK- 53
LCD_ACLK+ 53
LCD_A2- 53
LCD_A2+ 53
LCD_A1- 53
LCD_A1+ 53
LCD_A0- 53
LCD_A0+ 53
LCD_DDCCLK 52
LCD_DDCDATA 52
0.1U_0402_16V4Z~D
LCD_SMBCLK 39
LCD_SMBDAT 39
T28 PAD~D
3
+LCDVDD
12
R26
470_0402_5%~D
13
D
Q9
S
D24
2N7002W-7-F_SOT323-3~D
LCD_VCC_TEST_EN39
1 2
R156 0_0402_5%~D@
ENVDD52
+3.3V_RUN
C45
1
1
2
2
+LCDVDD
C44
0.1U_0402_16V4Z~D
1
2
+3.3V_RUN
+5V_ALW
C176
0.1U_0402_16V4Z~D
12
R155
10K_0402_5%~D
3
2
BAT54CW_SOT323~D
1 2
R527
@
0_0402_5%~D
BIA_PWM 52
1
Populate R155 and de-pop R156
for discrete because it
doesn't support DPST
+15V_ALW
2
G
2
I
2
+15V_ALW
12
R23
100K_0402_5%~D
1
O
G
DDTC124EUA-7-F_SOT323-3~D
3
12
13
D
2
G
S
Q7
+LCDVDD
R24
100K_0402_5%~D
Q8
2N7002W-7-F_SOT323-3~D
SI3456BDV-T1-E3_TSOP6~D
4 5
1
C30
2
0.1U_0603_50V4Z~D
Q11
D
S
G
3
12
R25
@
100K_0402_5%~D
1
6
2
1
+3.3V_RUN
1
C42
2
0.1U_0402_16V4Z~D
+3.3V_RUN
2
B B
A A
1
2
+INV_PWR_SRC
C180
0.1U_0603_50V4Z~D
LCD_SMBCLK
LCD_SMBDAT
G
1 3
D
S
Q12
@
2N7002W-7-F_SOT323-3~D
+3.3V_RUN
2
G
1 3
D
S
Q13
@
2N7002W-7-F_SOT323-3~D
I2CH_SCL
I2CH_SDA
I2CH_SCL 52
I2CH_SDA 52
1
C427
2
1
2
0.1U_0603_50V4Z~D
40mil
1
C463
2
2200P_0402_50V7K~D
+PWR_SRC
12
C173
1000P_0402_50V7K~D
R154
200K_0402_5%~D
Q24
FDS4435BZ_SO8~D
1
2
3
R153
1 2
100K_0402_5%~D
RUN_ON37,39,41,42,51
4
D
1 3
2
8
7
6
5
S
G
40mil
Q25
2N7002W-7-F_SOT323-3~D
+INV_PWR_SRC
1
C174
0.1U_0603_50V4Z~D
2
FDS4435: P CHANNAL
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Internal LVDS
LA-3302P
19 66Thursday, March 01, 2007
1
0.4
of
5
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
Size Document Number Rev
Date: Sheet
5
D D
4
3
2
1
D8
SDM10U45-7_SOD523-2~D
F3
@
+5V_RUN
21
12
0.12A_48V_NANOSMDC012F~D
12
R792
0_1206_5%~D
RED
DAT_DDC2
GREEN
JVGA_HS
BLUE
JVGA_VS
M_ID2#
CLK_DDC2
CRT_VCC
1
C151
2
0.01U_0402_16V7K~D
JCRT
6
11
1
7
12
2
8
13
14
10
15
SUYIN_070915FR015S201CU~D
16
17
3
9
4
5
D11
DA204U_SOT323~D
1
@
+3.3V_RUN
2
3
L11
CRT_RED36,52
CRT_GRN36,52
C C
CRT_BLU36,52
CRT_RED
CRT_GRN
CRT_BLU
R141
22P_0402_50V8J~D
1
C161
2
@
22P_0402_50V8J~D
1
C165
2
@
12
12
R142
150_0402_1%~D
150_0402_1%~D
12
R143
150_0402_1%~D
1
C162
2
@
Evaluate Package
DAT_DDC236,52
CLK_DDC236,52
SDM10U45-7_SOD523-2~D
+5V_RUN
B B
CRT_HSYNC52
CRT_VSYNC52
2 1
R60
1 2
30_0402_1%~D
R59
1 2
30_0402_1%~D
+5V_RUN_SYNC
D6
5
A2Y
3
SN74AHCT1G125GW_SC70-5~D
5
A2Y
3
R144
1K_0402_5%~D
1 2
1
U15
P
4
4
1 2
R146
10_0402_5%~D
1 2
R138
10_0402_5%~D
OE#
G
1
P
OE#
G
U14
SN74AHCT1G125GW_SC70-5~D
BLM18BB750SN1D_0603~D
1 2
BLM18BB750SN1D_0603~D
1 2
BLM18BB750SN1D_0603~D
1 2
22P_0402_50V8J~D
L1
BLM18AG121SN1D_0603~D
1 2
HSYNC_R 36
VSYNC_R 36
L2
BLM18AG121SN1D_0603~D
1 2
L10
L9
+5V_RUN_SYNC
12
R3
@
1K_0402_5%~D
1
C5
2
10P_0402_50V8J~D
1
C149
10P_0402_50V8J~D
2
@
12
@
R5
1K_0402_5%~D
1
C4
2
10P_0402_50V8J~D
R137
1 2
1
C719
2
@
10P_0402_50V8J~D
R2
2.2K_0402_5%~D
1 2
2.2K_0402_5%~D
1
C712
2
@
10P_0402_50V8J~D
0.1U_0402_16V4Z~D
2
1
C148
10P_0402_50V8J~D
2
@
T5 PAD~D
D10
DA204U_SOT323~D
1
@
3
1
C160
2
1
2
D9
DA204U_SOT323~D
1
@
2
3
C147
10P_0402_50V8J~D
@
A A
DA204U
K1
A2
DELL CONFIDENTIAL/PROPRIETARY
A1 K2
5
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
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Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
CRT
LA-3302P
20 66Thursday, March 01, 2007
1
0.4
of
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