Dell D410 Schematics

This Sheet of Engineering drawings and specifications contains Confidential,

Trade Secret and other Proprietary information of Dell Computer Corporation ( "Dell" ).

This document may not be transferred or copied without the express written authorization of Dell.

In addition, neither this sheet nor the information it contains may be used by or

disclosed to any third party without Dell’s express written consent.

This drawing is property of SEC, Use or copy of this drawing without proper permission

of the appropriate technical-document managing department is prohibited

4

3

Rev.

No

2

1

D

VENICE

CPU :

C

Chip Set :
Remarks :

Model Name :
PCB Code :

Dev. Step :

B

Revision :
Update :

DRAW CHECK

SE LEE

A

DOTHAN
ALVISO (GMCH)

915GM

VENICE Main
BA41-00454A

QT
A00

2004.12.10

APPROVAL

MK KIM

BL LEE

NO.

1.

2.

3.

4.

5.

6.

8.

9.

10.

11.

12.

13.

13.

14.

15.

16.

17.

18.

19.

20.

21.

22.

23.

24.

25.

26.

27.

28.

29.

30.

31.

27.

28.

29.

30.

D

C

B

A

SAMSUNG

4

3

2

1

This Sheet of Engineering drawings and specifications contains Confidential,

Trade Secret and other Proprietary information of Dell Computer Corporation ( "Dell" ).

This document may not be transferred or copied without the express written authorization of Dell.

In addition, neither this sheet nor the information it contains may be used by or

disclosed to any third party without Dell’s express written consent.

This drawing is property of SEC, Use or copy of this drawing without proper permission

of the appropriate technical-document managing department is prohibited

4

3

Rev.

No

2

1

Option

D

Thermistor
EMC6N300

Clock Generator

CY28411ZCT

Dothan

(478 Micro-FCBGA)

LCD Conn.

LVDS 1ch

SWITCH

CRT

D

4*100Mhz or 4*133Mhz

DDR2-Sodimm

sDVO

SIL1362

DVI

TV out

DDR2-Sodimm

DDR2 1ch

533 & 400Mhz

ALVISO

915GM

(1257 PCBGA)

C

Bluetooth

Powered USB

USB2

USB0

DMI*2

Switch

USB5

PCMCIA

Socket

CardBus

PCI6515

PCI

2x USB

HDD

USB3,4

PATA

AC97

B

Audio

STAC9751T

SPDIF

MDC

ICH6-M

(609 BGA)

LPC

SIO(Macallan III)

(256 LBGA)

PCIE

LOM

BCM5751

X-Bus

Jacks

Docking Connector

RJ11

Smartcard

Socket

MiniPCI

PI3L500

USB1

Buffered LPC

2x PS2

C

Docking

Connector

Q-Switch

RJ45

B

Connector

TAA Option

IRDA

A

Keybd

TP

LED

Firm Ware

Firm Ware

Daughter Board

A

Pointing

Stick

3

24

1

SAMSUNG

This Sheet of Engineering drawings and specifications contains Confidential,

Trade Secret and other Proprietary information of Dell Computer Corporation ( "Dell" ).

This document may not be transferred or copied without the express written authorization of Dell.

In addition, neither this sheet nor the information it contains may be used by or

disclosed to any third party without Dell’s express written consent.

This drawing is property of SEC, Use or copy of this drawing without proper permission

of the appropriate technical-document managing department is prohibited

SCHEMATIC ANNOTATIONS AND BOARD INFORMATION

D

4

3

Rev.

No

2

1

D

PCI Devices

Devices
Docking

Cardbus
MiniPCI SLOT

USB

Hub to PCI
LPC bridge/IDE/AC97/SMBUS
AGP
Internal MAC
AC Link

C

B

I2 C / SMB Address

Devices

ICH6

CK-410M (Clock Generator)
SODIMM0
SODIMM1

SSCG
BCM

PWR USB

MAC III

On b’d Diagnostic
Inverter
Battery
Smart Charger
THERMISTER

GMCH

EDID
DVI

USB PORT Assign

PORT NUMBER
0

1
2
3
4
5
6
7

IDSEL#
AD24

AD17
AD19
AD29(internal)

AD30(internal)
AD31(internal)
AD17(internal)
AD24(internal)

-

Address

Master

1101 001x
1010 000x
1010 001X

1101-010x
1100-100x

-

Master

1010 001x
0101 100x
0001 011h
0001 001x
0101 111x

Master

1010 000x
0111 000x

ASSIGNED TO
SYSTEM PORT (Left, Powered USB)

Docking
BLUETOOTH
SYSTEM PORT #1 (Rear)

SYSTEM PORT #2 (Rear)
Expresscard
RFU
RFU

REQ/GNT#
0

1
3

Programable

Hex

-

D2h
A0h
A2h

D4h
C8h

-

-

A2h
58h
16h
12h
5Eh

-

70h

Interrupts
A

D,C
B,D

Bus

SMBUS Master

Clock, Unused Clock Output Disable

-

­Spread spectrum Clock Generator

-

-

-

-

-

-

-

I2C Bus

LCD informationA0h

Voltage Rails

VDC
P5V_ALW
P5V_AUX
P3.3V_AUX
P3.3V_LAN
P2.5V_LAN
P1.2V_LAN
P3.3V_ALW
P1.8V_AUX
VCC_CORE
VTT

P5V
P1.5V

P2.5V
P3.3V
MEM_0.9V

Primary DC system power supply (9 to 21V)

5.0V LDO power rail for MAC III(off in S4-S5 without AC Adapter)

5.0V power rail (off in S4-S5)

3.3V power rail (off in S4-S5)

3.3V power rail (off in S4-S5 without AC ADAPTER)

2.5V power rail (off in S4-S5 without AC adapter)

1.25V power rail (off in S4-S5 without AC adapter)

3.3V LDO power rail for MAC III(off in S4-S5 without AC Adapter
GMCH/DDR II Power Source(off in S4-S5)
Core voltage for DOTHAN CPU (0.74~1.30V)
GMCH core, CPU/GMCH FSB Termination.

5.0V switched power rail (off in S3-S5)

1.5V switched power rail (off in S3-S5)

1.8V switched power rail (off in S3-S5)

2.5V switched power rail (off in S3-S5)

3.3V switched power rail (off in S3-S5)
DDR2 Termination (off in S3-S5)

SIL1362(DVI)P1.8V

C

B

A

POWER

P3.3V_LAN

P5V_ALW
P3.3V_ALW MEM_VREF

MAC III
ICH6-M
Flash Memory
Thermistor

P2.5V_LAN
P1.2V_LAN

BCM5751M
LED

4

P5V_AUX

ICH6
USB
STAC9751

P3.3V_AUX

ICH6
MINI-PCI

THERMISTOR

P1.8V_AUX

G MCH
SODIMM

P1.5V_AUX

ICH6

Memory

P5V

ICH4
PCI6515

MINI-PCI
STAC9751

MDC
MAC III
HDD

TOUCHPAD
PCI BUFFER

3

P3.3V

ICH6
PCI6515
MINI-PCI
STAC9751

SODIMM
MAC III
LED

MDC

HDD
FIR
CLOCK
BLUETOOTH

P2.5V

GMCH
ICH
DVI

P1.8V

DVI

P1.5V

MGM
ICH6

MEM_0.9

Memory

VTT

CPU
GMCH

VCC_CORE

CPU

2

A

SAMSUNG

1

This Sheet of Engineering drawings and specifications contains Confidential,

Trade Secret and other Proprietary information of Dell Computer Corporation ( "Dell" ).

This document may not be transferred or copied without the express written authorization of Dell.

In addition, neither this sheet nor the information it contains may be used by or

disclosed to any third party without Dell’s express written consent.

This drawing is property of SEC, Use or copy of this drawing without proper permission

of the appropriate technical-document managing department is prohibited

3

Rev.

No

24

2 Chips solution are propsed by ICS.

CY28411ZXCT : Lead free version

1

D

FSA

BSEL0

CPU

C

SMB3_CLK

SMB3_DATA

Q27
RHU002N06
Q25
RHU002N06

B

CLK3_SSCIN

CLK3_SMBDATA

CLK3_SMBCLK

CLK3_PWRGD*

A

Place SSCG close to ALVISO.
in order to minize the stub.

FSB

00

0

0
0

1

0

1

1

0
0

1
1

1
1

18-B316-D2

48-B424-B4

16-D218-B3 24-B448-B3

P5V

R823

10K

D

3

G

1

S

2

48-C34-B1

4-B3 13-B413-B24-B4

FSC

BSEL2BSEL1

G

1

4

0
1
0
1
0
1
0
1

D

3

S

2

48-C2 4-A44-B313-B213-B4

49-C3 4-A44-B313-B213-B4

49-C34-B4 13-B2 13-B44-B3
48-C2

41-B431-A427-C3

HOST CLK

266 MHz
333 MHz
200 MHz
400 MHz
133 MHz
100 MHz
166 MHz
RSVD1

P3.3V

10K

10K

R223

R219

No Stuff

48-C24-C3

Bus Selection for CK-410M (133MHz)
FSB/FSC : by CPU/ MCH BSEL(Page 6)
FSA : P3.3V PU

CLK3_CB48

CLK3_USB48

CLK3_BSEL1
CLK3_BSEL2

CHP3_PCISTP*

CHP3_CPUSTP*

CLK3_PWRGD*

CLK3_PCLKCB

CLK3_PCLKSIO

CLK3_PCLKDOCK

CLK3_PCLKMIN

CLK3_PCLKICH6M

CLK3_PCLKBCM

CLK3_SMBCLK

CLK3_SMBDATA

CLK3_SMBCLK
CLK3_SMBDATA

P3.3V

SSCD
MK1493-05

10K

R607

R608

CY25823ZC

U9
CY25823ZC

2

S3

3

S2

4

S1

1

CLK_IN

8

SDATA

7

SCLK

5

PWRDWN

6

REFOUT_SEL

33
1%

10K

R603

10K

R602

10K

R604

10K

R605

10K

R65

10K

R66

CLK3_AUD14_1

CK-410M
ICS954201

CY28411ZC

48-C422-B2

48-C3

16-A3

16-B2
4-A3 9-A46-C4
4-A3 9-A46-C4

49-A416-C2

16-C2 41-C449-A46-C4

22-B4 48-C2

28-C3 49-D3

36-B4 49-B3

34-C4

49-C216-C3

24-B4 49-D3

Place 14.318MHz within
500mils of CK-410M

VDDA

VDD

CLK_OUT

CLK_OUT*

IREF

VSSIREF

VSS

VSSA

0

R647

0

R648

49-D34-B1

1%

49.9

R817

R221

C823

4700nF

6.3V

4700nF

1%

1%

49.9

49.9

R229

R818

2.2

C265

6.3V

1%

49.9

R228

1%

49.9

R809

1%

49.9

R808

P3.3V

1%

49.9

R811

C796

1000nF

6.3V

P3.3V

MMZ1608S121AT
B524

49-D3 4-A4
16-B248-C3 16-A3

1%

1%

1%

49.9

49.9

49.9

R810

R224

R225

CLK0_HCLK0

6-C3

CLK0_HCLK0*

6-C3

CLK0_HCLK1

8-B2

CLK0_HCLK1*

8-B2

CLK0_ITP

7-B4

CLK0_ITP*

7-B4

CLK1_MCH3GPLL

9-D4

CLK1_MCH3GPLL*

9-D4

CLK1_PCIEICH

16-B1

CLK1_PCIEICH*

16-B1

CLK1_PCIELAN

24-C4

CLK1_PCIELAN*

24-C4

CLK1_DOTCLK

9-A1

CLK1_DOTCLK*

9-A1

CLK1_DREFCLK

9-A2

CLK1_DREFCLK*

9-A2

CLK3_SSCIN

4-A448-C3

CLK3_AUD14_1
CLK3_ICH14
CLK3_SIO14

28-B348-C3

Place Termination close to CK-410M

P3.3V

C598

47nF
25V

1

D

C

B

A

SAMSUNG

R806
R805

R803
R802

R804
R807

R822
R821

R820
R819

R801
R800

R794
R795

R799
R796

P3.3V

MMZ1608S121AT
B525

33
33

33
33

33
33

33
33

33
33

33
33

33
33

33
33

5.1

R748

5.1

R747

5.1

R746

5.1

R745

100nF

16V

C260

100nF

16V

C825

1%
1%

1%
1%

1%
1%

1%
1%

1%
1%

1%
1%

1%
1%

1%
1%

1%
1%

1%
1%

P3.3V

10K

10K

R737

R791

10

R790

10

R797

5%

48-C24-A4 41-B431-A427-C3

R740
R739
R741
R744
R798
R738

48-C24-A4 13-B413-B24-B4
49-C34-B4 13-B213-B44-A4

1

0.033nF

Y503

C800

14.31818MHz

1%

33

1%

33

1%

33

1%

33

1%

33

1%

33

0

R743

2

0.033nF

C799

475

R222

1%

25V47nF

C824

25V

47nF

C264

6.3V1000nF

16V10nF

C798

C832

U523
CY28411ZXCT

21

VDD_SRC0

28

VDD_SRC1

34

VDD_SRC2

1

VDD_PCI0

7

VDD_PCI1

42

VDD_CPU

12

FSA_USB48

16

FSB_TESTMODE

53

FSC_TESTSEL

55

PCI_STOP*

54

CPU_STOP*

10

VTT_PWRGD*_PD

5

PCI5
PCI4

3

PCI3

56

PCI2

9

PCIF1

8

PCIF0_ITPEN

46

SCLK

47

SDATA

50

XTAL_IN

49

XTAL_OUT

39

IREF

13

VSS_48

29

VSS_SRC

45

VSS_CPU

2

VSS_PCI0

6

VSS_PCI1

51

VSS_REF

25V

47nF

C261

25V47nF

25V47nF

C834

C262

CPU2_ITP_SRC7

CPU2*_ITP_SRC7*

47nF 25V

C263

10000nF

VDD_REF

VDD_48

VDD_A
VSS_A

CPU1

CPU1*

CPU0

CPU0*

SRC6

SRC6*

SRC5

SRC5*

SRC4

SRC4*

SRC3

SRC3*

SRC2

SRC2*

SRC1

SRC1*

SRC0

SRC0*

DOT96

DOT96*

REF

C833

6.3V

48
11

37
38

41
40

44
43

36
35

33
324

31
30

26
27

24
25

22
23

19
20

17
18

14
15

52

Trace Width *2

SMBUS Address "D2h"

P3.3V

1%

1%

1%

1%

1%

49.9

R789

49.9

R788

49.9

R787

49.9

R786

1%

49.9

R793

49.9

R792

C600

C599

10000nF

100nF

16
9

12

R637

11

R636

14
13

10
15

6.3V

1%33

33 1%

1%

1%

1%

475

49.9

49.9

R609

R635

R638

CLK3_AUD14

26-B448-C3

9-A2 9-A1

9-A19-A2

CLK1_DREFSSCLK

CLK1_DREFSSCLK*

CLK3_BSEL1
CLK3_BSEL2

3

VTT

VTT

R49

R50

10K

10K

9-A46-C44-C3
9-A46-C44-C3

R47

R52

0

0

2

This Sheet of Engineering drawings and specifications contains Confidential,

Trade Secret and other Proprietary information of Dell Computer Corporation ( "Dell" ).

This document may not be transferred or copied without the express written authorization of Dell.

In addition, neither this sheet nor the information it contains may be used by or

disclosed to any third party without Dell’s express written consent.

This drawing is property of SEC, Use or copy of this drawing without proper permission

of the appropriate technical-document managing department is prohibited

4

3

2

1

Rev.

No

D

VTT

47

C25
E23
B23
C26
E24
D24
B24
C20
B20
A21
B26
A24
B21
A22
A25
A19
D25
C23
C22

K25
N25
H26
M25
N24
L26

M23
G24

F25
H24
M26
L23
G25
H23

K24
L24

J25
J23

J26

CPU500-2

D15*
D14*
D13*
D12*
D11*
D10*
D9*
D8*
D7*
D6*
D5*
D4*
D3*
D2*
D1*
D0*
DINV0*
DSTBN0*
DSTBP0*

D31*
D30*
D29*
D28*
D27*
D26*
D25*
D24*
D23*
D22*
D21*
D20*
D19*
D18*
D17*
D16*
DINV1*
DSTBN1*
DSTBP1*

D47*
D46*
D45*
D44*
D43*
D42*
D41*
D40*
D39*
D38*

DATA GRP 2

D37*

DATA GRP 0DATA GRP 1

D36*
D35*
D34*
D33*
D32*

DINV2*

DSTBN2*

DSTBP2*

D63*
D62*
D61*
D60*
D59*
D58*
D57*
D56*
D55*
D54*

DATA GRP 3

D53*
D52*
D51*
D50*
D49*
D48*

DINV3*

DSTBN3*

DSTBP3*

Y25
AA26
Y23
V26
U25
V24
U26
AA23
R23
R26
R24
V23
U23
T25
AA24
Y26
T24
W25
W24

AF26
AF22
AF25
AD21
AE21
AF20
AD24
AF23
AE22
AD23
AC25
AC22
AC20
AB24
AC23
AB25
AD20
AE24
AE25

CPU1_D*(47:32)CPU1_D*(15:0)

48-B3

48-B3 8-B2

8-D3

8-B2
8-B2
8-B2

8-D3

8-B2
8-B2

CPU1_DBI2*
CPU1_DSTBN2*
CPU1_DSTBP2*

CPU1_D*(63:48)

CPU1_DBI3*
CPU1_DSTBN3*
CPU1_DSTBP3*CPU1_DSTBP1*

47
46
45
44
43
42
419
40
39
38
37
36
35
34
33
32

63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48

CPU500-1

CPU1_A*(16:3)

CPU1_ADSTB0*

C C

CPU1_REQ*(4:0)

CPU1_A*(31:17)

CPU1_ADSTB1*

8-D2

8-C2
8-B2

8-D2

8-C2

16
15
14
13
12
11
10
9
8
7
6
5
4
3

4
3
2
1
0

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

1 / 4 2 / 4

AA2
AA3

AF1
AE1
AF3
AD6
AE2
AD5
AC6
AB4
AD2
AE4
AD3
AC3
AC7
AC4
AF4
AE5

A16*

Y3

A15*
A14*

U1

A13*

Y1

A12*

Y4

A11*

W2

A10*

T4

A9*

W1

A8*

V2

A7*

R3

A6*

V3

A5*

U4

A4*

P4

A3*

U3

ADSTB0*

T1

REQ4*

P1

REQ3*

T2

REQ2*

P3

REQ1*

R2

REQ0*
A31*

A30*
A29*
A28*
A27*
A26*
A25*
A24*
A23*
A22*
A21*
A20*
A19*
A18*
A17*
ADSTB1*

BPRI*

DBSY*

DEFER*

DRDY*

ADDR GROUP 0

HITM*

IERR*

LOCK*
TRDY*

RESET*

A20M*
FERR*

IGNNE*

LINT0

ADDR GROUP 1

LINT1

LEGENCY CPU

STPCLK*

ADS*
BNR*

BR0*

DBR*

HIT*

INIT*

RS2*
RS1*
RS0*

SMI*

R48

N2
L1
J3
N4

A7
M2
L4
H2

K3
K4

A4
B5
J2
M3

B11
L2
K1
H1

C2
D3
A3

D1
D4
B4
C6

48-C4 8-A2
48-C4 8-A2
48-C4 8-A2

48-C3 15-C2
48-B3 15-C1
49-D3 15-C2

48-C4 15-C2
48-B4 15-B2
48-C4 15-B2
49-C3 15-B2

48-C4 8-C2
48-C4 8-C2
48-C3 8-C2

48-B3
49-D3 8-B2
48-B3 8-B2

48-C4 8-B2
48-B3 8-B2

48-B315-C2
48-B3 8-B2
48-B3 8-A2

8-C248-B3

7-A330-B2
8-B2

7-A38-C2

CPU1_ADS*
CPU1_BNR*
CPU1_BPRI*
CPU1_BREQ*

ITP3_DBRESET*
CPU1_DBSY*
CPU1_DEFER*
CPU1_DRDY*

CPU1_HIT*
CPU1_HITM*

CPU1_INIT*
CPU1_LOCK*
CPU1_TRDY*

CPU1_CPURST*
CPU1_RS2*
CPU1_RS1*
CPU1_RS0*

CPU1_A20M*
CPU1_FERR*
CPU1_IGNNE*

CPU1_INTR
CPU1_NMI
CPU1_SMI*
CPU1_STPCLK*

CPU1_DBI0*

CPU1_DSTBN0*

CPU1_DSTBP0*

CPU1_D*(31:16)

CPU1_DBI1*

CPU1_DSTBN1*

8-D3

8-B2
8-B2

8-D3

8-B2
8-B2

15
14
13
12
11
10

8
7
6
5
4
3
2
1
0

48-B38-B2

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16

48-B38-B2

B B

D

A

A

SAMSUNG

34 2

1

This Sheet of Engineering drawings and specifications contains Confidential,

Trade Secret and other Proprietary information of Dell Computer Corporation ( "Dell" ).

This document may not be transferred or copied without the express written authorization of Dell.

In addition, neither this sheet nor the information it contains may be used by or

disclosed to any third party without Dell’s express written consent.

This drawing is property of SEC, Use or copy of this drawing without proper permission

of the appropriate technical-document managing department is prohibited

4

3

2

1

Rev.

No

D

D

P3.3V_ALW

VTT

CPU500-3

3 / 4

48-C415-C28-A2

27.4

54.9 1%

1%54.9

R186

B15

BCLK0

B14

BCLK1

A16

ITP_CLK0

A15

ITP_CLK1

A6

SLP*

B7

DPSLP*

G1

DPRSTP*

C19

DPWR*

E4

PWRGOOD

5

H4

VID5

4

G4

VID4

3

G3

VID3

2

F3

VID2

1

F2

VID1

0

E2

VID0

B17

PROCHOT*

B18

THERMDA

A18

THERMDC

C17

THERMTRIP*

C14

BSEL1

C16

BSEL0

E1

0

PSI*

AD26

GTLREF0

AB1

1%54.9

COMP3

AB2

1%

COMP2

P26

COMP1

P25

1%27.4

COMP0

AE7

VCCSENSE

AF6

VSSSENSE

B2

NC1_RSVD1

C3

RSVD2

AF7

RSVD3

AC1

RSVD4

E26

RSVD5

C5

TEST1

F23

TEST2

HCLKPWR MGMTVIDTHERMMISC

CLK0_HCLK0

CLK0_HCLK0*

VTT

CPU1_SLP*

R81

CPU1_DPSLP*

200

CPU1_DPRSTP*

1%

CPU1_PWRGDCPU

15-C2

CPU1_DPWR*

CPU1_VID(5:0)

C

CPU1_PROCHOT*

CPU2_THERMDA
CPU2_THERMDC

0.5" max length

C224

100nF

CPU1_THRMTRIP*

CLK3_BSEL1
CLK3_BSEL2

CHP3_CPUSTP*

VTT

R164

1K
1%

R187

2K
1%

GTLREF : Keep the Voltage divider within 0.5"
of the first GTLREF0 pin with Zo=55ohm trace.

B

A

Minimize coupling of any switching signals to this net.

COMP0,2(COMP1,3) should be connected with Zo=27.4ohm(55ohm)
trace shorter than 1/2" to their respective Banias socket pins.

GND test points within 100mil of the VCC/VSSsense at the end of the line.
Route the VCC/VSSsense as a Zo=55ohm traces with equal length.
Observe 3:1 spacing b/w VCC/VSSsense lines and 25mil away
(preferred 50mil) from any other signal. And GND via 100mil away
from each of the VCC/VSS test point vias.

Std Voltage Dothan with 533 Mhz FSB updates
VCC (High Frequency Mode) = 1.26 V - 1.356 V (VID values)
TDP (Highest Frequency Mode) =27W (no change)
VCC (Lowest Frequency Mode) = 0.988 V (VID value)
TDP (Lowest Frequency Mode ) = 13.8 W

6-C2 49-B3

49-C331-C2
49-C331-D2
49-C231-C4

4-A3 4-C3 9-A4

49-A4

9-A44-C34-A3

41-C416-C24-C3

4-C1
4-C1

49-D315-C2

15-C2 49-C3

48-B38-B2

41-C4
49-D3

R689
R688
R660
R661

R80

1%

54.9

R185

VCCA3
VCCA2
VCCA1

VCCAVCCPXDP/ITP

VCCA0
VCCP1

VCCP2
VCCP3
VCCP4
VCCP5
VCCP6
VCCP7
VCCP8

VCCP9
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16
VCCP17
VCCP18
VCCP19
VCCP20
VCCP21
VCCP22
VCCP23
VCCP24
VCCP25

VCCQ1

VCCQ0

PREQ*
PRDY*
BPM3*
BPM2*
BPM1*
BPM0*

TRST*

TDO
TMS

TCK

AC26
N1
B1
F26

D10
D12
D14
D16
E11
E13
E15
F10
F12
F14
F16
K6
L5
L21
M6
M22
N5
N21
P6
P22
R5
R21
T6
T22
U21

W4
P23

B10
A10
C9
A9
B8
C8

A13

7-B4 7-B3

C12

TDI

A12
C11
B13

VTT

7-B4
7-B4
7-B4
7-B4
7-B4
7-B4

7-B3
7-B3
7-B3
7-B3

ITP I/F Signal

P1.5V

C644

C643

10000nF

100nF

6.3V

One 0.1uF & 10uF cap for each VCCA pin.

CPU1_PREQ*
CPU1_PRDY*
CPU1_BPM3*
CPU1_BPM2*
CPU1_BPM1*
CPU1_BPM0*

CPU1_TCK
CPU1_TDI
CPU1_TDO
CPU1_TMS
CPU1_TRST*

R51

54.9
1%

CPU1_PROCHOT*

R53

49-B36-C4

1%

CPU Core Voltage Table

VID(5:0)

0

0

0

0

0

0

0
0

0

0

0

0

0

0

0
0

0

1

0

0

0

1

0

1

0

0

0

-

0

0

0

1

0

1

0

0

0

0

0

0

0

0

1

0

1

0

0

0

1

0

1

1

1

0

0

1

0

0

1

0

0

1

1

0

0

1

0

0

00

1

0

0

01

1

0

1

0

0

1

0

1

0

1

1

0

0
0

0

1

0

1

0

1

1

1

0

1

0

1

1

0

0

1

1

0

0
0

1

0

1

0

1

1

1

1

1

1

0

1

1

0

1

11

0

1

1

HFM Voltage
770 : 1.26V ~ 1.372V
730,740,750,760 : 1.26 ~ 1.356
In case of Deeper sheep, core voltage is 0.726V.

Voltage

0

0

1.708 V

0

1.692 V

1

1.676 V

0

1

1.660 V

1

1
0

1.644 V

0

1

1.628 V

1

1.612 V

0

1

1.596 V

1

1

0

0

1.580 V

0

1.564 V

1
0

1

1.548 V

1

1.532 V

1

1.516 V

00

0

1.500 V

0

1

1

0

1.484 V

1

1.468 V

1
0

1.452 V

0

0

1

1.436 V

1

1.420 V

0

1

1.404 V

1

1.388 V

0

0

1

1.372 V

111

1.356 V

0
1

1

1

1

1.340 V

0

1.324 V

0

1.308 V

0

1

1.292 V

0

1

1.276 V

1

1
0

0

1.260 V

0

1.244 V

1
0

1.228 V

1
1

1.212 V

1

P3.3V

R552

1.5K
1%

3

1

475

2

1

Q508
MMBT3904LT1G

3

2

VID(5:0)

0

1

0

0

0

0

0

1

0

1

0

0

1

0

1

0

1

0

0

0

1

0

-

1

01

1

0

1

1

0

1

01

1

0

1

101

0

1

1

1

1

1

0

1
1

0

1
1

1

1

1

000

1

0

1

1

0

1

1

0

1

10

0

1

1

0

1

0

1

1

0

1

1

1

11

1

1

1

1

1

1

1

1

1

1
1

1

1

1

1

1
1

1

1

1

0

0

1

0

0

0

1

1

1

0

0

1

00

1

0

1

1

1

0

1

1

1

1

1
0

0

0

0

0

0

0

0

1

1

1

0

0

1

1

0
1

1

0
1

10

1

0

0

0

1

0

0

1
1

0

1

1

0

0
1

1

0
1

0

1
1

1

1

1

1

0

0

0
0

1

0
0

1

0

1

0

1

1

0

0
0

1

1
11

0

1
1

11

R551

10K

28-B349-A3

Q510
MMBT3904LT1G

Voltage

1.196 V

1.180 V0

1.164 V

1.148 V

1.132 V

1.116 V

1.100 V

1.084 V

1.068 V

1.052 V

1.036 V

1.020 V

1.004 V

0.988 V

0.972 V

0.956 V

0.940 V

0.924 V

0.908 V

0.892 V

0.876 V

0.860 V

0.844 V

0.828 V

0.812 V

0.796 V

0.780 V

0.764 V

0.748 V

0.732 V

0.716 V

0.700 V

KBC3_PROCHOT*

LFM

C

B

A

SAMSUNG

4

3

2

1

This Sheet of Engineering drawings and specifications contains Confidential,

Trade Secret and other Proprietary information of Dell Computer Corporation ( "Dell" ).

This document may not be transferred or copied without the express written authorization of Dell.

In addition, neither this sheet nor the information it contains may be used by or

disclosed to any third party without Dell’s express written consent.

This drawing is property of SEC, Use or copy of this drawing without proper permission

of the appropriate technical-document managing department is prohibited

4

3

2

1

Rev.

No

D

AF19

AF21

AE14

AE16

AE18

AE20

AE23

AE26

AF2

AF5

VSS179

VSS147

AB19

AB21

VSS180

VSS181

VSS148

VSS149

AB26

AB23

VSS182

VSS183

VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72

VSS150

VSS151

AC2

AF9

VSS184

VSS152

AC5

AC8

VSS185

VSS153

AD15

AD17

AD19

AD22

AD25

AE3

AE6

AE8

AE10

VSS169

VSS170

VSS137

VSS138

AB3

AA25

VSS171

VSS172

VSS140

VSS139

AB5

AB7

VSS173

VSS174

VSS141

VSS142

AB9

AB11

AE12

VSS175

VSS176

VSS143

VSS144

AB13

AB15

VSS177

VSS178

VSS145

VSS146

AB17

AD1

AD4

AD7

AD9

AD11

VSS161

VSS162

VSS163

VCC_CORE

VSS129

VSS130

VSS131

AA6

AA8

AA10

AA12

AD13

VSS164

VSS165

D6

D8
D18
D20
D22

E5

E7

E9
E17
E19
E21

F6

F8
F18
F20
F22

G5
G21

H6
H22

J21

K22

U5

V6
V22

W5

W21

Y6
Y22
AA5
AA7
AA9

AA11
AA13
AA15

VSS132

VSS133

AA14

AA16

VSS166

J5

VSS134

AA18

VSS167

VSS135

VSS168

CPU500-4

4 / 4

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36

VSS136

AA20

AA22

VCC_CORE

C174

10000nF
4V

C740

C218

10000nF
4V

C175

10000nF
4V 4V

C222

10000nF 10000nF

10000nF
4V

4V

C128

C173

10000nF

10000nF

4V

4V

C219

10000nF
4V

C127

10000nF
4V

C89

10000nF
4V

C171

10000nF
4V

C212

4V

C742

10000nF
4V

C214

10000nF
4V

C220

10000nF
4V

C84

10000nF
4V

C123

10000nF
4V

C81

10000nF
4V

C176

10000nF
4V

C217

10000nF
4V

C223

10000nF
4V

C82

10000nF
4V

C129

10000nF
4V

C216

10000nF
4V

C122

10000nF
4V

C126 C213

10000nF
4V

C221

10000nF
4V

C124

10000nF
4V

C177

10000nF
4V

C215

10000nF
4V

C88

10000nF
4V

C172

10000nF
4V

C86

10000nF

10000nF
4V

C90

10000nF
4V

C

VTT

C125
330uF

2.5V
AL

B

CPU1_PREQ*

CPU1_PRDY*
CPU1_BPM3*
CPU1_BPM2*
CPU1_BPM1*
CPU1_BPM0*

CLK0_ITP

CLK0_ITP*

CPU1_TCK

C83

100nF

C132

100nF

6-B3
6-B3
6-B3
6-B3
6-B3
6-B3

4-C1
4-C1

7-B36-B3

C120

100nF

C121

100nF

J520
CONN-28P-FPC

13

BPM5*

15

BPM4*

17

BPM3*

19

BPM2*

21

BPM1*

23

BPM0*

9

BCLK

8

BCLK*

11

FBO

10

GND1

14

GND2

16

GND3

18

GND4

20

GND5

22

GND6

C85

100nF

VTT1
VTT2

VTAP

TDO
TMS

TRST*

RESET*

DBR*
DBA*

TCK

NC1
NC2

C131

C130

100nF

100nF

C87

100nF

VTT

27
28

26
5

1

TDI

7
2
3

12
25

24
4

6

R588

R29

100nF16V

C596

C118

100nF

C119

100nF

P3.3V_AUX

1%

150

R46

22.6
1%

22.6
1%

VTT

1%

40.2

R30

1%

27.4

VTT

1%

1%

150

54.9

54.9

near the CPU

R590

R587

R589

CPU1_TCK

6-B37-B4

CPU1_TDI

6-B3

CPU1_TDO

6-B3

CPU1_TMS

6-B3

CPU1_TRST*

6-B3

CPU1_CPURST*

5-C38-C2

ITP3_DBRESET*

30-B2 5-C3

475

A2

VSS1

A5

VSS2

A8

VSS3

A11

VSS4

A14

VSS5

A17

VSS6

A20

VSS7

A23

VSS8

A26

VSS9

B3

VSS10

B6

VSS11

B9

VSS12

B12

VSS13

B16

VSS14

B19

VSS15

B22

VSS16

B25

VSS17

C1

VSS18

C4

VSS19

C7

VSS20

C10

VSS21

C13

VSS22

C15

VSS23

C18

VSS24

C21

VSS25

C24

VSS26

D2

VSS27

D5

VSS28

D7

VSS29

D9

VSS30

D11

VSS31

D13

VSS32

D15

VSS33

D17

VSS34

D19

VSS35

D21

VSS36

D23

VSS37

D26

VSS38

E3

VSS39

E6

VSS40

E8

VSS41

E10

VSS42

E12

VSS43

E14

VSS44

E16

VSS45

E18

VSS46

E20

VSS47

E22

VSS48

E25

VSS49

F1

VSS50

F4

VSS51

F5

VSS52

F7

VSS53

F9

VSS54

F11

VSS55

F13

VSS56

F15

VSS57

F17

VSS58

F19

VSS59

F21

VSS60

F24

VSS61

G2

VSS62

G6

VSS63

G22

VSS64

AF11

AF13

AF15

VSS186

VSS187

VSS188

VCC_CORE

AA17
AA19
AA21
AB6
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC9
AC11
AC13
AC15
AC17
AC19
AD8
AD10
AD12
AD14
AD16
AD18
AE9
AE11
AE13
AE15
AE17
AE19
AF8
AF10
AF12
AF14
AF16
AF18

VSS154

VSS155

VSS156

AC10

AC12

AC14

AF17

VSS189

VSS157

AC18

AC16

AF24

VSS190

VSS191

VSS158

VSS159

AC21

AC24

VSS192

VSS160

VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128

G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1
M4
M5
M21
M24
N3
N6
N22
N23
N26
P2
P5
P21
P24
R1
R4
R6
R22
R25
T3
T5
T21
T23
T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24
AA1
AA4

D

C

B

J520 connector didn’t place in the board.

R591

R592

AA

SAMSUNG

3

24

1

This Sheet of Engineering drawings and specifications contains Confidential,

Trade Secret and other Proprietary information of Dell Computer Corporation ( "Dell" ).

This document may not be transferred or copied without the express written authorization of Dell.

In addition, neither this sheet nor the information it contains may be used by or

disclosed to any third party without Dell’s express written consent.

This drawing is property of SEC, Use or copy of this drawing without proper permission

of the appropriate technical-document managing department is prohibited

4

3

2

1

Rev.

No

R662

24.9
1%

U514-1
915GM(DELL)

1 / 5

E4

HD0*

E1

HD1*

F4

HD2*

H7

HD3*

E2

HD4*

F1

HD5*

E3

HD6*

D3

HD7*

K7

HD8*

F2

HD9*

J7

HD10*

J8

HD11*

H6

HD12*

F3

HD13*

K8

HD14*

H5

HD15*

H1

HD16*

H2

HD17*

K5

HD18*

K6

HD19*

J4

HD20*

G3

HD21*

H3

HD22*

J1

HD23*

L5

HD24*

K4

HD25*

J5

HD26*

P7

HD27*

L7

HD28*

J3

HD29*

P5

HD30*

L3

HD31*

U7

HD32*

V6

HD33*

R6

HD34*

R5

HD35*

P3

HD36*

T8

HD37*

R7

HD38*

R8

HD39*

U8

HD40*

R4

HD41*

T4

HD42*

T5

HD43*

R1

HD44*

T3

HD45*

V8

HD46*

U6

HD47*

W6

HD48*

U3

HD49*

V5

HD50*

W8

HD51*

W7

HD52*

U2

HD53*

U1

HD54*

Y5

HD55*

Y2

HD56*

V4

HD57*

Y7

HD58*

W1

HD59*

W3

HD60*

Y3

HD61*

Y6

HD62*

W2

HD63*

C1

HXRCOMP

C2

HXSCOMP

D1

HXSWING

T1

HYRCOMP

L1

HYSCOMP

P1

HYSWING

R165

24.9
1%

HOST

HA3*
HA4*
HA5*
HA6*
HA7*
HA8*

HA9*
HA10*
HA11*
HA12*
HA13*
HA14*
HA15*
HA16*
HA17*
HA18*
HA19*
HA20*
HA21*
HA22*
HA23*
HA24*
HA25*
HA26*
HA27*
HA28*
HA29*
HA30*
HA31*

HADS*
HADSTB*0
HADSTB*1

HVREF
HBNR*

HBPRI*

HBREQ0*

HCPURST*

HCLKINN
HCLKINP

HDBSY*

HDEFER*

HDINV*0
HDINV*1
HDINV*2
HDINV*3
HDPWR*

HDRDY*
HDSTBN*0
HDSTBN*1
HDSTBN*2
HDSTBN*3
HDSTBP*0
HDSTBP*1
HDSTBP*2
HDSTBP*3

HEDRDY*

HHIT*

HHITM*

HLOCK*

HPCREQ*

HREQ*0

HREQ*1

HREQ*2

HREQ*3

HREQ*4

HRS0*
HRS1*
HRS2*

HCPUSLP*

HTRDY*

CPU1_ADS*
CPU1_ADSTB0*
CPU1_ADSTB1*

CPU1_BNR*
CPU1_BPRI*
CPU1_BREQ*
CPU1_CPURST*

CLK0_HCLK1*
CLK0_HCLK1

CPU1_DBSY*
CPU1_DEFER*
CPU1_DBI0*
CPU1_DBI1*
CPU1_DBI2*
CPU1_DBI3*
CPU1_DPWR*
CPU1_DRDY*
CPU1_DSTBN0*
CPU1_DSTBN1*
CPU1_DSTBN2*
CPU1_DSTBN3*
CPU1_DSTBP0*
CPU1_DSTBP1*
CPU1_DSTBP2*
CPU1_DSTBP3*

CPU1_HIT*
CPU1_HITM*
CPU1_LOCK*
CPU1_REQ*(4:0)

5-C348-C4

5-C3

5-C45-D4

CPU1_RS0*
CPU1_RS1*
CPU1_RS2*
CPU1_SLP*
CPU1_TRDY*

G9
C9
E9
B7
A10
F9
D8
B10
E10
G10
D9
E11
F10
G11
G13
C10
C11
D11
C12
B13
A12
F12
G12
E12
C13
B11
D13
A13
F13

F8
B9
E13
J11
A5
D5
E7
H10

AB1
AB2

C6
E6
H8
K3
T7
U5
G6
F7
G4
K1
R3
V3
G5
K2
R2
W4
F6
D4
D6
B3
A11
A7
D7
B8
C7
A8
A4
C5
B4
G8

R82

B5

3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

48-C4 5-D3

5-C4
5-B4

48-C4 5-C3
48-C3 5-C3
48-B3 5-C3

7-A3 5-C3

4-C1
4-C1

48-B3 5-C3
48-B3

5-C3
5-C2

49-D3

5-B248-B3
48-B3 5-C1
48-B3 5-B1
48-B3 6-C3

5-C3

48-B3

5-C2

5-B2

5-C1

5-B1

5-C2

5-B2

5-C1

5-B1

5-C3

48-C4

5-C348-B3
48-B3 5-C3

5-C4

0
1
2
3
4

48-C4 5-C3

48-C4 5-C3

0

48-C4 15-C2 6-C3

48-B3

CPUSLP
Dothan A stepping : Stuff resistor on SLP* of ICH6-M

Dothan B stepping : Stuff resistor on SLP* of GMCH.

CPU1_A*(31:3)

VTT

R112

100
1%

0.7V

R111

C133

200

100nF

1608

1%

Placed as close as possible.

D

C

B

A

D

CPU1_D*(63:0)

C

VTT

R663

221
1%

R664

100
1%

C693

100nF

Trace should be 10-mil wide
with 20mil spacing.

49-B3 8-A3

0.327V

MCH1_HXSWING

VTT

Trace should be 10-mil wide

C727

100nF

49-B3 8-A3

with 20mil spacing.

MCH1_HYSWING

0.327V

MCH1_HXSWING

MCH1_HYSWING

Trace should be 10-mil wide
with 20mil spacing.

R692

221

B

1%

R690

100
1%

5-C1 5-C2 5-D1 5-D2

VTT

R691

54.9
1%

8-C4 49-B3

8-B4 49-B3

R632

54.9
1%

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

A

SAMSUNG

4

3

2

1

This Sheet of Engineering drawings and specifications contains Confidential,

Trade Secret and other Proprietary information of Dell Computer Corporation ( "Dell" ).

This document may not be transferred or copied without the express written authorization of Dell.

In addition, neither this sheet nor the information it contains may be used by or

disclosed to any third party without Dell’s express written consent.

This drawing is property of SEC, Use or copy of this drawing without proper permission

of the appropriate technical-document managing department is prohibited

A
B

TV DAC

Component

D

C

Place 75 ohm termination resistors
close to GMCH

C

VGA3_BLUE_INT

VGA3_GREEN_INT

VGA3_RED_INT

RED, GREEN, BLUE
are GND referenced

B

LCD2_BIAPWM

CFG#
CFG(5)

A

CFG(6)
CFG(7)
CFG(9)
CFG(16)

CFG(19)
SDVODTA

4

Composite

Pb

CVBS

Y
Pr

DVO2_CTRLDATA

DVO2_CTRLCLK

CLK1_MCH3GPLL*

CLK1_MCH3GPLL

TVO3_COMP

TVO3_Y_G
TVO3_C_R

VGA2_DDCCLK

VGA2_DDCDATA

20-A4

20-A2
49-D2

20-A2

20-A4

49-C2

20-A4

20-A2
49-B3

49-C427-C2

Current Setting

Low

DMIx2
DDR-2

DT/Transportable
PEG Reversal
Dynamic ODT
Disabled

VCC 1.05V (def.)
VTT 1.05V (def.)
No (def.)

21-B3 49-C3
4-C1
4-C1

36-B1

20-B4 49-A4

VGA3_VSYNC

1%

VGA3_HSYNC

150 1%

150 1%

255 1%

150

LCD2_BIAPWM

R122

R123

R121

R120

LCD2_BKLTON

LCD2_DDCCLK

LCD2_DDCDATA

LCD2_VDDEN

R127

1.5K
1%

LCD1_CLK*

LCD1_CLK

LCD1_DATA0*
LCD1_DATA1*
LCD1_DATA2*

LCD1_DATA0
LCD1_DATA1
LCD1_DATA2

R126

100K

(def. : default Option)

High
DMIx4 (def.)

DDR-1

Mobile CPU (def.)
Normal
Enabled (def.)

VCC 1.5VCFG(18)
VTT 1.2V
SDVO Present

49-A321-B3

48-B3

48-B436-C2

49-B320-B4

MCH_P1.5V

1%

24.9

R128

H24

H25
AB29
AC29

A15

C16

A17
J18

751%

R117

R116

1% 75

B15
B16

4.99K

B17

R119

R113

1%

1% 75

E24
E23
E21

D21
C20

B20
A19
B19

H21

20-C4 48-B2

G21

48-B220-D4

J20

E25

27-C2

49-C4

F25

19-A349-C4

C23
C22

F23

49-C419-B4

F22

49-B3

19-A4

F26

19-C4

28-B3 13-B214-C3

C33

48-B3

C31

F28
F27

B30

19-B2

B29

19-B2

C25
C24

B34

19-C2

B33

19-C2

B32

19-B2

A34

19-C2

A33

19-C2

B31

19-B2

C29
D28
C27

C28
D27
C26

VTT

CLK3_BSEL1
CLK3_BSEL2

21-C3

D36

D34

E30

F34

EXP_RXN0

EXP_COMPI

EXP_ICOMPO

SDVOCTRL_DATA
SDVOCTRL_CLK
GCLKN
GCLKP

TVDAC_A

Pb

TVDAC_B

Y

TVDAC_C

Pr

TV_REFSET
TV_IRTNA
TV_IRTNB
TV_IRTNC

DDCCLK
DDCDATA
BLUE
BLUE*
GREEN
GREEN*
RED
RED*
VSYNC
HSYNC
REFSET

LBKLT_CRTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL

LACLKN
LACLKP
LBCLKN
LBCLKP

LADATAN0
LADATAN1
LADATAN2

LADATAP0
LADATAP1
LADATAP2

LBDATAN0
LBDATAN1
LBDATAN2

LBDATAP0
LBDATAP1
LBDATAP2

R115

4-A3

4-C3 6-C4

4-A3 6-C44-C3

G30

H34

J30

K34

EXP_RXN2

EXP_RXN3

EXP_RXN4

EXP_RXN1

MISCTVVGALVDS

G16

10K

CFG(17:3)
CFG(20:18)

DVO3_INT*

P34

L30

M34

N30

EXP_RXN9

EXP_RXN5

EXP_RXN6

EXP_RXN7

EXP_RXN8

CFG2

CFG3

CFG4

CFG0

CFG1

F16

F15

H13

G14

R114

2.21k
1%

Internal Pull-up
Internal Pull-down

U30

R30

T34

EXP_RXN10

EXP_RXN11

EXP_RXN12

CFG5

CFG6

CFG7

E16

D17

G15

R118

2.21k
1%

V34

W30

EXP_RXN13

CFG8

J16

D15

4

3

Rev.

No

21-C3

DVO3_INT

P36

U32

V36

W32

D30

Y34

EXP_RXP0

EXP_RXN14

EXP_RXN15

E34

F30

G34

EXP_RXP1

EXP_RXP2

H30

J34

K30

EXP_RXP4

EXP_RXP5

EXP_RXP3

L34

M30

N34

EXP_RXP6

EXP_RXP7

EXP_RXP8

P30

R34

T30

EXP_RXP9

EXP_RXP10

EXP_RXP11

U34

V30

W34

EXP_RXP12

EXP_RXP13

EXP_RXP14

EXP_RXP15

G32

E32

F36

EXP_TXN0

EXP_TXN1

H36

J32

K36

EXP_TXN2

EXP_TXN3

EXP_TXN4

L32

M36

N32

EXP_TXN5

EXP_TXN6

EXP_TXN7

R32

T36

EXP_TXN9

EXP_TXN8

EXP_TXN10

EXP_TXN13

EXP_TXN14

EXP_TXN11

EXP_TXN12

Y36

PCI-EXPRESS GRAPHICS

U514-2

915GM(DELL)

2 / 5

CFG/RSVD PM CLK NC

EXT_TS0*

EXT_TS1*

DREF_CLKN

DREF_CLKP

DREF_SSCLKN

CFG9

E15

CFG10

CFG11

D14

3

CFG12

E14

CFG13

H12

C14

CFG15

CFG16

CFG17

CFG18

CFG14

J15

H15

H14

G22

G23

MCH2_BMBUSY*

P2.5V

CFG19

CFG20

D23

RSVD21

G25

G24

10K
10K

RSVD22

RSVD23

J17

A31

16-C2 49-B3

RSVD24

RSVD25

A30

D26

R125
R124

RSVD26

RSVD27

D25

BM_BUSY*

J21

J23

THRMTRIP*

F5

H22

AD30

48-B3 16-B227-C330-B3

RSTIN*

PWROK

AE29

48-C3

A24

A23

C37

1%

R192

21-B3 16-B4 16-A2
24-B4

31-A4

DREF_SSCLKP

NC1

NC2

NC3

D37

AP37

AP36

AN37

4-A39-A1

9-A1 4-A3

4-B1
4-B1

100

24-C4

27-D2

49-B2

31-B4

AP2

2

J36

K32

L36

EXP_TXP4

EXP_TXP5

EXP_TXP6

NC10

NC11

A37

100nFC104
100nFC141
100nFC106
100nFC142

M32

N36

P32

EXP_TXP7

EXP_TXP8

EXP_TXP9

EXP_TXP10

DMIDDR MUXING

SM_OCDCOMP0
SM_OCDCOMP1

10V
10V
10V
10V

10V
10V
10V
10V

R36

T32

U36

V32

W36

EXP_TXP11

EXP_TXP12

EXP_TXP13

EXP_TXP14

EXP_TXP15

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP

DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP

DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP

DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

SM_CK0
SM_CK1
SM_CK2
SM_CK3
SM_CK4
SM_CK5

SM_CK0*
SM_CK1*
SM_CK2*
SM_CK3*
SM_CK4*
SM_CK5*

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

SM_CS0*
SM_CS1*
SM_CS2*
SM_CS3*

SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

SMRCOMPN
SMRCOMPP

SMVREF0
SMVREF1

SMXSLEWIN

SMXSLEWOUT

SMYSLEWIN

SMYSLEWOUT

AA31
Y31
AA33
Y33

AB35
AA35
AB37
AA37

AC31
AB31
AC33
AB33

AD35
AC35
AD37
AC37

AM33
AL1
AE11
AJ34
AF6
AC10

AN33
AK1
AE10
AJ33
AF5
AD10

AP21
AM21
AH21
AK21

AN16
AM14
AH15
AG16

AF22
AF16

AP14
AL15
AM11
AN10

AK10
AK11
AF37
AD1
AE27
AE28
AF9
AF10

21-B3
21-B3
21-B3
21-C3

21-C3
21-B3
21-B3
21-C3

16-C1
16-C1
16-C1
16-C136-B1 48-B4

16-C1
16-C1
16-C1
16-C1

13-C4
13-B4

13-C2
13-C2

13-C4
13-B4

13-C2
13-B2

13-B414-C3
13-B414-C3

14-C3 13-B2

13-C414-D3

13-C414-D3
14-C3 13-C2
14-C3 13-C2

14-C3 13-B4
14-C3 13-B4

13-B214-C3

13-B214-C3

MEM1_VREF

CLK1_DREFSSCLK

D32

E36

F32

EXP_TXP0

EXP_TXP1

EXP_TXP2

EXP_TXN15

NC4

NC5

NC6

NC7B1NC8A2NC9

AP1

AN1

CLK1_DREFSSCLK
CLK1_DREFSSCLK*
CLK1_DREFCLK
CLK1_DREFCLK*

PLT3_RST*

IMVP_PWRGD
GMCH1_THRMTRIP*

C103 100nF
C139 100nF
C105 100nF
C140 100nF

H32

G36

EXP_TXP3

A36

B37

2 1

DVO3_RED*
DVO3_GREEN*
DVO3_BLUE*
DVO3_CLK*

DVO3_RED
DVO3_GREEN
DVO3_BLUE
DVO3_CLK

DMI1_TXN0
DMI1_TXP0
DMI1_RXN0
DMI1_RXP0

DMI1_TXN1
DMI1_TXP1
DMI1_RXN1
DMI1_RXP1

CLK1_MCLK0
CLK1_MCLK1

CLK1_MCLK3
CLK1_MCLK4

CLK1_MCLK0*
CLK1_MCLK1*

CLK1_MCLK3*
CLK1_MCLK4*

MEM1_CKE0
MEM1_CKE1
MEM1_CKE2
MEM1_CKE3

MEM1_CS0*
MEM1_CS1*
MEM1_CS2*
MEM1_CS3*

P1.8V_AUX

MEM1_ODT0
MEM1_ODT1
MEM1_ODT2
MEM1_ODT3

4-A3 9-A2

1

Route as short as possible
1608

R190

R191

40.2

40.2
1%

1%

R189

80.6
1%

R218

80.6
1%

Place these close to SSCD.

9-A24-A3

R130
R129

0
0

CLK1_DOTCLK

4-B1

CLK1_DOTCLK*CLK1_DREFSSCLK*

4-B1

SAMSUNG

D

C

B

A

This Sheet of Engineering drawings and specifications contains Confidential,

Trade Secret and other Proprietary information of Dell Computer Corporation ( "Dell" ).

This document may not be transferred or copied without the express written authorization of Dell.

In addition, neither this sheet nor the information it contains may be used by or

disclosed to any third party without Dell’s express written consent.

This drawing is property of SEC, Use or copy of this drawing without proper permission

of the appropriate technical-document managing department is prohibited

4

Rev.

No

23

1

D

C

B

MEM1_ADQ(63:0)

13-D2 13-D4

MEM1_ABS0*
MEM1_ABS1*
MEM1_ABS2*

MEM1_ADM(7:0)

MEM1_ADQS(7:0)

MEM1_ADQS*(7:0)

MEM1_AMA(13:0)

MEM1_ACAS*
MEM1_ARAS*

MEM1_AWE*

14-C313-C4
14-C313-C4

13-C414-C3

13-B413-B2

13-B2 13-B4

13-A413-A2

14-D413-C4

13-B4 14-C3

14-C313-B4

14-C313-B4

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7
8
9
10
11
12
13

AK15
AK16
AL21

AJ37
AP35
AL29
AP24

AK36
AP33
AN29
AP23

AK35
AP34
AN30
AN23

AL17
AP17
AP18

AM17

AN18

AM18

AL19
AP20

AM19

AL20

AM16

AN20

AM20
AM15

AN15
AP16
AF29
AF28
AP15

AP9
AP4

AD3

AM8
AM4

AE5

AN8
AM5
AH1
AE4

AJ2

AJ1

2

1

0

3

AG35

AH35

AL37

AL35

SADQ0

SADQ1

SADQ3

SADQ2

SA_BS0*
SA_BS1*
SA_BS2*

SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

SA_DQS0*
SA_DQS1*
SA_DQS2*
SA_DQS3*
SA_DQS4*
SA_DQS5*
SA_DQS6*
SA_DQS7*

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13

SA_CAS*
SA_RAS*
SA_RCVENIN*
SA_RCVENOUT*
SA_WE*

8

5

976

4

10

AL34

AM36

AN35

AP32

AK37

AJ35

AH36

SADQ7

SADQ8

SADQ9

SADQ6

SADQ5

SADQ4

DDR SYSTEM MEMORY A

12

11

AM31

AM34

SADQ10

SADQ11

14

13

AM35

AL32

SADQ12

SADQ13

16

15

AM32

AN31

SADQ14

SADQ15

SADQ16

17

18

AP31

AN28

SADQ17

20

19

AP28

AL30

SADQ18

SADQ19

21

22

AM28

AM30

SADQ20

SADQ21

23

AL28

SADQ22

25

24

AP27

AM27

SADQ23

SADQ24

SADQ25

26

AM23

AM22

SADQ26

29

28

AL23

AM24

SADQ27

SADQ28

SADQ29

31

30

AP22

AN22

SADQ30

32

AM9

AL9

SADQ32

SADQ31

33

27

U514-3

915GM(DELL)

3 / 5

35

34

AL6

AP7

SADQ33

SADQ34

36

37

AP11

AP10

SADQ35

SADQ36

39

38

AL7

AM7

SADQ37

SADQ38

40

41

AN6

AN5

SADQ39

SADQ40

42

AN3

SADQ41

51

46

47

AL4

AM3

SADQ46

49

48

AK2

AK3

SADQ47

SADQ48

50

AG1

AG2

SADQ49

SADQ50

52

AL3

SADQ51

43

44

AP3

AP6

SADQ42

SADQ43

45

AM6

SADQ44

SADQ45

DDR SYSTEM MEMORY B

54

53

AM2

AH3

SADQ52

SADQ53

55

56

AG3

AF3

SADQ54

SADQ55

57

58

60

59

AF2

AE3

AD6

AC4

SADQ56

SADQ57

SADQ58

SADQ59

SB_RCVENIN*

SB_RCVENOUT*

61

63

62

AF1

AD4

AD5

SADQ61

SADQ62

SADQ60

SB_BS0*
SB_BS1*
SB_BS2*

SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7

SB_DQS0*
SB_DQS1*
SB_DQS2*
SB_DQS3*
SB_DQS4*
SB_DQS5*
SB_DQS6*
SB_DQS7*

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8

SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13

SB_CAS*
SB_RAS*

SB_WE*

SADQ63

AJ15
AG17
AG21

AF32
AK34
AK27
AK24
AJ10
AK5
AE7
AB7

AF34
AK32
AJ28
AK23
AM10
AH6
AF8
AB4

AF35
AK33
AK28
AJ23
AL10
AH7
AF7
AB5

AH17
AK17
AH18
AJ18
AK18
AJ19
AK19
AH19
AJ20
AH20
AJ16
AG18
AG20
AG15

AH14
AK14
AF15
AF14
AH16

10
11
12
13

0
1
2
3
4
5
6
7
8
9

14-C3 13-C2

13-C214-C3

14-C3 13-C2

14-B3 13-B2

14-B3 13-B2

13-C2
14-B4

13-B214-B3

MEM1_BBS0*
MEM1_BBS1*
MEM1_BBS2*

MEM1_BMA(13:0)

MEM1_BCAS*
MEM1_BRAS*

MEM1_BWE*

DDR/DDR2 Common Signal Mappping

Single Channel Mode Signal Mapping

Single Channel Signal Mapping.

SO-DIMM 0

SM_CK [1:0]

SM_CK* [1:0]

(DDR2 support)

SM_CS* [1:0]
SM_CKE [1:0]

SM_ODT [1:0]

SA_BS [2:0]

SA_DQ [63:0]
SA_DQS [7:0]

SA_DQS* [7:0]

SA_DM [7:0]

SO-DIMM 1

SM_CK [4:3]

SM_CK* [4:3]

(DDR2 support)

SM_CS* [3:2]
SM_CK [3:2]

SM_ODT [3:2]

(DDR2 support)(DDR2 support)

SB_BS [2:0]

SB_MA [13:0]SA_MA [13:0]

SB_RAS*SA_RAS*
SB_CAS*SA_CAS*

SB_WE*SA_WE*

D

C

B

SBDQ0

SBDQ6

SBDQ7

SBDQ8

AE31

SBDQ1

AE32

SBDQ2

AG32

SBDQ3

AG36

SBDQ4

AE33

AE34

SBDQ5

AF31

AF30

AH33

SBDQ9

AH32

SBDQ10

AK31

AG30

SBDQ11

SBDQ12

AG34

AG33

SBDQ13

SBDQ14

AJ31

AH31

SBDQ15

SBDQ16

AJ30

AK30

SBDQ17

SBDQ18

AH28

AH29

SBDQ20

SBDQ19

AK29

AH30

SBDQ21

SBDQ22

AH27

AG28

SBDQ23

SBDQ24

AF24

AG23

SBDQ25

SBDQ26

AJ22

AK22

SBDQ29

SBDQ27

SBDQ28

AH23

AH24

SBDQ30

AJ21

AG22

SBDQ31

SBDQ32

AG9

AG10

SBDQ33

SBDQ34

AH8

AG8

SBDQ35

SBDQ36

AH11

AH10

SBDQ37

SBDQ38

AJ9

AK9

SBDQ39

SBDQ40

AJ7

AK6

SBDQ41

SBDQ42

AJ4

AH5

SBDQ43

SBDQ44

AJ8

AK8

SBDQ45

SBDQ46

AJ5

AK4

SBDQ47

SBDQ48

AG5

AG4

SBDQ49

SBDQ50

AD8

AD9

SBDQ51

AH4

A

SBDQ52

SBDQ53

AE8

AG6

SBDQ54

SBDQ55

AD7

AC5

SBDQ56

SBDQ57

AB6

AB8

SBDQ58

SBDQ59

AA8

AC8

SBDQ60

SBDQ61

SBDQ62

AA4

AC7

SBDQ63

AA5

A

SAMSUNG

4

2

13

B523
BLM18PG181SN1

C229

100nF

VCCA_TVBG
VSSA_TVBG

VCCD_TVDAC

VCCDQ_TVDAC

VSSA_CRTDAC

VCC_SYNC

VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8

VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VTT33
VTT34
VTT35
VTT36
VTT37
VTT38
VTT39
VTT40
VTT41
VTT42
VTT43
VTT44
VTT45
VTT46
VTT47
VTT48
VTT49
VTT50
VTT51

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

VCCA_3GBG
VSSA_3GBG

2

C746
330uF

2.5V
AL

F17
E17
D18
C18
F18
E18
H18
G18
D19
H17

F19
E19
G19
H20

K13
J13
K12
W11
V11
U11
T11
R11
P11
N11
M11
L11
K11
W10
V10
U10
T10
R10
P10
N10
M10
K10
J10
Y9
W9
U9
R9
P9
N9
M9
L9
J9
N8
M8
N7
M7
N6
M6
A6
N5
M5
N4
M4
N3
M3
N2
M2
B2
V1
N1
M1
G1

AE37
W37
U37
R37
N37
L37
J37

F37
G37

Route VSSA_CRTDAC gnd from GMCH

P1.5V

to decoupling cap gnd lead and then
connect to the gnd plane.

B17

C96

100nF

From CRTDAC pin

max. 0.25"

VSSA_CRTDAC : Route caps within 250 mil of GMCH.

Route VSSA_CRTDAC gnd from GMCH to decoupling cap gnd
lead and then connect to the gnd plane

470nF

16V

C91

470nF

C645

16V

220nF

C180

16V

16V

220nF

C692

P2.5V

C138

100nF

P3.3V

BLM18PG181SN1

C92

2200nF
10V

max. 3"

Route FB within 3" of GMCH.

VTT

C182

C181

10000nF

2200nF

6.3V

10V

MCH_P1.5V

C193
10000nF

B14
BLM18PG181SN1

C93

100nF

B515
BLM18PG181SN1

C646

100nF

B18
BLM18PG181SN1

C99

100nF

P1.5V

C192
10000nF

1

P3.3V

B15

R597

C94

BLM18PG181SN1

100nF

P3.3V

P1.5V

C98

100nF

Place C17 closest to GMCH

P2.5V

R83

C100

100nF

BLM18PG181SN1

C728
330uF

2.5V
AL

B22

10

D505
MMBD301LT1

P3.3V

B16

BLM18PG181SN1

C95

100nF

P1.5V

VTT

10

MMBD301LT1
D11

SAMSUNG

P1.5V

13

13

This Sheet of Engineering drawings and specifications contains Confidential,

Trade Secret and other Proprietary information of Dell Computer Corporation ( "Dell" ).

This document may not be transferred or copied without the express written authorization of Dell.

In addition, neither this sheet nor the information it contains may be used by or

disclosed to any third party without Dell’s express written consent.

This drawing is property of SEC, Use or copy of this drawing without proper permission

of the appropriate technical-document managing department is prohibited

4

3

Rev.

No

100nF

100nF

100nF

P1.8V_AUX

C227

C254

AE12

AD11

AC11

VCCSM56

VCCSM57

VCCSM21

VCCSM22

AJ25

AH25

AG25

AB11

AB10

AB9

VCCSM58

VCCSM59

VCCSM60

VCCSM23

VCCSM24

VCCSM25

AF25

AE25

AE24

C255

AP8

AM1

VCCSM61

VCCSM62

VCCSM63

VCCSM27

VCCSM28

VCCSM26

AE23

AE22

AE1

AF20

VCCSM64

VCCSM29

VCCSM30

AE21

AE20

AE19

AP19

AF19

AF18

VCCA_SM0

VCCA_SM1

VCCA_SM2

VCCA_SM3

VCCSM31

VCCSM32

VCCSM33

VCCSM34

AE18

AE17

AE16

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCA_CRTDAC0
VCCA_CRTDAC1

VCCSM35

AE15

D

P1.8V_AUX

VTT

C230

C228

10000nF

10000nF

6.3V

6.3V

VTT

C187

C189

10000nF

6.3V

10000nF

6.3V

C184

10000nF

6.3V

C188

100nF

C183

100nF

C185

100nF

C186

100nF

C C

P1.5V

1

R166

P2.5V

C137

100nF

C190

4V

10000nF

C107

10nF
16V

P1.5V

B19

10uH

C649
470uF

4V
AL

B21

BLM18PG181SN1

C191

100nF

P2.5V

16V

P2.5V

C108

100nF

C134

100nF

C648
10000nF

C647

4700nF

6.3V

P1.5V

P1.5V

B20

10uH

C650
470uF

4V
AL

P1.5V

P1.5V

B

B24

C178

150uF

6V
AL

MMZ1608S121AT

B25

C179

100nF

150uF

C225

6V
AL

MMZ1608S121AT

C226

100nF

P1.5V

C101

C102

100nF

10000nF

A

C97

100nF

C135

100nF

M29

M28

G28

M27

W20

W18

AC2
AC1

AA1
AA2

T29
R29
N29

K29
V28

U28
T28
R28
P28
N28

K28
H28
V27

U27
T27
R27
P27
N27

K27
H27

K26
H26
K25

K24
K23
K22
K21

U20
T20
K20
V19
U19
K19

V18
T18
K18
K17

B23
C35

Y29
Y28
Y27

A35

J29

L28
J28

L27
J27

J25

B22
B21
A21

B26
B25
A25

B28
A28
A27

C257
C231
C256

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48

VCCH_MPLL1
VCCH_MPLL0
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL

VCCA_3GPLL0
VCCA_3GPLL1
VCCA_3GPLL2

VCCHV0
VCCHV1
VCCHV2

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2
VCCA_LVDS

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

100nF
100nF
100nF

AP13

AN13

AM13

AL13

AE14

VCCSM37

VCCSM38

VCCSM39

VCCSM40

VCCSM36

VCCSM5

VCCSM4

VCCSM3

VCCSM2

VCCSM0

VCCSM1

AP29

AC27

AD27

AD28

AH37

AM37

16V
16V

P1.8V_AUX

16V

AP12

AJ13

AH13

AG13

VCCSM42

VCCSM43

AF13

AE13

VCCSM46

VCCSM44

VCCSM45

AN12

VCCSM47

AK13

VCCSM41

U514-4

915GM(DELL)

VCCSM6

VCCSM7

VCCSM8

VCCSM9

VCCSM10

VCCSM11

VCCSM12

AJ26

AL26

AP26

AK26

AN26

AH26

AG26

AM26

AM12

AL12

VCCSM48

VCCSM49

VCCSM50

4 / 5

POWER

VCCSM13

VCCSM14

VCCSM15

AF26

AE26

AK12

AJ12

AH12

VCCSM51

VCCSM52

VCCSM17

VCCSM16

AP25

AN25

AM25

AG12

AF12

VCCSM53

VCCSM54

VCCSM55

VCCSM18

VCCSM19

VCCSM20

AL25

AK25

D

B

A

4

3

2

1

This Sheet of Engineering drawings and specifications contains Confidential,

Trade Secret and other Proprietary information of Dell Computer Corporation ( "Dell" ).

This document may not be transferred or copied without the express written authorization of Dell.

In addition, neither this sheet nor the information it contains may be used by or

disclosed to any third party without Dell’s express written consent.

This drawing is property of SEC, Use or copy of this drawing without proper permission

of the appropriate technical-document managing department is prohibited

4

Rev.

No

2

13

D

AG37

VSS0

Y37

VSS1

V37

VSS2

T37

VSS3

P37

VSS4

M37

VSS5

K37

VSS6

H37

VSS7

E37

VSS8

AN36

VSS9

AL36

VSS10

AJ36

VSS11

AF36

VSS12

AE36

VSS13

AD36

VSS14

AC36

VSS15

AB36

VSS16

AA36

VSS17

C36

VSS18

AE35

VSS19

Y35

VSS20

W35

VSS21

V35

VSS22

U35

C

B

R35
N35

M35

H35
G35

D35

AN34
AH34
AD34
AC34
AB34
AA34

C34

AL33
AF33
AD33

W33
U33
R33
N33

M33

H33
G33

D33

AN32

AJ32
AD32
AC32

VSS23

T35

VSS24
VSS25

P35

VSS26
VSS27
VSS28

L35

VSS29

K35

VSS30

J35

VSS31
VSS32
VSS33

F35

VSS34

E35

VSS35
VSS36

B35

VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48

V33

VSS49
VSS50

T33

VSS51
VSS52

P33

VSS53
VSS54
VSS55

L33

VSS56

K33

VSS57

J33

VSS58
VSS59
VSS60

F33

VSS61

E33

VSS62
VSS63
VSS64
VSS65
VSS66
VSS67

B36

VSSALVDS

VSS68

VSS69

Y32

AB32

AA32

D2

VSS270Y1VSS271

VSS70

VSS71

C32

A32

VSS72

VSS73

AL31

AL24

VSS267J2VSS268G2VSS269

VSS74

AG31

A26

AN24

VSS266

VTT

VSS75

W31

AD31

G26

E26

VSS264

VSS265

W13

V13
U13
T13
R13
P13
N13

M13

L13

W12

V12
U12
T12
R12
P12
N12

M12

L12

Y12

AA12

Y13

AA13

L14

M14

N14
P14
R14
T14
U14
V14

W14

Y14
AA14
AB14

L15

M15

N15

P15

R15

T15

VSS76

VSS77

V31

U31

J26

VSS263

VSS78

T31

L2

B27

VSS261

VSS262

VSS260

T2

V2

VSS258P2VSS259

AE2

AD2

VSS256

VSS257

AH2

VSS254

VSS255

AN2

AL2

VSS253

VSS252

U514-5

915GM(DELL)

5 / 5

VSS81

P31

VSS82

N31

VSS83

M31

L31

VSS84

VSS85

K31

VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8

VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
VSS_NCTF13
VSS_NCTF14
VSS_NCTF15
VSS_NCTF16
VSS_NCTF17
VSS_NCTF18
VSS_NCTF19
VSS_NCTF20
VSS_NCTF21
VSS_NCTF22
VSS_NCTF23
VSS_NCTF24
VSS_NCTF25
VSS_NCTF26
VSS_NCTF27
VSS_NCTF28
VSS_NCTF29
VSS_NCTF30
VSS_NCTF31
VSS_NCTF32
VSS_NCTF33
VSS_NCTF34
VSS_NCTF35
VSS_NCTF36

VSS_NCTF38
VSS_NCTF39
VSS_NCTF40
VSS_NCTF41
VSS_NCTF42
VSS_NCTF43
VSS_NCTF44
VSS_NCTF45
VSS_NCTF46

VSS86

VSS87

VSS88

VSS89

J31

F31

H31

G31

E31

VTT_NCTF0
VTT_NCTF1
VTT_NCTF2
VTT_NCTF3
VTT_NCTF4
VTT_NCTF5
VTT_NCTF6
VTT_NCTF7
VTT_NCTF8
VTT_NCTF9
VTT_NCTF10
VTT_NCTF11
VTT_NCTF12
VTT_NCTF13
VTT_NCTF14
VTT_NCTF15
VTT_NCTF16
VTT_NCTF17

VSS_NCTF68
VSS_NCTF67
VSS_NCTF66
VSS_NCTF65
VSS_NCTF64
VSS_NCTF63
VSS_NCTF62
VSS_NCTF61
VSS_NCTF60
VSS_NCTF59
VSS_NCTF58
VSS_NCTF57
VSS_NCTF56 VSS_NCTF37
VSS_NCTF55
VSS_NCTF54
VSS_NCTF53
VSS_NCTF52
VSS_NCTF51
VSS_NCTF50
VSS_NCTF49
VSS_NCTF48
VSS_NCTF47

VSS80

VSS79

R31

C3

VSS250A3VSS251

VSS90

VSS91

D31

AB3

AA3

VSS249

VSS92

AP30

AE30

AC3

VSS248

VSS247

AB26
AA26
Y26
AB25
AA25
Y25
AB24
AA24
Y24
AB23
AA23
Y23
AB22
AA22
Y22
AB21
AA21
Y21
R21
AB20
AA20
AB19
AA19
AB18
AA18
AB17
AA17
Y17
R17
AB16
AA16
Y16
W16
V16
U16
T16
R16
P16
N16
M16
L16
AB15
AA15
Y15
W15
V15
U15

VSS93

VSS94

AC30

AJ3

VSS246

VSS95

AB30

AA30

H4

VSS244C4VSS245

VSS96

VSS97

Y30

Y4

U4

VSS241P4VSS242L4VSS243

P1.8V_AUX

VTT

VSS98

VSS99

VSS100

C30

AJ29

AG29

AM29

AN4

AF4

VSS239

VSS240

VSS101

VSS102

AA29

AD29

VSS238

VSS103

VSS104

W29

W5

VSS236E5VSS237

VSS105

V29

T6

P6

J6

B6

AP5

AL5

VSS235

VSS106

U29

AA6

VSS229

VSS230L6VSS231

VSS232

VSS233

VSS234

AD26

VCCSM_NCTF0

AC26

VCCSM_NCTF1

AD25

VCCSM_NCTF2

AC25

VCCSM_NCTF3

AD24

VCCSM_NCTF4

AC24

VCCSM_NCTF5

AD23

VCCSM_NCTF6

AC23

VCCSM_NCTF7

AD22

VCCSM_NCTF8

AC22

VCCSM_NCTF9

AD21

VCCSM_NCTF10

AC21

VCCSM_NCTF11

AD20

VCCSM_NCTF12

AC20

VCCSM_NCTF13

AD19

VCCSM_NCTF14

AC19

VCCSM_NCTF15

AD18

VCCSM_NCTF16

AC18

VCCSM_NCTF17

AD17

VCCSM_NCTF18

AC17

VCCSM_NCTF19

AD16

VCCSM_NCTF20

AC16

VCCSM_NCTF21

AD15

VCCSM_NCTF22

AC15

VCCSM_NCTF23

AD14

VCCSM_NCTF24

AC14

VCCSM_NCTF25

AD13

VCCSM_NCTF26

AC13

VCCSM_NCTF27

AB13

VCCSM_NCTF28

AD12

VCCSM_NCTF29

AC12

VCCSM_NCTF30

AB12

VCCSM_NCTF31

L17

VCC_NCTF78

M17

VCC_NCTF77

N17

VCC_NCTF76

P17

VCC_NCTF75

T17

VCC_NCTF74

U17

VCC_NCTF73

V17

VCC_NCTF72

W17

VCC_NCTF71

L18

VCC_NCTF70

M18

VCC_NCTF69

N18

VCC_NCTF68

P18

VCC_NCTF67

R18 U21

VCC_NCTF66

Y18

VCC_NCTF65

L19

VCC_NCTF64

M19

VCC_NCTF63

N19

VCC_NCTF62

P19

VCC_NCTF61

R19

VCC_NCTF60

Y19

VCC_NCTF59

L20

VCC_NCTF58

M20

VCC_NCTF57

VSS110

VSS111

VSS112

VSS107

VSS108

VSS109

L29

F29

E29

P29

D29

H29

G29

AE6

AC6

VSS228

VSS227

VSS113

VSS114

A29

AC28

AJ6

VSS225

VSS226

VSS115

VSS116

AB28

AA28

AG7

AA7

V7

VSS221

VSS222

VSS223G7VSS224

VCC_NCTF0
VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8

VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56

VSS117

VSS118

VSS119

VSS120

E28

W28

AN27

AN7

AK7

VSS220

VSS121

AJ27

AL27

VSS219

VSS122

VSS123

AF27

AG27

L8

VSS216E8VSS217C8VSS218

W26
V26
U26
T26
R26
P26
N26
M26
L26
W25
V25
U25
T25
R25
P25
N25
M25
L25
W24
V24
U24
T24
R24
P24
N24
M24
L24
W23
V23
U23
T23
R23
P23
N23
M23
L23
W22
V22
U22
T22
R22
P22
N22
M22
L22
W21
V21

T21
P21
N21
M21
L21
Y20
R20
P20
N20

VSS124

VSS125

AB27

AA27

AL8

VSS126

VSS127

G27

W27

VSS213Y8VSS214P8VSS215

VSS128

VSS129

E27

K9

H9

VSS211A9VSS212

VSS130

AJ24

AG24

T9

VSS209

VSS210

VTT

VSS132

VSS131

J24

AA9

VSS133

F24

D24

AE9

AC9

VSS206

VSS207V9VSS208

VSS134

VSS135

B24

AH9

VSS204

VSS205

VSS203
VSS202
VSS201
VSS200
VSS199
VSS198
VSS197
VSS196
VSS195
VSS194
VSS193
VSS192
VSS191
VSS190
VSS189
VSS188
VSS187
VSS186
VSS185
VSS184
VSS183
VSS182
VSS181
VSS180
VSS179
VSS178
VSS177
VSS176
VSS175
VSS174
VSS173
VSS172
VSS171
VSS170
VSS169
VSS168
VSS167
VSS166
VSS165
VSS164
VSS163
VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS150
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136

AN9
D10
L10
Y10
AA10
F11
H11
Y11
AA11
AF11
AG11
AJ11
AL11
AN11
B12
D12
J12
A14
B14
F14
J14
K14
AG14
AJ14
AL14
AN14
C15
K15
A16
D16
H16
K16
AL16
C17
G17
AF17
AJ17
AN17
A18
B18
U18
AL18
C19
H19
J19
T19
W19
AG19
AN19
A20
D20
E20
F20
G20
V20
AK20
C21
F21
AF21
AN21
A22
D22
E22
J22
AH22
AL22
H23
AF23

D

C

B

A

A

SAMSUNG

4

3

2

1

This Sheet of Engineering drawings and specifications contains Confidential,

Trade Secret and other Proprietary information of Dell Computer Corporation ( "Dell" ).

This document may not be transferred or copied without the express written authorization of Dell.

In addition, neither this sheet nor the information it contains may be used by or

disclosed to any third party without Dell’s express written consent.

This drawing is property of SEC, Use or copy of this drawing without proper permission

of the appropriate technical-document managing department is prohibited

4

3

2

1

Rev.

No

D

C

B

A

MEM1_ADQ(63:0)

MEM1_AMA(13:0)

MEM1_ABS2*

MEM1_ABS0*
MEM1_ABS1*

MEM1_CS0*
MEM1_CS1*

CLK1_MCLK0

CLK1_MCLK0*

CLK1_MCLK1

CLK1_MCLK1*

MEM1_CKE0
MEM1_CKE1

MEM1_ACAS*
MEM1_ARAS*

MEM1_AWE*

CLK3_SMBCLK

CLK3_SMBDATA

MEM1_ODT0
MEM1_ODT1

MEM1_ADM(7:0)

MEM1_ADQS(7:0)

MEM1_ADQS*(7:0)

10-B4 14-D4

10-C4 14-C3

10-C4 14-C3

9-B1 14-D3
9-B1 14-D3

9-C1
9-C1
9-C1
9-C1
9-B1
9-B1 14-C3

10-B4 14-C3

10-B4 14-C3

R231
R230

48-C2
4-A4 13-B24-B4
4-A4 13-B24-B4

4-B3

49-C3
9-B1
9-B1 14-C3

13-D210-D4

0
1
2
3
4
5
6
7
8
9
10
11
12
13

14-C310-C4

14-C3

14-C310-B4

10K
10K

4-B3

14-C3

13-B210-C4

0
1
2
3
4
5
6
7

13-B210-C4

0
1
2
3
4
5
6
7

13-A210-C4

0
1
2
3
4
5
6
7

SMBUS ADDR " A0h"

DDR1-1
DDR2-SODIMM-200P-STD

1/2

102

A0

101

A1

100

A2

99

A3

98

A4

97

A5

94

A6

92

A7

93

A8

91

A9

105

A10_AP

90

A11

89

A12

116

A13

86

A14

84

A15

85

A16_BA2

107

BA0

106

BA1

110

S0*

115

S1*

30

CK0

32

CK0*

164

CK1

166

CK1*

79

CKE0

80

CKE1

113

CAS*

108

RAS*

109

WE*

198

SA0

200

SA1

197

SCL

195

SDA

114

ODT0

119

ODT1

10

DM0

26

DM1

52

DM2

67

DM3

130

DM4

147

DM5

170

DM6

185

DM7

13

DQS0

31

DQS1

51

DQS2

70

DQS3

131

DQS4

148

DQS5

169

DQS6

188

DQS7

11

DQS*0

29

DQS*1

49

DQS*2

68

DQS*3

129

DQS*4

146

DQS*5

167

DQS*6

186

DQS*7

DDR2 SO-DIMM #0
Bottom

P1.8V_AUX

DDR1-2
DDR2-SODIMM-200P-STD

112

C885

2200nF
10V

VDD1

111

VDD2

117

VDD3

96

VDD4

95

VDD5

118

VDD6

81

VDD7

82

VDD8

87

VDD9

103

VDD10

88

VDD11

104

VDD12

199

VDDSPD

83

NC1

120

NC2

50

NC3

69

NC4

163

NCTEST

1

VREF

201

GND0

202

GND1

47

VSS1

133

VSS2

183

VSS3

77

VSS4

12

VSS5

48

VSS6

184

VSS7

78

VSS8

71

VSS9

72

VSS10

121

VSS11

122

VSS12

196

VSS13

193

VSS14

8

VSS15

C869

2200nF
10V

CONTACT-PLATE-EMI

EMI4

EMI

0

5

DQ0

1

7

DQ1

2

17

DQ2

3

19

DQ3

4

4

DQ4

5

6

DQ5

6

14

DQ6

7

16

DQ7

8

23

DQ8

25

DQ9

10

35

DQ10

11

37

DQ11

12 13

20

DQ12

13

22

DQ13

14

36

DQ14

15

38

DQ15

16

43

DQ16

17

45

DQ17

18

55

DQ18

19

57

DQ19

20

44

DQ20

21

46

DQ21

22

56

DQ22

23

58

DQ23

24

61

DQ24

25

63

DQ25

26

73

DQ26

27

75

DQ27

28

62

DQ28

29

64

DQ29

30

74

DQ30

31

76

DQ31

32

123

DQ32

33

125

DQ33

34

135

DQ34

35

137

DQ35

36

124

DQ36

37

126

DQ37

38

134

DQ38

39

136

DQ39

40

141

DQ40

41

143

DQ41

42

151

DQ42

43

153

DQ43

44

140

DQ44

45

142

DQ45

46

152

DQ46

47 5

154

DQ47

48

157

DQ48

49

159

DQ49

50

173

DQ50

51

175

DQ51

52

158

DQ52

53

160

DQ53

54

174

DQ54

55

176

DQ55

56

179

DQ56

57

181

DQ57

58

189

DQ58

59

191

DQ59

60

180

DQ60

61

182

DQ61

62

192

DQ62

63

194

DQ63

9

P3.3V

C862

100nF
16V

MEM1_VREF

C890

100nF
16V

C861

2200nF
10V

C294

2200nF
10V

P1.8V_AUX

C282

2200nF
10V

VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57

18
24
41
53
42
54
59
65
60
66
127
139
128
145
165
171
172
177
187
178
190
9
21
33
155
34
132
144
156
168
2
3
15
27
39
149
161
28
40
138
150
162

C292

2200nF
10V

C280

2200nF
10V

P3.3V

MEM1_ADQ(63:0)

MEM1_BMA(13:0)

MEM1_BBS2*

MEM1_BBS0*
MEM1_BBS1*

MEM1_CS2*
MEM1_CS3*

CLK1_MCLK3

CLK1_MCLK3*

CLK1_MCLK4

CLK1_MCLK4*

MEM1_CKE2

MEM1_CKE3

MEM1_BCAS*
MEM1_BRAS*

MEM1_BWE*

CLK3_SMBCLK

CLK3_SMBDATA

MEM1_ODT2

MEM1_ODT3

MEM1_ADM(7:0)

MEM1_ADQS(7:0)

MEM1_ADQS*(7:0)

10-C4
13-B4

10-C4
13-B4

10-C4
13-A4

10-B2 14-B4

10-C2 14-C3

10-C2

9-C1
9-B1
9-C1
9-B1

10-B2 14-B3

R825

R824

9-B1 14-C3
9-B1 14-C3

13-D410-D4

0
1
2
3
4
5
6
7
8
9
10
11
12

14-C310-C2
14-C3

14-C39-B1
14-C39-B1

14-C39-B1
14-C39-B1

14-B310-B2

14-B310-B2

10K
10K

4-B3 4-B4 13-B44-A4 48-C2

49-C34-B3 4-B4 13-B44-A4

0
1
2
3
4

6
7

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7

SMBUS ADDR " A2h"

DDR2 SO-DIMM #1
Top

DDR500-1
DDR2-SODIMM-200P-RVS

1/2 2/22/2

102

A0

101

A1

100

A2

99

A3

98

A4

97

A5

94

A6

92

A7

93

A8

91

A9

105

A10_AP

90

A11

89

A12

116

A13

86

A14

84

A15

85

A16_BA2

107

BA0

106

BA1

110

S0*

115

S1*

30

CK0

32

CK0*

164

CK1

166

CK1*

79

CKE0

80

CKE1

113

CAS*

108

RAS*

109

WE*

198

SA0

200

SA1

197

SCL

195

SDA

114

ODT0

119

ODT1

10

DM0

26

DM1

52

DM2

67

DM3

130

DM4

147

DM5

170

DM6

185

DM7

13

DQS0

31

DQS1

51

DQS2

70

DQS3

131

DQS4

148

DQS5

169

DQS6

188

DQS7

11

DQS*0

29

DQS*1

49

DQS*2

68

DQS*3

129

DQS*4

146

DQS*5

167

DQS*6

186

DQS*7

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

D

P1.8V_AUX

DDR500-2
DDR2-SODIMM-200P-RVS

0

5

1

7

2

17

3

19

4

4

5

6

6

14

7

16

8

23

9

25

10

35

11

37

12

20

13

22

14

36

15

38

16

43

17

45

18

55

19

57

20

44

21

46

22

56

23

58

24

61

25

63

26

73

27

75

28

62

29

64

30

74

31

76

32

123

33

125

34

135

35

137

36

124

37

126

38

134

39

136

40

141

41

143

42

151

43

153

44

140

45

142

46

152

47

154

48

157

49

159

50

173

51

175

52

158

53

160

54

174

55

176

56

179

57

181

58

189

59

191

60

180

61

182

62

192

63

194

P3.3V

MEM1_VREF

C854

100nF
16V

C271

100nF

P1.8V_AUX

C855

2200nF
10V

C871

2200nF

C272

2200nF
10V

112
111
117

96
95

118

81
82
87

103

88

104
199

83

120

50
69

163

1

201
202

47
133
183

77

12

48
184

78

71

72
121
122
196
193

8

C879

2200nF
10V

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12

VDDSPD
NC1

NC2
NC3
NC4
NCTEST

VREF
GND0

GND1
VSS1

VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15

C881

2200nF
10V

VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57

C876

2200nF
10V10V

18
24
41
53
42
54
59
65
60
66
127
139
128
145
165
171
172
177
187
178
190
9
21
33
155
34
132
144
156
168
2
3
15
27
39
149
161
28
40
138
150
162

C873

2200nF
10V

C

B

A

SAMSUNG

4

3

2

1

This Sheet of Engineering drawings and specifications contains Confidential,

Trade Secret and other Proprietary information of Dell Computer Corporation ( "Dell" ).

This document may not be transferred or copied without the express written authorization of Dell.

In addition, neither this sheet nor the information it contains may be used by or

disclosed to any third party without Dell’s express written consent.

This drawing is property of SEC, Use or copy of this drawing without proper permission

of the appropriate technical-document managing department is prohibited

4

3

2

1

Rev.

No

D

MEM_0.9V

MEM1_AMA(13:0) MEM1_CS0*

C

MEM1_BMA(13:0)

B

10-B4
13-C4

10-B2
13-C2

0
1
2
3

4
5
6
7

8
9
10
11

12
13

0
1
2
3

4
5
6
7

8
9
10
11

12
13

RA503-2

RA5-2

RA506-1

RA5-1

RA506-2

RA6-2
RA509-1
RA509-2

RA6-1

RA7-2

RA4-1
RA511-1

RA7-1
RA500-2

RA515-2
RA507-2
RA516-1
RA507-1

RA516-2
RA508-2
RA517-1
RA517-2

RA508-1
RA510-2
RA505-1
RA518-1

RA510-1
RA513-1

34
34
12
12

34
34
12
34

12
34

2

1
12

12
34

34
34
12
12

34
34
12
34

12
34
12
12

12
12

56
56
56
56

56
56
56
56

56
56
56
56

56
56

56
56
56
56

56
56
56
56

56
56
56
56

56
56

MEM_0.9V

P1.8V_AUX

100nF 100nF

Array resistors & Single resistors used to improve layout & routing.

MEM_0.9V

12

MEM1_CS1*
MEM1_CS2*
MEM1_CS3*

MEM1_CKE0
MEM1_CKE1
MEM1_CKE2
MEM1_CKE3

MEM1_ODT0
MEM1_ODT1
MEM1_ODT2
MEM1_ODT3

MEM1_ABS0*
MEM1_ABS1*
MEM1_ABS2*

MEM1_ACAS*
MEM1_ARAS*

MEM1_AWE*

MEM1_BBS0*
MEM1_BBS1*
MEM1_BBS2*

MEM1_BCAS*
MEM1_BRAS*

MEM1_BWE*

13-C49-B1
13-C49-B1
13-C29-B1
13-C29-B1

13-B49-B1
13-B49-B1
13-B29-B1

9-B1 13-B2

13-B4

9-B1
9-B1 13-B4
9-B1 13-B2

13-B29-B1

10-C4 13-C4

13-C4

10-C4

13-C410-C4

13-B410-B4
10-B4 13-B4
10-B4 13-B4

13-C210-C2

13-C210-C2
10-C2 13-C2

10-B2 13-B2

13-B210-B2

13-B210-B2

RA501-1

RA2-1
RA514-1
RA502-1

RA8-1
RA511-2
RA512-1
RA518-2

RA500-1

RA2-2
RA513-2
RA502-2

RA4-2
RA503-1

RA8-2

RA3-2
RA501-2

RA3-1

RA505-2
RA515-1
RA512-2

RA504-2
RA514-2
RA504-1

12
12
12

12
34
12
34

12
34
34
34

4

3
12
34

34
34
12

4

3

2

1

4

3

34
34
12

56
56
56
56

56
56
56
56

56
56
56
56

56
56
56

56
56
56

56
56
56

56
56
56

P1.8V_AUX P1.8V_AUX

C874

C884C273

100nF

100nF 100nF

C287

C883C878

Place near GMCH

C847C850

100nF100nF

Place near SO-DIMM0

100nF100nF

C844

100nF

Place near SO-DIMM1

C835 C840

100nF

100nF

C842

VCCSM
DDR-II ::

P1.8V_AUX
VCCA_SM

P1.5V

VCCA_SM

VCCSM

Channel A

Alviso-GM

Memory Topology

( Single channel for DDR-II )

(TBD) "

(TBD) "

(TBD) "

(TBD) "

(TBD) "

(TBD) "

(TBD) "

(TBD) "

Address

CS
CKE

BS

CAS/RAS/WE

DQ(63:0)

CLK

CLK

P0.9V

P3.3V

P1.8V_AUX

DDR-II

Standard

Connector

Memory Channel A-1

P1.8V_AUX

P3.3V

DDR-II

Reverse

Connector

Memory Channel A-2

Bottom

Top

D

C

B

MEM_0.9V

C288

C872

C839

A

C843

100nF
16V

C852

100nF
16V

100nF
16V

C841

100nF 100nF
16V

C283

16V

C837

100nF
16V

C880

100nF
16V

C849

100nF
16V

C882

100nF
16V

C875

100nF
16V

C286

100nF
16V

C845

100nF
16V

C853

16V

C877

C836

100nF

100nF
16V16V

C846

100nF
16V

100nF

100nF100nF

16V16V

C848

100nF
16V

C870

100nF
16V

C285

100nF
16V

C281

100nF
16V

Place one cap close to every 2 pull-up resistors terminated to P0.9V

4

3

C291

100nF
16V 16V

C838

100nF

C851

100nF
16V

C290

100nF
16V

A

SAMSUNG

2

1

This Sheet of Engineering drawings and specifications contains Confidential,

Trade Secret and other Proprietary information of Dell Computer Corporation ( "Dell" ).

This document may not be transferred or copied without the express written authorization of Dell.

In addition, neither this sheet nor the information it contains may be used by or

disclosed to any third party without Dell’s express written consent.

This drawing is property of SEC, Use or copy of this drawing without proper permission

of the appropriate technical-document managing department is prohibited

D

VCC_RTC

C113

1000nF

R86

20K

1%

C114

1000nF

6.3V

R167

100K

CHP3_RTCRST*

15-C349-A4

For RTC reset

R640

32.768KHz

14

23

C603

0.01nF

Y500

C

AUD3_AC97_BCLK

26-C4 49-D2

R181

47

C208

0.027nF

AUD3_AC97_SYNC

MDC3_AC97_SYNC

AUD3_AC97_RST*

MDC3_AC97_RST*

AUD3_AC97_SDI0

MDC3_AC97_SDI1

AUD3_AC97_SDO

MDC3_AC97_SDO

49-D226-C4
33-C2
26-C4 49-D2
33-C2
26-C4 49-D2
33-C2

49-B326-C4
33-C2 49-A3

B

IDE3_IORDY

IDE3_IDEIRQ

IDE3_DACK*

IDE3_IOW*

IDE3_IOR*

48-B332-C1
18-C3 49-D432-C1

48-B332-C1

48-C332-C1

48-C3

32-C1

34

Rev.

No

10M

CHP3_INTRUDER*

C651

0.01nF

0.01nF

0.5pF

0.01nF

C163

C162

R641

CHP3_RTCRST*

0.01nF

0.01nF

0.5pF

0.5pF

C207

C206

0.5pF

0.01nF

C166

0

0.5pF

R156
R155
R180
R182

R158
R157

0.01nF

C165

0.5pF

VCC_RTC

49-A415-C4

49-D231-C2

33 1%
33 1%
33 1%
33

33 1%
33 1%

U515-1
82801FBM(DELL)

R84

680K

1 / 5

1%

Y1

RTCX1

Y2

RTCX2

AA2

RTCRST*

AA3

INTRUDER*

AA5

INTVRMEN

D12

EE_CS

B12

EE_SHCLK

D11

EE_DOUT

F13

EE_DIN

F12

LAN_CLK

B11

LAN_RSTSYNC

E12

LANRXD0

E11

LANRXD1

C13

LANRXD2

C12

LANTXD0

C11

LANTXD1

E13

LANTXD2

C10

ACZ_BIT_CLK

B9

ACZ_SYNC

A10

ACZ_RST*

1%

F11

ACZ_SDIN0

F10

ACZ_SDIN1

B10

ACZ_SDIN2

C9

ACZ_SDO

AC19

SATALED*

AE3

SATA0RXN

AD3

SATA0RXP

AG2

SATA0TXN

AF2

SATA0TXP

AD7

SATA2RXN

AC7

SATA2RXP

AF6

SATA2TXN

AG6

SATA2TXP

AC2

SATA_CLKN

AC1

SATA_CLKP

AG11

SATARBIAS*

AF11

SATARBIAS

AF16

IORDY

AB16

IDEIRQ

AB15

DDACK*

AC14

DIOW*

AE16

DIOR*

LAD0_FWH0
LAD1_FWH1
LAD2_FWH2
LAD3_FWH3

RTC

LPCCPUIDE

LDRQ1*_GPI41

LFRAME*_FWH4

LANAZALIA

DPRSLP*_TP4

DPSLP*_TP2

CPUPWRGD_GPO49

THRMTRIP*

SATA

LDRQ0*

A20GATE

A20M*

CPUSLP*

FERR*

IGNNE*

INIT3_3V*

INIT*
INTR

RCIN*

NMI

SMI*

STPCLK*

DA0
DA1
DA2

DCS1*
DCS3*

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8

DD9
DD10
DD11
DD12
DD13
DD14
DD15

DDREQ

2

1

CPUSLP*
Dothan A stepping : Stuff resistor on SLP* of ICH6-M

Dothan B stepping ~ : Stuff resistor on SLP of GMCH.

D

DPRSTP*
Dothan : No stuff

Yonah : Stuff

P2
N3
N5
N4

N6
P4

P3

AF22
AF23

AE27
AE24

AD27
AF24
AG25
AG26

AE22
AF27
AG24

AD23
AF25

AG27
AE26
AE23
AC16

AB17
AC17

AD16
AE17

AD14
AF15
AF14
AD12
AE14
AC11
AD11
AB11
AE13
AF13
AB12
AB13
AC13
AE15
AG15
AD13

AB14

10
11
12
13
14
15

R195
R193

0
1
2
3
4
5
6
7
8
9

27-C2

0
1
2
3

48-C2 28-A2
48-C2 27-C2

27-C249-B3 24-B4

48-C3 28-B2

0
0

49-D3 6-C3

48-B4

48-C4 32-C1
48-C4 32-C1
48-C4 32-C2

48-D3 32-C1
48-D3 32-C2

48-C3
48-D3

48-C3 32-C1

LPC3_LAD(3:0)

24-C4
49-B4

CHP3_LDRQ0*
CHP3_LDRQ1*

LPC3_LFRAME*

KBC3_A20G

CPU1_A20M*

5-C348-C3

CPU1_SLP*

6-C3

8-A2

48-C4

CPU1_DPRSTP*

6-C349-C3

CPU1_DPSLP*

12

RA1-1

CPU1_PWRGDCPU

6-C4

CPU1_IGNNE*

5-B349-D3

CPU1_INIT*

5-C348-B3

CPU1_INTR

5-B348-C4

KBC3_ICH6RCIN*

27-B349-C2

CPU1_NMI

5-B3

CPU1_SMI*

5-B348-C4

CPU1_STPCLK*

5-B349-C3

IDE3_A0
IDE3_A1
IDE3_A2

IDE3_CS1*
IDE3_CS3*
IDE3_D(15:0)

32-D2
48-B3

IDE3_DREQ

VTT

3

RA1-2

56

4

56

CPU1_FERR*

5-B348-B3

VTT

R194

47

Place 56 ohm resistor within 2" of ICH6-M
Place PU resistor within 2" of ICH6-M

C

B

A

A

SAMSUNG

4

3

2

1