DELL D400 Schematics

Insert AC adapter only,

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then without press power

button

DP1 (Pebble) Power Sequence

PS_ID

PS_ID is to confirm that insertion of

AC adapter 65W or 90W

Power Plan:

0. RTC power plane.

1. Always power plane.

2. SUS power plane.

3. RUN power plane.

ACPI Power State:

1. S0: System Full On, All power planes are ON.

2. S3: Suspend to RAM, RUN power off.

3. S4: Suspend to Disk, RTC and Always power
ON.(AC)

4. S5: Soft Off, power state like S4.

PWR_SRC

+RTCSRC is generated by

PWR_SRC

through D40

+RTCSRC

U9 U13

Pin 1 Pin 1

+RTCSRC will be input of MAXIM 1615,

then +RTC_PWR is the output of

MAXIM 1615

Pin 3

+RTC_PWR

With either LIVE_ON_BATT or

ACAV_IN existed, +RTC_PWR can

convert to +5VALW through Q61

+5VALW

X7 XTAL 32.768K will

oscillate after
+3.3VRTC comes up
high & U37.2 should
driven high after
+3VALW comes up.

If no ALW power, what
should we do?
A: Check all ACAV_IN
relate circuit.

+RTCSRC will be input of MAXIM 1615,

then +3.3VRTC is the output of MAXIM

1615

Pin 3

+3.3VRTC

With either LIVE_ON_BATT or

ACAV_IN existed, +3.3VRTC can

convert to +3VALW through Q62

+3VALW

Macallen

32 K Hz

Go!

If Macallen is working.

Q: If no debug out pulse?

1. Macallen.

2. BIOS ROM.

CN8 pin2 will have 1,2,3,4
pulse when AC adapter
attached( DEBUG_OUT )

Insert AC adapter only, then

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press power

button

POWER_SW#

DP1 (Pebble) Power Sequence

AUX_EN from

Macallen

After +3VALW , +5VALW,

DEBUG_OUT were all come out.

Macallen should assert SUS_ON.

SUS_ON

SUS_ON and AUX_EN were initial

trigger for MAX1632. It will result in

producing +5VSUS , +3VSRC and

DC_12CV.

+5VSUS

+5VSUS was initial

trigger for SC1486. It

will produce

+2.5VSUS

+3VSRC

Q17

+3VSUS

If Macallen do not driven SUS_ON high

1. Re-heat Macallen.

2. Change one new Macallen.

3. Still no SUS_ON, check BIOS ROM.

DC_12V

Q60

With

RUNPWROK

asserts

+12V

+2.5VSUS

Check All SUS power planes
are in correct voltage level?

SUS_ON

2.5V_PWRGD

+3VSUS was initial

trigger for MAX1644. It

will produce +1.5VSUS.

+1.5VSUS

1632_3VOK

If these three signal

driven high, then through

U74 ( AND gate ) will

produce SUSPWROK

SUSPWROK

If SUSPWROK is OK, it will

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drive to ICH4

SUSPWROK

When initialized ICH4, drives

SLP_S3# which causes Macallen to

drive RUN_ON.

RUN_ON

After approximate 10ms soft

start delay, RUN power

switches are turned on and

connecting RUN planes with

SUS planes

DP1 (Pebble) Power Sequence

+5VSUS

+5VSUS was initial

trigger for

TPS793475.It will

produce +5VA

+5VA

4.75V for audio circuit.

SUS POWER PLANES

+3VSUS

+3VSUS was initial

trigger for MAX1792.It

will produce +1.8VRUN

+1.8VRUN

Make sure all RUN power
planes are in correct voltage
level.

RUN POWER PLANES

+5VSUS+5VRUN

Q55

Delay 10ms

+3VSRC

+1.5VSUS

+5VRUN

Q18

Q69

+5VRUN was initial

trigger for SC1486.It

will produce
+1.25VRUN

+3VRUN

+1.5VRUN

+1.25VRUN

1.25V_PWRGD

If these three signal

assert, then through

U20 ( AND gate ) will

produce RUNPWROK

RUNPWROK

10ms after +5VRUN power

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plane comes up

RUNPWROK

DP1 (Pebble) Power Sequence

RUNPWROK was initial trigger

for MAX1715. It will produce

+1.2VRUN and VCC_IO

+1.2VRUN

After +1.2VRUN and

VCC_IO came out.

MAX1715 will produce

1715PWROK

1715PWROK

When Macallen is ready to

VCC_IO

release the Banias, it will

drive RESET_OUT#

RESET_OUT#

RUNPWROK was initial trigger

for SC1476. It will produce

VCC_CORE

If no Vcore:

1. Check high/low side MOSFET.

2. Check U67 SC1476

VCC_CORE

After VCC_CORE came

out. SC1476 will

produce

VCORE_PWRGD

VCORE_PWRGD

10ms after VCC_CORE

and VCC_IO are within

regulation.

VCORE_PWRGD is driven

to ICH4 ( VGATE )

Delay 10ms

DELAY_IMVP_PWRGD

DELAY_IMVP_PWRGD is driven

to ICH4 as PWROK allowing

release of the Banias from INIT

and deassertion of PCIRST#

VCORE_PWRGD_D

VGATE

If CPU power is OK and CPURST# de-assertion.

1. CPU: re-heat, change one new.

2. Change BIOS ROM.

CK408_IMVP_PWRGD

( TO CLOCK GEN )

All clocks

Next step should check:

1. PCIRST#

2. CPURST#

3. GTL_ADS#