Dell B120, B130, 1300 Schematics
A
Key West Block Diagram
CLK GEN
3
ICS954226AG
4 4
SB
3 3
Mini-PCI
25
B
4,5
Mobile CPU
Celeron/Dothan
Host BUS
400MHz
6,7,8,9,10
Alviso
GML
DMI I/F
100MHz
C
Project code: 91.4D901.001
PCB P/N : 48.4D901.0SD
REVISION : 05209-SD
DDRII*2
400MHz
11,12
LVDS
D
13
LCD
E
SYSTEM DC/DC
33
34,35
MAX8734A
INPUTS
DCBATOUT
SB
SYSTEM DC/DC
TPS5130
INPUTS
DCBATOUT
OUTPUTS
5V_S3
3V_S3
OUTPUTS
1D05V_S0
1D2V_S0
1D8V_S3
MAXIM CHARGER
RGB CRT
CRT
31
14
INPUTS
DCBATOUT
MAX1909
OUTPUTS
BT+
18V 4.0A
5V 100mA
802.11a/b/g
15,16,17,18
22
RJ45
CONN
22
RJ11
CONN
2 2
LINE OUT
10/100 BCM4401
MODEM
MDC 1.5 Card
24
OP AMP
21
PCI BUS
26
24
SB
AZALIA
ICH6-M
MAX4411
USB 2.0
P IDE
PCI EXPRESS / USB 2.0
LPC Bus
Power
Switch
MASTER
SLAVE
20
USB x 3
HDD
DVD/
CD-RW
PCI EXPRESS
CARD
26
20
20
20
TPS2231
23
KBC
H8S/RE144AV
27
FlashRom
4Mb
(512kB)
29
MIC IN
AC'97 CODEC
24
STAC9200
CPU DC/DC
32
MAX1907
INPUTS
OUTPUTS
VCC_CORE
DCBATOUT
0.844~1.3V
27A
PCB LAYER
Signal 1
L1:
GND
L2:
Signal 2
L3:
Signal 3
L4:
VCC
L5:
Signal 4
L6:
SC
1 1
OP AMP
TPA6017
24
SB
28
Touch
Pad
Int.
KB
28
SMBus
Thermal Sensor
& Fan
ENC 6N300
SB
2CH SPEAKER
A
B
C
D
19
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
Block Diagram
Block Diagram
Block Diagram
KeyWest
KeyWest
KeyWest
E
SD
SD
137Tuesday, August 16, 2005
137Tuesday, August 16, 2005
137Tuesday, August 16, 2005
of
of
of
SD
A
B
C
D
E
ICH6-M Integrated Pull-up
and Pull-down Resistors
ACZ_BIT_CLK,
EE_DOUT, EE_CS, GNT[5]#/GPO[17],
GNT[6]#/GPO[16],
4 4
LAD[3:0]#/FB[3:0]#, LDRQ[0],
PME#, PWRBTN#,
LAN_RXD[2:0]
ACZ_RST#, ACZ_SDIN[2:0], ACZ_SYNC,
ACZ_SDOUT,ACZ_BITCLK,
SPKR
USB[7:0][P,N]
DD[7],
LAN_CLK
3 3
ICH6-M IDE Integrated Series
DPRSLP#, EE_DIN,
TP[3]
SDDREQ
LDRQ[1]/GPI[41],
DPRSLPVR,
ICH6 internal 20K pull-ups
ICH6 internal 10K pull-ups
ICH6 internal 20K pull-downs
ICH6 internal 15K pull-downs
ICH6 internal 11.5K pull-downs
ICH6 internal 100K pull-downs
ICH6-M EDS 14308 0.8V1
Termination Resistors
DD[15:0],
DDACK#,
DCS3#,
IORDY,
IDEIRQ
DIOR#, DREQ,DIOW#,
DA[2:0],
DCS1#,
approximately 33 ohm
Power name description
5V_S0= 5 Voltage power up on system work(S0 state)
5V_S3= 5 Voltage suspend to RAM(S3 state)
5V_S5= 5 Voltage soft off(S5 state)
3D3V_S0= 3.3 Voltage power up on system work(S0 state)
3D3V_S3= 3.3 Voltage suspend to RAM(S3 state)
3D3V_S5= 3.3 Voltage soft off(S5 state)
LVDDR_2D5V= 2.5 Voltage power up on system work(S0 state)
1D8V_S3= 1.8 Voltage suspend to RAM(S3 state)
2D5V_S0= 2.5 Voltage power up on system work(S0 state)
VCC_CORE_S0= CPU VID Voltage power up on system work(S0 state)
1D5V_VCCA_S0= 1.5 Voltage power up on system work(S0 state)
1D5V_S0= 1.5 Voltage power up on system work(S0 state)
1D5V_S5= 1.5 Voltage soft off(S5 state)
DDR_VREF_S3= 0.9 Voltage suspend to RAM(S3 state)
0D9V_S0= 0.9 Voltage power up on system work(S0 state)
1D2_VGA_S0= 1.2 Voltage power up on system work(S0 state) for VGA
1D05V_S0= 1.05 Voltage power up on system work(S0 state)
CORE_GMCH_S0= 1.05 Voltage power up on system work(S0 state) for ALVISO core power
VCCP_GMCH_S0= 1.05 Voltage power up on system work(S0 state)for ALVISO BUSIO power
1D05V_S010,34,35,36,37
VCCP_GMCH_S04,5,6,7,9,10,15,17,19,32,37
CORE_GMCH_S06,9,10,37
0D9V_S012,35,36
DDR_VREF_S37,11,35
1D5V_S05,7,9,16,17,20,36,37
1D5V_S317,34,35,36
1D5V_VCCA_S05
VCC_CORE_S05,32,36
1D8V_S37,9,10,11,12,16,34,35,36,37
2D5V_S07,9,14,17,34,36
2D5V_CRTDAC_S09
3D3V_LCD_S013
3D3V_S03,4,5,7,9,11,13,15,16,17,18,19,20,23,24,25,27,29,32,34,36,37
3D3V_S316,17,18,19,20,25,26,33,37
3D3V_S54,13,16,19,27,28,29,30,31,32,33,34,35,36
3D3V_LAN_S521,22,36,37
+3V_SRC33,36
+3D3VRTC15,19,28,33,36
RTC_AUX_S515,17
VDDA23
5V_S013,14,17,18,19,20,24,25,27,28,32,35,36,37
5V_S313,17,19,23,24,26,33,34,35,36,37
5V_S513,32,33,34,36
5V_CRT_S014
+15V13,19,33,36,37
DCBATOUT13,31,33,34,35,36,37
BT+30,31,37
AD+30,31,37
1D05V_S0
VCCP_GMCH_S0
CORE_GMCH_S0
0D9V_S0
DDR_VREF_S3
1D5V_S0
1D5V_S3
1D5V_VCCA_S0
VCC_CORE_S0
1D8V_S3
2D5V_S0
2D5V_CRTDAC_S0
3D3V_LCD_S0
3D3V_S0
3D3V_S3
3D3V_S5
3D3V_LAN_S5
+3V_SRC
+3D3VRTC
RTC_AUX_S5
VDDA
5V_S0
5V_S3
5V_S5
5V_CRT_S0
+15V
DCBATOUT
BT+
AD+
SB
XDP_BPM#54
XDP_PRDY#4
XDP_BPM#34
XDP_BPM#24
XDP_BPM#14
XDP_BPM#04
DBR#4,16
VCCP_GMCH_S0
XDP_TDI_FELX
XDP_TMS_FELX
XDP_TRST#_FELX
XDP_TCK_FELX
XDP_TDO_FELX
ITP_CPU#
ITP_CPU
CPURST_FLEX#
12
C4
C4
DY
DY
TP116 TPAD30TP116 TPAD30
TP118 TPAD30TP118 TPAD30
TP117 TPAD30TP117 TPAD30
TP119 TPAD30TP119 TPAD30
TP120 TPAD30TP120 TPAD30
TP122 TPAD30TP122 TPAD30
TP121 TPAD30TP121 TPAD30
TP123 TPAD30TP123 TPAD30
TP124 TPAD30TP124 TPAD30
TP125 TPAD30TP125 TPAD30
TP126 TPAD30TP126 TPAD30
TP127 TPAD30TP127 TPAD30
TP128 TPAD30TP128 TPAD30
TP129 TPAD30TP129 TPAD30
TP130 TPAD30TP130 TPAD30
TP131 TPAD30TP131 TPAD30
SB
Clock Gen.
DDR Module 1
DDR Module 2
LCD
Guardian
Battery
EEPROM
SMBus addr.Device
D2
A0
A4
58
5E
16
A2
USB Port Key West Define
USBP[0]
USBP[1]
USBP[2]
USBP[3]
USBP[4]
USBP[5]
USBP[6]
USBP[7]
USB1 Up connector
New card used
USB1 Down connector
NC
USB2 connector
NC
NC
NC
PCIE Port Key West Define
PE[1]
PE[2]
PE[3]
PE[4]
NC
NC
NC
New card used
R9 0R2J-GP
R9 0R2J-GP
2 2
1 1
XDP_TDI4
XDP_TMS4
XDP_TRST#4
XDP_TCK4
XDP_TDO4
CLK_XDP_CPU#3,4
CLK_XDP_CPU3,4
H_CPURST#4,6
1 2
DY
DY
R10 0R2J-GP
R10 0R2J-GP
1 2
DY
DY
R11 0R2J-GP
R11 0R2J-GP
1 2
DY
DY
R265 0R2J-GP
R265 0R2J-GP
1 2
DY
DY
R12 22D6R2F-L1-GP
R12 22D6R2F-L1-GP
1 2
DY
DY
R14 0R2J-GP
R14 0R2J-GP
1 2
DY
DY
R15 0R2J-GP
R15 0R2J-GP
1 2
DY
DY
R13 22D6R2F-L1-GP
R13 22D6R2F-L1-GP
1 2
DY
DY
SB
SB
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
A
B
C
D
PCI RESOURCE TABLE
DEVICE IDSEL
Mini-PCI
LAN
AD19
AD16
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet of
PCI IRQ
P_INTB# / P_INTD#
P_INTC#
ITP
ITP
ITP
KeyWest
KeyWest
KeyWest
REQ# / GNT#
REQ3#/GNT3#
REQ4#/GNT4#
SB
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
237Tuesday, August 16, 2005
237Tuesday, August 16, 2005
237Tuesday, August 16, 2005
of
E
of
SD
SD
SD
A
L9
L9
1 2
MLB-201209-21-GP
MLB-201209-21-GP
4 4
3D3V_S0
12
L23
L23
1 2
MLB-201209-21-GP
MLB-201209-21-GP
C651
C651
SCD1U16V
SCD1U16V
12
3D3V_APWR_S0
12
C344
C344
SC10U10V6ZY-U
SC10U10V6ZY-U
C162
C162
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
3D3V_CLKGEN_S0
12
C349
C349
SCD1U16V
SCD1U16V
12
12
C350
C350
SCD1U16V
SCD1U16V
C348
C348
SCD1U16V
SCD1U16V
SB
SB
SD
R432 33R2J-2-GPR432 33R2J-2-GP
PCLK_FWH29
PCLK_LAN21
PCLK_MINI25
PCLK_KBC27
CLK_ICHPCI16
PM_STPPCI#16
3 3
X5 CL=20pF±0.2pF
Freq. Tolerance:±30ppm
C356
C356
1 2
SC33P50V2JN
SC33P50V2JN
C357
C357
1 2
SC27P50V2JN-L-GP
SC27P50V2JN-L-GP
SB
2 2
X5
X5
X-14D31818M-33GP
X-14D31818M-33GP
1 2
SD
SC
CLK_XIN
12
X7
X7
XTAL-14D318M
XTAL-14D318M
CLK_XOUT
DY
DY
Place X7 and X5 co-layout
SC
SMBC_ICH11,18
SMBD_ICH11,18
DREFCLK7
DREFCLK#7
CLK_ICH1416
SB
CLK_PWRGD#32
X7 CL=20pF
Freq. Tolerance:±20ppm
1 2
R133 33R2J-2-GPR133 33R2J-2-GP
1 2
R134 33R2J-2-GPR134 33R2J-2-GP
1 2
R417 22R2J-2-GPR417 22R2J-2-GP
1 2
R135 33R2J-2-GPR135 33R2J-2-GP
1 2
R120 33R2J-2-GPR120 33R2J-2-GP
1 2
R121 33R2J-2-GPR121 33R2J-2-GP
1 2
SC
R433 33R2J-2-GPR433 33R2J-2-GP
1 2
1 2
R122 475R2F-L1-GPR122 475R2F-L1-GP
NEAR CLKGEN
3D3V_CLKGEN_S0
0
0
1
1
0
0
1
1
FS_A
CPU
FS_A
266M
0
133M
01200M
166M
1
00333M
1
0
400M
1 Reserved
1 2
R118 10KR2J-2-GPR118 10KR2J-2-GP
1 1
FS_B
FS_C
0
0
0
1
1 100M
1
1
A
3D3V_S0
12
CLK_XIN
CLK_XOUT
B
3D3V_S03D3V_S0
12
R580
R580
10KR2J-2-GP
10KR2J-2-GP
DY
DY
CLK_PCI3
CLK_PCI4
CLK_PCI5
SS_SEL
ITP_EN
DOT96T
DOT96C
CLK_REF14
CLK_IREF
R119
R119
1 2
4D7R3J-L1-GP
4D7R3J-L1-GP
C354
C354
SCD1U16V
SCD1U16V
56
3
4
5
9
8
55
46
47
14
15
50
49
52
39
10
2
6
51
45
38
13
29
3D3V_48MPWR_S0
12
C160
C160
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
12
C355
C355
SCD1U16V
SCD1U16V
U62
U62
PCI0
PCI1
PCI2
PCI3
PCIF1/SEL100/96#
PCIF0/ITP_EN
PCI_STOP#
SCL
SDA
DOT96
DOT96#
XTAL_IN
XTAL_OUT
REF
IREF
VTT_PWRGD#/PD
VSS_PCI
VSS_PCI
VSS_REF
VSS_CPU
VSSA
VSS48
VSS_SRC
12
C161
C161
SCD1U16V
SCD1U16V
12
C351
C351
SCD1U16V
SCD1U16V
LVDS
LVDS#
SRC1
SRC1#
SRC2
SRC2#
SRC3
SRC3#
SRC4
SRC4#
SRC5
SRC5#
SRC6
SRC6#
CPU2_ITP/SRC7
CPU2_ITP#/SRC7#
CPU0
CPU0#
CPU1
CPU1#
CPU_STOP#
FSC/TEST_SEL
FSB/TEST_MODE
USB48/FSA
VDD_SRC
VDD_SRC
VDD_PCI
VDD_PCI
VDD_REF
VDD_CPU
VDDA
VDD48
VDD_SRC
ICS954226AGLFTGP
ICS954226AGLFTGP
71.95422.00W
71.95422.00W
17
18
19
20
22
23
24
25
26
27
31
30
33
32
36
35
44
43
41
40
54
53
16
12
34
21
7
1
48
42
37
11
28
SB
1st source: 71.95422.00W (ICS954226AGLFTGP)
2nd source: 71.00140.00W (IDTCV140PAG-GP)
3rd source: 71.28442.00W (CY28442ZXC-2T-GP)
B
12
C
C343
C343
SCD1U16V
SCD1U16V
CLK_SRCT0
CLK_SRCC0
CLK_SRCT1
CLK_SRCC1
CLK_SRCT3
CLK_SRCC3
CLK_SRCT5
CLK_SRCC5
CLK_SRCT6
CLK_CPUT1
CLK_CPUC1
CLK_CPUT2
CLK_CPUC2
CLK_CPUC0
CLK_CPUT0
FS_C
FS_A
C
3D3V_S0
12
C358
C358
SCD1U16V
SCD1U16V
RN42
RN42
2 3
1
SRN33J-5-GP-U
SRN33J-5-GP-U
RN43
RN43
2 3
1
4
SRN33J-5-GP-U
SRN33J-5-GP-U
RN41
RN41
2 3
1
4
SRN33J-5-GP-U
SRN33J-5-GP-U
RN44
RN44
1
4
2 3
1
2 3
SRN33J-5-GP-U
SRN33J-5-GP-U
R137 2K2R2J-2-GPR137 2K2R2J-2-GP
1 2
R424 22R2J-2-GPR424 22R2J-2-GP
1 2
3D3V_CLKGEN_S0
3D3V_APWR_S0
3D3V_48MPWR_S0
DY
DY
SRN33J-5-GP-U
SRN33J-5-GP-U
RN46
RN46
4
RN40
RN40
2 3
1
RN45
RN45
1
2 3
SRN33J-5-GP-U
SRN33J-5-GP-U
ICS954226AG Spread
Spectrum Select
S3 S2 S1 S0 Spread Amount%
000
0000
0
0
0
1
0
1
0
1
0
11
0
0
1 +/-0.3
00
1
001
1
0
1
1
1
1
1
11
1
11
0
1
0
1
1
1
0
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
12
R123
R123
10KR2J-2-GP
10KR2J-2-GP
ITP_EN
12
R136
R136
10KR2J-2-GP
10KR2J-2-GP
DY
DY
4
4
SRN33J-5-GP-U
SRN33J-5-GP-U
SBSB
4
CPU_SEL0 4,7
CPU_SEL1 4,7
CLK48_USB 16
-0.8
-1.0
-1.25
-1.5
-1.75
-2.0
-2.5
-3.0
+/-0.4
+/-0.5
+/-0.6
+/-0.8
+/-1.0
+/-1.25
+/-1.5
D
Dummy R123(up side),Mounting R136(down side)
--SRC7 on
Mounting R136(up side),Dummy R123(down side)
--CPU2_ITP on
TP78 TPAD30TP78 TPAD30
TP79 TPAD30TP79 TPAD30
PM_STPCPU# 16,32
D
DREFSSCLK 7
DREFSSCLK# 7
CLK_PCIE_NEW 20
CLK_PCIE_NEW# 20
CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7
CLK_PCIE_ICH 16
CLK_PCIE_ICH# 16
CLK_XDP_CPU 2,4
CLK_XDP_CPU# 2,4
CLK_MCH_BCLK 6
CLK_MCH_BCLK# 6
CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4
<Variant Name>
<Variant Name>
<Variant Name>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
PREQ2# 20
SB
E
3D3V_S0
12
R421
R421
10KR2J-2-GP
10KR2J-2-GP
DY
DY
H/L: 100/96MHz
SS_SEL
12
R419
R419
10KR2J-2-GP
10KR2J-2-GP
SB
CLK_XDP_CPU
CLK_XDP_CPU#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_MCH_BCLK
CLK_MCH_BCLK#
DREFCLK
DREFCLK#
DREFSSCLK
DREFSSCLK#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_NEW
CLK_PCIE_NEW#
CLK_PCIE_ICH
CLK_PCIE_ICH#
Clock Generator (ICS954226AG)
Clock Generator (ICS954226AG)
Clock Generator (ICS954226AG)
R435 49D9R2F-GP
R435 49D9R2F-GP
1 2
DY
DY
R427 49D9R2F-GP
R427 49D9R2F-GP
1 2
DY
DY
R425 49D9R2F-GPR425 49D9R2F-GP
1 2
R429 49D9R2F-GPR429 49D9R2F-GP
1 2
R428 49D9R2F-GPR428 49D9R2F-GP
1 2
R426 49D9R2F-GPR426 49D9R2F-GP
1 2
R125 49D9R2F-GPR125 49D9R2F-GP
1 2
R124 49D9R2F-GPR124 49D9R2F-GP
1 2
R418 49D9R2F-GPR418 49D9R2F-GP
1 2
R420 49D9R2F-GPR420 49D9R2F-GP
1 2
R410 49D9R2F-GPR410 49D9R2F-GP
1 2
R411 49D9R2F-GPR411 49D9R2F-GP
1 2
R423 49D9R2F-GPR423 49D9R2F-GP
1 2
R422 49D9R2F-GPR422 49D9R2F-GP
1 2
R412 49D9R2F-GPR412 49D9R2F-GP
1 2
R413 49D9R2F-GPR413 49D9R2F-GP
1 2
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
KeyWest
KeyWest
KeyWest
337Tuesday, August 16, 2005
337Tuesday, August 16, 2005
337Tuesday, August 16, 2005
E
3D3V_S0
3D3V_S04,5,7,9,11,13,15,16,17,18,19,20,23,24,25,27,29,32,34,36,37
SD
SD
SD
A
H_A#[31..3]6
H_A#3
P4
H_A#4
U4
H_A#5
V3
H_A#6
R3
H_A#7
4 4
H_ADSTB#06
H_REQ#[4..0]6
3 3
H_ADSTB#16
H_A20M#15
H_FERR#15
H_IGNNE#15
H_STPCLK#15
H_INTR15
H_NMI15
H_SMI#15
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
AA3
AA2
AF4
AC4
AC7
AC3
AD3
AE4
AD2
AB4
AC6
AD5
AE2
AD6
AF3
AE1
AF1
AE5
V2
W1
T4
W2
Y4
Y1
U1
Y3
U3
R2
P3
T2
P1
T1
C2
D3
A3
C6
D1
D4
B4
CPU
2 2
62.10055.011
62.10055.011
U46A
U46A
A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
ADDR GROUP 0
A16#
ADSTB#0
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
ADDR GROUP 1
A31#
ADSTB#1
A20M#
FERR#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#
HCLK THERM XTP/ITP SIGNALS CONTROL
PZ47903
PZ47903
ITP Conn.
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
RESET#
RS0#
RS1#
RS2#
TRDY#
HIT#
HITM#
BPM#0
BPM#1
BPM#2
BPM#3
PRDY#
PREQ#
TCK
TDO
TMS
TRST#
DBR#
PROCHOT#
THERMDA
THERMDC
THERMTRIP#
ITP_CLK1
ITP_CLK0
BCLK1
BCLK0
TDI
TCK(PIN 5)
TCK(PIN A13)
FBO(PIN 11)
N2
L1
J3
L4
H2
M2
N4
A4
B5
J2
B11
H1
K1
L2
M3
K3
K4
C8
B8
A9
C9
A10
B10
A13
C12
A12
C11
B13
A7
B17
B18
A18
C17
A15
A16
B14
B15
B
H_RS#0
H_RS#1
H_RS#2
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
DBR#
CPU_PROCHOT#
H_ADS# 6
H_BNR# 6
H_BPRI# 6
H_DEFER# 6
H_DRDY# 6
H_DBSY# 6
H_BREQ#0 6
H_IERR#
H_INIT# 15
H_LOCK# 6
H_CPURST# 2,6
H_TRDY# 6
H_HIT# 6
H_HITM# 6
XDP_BPM#0 2
XDP_BPM#1 2
XDP_BPM#2 2
XDP_BPM#3 2
XDP_PRDY# 2
XDP_BPM#5 2
XDP_TCK 2
XDP_TDI 2
XDP_TDO 2
XDP_TMS 2
XDP_TRST# 2
DBR# 2,16
THERMDP1 19
THERMDN 19
PM_THRMTRIP-A# 19
CLK_XDP_CPU# 2,3
CLK_XDP_CPU 2,3
CLK_CPU_BCLK# 3
CLK_CPU_BCLK 3
VCCP_GMCH_S0
PM_THRMTRIP-A#
VCCP_GMCH_S0
12
R274
R274
56R2J-4-GP
56R2J-4-GP
Place testpoint on
H_IERR# with a GND
0.1" away
H_RS#[2..0] 6
PM_THRMTRIP#
should connect to
SB
ICH6 and Alviso
without T-ing
( No stub)
CPU_SEL03,7
CPU_SEL13,7
Only support 400MHz ( GML )
12
R608
R608
56R2J-4-GP
56R2J-4-GP
SB
C
VCCP_GMCH_S0
1 2
1KR2F-3-GP
1KR2F-3-GP
H_DSTBN#06
H_DSTBP#06
H_DINV#06
H_DSTBN#16
H_DSTBP#16
H_DINV#16
R256 0R2J-GPR256 0R2J-GP
1 2
R257 0R2J-GPR257 0R2J-GP
1 2
R37
R37
12
R38
R38
2KR2F-3-GP
2KR2F-3-GP
BSEL[1:0] Freq.(MHz)
L H 100
L L 133
TP3TPAD30 TP3TPAD30
CPU_SEL0_CPU
SD
TP1TPAD30 TP1TPAD30
TP5TPAD30 TP5TPAD30
TP6TPAD30 TP6TPAD30
TP60TPAD30 TP60TPAD30
Layout Note:
0.5" max length.
CPU_SEL1_CPU
D
1st source:62.10079.001
2nd source:62.10053.341
62.10055.011
62.10055.011
U46B
U46B
H_D#0
A19
PSI#
C20
D24
C26
C25
C23
C22
D25
H23
G25
M26
H24
G24
M23
N24
M25
H26
N25
C16
C14
AF7
AC1
AD26
A25
A22
B21
A24
B26
A21
B20
B24
E24
B23
E23
L23
F25
K25
K24
L24
E26
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
DATA GRP 2
DATA GRP 0DATA GRP 1
D13#
D14#
D15#
DSTBN0#
DSTBN2#
DSTBP0#
DSTBP2#
DINV0#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
J23
D23#
D24#
J25
D25#
L26
D26#
D27#
D28#
D29#
D30#
D31#
DSTBN1#
DSTBP1#
J26
DINV1#
E1
PSI#
BSEL0
BSEL1
MISC
C3
RSVD2
RSVD3
RSVD4
RSVD5
GTLREF0
PZ47903
PZ47903
DINV2#
DATA GRP 3
DSTBN3#
DSTBP3#
DINV3#
COMP0
COMP1
COMP2
COMP3
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
TEST1
TEST2
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
CPU_TP3
CPU_TP4
CPU_TP5
CPU_TP6
GTLREF
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
SLP#
Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
W25
W24
T24
AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26
AE24
AE25
AD20
COMP0
P25
COMP1
P26
COMP2
AB2
COMP3
AB1
G1
B7
C19
E4
A6
TEST1
C5
TEST2
F23
R31
R31
1KR2J-1-GP
1KR2J-1-GP
DY
DY
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
R286 27D4R2F-L1-GPR286 27D4R2F-L1-GP
R287 54D9R2F-L1-GPR287 54D9R2F-L1-GP
R40 27D4R2F-L1-GPR40 27D4R2F-L1-GP
R39 54D9R2F-L1-GPR39 54D9R2F-L1-GP
12
12
H_DSTBN#2 6
H_DSTBP#2 6
H_DINV#2 6
Layout Note:
Comp0, 2 connect with Zo=27.4 ohm, make
trace length shorter than 0.5" .
Comp1, 3 connect with Zo=55 ohm, make
trace length shorter than 0.5" .
H_DSTBN#3 6
H_DSTBP#3 6
H_DINV#3 6
1 2
1 2
1 2
1 2
H_DPRSLP# 15
H_DPSLP# 15
H_DPWR# 6
H_CPUSLP# 6,15
R268
R268
1KR2J-1-GP
1KR2J-1-GP
DY
DY
E
VCCP_GMCH_S02,5,6,7,9,10,15,17,19,32,37
H_D#[63..0] 6
VCCP_GMCH_S0
12
R272
R272
200R2F-L-GP
200R2F-L-GP
VCCP_GMCH_S0
H_PWRGD 15
VCCP_GMCH_S0
C
VCCP_GMCH_S0
12
R513
R513
56R2J-4-GP
56R2J-4-GP
DY
DY
1
3
2
Q54
Q54
MMBT3904LT1-2-GP
MMBT3904LT1-2-GP
DY
DY
SB
3D3V_S5
12
R514
R514
330R2J-3-GP
330R2J-3-GP
PROCHOT# 27
D
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
CPU (1 of 2)
CPU (1 of 2)
CPU (1 of 2)
KeyWest
KeyWest
KeyWest
437Tuesday, August 16, 2005
437Tuesday, August 16, 2005
437Tuesday, August 16, 2005
of
of
E
of
SD
SD
SD
R532
R532
150R2F-1-GP
150R2F-1-GP
SB
SB
CPU_PROCHOT#
H_CPURST#
XDP_TDO
CPU_PROCHOT#
1 1
XDP_TDI
XDP_TMS
XDP_TRST#
XDP_TCK
R267 54D9R2F-L1-GPR267 54D9R2F-L1-GP
R260 54D9R2F-L1-GP
R260 54D9R2F-L1-GP
R258 56R2J-4-GPR258 56R2J-4-GP
R261 150R2F-1-GPR261 150R2F-1-GP
R263 39D2R2F-L-GPR263 39D2R2F-L-GP
R259 680R2J-3-GPR259 680R2J-3-GP
R262 27D4R2F-L1-GPR262 27D4R2F-L1-GP
DY
DY
1 2
1 2
1 2
1 2
12
12
12
SB
3D3V_S0
12
DBR#
All place within 2" to CPU
A
B
A
VCC_CORE_S0 VCC_CORE_S0
AA11
AA13
AA15
AA17
AA19
AA21
AA5
4 4
3 3
2 2
1 1
AA7
AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AB6
AB8
AC11
AC13
AC15
AC17
AC19
AC9
AD10
AD12
AD14
AD16
AD18
AD8
AE11
AE13
AE15
AE17
AE19
AE9
AF10
AF12
AF14
AF16
AF18
AF8
D18
D20
D22
E17
E19
E21
F18
F20
F22
G21
Layout Note:
62.10055.011
62.10055.011
U46C
U46C
VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
D6
VCC45
D8
VCC46
VCC47
VCC48
VCC49
E5
VCC50
E7
VCC51
E9
VCC52
VCC53
VCC54
VCC55
F6
VCC56
F8
VCCSENSE
VCC57
VCC58
VSSSENSE
PZ47903
PZ47903
VCCSENSE and VSSSENSE lines
should be of equal length.
Layout Note:
Provide a test point (with
no stub) to connect a
differential probe
between VCCSENSE and
VSSSENSE at the location
where the two 54.9ohm
resistors terminate the
55 ohm transmission line.
A
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCCA0
VCCA1
VCCA2
VCCA3
VCCP0
VCCP1
VCCP2
VCCP3
VCCP4
VCCP5
VCCP6
VCCP7
VCCP8
VCCP9
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16
VCCP17
VCCP18
VCCP19
VCCP20
VCCP21
VCCP22
VCCP23
VCCP24
VCCQ0
VCCQ1
VID0
VID1
VID2
VID3
VID4
VID5
G5
H22
H6
J21
J5
K22
U5
V22
V6
W21
W5
Y22
Y6
F26
B1
N1
AC26
D10
D12
D14
D16
E11
E13
E15
F10
F12
F14
F16
K6
L21
L5
M22
M6
N21
N5
P22
P6
R21
R5
T22
T6
U21
P23
W4
E2
F2
F3
G3
G4
H4
AE7
AF6
1.8V is for Dothan
A2 before.
Intel suggest Dothan
A2 or later only use
1.5V
1D5V_VCCA_S0
SCD01U16V2KX-LGP
SCD01U16V2KX-LGP
TP_VCCA1
TP_VCCA2
TP_VCCA3
CPU_D10
R271 0R0402-PADR271 0R0402-PAD
1 2
TP_VCCSENSE
TP_VSSSENSE
54D9R2F-L1-GP
54D9R2F-L1-GP
1D5V OR 1D8V
12
C18
C18
TP2 TPAD30TP2 TPAD30
TP4 TPAD30TP4 TPAD30
TP61 TPAD30TP61 TPAD30
H_VID0 32
H_VID1 32
H_VID2 32
H_VID3 32
H_VID4 32
H_VID5 32
12
12
R51
R51
DY
DY
VCCP_GMCH_S0
R50
R50
54D9R2F-L1-GP
54D9R2F-L1-GP
DY
DY
B
12
C12
C12
SC10U10V6ZY-U
SC10U10V6ZY-U
B
A11
A14
A17
A20
A23
A26
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE3
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF24
B12
B16
B19
B22
B25
C10
C13
C15
C18
C21
C24
D11
U46D
U46D
A2
VSS0
A5
VSS1
A8
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
B3
VSS75
B6
VSS76
B9
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
C1
VSS83
C4
VSS84
C7
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
D2
VSS92
D5
VSS93
D7
VSS94
D9
VSS95
VSS96
PZ47903
PZ47903
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
D13
D15
D17
D19
D21
D23
D26
E3
E6
E8
E10
E12
E14
E16
E18
E20
E22
E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1
M4
M5
M21
M24
N3
N6
N22
N23
N26
P2
P5
P21
P24
R1
R4
R6
R22
R25
T3
T5
T21
T23
T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24
62.10055.011
62.10055.011
C
VCCP_GMCH_S0
C21
C21
12
VCC_CORE_S0
12
C622
C622
DY
DY
C
3D3V_S0
12
BC45
BC45
SC1U10V3ZY
SC1U10V3ZY
DY
DY
0.1u *10 150u *1
C22
C22
12
12
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
VCC_CORE_S0
12
C19
C19
VCC_CORE_S0
12
C41
C41
12
C623
C623
DY
DY
DY
DY
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
C32
C32
12
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
C624
C624
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
12
1
2
3
12
C20
C20
12
DY
DY
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
C36
C36
C49
C49
12
U45
U45
SHDN#
GND
IN
G913CF-GP
G913CF-GP
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
I max = 120 mA
SET
OUT
DY
DY
C25
C25
12
12
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
10u *35270u *4
12
12
C26
C26
C24
C24
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
12
C254
C254
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SB
SD
12
C625
C625
C626
C626
DY
DY
DY
DY
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
C13
C13
12
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
12
C627
C627
5
4
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
12
C255
C255
1D5V_VCCA_S0
SB
12
C31
C31
DY
DY
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
C30
C30
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
12
C628
C628
12
BC46
BC46
SC22P50V2JN-4GP
SC22P50V2JN-4GP
12
BC2
BC2
SC1U10V3ZY
SC1U10V3ZY
DY
DY
C37
C37
12
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
12
C34
C34
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
12
C258
C258
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
12
C629
C629
DY
DY
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
D
DY
DY
1D5V_VCCA_SET
C23
C23
12
12
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
12
12
C40
C40
C35
C35
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
12
C257
C257
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
12
C630
C630
DY
DY
DY
DY
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
D
E
VCC_CORE_S032,36
VCCP_GMCH_S02,4,6,7,9,10,15,17,19,32,37
3D3V_S03,4,7,9,11,13,15,16,17,18,19,20,23,24,25,27,29,32,34,36,37
1D5V_S07,9,16,17,20,36,37
1D5V_VCCA_S0 1D5V_S0
Need change to CAP
12
12
C261
C261
C262
C262
R30
R30
1 2
0R0402-PAD
0R0402-PAD
Need change to CAP
C29
C29
12
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
C259
C259
12
12
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
12
R280
R280
12K7R3F-GP
12K7R3F-GP
DY
DY
R281
R281
49K9R2F-L-GP
49K9R2F-L-GP
DY
DY
TC1
TC1
12
12
C39
C39
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
12
C260
C260
ST100U6D3VBM-8GP
ST100U6D3VBM-8GP
C42
C42
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
SB
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
12
C631
C631
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
Date: Sheet
Date: Sheet
Date: Sheet
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
CPU (2 of 2)
CPU (2 of 2)
CPU (2 of 2)
KeyWest
KeyWest
KeyWest
E
537Tuesday, August 16, 2005
537Tuesday, August 16, 2005
537Tuesday, August 16, 2005
VCC_CORE_S0
VCCP_GMCH_S0
3D3V_S0
1D5V_S0
of
of
of
SD
SD
SD
A
Trace 10 mil wide with 20 mil spacing
H_XRCOMP
12
R78
R78
24D9R2F-L-GP
24D9R2F-L-GP
4 4
VCCP_GMCH_S0
R77
R77
54D9R2F-L1-GP
54D9R2F-L1-GP
1 2
H_XSCOMP
VCCP_GMCH_S0
12
R75
R75
221R3F-1-GP
221R3F-1-GP
H_XSWING
12
R76
3 3
R76
100R2F-L1-GP-U
100R2F-L1-GP-U
1 2
C85
C85
SCD1U16V
SCD1U16V
VCCP_GMCH_S0
VCCP_GMCH_S0
H_YRCOMP
12
R91
R91
24D9R2F-L-GP
24D9R2F-L-GP
R92
R92
54D9R2F-L1-GP
54D9R2F-L1-GP
1 2
H_YSCOMP
12
R89
R89
221R3F-1-GP
221R3F-1-GP
H_YSWING
12
R90
R90
100R2F-L1-GP-U
100R2F-L1-GP-U
1 2
H_D#[63..0]4 H_A#[31..3] 4
C98
C98
SCD1U16V
SCD1U16V
Trace 10 mil wide with 20 mil spacing
Alviso Strapping Signals
and Configuration
Pin Name
CFG[2:0]
CFG[4:3] Reserved
CFG5 DMI x2 Select
2 2
CFG6 Reserved
CFG7
CFG8
CFG9
CFG[11:10]
CFG[13:12]
CFG[15:14] Reversed
CFG16
CFG17
CFG18
1 1
CFG19
CFG20
SDVOCRTL
_DATA
All strap signals are sampled with respect to the leading
NOTE:
edge of the Alviso GMCH PWORK In signal.
Strap Description Configuration
CPU Strap
Reserved
PCI Express Graphics
Lane Reversal
Reserved
XOR/ALL Z test
straps
FSB Dynamic ODT
Reversed
GMCH core VCC
Select
CPU VTT Select
Reversed
SDVO Present
A
REV.NO. 1.0
REF. NO. 15577
001 = FSB533FSB Frequency Select
101 = FSB400
others = Reversed
0 = DMI x2
1 = DMI x4
0 = DDR2
1 = DDR1
0 = Reserved
1 = Dothan
0 = Reserve Lanes
1 = Normal
00 = Reserved
01 = XOR mode enabled
10 = All Z mode enabled
11 = Normal Operation
0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled
0 = 1.05V
1 = 1.5V
0 = 1.05V
1 = 1.2V
(Default)
(Default)
(Default)
(Default)
(Default)
(Default)
0 = No SDVO device present
1= SDVO device present
page 183
(Default)
(Default)
(Default)
B
C
D
E
CORE_GMCH_S0
CORE_GMCH_S09,10,37
VCCP_GMCH_S0
VCCP_GMCH_S02,4,5,7,9,10,15,17,19,32,37
Power On Sequencing
U18A
U18A
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING
E4
HD0#
E1
HD1#
F4
HD2#
H7
HD3#
E2
HD4#
F1
HD5#
E3
HD6#
D3
HD7#
K7
HD8#
F2
HD9#
J7
HD10#
J8
HD11#
H6
HD12#
F3
HD13#
K8
HD14#
H5
HD15#
H1
HD16#
H2
HD17#
K5
HD18#
K6
HD19#
J4
HD20#
G3
HD21#
H3
HD22#
J1
HD23#
L5
HD24#
K4
HD25#
J5
HD26#
P7
HD27#
L7
HD28#
J3
HD29#
P5
HD30#
L3
HD31#
U7
HD32#
V6
HD33#
R6
HD34#
R5
HD35#
P3
HD36#
T8
HD37#
R7
HD38#
R8
HD39#
U8
HD40#
R4
HD41#
T4
HD42#
T5
HD43#
R1
HD44#
T3
HD45#
V8
HD46#
U6
HD47#
W6
HD48#
U3
HD49#
V5
HD50#
W8
HD51#
W7
HD52#
U2
HD53#
U1
HD54#
Y5
HD55#
Y2
HD56#
V4
HD57#
Y7
HD58#
W1
HD59#
W3
HD60#
Y3
HD61#
Y6
HD62#
W2
HD63#
C1
HXRCOMP
C2
HXSCOMP
D1
HXSWING
T1
HYRCOMP
L1
HYSCOMP
P1
HYSWING
71.0GMCH.0JU
71.0GMCH.0JU
HCPURST#
HOST
HOST
HCPUSLP#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HADS#
HADSTB#0
HADSTB#1
HVREF
HBNR#
HBPRI#
HBREQ0#
HCLKINN
HCLKINP
HDBSY#
HDEFER#
HDINV#0
HDINV#1
HDINV#2
HDINV#3
HDPWR#
HDRDY#
HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3
HEDRDY#
HHITM#
HLOCK#
HPCREQ#
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HRS0#
HRS1#
HRS2#
HTRDY#
910GML(LF C1):71.0GMCH.M28
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HHIT#
G9
C9
E9
B7
A10
F9
D8
B10
E10
G10
D9
E11
F10
G11
G13
C10
C11
D11
C12
B13
A12
F12
G12
E12
C13
B11
D13
A13
F13
F8
B9
E13
J11
A5
D5
E7
H10
AB1
AB2
C6
E6
H8
K3
T7
U5
G6
F7
G4
K1
R3
V3
G5
K2
R2
W4
F6
D4
D6
B3
A11
A7
D7
B8
C7
A8
A4
C5
B4
G8
B5
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
TP_H_EDRDY#
TP_H_PCREQ#
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
H_CPUSLP#_GMCH
H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPRI# 4
H_BREQ#0 4
H_CPURST# 2,4
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
CLK_MCH_BCLK# 3
CLK_MCH_BCLK 3
H_DBSY# 4
H_DEFER# 4
H_DPWR# 4
H_DRDY# 4
TP64 TPAD30TP64 TPAD30
H_HIT# 4
H_HITM# 4
H_LOCK# 4
TP11 TPAD30TP11 TPAD30
H_TRDY# 4
VCCP_GMCH_S0
12
R310
R310
100R2F-L1-GP-U
100R2F-L1-GP-U
H_VREF
12
12
R311
R311
200R2F-L-GP
C281
C281
For
Banias/Celeron-M:R291=DUMMY
For Dothan A:R291=DUMMY
For Dothan B:R291=0R
200R2F-L-GP
H_DINV#[3..0] 4
H_DSTBN#[3..0] 4
H_DSTBP#[3..0] 4
R291
R291
1 2
0R0402-PAD
0R0402-PAD
H_REQ#[4..0] 4
H_RS#[2..0] 4
915GM (LF C1):71.0GMCH.M27
B
C
D
VID
VR_ON
Vcc_core
Vccp
Vcc_mch
MCH_PWERGD
CLK_ENABLE#
VGATE TO ICH6
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
>3mS
10~30uS
H_DPWR#
H_CPUSLP# 4,15
Vboot
<10uS
CORE_GMCH_S0
12
R358
R358
0R2J-GP
0R2J-GP
DY
DY
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
GMCH (1 of 5)
GMCH (1 of 5)
GMCH (1 of 5)
KeyWest
KeyWest
KeyWest
Vboot Vvid
>100uS
3~10mS
637Tuesday, August 16, 2005
637Tuesday, August 16, 2005
637Tuesday, August 16, 2005
E
SD
SD
of
of
of
SD
A
U18B
U18B
AA31
DMIRXN0
AB35
DMIRXN1
AC31
DMIRXN2
AD35
DMIRXN3
Y31
DMIRXP0
AA35
DMIRXP1
AB31
DMIRXP2
AC35
DMIRXP3
AA33
DMITXN0
AB37
DMITXN1
AC33
DMITXN2
AD37
DMITXN3
Y33
DMITXP0
AA37
DMITXP1
AB33
DMITXP2
AC37
DMITXP3
AM33
SM_CK0
AL1
SM_CK1
AE11
SM_CK2
AJ34
SM_CK3
AF6
SM_CK4
AC10
SM_CK5
AN33
SM_CK0#
AK1
SM_CK1#
AE10
SM_CK2#
AJ33
SM_CK3#
AF5
SM_CK4#
AD10
SM_CK5#
AP21
SM_CKE0
AM21
SM_CKE1
AH21
SM_CKE2
AK21
SM_CKE3
AN16
SM_CS0#
AM14
SM_CS1#
AH15
SM_CS2#
AG16
SM_CS3#
AF22
SM_OCDCOMP0
AF16
SM_OCDCOMP1
AP14
SM_ODT0
AL15
SM_ODT1
AM11
SM_ODT2
AN10
SM_ODT3
AK10
SMRCOMPN
AK11
SMRCOMPP
AF37
SMVREF0
AD1
SMVREF1
AE27
SMXSLEWIN
AE28
SMXSLEWOUT
AF9
SMYSLEWIN
AF10
SMYSLEWOUT
71.0GMCH.0JU
71.0GMCH.0JU
EXT_TSO# 27
Ref ALVISO EDS-1 Page 115
For Dothan-B
12
R66
R66
1KR2J-1-GP
1KR2J-1-GP
DY
DY
CPU_SEL0
CPU_SEL1
12
R67
R67
4K7R2J-2-GP
4K7R2J-2-GP
DY
DY
CPU_SEL0=0(R67):133MHZ
CPU_SEL0=1(R66):100MHZ
SD
CPU_SEL0 3,4
CPU_SEL1 3,4
CFG(2..1) FREQ.(MHz)
10 400
00 533
11 Reserved
R372
R372
DMI_TXN[3..0]16
DMI_TXP[3..0]16
DMI_RXN[3..0]16
DMI_RXP[3..0]16
CLK_DDR011
CLK_DDR111
CLK_DDR311
CLK_DDR411
CLK_DDR0#11
CLK_DDR1#11
CLK_DDR3#11
CLK_DDR4#11
M_CKE0_R#11,12
M_CKE1_R#11,12
M_CKE2_R#11,12
M_CKE3_R#11,12
M_CS0_R#11,12
M_CS1_R#11,12
M_CS2_R#11,12
M_CS3_R#11,12
M_OCDCOMP0
M_OCDCOMP1
12
M_ODT011,12
DY
DY
40D2R2F-GP
40D2R2F-GP
M_ODT111,12
M_ODT211,12
M_ODT311,12
DDR_VREF_S3
4 4
3 3
Layout Note:
Route as short
as possible
12
R373
R373
DY
DY
40D2R2F-GP
40D2R2F-GP
SB
2 2
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
2D5V_S0
R345
R345
1 2
R349
R349
1 2
PM_EXTTS#0
10KR2J-2-GP
10KR2J-2-GP
PM_EXTTS#1
10KR2J-2-GP
10KR2J-2-GP
C112
C112
12
R516
R516
1 2
DY
DY
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
M_RCOMPN
M_RCOMPP
SMXSLEW
SMYSLEW
SB
0R2J-GP
0R2J-GP
VCCP_GMCH_S0
FOR DDR2
1D8V_S3
12
R371
R371
80D6R2F-L-GP
80D6R2F-L-GP
M_RCOMPN CFG0
12
R391
R391
80D6R2F-L-GP
80D6R2F-L-GP
M_RCOMPP
1 1
A
12
R319
R319
10KR2J-2-GP
10KR2J-2-GP
4K7R2J-2-GP
4K7R2J-2-GP
SD
DY
DY
R64
R64
12
R65
R65
10KR2J-2-GP
10KR2J-2-GP
DY
DY
12
B
CFG/RSVD
CFG/RSVD
BM_BUSY#
EXT_TS0#
EXT_TS1#
THRMTRIP#
PM
PM
DREF_CLKN
DREF_CLKP
DREF_SSCLKN
CLK
CLK
DREF_SSCLKP
NC#AP37
NC#AN37
NC#AP36
NC
NC
B
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
PWROK
RSTIN#
NC#AP2
NC#AP1
NC#AN1
NC#B1
NC#A2
NC#B37
NC#A36
NC#A37
DMI
DMI
DDR MUXING
DDR MUXING
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
H13
G14
F16
F15
G15
E16
D17
J16
D15
E15
D14
E14
H12
C14
H15
J15
H14
G22
G23
D23
G25
G24
J17
A31
A30
D26
D25
J23
J21
H22
F5
AD30
AE29
A24
A23
C37
D37
AP37
AN37
AP36
AP2
AP1
AN1
B1
A2
B37
A36
A37
CPU_SEL1
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
PM_EXTTS#0
PM_EXTTS#1
RST1#
R374 100R2F-L1-GP-UR374 100R2F-L1-GP-U
GMCH_TP3
GMCH_TP4
GMCH_TP5
GMCH_TP6
GMCH_TP7
GMCH_TP8
GMCH_TP9
GMCH_TP10
GMCH_TP11
GMCH_TP12
GMCH_TP13
CFG0
G16
When Low 2.2K Ohm
R324 DUMMY-R2R324 DUMMY-R2
1 2
R322 DUMMY-R2R322 DUMMY-R2
1 2
R318 DUMMY-R2R318 DUMMY-R2
1 2
R326 2K2R2J-2-GPR326 2K2R2J-2-GP
1 2
R327 DUMMY-R2R327 DUMMY-R2
1 2
R314 DUMMY-R2R314 DUMMY-R2
1 2
R323 DUMMY-R2R323 DUMMY-R2
1 2
R325 DUMMY-R2R325 DUMMY-R2
1 2
R68 DUMMY-R2R68 DUMMY-R2
1 2
R320 DUMMY-R2R320 DUMMY-R2
1 2
R312 DUMMY-R2R312 DUMMY-R2
1 2
R321 DUMMY-R2R321 DUMMY-R2
1 2
R316 DUMMY-R2R316 DUMMY-R2
1 2
R313 DUMMY-R2R313 DUMMY-R2
1 2
R315 DUMMY-R2R315 DUMMY-R2
1 2
C
R317
R317
1 2
1 2
CPU_SEL0
1KR2J-1-GP
1KR2J-1-GP TP68TPAD30 TP68TPAD30
GMCH_DDCCLK14
GMCH_DDCDATA14
TP70 TPAD30TP70 TPAD30
TP66 TPAD30TP66 TPAD30
TP65 TPAD30TP65 TPAD30
TP13 TPAD30TP13 TPAD30
TP12 TPAD30TP12 TPAD30
TP69 TPAD30TP69 TPAD30
TP67 TPAD30TP67 TPAD30
PM_BMBUSY# 16
DREFCLK# 3
DREFCLK 3
DREFSSCLK# 3
DREFSSCLK 3
TP22 TPAD30TP22 TPAD30
TP20 TPAD30TP20 TPAD30
TP21 TPAD30TP21 TPAD30
TP17 TPAD30TP17 TPAD30
TP18 TPAD30TP18 TPAD30
TP19 TPAD30TP19 TPAD30
TP9 TPAD30TP9 TPAD30
TP10 TPAD30TP10 TPAD30
TP16 TPAD30TP16 TPAD30
TP15 TPAD30TP15 TPAD30
TP14 TPAD30TP14 TPAD30
VGA_BLUE14
VGA_GREEN14
VGA_RED14
R74 150R2F-1-GP
R74 150R2F-1-GP
1 2
DY
DY
R73 150R2F-1-GP
R73 150R2F-1-GP
1 2
DY
DY
R72 150R2F-1-GP
R72 150R2F-1-GP
SC
BL_ON
BIA_PWM
LIBG
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
1 2
DY
DY
VGA_VSYNC14
VGA_HSYNC14
THERMTRIP_GMCH# 19
GMCH_PWROK 32
PLT_RST1# 18,20,27,29
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
R351 100KR2J-1-GPR351 100KR2J-1-GP
1 2
R347 100KR2J-1-GPR347 100KR2J-1-GP
1 2
R348 1K5R2F-2-GPR348 1K5R2F-2-GP
1 2
EDID_DAT13
Strapping
CFG[17:3] have internal pullup resistors.
CFG[19:18] have internal pulldown resistors
Intel suggest NC Due to votusly DVO
R53 39R2J-L-GPR53 39R2J-L-GP
R52 39R2J-L-GPR52 39R2J-L-GP
R359 255R2F-L-GPR359 255R2F-L-GP
GBKLT_EN27
LCDVDD_ON13,27
RN27
RN27
1
2
3
4 5
EDID_CLK13
SRN2K2
SRN2K2
C
8
7
6
Less than 0.5", trace impendance 37.5ohmTrace impendance 50ohm
1 2
1 2
1 2
SB
BIA_PWM13,27
BL_ON13
SB
TP62TPAD30 TP62TPAD30
TP73TPAD30 TP73TPAD30
TP72TPAD30 TP72TPAD30
2D5V_S0
3D3V_S0
1
23
4
TP71TPAD30 TP71TPAD30
CLK_MCH_3GPLL#3
CLK_MCH_3GPLL3
SB
R533 0R2J-GPR533 0R2J-GP
1 2
NO STUFF
TXACLK-13
TXACLK+13
TXBCLK-13
TXBCLK+13
TXAOUT0-13
TXAOUT1-13
TXAOUT2-13
TXAOUT0+13
TXAOUT1+13
TXAOUT2+13
TXBOUT0-13
TXBOUT1-13
TXBOUT2-13
TXBOUT0+13
TXBOUT1+13
TXBOUT2+13
RN26
RN26
SRN4K7J-8-GP
SRN4K7J-8-GP
LDDC_CLK
D
Alviso will provide SDVO_CTRLCLK
and CTRLDATA pulldowns on-die
U18G
U18G
SDVO_DAT
SDVO_CLK
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LIBG
2D5V_S0
U15
U15
5
6
2N7002DW-7F-GP
2N7002DW-7F-GP
VSYNC
HSYNC
CRTIREF
L_LVBG
L_VREFH
L_VREFL
34
2
1
H24
SDVOCTRL_DATA
H25
SDVOCTRL_CLK
AB29
GCLKN
AC29
GCLKP
A15
TVDAC_A
C16
TVDAC_B
A17
TVDAC_C
J18
TV_REFSET
B15
TV_IRTNA
B16
TV_IRTNB
B17
TV_IRTNC
E24
DDCCLK
E23
DDCDATA
E21
BLUE
D21
BLUE#
C20
GREEN
B20
GREEN#
A19
RED
B19
RED#
H21
VSYNC
G21
HSYNC
J20
REFSET
E25
LBKLT_CRTL
F25
LBKLT_EN
C23
LCTLA_CLK
C22
LCTLB_DATA
F23
LDDC_CLK
F22
LDDC_DATA
F26
LVDD_EN
C33
LIBG
C31
LVBG
F28
LVREFH
F27
LVREFL
B30
LACLKN
B29
LACLKP
C25
LBCLKN
C24
LBCLKP
B34
LADATAN0
B33
LADATAN1
B32
LADATAN2
A34
LADATAP0
A33
LADATAP1
B31
LADATAP2
C29
LBDATAN0
D28
LBDATAN1
C27
LBDATAN2
C28
LBDATAP0
D27
LBDATAP1
C26
LBDATAP2
71.0GMCH.0JU
71.0GMCH.0JU
LDDC_DATA
D
E
3D3V_S03,4,5,9,11,13,15,16,17,18,19,20,23,24,25,27,29,32,34,36,37
2D5V_S09,14,17,34,36
1D8V_S39,10,11,12,16,34,35,36,37
1D5V_S05,9,16,17,20,36,37
VCCP_GMCH_S02,4,5,6,9,10,15,17,19,32,37
DDR_VREF_S311,35
R79
PEG_COMP
When High 1K Ohm
R350 DUMMY-R2R350 DUMMY-R2
1 2
R346 DUMMY-R2R346 DUMMY-R2
1 2
R344 DUMMY-R2R344 DUMMY-R2
1 2
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
E
EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8
EXP_TXN9
EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
D36
D34
E30
F34
G30
H34
J30
K34
L30
M34
N30
P34
R30
T34
U30
V34
W30
Y34
D30
E34
F30
G34
H30
J34
K30
L34
M30
N34
P30
R34
T30
U34
V30
W34
E32
F36
G32
H36
J32
K36
L32
M36
N32
P36
R32
T36
U32
V36
W32
Y36
D32
E36
F32
G36
H32
J36
K32
L36
M32
N36
P32
R36
T32
U36
V32
W36
GMCH (2 of 5)
GMCH (2 of 5)
GMCH (2 of 5)
KeyWest
KeyWest
KeyWest
2D5V_S0
THERMTRIP_GMCH#
EXP_COMPI
EXP_ICOMPO
MISCTVVGALVDS
MISCTVVGALVDS
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15
PCI-EXPRESS GRAPHICS
PCI-EXPRESS GRAPHICS
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
R79
24D9R2F-L-GP
24D9R2F-L-GP
VCCP_GMCH_S0
12
R609
R609
56R2J-4-GP
56R2J-4-GP
737Tuesday, August 16, 2005
737Tuesday, August 16, 2005
737Tuesday, August 16, 2005
of
of
of
3D3V_S0
2D5V_S0
1D8V_S3
1D5V_S0
VCCP_GMCH_S0
DDR_VREF_S3
1D5V_S0
12
CFG18
CFG19
CFG20
SB
SD
SD
SD
A
B
C
D
E
SUPPORT DDRII 400
4 4
U18C
M_A_DATA[63..0]11 M_B_DATA[63..0]11
3 3
2 2
M_A_DATA0
M_A_DATA1
M_A_DATA2
M_A_DATA3
M_A_DATA4
M_A_DATA5
M_A_DATA6
M_A_DATA7
M_A_DATA8
M_A_DATA9
M_A_DATA10
M_A_DATA11
M_A_DATA12
M_A_DATA13
M_A_DATA14
M_A_DATA15
M_A_DATA16
M_A_DATA17
M_A_DATA18
M_A_DATA19
M_A_DATA20
M_A_DATA21
M_A_DATA22
M_A_DATA23
M_A_DATA24
M_A_DATA25
M_A_DATA26
M_A_DATA27
M_A_DATA28
M_A_DATA29
M_A_DATA30
M_A_DATA31
M_A_DATA32
M_A_DATA33
M_A_DATA34
M_A_DATA35
M_A_DATA36
M_A_DATA37
M_A_DATA38
M_A_DATA39
M_A_DATA40
M_A_DATA41
M_A_DATA42
M_A_DATA43
M_A_DATA44
M_A_DATA45
M_A_DATA46
M_A_DATA47
M_A_DATA48
M_A_DATA49
M_A_DATA50
M_A_DATA51
M_A_DATA52
M_A_DATA53
M_A_DATA54
M_A_DATA55
M_A_DATA56
M_A_DATA57
M_A_DATA58
M_A_DATA59
M_A_DATA60
M_A_DATA61
M_A_DATA62
M_A_DATA63
AG35
AH35
AL35
AL37
AH36
AJ35
AK37
AL34
AM36
AN35
AP32
AM31
AM34
AM35
AL32
AM32
AN31
AP31
AN28
AP28
AL30
AM30
AM28
AL28
AP27
AM27
AM23
AM22
AL23
AM24
AN22
AP22
AM9
AL9
AL6
AP7
AP11
AP10
AL7
AM7
AN5
AN6
AN3
AP3
AP6
AM6
AL4
AM3
AK2
AK3
AG2
AG1
AL3
AM2
AH3
AG3
AF3
AE3
AD6
AC4
AF2
AF1
AD4
AD5
U18C
SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8
SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42
SADQ43
SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63
AK15
SA_BS0#
AK16
SA_BS1#
AL21
SA_BS2#
AJ37
SA_DM0
AP35
SA_DM1
AL29
SA_DM2
AP24
SA_DM3
AP9
SA_DM4
AP4
SA_DM5
AJ2
SA_DM6
AD3
SA_DM7
AK36
SA_DQS0
AP33
SA_DQS1
AN29
SA_DQS2
AP23
SA_DQS3
AM8
SA_DQS4
AM4
SA_DQS5
AJ1
SA_DQS6
AE5
SA_DQS7
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_CAS#
SA_RAS#
SA_WE#
AK35
AP34
AN30
AN23
AN8
AM5
AH1
AE4
AL17
AP17
AP18
AM17
AN18
AM18
AL19
AP20
AM19
AL20
AM16
AN20
AM20
AM15
AN15
AP16
AF29
AF28
AP15
SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
SA_RCVENIN#
SA_RCVENOUT#
M_A_SDM0
M_A_SDM1
M_A_SDM2
M_A_SDM3
M_A_SDM4
M_A_SDM5
M_A_SDM6
M_A_SDM7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
GMCH_TP48
GMCH_TP49
TP77 TPAD30TP77 TPAD30
M_A_BS0# 11,12
M_A_BS1# 11,12
M_A_BS2# 11,12
M_A_SDM[7..0] 11
M_A_DQS[7..0] 11
M_A_DQS#[7..0] 11
M_A_A[13..0] 11,12
M_A_CAS# 11,12
M_A_RAS# 11,12
M_A_WE# 11,12
M_B_DATA0
M_B_DATA1
M_B_DATA2
M_B_DATA3
M_B_DATA4
M_B_DATA5
M_B_DATA6
M_B_DATA7
M_B_DATA8
M_B_DATA9
M_B_DATA10
M_B_DATA11
M_B_DATA12
M_B_DATA13
M_B_DATA14
M_B_DATA15
M_B_DATA16
M_B_DATA17
M_B_DATA18
M_B_DATA19
M_B_DATA20
M_B_DATA21
M_B_DATA22
M_B_DATA23
M_B_DATA24
M_B_DATA25
M_B_DATA26
M_B_DATA27
M_B_DATA28
M_B_DATA29
M_B_DATA30
M_B_DATA31
M_B_DATA32
M_B_DATA33
M_B_DATA34
M_B_DATA35
M_B_DATA36
M_B_DATA37
M_B_DATA38
M_B_DATA39
M_B_DATA40
M_B_DATA41
M_B_DATA42
M_B_DATA43
M_B_DATA44
M_B_DATA45
M_B_DATA46
M_B_DATA47
M_B_DATA48
M_B_DATA49
M_B_DATA50
M_B_DATA51
M_B_DATA52
M_B_DATA53
M_B_DATA54
M_B_DATA55
M_B_DATA56
M_B_DATA57
M_B_DATA58
M_B_DATA59
M_B_DATA60
M_B_DATA61
M_B_DATA62
M_B_DATA63
AE31
AE32
AG32
AG36
AE34
AE33
AF31
AF30
AH33
AH32
AK31
AG30
AG34
AG33
AH31
AJ31
AK30
AJ30
AH29
AH28
AK29
AH30
AH27
AG28
AF24
AG23
AJ22
AK22
AH24
AH23
AG22
AJ21
AG10
AG9
AG8
AH8
AH11
AH10
AK9
AK6
AH5
AK8
AK4
AG5
AG4
AD8
AD9
AH4
AG6
AE8
AD7
AC5
AB8
AB6
AA8
AC8
AC7
AA4
AA5
U18D
U18D
SBDQ0
SBDQ1
SBDQ2
SBDQ3
SBDQ4
SBDQ5
SBDQ6
SBDQ7
SBDQ8
SBDQ9
SBDQ10
SBDQ11
SBDQ12
SBDQ13
SBDQ14
SBDQ15
SBDQ16
SBDQ17
SBDQ18
SBDQ19
SBDQ20
SBDQ21
SBDQ22
SBDQ23
SBDQ24
SBDQ25
SBDQ26
SBDQ27
SBDQ28
SBDQ29
SBDQ30
SBDQ31
SBDQ32
SBDQ33
SBDQ34
SBDQ35
SBDQ36
SBDQ37
AJ9
SBDQ38
SBDQ39
AJ7
SBDQ40
SBDQ41
AJ4
SBDQ42
SBDQ43
SBDQ44
AJ8
SBDQ45
AJ5
SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
SB_RCVENIN#
SB_RCVENOUT#
SB_BS0#
SB_BS1#
SB_BS2#
SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_CAS#
SB_RAS#
SB_WE#
AJ15
AG17
AG21
AF32
AK34
AK27
AK24
AJ10
AK5
AE7
AB7
AF34
AK32
AJ28
AK23
AM10
AH6
AF8
AB4
AF35
AK33
AK28
AJ23
AL10
AH7
AF7
AB5
AH17
AK17
AH18
AJ18
AK18
AJ19
AK19
AH19
AJ20
AH20
AJ16
AG18
AG20
AG15
AH14
AK14
AF15
AF14
AH16
M_B_SDM0
M_B_SDM1
M_B_SDM2
M_B_SDM3
M_B_SDM4
M_B_SDM5
M_B_SDM6
M_B_SDM7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
GMCH_TP50
GMCH_TP51
TP75 TPAD30TP75 TPAD30TP76 TPAD30TP76 TPAD30
TP74 TPAD30TP74 TPAD30
M_B_BS0# 11,12
M_B_BS1# 11,12
M_B_BS2# 11,12
M_B_SDM[7..0] 11
M_B_DQS[7..0] 11
M_B_DQS#[7..0] 11
M_B_A[13..0] 11,12
M_B_CAS# 11,12
M_B_RAS# 11,12
M_B_WE# 11,12
71.0GMCH.0JU
71.0GMCH.0JU
1 1
A
B
C
71.0GMCH.0JU
71.0GMCH.0JU
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
D
Date: Sheet
GMCH (3 of 5)
GMCH (3 of 5)
GMCH (3 of 5)
KeyWest
KeyWest
KeyWest
E
SD
SD
837Tuesday, August 16, 2005
837Tuesday, August 16, 2005
837Tuesday, August 16, 2005
of
of
of
SD
A
For TVDAC capacitors
Stuff SCD1U10V2MX-1 for TV-OUT enable
SB
3D3V_S0
12
C268
U10
U10
3
VIN
APL5308-25AC-1GPU
APL5308-25AC-1GPU
12
C50
C50
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
C268
VOUT
GND
4 4
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
3 3
3D3V_S0
2 2
CORE_GMCH_S0
Stuff 0R2-0 for TV-OUT disable
R55
R55
TVDAC_PWR
1 2
10R2J-2-GP
10R2J-2-GP
2D5V_CRTDAC_S0
2
1
12
SSM5818SLPT-GP
SSM5818SLPT-GP
C51
C51
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
2 1
1D5V_S0
D4
D4
1D5V_DLVDS_S0
H17
B26
VSSA_TVBG
VCC8
VCC9
R28
D19
P28
VCCD_TVDAC
VCC10
N28
VCCDQ_TVDAC
VCC11
M28
VCC12
L28
B25
VCCD_LVDS0
VCC13
K28
F17
E17
D18
C18
F18
E18
G18
H18
VCCA_TVDACA1
VCC1
N29
VCCA_TVDACB0
VCC2
M29
VCCA_TVDACB1
VCC3
VCCA_TVBG
VCCA_TVDACC0
VCCA_TVDACC1
VCC4
VCC5
VCC6
VCC7
J29
T28
K29
V28
U28
VCCA_TVDACA0
VCC0
T29
R29
A25
VCCD_LVDS1
VCC14
J28
VCCD_LVDS2
VCC15
H28
A35
VCC16
G28
VCCA_LVDS
VCC17
V27
B22
VCC18
U27
B
B21
VCCHV0
VCC19
T27
VCCHV1
VCC20
A21
R27
VCCHV2
VCC21
P27
12
V1.8_DDR_CAP1
AM37
VCC22
N27
VCCSM0
VCC23
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
C130
C130
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
12
C129
C129
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
C128
C128
1 2
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
V1.8_DDR_CAP2
V1.8_DDR_CAP5
AH37
AP29
AD28
AD27
AC27
AP26
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCC24
VCC25
VCC26
VCC27
VCC28
J27
L27
K27
K26
H27
M27
12
C66
C66
Note: All VCCSM
pins shorted
internally
AK26
AJ26
AH26
AN26
AM26
AL26
VCCSM6
VCCSM7
VCCSM8
VCCSM9
VCCSM10
VCCSM11
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
J25
K25
K24
K23
K22
H26
AG26
VCCSM12
VCC35
K21
AF26
VCCSM13
VCC36
W20
AE26
VCCSM14
VCC37
U20
12
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
AP25
AN25
AM25
AL25
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCC38
VCC39
VCC40
VCC41
VCC42
T20
K20
V19
U19
2D5V_S02D5V_TVDAC_S0
G10
G10
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
C67
C67
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
C321
C321
AK25
AJ25
AH25
AG25
AF25
AE25
AE24
AE23
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
POWER
POWER
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCCH_MPLL1
T18
K19
V18
K18
K17
AC2
W18
C
1D5V_S0
G11
G11
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
2D5V_S0 2D5V_ALVDS_S0
G13
G13
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
2D5V_S0 2D5V_TXLVDS_S0
G12
G12
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
12
12
C309
C309
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
AE22
AE21
AE20
AE19
AE18
AE17
AE16
AE15
AE14
AP13
AN13
AM13
AL13
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCH_MPLL0
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL
VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC
VCC_SYNC
F19
B23
AC1
C35
AA1
AA2
E19
H20
G19
AK13
K13
C71
C71
C75
C75
C73
C73
AJ13
VCCSM41
VTT0
J13
AH13
VCCSM42
VTT1
K12
12
AG13
VCCSM43
VTT2
W11
VCCSM44
VTT3
1D5V_DLVDS_S0
12
12
C70
C70
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
12
12
C74
C74
SCD01U16V2KX-LGP
SCD01U16V2KX-LGP
12
12
C72
C72
SC4D7U10V5ZY
SC4D7U10V5ZY
FOR DDR2
1D8V_S3
TC7
TC7
ST100U4VBM-U
ST100U4VBM-U
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
AF13
AE13
AP12
AN12
AM12
AL12
AK12
AJ12
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
L11
T11
V11
P11
U11
R11
N11
M11
Note: All VCCSM
pins shorted
internally
C127
C127
1 2
AH12
AG12
AF12
AE12
AD11
AC11
VCCSM52
VCCSM53
VCCSM54
VCCSM55
VCCSM56
VCCSM57
VCCSM58
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
T10
K11
V10
U10
R10
W10
D
12
C310
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
12
C126
C126
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
12
C125
C125
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
2D5V_TXLVDS_S02D5V_ALVDS_S0
V1.8_DDR_CAP4
V1.8_DDR_CAP3
V1.8_DDR_CAP6
AB11
AB10
AB9
AP8
AM1
VCCSM59
VTT18
P10
VCCSM60
VTT19
N10
VCCSM61
VTT20
M10
VCCSM62
VTT21
K10
AE1
VCCSM63
VTT22
J10
AF20
B28
A28
A27
VCCSM64
VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2
VTT23Y9VTT24W9VTT25U9VTT26R9VTT27P9VTT28N9VTT29M9VTT30L9VTT31J9VTT32N8VTT33M8VTT34N7VTT35M7VTT36N6VTT37M6VTT38A6VTT39N5VTT40M5VTT41N4VTT42M4VTT43N3VTT44M3VTT45N2VTT46M2VTT47B2VTT48V1VTT49N1VTT50M1VTT51
C310
12
U37
VCC3G1
VCC3G2
R37
N37
VCC3G3
L37
VCC3G4
VCC3G5
12
J37
VCC3G6
C313
C313
AE37
W37
AP19
AF19
AF18
VCC3G0
VCCA_SM0
VCCA_SM1
VCCA_SM2
VCCA_SM3
G23
G23
1 2
12
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
Y29
VCCA_3GPLL0
GAP-CLOSE-PWR
GAP-CLOSE-PWR
C136
C136
ST100U6D3VBM-8GP
ST100U6D3VBM-8GP
C99
C99
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
C312
C312
2D5V_3GBG_S0 2D5V_S0
Y27
Y28
G37
F37
VSSA_3GBG
VCCA_3GBG
VCCA_3GPLL2
VCCA_3GPLL1
E
1D5V_S01D5V_DDRDLL_S0
G36
G36
1 2
12
GAP-CLOSE-PWR
GAP-CLOSE-PWR
TC15
TC15
ST100U6D3VBM-8GP
ST100U6D3VBM-8GP
1D5V_3GPLL_S0
12
12
C301
C301
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
G14
G14
1 2
12
C86
C86
GAP-CLOSE-PWR
GAP-CLOSE-PWR
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
U18E
U18E
71.0GMCH.0JU
71.0GMCH.0JU
G1
1D5V_S01D5V_PCIE_S0
SB
R610
R610
1 2
0R0603-PAD
0R0603-PAD
1D5V_S0
12
12
C311
C311
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
Supply Icc-max
1D8V_S3
1D5V_DDRDLL_S0 VCCA_SM 0.1A
1D5V_PCIE_S0
/1D5V_3GPLL_S0
2D5V_3GBG_S0 VCCA_3GBG 0.01A
1D5V_DLVDS_S0 VCCD_LVDS 0.05A
2D5V_ALVDS_S0 VCCA_LVDS 0.02A
2D5V_TXLVDS_S0 VCCTX_LVDS 0.05A
1 1
VCCP_GMCH_S0 VTT 0.81A
CORE_GMCH_S0
2D5V_CRTDAC_S0 VCCA_CRTDAC
3D3V_TVDAC
/3D3V_ATVBG_S0
1D5V_TVDAC_S0 VCCD_TVDAC 24mA
2D5V_TVDAC_S0
12
C297
C296
C296
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
C297
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
12
C300
C300
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
Signal Group
VCCSM ?
VCC3G/VCCA_3GPLL 1A
VCC
3.9A
68mA
VCCA_TVDAC
/VCCA_TVBG
120mA
VCCHV 0.01A
A
12
C299
C299
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
GAP-CLOSE-PWR
GAP-CLOSE-PWR
12
C298
C298
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
G32
G32
1D5V_S0
12
L5
L5
1 2
IND-D1UH-GP
IND-D1UH-GP
L14
L14
1 2
IND-D1UH-GP
IND-D1UH-GP
L7
L7
1 2
IND-D1UH-GP
IND-D1UH-GP
L6
L6
1 2
IND-D1UH-GP
IND-D1UH-GP
B
12
C69
C69
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
12
C278
C278
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
12
C111
C111
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
12
C110
C110
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
1D5V_HMPLL_S0
1D5V_DPLLA_S0
12
C68
C68
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
1D5V_DPLLB_S0
12
C288
C288
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
1D5V_HPLL_S0
12
C113
C113
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
1D5V_MPLL_S0
12
C114
C114
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
C
2D5V_CRTDAC
12
C277
C277
SC22U10V6ZY-2GP
SC22U10V6ZY-2GP
VCCP_GMCH_S0
12
C83
C83
12
C285
C285
SCD022U16V2KXLGP
SCD022U16V2KXLGP
12
C82
C82
ST100U6D3VBM-8GP
ST100U6D3VBM-8GP
R332
R332
1 2
0R0805-PAD
0R0805-PAD
12
C276
C276
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
12
C286
C286
SCD1U10V2KX-LGP
SCD1U10V2KX-LGP
2D5V_CRTDAC_S0
R333
R333
1 2
0R3-U-GP
0R3-U-GP
DY
DY
R334
R334
1 2
10R2J-2-GP
10R2J-2-GP
Route VSSA_CRTDAC gnd from GMCH to
decoupling cap ground lead and then
connect to the gnd plane.
Layout Notes: VSSA_CRTDAC
Route caps within 250mil
of Alviso. Route FB
within 3" of Alviso.
12
C96
C96
SC10U10V6ZY-U
SC10U10V6ZY-U
D
SCD47U10V3KX-LGP
SCD47U10V3KX-LGP
2D5V_S0
VCCP_GMCH_D
2 1
SSM5818SLPT-GP
SSM5818SLPT-GP
VCCP_GMCH_CAP2
VCCP_GMCH_CAP1
12
12
C61
C61
C62
C62
VCCP_GMCH_S0
D22
D22
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet of
VCCP_GMCH_CAP3
12
VCCP_GMCH_S0
SCD47U10V3KX-LGP
SCD47U10V3KX-LGP
12
C295
C295
GMCH (4 of 5)
GMCH (4 of 5)
GMCH (4 of 5)
KeyWest
KeyWest
KeyWest
VCCP_GMCH_CAP4
C97
C97
12
SCD22U16V3ZY-GP
SCD22U16V3ZY-GP
C84
C84
SCD22U16V3ZY-GP
SCD22U16V3ZY-GP
12
C294
C294
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
937Tuesday, August 16, 2005
937Tuesday, August 16, 2005
937Tuesday, August 16, 2005
of
E
of
SD
SD
SD
A
G21
G21
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
G20
G20
B27
E27
VSS261
VSS260L2VSS268J2VSS269G2VSS270D2VSS271
W27
G27
VSS128
VSS129
VSS259P2VSS258T2VSS257V2VSS256
AB27
AA27
VSS125
VSS126
VSS127
VSS255
AE2
AD2
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
G19
G19
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
AN27
AL27
AJ27
AG27
AF27
VSS121
VSS122
VSS123
VSS124
VSS254
VSS253
VSS252
VSS251A3VSS250C3VSS249
AL2
AH2
AN2
P29
L29
H29
G29
F29
E29
D29
A29
AC28
AB28
AA28
W28
E28
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS248
VSS247
VSS246
AA3
AB3
AC3
VSS245C4VSS244H4VSS243L4VSS242P4VSS241U4VSS240Y4VSS239
AJ3
AF4
VSS238
AN4
CORE_GMCH_S0 1D05V_S0 VCCP_GMCH_S0 1D05V_S0
4 4
J26
G26
E26
A26
AN24
U18F
U18F
3 3
AL24
VSS266
VSS267
VSSALVDS
B36
71.0GMCH.0JU
71.0GMCH.0JU
VSS262
VSS263
VSS264
VSS265
Y1
U29
VSS107
VSS237E5VSS236W5VSS235
V29
VSS106
AL5
AA29
W29
VSS104
VSS105
VSS234
AP5
B
AM29
AJ29
AG29
AD29
VSS100
VSS101
VSS102
VSS103
VSS233B6VSS232J6VSS231L6VSS230P6VSS229T6VSS228
C
G16
G16
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
G15
G15
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
G17
G17
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
AB34
AA34
C34
AL33
AF33
AD33
W33
V33
U33
T33
R33
P33
N33
M33
L33
K33
J33
H33
G33
F33
E33
D33
AN32
AJ32
AD32
AC32
AB32
AA32
Y32
C32
A32
AL31
AG31
AD31
W31
V31
U31
T31
R31
P31
N31
M31
L31
K31
J31
H31
G31
F31
E31
D31
AP30
AE30
AC30
AB30
AA30
Y30
C30
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS
VSS
VSS196
VSS195
VSS194
VSS193
VSS192
VSS191
VSS190
VSS189
VSS188
VSS187
VSS186
VSS185
VSS184
VSS183
VSS182
VSS181
VSS180
VSS179
VSS178
VSS177
VSS176
VSS175
VSS174
VSS173
K15
A16
K16
C15
D16
H16
AN14
AA6
VSS227
VSS226
VSS225
VSS224G7VSS223V7VSS222
VSS221
VSS220
VSS219
VSS218C8VSS217E8VSS216L8VSS215P8VSS214Y8VSS213
AJ6
AE6
AA7
AC6
AK7
AN7
AG7
VSS212A9VSS211H9VSS210K9VSS209T9VSS208V9VSS207
AL8
AA9
VSS206
VSS205
VSS204
VSS203
VSS202
VSS201
VSS200
VSS199
VSS198
VSS197
J12
L10
F11
Y11
Y10
D10
AE9
AC9
AH9
AN9
H11
AA11
AA10
B12
AJ11
AL11
AF11
AN11
AG11
D12
J14
F14
A14
B14
K14
AJ14
AL14
AG14
D
AL36
AJ36
AF36
AE36
AD36
AC36
AB36
AA36
C36
AE35
Y35
W35
V35
U35
T35
R35
P35
N35
M35
L35
K35
J35
H35
G35
F35
E35
D35
B35
AN34
AH34
AD34
AC34
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS172
VSS171
VSS170
VSS169
VSS168
VSS167
VSS166
VSS165
VSS164
VSS163
VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS150
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
J19
U18
T19
C19
H19
W19
AL18
A18
G17
B18
AJ17
AF17
AN17
C17
AL16
F20
G20
F21
V20
C21
AK20
A20
E20
D20
AN19
AG19
J22
A22
E22
D22
AF21
AN21
AN36
AH22
E37
VSS9
VSS139
AL22
H37
VSS8
VSS138
H23
K37
VSS7
VSS137
AF23
M37
VSS6
VSS136
B24
CORE_GMCH_S06,9,37
VCCP_GMCH_S02,4,5,6,7,9,15,17,19,32,37
VSS5
VSS135
P37
D24
E
T37
VSS4
VSS134
F24
1D05V_S034,35,36,37
V37
VSS3
VSS133
J24
1D8V_S37,9,11,12,16,34,35,36,37
Y37
VSS2
VSS132
AG24
AG37
VSS1
VSS131
AJ24
CORE_GMCH_S0
VCCP_GMCH_S0
1D8V_S3
1D05V_S0
VSS0
VSS130
VCC_NCTF6
VSS_NCTF6
P26
VCC_NCTF5
VSS_NCTF5
Y25
R26
AA25
VCC_NCTF4
VSS_NCTF4
T26
VCC_NCTF3
VSS_NCTF3
AB25
CORE_GMCH_S0
W26
V26
U26
VCC_NCTF0
VCC_NCTF1
VCC_NCTF2
VSS_NCTF2
VSS_NCTF1
VSS_NCTF0
Y26
AA26
AB26
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
GMCH (5 of 5)
GMCH (5 of 5)
GMCH (5 of 5)
KeyWest
KeyWest
KeyWest
10 37Tuesday, August 16, 2005
10 37Tuesday, August 16, 2005
10 37Tuesday, August 16, 2005
E
SD
SD
of
of
SD
AD14
AC14
AD13
VCCSM_NCTF24
VCCSM_NCTF25
VCCSM_NCTF26
VCCSM_NCTF27
VCCP_GMCH_S0
FOR DDR2
AC18
AD17
AC17
AD16
AC16
AD15
AC15
VCCSM_NCTF17
VCCSM_NCTF18
VCCSM_NCTF19
VCCSM_NCTF20
VCCSM_NCTF21
VCCSM_NCTF22
VCCSM_NCTF23
AD18
VCCSM_NCTF13
VCCSM_NCTF14
VCCSM_NCTF15
VCCSM_NCTF16
AD23
AC23
AD22
AC22
VCCSM_NCTF7
VCCSM_NCTF8
VCCSM_NCTF9
VCCSM_NCTF10
VCCSM_NCTF11
VCCSM_NCTF12
VTT_NCTF17
VTT_NCTF16
VTT_NCTF15
VTT_NCTF14
VTT_NCTF13
L12
T12
P12
N12
R12
M12
B
VCCSM_NCTF6
VTT_NCTF12
AC24
U12
VCCSM_NCTF5
VTT_NCTF11
AD24
V12
AC25
VCCSM_NCTF4
VTT_NCTF10
W12
VCCSM_NCTF3
VTT_NCTF9
AD26
AC26
AD25
VCCSM_NCTF1
VCCSM_NCTF2
VTT_NCTF8
VTT_NCTF7
L13
N13
M13
VCCSM_NCTF0
VTT_NCTF6
T17
P17
N17
M17
L17
VCC_NCTF75
VCC_NCTF76
VCC_NCTF77
VCC_NCTF78
VTT_NCTF5
VTT_NCTF4
VTT_NCTF3
VTT_NCTF2
VTT_NCTF1
T13
P13
V13
R13
U13
W13
VCC_NCTF74
VTT_NCTF0
U17
N18
L18
W17
V17
M18
VCC_NTTF69
VCC_NCTF68
VCC_NCTF70
VCC_NCTF71
VCC_NCTF72
VCC_NCTF73
VSS_NCTF68
Y12
P19
N19
M19
L19
Y18
R18
P18
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VCC_NCTF65
VCC_NCTF66
VCC_NCTF67
VSS_NCTF67
VSS_NCTF66
VSS_NCTF65
VSS_NCTF64
VSS_NCTF63
VSS_NCTF62
L14
Y13
P14
N14
M14
AA12
AA13
P20
N20
M20
L20
Y19
R19
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
NCTF
NCTF
VSS_NCTF61
VSS_NCTF60
VSS_NCTF59
VSS_NCTF58
VSS_NCTF57
VSS_NCTF56
T14
V14
Y14
R14
U14
W14
P21
N21
M21
L21
Y20
R20
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VSS_NCTF55
VSS_NCTF54
VSS_NCTF53
L15
AA14
AB14
C
V21
U21
T21
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF47
VCC_NCTF48
VSS_NCTF52
VSS_NCTF51
VSS_NCTF50
VSS_NCTF49
VSS_NCTF48
VSS_NCTF47
T15
P15
N15
R15
U15
M15
R22
P22
N22
M22
L22
W21
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VSS_NCTF46
VSS_NCTF45
VSS_NCTF44
VSS_NCTF43
VSS_NCTF42
VSS_NCTF41
L16
V15
Y15
W15
AA15
AB15
M23
L23
W22
V22
U22
T22
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VSS_NCTF40
VSS_NCTF39
VSS_NCTF38
VSS_NCTF37
VSS_NCTF36
VSS_NCTF35
T16
P16
N16
R16
U16
M16
V23
U23
T23
R23
P23
N23
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VSS_NCTF34
VSS_NCTF33
VSS_NCTF32
VSS_NCTF31
VSS_NCTF30
VSS_NCTF29
V16
Y16
R17
W16
AA16
AB16
R24
P24
N24
M24
L24
W23
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VSS_NCTF28
VSS_NCTF27
VSS_NCTF26
VSS_NCTF25
VSS_NCTF24
VSS_NCTF23
Y17
AA17
AB17
AA18
AB18
AA19
M25
L25
W24
V24
U24
T24
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VSS_NCTF22
VSS_NCTF21
VSS_NCTF20
VSS_NCTF19
VSS_NCTF18
VSS_NCTF17
Y21
R21
AB19
AA20
AB20
AA21
D
V25
U25
T25
R25
P25
N25
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VSS_NCTF16
VSS_NCTF15
VSS_NCTF14
VSS_NCTF13
Y22
AB21
AA22
AB22
N26
M26
L26
W25
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VSS_NCTF12
VSS_NCTF11
VSS_NCTF10
VSS_NCTF9
VSS_NCTF8
VSS_NCTF7
Y23
Y24
AA23
AB23
AA24
AB24
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet of
AD21
AC21
AD20
AC20
AD19
AC19
1D8V_S3
AC13
AB13
AD12
AC12
U18H
U18H
2 2
1 1
A
AB12
VCCSM_NCTF29
VCCSM_NCTF30
VCCSM_NCTF31
71.0GMCH.0JU
71.0GMCH.0JU
VCCSM_NCTF28
DM2
M_B_A[13..0]8,12
M_B_BS2#8,12
M_B_BS0#8,12
M_B_BS1#8,12
M_B_DATA[63..0]8
M_B_DQS#[7..0]8
M_B_DQS[7..0]8
M_ODT27,12
M_ODT37,12
C362
C362
SCD1U16V
SCD1U16V
12
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_DATA0
M_B_DATA1
M_B_DATA2
M_B_DATA3
M_B_DATA4
M_B_DATA5
M_B_DATA6
M_B_DATA7
M_B_DATA8
M_B_DATA9
M_B_DATA10
M_B_DATA11
M_B_DATA12
M_B_DATA13
M_B_DATA14
M_B_DATA15
M_B_DATA16
M_B_DATA17
M_B_DATA18
M_B_DATA19
M_B_DATA20
M_B_DATA21
M_B_DATA22
M_B_DATA23
M_B_DATA24
M_B_DATA25
M_B_DATA26
M_B_DATA27
M_B_DATA28
M_B_DATA29
M_B_DATA30
M_B_DATA31
M_B_DATA32
M_B_DATA33
M_B_DATA34
M_B_DATA35
M_B_DATA36
M_B_DATA37
M_B_DATA38
M_B_DATA39
M_B_DATA40
M_B_DATA41
M_B_DATA42
M_B_DATA43
M_B_DATA44
M_B_DATA45
M_B_DATA46
M_B_DATA47
M_B_DATA48
M_B_DATA49
M_B_DATA50
M_B_DATA51
M_B_DATA52
M_B_DATA53
M_B_DATA54
M_B_DATA55
M_B_DATA56
M_B_DATA57
M_B_DATA58
M_B_DATA59
M_B_DATA60
M_B_DATA61
M_B_DATA62
M_B_DATA63
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
12
C361
C361
SC2D2U6D3V3MXLGP
SC2D2U6D3V3MXLGP
DM2
102
A0
101
A1
100
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
105
A10/AP
90
A11
89
A12
116
A13
86
A14
84
A15
85
A16/BA2
107
BA0
106
BA1
5
DQ0
7
DQ1
17
DQ2
19
DQ3
4
DQ4
6
DQ5
14
DQ6
16
DQ7
23
DQ8
25
DQ9
35
DQ10
37
DQ11
20
DQ12
22
DQ13
36
DQ14
38
DQ15
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194
11
29
49
68
129
146
167
186
13
31
51
70
131
148
169
188
114
119
1
2
202
62.10017.A51 62.10017.A41
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
/DQS0
/DQS1
/DQS2
/DQS3
/DQS4
/DQS5
/DQS6
/DQS7
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
ODT0
ODT1
VREF
VSS
GND
DDR2-200P-4
DDR2-200P-4
NC#163/TEST
High 9.2mm
Hi 9.2 mm
108
/RAS
109
/WE
113
/CAS
110
/CS0
115
/CS1
79
CKE0
80
CKE1
30
CK0
32
/CK0
164
CK1
166
/CK1
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
SDA
SCL
VDDSPD
SA0
SA1
NC#50
NC#69
NC#83
NC#120
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NORMAL TYPE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GND
M_B_SDM0
10
M_B_SDM1
26
M_B_SDM2
52
M_B_SDM3
67
M_B_SDM4
130
M_B_SDM5
147
M_B_SDM6
170
M_B_SDM7
185
195
197
199
R139 10KR2J-2-GPR139 10KR2J-2-GP
198
1 2
R138 10KR2J-2-GPR138 10KR2J-2-GP
200
1 2
50
69
83
120
163
81
82
87
88
95
96
103
104
111
112
117
118
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196
201
1D8V_S3
M_B_RAS# 8,12
M_B_WE# 8,12
M_B_CAS# 8,12
M_CS2_R# 7,12
M_CS3_R# 7,12
M_CKE2_R# 7,12
M_CKE3_R# 7,12
CLK_DDR3 7
CLK_DDR3# 7
CLK_DDR4 7
CLK_DDR4# 7
M_B_SDM[7..0] 8
SMBD_ICH 3,18
SMBC_ICH 3,18
3D3V_S0
C359
C359
SCD1U16V
SCD1U16V
12
SB
SUPPORT DDRII 400
1st source:62.10017.A51
3D3V_S0
12
C360
C360
SC2D2U6D3V3MXLGP
SC2D2U6D3V3MXLGP
M_A_A[13..0]8,12
M_A_BS2#8,12
M_A_BS0#8,12
M_A_BS1#8,12
M_A_DATA[63..0]8
M_A_DQS#[7..0]8
M_A_DQS[7..0]8
M_ODT07,12
DDR_VREF_S3DDR_VREF_S3
M_ODT17,12
C170
C170
SCD1U16V
SCD1U16V
12
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_DATA0
M_A_DATA1
M_A_DATA2
M_A_DATA3
M_A_DATA4
M_A_DATA5
M_A_DATA6
M_A_DATA7
M_A_DATA8
M_A_DATA9
M_A_DATA10
M_A_DATA11
M_A_DATA12
M_A_DATA13
M_A_DATA14
M_A_DATA15
M_A_DATA16
M_A_DATA17
M_A_DATA18
M_A_DATA19
M_A_DATA20
M_A_DATA21
M_A_DATA22
M_A_DATA23
M_A_DATA24
M_A_DATA25
M_A_DATA26
M_A_DATA27
M_A_DATA28
M_A_DATA29
M_A_DATA30
M_A_DATA31
M_A_DATA32
M_A_DATA33
M_A_DATA34
M_A_DATA35
M_A_DATA36
M_A_DATA37
M_A_DATA38
M_A_DATA39
M_A_DATA40
M_A_DATA41
M_A_DATA42
M_A_DATA43
M_A_DATA44
M_A_DATA45
M_A_DATA46
M_A_DATA47
M_A_DATA48
M_A_DATA49
M_A_DATA50
M_A_DATA51
M_A_DATA52
M_A_DATA53
M_A_DATA54
M_A_DATA55
M_A_DATA56
M_A_DATA57
M_A_DATA58
M_A_DATA59
M_A_DATA60
M_A_DATA61
M_A_DATA62
M_A_DATA63
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
12
C169
C169
SC2D2U6D3V3MXLGP
SC2D2U6D3V3MXLGP
2nd source:62.10017.A61
DM1
DM1
102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
85
107
106
5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194
11
29
49
68
129
146
167
186
13
31
51
70
131
148
169
188
114
119
1
2
202
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2
BA0
BA1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
/DQS0
/DQS1
/DQS2
/DQS3
/DQS4
/DQS5
/DQS6
/DQS7
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
ODT0
ODT1
VREF
VSS
GND
DDR2-200P-5
DDR2-200P-5
NC#163/TEST
108
/RAS
109
/WE
113
/CAS
110
/CS0
115
/CS1
79
CKE0
80
CKE1
30
CK0
32
/CK0
164
CK1
166
/CK1
10
DM0
26
DM1
52
DM2
67
DM3
130
DM4
147
DM5
170
DM6
185
DM7
195
SDA
197
SCL
199
VDDSPD
NC#50
NC#69
NC#83
NC#120
Low5.2 mm
R116 10KR2J-2-GPR116 10KR2J-2-GP
198
SA0
R115 10KR2J-2-GPR115 10KR2J-2-GP
200
SA1
50
69
83
120
163
81
VDD
82
VDD
87
VDD
88
VDD
95
VDD
96
VDD
103
VDD
104
VDD
111
VDD
112
VDD
117
VDD
118
VDD
3
VSS
8
VSS
9
VSS
12
VSS
15
VSS
18
VSS
21
VSS
24
VSS
27
VSS
28
VSS
33
VSS
34
VSS
39
VSS
40
VSS
41
VSS
42
VSS
47
VSS
48
VSS
53
VSS
54
VSS
59
VSS
60
VSS
65
NORMAL TYPE
VSS
66
VSS
71
VSS
72
VSS
77
VSS
78
VSS
121
VSS
122
VSS
127
VSS
128
VSS
132
VSS
133
VSS
138
VSS
139
VSS
144
VSS
145
VSS
149
VSS
150
VSS
155
VSS
156
VSS
161
VSS
162
VSS
165
VSS
168
VSS
171
VSS
172
VSS
177
VSS
178
VSS
183
VSS
184
VSS
187
VSS
190
VSS
193
VSS
196
VSS
201
GND
1st source:62.10017.A41
2nd source:62.10017.661
M_A_RAS# 8,12
M_A_WE# 8,12
M_A_CAS# 8,12
M_CS0_R# 7,12
M_CS1_R# 7,12
M_CKE0_R# 7,12
M_CKE1_R# 7,12
CLK_DDR0 7
CLK_DDR0# 7
CLK_DDR1 7
CLK_DDR1# 7
M_A_SDM0
M_A_SDM1
M_A_SDM2
M_A_SDM3
M_A_SDM4
M_A_SDM5
M_A_SDM6
M_A_SDM7
SMBD_ICH
SMBC_ICH
1 2
1 2
1D8V_S3
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
M_A_SDM[7..0] 8
SB
C163
C163
SCD1U16V
SCD1U16V
DDR Socket
DDR Socket
DDR Socket
KeyWest
KeyWest
KeyWest
1D8V_S37,9,10,12,16,34,35,36,37
DDR_VREF_S37,35
3D3V_S03,4,5,7,9,13,15,16,17,18,19,20,23,24,25,27,29,32,34,36,37
12
12
C164
C164
SC2D2U6D3V3MXLGP
SC2D2U6D3V3MXLGP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
3D3V_S0
11 37Tuesday, August 16, 2005
11 37Tuesday, August 16, 2005
11 37Tuesday, August 16, 2005
DDR_VREF_S3
of
of
of
1D8V_S3
3D3V_S0
SD
SD
SD
1D8V_S3
PLACE CAPS BETWEEN AND NEAR DDR SKTS
PLACE EACH 0.1UF CAP CLOSE TO POWER
PIN
12
12
12
C152
C152
SCD1U16V
SCD1U16V
C167
C167
SCD1U16V
SCD1U16V
C176
C176
SCD1U16V
SCD1U16V
12
12
12
C150
C150
SCD1U16V
SCD1U16V
C179
C179
SCD1U16V
SCD1U16V
C153
C153
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
12
12
C151
C151
SCD1U16V
SCD1U16V
C180
C180
SCD1U16V
SCD1U16V
12
C185
C185
SC10U6D3V5MXL1GP
SC10U6D3V5MXL1GP
12
12
C149
C149
SCD1U16V
SCD1U16V
C165
C165
SCD1U16V
SCD1U16V
12
12
12
C183
C183
SCD1U16V
SCD1U16V
C184
C184
SCD1U16V
SCD1U16V
EC30
EC30
SCD1U16V
SCD1U16V
12
12
12
C178
C178
SCD1U16V
SCD1U16V
C182
C182
SCD1U16V
SCD1U16V
EC38
EC38
SCD1U16V
SCD1U16V
12
12
12
C168
C168
SCD1U16V
SCD1U16V
C181
C181
SCD1U16V
SCD1U16V
EC23
EC23
SCD1U16V
SCD1U16V
12
12
12
C166
C166
SCD1U16V
SCD1U16V
C177
C177
SCD1U16V
SCD1U16V
EC24
EC24
SCD1U16V
SCD1U16V
Address / Command/Control
M_A_A18,11
M_A_A08,11
M_A_A38,11
M_A_A108,11
M_B_CAS#8,11
M_B_RAS#8,11
M_B_WE#8,11
M_CS3_R#7,11
M_A_A78,11
M_A_A68,11
M_A_A48,11
M_A_A28,11
M_B_BS0#8,11
M_B_A28,11
M_B_A108,11
M_B_A48,11
M_CKE2_R#7,11
M_B_A58,11
M_B_A118,11
M_B_A68,11
M_A_BS1#8,11
M_A_RAS#8,11
M_CS0_R#7,11
M_A_A138,11
M_B_BS2#8,11
M_B_A128,11
M_CKE3_R#7,11
M_B_A78,11
M_CS2_R#7,11
M_B_A138,11
M_B_A08,11
M_B_BS1#8,11
M_A_WE#8,11
M_A_BS0#8,11
M_A_CAS#8,11
M_CS1_R#7,11
M_B_A38,11
M_B_A18,11
M_B_A98,11
M_B_A88,11
1
2 3
1
2 3
1
2 3
1
2 3
1
2 3
1
2 3
1
2 3
1
2 3
1
2 3
1
2 3
1
2 3
1
2 3
1
2 3
1
2 3
1
2 3
1
2 3
1
2 3
1
2 3
1
2 3
1
2 3
RN32
RN32
4
SRN56J-4-GP
SRN56J-4-GP
RN34
RN34
4
SRN56J-4-GP
SRN56J-4-GP
RN5
RN5
4
SRN56J-4-GP
SRN56J-4-GP
RN7
RN7
4
SRN56J-4-GP
SRN56J-4-GP
RN35
RN35
4
SRN56J-4-GP
SRN56J-4-GP
RN33
RN33
4
SRN56J-4-GP
SRN56J-4-GP
RN8
RN8
4
SRN56J-4-GP
SRN56J-4-GP
RN9
RN9
4
SRN56J-4-GP
SRN56J-4-GP
RN13
RN13
4
SRN56J-4-GP
SRN56J-4-GP
RN14
RN14
4
SRN56J-4-GP
SRN56J-4-GP
RN30
RN30
4
SRN56J-4-GP
SRN56J-4-GP
RN28
RN28
4
SRN56J-4-GP
SRN56J-4-GP
RN12
RN12
4
SRN56J-4-GP
SRN56J-4-GP
RN15
RN15
4
SRN56J-4-GP
SRN56J-4-GP
RN4
RN4
4
SRN56J-4-GP
SRN56J-4-GP
RN6
RN6
4
SRN56J-4-GP
SRN56J-4-GP
RN31
RN31
4
SRN56J-4-GP
SRN56J-4-GP
RN29
RN29
4
SRN56J-4-GP
SRN56J-4-GP
RN10
RN10
4
SRN56J-4-GP
SRN56J-4-GP
RN11
RN11
4
SRN56J-4-GP
SRN56J-4-GP
0D9V_S0
0D9V_S0
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
C198
C198
SCD1U16V
SCD1U16V
C197
C197
SCD1U16V
SCD1U16V
C196
C196
SCD1U16V
SCD1U16V
C195
C195
SCD1U16V
SCD1U16V
C191
C191
SCD1U16V
SCD1U16V
C194
C194
SCD1U16V
SCD1U16V
C193
C193
SCD1U16V
SCD1U16V
C192
C192
SCD1U16V
SCD1U16V
C199
C199
SCD1U16V
SCD1U16V
C200
C200
SCD1U16V
SCD1U16V
C333
C333
SCD1U16V
SCD1U16V
C334
C334
SCD1U16V
SCD1U16V
C335
C335
SCD1U16V
SCD1U16V
C336
C336
SCD1U16V
SCD1U16V
C337
C337
SCD1U16V
SCD1U16V
C338
C338
SCD1U16V
SCD1U16V
C339
C339
SCD1U16V
SCD1U16V
C340
C340
SCD1U16V
SCD1U16V
C201
C201
SCD1U16V
SCD1U16V
C202
C202
SCD1U16V
SCD1U16V
0D9V_S0
0D9V_S035,36
1D8V_S3
1D8V_S37,9,10,11,16,34,35,36,37
C330
RN39
M_CKE0_R#7,11
M_A_BS2#8,11
M_A_A128,11
M_A_A98,11
M_CKE1_R#7,11
M_A_A118,11
M_A_A88,11
M_A_A58,11
M_ODT07,11
M_ODT17,11
M_ODT27,11
M_ODT37,11
1
2 3
1
2 3
1
2 3
1
2 3
R402 56R2J-4-GPR402 56R2J-4-GP
1 2
R401 56R2J-4-GPR401 56R2J-4-GP
1 2
R140 56R2J-4-GPR140 56R2J-4-GP
1 2
R141 56R2J-4-GPR141 56R2J-4-GP
1 2
RN39
4
SRN56J-4-GP
SRN56J-4-GP
RN38
RN38
4
SRN56J-4-GP
SRN56J-4-GP
RN36
RN36
4
SRN56J-4-GP
SRN56J-4-GP
RN37
RN37
4
SRN56J-4-GP
SRN56J-4-GP
0D9V_S0
1 2
1 2
1 2
1 2
C330
SCD1U16V
SCD1U16V
C331
C331
SCD1U16V
SCD1U16V
C332
C332
SCD1U16V
SCD1U16V
C329
C329
SCD1U16V
SCD1U16V
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
DDR Serial/Terminator Resistor
DDR Serial/Terminator Resistor
DDR Serial/Terminator Resistor
KeyWest
KeyWest
KeyWest
12 37Tuesday, August 16, 2005
12 37Tuesday, August 16, 2005
12 37Tuesday, August 16, 2005
of
of
of
SD
SD
SD
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