Dell ALIENWARE 13 Schematics
A
B
C
D
E
MODEL NAME : ZAP00
PROJECT CODE : ANRZAP0000
1 1
PCB NO : DA8000WL000 LA-A301P M/B
DA4001XN000 LS-A301P LOGO/B
DA4001XO000 LS-A302P IND/B
DA4001XP000 LS-A303P BTN/B
DA4001XQ000 LS-A304P NGFF/B
FPC NO : LF-A301P HEAD/B
LF-A302P SLIT_R/B
LF-A303P SLIT_L/B
LF-A304P KB/B
Compal Confidential
2 2
Schematic Document
Crescent Bay Platform
Intel Broadwell ULT
2014-09-23 Rev: 1.0
3 3
X76@ : 76 level
46@ : 46 level
@ : Nopop component
CONN@ : Connector component
XDP@ : XDP function
EMI@ : EMI parts
@EMI@ : Reserve EMI parts
ESD@ : ESD parts
@ESD@ : Reserve ESD parts
RF@ : RF parts
BDWI5@ : CPU BDW I5
H@:Haswell
4 4
B@:Broadwell
sualaptop365.edu.vn
A
B
DAX
PCB
DAZ16C00100
R1@
DAX
PCB
DAZ16C00101
R3@
C
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2013/09/09 2014/09/09
2013/09/09 2014/09/09
2013/09/09 2014/09/09
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Title
Title
Title
Cover page
Cover page
Cover page
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
LA-A301P
LA-A301P
LA-A301P
Date: Sheet of
Date: Sheet of
Date: Sheet of
E
1 56Thursday, September 25, 2014
1 56Thursday, September 25, 2014
1 56Thursday, September 25, 2014
1.0
1.0
1.0
A
B
C
D
E
eDP
P.19
eDP 1.3
panel
1 1
HDMI
P.21
connector
P.20
mini DP
PS8407A
re-driver
P.21
HDMI 1.4a (DDI1)
DP 1.2 (DDI2)
P.06~16
FFS
P.36 P.40 P.06
LNG3DMTR
Memory Bus Dual Channel
1.35V,DDR3L,1600 MHz
Fan control
NCT7718W
W83L771AWG-2
204pin SO-DIMM x2
XDP connector
P.17,18
connector
USB3.0 port2
P.22~29
dGPU
nVIDIA
N15P-GX,50W
4pcs GDDR5
PCI-E x4
PCIE MUX
PERICOM
P.34
PCI-E(GEN2)x4
port5(L0~L3)
Crescent Bay Platform
Broadwell ULT
PI3PCIE3415
2 2
Video
docking
P.34
PCI-E x4
CDR_I2C
USB3.0 port4
USB2.0 port3
Broadwell U Processor
+
Wildcat Point-LP PCH
NGFF (M.2)WLAN+BT
P.32
QCA killer 1525(E Key)
RJ45
connector
3 3
LAN(Gigabit)
Killer E2201
P.30P.30
PCI-E2.0 port3
USB2.0 port7
PCI-E2.0 port4
15W , BGA 1168 balls
USB2.0 port1
USB3.0 port2
USB2.0 port0
USB3.0 port3
USB2.0 port2
USB2.0 port4
USB2.0 port5
USB2.0 port6
CDR_I2C
SATA3.0 port0 ; option1
SATA3.0 port0 ; option2
SATA3.0 port1 ; option2
USB connector 1 , Right side
USB power share
USB connector 2 , Left side 1
USB connector 3 , Left side 2
Touch screen
Digital camera(with digital MIC)
AlienFX / ELC , C8051F383-GQ
ELC PWM expander , TLC59116F
2.5”HDD or SSD
Dual 2280 M.2 SATA support via
a 7mm drive caddy(with redriver IC)
P.38,39
P.38,39
LED SET
P.33
P.33
P.33
P.19
P.19
P.37
P.36
P.36
P.31
SPI ROM
P.09
8MB
DC in
1.05V
Battery
3V/5V
System
4 4
1.35V
1.5V
CPU
Vcore
A
dGPU
Core
Charger
dGPU
1.35V
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SPI
Int. KBD
ENE KC3810
B
P.41
P.41
LPC Bus
ENE KB9022
P.41
HD Audio
I2C(400KHz)
PS2
C
Touch pad
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRAN SFERED FROM THE CUSTODY OF T HE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEIT HER THIS SHEET NOR THE I NFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEIT HER THIS SHEET NOR THE I NFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEIT HER THIS SHEET NOR THE I NFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTR ONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTR ONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTR ONICS, INC.
P.38
2013/09/09 2014/09/09
2013/09/09 2014/09/09
2013/09/09 2014/09/09
Audio codec
Realtek
ALC3234
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
digital MIC
Speaker
Headphone/MIC Global headset
combo JACK
Headphone/MIC Retaskable
combo JACK
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Block diagram
Block diagram
Block diagram
LA-A301P
LA-A301P
LA-A301P
E
P.31
P.31
P.31
1.0
1.0
2 56Friday, September 19, 2014
2 56Friday, September 19, 2014
2 56Friday, September 19, 2014
1.0
A
Board ID Table for AD channel
Vcc 3.3V +/- 1%
Board ID
10
11
12
13
14
15 330K +/- 1%
16
17
18
19 NC
100K +/- 1%Ra
Rb V min
0
1
2
3
4
5
6
0 0.000V
12K +/- 1%
15K +/- 1%
20K +/- 1%
27K +/- 1%
33K +/- 1%
43K +/- 1%
7 56K +/- 1%
8
75K +/- 1% 1.398V
9
100K +/- 1%
160K +/- 1%
200K +/- 1%
240K +/- 1%
270K +/- 1%
430K +/- 1%
560K +/- 1%
750K +/- 1%
AD_BID
V typ
AD_BID
0.000V 0.300V
0.347V
0.354V
0.423V 0.430V
0.541V
0.691V
0.807V
0.550V
0.702V
0.819V
0.978V 0.992V
1.169V
1.185V
1.414V 1.430V
1.634V
1.650V
1.849V 1.865V
2.015V
2.185V
2.316V
2.031V
2.200V
2.329V
2.395V 2.408V
2.521V
2.667V
2.791V
2.533V
2.677V 0xCA - 0xD3
2.800V
2.905V 2.912V
3.300V
V
AD_BID
0.360V
0.438V
0.559V
0.713V
0.831V
1.006V
1.200V
1.667V
1.881V130K +/- 1%
2.046V
2.215V
2.343V
2.421V
2.544V
2.687V
2.808V
2.919V
3.300V
max
EC AD3
0x00 - 0x0B
0x0C - 0x1C
0x1D - 0x26
0x27 - 0x30
0x31 - 0x3B
0x3C - 0x46
0x47 - 0x54
0x55 - 0x64
0x65 - 0x76
0x77 - 0x87
0x88 - 0x96
0x97 - 0xA3
0xA4 - 0xAD
0xAE - 0xB7
0xB8 - 0xC0
0xC1 - 0xC9
0xD4 - 0xDC
0xDD - 0xE6
0xE7 - 0xFF3.000V
NVIDIA
Graphic
AMD
Graphic
ULT
1 1
Board ID table and PCB version
Rb
ID
0
1
2
3
4
5 33K
6 43K
HSW(Haswell)
0
EVT-1(R0.1) , EVT-2(R0.1)
12K
EVT-3(R0.2)
15K
DVT-1(R0.3) , DVT1.1(R0.4)
20K
DVT-2(R0.5)
27K
Not use
Pilot(R1.0) Pilot(R1.0)
BDW(Broadwell)
EVT-1(R0.1)
EVT-2(R0.2)
DVT-1(R0.5)
Not use
DVT-1.1(N16P,R0.6)
DVT-2(R1.0)Not use
Port1
Port2
Port3
Port4
Port0
Port1
Port2
Port3
Port4
Port5
Port6
Port7
Lane 1
Lane 2
Lane 3
Lane 4
USB3.0
Left side 1
Right side (power share)
Left side 2
Caldera
USB2.0
Left side 1
Right side (power share)
Left side 2
Caldera
Touch screen
Camera
ELC
BT
PCI EXPRESS
WLAN(M.2 Card)
10/100/1000 LAN
Symbol Note :
: means Digital Ground
: means Analog Ground
sualaptop365.edu.vn
CLOCK SIGNAL
CLKOUT_PCIE0
CLKOUT_PCIE1
CLKOUT_PCIE2
CLKOUT_PCIE3
CLKOUT_PCIE4
CLKOUT_PCIE5
Lane 5
PCIE 4x MUX
Lane 6
SATA
M.2 Card WLAN
10/100/1000 LAN
N15P-GX , Video docking
SATA1
SATA2
HDD or NGFF SSD1SATA0
NGFF SSD2
SATA3
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
2013/09/09 2014/09/09
2013/09/09 2014/09/09
2013/09/09 2014/09/09
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Notes list
Notes list
Notes list
LA-A301P
LA-A301P
LA-A301P
4 56Friday, September 19, 2014
4 56Friday, September 19, 2014
4 56Friday, September 19, 2014
1.0
1.0
1.0
5
4
3
2
1
D D
C C
SMBUS Address [0x90]
ULT
Broadwell
AP2
AH1
AN1
AK1
AU3
AH3
79
80
MEM_SMBCLK
MEM_SMBDATA
SML0CLK
SML0DATA
SML1_SMBCLK
EC_SMB_CK2
EC_SMB_DA2
2.2K
2.2K
1K
1K
2.2K
2.2K
2.2K
2.2K
+3.3V_ALW_PCH
N-MOS
N-MOS
+3.3V_ALW_PCH
+3.3V_ALW_PCH
N-MOS
N-MOS
+3VALW_EC
EC_SMB_CK2
EC_SMB_DA2SML1_SMBDATA
10K
10K
+3VS
DDR_XDP_WLAN_TP_SMBCLK
DDR_XDP_WLAN_TP_SMBDAT
N-MOS
N-MOS
UF1,FAN8
7
SMBUS Address [0x98]
0 ohm
0 ohm
1.8K
1.8K
+3VS_VGA
VGA_SMB_CK2
VGA_SMB_DA2T4T3
DDR_XDP_SMBCLK_R1
DDR_XDP_SMBDAT_R1
UV1
GPU
SMBUS Address [0x9E]
202
200
202
200
DIMMA
DIMMB
XDP
53
51
FFS
4
6
SMBUS Address [A0]
SMBUS Address [A4]
SMBUS Address [TBD]
SMBUS Address [TBD]
KBC
B B
KB9012A4
77
78
EC_SMB_CK1
EC_SMB_DA1
2.2K
2.2K
+3VALW_EC
UF2,FAN8
7
0 ohm
0 ohm
SMBUS Address [0x9A]
SCL
SDA
PU700
12
Charger
11
SMBUS Address [0x12]
100 ohm
100 ohm
I2C switch
CLK_SMB
DAT_SMB
CDR_I2C_CLK 7
CDR_I2C_DAT
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
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4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2013/09/09 2014/09/09
2013/09/09 2014/09/09
2013/09/09 2014/09/09
PBATT1
7
6
Video
docking
6
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
SMBUS Address [0x16]
SMBUS Address [TBD]
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
SMBus block diagram
SMBus block diagram
SMBus block diagram
LA-A301P
LA-A301P
LA-A301P
1
5 56Friday, September 19, 2014
5 56Friday, September 19, 2014
5 56Friday, September 19, 2014
1.0
1.0
1.0
5
UC1
UC1
UC1
4
3
2
1
S IC CL8064701477802 SR1EF D0 1.7G A31!
SA00007LO2L
R1HSWI5@
UC1
S IC CL8064701477802 SR1EF D0 1.7G A31!
SA00007LO1L
D D
R3HSWI5@
PCH_JTAG_TDO<8>
C C
PCH_JTAG_TDI<8>
PCH_JTAG_TMS<8>
RUNPWROK
@ESD@
CC5
0.1U_0402_10V7K
Place CC5
close to UC4
+1.05VS
RC16 49.9_0402_1%@
RC18 62_0402_5%
B B
A A
DDR3 COMPENSATION SIGNALS
CAD Note:
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mil
S IC A31 FH8065801620203 QH17 E0 2G
SA00008991L
R1BDWI5@
UC1
S IC A31 FH8065801620203 QH17 E0 2G
SA00008992L
R3BDWI5@
1 2
TDI_XDP TDI_XDP_R
@
RC4 0_0402_1%
1
2
1 2
1 2
5
H_CATERR#
H_PROCHOT#
12
RC25
10K_0402_5%
RUNPWROK<41>
S IC A31 FH8065801620004 QH3E F0 2.4G
SA000089A1L
R1BDWI7@
UC1
S IC A31 FH8065801620004 QH3E F0 2.4G
SA000089A2L
R3BDWI7@
HDMI
mini DP
+3VS
CC1
12
0.1U_0402_10V7K
1 2
TDO_XDP
@
RC3 0_0402_1%
RUNPWROK
1 2
@
RC5 0_0402_1%
RUNPWROK
1 2
TMS_XDP
@
RC6 0_0402_1%
RUNPWROK
TRST#_XDP XDP_TRST#
RUNPWROK
PCH_JTAG_JTAGX<8>
PCH_JTAG_TCK<8>
H_CPUPWRGD
1
CC8
100P_0402_50V8J
ESD@
2
12
SM_RCOMP0
RC29200_0402_1%
12
SM_RCOMP1
RC30120_0402_1%
12
SM_RCOMP2
RC31100_0402_1%
@
UC3
14
VCC
2
1A
1
1OE
5
2A
4
2OE
9
3A
10
3OE
12
4A
13
4OE
74CBTLV3126BQ_DHVQFN14_2P5X3
PCH_JTAG_RST#
PCH_JTAG_TDO TDI_XDP_R
PCH_JTAG_TCK
H_PROCHOT#<41,47,48>
sualaptop365.edu.vn
DDR3_DRAMRST#_CPU<17,18>
@
1 2
@
DDR_PG_CTRL<17>
Place CC9
on BOT
DDI1_LANE_N0<21>
DDI1_LANE_P0<21>
DDI1_LANE_N1<21>
DDI1_LANE_P1<21>
DDI1_LANE_N2<21>
DDI1_LANE_P2<21>
DDI1_LANE_N3<21>
DDI1_LANE_P3<21>
DDI2_LANE_N0<20>
DDI2_LANE_P0<20>
DDI2_LANE_N1<20>
DDI2_LANE_P1<20>
DDI2_LANE_N2<20>
DDI2_LANE_P2<20>
DDI2_LANE_N3<20>
DDI2_LANE_P3<20>
3
XDP_TDOPCH_JTAG_TDO
1B
6
XDP_TDI
2B
8
XDP_TMS
3B
11
4B
7
GND
15
GND PAD
12
XDP_TRST#
RC170_0402_1%
XDP_TCLK
RC190_0402_1%
12
TDO_XDP
RC200_0402_5% XDP@
12
RC230_0402_5% XDP@
12
XDP_TCLK
RC240_0402_5% XDP@
H_CATERR#
1 2
@ESD@
CC9
0.047U_0402_16V4Z
PECI_EC
H_PROCHOT#_R
H_CPUPWRGD
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
PECI_EC<41>
RC26 56_0402_5%
DDR3_DRAMRST#_CPU
4
CC3
XDP@
RC7 1K_0402_5%XDP@
RC9 0_0402_5%XDP @
RC11 0_0402_5%XDP@
RC12 0_0402_5%XDP@
PCH_JTAG_TCK
3
HASWELL_MCP_E
C45
EDP_TXN0
B46
EDP_TXP0
A47
EDP_TXN1
B47
EDP_TXP1
C47
EDP_TXN2
C46
EDP_TXP2
A49
DDI EDP
1 OF 19
1 2
1 2
1 2
1 2
1 8
2 7
3 6
4 5
RPC1
0_8P4R_5%
XDP@
J62
PRDY
K62
PREQ
E60
PROC_TCK
E61
PROC_TMS
E59
PROC_TRST
F63
PROC_TDI
F62
PROC_TDO
J60
BPM#0
H60
BPM#1
H61
BPM#2
H62
BPM#3
K59
BPM#4
H63
BPM#5
K60
BPM#6
J61
BPM#7
Rev1p2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EDP_TXN3
B49
EDP_TXP3
A45
EDP_AUXN
B45
EDP_AUXP
D20
Rev1p2
CFG0
CFG1
CFG2
CFG4
CFG5
CFG6
CFG7
RC28 0_0402_1%@
T1@
T2@
T3@
T4@
T5@
T6@
EDP_COMP
A43
EDP_DISP_UTIL
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
1 2
@
RC27
0_0402_5%
1 2
Compal Secret Data
Compal Secret Data
Compal Secret Data
JXDP
GND0
OBSFN_A0
OBSFN_A1
GND2
OBSDATA_A0
OBSDATA_A1
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGOOD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16
SAMTE_BSH-030-01-L-D-A
CONN@
EDP_RCOMP
EDP_DISP_UTIL
XDP_PREQ#
XDP_PRDY#
CFG0<16>
CFG1<16>
CFG2<16>
CFG3<16>
XDP_OBS0_R
XDP_OBS1_R
CFG4<16>
CFG5<16>
CFG6<16>
CFG7<16>
CFD_PWRBTN#_XDP
CPU_PWR_DEBUG#_R PLT_RST#
SYS_PWROK_XDP
DDR_XDP_SMBDAT_R1
DDR_XDP_SMBCLK_R1
XDP_TCLK
+3VALW_PCH
@
RC21
1K_0402_5%
1 2
SYS_PWROK_XDP
1
@ESD@
CC7
0.1U_0402_10V7K
2
Place near JXDP pin47
XDP_PRDY#
XDP_PREQ#
XDP_TCK
XDP_TMS
XDP_TRST#
XDP_TDI
XDP_TDO
XDP_OBS0_R
XDP_OBS1_R
2013/09/09 2014/09/09
2013/09/09 2014/09/09
2013/09/09 2014/09/09
1 2
@
RC1
0_0402_5%
PCH_JTAG_RST#
Deciphered Date
Deciphered Date
Deciphered Date
2
EDP_TX0# <19>
EDP_TX0 <19>
EDP_TX1# <19>
EDP_TX1 <19>
EDP_TX2# <19>
EDP_TX2 <19>
EDP_TX3# <19>
EDP_TX3 <19>
EDP_AUX# <19>
EDP_AUX <19>
OBSFN_C0
OBSFN_C1
OBSDATA_C0
OBSDATA_C1
OBSDATA_C2
OBSDATA_C3
OBSFN_D0
OBSFN_D1
OBSDATA_D0
OBSDATA_D1
OBSDATA_D2
OBSDATA_D3
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
XDP_DBRESET#
EDP_BIA_PWM <10,19>
+1.05VS+1.05VS
2
GND1
4
6
8
GND3
10
12
14
GND5
16
18
20
GND7
22
24
26
GND9
28
30
32
GND11
34
36
38
GND13
40
42
44
46
48
50
GND15
52
TD0
54
TRST#
56
TDI
58
TMS
60
GND17
1 2
RC22
0_0402_1%
PCH_JTAG_RST# <8>
TDO_XDP
TRST#_XDP
TDI_XDP
TMS_XDP
CFG3_R
@
+VCCIOA_OUT
12
RC224.9_0402_1%~D
COMPENSATION PU FOR eDP
CAD Note:
Trace width=20mils
Spacing=25mils
Max length=100mils
CFG17
CFG16
CFG8
CFG9
CFG10
CFG11CFG3
CFG19
CFG18
CFG12
CFG13
CFG14
CFG15
CLK_XDP
CLK_XDP#
XDP_RST#_R
XDP_DBRESET#
RC8 0_0402_5%XDP@
RC10 0_0402_5%XDP@
SYS_RESET#
1 2
1 2
RC13
1K_0402_5%
XDP@
1 2
RC15
1K_0402_5%
XDP@
CFG17 <16>
CFG16 <16>
CFG8 <16>
CFG9 <16>
CFG10 <16>
CFG11 <16>
CFG19 <16>
CFG18 <16>
CFG12 <16>
CFG13 <16>
CFG14 <16>
CFG15 <16>
12
CFG3
SYS_RESET# <10>
RC14
1K_0402_1%
1 2
12
CC6
0.1U_0402_10V7K
PLT_RST#
ESD@
CC4
0.047U_0402_16V4Z
Place CC4
close to RC13.1
PU/PD for JTAG signals
@
XDP_TMS
XDP_TDI
XDP_PREQ#
TDO_XDP
XDP_TDO
XDP_TCK
XDP_TRST#
Title
Title
Title
Size Docum ent Number Rev
Size Docum ent Number Rev
Size Docum ent Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
1 8
2 7
3 6
4 5
RPC2
51_8P4R_5%
@
1 8
2 7
3 6
4 5
RPC3
51_8P4R_5%
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
MCP(1,2/19) eDP,XDP,MISC
MCP(1,2/19) eDP,XDP,MISC
MCP(1,2/19) eDP,XDP,MISC
LA-A301P
LA-A301P
LA-A301P
1
1
2
CLK_CPU_ITP <9>
CLK_CPU_ITP# <9>
PLT_RST# <10,30,32,41>
+3VS
+1.05VS
6 56Wednesday, Septem ber 24, 2014
6 56Wednesday, Septem ber 24, 2014
6 56Wednesday, Septem ber 24, 2014
1.0
1.0
1.0
UC1A
+1.05VS
C54
DDI1_TXN0
C55
DDI1_TXP0
B58
DDI1_TXN1
C58
DDI1_TXP1
B55
DDI1_TXN2
A55
DDI1_TXP2
A57
DDI1_TXN3
B57
DDI1_TXP3
C51
DDI2_TXN0
C50
DDI2_TXP0
C53
DDI2_TXN1
B54
DDI2_TXP1
C49
DDI2_TXN2
B50
DDI2_TXP2
A53
DDI2_TXN3
B53
DDI2_TXP3
@
0.1U_0402_10V7K
0.1U_0402_10V7K
1
1
CC2
XDP@
2
2
DDI1_LANE_N0
DDI1_LANE_P0
DDI1_LANE_N1
DDI1_LANE_P1
DDI1_LANE_N2
DDI1_LANE_P2
DDI1_LANE_N3
DDI1_LANE_P3
DDI2_LANE_N0
DDI2_LANE_P0
DDI2_LANE_N1
DDI2_LANE_P1
DDI2_LANE_N2
DDI2_LANE_P2
DDI2_LANE_N3
DDI2_LANE_P3
Place near JXDP
PBTN_OUT#<10,41>
CPU_PWR_DEBUG#<13>
SYS_PWROK<10,41>
DDR_XDP_WLAN_TP_SMBDAT<9,17,18,36>
DDR_XDP_WLAN_TP_SMBCLK<9,17,18,36>
UC1B
D61
PROC_DETECT
K61
CATERR
N62
PECI
K63
PROCHOT
C61
PROCPWRGD
AU60
SM_RCOMP0
AV60
SM_RCOMP1
AU61
SM_RCOMP2
AV15
SM_DRAMRST
AV61
SM_PG_CNTL1
1
2
H_CPUPWRGD H_VCCST_PWRGD_XDP
SYS_PWROK
HASWELL_MCP_E
MISC
JTAG
THERMAL
PWR
DDR3
2 OF 19
5
4
3
2
1
Non-Interleaved memory
HASWELL_MCP_E
DDR CHANNEL B
SB_CK#0
SB_CK0
SB_CK#1
SB_CK1
SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3
SB_CS#0
SB_CS#1
SB_ODT0
SB_RAS
SB_WE
SB_CAS
SB_BA0
SB_BA1
SB_BA2
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7
SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7
AM38
AN38
AK38
AL38
AY49
AU50
AW49
AV50
AM32
AK32
AL32
AM35
AK35
AM33
AL35
AM36
AU49
AP40
AR40
AP42
AR42
AR45
AP45
AW46
AY46
AY47
AU46
AK36
AV47
AU47
AK33
AR46
AP46
AW30
AV26
AN28
AN25
AW22
AV18
AN21
AN18
AV30
AW26
AM28
AM25
AV22
AW18
AM21
AM18
M_CLK_DDR#2
M_CLK_DDR2
M_CLK_DDR#3
M_CLK_DDR3
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
DDR_B_RAS#
DDR_B_WE#
DDR_B_CAS#
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
M_CLK_DDR#2 <18>
M_CLK_DDR2 <18>
M_CLK_DDR#3 <18>
M_CLK_DDR3 <18>
DDR_CKE2_DIMMB <18>
DDR_CKE3_DIMMB <18>
DDR_CS2_DIMMB# <18>
DDR_CS3_DIMMB# <18>
DDR_B_RAS# <18>
DDR_B_WE# <18>
DDR_B_CAS# <18>
DDR_B_BS0 <18>
DDR_B_BS1 <18>
DDR_B_BS2 <18>
DDR_B_DQS#[0..7] <18>
DDR_B_DQS[0..7] <18>
AY31
AW31
AY29
AW29
AV31
AU31
AV29
AU29
AY27
AW27
AY25
AW25
AV27
AU27
AV25
AU25
AM29
AK29
AL28
AK28
AR29
AN29
AR28
AP28
AN26
AR26
AR25
AP25
AK26
AM26
AK25
AL25
AY23
AW23
AY21
AW21
AV23
AU23
AV21
AU21
AY19
AW19
AY17
AW17
AV19
AU19
AV17
AU17
AR21
AR22
AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18
AL18
AK20
AM20
AR18
AP18
UC1D
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
HASWELL_MCP_E
DDR CHANNEL A
SA_CLK#0
SA_CLK0
SA_CLK#1
SA_CLK1
SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3
SA_CS#0
SA_CS#1
SA_ODT0
SA_RAS
SA_WE
SA_CAS
SA_BA0
SA_BA1
SA_BA2
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7
SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7
SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1
AU37
AV37
AW36
AY36
AU43
AW43
AY42
AY43
AP33
AR32
AP32
AY34
AW34
AU34
AU35
AV35
AY41
AU36
AY37
AR38
AP36
AU39
AR36
AV40
AW39
AY39
AU40
AP35
AW41
AU41
AR35
AV42
AU42
AJ61
AN62
AM58
AM55
AV57
AV53
AL43
AL48
AJ62
AN61
AN58
AN55
AW57
AW53
AL42
AL49
AP49
AR51
AP51
M_CLK_DDR#0
M_CLK_DDR0
M_CLK_DDR#1
M_CLK_DDR1
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_A_RAS#
DDR_A_WE#
DDR_A_CAS#
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
M_CLK_DDR#0 <17>
M_CLK_DDR0 <17>
M_CLK_DDR#1 <17>
M_CLK_DDR1 <17>
DDR_CKE0_DIMMA <17>
DDR_CKE1_DIMMA <17>
DDR_CS0_DIMMA# <17>
DDR_CS1_DIMMA# <17>
DDR_A_RAS# <17>
DDR_A_WE# <17>
DDR_A_CAS# <17>
DDR_A_BS0 <17>
DDR_A_BS1 <17>
DDR_A_BS2 <17>
DDR_A_MA[0..15] <17> DDR_B_MA[0..15] <18>
DDR_A_DQS#[0..7] <17>
DDR_A_DQS[0..7] <17>
+SM_VREF_CA
+SM_VREF_DQ0
+SM_VREF_DQ1
DDR_B_D[0..15]<18>
DDR_B_D[16..31]<18>
DDR_B_D[32..47]<18>
DDR_B_D[48..63]<18>
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
AH63
AH62
AK63
AK62
AH61
AH60
AK61
AK60
AM63
AM62
AP63
AP62
AM61
AM60
AP61
AP60
AP58
AR58
AM57
AK57
AL58
AK58
AR57
AN57
AP55
AR55
AM54
AK54
AL55
AK55
AR54
AN54
AY58
AW58
AY56
AW56
AV58
AU58
AV56
AU56
AY54
AW54
AY52
AW52
AV54
AU54
AV52
AU52
AK40
AK42
AM43
AM45
AK45
AK43
AM40
AM42
AM46
AK46
AM49
AK49
AM48
AK48
AM51
AK51
UC1C
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
D D
C C
DDR_A_D[0..15]<17>
DDR_A_D[16..31]<17>
DDR_A_D[32..47]<17>
DDR_A_D[48..63]<17>
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
B B
1
CC12
0.022U_0402_16V7K
2
12
RC41
24.9_0402_1%~D
Rev1p2
+1.35V
12
RC33
1.82K_0402_1%
12
RC39
1.82K_0402_1%
1 2
RC36
2.2_0402_1%
1
CC10
0.022U_0402_16V7K
2
12
RC42
24.9_0402_1%~D
3
+1.35V
12
RC34
+SM_VREF_DQ0_DIMM1+SM_VREF_CA_DIMM +SM_VREF_DQ1_DIMM2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1.82K_0402_1%
1 2
RC37
2.2_0402_1%
12
RC40
1.82K_0402_1%
2013/09/09 2014/09/09
2013/09/09 2014/09/09
2013/09/09 2014/09/09
+SM_VREF_DQ0
Compal Secret Data
Compal Secret Data
Compal Secret Data
3 OF 19
+1.35V
12
RC32
1.82K_0402_1%
12
RC38
1.82K_0402_1%
A A
+SM_VREF_CA +SM_VREF_DQ1
1 2
RC35
2.2_0402_1%
sualaptop365.edu.vn
5
4
1
CC11
0.022U_0402_16V7K
2
12
RC43
24.9_0402_1%~D
Deciphered Date
Deciphered Date
Deciphered Date
2
4 OF 19
Rev1p2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
MCP(3,4/19) DDR3L
MCP(3,4/19) DDR3L
MCP(3,4/19) DDR3L
LA-A301P
LA-A301P
LA-A301P
1
1.0
1.0
7 56Friday, September 19, 2014
7 56Friday, September 19, 2014
7 56Friday, September 19, 2014
1.0
5
4
3
2
1
D D
JP1
2
+RTC_CELL
CC14
1 2
15P_0402_50V8J
CC15
15P_0402_50V8J
2
2
1U_0402_6.3V6K
1 2
1 2
RC50 1M_0402_5%
C C
+RTCVCC
1 2
1 2
RC49 20K_0402_5%
RC51 20K_0402_5%
1
1
@
CMOS1 SHORT PADS~D
1 2
CC17
12
32.768KHZ_12.5PF_1TJF125DP1A000D
2
CC16
1U_0402_6.3V6K
1
PCH_AZ_CODEC_SDIN0<31>
YC1
ME_EN<41>
CMOS place near DIMM connector
Shunt
Open
Shunt
Open
B B
+1.05VS
RC56 1K_0402_1%@
RC57 51_0402_1%@
+1.05VS
1 8
2 7
3 6
4 5
RPC5
51_8P4R_5%
12
12
CMOS settingCMOS_CLR1
Clear CMOS
Keep CMOS
TPM settingME_CLR1
Clear ME RTC Registers
Keep ME RTC Registers
PCH_JTAG_JTAGX
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
112
JUMP_43X39
1 2
RC52 1K_0402_5%
PCH_JTAG_RST#<6>
PCH_JTAG_TCK<6>
PCH_JTAG_TDI<6>
PCH_JTAG_TDO<6>
PCH_JTAG_TMS<6>
PCH_JTAG_JTAGX<6>
12
+RTCVCC
PCH_RTCX1
RC48
10M_0402_5%
PCH_RTCX2
INTRUDER#
PCH_INTVRMEN
SRTCRST#
PCH_RTCRST#
PCH_AZ_BITCLK
PCH_AZ_SYNC
PCH_AZ_RST#
PCH_AZ_CODEC_SDIN0
PCH_AZ_SDOUT
PCH_JTAG_RST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_JTAG_JTAGX
UC1E
AW5
RTCX1
AY5
RTCX2
AU6
INTRUDER
AV7
INTVRMEN
AV6
SRTCRST
AU7
RTCRST
AW8
HDA_BCLK/I2S0_SCLK
AV11
HDA_SYNC/I2S0_SFRM
AU8
HDA_RST/I2S_MCLK
AY10
HDA_SDI0/I2S0_RXD
AU12
HDA_SDI1/I2S1_RXD
AU11
HDA_SDO/I2S0_TXD
AW10
HDA_DOCK_EN/I2S1_TXD
AV10
HDA_DOCK_RST/I2S1_SFRM
AY8
I2S1_SCLK
AU62
PCH_TRST
AE62
PCH_TCK
AD61
PCH_TDI
AE61
PCH_TDO
AD62
PCH_TMS
AL11
RSVD
AC4
RSVD
AE63
JTAGX
AV2
RSVD
HASWELL_MCP_E
SATAAUDIO
SATA_RN0/PERN6_L3
SATA_RP0/PERP6_L3
SATA_TN0/PETN6_L3
SATA_TP0/PETP6_L3
SATA_RN1/PERN6_L2
SATA_RP1/PERP6_L2
SATA_TN1/PETN6_L2
SATA_TP1/PETP6_L2
SATA_RN2/PERN6_L1
SATA_RP2/PERP6_L1
SATA_TN2/PETN6_L1
SATA_TP2/PETP6_L1
SATA_RN3/PERN6_L0
SATA_RP3/PERP6_L0
SATA_TN3/PETN6_L0
SATA_TP3/PETP6_L0
RTC
JTAG
5 OF 19
HDA for Codec
1 2
@EMI@
1
CC18
27P_0402_50V8J
2
RC58 33_0402_5%EMI@
1 2
RC59 33_0402_5%EMI@
1 2
RC60 33_0402_5%EMI@
1 2
RC61 33_0402_5%EMI@
PCH_AZ_CODEC_SDOUT<31>
PCH_AZ_CODEC_SYNC<31>
PCH_AZ_CODEC_RST#<31>
PCH_AZ_CODEC_BITCLK<31>
+RTCVCC
12
RC44
330K_0402_1%
PCH_INTVRMEN
INTVRMEN - INTEGRATED SUS 1.05V VRM ENABLE
High - Enable Internal VRs
Low - Enable External VRs
SATA0GP/GPIO34
SATA1GP/GPIO35
SATA2GP/GPIO36
SATA3GP/GPIO37
SATA_IREF
RSVD
RSVD
SATA_RCOMP
SATALED
Rev1p2
J5
H5
B15
A15
J8
H8
A17
B17
J6
H6
B14
C15
F5
E5
C17
D17
V1
EC_SMI#
U1
PCH_GPIO35
V6
PCH_GPIO36
AC1
PCH_GPIO37
A12
SATA_IREF
L11
K10
C12
SATA_RCOMP
U3
SATALED#
PCH_AZ_SDOUT
PCH_AZ_SYNC
PCH_AZ_RST#
PCH_AZ_BITCLK
SATA_PRX_DTX_N0 <36>
SATA_PRX_DTX_P0 <36>
SATA_PTX_DRX_N0 <36>
SATA_PTX_DRX_P0 <36>
SATA_PRX_DTX_N1 <36>
SATA_PRX_DTX_P1 <36>
SATA_PTX_DRX_N1 <36>
SATA_PTX_DRX_P1 <36>
1 2
RC53
10K_0402_5%
1 2
RC54 0_0603_1%@
1 2
RC55 3.01K_0402_1%
SATALED# <38>
PCH_GPIO36
PCH_GPIO35
PCH_GPIO37
+3VS
12
@
RC46
1K_0402_5%
PCH_AZ_SDOUT
FLASH DESCRIPTOR SECURITY OVERRIDE
LOW = DESABLED (DEFAULT)
HIGH = ENABLED
SATA HDD or NGFF SSD1
NGFF SSD2
+3VS
EC_SMI# <41>
+1.05VS_ASATA3PLL
SATA Impedance Compensation
CAD note:
Place the resistor within 500 mils of the PCH. Avoid
routing next to clock pins.
reference FFRD schematics 0.5
+3VS
1 8
2 7
3 6
4 5
RPC4
10K_8P4R_5%
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
sualaptop365.edu.vn
5
4
3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2013/09/09 2014/09/09
2013/09/09 2014/09/09
2013/09/09 2014/09/09
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
MCP(5/19) RTC,SATA,HDA,JTAG
MCP(5/19) RTC,SATA,HDA,JTAG
MCP(5/19) RTC,SATA,HDA,JTAG
LA-A301P
LA-A301P
LA-A301P
1
8 56Friday, September 19, 2014
8 56Friday, September 19, 2014
8 56Friday, September 19, 2014
1.0
1.0
1.0
5
4
3
2
1
+3VALW_PCH
D D
UC1G
+3VS
PCH_SPI_HOLD1#
PCH_SPI_CLK_R
PCH_SPI_MOSI_1
AU14
AW12
AY12
AW11
AV12
AA3
Y7
Y4
AC2
AA2
AA4
Y6
AF1
CC20
0.1U_0402_10V7K
1 2
LAD0
LAD1
LAD2
LAD3
LFRAME
SPI_CLK
SPI_CS0
SPI_CS1
SPI_CS2
SPI_MOSI
SPI_MISO
SPI_IO2
SPI_IO3
DI(IO0)
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LFRAME#
PCH_SPI_CLKPCH_SPI_CLK_R
PCH_SPI_CS0#
PCH_SPI_MOSI
PCH_SPI_MISO
PCH_SPI_WP#
PCH_SPI_HOLD#
8
VCC
7
6
CLK
5
LPC_LAD0<41>
LPC_LAD1<41>
LPC_LAD2<41>
LPC_LAD3<41>
LPC_LFRAME#<41>
EMI@
RC66
1 2
15_0402_1%
RPC6
1 8
2 7
3 6
4 5
15_8P4R_5%
UC4
1
CS#
2
DO(IO1)
HOLD#(IO3)
3
WP#(IO2)
4
GND
64M EN25QH64-104HIP SOP 8P
+3VS
1
2
PCH_SPI_HOLD1#
PCH_SPI_MISO_1
PCH_SPI_WP1#
PCH_SPI_MOSI_1
1 2
RC67 1K_0402_1%
1 2
RC68 1K_0402_1%
PCH_SPI_CS0#
PCH_SPI_MISO_1
PCH_SPI_WP1#
@EMI@
CC19
68P_0402_50V8J
C C
HASWELL_MCP_E
LPC
SPI C-LINK
SMBUS
7 OF 19
SMBALERT/GPIO11
SMBCLK
SMBDATA
SML0ALERT/GPIO60
SML0CLK
SML1ALERT/PCHHOT/GPIO73
SML0DATA
SML1CLK/GPIO75
SML1DATA/GPIO74
CL_CLK
CL_DATA
CL_RST
Rev1p2
SML0DATA<34>
SML0CLK<34>
AN2
PCH_SMB_ALERT#
AP2
MEM_SMBCLK
AH1
MEM_SMBDATA
AL2
AN1
SML0CLK
AK1
SML0DATA
AU4
PCH_HOT#
AU3
SML1_SMBCLK
AH3
SML1_SMBDATA
AF2
AD2
AF4
SML1_SMBCLK
SML1_SMBDATA
MEM_SMBCLK
MEM_SMBDATA
SML0DATA
SML0CLK
10K_0402_5%
T7@
T8@
T9@
RPC7
1 8
2 7
3 6
4 5
2.2K_0804_8P4R_5%
1 8
2 7
3 6
4 5
RPC8
1K_0804_8P4R_5%
@
RC62
12
12
RC63
10K_0402_5%
+3VALW_PCH
MEM_SMBCLKLPC_LAD3
MEM_SMBDATA
MEM Bus : DDR/XDP/WLAN/TP
+3VS
+3VS
2
G
6 1
D
5
DMN66D0LDW-7_SOT363-6
3 4
SGD
QC1A
DMN66D0LDW-7_SOT363-6
RC64
10K_0402_5%
S
QC1B
12
12
RC65
10K_0402_5%
SML1 Bus : EC/Sensors
+3VALW_PCH
2
QC2B
G
SML1_SMBCLK
SML1_SMBDATA
DMN66D0LDW-7_SOT363-6
61
S
D
DMN66D0LDW-7_SOT363-6
QC2A
5
34
SGD
DDR_XDP_WLAN_TP_SMBCLK <6,17,18,36>
DDR_XDP_WLAN_TP_SMBDAT <6,17,18,36>
EC_SMB_CK2 <22,40,41>
EC_SMB_DA2 <22,40,41>
CC21
15P_0402_50V8J
CC22
15P_0402_50V8J
+1.05VS_AXCK_LCPLL
12
RC7122_0402_5% EMI@
12
12
CLK_PCI_LPC <41>
CLK_CPU_ITP# <6>
CLK_CPU_ITP <6>
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
MCP(6,7/19) CLK,SMB,SPI,LPC
MCP(6,7/19) CLK,SMB,SPI,LPC
MCP(6,7/19) CLK,SMB,SPI,LPC
LA-A301P
LA-A301P
LA-A301P
1
1.0
1.0
9 56Friday, September 19, 2014
9 56Friday, September 19, 2014
9 56Friday, September 19, 2014
1.0
1 2
1 2
1 2
1 2
2
1M_0402_5%
RC69
1 2
RC70
3.01K_0402_1%
1 2
3
4
YC2
24MHZ_12PF_X3G024000DC1H
1
2
B B
UC1F
C43
CLKOUT_PCIE_N0
C42
CLKOUT_PCIE_P0
U2
PCIECLKRQ0/GPIO18
B41
CLKOUT_PCIE_N1
A41
CLKOUT_PCIE_P1
Y5
PCIECLKRQ1/GPIO19
CLK_PCIE_WLAN#<32>
WLAN(M2 card)
10/100/1000 LAN
GPU (N15P-GX and Caldera)
DII-DMN65D8LW-7~D
1 3
D
CLKREQ#_WLAN<32>
A A
CLKREQ#_WLAN WLAN_CLKREQ#_R
S
QC3
G
2
+3VS
CLK_PCIE_WLAN<32>
WLAN_CLKREQ#_R<11>
CLK_PCIE_LAN#<30>
CLK_PCIE_LAN<30>
CLKREQ#_LAN<30>
CLK_PEG_GPU#<34>
CLK_PEG_GPU<34>
CLKREQ#_GPU<22,34>
+3VS
WLAN_CLKREQ#_R
RPC10
1 8
2 7
3 6
4 5
10K_8P4R_5%
C41
CLKOUT_PCIE_N2
B42
CLKOUT_PCIE_P2
AD1
PCIECLKRQ2/GPIO20
B38
CLKOUT_PCIE_N3
C37
CLKOUT_PCIE_P3
N1
PCIECLKRQ3/GPIO21
A39
CLKOUT_PCIE_N4
B39
CLKOUT_PCIE_P4
U5
PCIECLKRQ4/GPIO22
B37
CLKOUT_PCIE_N5
A37
CLKOUT_PCIE_P5
T2
PCIECLKRQ5/GPIO23
sualaptop365.edu.vn
5
4
3
HASWELL_MCP_E
A25
RSVD
RSVD
Rev1p2
B25
K21
M21
C26
C35
C34
AK8
AL8
AN15
AP15
B35
A35
XTAL24_IN
XTAL24_OUT
CLK_BIASREF
RC157 10K_0402_5%
RC158 10K_0402_5%
RC159 10K_0402_5%
RC160 10K_0402_5%
CLKOUT_LPC0
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
XTAL24_IN
XTAL24_OUT
DIFFCLK_BIASREF
CLOCK
SIGNALS
6 OF 19
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
TESTLOW_C35
TESTLOW_C34
TESTLOW_AK8
TESTLOW_AL8
CLKOUT_LPC_0
CLKOUT_LPC_1
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
2013/09/09 2014/09/09
2013/09/09 2014/09/09
2013/09/09 2014/09/09
5
D D
C C
+3VALW_PCH
+3V_DSW
1 2
RC72 10K_0402_5%
1 2
RC73 10K_0402_5%@
1 2
RC74 10K_0402_5%@
1 2
RC77 8.2K_0402_5%
1 2
RC79 10K_0402_5%
1 2
RC80 1K_0402_5%
1 2
RC161 10K_0402_5%
+3VS
1 2
RC81 8.2K_0402_5%
SYS_PWROK
@ESD@
CC25
0.047U_0402_16V4Z
ME_SUS_PWR_ACK
SUSACK#
SUS_STAT#/LPCPD#
PCH_BATLOW#
AC_PRESENT
PCIE_WAKE#_R
PCH_SLP_WLAN#
CLKRUN#
1
2
Note: SUSACK# and SUSWARN# can be tied together if
EC does not want to involve in the handshake mechanism
for the deep sleep state entry and exit can be NC ,if not support deep Sx
SYS_PWROK<6,41>
PCH_PWROK<41>
Place CC25 on BOT
PCH_PWROK
@ESD@
CC26
0.047U_0402_16V4Z
1
2
PCH_BATLOW# need pull high to VCCDSW3_3
(If no deep Sx , connect to VCCSUS3_3)
Place CC26
close to RP50.2&RP50.3
+3VS
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
GPIO77
PCH_TP_INT#
EDP_BIA_PWM
PRODUCT_ID1
DGPU_HOLD_RST#
FFS_INT1
ENVDD_PCH
PRODUCT_ID1
TP_INT#<38,41>
RC88 10K_0402_5%
RC90 10K_0402_5%
B B
RC91 10K_0402_5%@
RC96 10K_0402_5%H@
RC93 10K_0402_5%@
RC94 10K_0402_5%
RC95 100K_0402_5%@
RC97 10K_0402_5%B@
4
PCH_DPWROK
ME_SUS_PWR_ACK_R SUSACK#
1 2
RC75 0_0402_5%@
1 2
RC76 0_0402_5%@
PCH_RSMRST#_R
3
Place CC23
close to UC5.1 &
UC5.2
PCH_PLTRST#<22,34>
PCH_PLTRST#
ESD@
CC23
0.047U_0402_16V4Z
1
2
+3VS
5
1
IN1
2
IN2
3
2
CC24
@
1 2
0.1U_0402_10V7K
VCC
4
PLT_RST#
OUT
GND
UC5
MC74VHC1G08DFT2G_SC70-5
12
RC78
100K_0402_5%
1
PLT_RST# <6,30,32,41>
DPWROK: Tired toghter with RSMRST#
that do not support Deep Sx
DSWODVREN - On Die DSW VR Enable
DPWROK
WAKE
SLP_S4
SLP_S3
SLP_A
SLP_SUS
SLP_LAN
Rev1p2
Rev1p2
AW7
AV5
AJ5
V5
AG4
AE6
AP5
AJ6
AT4
AL5
AP4
AJ7
B9
C9
D9
D11
C5
B6
B5
A6
C8
A8
D6
HIGH = ENABLED (DEFAULT)
LOW = DISABLED
DSWODVREN
PCH_DPWROK
CLKRUN#
SUS_STAT#/LPCPD#
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_S3#
CPU_DPB_CTRLCLK
CPU_DPB_CTRLDAT
CPU_DPC_CTRLCLK
CPU_DPC_CTRLDAT
CPU_DPB_AUX#
CPU_DPC_AUX#
CPU_DPB_AUX
CPU_DPC_AUX
DPB_HPD
DPC_HPD
CPU_EDP_HPD#
100K_0402_5%
1 2
RC82 330K_0402_5%
1 2
@
RC85
0_0402_5%
T12@
T14@
CPU_DPB_CTRLCLK <21>
CPU_DPB_CTRLDAT <21>
CPU_DPC_CTRLCLK <20>
CPU_DPC_CTRLDAT <20>
CPU_DPC_AUX# <20>
CPU_DPC_AUX <20>
12
RC99
PCIE_WAKE#PCIE_WAKE#_R
SUSCLK <32>
SIO_SLP_S5# <37>
SIO_SLP_S4# <37,41>
SIO_SLP_S3# <37,41>
SLP_SUS# <41>
RC98
100K_0402_5%
1 2
+RTCVCC
PCH_DPWROK <41>
PCIE_WAKE# <30,41>
DPB_HPD <21>
DPC_HPD <20>
CPU_EDP_HPD# <19>
CPU_DPB_CTRLCLK
CPU_DPB_CTRLDAT
CPU_DPC_CTRLCLK
CPU_DPC_CTRLDAT
CPU_DPB_AUX#
CPU_DPB_AUX
1 8
2 7
3 6
4 5
RPC12
2.2K_8P4R_5%
1 8
2 7
3 6
4 5
RPC13
100K_8P4R_5%
+3VS
UC1H
SUSACK#<41>
ME_SUS_PWR_ACK<41>
SUSACK#
SYS_PWROK
EC_RSMRST#<41>
PBTN_OUT#<6,41>
ACIN<22,37,41,47,48>
SIO_SLP_S0#<41>
EDP_BIA_PWM<6,19>
PANEL_BKLEN<41>
+3VS
1 3
D
QC4
2N7002K_SOT23-3
1 2
RC100
0_0402_5%
@
1 2
RC84 0_0402_1%@
4 5
3 6
2 7
1 8
1 2
DC2 RB751V-40_SOD323-2
2
G
S
RPC11
0_8P4R_5%
1 2
RC86 0_0402_1%@
1 2
RC87 0_0402_1%@
DGPU_HOLD_RST#<22,41>
SYS_RESET#<6>
@
RC89
0_0402_1%
ENVDD_PCH<19>
DGPU_PWR_EN<24>
FFS_INT1<36>
PCH_RSMRST#_R
ME_SUS_PWR_ACK_R
PBTN_OUT#
AC_PRESENT
PCH_BATLOW#
SIO_SLP_S0#
PCH_SLP_WLAN#
12
SUSACK#_R
SYS_RESET#
SYS_PWROK_R
PCH_PWROK_R
PM_APWROK_R
PCH_PLTRST#
EDP_BKLCTLEDP_BIA_PWM
PANEL_BKLEN
ENVDD_PCH
GPIO77
DGPU_PWR_EN
DGPU_HOLD_RST#
T15 @
PCH_TP_INT#
PRODUCT_ID1
FFS_INT1
AK2
SUSACK
AC3
SYS_RESET
AG2
SYS_PWROK
AY7
PCH_PWROK
AB5
APWROK
AG7
PLTRST
AW6
RSMRST
AV4
SUSWARN/SUSPWRDNACK/GPIO30
AL7
PWRBTN
AJ8
ACPRESENT/GPIO31
AN4
BATLOW/GPIO72
AF3
SLP_S0
AM5
SLP_WLAN/GPIO29
UC1I
B8
EDP_BKLCTL
A9
EDP_BKLEN
C6
EDP_VDDEN
U6
PIRQA/GPIO77
P4
PIRQB/GPIO78
N4
PIRQC/GPIO79
N2
PIRQD/GPIO80
AD4
PME
U7
GPIO55
L1
GPIO52
L3
GPIO54
R5
GPIO51
L4
GPIO53
HASWELL_MCP_E
SYSTEM POWER MANAGEMENT
HASWELL_MCP_E
eDP SIDEBAND
GPIO
8 OF 19
9 OF 19
DISPLAY
DSWVRMEN
CLKRUN/GPIO32
SUS_STAT/GPIO61
SUSCLK/GPIO62
SLP_S5/GPIO63
DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPB_AUXN
DDPC_AUXN
DDPB_AUXP
DDPC_AUXP
DDPB_HPD
DDPC_HPD
EDP_HPD
PRODUCT_ID1:
Haswell---H
Broadwell---L
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
sualaptop365.edu.vn
5
4
3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2013/09/09 2014/09/09
2013/09/09 2014/09/09
2013/09/09 2014/09/09
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
MCP(8,9/19) DDI,EDP,GPIO
MCP(8,9/19) DDI,EDP,GPIO
MCP(8,9/19) DDI,EDP,GPIO
LA-A301P
LA-A301P
LA-A301P
1
10 56Friday, September 19, 2014
10 56Friday, September 19, 2014
10 56Friday, September 19, 2014
1.0
1.0
1.0
5
D D
+3VS
1 2
1 2
PRODUCT_ID2
12
DEVSLP0
12
DEVSLP1
12
SIO_EXT_SCI#
12
HDD_DET#
12
GPIO27
12
SLATE_MODE_R
12
PCH_AUDIO_EN
PRODUCT_ID2
C C
RC163 10K_0402_5%
RC108 10K_0402_5%
RC162 10K_0402_5%
RC110 100K_0402_5%
RC114 100K_0402_5%
+3V_DSW
RC115 10K_0402_5%
+3VALW_PCH
RC117 10K_0402_5%
RC118 10K_0402_5%
RC164 10K_0402_5%@
WAKE_PCH#<41>
PRODUCT_ID2:
NV GPU---H
AMD GPU---L
B B
+3VALW_PCH
+3VS
RPC18
18
27
36
45
10K_8P4R_5%
RPC16
18
27
36
45
8.2K_8P4R_5%
PCH_GPIO9
PCH_GPIO44
PCH_GPIO46
ODD_DA#
BT_OFF#
WL_OFF#
SERIRQ
4
T16 PAD~D@
EC_LID_OUT#<41>
CAB_DET_SINK<20>
BT_OFF#<32>
1 2
@
RC153 0_0402_1%
PCIE_MUX<34>
HDD_DET#<36>
WL_OFF#<32>
T20 PAD~D@
T21 PAD~D@
T23 PAD~D@
T26 PAD~D@
T27 PAD~D@
EC_SCI#<41>
DEVSLP0<36>
DEVSLP1<36>
HDA_SPKR<31>
PCH_AUDIO_EN
PCH_GPIO12
EC_LID_OUT#
ODD_DA#
CAB_DET_SINK
BT_OFF#
GPIO27
HDD_DET#
SLATE_MODE_R
WL_OFF#
PCH_GPIO44
PCH_GPIO47
PCH_GPIO48
PCH_GPIO49
PRODUCT_ID2
PCH_GPIO14
PCH_GPIO25
PCH_GPIO46
PCH_GPIO9
EC_SCI#
DEVSLP0
DEVSLP1
SIO_EXT_SCI#
HDA_SPKR
UC1J
P1
BMBUSY/GPIO76
AU2
GPIO8
AM7
LAN_PHY_PWR_CTRL/GPIO12
AD6
GPIO15
Y1
GPIO16
T3
GPIO17
AD5
GPIO24
AN5
GPIO27
AD7
GPIO28
AN3
GPIO26
AG6
GPIO56
AP1
GPIO57
AL4
GPIO58
AT5
GPIO59
AK4
GPIO44
AB6
GPIO47
U4
GPIO48
Y3
GPIO49
P3
GPIO50
Y2
HSIOPC/GPIO71
AT3
GPIO13
AH4
GPIO14
AM4
GPIO25
AG5
GPIO45
AG3
GPIO46
AM3
GPIO9
AM2
GPIO10
P2
DEVSLP0/GPIO33
C4
SDIO_POWER_EN/GPIO70
L2
DEVSLP1/GPIO38
N5
DEVSLP2/GPIO39
V2
SPKR/GPIO81
3
HASWELL_MCP_E
CPU/
MISC
GPIO
LPIO
10 OF 19
BBS_BIT
12
RC124
1K_0402_5%
GPIO86
BOOT BIOS STRAP BIT BBS
HIGH(LPC)
LOW(DEFAULT) (SPI)
THERMTRIP
RCIN/GPIO82
SERIRQ
PCH_OPI_RCOMP
RSVD
RSVD
GSPI0_CS/GPIO83
GSPI0_CLK/GPIO84
GSPI0_MISO/GPIO85
GSPI0_MOSI/GPIO86
GSPI1_CS/GPIO87
GSPI1_CLK/GPIO88
GSPI1_MISO/GPIO89
GSPI_MOSI/GPIO90
UART0_RXD/GPIO91
UART0_TXD/GPIO92
UART0_RTS/GPIO93
UART0_CTS/GPIO94
UART1_RXD/GPIO0
UART1_TXD/GPIO1
UART1_RST/GPIO2
UART1_CTS/GPIO3
I2C0_SDA/GPIO4
I2C0_SCL/GPIO5
I2C1_SDA/GPIO6
I2C1_SCL/GPIO7
SDIO_CLK/GPIO64
SDIO_CMD/GPIO65
SDIO_D0/GPIO66
SDIO_D1/GPIO67
SDIO_D2/GPIO68
SDIO_D3/GPIO69
Rev1p2
D60
V4
T4
AW15
AF20
AB21
R6
PCH_GPIO83
L6
PCH_GPIO84
N6
PCH_GPIO85
L8
BBS_BIT
R7
GC6_EVENT#
L5
GPU_GC6_FB_EN
N7
K2
PCH_GPIO90
J1
CPPE#
K3
CPUSB#
J2
PCH_GPIO93
G1
PCH_GPIO94
K4
G2
FFS_INT2
J3
LCD_CBL_DET#
J4
F2
I2C0_SDA
F3
I2C0_SCL
G4
I2C1_SDA_TP
F1
I2C1_SCL_TP
E3
F4
D3
E4
C3
E2
H_THERMTRIP#
KB_RST#
SERIRQ
PCH_OPI_COMP
+1.05VS
1 2
RC102
49.9_0402_1%
T17PAD~D @
T18PAD~D @
T19PAD~D @
GC6_EVENT# <22,41>
GPU_GC6_FB_EN <22,25,41>
T22PAD~D @
T24PAD~D @
T25PAD~D @
FFS_INT2 <36>
I2C1_SDA_TP <38>
I2C1_SCL_TP <38>
12
RC101
1K_0402_5%
2
+1.05VS
1
ESD@
CC27
100P_0402_50V8J
2
Close to RC101
KB_RST# <41>
SERIRQ <41>
WLAN_CLKREQ#_R<9>
LCD_CBL_DET#
FFS_INT2
CPPE#
CPUSB#
I2C1_SDA_TP
I2C1_SCL_TP
I2C0_SDA
I2C0_SCL
KB_RST#
WLAN_CLKREQ#_R
RC106
10K_0402_5%
12
RPC19
4 5
3 6
2 7
1 8
100K_8P4R_5%
RPC14
1 8
2 7
3 6
4 5
2.2K_0804_8P4R_5%
RPC15
18
27
36
45
10K_8P4R_5%
1
+3VS
+3VS_WLAN_NGFF
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
sualaptop365.edu.vn
5
4
3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2013/09/09 2014/09/09
2013/09/09 2014/09/09
2013/09/09 2014/09/09
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
MCP(10/19) GPIO,LPIO,MISC
MCP(10/19) GPIO,LPIO,MISC
MCP(10/19) GPIO,LPIO,MISC
LA-A301P
LA-A301P
LA-A301P
1
11 56Friday, September 19, 2014
11 56Friday, September 19, 2014
11 56Friday, September 19, 2014
1.0
1.0
1.0
5
D D
4
3
2
1
PCIe
HASWELL_MCP_E
11 OF 19
AN8
AM8
AR7
AT7
AR8
AP8
AR10
AT10
AM15
AL15
AM13
AN13
AP11
AN11
AR13
AP13
G20
H20
C33
B34
E18
F18
B33
A33
AJ10
AJ11
AN10
AM10
AL3
AT1
AH2
AV3
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_CALDERA_N3
USB20_CALDERA_P3
USB20_TOUCH_N4
USB20_TOUCH_P4
USB20_CAM_N5
USB20_CAM_P5
USB20_ELC_N6
USB20_ELC_P6
USB20_BT_N7
USB20_BT_P7
USB3RN1
USB3RP1
USB3TN1
USB3TP1
USB3RN2
USB3RP2
USB3TN2
USB3TP2
USBRBIAS
USB2N0
USB2P0
USB2N1
USB2P1
USB2N2
USB2P2
USB2N3
USB2P3
USB2N4
USB2P4
USB2N5
USB2P5
USB2N6
USB2P6
USB2N7
USB2P7
USB3RN1
USB3RP1
USB
USB3TN1
USB3TP1
USB3RN2
USB3RP2
USB3TN2
USB3TP2
USBRBIAS
USBRBIAS
RSVD
RSVD
OC0/GPIO40
OC1/GPIO41
OC2/GPIO42
OC3/GPIO43
Rev1p2
USB20_N0 <33>
USB20_P0 <33>
USB20_N1 <33>
USB20_P1 <33>
USB20_N2 <33>
USB20_P2 <33>
USB20_CALDERA_N3 <34>
USB20_CALDERA_P3 <34>
USB20_TOUCH_N4 <19>
USB20_TOUCH_P4 <19>
USB20_CAM_N5 <19>
USB20_CAM_P5 <19>
USB20_ELC_N6 <37>
USB20_ELC_P6 <37>
USB20_BT_N7 <32>
USB20_BT_P7 <32>
USB3RN1 <33>
USB3RP1 <33>
USB3TN1 <33>
USB3TP1 <33>
USB3RN2 <33>
USB3RP2 <33>
USB3TN2 <33>
USB3TP2 <33>
USB_OC0# <33>
USB_OC1# <33>
USB_OC2# <33>
Left side 1
Right side (power share)
Left side 2
Caldera
Touch screen
Camera
ELC
Bluetooth
Left side 1
Right side (power share)
12
RC127
22.6_0402_1%~D
CAD NOTE:
Route single-end 50-ohms and max 500-mils length.
Avoid routing next to clock pins or under stitching capacitors.
Recommended minimum spacing to other signal traces is 15 mils.
UC1K
PEG_CRX_GTX_N0<34>
PEG_CRX_GTX_P0<34>
PEG_CTX_GRX_N0<34>
PEG_CTX_GRX_P0<34>
PEG_CRX_GTX_N1<34>
PEG_CRX_GTX_P1<34>
PEG_CTX_GRX_N1<34>
PCIE 4X MUX
C C
WLAN (M.2 Card)
10/100/1000 LAN
B B
PEG_CTX_GRX_P1<34>
PEG_CRX_GTX_N2<34>
PEG_CRX_GTX_P2<34>
PEG_CTX_GRX_N2<34>
PEG_CTX_GRX_P2<34>
PEG_CRX_GTX_N3<34>
PEG_CRX_GTX_P3<34>
PEG_CTX_GRX_N3<34>
PEG_CTX_GRX_P3<34>
PCIE_PRX_WLANTX_N3<32>
PCIE_PRX_WLANTX_P3<32>
PCIE_PTX_WLANRX_N3<32>
PCIE_PTX_WLANRX_P3<32>
PCIE_PRX_LANTX_N4<30>
PCIE_PRX_LANTX_P4<30>
PCIE_PTX_LANRX_N4<30>
PCIE_PTX_LANRX_P4<30>
PEG_CRX_GTX_N0
PEG_CRX_GTX_P0
PEG_CTX_GRX_N0
PEG_CTX_GRX_P0
PEG_CRX_GTX_N1
PEG_CRX_GTX_P1
PEG_CRX_GTX_N2
PEG_CRX_GTX_P2
PEG_CRX_GTX_N3
PEG_CRX_GTX_P3
Left side 2
Caldera
+1.05VS_AUSB3PLL
12
CC28 0.22U_0402_10V6K
12
CC29 0.22U_0402_10V6K
12
CC31 0.22U_0402_10V6K
12
CC30 0.22U_0402_10V6K
12
CC32 0.22U_0402_10V6K
12
CC33 0.22U_0402_10V6K
12
CC34 0.22U_0402_10V6K
12
CC35 0.22U_0402_10V6K
1 2
CC90 0.1U_0402_10V7K
1 2
CC89 0.1U_0402_10V7K
1 2
CC36 0.1U_0402_10V7K
1 2
CC37 0.1U_0402_10V7K
USB3RN3<33>
USB3RP3<33>
USB3TN3<33>
USB3TP3<33>
USB3RN4<34>
USB3RP4<34>
USB3TN4<34>
USB3TP4<34>
RC128
3.01K_0402_1%
1 2
PCH_PCIE_RCOMP
PEG_CTX_GRX_C_N0
PEG_CTX_GRX_C_P0
PEG_CTX_GRX_C_N1PEG_CTX_GRX_N1
PEG_CTX_GRX_C_P1PEG_CTX_GRX_P1
PEG_CTX_GRX_C_N2PEG_CTX_GRX_N2
PEG_CTX_GRX_C_P2PEG_CTX_GRX_P2
PEG_CTX_GRX_C_N3PEG_CTX_GRX_N3
PEG_CTX_GRX_C_P3PEG_CTX_GRX_P3
PCIE_PTX_WLANRX_N3_C
PCIE_PTX_WLANRX_P3_C
PCIE_PTX_LANRX_N4_C
PCIE_PTX_LANRX_P4_C
F10
E10
C23
C22
F8
E8
B23
A23
H10
G10
B21
C21
E6
F6
B22
A21
G11
F11
C29
B30
F13
G13
B29
A29
G17
F17
C30
C31
F15
G15
B31
A31
E15
E13
A27
B27
PERN5_L0
PERP5_L0
PETN5_L0
PETP5_L0
PERN5_L1
PERP5_L1
PETN5_L1
PETP5_L1
PERN5_L2
PERP5_L2
PETN5_L2
PETP5_L2
PERN5_L3
PERP5_L3
PETN5_L3
PETP5_L3
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4
PERN1/USB3RN3
PERP1/USB3RP3
PETN1/USB3TN3
PETP1/USB3TP3
PERN2/USB3RN4
PERP2/USB3RP4
PETN2/USB3TN4
PETP2/USB3TP4
RSVD
RSVD
PCIE_RCOMP
PCIE_IREF
+3VALW_PCH
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
sualaptop365.edu.vn
5
4
3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2013/09/09 2014/09/09
2013/09/09 2014/09/09
2013/09/09 2014/09/09
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
1 8
2 7
3 6
4 5
RPC17
10K_8P4R_5%
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
MCP(11/19) PCIE,USB
MCP(11/19) PCIE,USB
MCP(11/19) PCIE,USB
LA-A301P
LA-A301P
LA-A301P
1
1.0
1.0
12 56Friday, September 19, 2014
12 56Friday, September 19, 2014
12 56Friday, September 19, 2014
1.0
5
4
3
2
1
VR_ONVCCST_PG_EC
Place CC40
close to RC133.1
H_CPU_SVIDALRT#
RC135 close to CPU
VR_SVID_DAT
12
RC137
10K_0402_5%
@ESD@
CC40
0.1U_0402_10V7K
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Rev1p2
C36
C40
C44
C48
C52
C56
E23
E25
E27
E29
E31
E33
E35
E37
E39
E41
E43
E45
E47
E49
E51
E53
E55
E57
F24
F28
F32
F36
F40
F44
F48
F52
F56
G23
G25
G27
G29
G31
G33
G35
G37
G39
G41
G43
G45
G47
G49
G51
G53
G55
G57
H23
J23
K23
K57
L22
M23
M57
P57
U57
W57
+CPU_CORE
1
2
+VCCIO_OUT
@
RC129
0_0603_5%
1 2
VR_SVID_CLK<53>
RF@
CC41
68P_0402_50V8J
1
2
H_VR_READY<53>
CPU_PWR_DEBUG#<6>
+CPU_CORE
+VCCIO_OUT_R
+VCCIOA_OUT
VR_ON<41,53>
+CPU_CORE
+1.35V
+1.05VS
VCCSENSE
H_CPU_SVIDALRT#
VR_SVID_DAT
VCCST_PG_EC
CPU_PWR_DEBUG#
T33 @
T34 @
T35 @
T36 @
T37 @
T38 @
T39 @
T40 @
T41 @
T42 @
T43 @
T44 @
T45 @
AH26
AJ31
AJ33
AJ37
AN33
AP43
AR48
AY35
AY40
AY44
AY50
AC58
AB23
AD23
AA23
AE59
AD60
AD59
AA59
AE60
AC59
AG58
AC22
AE22
AE23
AB57
AD57
AG57
L59
J58
F59
N58
E63
A59
E20
L62
N63
L63
B59
F60
C59
D63
H59
P62
P60
P61
N59
N61
T59
U59
V59
C24
C28
C32
UC1L
RSVD
RSVD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VCC
RSVD
RSVD
VCC_SENSE
RSVD
VCCIO_OUT
VCCIOA_OUT
RSVD
RSVD
RSVD
VIDALERT
VIDSCLK
VIDSOUT
VCCST_PWRGD
VR_EN
VR_READY
VSS
PWR_DEBUG
VSS
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VCCST
VCCST
VCCST
VCC
VCC
VCC
VCC
VCC
VCC
HASWELL_MCP_E
12 OF 19
HSW ULT POWER
1 2
ESD@
CC39
22U_0603_6.3V6M
ESD solutionPlace C38
RC130
75_0402_5%
RC131
43_0402_1%
+1.05VS
+1.35V
RC130 close to CPU
12
12
RC135
130_0402_1%
+1.05VS
D D
@ESD@
CC38
220P_0402_50V8J
1
2
+CPU_CORE
between RC137 and UC1
+1.05VS
12
SVID ALERT
VR_SVID_ALRT#<53>
SVID DATA
C C
need to pull-up double side
( PWR_VR & CPU )
VR_SVID_DAT<53>
VCCST_PG_EC<41>
VCCST_PG_EC
Define EC OD pin
need double confirm.
B B
VCCSENSE<53>
VSSSENSE<15,53>
VCCSENSE
VSSSENSE
+CPU_CORE
12
RC138
100_0402_1%
12
RC141
100_0402_1%
CAD Note: PU resistor on HW side
CAD Note: PD resistor on HW side
+1.05VS
1 2
1 2
RC139
@
RC139
150_0402_1%
Intel check list , XDP use only
CPU_PWR_DEBUG#
@
RC140
10K_0402_5%
+1.35V
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
CC42
1
2
2.2U_0402_6.3V6M
CC43
CC44
1
1
2
2
VDDQ DECOUPLING
2.2U_0402_6.3V6M
CC45
1
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CC46
2
10U_0603_6.3V6M
1
CC47
2
10U_0603_6.3V6M
1
1
CC48
CC49
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
CC51
CC50
2
2
+1.35V : 470UF/2V/7343 *2 (PWR)
10UF/6.3V/0603 * 6
A A
2.2UF/6.3V/0402 * 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
sualaptop365.edu.vn
5
4
3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2013/09/09 2014/09/09
2013/09/09 2014/09/09
2013/09/09 2014/09/09
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
MCP(12/19) Power
MCP(12/19) Power
MCP(12/19) Power
LA-A301P
LA-A301P
LA-A301P
1
13 56Friday, September 19, 2014
13 56Friday, September 19, 2014
13 56Friday, September 19, 2014
1.0
1.0
1.0
5
D D
4
3
2
1
+1.05VS +1.05VS_AUSB3PLL
1 2
LC1
2.2UH_LQM2MPN2R2NG0L_30%
+1.05VS_ASATA3PLL
1 2
LC2
2.2UH_LQM2MPN2R2NG0L_30%
LC3
2.2UH_LQM2MPN2R2NG0L_30%
LC4
C C
2.2UH_LQM2MPN2R2NG0L_30%
LC5
2.2UH_LQM2MPN2R2NG0L_30%
+1.5VS +3VS
+VCCHDA
RC142
0_0805_1%
1 2
@
1 2
@
1 2
1 2
+1.05VS_APLLOPI
+1.05VS_AXCK_DCB
+1.05VS_AXCK_LCPLL
RC145 0_0402_1%@
RC146 0_0402_5%@
RC147 0_0402_5%@
CC79 0.1U_0402_10V7K
Reserve for HDA issue, C79 close to UC1M.AH14
+1.05VS
B B
+3V_DSW
+3VALW_PCH
+3VS
+1.05VS
+1.05VS
+3VALW_PCH
+1.05VS
1 2
CC53 1U_0402_6.3V6K
1 2
CC54 100U_A1_6.3VM_R70M
1 2
CC59 1U_0402_6.3V6K
1 2
CC55 100U_A1_6.3VM_R70M
1 2
CC63 1U_0402_6.3V6K
1 2
CC64 100U_A1_6.3VM_R70M@
1 2
CC68 1U_0402_6.3V6K
1 2
CC70 100U_A1_6.3VM_R70M
1 2
CC73 1U_0402_6.3V6K
1 2
CC75 100U_A1_6.3VM_R70M
1 2
1 2
1 2
1 2
1 2
CC81 1U_0402_6.3V6K
1 2
CC82 1U_0402_6.3V6K
1 2
CC83 1U_0402_6.3V6K
1 2
CC84 22U_0603_6.3V6M
1 2
CC85 22U_0603_6.3V6M
1 2
CC86 1U_0402_6.3V6K
1 2
CC87 1U_0402_6.3V6K
CC88 0.1U_0402_10V7K
1 2
CC52 1U_0402_6.3V6K@
+VCCHDA+3VALW_PCH
12
HASWELL_MCP_E
mPHY
OPI
USB3
AXALIA/HDA
VRM/USB2/AZALIA
GPIO/LCC
LPT LP POWER
+1.05VS
+1.05VS
+1.05VS_AUSB3PLL
+1.05VS_ASATA3PLL
+1.05VS_APLLOPI
T46 @
+VCCHDA
T47 @
+3VALW_PCH
+3V_DSW
+3VS
+1.05VS_AXCK_DCB
+1.05VS_AXCK_LCPLL
+1.05VS
+1.05VS
+3VALW_PCH
AH14
AH13
AH10
AA21
W21
AC9
M20
AE20
AE21
K9
L10
M9
N8
P9
B18
B11
Y20
J13
AA9
V8
W9
J18
K19
A20
J17
R21
T21
K18
V21
UC1M
VCCHSIO
VCCHSIO
VCCHSIO
VCC1_05
VCC1_05
VCCUSB3PLL
VCCSATA3PLL
RSVD
VCCAPLL
VCCAPLL
DCPSUS3
VCCHDA
DCPSUS2
VCCSUS3_3
VCCSUS3_3
VCCDSW3_3
VCC3_3
VCC3_3
VCCCLK
VCCCLK
VCCACLKPLL
VCCCLK
VCCCLK
VCCCLK
RSVD
RSVD
RSVD
VCCSUS3_3
VCCSUS3_3
Close to UC1M.K9/UC1M.M9
Close to UC1M.AH10
Close to UC1M.AC9/UC1M.AA9/UC1M.AE20/UC1M.AE21
Close to UC1M.V8
Close to UC1M.J17
Close to UC1M.R21
Close to UC1M.AH14
Close to UC1M.N8
13 OF 19
RTC
SPI
CORE
THERMAL SENSOR
SDIO/PLSS
SUS OSCILLATOR
USB2
VCCSUS3_3
VCCRTC
DCPRTC
VCCSPI
VCCASW
VCCASW
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
DCPSUSBYP
DCPSUSBYP
VCCASW
VCCASW
VCCASW
DCPSUS1
DCPSUS1
VCCTS1_5
VCC3_3
VCC3_3
VCCSDIO
VCCSDIO
DCPSUS4
RSVD
VCC1_05
VCC1_05
Rev1p2
+3VALW_PCH
AH11
AG10
AE7
+VCCRTCEXT
Y8
AG14
AG13
J11
CC67 10U_0603_6.3V6M
H11
CC69 1U_0402_6.3V6K
H15
CC71 1U_0402_6.3V6K
AE8
+PCH_VCCDSW
AF22
AG19
AG20
CC72 1U_0402_6.3V6K
AE9
AF9
CC74 22U_0603_6.3V6M@
AG8
CC76 1U_0402_6.3V6K
AD10
AD8
T48 @
T49 @
J15
K14
K16
CC77 0.1U_0402_10V7K
U8
T9
CC78 1U_0402_6.3V6K
AB8
T50 @
AC20
AG16
AG17
+1.05VS
1 2
CC80 1U_0402_6.3V6K
CC60 close to UC1M.AH11
1 2
CC60 1U_0402_6.3V6K
+RTCVCC
1 2
CC61 0.1U_0402_10V7K
+3VS
1 2
CC62 0.1U_0402_10V7K@
+1.05VS
+1.05VS
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
+1.5VS
+3VS
+3VS
+1.05VS
+RTCVCC
CC56
1U_0402_6.3V6K
+1.05VS
1
CC57
2
0.1U_0402_10V7K
1 2
ESD@
CC65
22U_0603_6.3V6M
1
CC58
2
0.1U_0402_10V7K
+3VS
ESD solution
1
2
1 2
ESD@
CC66
22U_0603_6.3V6M
+1.35V+1.05VS
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
sualaptop365.edu.vn
5
4
3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2013/09/09 2014/09/09
2013/09/09 2014/09/09
2013/09/09 2014/09/09
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
MCP(13/19) Power
MCP(13/19) Power
MCP(13/19) Power
LA-A301P
LA-A301P
LA-A301P
1
14 56Friday, September 19, 2014
14 56Friday, September 19, 2014
14 56Friday, September 19, 2014
1.0
1.0
1.0
5
D D
4
3
2
1
HASWELL_MCP_E
UC1N
A11
VSS
A14
VSS
A18
VSS
A24
VSS
A28
VSS
A32
VSS
A36
VSS
A40
VSS
A44
VSS
A48
VSS
A52
VSS
A56
VSS
AA1
VSS
AA58
VSS
AB10
VSS
AB20
VSS
C C
B B
AB22
AC61
AD21
AD63
AE10
AE58
AF11
AF12
AF14
AF15
AF17
AF18
AG11
AG21
AG23
AG60
AG61
AG62
AG63
AH17
AH19
AH20
AH22
AH24
AH28
AH30
AH32
AH34
AH36
AH38
AH40
AH42
AH44
AH49
AH51
AH53
AH55
AH57
AJ13
AJ14
AJ23
AJ25
AJ27
AJ29
VSS
AB7
VSS
VSS
VSS
AD3
VSS
VSS
VSS
AE5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AG1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
14 OF 19
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Rev1p2
AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20
AP22
AP23
AP26
AP29
AP31
AP38
AP39
AP48
AP52
AP54
AP57
AR11
AR15
AR17
AR23
AR31
AR33
AR39
AR43
AR49
AR52
AT13
AT35
AT37
AT40
AT42
AT43
AT46
AT49
AT61
AT62
AT63
AU16
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU33
AU51
AU53
AU55
AU57
AU59
AV14
AV16
AV20
AV24
AV28
AV33
AV34
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55
HASWELL_MCP_E
UC1O
VSS
VSS
VSS
VSS
AP3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AR5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AU1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
15 OF 19
Rev1p2
AV59
VSS
AV8
VSS
AW16
VSS
AW24
VSS
AW33
VSS
AW35
VSS
AW37
VSS
AW4
VSS
AW40
VSS
AW42
VSS
AW44
VSS
AW47
VSS
AW50
VSS
AW51
VSS
AW59
VSS
AW60
VSS
AY11
VSS
AY16
VSS
AY18
VSS
AY22
VSS
AY24
VSS
AY26
VSS
AY30
VSS
AY33
VSS
AY4
VSS
AY51
VSS
AY53
VSS
AY57
VSS
AY59
VSS
AY6
VSS
B20
VSS
B24
VSS
B26
VSS
B28
VSS
B32
VSS
B36
VSS
B4
VSS
B40
VSS
B44
VSS
B48
VSS
B52
VSS
B56
VSS
B60
VSS
C11
VSS
C14
VSS
C18
VSS
C20
VSS
C25
VSS
C27
VSS
C38
VSS
C39
VSS
C57
VSS
D12
VSS
D14
VSS
D18
VSS
D2
VSS
D21
VSS
D23
VSS
D25
VSS
D26
VSS
D27
VSS
D29
VSS
D30
VSS
D31
VSS
UC1P
HASWELL_MCP_E
D33
VSS
D34
VSS
D35
VSS
D37
VSS
D38
VSS
D39
VSS
D41
VSS
D42
VSS
D43
VSS
D45
VSS
D46
VSS
D47
VSS
D49
VSS
D5
VSS
D50
VSS
D51
VSS
D53
VSS
D54
VSS
D55
VSS
D57
VSS
D59
VSS
D62
VSS
D8
VSS
E11
VSS
E17
VSS
F20
VSS
F26
VSS
F30
VSS
F34
VSS
F38
VSS
F42
VSS
F46
VSS
F50
VSS
F54
VSS
F58
VSS
F61
VSS
G18
VSS
G22
VSS
G3
VSS
G5
VSS
G6
VSS
G8
VSS
H13
VSS
16 OF 19
VSS_SENSE
Rev1p2
H17
VSS
H57
VSS
J10
VSS
J22
VSS
J59
VSS
J63
VSS
K1
VSS
K12
VSS
L13
VSS
L15
VSS
L17
VSS
L18
VSS
L20
VSS
L58
VSS
L61
VSS
L7
VSS
M22
VSS
N10
VSS
N3
VSS
P59
VSS
P63
VSS
R10
VSS
R22
VSS
R8
VSS
T1
VSS
T58
VSS
U20
VSS
U22
VSS
U61
VSS
U9
VSS
V10
VSS
V3
VSS
V7
VSS
W20
VSS
W22
VSS
Y10
VSS
Y59
VSS
Y63
VSS
V58
VSS
AH46
VSS
V23
VSS
E62
AH16
VSS
12
@
RC148
100_0402_1%
VSSSENSE <13,53>
RC148 SHOULD BE PLACED CLOSE TO CPU
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
sualaptop365.edu.vn
5
4
3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2013/09/09 2014/09/09
2013/09/09 2014/09/09
2013/09/09 2014/09/09
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
MCP(14,15,16/19) VSS
MCP(14,15,16/19) VSS
MCP(14,15,16/19) VSS
LA-A301P
LA-A301P
LA-A301P
1
15 56Friday, September 19, 2014
15 56Friday, September 19, 2014
15 56Friday, September 19, 2014
1.0
1.0
1.0
5
D D
4
3
2
1
UC1S
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG18
CFG17
CFG19
CFG_RCOMP
RSVD
RSVD
RSVD
RSVD
RSVD
TD_IREF
HASWELL_MCP_E
17 OF 19
DAISY_CHAIN_NCTF_A3
DAISY_CHAIN_NCTF_A4
DAISY_CHAIN_NCTF_A60
DAISY_CHAIN_NCTF_A61
DAISY_CHAIN_NCTF_A62
DAISY_CHAIN_NCTF_AV1
DAISY_CHAIN_NCTF_AW1
DAISY_CHAIN_NCTF_AW2
DAISY_CHAIN_NCTF_AW3
DAISY_CHAIN_NCTF_AW61
DAISY_CHAIN_NCTF_AW62
DAISY_CHAIN_NCTF_AW63
Rev1p2
HASWELL_MCP_E
RESERVED
19 OF 19
A3
A4
A60
A61
A62
AV1
AW1
AW2
AW3
AW61
AW62
AW63
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
PROC_OPI_RCOMP
RSVD
RSVD
RSVD
RSVD
Rev1p2
DC_TEST_A3_B3
DC_TEST_A4
DC_TEST_A60
DC_TEST_A61_B61
DC_TEST_A62
DC_TEST_AV1
DC_TEST_AW1
DC_TEST_AY2_AW2
DC_TEST_AY3_AW3
DC_TEST_AY61_AW61
DC_TEST_AW63
AV63
AU63
C63
C62
B43
A51
B51
L60
N60
W23
Y22
AY15
AV62
D58
P22
VSS
N21
VSS
P20
R20
T77PAD~D @
T78PAD~D @
T79PAD~D @
T80PAD~D @
T81PAD~D @
T82PAD~D @
T83PAD~D @
T84PAD~D @
T85PAD~D @
T86PAD~D @
T87PAD~D @
T88PAD~D @
T89PAD~D @
T91PAD~D @
T93PAD~D @
T51PAD~D @
T53PAD~D @
T61PAD~D @
T63PAD~D @
T66PAD~D @
T75PAD~D @
PROC_OPI_RCOMP
UC1R
@
T54 PAD~D
@
T58 PAD~D
@
T62 PAD~D
@
T64 PAD~D
@
T68 PAD~D
@
T70 PAD~D
@ T73PAD~D
T72 PAD~D
1 2
RC152
49.9_0402_1%
RSVD_AT2
RSVD_AU44
RSVD_AV44
RSVD_D15
RSVD_F22
RSVD_H22
RSVD_J21
AU44
AV44
AT2
RSVD
RSVD
RSVD
D15
RSVD
F22
RSVD
H22
RSVD
J21
RSVD
UC1Q
DC_TEST_AY2_AW2
DC_TEST_AY3_AW3
T52 PAD~D@
T60 PAD~D@
C C
B B
RC150
49.9_0402_1%
1 2
RC151
8.2K_0402_1%
DC_TEST_AY60
DC_TEST_AY61_AW61
DC_TEST_AY62_AW62
TP_DC_TEST_B2
DC_TEST_A3_B3
DC_TEST_A61_B61
DC_TEST_B62_B63
DC_TEST_C1_C2 DC_TEST_AY62_AW62
CFG0<6>
CFG1<6>
CFG2<6>
CFG3<6>
CFG4<6>
CFG5<6>
CFG6<6>
CFG7<6>
CFG8<6>
CFG9<6>
CFG10<6>
CFG11<6>
CFG12<6>
CFG13<6>
CFG14<6>
CFG15<6>
CFG16<6>
CFG18<6>
CFG17<6>
CFG19<6>
12
CFG_RCOMP
T90 PAD~D@
T92 PAD~D@
T94 PAD~D@
T95 PAD~D@
T96 PAD~D@
TDI_IREF
AY2
DAISY_CHAIN_NCTF_AY2
AY3
DAISY_CHAIN_NCTF_AY3
AY60
DAISY_CHAIN_NCTF_AY60
AY61
DAISY_CHAIN_NCTF_AY61
AY62
DAISY_CHAIN_NCTF_AY62
B2
DAISY_CHAIN_NCTF_B2
B3
DAISY_CHAIN_NCTF_B3
B61
DAISY_CHAIN_NCTF_B61
B62
DAISY_CHAIN_NCTF_B62
B63
DAISY_CHAIN_NCTF_B63
C1
DAISY_CHAIN_NCTF_C1
C2
DAISY_CHAIN_NCTF_C2
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG18
CFG17
CFG19
AC60
AC62
AC63
AA63
AA60
AA62
AA61
Y62
Y61
Y60
V62
V61
V60
U60
T63
T62
T61
T60
U63
U62
V63
A5
E1
D1
J20
H18
B12
CFG4
HASWELL_MCP_E
N23
R23
T23
U10
AL1
AM11
AP7
AU10
AU15
AW14
AY14
RSVD_N23
RSVD_R23
RSVD_T23
RSVD_U10
RSVD_AL1
RSVD_AM11
RSVD_AP7
RSVD_AU10
RSVD_AU15
RSVD_AW14
RSVD_AY14
18 OF 19
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
Rev1p2
CFG STRAPS for CPU
CFG4
12
RC149
1K_0402_1%
Display Port Presence Strap
1: Disabled; No Physical Display Port
attached to Embedded Display Port
0: Enabled; An external Display Port device is
connected to the Embedded Display Port
@
T55PAD~D
@
T56PAD~D
@
T57PAD~D
@
T59PAD~D
@
T65PAD~D
@
T67PAD~D
@
T69PAD~D
@
T71PAD~D
@
@
T74PAD~D
@
T76PAD~D
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
sualaptop365.edu.vn
5
4
3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2013/09/09 2014/09/09
2013/09/09 2014/09/09
2013/09/09 2014/09/09
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
MCP(17,18,19/19) CFG,RSVD
MCP(17,18,19/19) CFG,RSVD
MCP(17,18,19/19) CFG,RSVD
LA-A301P
LA-A301P
LA-A301P
1
16 56Friday, September 19, 2014
16 56Friday, September 19, 2014
16 56Friday, September 19, 2014
1.0
1.0
1.0
5
4
3
2
1
2-3A to 1 DIMMs/channel
+SM_VREF_DQ0_DIMM1
2.2U_0402_6.3V6M
0.1U_0402_10V7K
D D
Populate RD1, De-Populate RD7 for Intel DDR3
VREFDQ multiple methods M1
Populate RD7, De-Populate RD1 for Intel DDR3
VREFDQ multiple methods M3
DDR_A_DQS#[0..7]<7>
DDR_A_D[0..63]<7>
DDR_A_DQS[0..7]<7>
DDR_A_MA[0..15]<7>
+1.35V
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C C
B B
A A
1
CD5
CD4
2
2
+1.35V
10U_0603_6.3V6M
+0.675VS
10U_0603_6.3V6M
10U_0603_6.3V6M
@
CD12
CD13
1
2
Layout Note:
Place near JDIMM1
1
2
Layout Note:
Place near JDIMM1.203,204
1
1
2
2
0.1U_0402_10V7K
0.1U_0402_10V7K
CD25
CD24
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CD6
2
10U_0603_6.3V6M
CD15
CD14
1
2
0.1U_0402_10V7K
CD26
1
2
1U_0402_6.3V6K
1
1
CD7
CD8
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
@
CD16
CD17
1
1
2
2
10U_0603_6.3V6M
0.1U_0402_10V7K
CD28
CD27
1
1
2
2
All VREF traces should
have 10 mil trace width
Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket
1U_0402_6.3V6K
1
CD9
2
10U_0603_6.3V6M
CD18
1
1
2
2
10U_0603_6.3V6M
CD29
1
2
1U_0402_6.3V6K
1
CD10
2
330U_D3_2.5VY_R6M
1
CD19
+
2
1U_0402_6.3V6K
1
CD11
2
CD20
1 2
RD11 10K_0402_5%
1 2
RD12 10K_0402_5%
+3VS
ESD@
CD33
22U_0603_6.3V6M
ESD solution
1 2
DDR_CKE0_DIMMA<7>
DDR_CS1_DIMMA#<7>
+3VS
M_CLK_DDR0<7>
M_CLK_DDR#0<7>
DDR_A_BS0<7>
DDR_A_WE#<7>
DDR_A_CAS#<7>
+1.35V
CD1
1
2
DDR_A_BS2<7>
2.2U_0402_6.3V6M
1
2
DDR_A_D13
DDR_A_D8
CD2
1
DDR_A_D14
2
DDR_A_D10
DDR_A_D29
DDR_A_D28 DDR_A_D24
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_A_D41
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D43
DDR_A_D47
DDR_A_D51
DDR_A_D50
DDR_A_D49
DDR_A_D48
DDR_CKE0_DIMMA
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_CS1_DIMMA#
DDR_A_D0
DDR_A_D1
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D6
DDR_A_D21
DDR_A_D20
DDR_A_D17
DDR_A_D16
DDR_A_D36
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D38
DDR_A_D62
DDR_A_D58
DDR_A_D60
DDR_A_D61
0.1U_0402_10V7K
1
@
CD31
CD32
+0.675VS
2
JDIMM1
1
VREF_DQ
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DM0
13
VSS
15
DQ2
17
DQ3
19
VSS
21
DQ8
23
DQ9
25
VSS
27
DQS1#
29
DQS1
31
VSS
33
DQ10
35
DQ11
37
VSS
39
DQ16
41
DQ17
43
VSS
45
DQS2#
47
DQS2
49
VSS
51
DQ18
53
DQ19
55
VSS
57
DQ24
59
DQ25
61
VSS
63
DM3
65
VSS
67
DQ26
69
DQ27
71
VSS
73
CKE0
75
VDD
77
NC
79
BA2
81
VDD
83
A12/BC#
85
A9
87
VDD
89
A8
91
A5
93
VDD
95
A3
97
A1
99
VDD
101
CK0
103
CK0#
105
VDD
107
A10/AP
109
BA0
111
VDD
113
WE#
115
CAS#
117
VDD
119
A13
121
S1#
123
VDD
125
TEST
127
VSS
129
DQ32
131
DQ33
133
VSS
135
DQS4#
137
DQS4
139
VSS
141
DQ34
143
DQ35
145
VSS
147
DQ40
149
DQ41
151
VSS
153
DM5
155
VSS
157
DQ42
159
DQ43
161
VSS
163
DQ48
165
DQ49
167
VSS
169
DQS6#
171
DQS6
173
VSS
175
DQ50
177
DQ51
179
VSS
181
DQ56
183
DQ57
185
VSS
187
DM7
189
VSS
191
DQ58
193
DQ59
195
VSS
197
SA0
199
VDDSPD
201
SA1
203
VTT
205
GND1
207
BOSS1
FOX_AS0A621-J4RB-7H
CONN@
RESET#
VREF_CA
EVENT#
sualaptop365.edu.vn
5
4
DQS0#
DQS0
DQ12
DQ13
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQS3#
DQS3
DQ30
DQ31
CKE1
CK1#
RAS#
ODT0
ODT1
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQS5#
DQS5
DQ46
DQ47
DQ52
DQ53
DQ54
DQ55
DQ60
DQ61
DQS7#
DQS7
DQ62
DQ63
GND2
BOSS2
+1.35V+1.35V
2
VSS
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
3
DDR_A_D9
DDR_A_D12
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D15
DDR_A_D11
DDR_A_D25
DDR3_DRAMRST#_CPU
DDR_A_D27
DDR_A_D26
DDR_A_D45DDR_A_D44
DDR_A_D40
DDR_A_D42
DDR_A_D46
DDR_A_D52
DDR_A_D53
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D54
DDR_A_D55
DDR_CKE1_DIMMA
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
M_ODT1
DDR_A_D5
DDR_A_D4
DDR_A_D3
DDR_A_D7
DDR_A_D18
DDR_A_D19
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D22
DDR_A_D23
DDR_A_D37
DDR_A_D32
DDR_A_D35
DDR_A_D39
DDR_A_D63
DDR_A_D59
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D56
DDR_A_D57
+0.675VS
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+1.35V
12
RD2
470_0402_5%
@ESD@
1
CD3
0.1U_0402_10V7K
2
CAD NOTE
PLACE THE CAP NEAR TO
DIMM RESET PIN
DDR_CKE1_DIMMA <7>
M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>
DDR_A_BS1 <7>
DDR_A_RAS# <7>
DDR_CS0_DIMMA# <7>
+SM_VREF_CA_DIMM
2.2U_0402_6.3V6M
CD22
1
2
DDR_PG_CTRL<6>
DDR3_DRAMRST#_CPU <6,18>
0.1U_0402_10V7K
CD23
1
2
UD1
NC1VCC
2
A
3
GND
74AUP1G07GW_TSSOP5
M_THERMAL# <18,41>
DDR_XDP_WLAN_TP_SMBDAT <6,9,18,36>
DDR_XDP_WLAN_TP_SMBCLK <6,9,18,36>
Compal Secret Data
Compal Secret Data
2013/09/09 2014/09/09
2013/09/09 2014/09/09
2013/09/09 2014/09/09
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
+5VALW +1.35V
+1.35V
5
4
Y
DDR3L SODIMM ODT GENERATION
QD1
12
RD4
220K_0402_5%~D
@
RD10
2M_0402_5%
1 2
@
CD30
0.1U_0402_10V7K
1 2
BSS138-G_SOT23-3
1 3
D
S
G
2
0.675V_DDR_VTT_ON
M_ODT
1 2
RD5 66.5_0402_1%
1 2
RD6 66.5_0402_1%
1 2
RD7 66.5_0402_1%
1 2
RD8 66.5_0402_1%
1
@ESD@
CD21
0.1U_0402_10V7K
2
Place CD21
between QD1 and RD6
Title
Title
Title
DDRIII DIMMA
DDRIII DIMMA
DDRIII DIMMA
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
LA-A301P
LA-A301P
LA-A301P
Date: Sheet of
Date: Sheet of
Date: Sheet of
M_ODT0
M_ODT1
M_ODT2 <18>
M_ODT3 <18>
0.675V_DDR_VTT_ON <50>
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
17 56Friday, September 19, 2014
17 56Friday, September 19, 2014
1
17 56Friday, September 19, 2014
1.0
1.0
1.0
DQ4
DQ5
VSS
VSS
DQ6
DQ7
VSS
VSS
DM1
VSS
VSS
VSS
DM2
VSS
VSS
VSS
VSS
VSS
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
VDD
BA1
VDD
S0#
VDD
NC
VDD
VSS
VSS
DM4
VSS
VSS
VSS
VSS
VSS
VSS
DM6
VSS
VSS
VSS
VSS
VSS
SDA
SCL
VTT
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