DELL 1749 Schematics

A

1 1

B

C

D

E

Compal Confidential

2 2

NAT02 M/B Schematics Document

Intel Arrandale Processor with DDRIII + Ibex Peak-M

3 3

2009-11-26

REV:1.0

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/09/21 2010/09/21

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Page

NAT02 M/B LA-5154P Schematic

1 49Thursday, November 26, 2009

E

1.0

5

Block Diagram Compal confidential Model : NAT01

D D

CRT CONN

+5VS

LVDS CONN

+LCDVDD +3.3V_ALW

P.35

DP CONN

+5VS

P.37

HDMI CONN

+5VS

C C

To Card-reader subboard

8 IN 1 CONN

+3VS

IEEE1394

P.36

+3VS +1.8VS

FFS

+3VS

VGA

LVDS

DPD

DPB

HDMI Level Shift

CardBus

OZ888GS0

P.14

P.36

P.30

FAN

+5VS +3VS

4

P.14

+CPU_CORE

+1.1VS_VTT

Arrandale (UMA)

Processor

rPGA988A

FDI x8 (UMA)

100MHz

2.7GT/s

Ibex Peak-M

100MHz

PCI-Express x 8 (ABD PCIE1 2.5GT/S CKD PCIE1/2 2.5/5GT/S)

+1.05VS

page 15,16,17 18,19, 20,21,22,23

LPC BUS

+3VS 33MHz

3

Intel

page 5,6,7,8,9,10

Intel

PCH

DMI x4

100MHz

1GB/s x4

USBx14

SATA x 6

(GEN1 1.5GT/S ,GEN2 3GT/S)

HD Audio

SPI

SPI ROM x1 32Mbit

page 15

Clock Generator

IDT: 9LRS3199AKLFT SILEGO: SLG8SP587

133/120/100/96/14.318MHZ to PCH

48MHZ to CardReader

Memory BUS(DDRIII)

Dual Channel

1.5V DDRIII 800/1066/1333

6.4G/8.5G/10.6G

100M/133M/166M(CFD)

3.3V 48MHz

100MHz

3.3V 24MHz

2

page 13

Right Front Side.

Right behind side.

port 5

DDRIII-DIMM X2

BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 ,8

+1.5V

+0.75VS

USB Port X1

+5V_ALW

USB Port1 X1

+5V_ALW

Bluetooth

Touch Screen

Camera

P.11,12

P.30

P.32

P.30

Charge USB/E-SATA Ports X1

+5VALW

1

CPU XDP

133MHz

page 06

To Card-reader subboard

To Single USB subboard

P.30

Express Card

P.28

B B

RJ45

Mini Card 3

TV Tuner

+3VS

DC/DC Interface

A A

P.28 P.27 P.27

BATT IN

P.33 P.47

1.1VS_VTTPower Sequence

DC IN

5

RTL8111DL

+3VALW

Mini Card 2

WLAN

+3VS +1.5VS+1.5VS

USB[x]

P.45

P.40

P.24

PCIE1PCIE2PCIE3

Mini Card 1

WWAN

+3VS +1.5VS

USB[x]USB[x]

VCORE

CHARGER

1.5V/0.75V

P.46 P.44

3V/5V

GFX_Core/1.05V 1.05V/1.8V

4

Int.KBD & BL

P.42P.41

P.43P.48

ENE KBC

KB926QFD3

+RTC_CELL

+3VALW

P.31

SPI

SB3526

+3VS

To Cap Sensor subboard

page 32

Touch Pad

P.32P.32

Flash ROM

16Mx1sector

P.31

+3VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/09/21 2010/09/21

Compal Secret Data

Deciphered Date

Azalia Codec

92HD73C

+3VS +VDDA

AMP

MAX4411x2

HeadPhone & MIC Jack

2

PCI Express BUS

P.25

port 4

E-ODD

+3VS

+5VS

S-HDD-2

P.29 P.29 P.29

+5VS

AMP

MAX9736A

P.26

P.25

B+

AMP

MAX9736A

P.26

B+

Dig. MIC

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

NAT02 M/B LA-5154P Schematic

port 1port 0

S-HDD-1

+5VS

Speaker

Subwoofer

P.30

Block Diagrams

1

1.0

2 49Thursday, November 26, 2009

1.0

A

Voltage Rails

Power Plane Description

VIN

1 1

2 2

B+

+CPU_CORE

+VGFX_CORE

+0.75VS 0.75V switched power rail for DDR terminator

+1.05VS

+1.1VS_VTT 1.1V switched power rail (1.05 for AUB CPU) ON OFF OFF

+1.1VS

+1.5V 1.5V power rail for DDRIII ON ON OFF

+1.5VS

+1.8VS 1.8V switched power rail

+3VALW 3.3V always on power rail

+LAN_IO 3.3V power rail for LAN ON ON

+3VS

+5VALW

+5VS

B+_BIAS B+ always on power rail ON ON*

+RTCVCC RTC power

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for CPU

Core voltage for Graphic ON OFFOFF

1.05V switched power rail for PCH

1.1V power rail for PCIE of GUP

1.5V switched power rail

3.3V switched power rail

5V always on power rail

5V switched power rail

B

S1 S3 S5

N/A N/A N/A

ON

ON OFF

ON OFF OFF

ON

N/AN/AN/A

OFF

ON ON*

ON*

OFF

ON ON*

OFF

OFFON

ONON

Board ID

X00 X01 X02 MP X00 X01 X02 MP

C

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH HIGH HIGH HIGH

LOW

HIGH

LOWLOWLOW

HIGHHIGHHIGH

HIGH

LOW LOW LOW LOW

Board ID / SKU ID Table for AD channel

Vcc 3.3V +/- 5%

VGA

M96 M96 M96

M96 Madison Madison Madison Madison

100K +/- 1%Ra

Rb V min

AD_BID

0

8.2K +/- 1% 18K +/- 1% 33K +/- 1% 56K +/- 1% 100K +/- 1% 200K +/- 1%

NC

0.216 V 0.250 V 0.289 V

0.436 V

0.712 V

1.036 V

1.453 V 1.650 V 1.759 V

1.935 V

2.500 V

0 V

D

ON

OFF

ON

OFF

V typ

AD_BID

V

AD_BID

0 V 0.100 V

0.503 V

0.819 V

0.538 V

0.875 V

1.185 V 1.264 V

2.200 V

3.300 V

2.341 V

3.300 V

ON ON

ON

OFF

max

E

LOW

OFF

External PCI Devices

Device IDSEL#

REQ#/GNT#

Interrupts

USB Port Table

EC SM Bus1 address

3 3

Device

Smart Battery

Address Address

0001 011X b

EC SM Bus2 address

Device

WWAN

WLAN

Express Card

USB Port

0

1

2

3

4

5

6

7

Ibex SM Bus address

Device

Clock Generator (9LRS3191AKLFT, SLG8S P585)

DDR DIMM0

DDR DIMM1

Free Fall Sensor

4 4

CPU XDP

PCH XDP

XDCP_ISL90727

XDCP_ISL90728

A

Address

1101 0010b

1001 000Xb

1001 010Xb

remove

0101 110Xb

0111 110Xb

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

8

9

10

11

2009/09/21 2010/09/21

C

Device

USB&ESATA Reader/BD

USB board

WPAN WLAN WWAN

NC NC

Express

Touch screen Bluetooth

Camera

Compal Secret Data

Deciphered Date

D

BTO Option Table

BTO Item BOM Structure

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

Compal Electronics, Inc.

NAT02 M/B LA-5154P Schematic

Notes List

E

1.0

3 49Thursday, November 26, 2009

1.0

5

4

3

2

1

D D

SUSP#

TPS51117RGYR

(PU7)

SUSP#

ISL6268CAZ-T

(PU8)

ADAPTER

VR_ON

ISL62883HRZ-T (PU13)

BATTERY

B+

GFXVR_PWRGD

SYSON

ISL62881HRZ-T (PU22)

ISL6268CAZ-T (PU10)

C C

SUSP#

CHARGER

SUSP#

TPS51117RGYR (PU6)

TPS51427

2500mA

15000mA

65000mA

15000mA

12800mA

5700mA

+1.8VS

+1.1VS_VTT

+CPU_CORE

+GFX_CORE

+1.5V

+1.05VS

SUSP#

0 Ohm

SI4800BDY (U25)

RT9025 (PU12)

RT9026 (PU10)

+1.05VS_CK505

8881mA

+1.5VS

913mA

+1.1VS

?mA

+0.75VS

(PU5)

+5VALW

8400mA

RUNON

SI4800BDY (U22)

2000mA 8677mA160mA 20mA

USB_EN#

TPS2062ADR (U17)

EN_EOL#

SI3456BDY (Q3)

+LAN_IO

B B

+5VS

+5V_CHGUSB

EN_EOL#

RTL8111DL

FUSE

0 Ohm

+CRT_VCC

+AVDD_AUDIO

+5VS_KBL

(U9)

+LAN_VDD

+3VALW

SUSP

FBM-11-160808-601-T (L29)

+EC_AVCC

SUSP

SI4800BDY (U21)

+3VS

0 Ohm

+3VS_CK505

+DVDD_AUDIO

+3V_WLAN

VDDEN

SI2310BDS-T1-E3

(Q25)

+LCDVDD

EN_EOL#

SI2310BDS

(Q34)

+3VS_DELAY

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/09/21 2010/09/21

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Power Rail

NAT02 M/B LA-5154P Schematic

1

4 49Thursday, November 26, 2009

1.0

5

JCPU1A

DMI_PTX_HRX_N0<17> DMI_PTX_HRX_N1<17> DMI_PTX_HRX_N2<17> DMI_PTX_HRX_N3<17>

DMI_PTX_HRX_P0<17> DMI_PTX_HRX_P1<17> DMI_PTX_HRX_P2<17>

UMA

DMI_PTX_HRX_P3<17>

DMI_HTX_PRX_N0<17> DMI_HTX_PRX_N1<17> DMI_HTX_PRX_N2<17> DMI_HTX_PRX_N3<17>

DMI_HTX_PRX_P0<17> DMI_HTX_PRX_P1<17> DMI_HTX_PRX_P2<17> DMI_HTX_PRX_P3<17>

H_FDI_TXN0<17> H_FDI_TXN1<17> H_FDI_TXN2<17> H_FDI_TXN3<17> H_FDI_TXN4<17> H_FDI_TXN5<17> H_FDI_TXN6<17> H_FDI_TXN7<17>

H_FDI_TXP0<17> H_FDI_TXP1<17> H_FDI_TXP2<17> H_FDI_TXP3<17> H_FDI_TXP4<17> H_FDI_TXP5<17> H_FDI_TXP6<17> H_FDI_TXP7<17>

H_FDI_FSYNC0<17> H_FDI_FSYNC1<17>

H_FDI_LSYNC0<17> H_FDI_LSYNC1<17>

H_FDI_TXN0 H_FDI_TXN1 H_FDI_TXN2 H_FDI_TXN3 H_FDI_TXN4 H_FDI_TXN5 H_FDI_TXN6 H_FDI_TXN7

H_FDI_TXP0 H_FDI_TXP1 H_FDI_TXP2 H_FDI_TXP3 H_FDI_TXP4 H_FDI_TXP5 H_FDI_TXP6 H_FDI_TXP7

H_FDI_INT< 17>

D D

C C

B B

A24

DMI_RX#[0]

C23

DMI_RX#[1]

B22

DMI_RX#[2]

A21

DMI_RX#[3]

B24

DMI_RX[0]

D23

DMI_RX[1]

B23

DMI_RX[2]

A22

DMI_RX[3]

D24

DMI_TX#[0]

G24

DMI_TX#[1]

F23

DMI_TX#[2]

H23

DMI_TX#[3]

D25

DMI_TX[0]

F24

DMI_TX[1]

E23

DMI_TX[2]

G23

DMI_TX[3]

E22

FDI_TX#[0]

D21

FDI_TX#[1]

D19

FDI_TX#[2]

D18

FDI_TX#[3]

G21

FDI_TX#[4]

E19

FDI_TX#[5]

F21

FDI_TX#[6]

G18

FDI_TX#[7]

D22

FDI_TX[0]

C21

FDI_TX[1]

D20

FDI_TX[2]

C18

FDI_TX[3]

G22

FDI_TX[4]

E20

FDI_TX[5]

F20

FDI_TX[6]

G19

FDI_TX[7]

F17

FDI_FSYNC[0]

E17

FDI_FSYNC[1]

C17

FDI_INT

F18

FDI_LSYNC[0]

D17

FDI_LSYNC[1]

IC,AUB_CFD_rPGA,R0P9

CONN@

DMI Intel(R) FDI

PCI EXPRESS -- GRAPHICS

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RBIAS

PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]

PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]

PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]

PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

4

R605

B26 A26 B27 A25

K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31

J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30

L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26

L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25

PEG_IRCOMP

EXP_RBIAS

UMA Remove PCI E-16X

R605

1 2

R613

1 2

49.9_0402_1%~D

750_0402_1%~D

3

R1035

3.01K_0402_1%~D @

R1036

3.01K_0402_1%~D @

3.01K_0402_1%~D @ R1037

3.01K_0402_1%~D

R1038

3.01K_0402_1%~D

WW41 Recommend not pull down PCIE2.0 Jitter is over on ES1

H_DIMMA_REF<11> H_DIMMB_REF<12>

1 2

@R1037

@

1 2

@R1038

@

1 2

R212

R212 0_0402_5%~D

0_0402_5%~D

1 2 1 2

R213

0_0402_5%~D

2

JCPU1E

RSVD32

AP25

RSVD1

AL25

RSVD2

AL24

RSVD3

AL22

RSVD4

AJ33

RSVD5

AG9

RSVD6

M27

RSVD7

L28

RSVD8

J17

(SA_DIMM_VREF)

RSVD9

H17

(SB_DIMM_VREF)

RSVD10

G25

RSVD11

G17

RSVD12

E31

RSVD13

E30

RSVD14

CFG0

AM30 AM28 AP31

AL32

AL30 AM31 AN29 AM32 AK32 AK31 AK28

AJ28 AN30 AN32

AJ32

AJ29

AJ30 AK30

H16

B19 A19

A20 B20

AC9 AB9

A34 A33

C35 B35

U9

T9

C1 A3

J29 J28

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] RSVD_TP_86

RSVD15 RSVD16

RSVD17 RSVD18

RSVD19 RSVD20

RSVD21 RSVD22

RSVD_NCTF_23 RSVD_NCTF_24

RSVD26 RSVD27

RSVD_NCTF_28 RSVD_NCTF_29

RSVD_NCTF_30 RSVD_NCTF_31

RESERVED

CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18

@

@ @

@

RSVD33

RSVD34 RSVD35

RSVD36

RSVD_NCTF_37

RSVD38 RSVD39

RSVD_NCTF_40 RSVD_NCTF_41

RSVD_NCTF_42 RSVD_NCTF_43

RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52

RSVD53 RSVD_NCTF_54 RSVD_NCTF_55 RSVD_NCTF_56 RSVD_NCTF_57

RSVD58

RSVD_TP_59 RSVD_TP_60

KEY RSVD62 RSVD63 RSVD64 RSVD65

RSVD_TP_66 RSVD_TP_67 RSVD_TP_68 RSVD_TP_69 RSVD_TP_70 RSVD_TP_71 RSVD_TP_72 RSVD_TP_73 RSVD_TP_74 RSVD_TP_75

RSVD_TP_76 RSVD_TP_77 RSVD_TP_78 RSVD_TP_79 RSVD_TP_80 RSVD_TP_81 RSVD_TP_82 RSVD_TP_83 RSVD_TP_84 RSVD_TP_85

VSS

AJ13 AJ12

AH25 AK26

AL26 AR2

AJ26 AJ27

AP1 AT2

AT3 AR1

AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33 AT33 AT34 AP35 AR35 AR32

E15 F15 A2 D15 C15 AJ15 AH15

AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3

V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9

AP34

@

@ @

@

@ @

@

R649

R649 0_0402_5%~D

0_0402_5%~D

R648

R648 0_0402_5%~D

0_0402_5%~D

PAD

PAD PAD

PAD

PAD PAD

PAD

1

T97

T97 T98

T98

T99

T99 T100

T100

T101

T102

@

12

@

12

IC,AUB_CFD_rPGA,R0P9

CONN@

CFG0 - PCI-Expr ess Configurati on Select

*1:Single PEG 0:Bifurcation e nabled

CFG3 - PCI-Expr ess Static Lane Reversal

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/09/21 2010/09/21

Compal Secret Data

*1 :Normal Oper ation 0 :Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

CFG4 - Display Port Presence

*1:Disabled; No Physical Displ ay Port attached to Embedded Displa y Port 0:Enabled; An e xternal Display Port device is co nnected to the Embedded Display Port

*:Default

Compal Electronics, Inc.

PROCESSOR (1/6) DMI,FDI,PEG

NAT02 M/B LA-5154P Schematic

1

5 49Thursday, November 26, 2009

1.0

5

JCPU1B

H_COMP3

H_COMP2

H_COMP1

H_COMP0

SKTOCC#_R

@

PAD

T5

R1039

1 2

0_0402_5%~D

R1042

1 2

0_0402_5%~D

R300

R300 0_0402_5%~D

0_0402_5%~D

R263

R263 0_0402_5%~D

0_0402_5%~D

R1043

R1043 0_0402_5%~D

0_0402_5%~D

R1045

1 2

0_0402_5%~D

R316

R316 0_0402_5%~D

0_0402_5%~D

R289

1 2

1.5K_0402_1%~D

T5

1 2

H_CATERR#

H_PECI_R

H_PROCHOT#

H_THERMTRIP#_R

H_CPURST#

H_PM_SYNC_R

H_CPUPWRGD_1

H_CPUPWRGD_0

PM_DRAM_PWRGD_R

PLT_RST#_R

12

R1052

R1052 750_0402_1%~D

750_0402_1%~D

D D

H_PECI<20>

H_PROCHOT#<46>

H_THERMTRIP#<20>

H_PM_SYNC<17>

C C

H_CPUPWRGD<20>

PM_DRAM_PWRGD<17>

H_VTTPWRGD<45>

H_PWRGD_XDP H_PWRGD_XDP_R

PLT_RST#<19,24,27,28,30,31>

JCPU1B

AT23

COMP3

AT24

COMP2

G16

COMP1

AT26

COMP0

AH24

SKTOCC#

AK14

CATERR#

AT15

PECI

AN26

PROCHOT #

AK15

THERMTR IP#

AP26

RESET_O BS#

AL15

PM_SYNC

AN14

VCCPW RGOOD_1

AN27

VCCPW RGOOD_0

AK13

SM_DRAM PWROK

AM15

VTTPW RGOOD

AM26

TAPPW RGOOD

AL14

RSTIN#

IC,AUB_CFD_rPGA,R0P9

CONN@

4

MISC THERMAL

DPLL_RE F_SSCLK

DPLL_RE F_SSCLK#

CLOCKS

SM_DRAM RST#

SM_RCOM P[0] SM_RCOM P[1] SM_RCOM P[2]

PM_EXT_ TS#[0] PM_EXT_ TS#[1]

DDR3

MISC

DDR3

MISC

PWR MANAGEMENT

JTAG & BPM

BCLK

BCLK#

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK #

PRDY#

PREQ#

TCK

TMS

TRST#

TDO

TDI_M

TDO_M

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

A16 B16

AR30 AT30

E16 D16

A18 A17

F6

AL1 AM1 AN1

AN15 AP15

AT28 AP27

AN28 AP28 AT27

AT29

TDI

AR27 AR29 AP29

AN25

AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23

3

CLK_CPU_BCLK_R CLK_CPU_BCLK#_R

CLK_CPU_ITP_R CLK_CPU_ITP#_R

CLK_CPU_DMI_R CLK_CPU_DMI#_R

CLK_CPU_DP_R CLK_CPU_DP#_R

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

PM_EXTTS#0 PM_EXTTS#1_R

XDP_PRDY# XDP_PREQ#

XDP_TCLK XDP_TMS XDP_TRST#

XDP_TDI_R XDP_TDO_R XDP_TDI_M XDP_TDO_M

XDP_DBR#_R

R1060 0_0402_5%~DR1060 0_0402_5%~D

R1044 0_0402_5%~DR1044 0_0402_5%~D R1046 0_0402_5%~DR1046 0_0402_5%~D R1047 0_0402_5%~DR1047 0_0402_5%~D R1048 0_0402_5%~DR1048 0_0402_5%~D R1049 0_0402_5%~DR1049 0_0402_5%~D R1050 0_0402_5%~DR1050 0_0402_5%~D R1051 0_0402_5%~DR1051 0_0402_5%~D R284 0_0402_5%~DR284 0_0402_5%~D

R609 0_0402_5%~DR609 0_0402_5%~D

1 2

R610 0_0402_5%~DR610 0_0402_5%~D

1 2

R655 0_0402_5%~DR655 0_0402_5%~D

1 2

R654 0_0402_5%~DR654 0_0402_5%~D

1 2

R606 0_0402_5%~DR606 0_0402_5%~D

1 2

R607 0_0402_5%~DR607 0_0402_5%~D

1 2

RU83 0_0402_5%~DRU83 0_0402_5%~D

1 2

RU84 0_0402_5%~DRU84 0_0402_5%~D

1 2

R1121 0_0402_5%~D@ R1121 0_0402_5%~D@

1 2

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

G

2

13

D

S

D

S

1 2

R1040 10K_0402_5%~DR1040 10K_0402_5%~D

1 2

R288 10K_0402_5%~DR288 10K_0402_5%~D

1 2

R1041 0_0402_5%~DR1041 0_0402_5%~D

1 2

XDP_DBRESET#

XDP_OBS0XDP_OBS0_R XDP_OBS1XDP_OBS1_R XDP_OBS2XDP_OBS2_R XDP_OBS3XDP_OBS3_R XDP_OBS4XDP_OBS4_R XDP_OBS5XDP_OBS5_R XDP_OBS6XDP_OBS6_R XDP_OBS7XDP_OBS7_R

CLK_CPU_XDP CLK_CPU_XDP#

Q36BSS138_SOT23~D

CLK_CPU_BCLK <20> CLK_CPU_BCLK# <20>

CLK_CPU_DMI <16> CLK_CPU_DMI# <16>

CLK_CPU_DP <16> CLK_CPU_DP# <16>

DDR_RST_GATE <11,12,20>

SM_DRAMRST# <11,12>

+1.1VS_VTT

PM_EXTTS#0_1 <11,12>

XDP_DBRESET# <17>

2

+3VALW

C1142

R1136

1 2

10K_0402_5%~D

1.5V_PWRGD<44>

74AHC1G08GW_SOT353-5~D

XDP_TMS XDP_TDI_R XDP_PREQ# XDP_TCLK

XDP_TRST#

XDP_TDI_R XDP_TDI

XDP_TDI_M XDP_TDO_R

C1142

1 2

0.1U_0402_10V6K~D

5

U69

1

P

IN1

4

O

1.5K_0402_1%~D

IN2

G

3

1 2 1 2 1 2 1 2

1 2

1 2 1 2

@

1 2 1 2

1.5K_0402_1%~D

2

R657 51_0402_1%~D@R657 51_0402_1%~D@ R653 51_0402_1%~D@R653 51_0402_1%~D@

R656 51_0402_1%~D@R656 51_0402_1%~D@

R669 51_0402_1%~D@R669 51_0402_1%~D@

R651 51_0402_1%~DR651 51_0402_1%~D

R661 0_0402_5%~DR661 0_0402_5%~D

R662 0_0402_5%~D@R662 0_0402_5%~D@

12

R663

R663 0_0402_5%~D

0_0402_5%~D

R667 0_0402_5%~D

R667 0_0402_5%~D R668 0_0402_5%~DR668 0_0402_5%~D

1

R290

12

750_0402_1%~D

+1.1VS_VTT

PM_DRAM_PWRGD_R

R1103

1 2

XDP_TDOXDP_TDO_M

JTAG MAPPING

Scan Chain (Default)

CPU Only

GMCH Only

STUFF -> R653, R657, R662 NO STUFF -> R655, R660

STUFF -> R653, R655 NO STUFF -> R657, R660, R662

STUFF -> R660, R662 NO STUFF -> R653, R655, R657

WW51.4 CRB Board Rework/workaround- Rev 0.1 has changed the resistors in RSTIN#

PAD

PAD PAD

PAD

XDP_PREQ# XDP_PRDY#

XDP_OBS0 XDP_OBS1

XDP_OBS2 XDP_OBS3

XDP_OBS4 XDP_OBS5

XDP_OBS6 XDP_OBS7

H_PWRGOOD_R PBTN_OUT#_XDP

H_PWRGD_XDP

SMB_DATA_S3

@

SMB_CLK_S3

@

XDP_TCLK

2009/09/21 2010/09/21

3

B B

+1.5V

PM_DRAM_PWRGD_R

A A

5

[Calpella] Platform – Design Guide Addendum / Update – Rev. 1.52

12

R1054

@R1054

@

1.1K_0402_1%~D

12

R1055

@R1055

@

3K_0402_1%~D

H_CATERR# H_PROCHOT# H_CPURST#

H_COMP0 H_COMP1 H_COMP2 H_COMP3

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

PCH_SMBDATA<11,12,16>

PCH_SMBCLK<11,12,16>

R1053 49.9_0402_1%~DR1053 49.9_0402_1%~D R1061 68_0402_5%~DR1061 68_0402_5%~D R1062 68_0402_5%~D@R1062 68_0402_5%~D@

R650 49.9_0402_1%~DR650 49.9_0402_1%~D

1 2

R234 49.9_0402_1%~DR234 49.9_0402_1%~D

1 2

R659 20_0402_1%~DR659 20_0402_1%~D

1 2

R658 20_0402_1%~DR658 20_0402_1%~D

1 2

R645 100_0402_1%~DR645 100_0402_1%~D

1 2

R646 24.9_0402_1%~DR646 24.9_0402_1%~D

1 2

R647 130_0402_1%~DR647 130_0402_1%~D

1 2

1 3

1 2 1 2 1 2

+3VS

2

G

D

S

D

S

Q52

Q52 2N7002LT1G_SOT23-3

2N7002LT1G_SOT23-3

+3VS

2

G

D

S

D

S

Q53

Q53 2N7002LT1G_SOT23-3

2N7002LT1G_SOT23-3

R480

4.7K_0402_5%~D

1 2

SMB_DATA_S3

R1099

4.7K_0402_5%~D

1 2

SMB_CLK_S3

4

+1.1VS_VTT

+3VS

PBTN_OUT#<17,31>

+1.1VS_VTT

C315

0.1U_0402_16V4Z~D

@

R365

R365 1K_0402_5%~D

1K_0402_5%~D

H_CPUPWRGD

1

2

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF CO MPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF CO MPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

1 2 1 2

R363 0_0402_5%~DR363 0_0402_5%~D

T103

T103 T104

T104

Issued Date

XDP Connector

JP8

1

GND0

3

OBSFN_A 0

5

OBSFN_A 1

7

GND2

9

OBSDATA _A0

11

OBSDATA _A1

13

GND4

15

OBSDATA _A2

17

OBSDATA _A3

19

GND6

21

OBSFN_B 0

23

OBSFN_B 1

25

GND8

27

OBSDATA _B0

29

OBSDATA _B1

31

GND10

33

OBSDATA _B2

35

OBSDATA _B3

37

GND12

39

PWRG OOD/HOOK0

41

HOOK1

43

VCC_OBS _AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

Compal Secret Data

SAMTE_BSH-030-01-L-D-ACONN@

Deciphered Date

GND1 OBSFN_C 0 OBSFN_C 1

GND3

OBSDATA _C0 OBSDATA _C1

GND5

OBSDATA _C2 OBSDATA _C3

GND7 OBSFN_D 0 OBSFN_D 1

GND9

OBSDATA _D0 OBSDATA _D1

GND11 OBSDATA _D2 OBSDATA _D3

GND13

ITPCLK/HOO K4

ITPCLK#/HO OK5

VCC_OBS _CD

RESET#/H OOK6

DBR#/HOO K7

GND15

TRST#

TMS

GND17

TD0

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56

TDI

58 60

2

H_RESET#_R

CLK_CPU_XDP CLK_CPU_XDP#

H_RESET#_R XDP_DBRESET#

XDP_TDO XDP_TRST# XDP_TDI XDP_TMS

R1063

R1063 1K_0402_5%~D

1K_0402_5%~D

1 2 1 2

R362

R362 0_0402_5%~D

0_0402_5%~D

1 2

Title

Size Document Number Rev

Custom

Date: Sheet of

H_CPURST#

@

R1064

R1064 1K_0402_5%~D

1K_0402_5%~D

R1065

R1065 51_0402_1%~D

51_0402_1%~D

Compal Electronics, Inc.

PROCESSOR (2/6) CLK,JTAG

NAT02 M/B LA-5154P Schematic

PCI_PLTRST# <19>

+1.1VS_VTT

Leakage Issue

+3VS

+1.1VS_VTT

1

6 49Thursday, November 26, 2009

1.0

5

JCPU1C

C10

D10

H10

G10

AH5 AF5 AK6 AK7 AF6 AG5

AJ10

AL10 AK12

AK8

AK11

AN8 AM10 AR11

AL11

AM9

AN9

AT11

AP12 AM12 AN12 AM13

AT14

AT12

AL13 AR14

AP14

AC3 AB2

AE1 AB3 AE9

A10

B10

E10

F10

J10

AJ7 AJ6

AJ9

AL7

AL8

C7 A7

A8 D8

E6

E9 B7 E7 C6

G8 K7

G7

M6 M8

K8 N8 P9

U7

F7

J8

J7

L7

L9 L6

JCPU1C

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

DDR SYSTEM MEMORY A

DDR_A_D [0..63]<11> DDR_A_D M[0..7]<11>

DDR_A_D QS#[0..7]<1 1>

DDR_A_D QS[0..7]<11>

DDR_A_M A[0..15]< 11>

DDR_A_D 0 DDR_A_D 1

D D

C C

B B

DDR_A_B S0<11> DDR_A_B S1<11> DDR_A_B S2<11>

DDR_A_C AS#<11> DDR_A_R AS#<11>

DDR_A_W E#<11>

DDR_A_D 2 DDR_A_D 3 DDR_A_D 4 DDR_A_D 5 DDR_A_D 6 DDR_A_D 7 DDR_A_D 8 DDR_A_D 9 DDR_A_D 10 DDR_A_D 11 DDR_A_D 12 DDR_A_D 13 DDR_A_D 14 DDR_A_D 15 DDR_A_D 16 DDR_A_D 17 DDR_A_D 18 DDR_A_D 19 DDR_A_D 20 DDR_A_D 21 DDR_A_D 22 DDR_A_D 23 DDR_A_D 24 DDR_A_D 25 DDR_A_D 26 DDR_A_D 27 DDR_A_D 28 DDR_A_D 29 DDR_A_D 30 DDR_A_D 31 DDR_A_D 32 DDR_A_D 33 DDR_A_D 34 DDR_A_D 35 DDR_A_D 36 DDR_A_D 37 DDR_A_D 38 DDR_A_D 39 DDR_A_D 40 DDR_A_D 41 DDR_A_D 42 DDR_A_D 43 DDR_A_D 44 DDR_A_D 45 DDR_A_D 46 DDR_A_D 47 DDR_A_D 48 DDR_A_D 49 DDR_A_D 50 DDR_A_D 51 DDR_A_D 52 DDR_A_D 53 DDR_A_D 54 DDR_A_D 55 DDR_A_D 56 DDR_A_D 57 DDR_A_D 58 DDR_A_D 59 DDR_A_D 60 DDR_A_D 61 DDR_A_D 62 DDR_A_D 63

DDR_A_B S0 DDR_A_B S1 DDR_A_B S2

DDR_A_C AS# DDR_A_R AS# DDR_A_W E#

SA_CK[0]

SA_CK#[0]

SA_CKE[0]

SA_CK[1]

SA_CK#[1]

SA_CKE[1]

SA_CS#[0] SA_CS#[1]

SA_ODT[0] SA_ODT[1]

SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

4

AA6 AA7 P7

Y6 Y5 P6

AE2 AE8

AD8 AF9

B9 D7 H7 M7 AG6 AM7 AN10 AN13

C9 F8 J9 N9 AH7 AK9 AP11 AT13

C8 F9 H9 M9 AH8 AK10 AN11 AR13

Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9

DDR_A_D M0 DDR_A_D M1 DDR_A_D M2 DDR_A_D M3 DDR_A_D M4 DDR_A_D M5 DDR_A_D M6 DDR_A_D M7

DDR_A_D QS#0 DDR_A_D QS#1 DDR_A_D QS#2 DDR_A_D QS#3 DDR_A_D QS#4 DDR_A_D QS#5 DDR_A_D QS#6 DDR_A_D QS#7

DDR_A_D QS0 DDR_A_D QS1 DDR_A_D QS2 DDR_A_D QS3 DDR_A_D QS4 DDR_A_D QS5 DDR_A_D QS6 DDR_A_D QS7

DDR_A_M A0 DDR_A_M A1 DDR_A_M A2 DDR_A_M A3 DDR_A_M A4 DDR_A_M A5 DDR_A_M A6 DDR_A_M A7 DDR_A_M A8 DDR_A_M A9 DDR_A_M A10 DDR_A_M A11 DDR_A_M A12 DDR_A_M A13 DDR_A_M A14 DDR_A_M A15

DDR_A_C LK0 <11> DDR_A_C LK0# <11> DDR_A_C KE0 <11>

DDR_A_C LK1 <11> DDR_A_C LK1# <11> DDR_A_C KE1 <11>

DDR_A_C S0# <11> DDR_A_C S1# <11>

DDR_A_O DT0 <1 1> DDR_A_O DT1 <1 1>

3

DDR_B_D [0..63]<12>

DDR_B_D M[0..7]<12>

DDR_B_D QS#[0..7]<1 2>

DDR_B_D QS[0..7]<12> DDR_B_M A[0..15]<12>

DDR_B_D 0 DDR_B_D 1 DDR_B_D 2 DDR_B_D 3 DDR_B_D 4 DDR_B_D 5 DDR_B_D 6 DDR_B_D 7 DDR_B_D 8 DDR_B_D 9 DDR_B_D 10 DDR_B_D 11 DDR_B_D 12 DDR_B_D 13 DDR_B_D 14 DDR_B_D 15 DDR_B_D 16 DDR_B_D 17 DDR_B_D 18 DDR_B_D 19 DDR_B_D 20 DDR_B_D 21 DDR_B_D 22 DDR_B_D 23 DDR_B_D 24 DDR_B_D 25 DDR_B_D 26 DDR_B_D 27 DDR_B_D 28 DDR_B_D 29 DDR_B_D 30 DDR_B_D 31 DDR_B_D 32 DDR_B_D 33 DDR_B_D 34 DDR_B_D 35 DDR_B_D 36 DDR_B_D 37 DDR_B_D 38 DDR_B_D 39 DDR_B_D 40 DDR_B_D 41 DDR_B_D 42 DDR_B_D 43 DDR_B_D 44 DDR_B_D 45 DDR_B_D 46 DDR_B_D 47 DDR_B_D 48 DDR_B_D 49 DDR_B_D 50 DDR_B_D 51 DDR_B_D 52 DDR_B_D 53 DDR_B_D 54 DDR_B_D 55 DDR_B_D 56 DDR_B_D 57 DDR_B_D 58 DDR_B_D 59 DDR_B_D 60 DDR_B_D 61 DDR_B_D 62 DDR_B_D 63

DDR_B_B S0<12> DDR_B_B S1<12> DDR_B_B S2<12>

DDR_B_C AS#<12> DDR_B_R AS#<12>

DDR_B_W E#<12>

DDR_B_BS0 DDR_B_B S1 DDR_B_B S2

DDR_B_C AS# DDR_B_R AS# DDR_B_W E#

AG1

AG4 AG3

AM6

AM4 AM3

AR10

AT10

AF3

AJ3

AK1

AJ4 AH4 AK3 AK4

AN2 AK5 AK2

AP3 AN5 AT4 AN6 AN4 AN3 AT5 AT6 AN7 AP6 AP8 AT9 AT7 AP9

AB1

AC5

AC6

B5 A5 C3 B3 E4 A6 A4 C4 D1 D2 F2 F1 C2 F5 F3 G4 H6 G2

J6

J3 G1 G5

J2

J1

J5 K2 L3

M1

K5 K4

M4 N5

W5

R7

Y7

JCPU1D

SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

SB_BS[0] SB_BS[1] SB_BS[2]

SB_CAS# SB_RAS# SB_WE#

2

W8

SB_CK[0]

W9

SB_CK#[0]

M3

SB_CKE[0]

V7

SB_CK[1]

V6

SB_CK#[1]

M2

SB_CKE[1]

AB8

SB_CS#[0]

AD6

SB_CS#[1]

AC7

SB_ODT[0]

AD1

SB_ODT[1]

DDR_B_D M0

D4

SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

DDR SYSTEM MEMORY - B

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

E1 H3 K1 AH1 AL2 AR4 AT8

D5 F4 J4 L4 AH2 AL4 AR5 AR8

C5 E3 H4 M5 AG2 AL5 AP5 AR7

U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1

DDR_B_D M1 DDR_B_D M2 DDR_B_D M3 DDR_B_D M4 DDR_B_D M5 DDR_B_D M6 DDR_B_D M7

DDR_B_D QS#0 DDR_B_D QS#1 DDR_B_D QS#2 DDR_B_D QS#3 DDR_B_D QS#4 DDR_B_D QS#5 DDR_B_D QS#6 DDR_B_D QS#7

DDR_B_D QS0 DDR_B_D QS1 DDR_B_D QS2 DDR_B_D QS3 DDR_B_D QS4 DDR_B_D QS5 DDR_B_D QS6 DDR_B_D QS7

DDR_B_M A0 DDR_B_M A1 DDR_B_M A2 DDR_B_M A3 DDR_B_M A4 DDR_B_M A5 DDR_B_M A6 DDR_B_M A7 DDR_B_M A8 DDR_B_M A9 DDR_B_M A10 DDR_B_M A11 DDR_B_M A12 DDR_B_M A13 DDR_B_M A14 DDR_B_M A15

1

DDR_B_C LK0 <12> DDR_B_C LK0# <12> DDR_B_C KE0 <12>

DDR_B_C LK1 <12> DDR_B_C LK1# <12> DDR_B_C KE1 <12>

DDR_B_C S0# <12> DDR_B_C S1# <12>

DDR_B_O DT0 <1 2> DDR_B_O DT1 <1 2>

IC,AUB_CFD _rPGA,R0P9

CONN@

A A

Security Class ification

2009/09/ 21 2010/09/ 21

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/09/ 21 2010/09/ 21

3

Compal Secret Data

Deciphered Date

IC,AUB_CFD _rPGA,R0P9

CONN@

2

Compal Electronics, Inc.

Title

PROCESSOR (3/6) DDRIII

Size Document Num ber Rev

B

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

NAT02 M/B LA-5154P Schematic

1

of

7 49Thursday, November 26, 2 009

1.0

5

JCPU1F

+CPU_CORE

WW15 MOW

48A Continuous 18A

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

D D

C C

B B

A A

AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26

VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

1.1V RAIL POWER

CPU CORE SUPPLY

POWER

CPU VIDS

SENSE LINES

Peak 21A

VTT0_1 VTT0_2 VTT0_3 VTT0_4 VTT0_5 VTT0_6 VTT0_7 VTT0_8

VTT0_9 VTT0_10 VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32

VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

PROC_DPRSLPVR

VTT_SELECT

ISENSE

VCC_SENSE

VSS_SENSE

VTT_SENSE

VSS_SENSE_VTT

4

AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15

AN33

PSI#

AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34

H_VTTVID1

G15

H_VTTVID1 = low, 1.1V

H_VTTVID1 = high, 1.05V

AN35

1 2

C1557 1000P_0402_50 V7K~D@C1557 1000P_0402_50V7K~D@

VCCSENSE_R

AJ34

VSSSENSE_R

AJ35

B15

VSS_SENSE_VTT

A15

10U_0805_6.3V6M~D

1

C183

C174

2

10U_0805_6.3V6M~D

C222

22U_0805_6.3V6M~OK

10U_0805_6.3V6M~D

330U_X_2VM_R6M~OK

1

+

C1010

C1009

2

330U_X_2VM_R6M~OK

22U_0805_6.3V6M~OK

1

C240

2

IMVP_IMON <46>

R0.3 modify

R641 0_0402_5%~DR641 0_0402_5%~D

1 2

R642 0_0402_5%~DR642 0_0402_5%~D

1 2

R608 0_0402_5%~DR608 0_0402_5%~D

1 2

close to CPU side.

3

10U_0805_6.3V6M~D

1

C192

2

+1.1VS_VTT

1

+

C1011

2

330U_X_2VM_R6M~OK

+1.1VS_VTT

10U_0805_6.3V6M~D

1

C203

C195

2

10U_0805_6.3V6M~D

1

+

R1.0 modify

@

2

H_PSI# <46>

CPU_VID0 <46> CPU_VID1 <46> CPU_VID2 <46> CPU_VID3 <46> CPU_VID4 <46> CPU_VID5 <46> CPU_VID6 <46> H_DPRSLPVR <46>

H_VTTVID1 <45>

1

C211

2

10U_0805_6.3V6M~D

CSC (Curre nt Sense C onfigurati on) 8/25

VTT Rail

Auburndale +1.1VS_VT T=1.05V Clarksfiel d +1.1VS_V TT=1.1V

1 2

R643 100_0402_1%~DR643 100_0402_1%~D

VCCSENSE VSSSENSE

1 2

VTT_SENSE <45>

R644 100_0402_1%~DR644 100_0402_1%~D

+1.1VS_VTT

1

C159

2

CPU_VID0

CPU_VID1

CPU_VID2

CPU_VID3

CPU_VID4

CPU_VID5

CPU_VID6

H_DPRSLPVR

H_PSI#

10U_0805_6.3V6M~D

R1066 1K_0402_1%~DR1066 1K_0402_1%~D

1 2

R1067 1K_0402_1%~D@R10 67 1K_0402_1%~D@

1 2

R1068 1K_0402_1%~DR1068 1K_0402_1%~D

1 2

R1069 1K_0402_1%~D@R10 69 1K_0402_1%~D@

1 2

R1070 1K_0402_1%~DR1070 1K_0402_1%~D

1 2

R1071 1K_0402_1%~D@R10 71 1K_0402_1%~D@

1 2

R343 1K_0402_1%~D@R343 1K_0402_1%~D@

1 2

R1072 1K_0402_1%~DR1072 1K_0402_1%~D

1 2

R1073 1K_0402_1%~D@R10 73 1K_0402_1%~D@

1 2

R1074 1K_0402_1%~DR1074 1K_0402_1%~D

1 2

R1075 1K_0402_1%~DR1075 1K_0402_1%~D

1 2

R1076 1K_0402_1%~D@R10 76 1K_0402_1%~D@

1 2

R1077 1K_0402_1%~D@R10 77 1K_0402_1%~D@

1 2

R1078 1K_0402_1%~DR1078 1K_0402_1%~D

1 2

R347 1K_0402_1%~DR347 1K_0402_1%~D

1 2

R1079 1K_0402_1%~D@R10 79 1K_0402_1%~D@

1 2

R348 1K_0402_1%~D@R348 1K_0402_1%~D@

1 2

R1080 1K_0402_1%~DR1080 1K_0402_1%~D

1 2

470U_D2_2VM_R4.5M~OK

+CPU_CORE

VCCSENSE <46>

VSSSENSE <46>

+CPU_CORE

1

C191

2

+1.1VS_VTT

+CPU_CORE

C1044

2

10U_0805_6.3V6M~D

1

C201

2

10U_0805_6.3V6M~D

(Place these capacitors between inductor and socket on Bottom)

10U_0805_6.3V6M~D

4 x 470uF(4.5mohm@100kHz; 4.0mohm@SRF)

1

+

2

C251

470U_D2_2VM_R4.5M~OK

TOP side (under inductor)

10U_0805_6.3V6M~D

1

2

+CPU_CORE

1

2

1

+

2

+CPU-CORE Decoupling SPCAP,Polymer

MLCC 0805 X5R

1

C213

2

10U_0805_6.3V6M~D

1

C185

2

(Place these capacitors under CPU socket, top layer)

+CPU_CORE

22U_0805_6.3V6M~OK

1

C1034

2

22U_0805_6.3V6M~OK

(Place these capacitors on CPU cavity, Bottom Layer)

+CPU_CORE

22U_0805_6.3V6M~OK

1

C1039

2

22U_0805_6.3V6M~OK

C1012

470U_D2_2VM_R4.5M~OK

1

C233

C194

C1035

C1040

(Place these capacitors on CPU cavity, Bottom Layer)

C245

2

10U_0805_6.3V6M~D

1

C199

2

10U_0805_6.3V6M~D

1

C1036

2

22U_0805_6.3V6M~OK

1

C1041

2

22U_0805_6.3V6M~OK

1

+

2

C533

470U_D2_2VM_R4.5M~OK

1

2

1

2

C,uF

4X470uF 4m ohm/4

16X22uF

16X10uF 3m ohm/16

10U_0805_6.3V6M~D

1

C190

2

1

C208

2

10U_0805_6.3V6M~D

22U_0805_6.3V6M~OK

1

C1037

2

22U_0805_6.3V6M~OK

1

C1042

2

1

+

2

470U_D2_2VM_R4.5M~OK

ESR, mohm

3m ohm/12

1

C200

10U_0805_6.3V6M~D

C214

1

C1062

2

1

C1063

2

1

+

2

1

2

1

2

22U_0805_6.3V6M~OK

470U_D2_2VM_R4.5M~OK

1

2

1

2

22U_0805_6.3V6M~OK

C263

@

Stuffing Option

2X470uF

10U_0805_6.3V6M~D

C212

C223

10U_0805_6.3V6M~D

1

C1038

2

1

C1043

2

C167

@

1

C232

2

1

C239

2

1

+

2

Security Classification

IC,AUB_CFD_rPGA,R0P9

CONN@

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/09/21 2010/09/21

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR (4/6) PWR,Bypass

NAT02 M/B LA-5154P Schematic

8 49Thursday, November 26, 2009

1

1.0

5

4

3

2

1

UMA

+VGFX_C ORE

JCPU1G

330U_X_ 2VM_R6M~OK

1

CU51

@+CU51

D D

C C

B B

@

2

1

+

CU52

2

330U_X_ 2VM_R6M~OK

22U_080 5_6.3V6M~OK

22U_0805_6.3V6M~OK

CU4

1

2

+1.1VS_V TT

C179

+1.1VS_V TT

C177

22U_0805_6.3V6M~OK

1

2

1

2

1

2

10U_0805_6.3V6M~D

CU5

CU1

1

2

1

C178

22U_080 5_6.3V6M~OK

2

1

C176

22U_080 5_6.3V6M~OK

2

10U_0805_6.3V6M~D

CU6

JCPU1G

AT21

VAXG1

AT19

VAXG2

AT18

VAXG3

AT16

VAXG4

AR21

VAXG5

AR19

VAXG6

AR18

VAXG7

AR16

VAXG8

AP21

VAXG9

AP19

VAXG10

AP18

VAXG11

AP16

VAXG12

AN21

VAXG13

AN19

VAXG14

AN18

VAXG15

AN16

VAXG16

AM21

VAXG17

AM19

VAXG18

AM18

VAXG19

AM16

VAXG20

AL21

VAXG21

AL19

VAXG22

AL18

VAXG23

AL16

VAXG24

AK21

VAXG25

AK19

VAXG26

AK18

VAXG27

AK16

VAXG28

AJ21

VAXG29

AJ19

VAXG30

AJ18

VAXG31

AJ16

VAXG32

AH21

VAXG33

AH19

VAXG34

AH18

VAXG35

AH16

VAXG36

J24

VTT1_45

J23

VTT1_46

H25

VTT1_47

K26

VTT1_48

J27

VTT1_49

J26

VTT1_50

J25

VTT1_51

H27

VTT1_52

G28

VTT1_53

G27

VTT1_54

G26

VTT1_55

F26

VTT1_56

E26

VTT1_57

E25

VTT1_58

IC,AUB_CFD _rPGA,R0P9

CONN@

15A

VAXG_SENSE

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3]

3A

GRAPHICS VIDs

GFX_VID[4] GFX_VID[5] GFX_VID[6]

GFX_VR_EN

GFX_DPRSLPVR

GFX_IMON

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18

DDR3 - 1.5V RAILS

VTT0_59 VTT0_60 VTT0_61 VTT0_62

VTT1_63 VTT1_64 VTT1_65

1.1V1.8V

VTT1_66 VTT1_67 VTT1_68

VCCPLL1 VCCPLL2 VCCPLL3

GRAPHICS

FDI PEG & DMI

POWER

0.6A

11/17 follow In tel suggest to change RU93 to 470 ohm

UMA

AR22 AT22

AM22 AP22 AN22 AP23 AM23 AP24 AN24

AR25 AT25 AM24

AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1

P10 N10 L10 K10

J22 J20 J18 H21 H20 H19

L26 L27 M26

VCC_AXG _SENSE <48 > VSS_AXG _SENSE <48>

GFXVR_V ID_0 <48 > GFXVR_V ID_1 <48 > GFXVR_V ID_2 <48 > GFXVR_V ID_3 <48 > GFXVR_V ID_4 <48 > GFXVR_V ID_5 <48 > GFXVR_V ID_6 <48 >

GFXVR_D PRSLPVR_R

C193

1U_0402 _6.3V4Z~D

+1.1VS_V TT

1

2

+1.8VS_V CCSFR

C175

1U_0402 _6.3V4Z~D

RU93 470_0402_5%~DRU93 470 _0402_5%~D

1 2

RU1 0_0402_5%~DRU1 0_ 0402_5%~D

1U_0402 _6.3V4Z~D

1

C196

2

+1.1VS_V TT

C158

22U_080 5_6.3V6M~OK

1

C182

2

1U_0402 _6.3V4Z~D

1

C202

C209

2

1U_0402 _6.3V4Z~D

1

C160

10U_080 5_6.3V6M~D

2

2.2U_060 3_6.3V6K~D

1

C180

C168

2

4.7U_080 5_10V4Z~D

GFXVR_E N < 48> GFXVR_D PRSLPVR <48> GFXVR_IMO N <48>

22U_080 5_6.3V6M~OK

1

C184

C216

2

1U_0402 _6.3V4Z~D

1

C165

2

22U_080 5_6.3V6M~OK

+1.5V_CP U_DDR +1.5V

1

C224

2

22U_080 5_6.3V6M~OK

R228

0.022_08 05_1%~OK

1 2

C1033

1 2

0.1U_040 2_16V7K~D

C1143

1 2

0.1U_040 2_16V7K~D

C1144

1 2

0.1U_040 2_16V7K~D

C1145

1 2

0.1U_040 2_16V7K~D

PJP12

PJP12 JUMP_43 X118@

JUMP_43 X118@

2

1

+

C250

2

330U_D2_2V_Y~OK

+1.8VS

112

PJP13

PJP13 JUMP_43 X118@

JUMP_43 X118@

112

PJP14

PJP14 JUMP_43 X118@

JUMP_43 X118@

112

2

A A

Security Class ification

2009/09/ 21 2010/09/ 21

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/09/ 21 2010/09/ 21

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PROCESSOR (5/6) PWR

Size Document Num ber Rev

Custom

NAT02 M/B LA-5154P Schematic

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

9 49Thursday, November 26, 2 009

1

1.0

5

JCPU1H

AT20

VSS1

AT17

VSS2

AR31

VSS3

AR28

VSS4

AR26

VSS5

AR24

VSS6

D D

C C

B B

AR23 AR20 AR17 AR15 AR12

AR9 AR6

AR3 AP20 AP17 AP13 AP10

AP7

AP4

AP2 AN34 AN31 AN23 AN20 AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11

AM8

AM5

AM2

AL34 AL31 AL23 AL20 AL17 AL12

AL9 AL6

AL3 AK29 AK27 AK25 AK20 AK17

AJ31 AJ23 AJ20 AJ17 AJ14 AJ11

AJ8

AJ5

AJ2 AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13

AH9 AH6 AH3

AG10

AF8 AF4 AF2

AE35

VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80

4

VSS

VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30

3

JCPU1I

K27

VSS161

K9

VSS162

K6

VSS163

K3

VSS164

J32

VSS165

J30

VSS166

J21

VSS167

J19

VSS168

H35

VSS169

H32

VSS170

H28

VSS171

H26

VSS172

H24

VSS173

H22

VSS174

H18

VSS175

H15

VSS176

H13

VSS177

H11

VSS178

H8

VSS179

H5

VSS180

H2

VSS181

G34

VSS182

G31

VSS183

G20

VSS184

G9

VSS185

G6

VSS186

G3

VSS187

F30

VSS188

F27

VSS189

F25

VSS190

F22

VSS191

F19

VSS192

F16

VSS193

E35

VSS194

E32

VSS195

E29

VSS196

E24

VSS197

E21

VSS198

E18

VSS199

E13

VSS200

E11

VSS201

E8

VSS202

E5

VSS203

E2

VSS204

D33

VSS205

D30

VSS206

D26

VSS207

D9

VSS208

D6

VSS209

D3

VSS210

C34

VSS211

C32

VSS212

C29

VSS213

C28

VSS214

C24

VSS215

C22

VSS216

C20

VSS217

C19

VSS218

C16

VSS219

B31

VSS220

B25

VSS221

B21

VSS222

B18

VSS223

B17

VSS224

B13

VSS225

B11

VSS226

B8

VSS227

B6

VSS228

B4

VSS229

A29

VSS230

A27

VSS231

A23

VSS232

A9

VSS233

2

VSS

NCTF

VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7

AT35 AT1 AR34 B34 B2 B1 A35

1

IC,AUB_CFD _rPGA,R0P9

CONN@

A A

Security Class ification

2009/09/ 21 2010/09/ 21

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/09/ 21 2010/09/ 21

3

Compal Secret Data

IC,AUB_CFD _rPGA,R0P9

CONN@

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR (6/6) VSS

NAT02 M/B LA-5154P Schematic

10 49Thursday, November 26, 2 009

1

1.0

5

M1 Circuit M3 Circuit

+1.5V

12

R170

1K_0402_1%~D

12

D D

+V_DDR3_DIMMA_REF

R169

1K_0402_1%~D

M2 Circuit

+3V

1

C164

@C164

@

1U_0402_6.3V4Z~D

C C

Layout Note: Place near JDIMM1

B B

10U_0805_6.3V6M~D

Layout Note: Place near JDIMM1.203 & JDIMM1.204

A A

PCH_SMBCLK PCH_SMBDATA

PM_SLP_S4#<17>

10U_0805_6.3V6M~D

1

C204

C186

2

+0.75VS

1U_0603_10V4Z~D

2

C1015

1

1U_0603_10V4Z~D

2

+1.5V

1

2

U45

@U45

@

1

VDD

2

GND

3

SCL

ISL90727WIE627Z-TK_SC70-6

Layout Note: Place these 4 Caps near Command and Control signals of DIMMA

10U_0805_6.3V6M~D

1

C187

C171

2

10U_0805_6.3V6M~D

1U_0603_10V4Z~D

2

C280

C1016

1

1U_0603_10V4Z~D

5

6

RH

5

RW

4

SDA

+5VALW

12

R226

@R226

@

100K_0402_5%~D

3

Q48B

@Q48B

@

2N7002DW-7-F_SOT363-6~D

5

4

1

C170

2

10U_0805_6.3V6M~D

1

2

C1017

C281

10U_0805_6.3V6M~D

2

1

VREF_RW_POT0

PP_S4GT

10U_0805_6.3V6M~D

C205

1 2

0_0402_5%~D

+1.5V

12

R223

@R223

@

12.1K_0402_1%~D

12

R222

@R222

@

12.1K_0402_1%~D

1

2

0.1U_0402_16V4Z~D

DDR_A_DQS#[0..7]<7>

DDR_A_D[0..63]<7>

DDR_A_DM[0..7]<7>

DDR_A_DQS[0..7]<7>

DDR_A_MA[0..15]<7>

PCH_SMBCLK<6,12,16>

PCH_SMBDATA<6,12,16>

+V_DDR3_DIMMA_REF2 +V_DD R3_DIMMB_REF2

R1245

@

+5VALW

C153

@C153

@

1 2

8

3

P

+

1

0

2

-

G

U46A

@ U46A

@

LM358DT_SO8

4

VREF_OPAMP_POT0

PP_S4GT<12>

12

R230

@R230

@

1M_0402_5%~D

0.1U_0402_16V4Z~D

1

C1045

C1013

2

0.1U_0402_16V4Z~D

+V_DDR3_DIMMA_REF

PCH_SMBCLK

PCH_SMBDATA

R1229

1 2

0_0402_5%~D

@

1U_0402_6.3V4Z~D

R221

@R221

@

2.2_0402_5%~D

1 2

10_0402_5%~D

PP_S4GT

0.1U_0402_16V4Z~D

1

C1046

2

1 3

Q37

D

BSS138_SOT23~D

4

H_DIMMA_REF<5>

+V_DDR3_DIMMA_REF

+V_DDR3_DIMMB_REF+V_DDR3_DIMMA_REF

R1246

1 2

0_0402_5%~D

@

2008/9/8 #40075 5 Calpella Clarks field DDR3 SO-DIMM VREFDQ Platform Design Guide Ch ange Details

VREF_POT0_R

12

1

C163

@C163

R220

@R220

@

2

C1064

2

G

4

S

@

1U_0402_6.3V4Z~D

2

PP_S4GT_Q_0

61

Q48A

@Q48A

@

2N7002DW-7-F_SOT363-6~D

1

+

C197

C197 330U_D2_2V_Y~OK

330U_D2_2V_Y~OK

2

R313

@ R 313

@

100K_0402_5%~D

1 2

VREF_POT0_R

M1 Circuit

1K_0402_1%~D

DDR_RST_GATE <6,12,20>

H_DIMMA_REF <5>

3

R178 0_0402_5%~DR178 0_0402_5%~D

1 2

R179 0_0402_5%~DR179 0_0402_5%~D

1 2

R227 0_0402_5%~D@R227 0_0402_5%~D@

1 2

1

C112

C124

0.1U_0402_16V4Z~D

+1.5V

12

R1247

12

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+V_DDR3_DIMMA_REF2

R1248

1K_0402_1%~D

+3VS

2.2U_0603_6.3V4Z~D

Issued Date

C112

2.2U_0805_16V4Z~D

2

DDR_A_CKE0<7>

DDR_A_BS2<7>

DDR_A_CLK0<7> DDR_A_CLK0#<7>

DDR_A_BS0<7>

DDR_A_WE#<7>

DDR_A_CAS#<7> DDR_A_ODT0 <7>

DDR_A_CS1#<7>

1

C1014

2

2009/09/21 2010/09/21

3

VREF_DQA

DDR_A_D0 DDR_A_D1

DDR_A_DM0

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_DM3

DDR_A_D26 DDR_A_D27 DDR_A_D31

DDR_A_CKE0

DDR_A_BS2

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

DDR_A_CLK0 DDR_A_CLK0#

DDR_A_MA10 DDR_A_BS0

DDR_A_WE# DDR_A_CAS#

DDR_A_MA13 DDR_A_CS1#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_DM7

DDR_A_D58 DDR_A_D59

R1057 10K_0402_5%~DR1057 10K_0402_5%~D

1 2

1

C276

0.1U_0402_16V4Z~D

2

+1.5V +1.5V

11 13 15 17 19 21 23 25 27

31 33 35 37 39 41 43 45 47 49 51 53 55 57 59

63 65 67 69 71

73 75 77 79 81 83 85 87 89 91 93 95 97

99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201

12

R1081

10K_0402_5%~D

Compal Secret Data

203

205

Deciphered Date

2

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS129RESET# VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS2261DQS#3 DM3 VSS23 DQ26 DQ27 VSS25

CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1

G1

FOX_AS0A626-U4RN-7F

CONN@

2

DQS#0

VSS10

VSS12

VSS14

VSS16

VSS17

VSS19

VSS21

VSS24

VSS26

VDD10

VDD12

VDD14

VDD16

VDD18

VREF_CA

VSS28

VSS30

VSS31

VSS33

VSS35

DQS#5

VSS38

VSS40

VSS42

VSS43

VSS45

VSS47

DQS#7

VSS50

VSS52

EVENT#

DQ4 DQ5

VSS3

DQS0

VSS6

DQ6

DQ7 VSS8 DQ12 DQ13

DM1

DQ14 DQ15

DQ20 DQ21

DM2

DQ22 DQ23

DQ28 DQ29

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

CK1#

RAS#

ODT0

ODT1

NC2

DQ36 DQ37

DM4

DQ38 DQ39

DQ44 DQ45

DQS5

DQ46 DQ47

DQ52 DQ53

DM6

DQ54 DQ55

DQ60 DQ61

DQS7

DQ62 DQ63

SDA

VTT2

CK1

BA1

SCL

1

2

DDR_A_D4

4

DDR_A_D5

6 8

DDR_A_DQS#0

10

DDR_A_DQS0

12 14

DDR_A_D6

16

DDR_A_D7

18 20

DDR_A_D12

22

DDR_A_D13

24 26

DDR_A_DM1

28

SM_DRAMRST#

30 32

DDR_A_D14

34

DDR_A_D15

36 38

DDR_A_D20

40

DDR_A_D21

42 44

DDR_A_DM2

46 48

DDR_A_D22

50

DDR_A_D23

52 54

DDR_A_D28

56

DDR_A_D29

58 60

DDR_A_DQS#3

62

DDR_A_DQS3

64 66

DDR_A_D30

68 70 72

DDR_A_CKE1

74 76

DDR_A_MA15

78

A15 A14

A11

A7

A6 A4

A2 A0

S0#

G2

80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_A_MA14

DDR_A_MA11 DDR_A_MA7

DDR_A_MA6 DDR_A_MA4

DDR_A_MA2 DDR_A_MA0

DDR_A_CLK1 DDR_A_CLK1#

DDR_A_BS1 DDR_A_RAS#

DDR_A_CS0# DDR_A_ODT0

DDR_A_ODT1

DDR_VREF_CA_DIMMA

DDR_A_D36 DDR_A_D37

DDR_A_DM4

DDR_A_D38 DDR_A_D39

DDR_A_D44DDR_A_D44 DDR_A_D45

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_DM6

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D62 DDR_A_D63

PM_EXTTS#0_1 SMBDATA SMBCLK

+0.75VS

+1.5V

R56

1K_0402_5%~D

1 2

DDR_A_CKE1 <7>

DDR_A_CLK1 <7> DDR_A_CLK1# <7>

DDR_A_BS1 <7> DDR_A_RAS# <7>

DDR_A_CS0# <7>

DDR_A_ODT1 <7>

R1056 0_0402_5%~DR1056 0_0402_5%~D

1 2

2.2U_0603_6.3V4Z~D

PM_EXTTS#0_1 <6,12>

SMBDATA <12,13,14,16> SMBCLK <12,13,14,16>

SM_DRAMRST# <6,12>

1

C230

2

+V_DDR3_DIMMA_REF2

1

C220

0.1U_0402_16V4Z~D

2

DDR3 SO-DIMM A Standard Type

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Date: Sheet of

Compal Electronics, Inc.

DDRIII-SODIMM SLOT1

NAT02 M/B LA-5154P Schematic

1

1.0

of

11 49Thursday, November 26, 2009

5

M1 Circuit

+1.5V

12

R1230

1K_0402_1%~D

D D

+V_DDR3_DIMMB_REF

M2 Circuit

C C

B B

A A

@C156

@

1U_0402_6.3V4Z~D

PCH_SMBCLK

PCH_SMBDATA

C172

10U_0805_6.3V6M~D

Layout Note: Place near JDIMM2.203 & JDIMM2.204

1U_0603_10V4Z~D

12

Q44

BSS138_SOT23~D

+3V

1

C156

2

Layout Note: Place near JDIMM2

+1.5V

10U_0805_6.3V6M~D

1

C188

2

10U_0805_6.3V6M~D

+0.75VS

C1018

C282

2

1

1U_0603_10V4Z~D

+V_DDR3_DIMMB_REF

R1231

1K_0402_1%~D

2

G

1 3

D

S

D

S

R321

@ R321

@

100K_0402_5%~D

1 2

U8

@U8

@

1

VDD

2

GND

3

SCL

ISL90728WIE627Z-TK_SC70-6

1

C206

2

10U_0805_6.3V6M~D

1U_0603_10V4Z~D

C283

2

1

5

6

RH

5

RW

4

SDA

10U_0805_6.3V6M~D

1

C173

C189

2

C1019

2

1

1U_0603_10V4Z~D

1

2

C298

1

10U_0805_6.3V6M~D

2

2008/9/8 #40075 5 Calpella Clarks field DDR3 SO-DIMM VREFDQ Platform Design Guide Ch ange Details

DDR_RST_GATE <6,11,20>

H_DIMMB_REF <5>

+1.5V

12

R196

@R196

@

12.1K_0402_1%~D

VREF_RW_POT1

12

R197

@R197

@

12.1K_0402_1%~D

Layout Note: Place these 4 Caps near Command and Control signals of DIMMA

0.1U_0402_16V4Z~D

1

C1047

C207

2

10U_0805_6.3V6M~D

+5VALW

8

5

P

+

6

-

G

4

VREF_OPAMP_POT1

PP_S4GT<11>

1

C1048

2

0.1U_0402_16V4Z~D

DDR_B_DQS#[0..7]<7>

DDR_B_D[0..63]<7>

DDR_B_DM[0..7]<7>

DDR_B_DQS[0..7]<7>

DDR_B_MA[0..15]<7>

PCH_SMBDATA<6,11,16>

U46B

@U46B

@

LM358DT_SO8

7

0

PP_S4GT

1

C1049

2

4

PCH_SMBCLK<6,11,16>

R193

@R193

@

1 2

2.2_0402_5%~D

R194

@R194

@

10_0402_5%~D

2

G

1

C1050

2

0.1U_0402_16V4Z~D

4

+V_DDR3_DIMMB_REF

H_DIMMB_REF<5>

PCH_SMBCLK

PCH_SMBDATA

VREF_POT1_R

12

1

2

PP_S4GT_Q_1

13

D

Q49

@

Q49

@

2N7002LT1G_SOT23-3

S

1

+

C198

C198 330U_D2_2V_Y~OK

330U_D2_2V_Y~OK

2

VREF_POT1_R

C128

@C128

@

1U_0402_6.3V4Z~D

3

M1 Circuit

R166 0_0402_5%~DR166 0_0402_5%~D

1 2

M3 Circuit

R165 0_0402_5%~DR165 0_0402_5%~D

1 2

R186 0_0402_5%~D@R186 0_0402_5%~D@

1 2

C110

2.2U_0805_16V4Z~D

DDR_B_BS2<7>

DDR_B_BS0<7>

DDR_B_WE#<7>

DDR_B_CAS#<7> DDR_B_ODT0 <7>

DDR_B_CS1#<7>

+3VS

C1020

2.2U_0603_6.3V4Z~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

VREF_DQB

DDR_B_D0 DDR_B_D1

DDR_B_DM0

DDR_B_D2 DDR_B_D3

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1

1

C122

2

0.1U_0402_16V4Z~D

DDR_B_CLK0<7> DDR_B_CLK0#<7>

1

C277

0.1U_0402_16V4Z~D

2

DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D16 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D18 DDR_B_D19

DDR_B_D24 DDR_B_D25

DDR_B_DM3

DDR_B_D26 DDR_B_D27

DDR_B_BS2

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA5

DDR_B_MA3 DDR_B_MA1

DDR_B_CLK0 DDR_B_CLK0#

DDR_B_MA10 DDR_B_BS0

DDR_B_WE# DDR_B_CAS#

DDR_B_MA13 DDR_B_CS1#

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_DM5

DDR_B_D42 DDR_B_D43

DDR_B_D48 DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50 DDR_B_D51

DDR_B_D56 DDR_B_D57

DDR_B_DM7

DDR_B_D58 DDR_B_D59

R1059 10K_0402_5%~DR1059 10K_0402_5%~D

1 2

R1082 10K_0402_5%~DR1082 10K_0402_5%~D

2009/09/21 2010/09/21

+1.5V

3 5 7

9 11 13 15 17 19 21 23 25 27

33 35

39 41

45 47 49 51 53 55 57 59

63

67 69

73 75 77 79 81 83 85 87 89 91 93 95 97 99

101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203

205

Compal Secret Data

Deciphered Date

JDIMM2

FOX_AS0A626-U8RN-7F

CONN@

2

VREF_DQ1VSS1 VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS129RESET# VSS1131VSS12 DQ10 DQ11 VSS1337VSS14 DQ16 DQ17 VSS1543VSS16 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS2261DQS#3 DM3 VSS2365VSS24 DQ26 DQ27 VSS2571VSS26

CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1

G1

DQ4 DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6 DQ7

VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35 DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47 DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA

VTT2

2

CK1

BA1

SCL

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78

A15

80

A14

82 84

A11

86

A7

88 90

A6

92

A4

94 96

A2

98

A0

100 102 104 106 108 110 112 114

S0#

116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

G2

+1.5V

DDR_B_D4 DDR_B_D5

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D6 DDR_B_D7

DDR_B_D12 DDR_B_D13

DDR_B_DM1 SM_DRAMRST#

DDR_B_D14 DDR_B_D15

DDR_B_D20 DDR_B_D21

DDR_B_DM2

DDR_B_D22 DDR_B_D23

DDR_B_D28 DDR_B_D29

DDR_B_DQS#3 DDR_B_DQS3

DDR_B_D30 DDR_B_D31

DDR_B_CKE1DDR_B_CKE0

DDR_B_MA15 DDR_B_MA14

DDR_B_MA11 DDR_B_MA7

DDR_B_MA6 DDR_B_MA4

DDR_B_MA2 DDR_B_MA0

DDR_B_CLK1 DDR_B_CLK1#

DDR_B_BS1 DDR_B_RAS#

DDR_B_CS0# DDR_B_ODT0

DDR_B_ODT1

DDR_VREF_CA_DIMMB

DDR_B_D36 DDR_B_D37

DDR_B_DM4

DDR_B_D38 DDR_B_D39

DDR_B_D44 DDR_B_D45

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D46 DDR_B_D47

DDR_B_D52 DDR_B_D53

DDR_B_DM6

DDR_B_D54 DDR_B_D55

DDR_B_D60 DDR_B_D61

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D62 DDR_B_D63

PM_EXTTS#0_1 SMBDATA SMBCLK

1

SM_DRAMRST# <6,11>

DDR_B_CKE1 <7>DDR_B_CKE0<7>

DDR_B_CLK1 <7> DDR_B_CLK1# <7>

DDR_B_BS1 <7> DDR_B_RAS# <7>

DDR_B_CS0# <7>

DDR_B_ODT1 <7>

R1058 0_0402_5%~DR1058 0_0402_5%~D

1 2

2.2U_0603_6.3V4Z~D

M1 Circuit

1K_0402_1%~D

PM_EXTTS#0_1 <6,11>

SMBDATA <11,13,14,16>

+0.75VS

SMBCLK <11 ,13,14,16>

R1249

+V_DDR3_DIMMB_REF2

1

C231

2

+1.5V

12

+V_DDR3_DIMMB_REF2

12

R1250

1K_0402_1%~D

1

C221

0.1U_0402_16V4Z~D

2

+V_DDR3_DIMMB_REF2

DDR3 SO-DIMM B Standard Type

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

DDRIII-SODIMM SLOT2

NAT02 M/B LA-5154P Schematic

12 49Thursday, November 26, 2009

1

1.0

A

B

C

D

E

F

G

H

+CLK_VD DSRC

L80

L79

+1.05VS

1 1

CLK_BUF _DREF_96M<16> CLK_BUF _DREF_96M#<16>

2 2

3 3

CLK_BUF _PCIE_SATA<16> CLK_BUF _PCIE_SATA#<16>

CLK_BUF _CPU_DMI< 16> CLK_BUF _CPU_DMI#<16>

L79 FBMA-L11 -201209-221LMA 30T_0805

FBMA-L11 -201209-221LMA 30T_0805

1

C1051

C1051 10U_080 5_10V4Z~D

10U_080 5_10V4Z~D

2

CLK_BUF _DREF_96M CLK_BUF _DREF_96M#

CLK_BUF _PCIE_SATA

+CLK_VD D

Silego Have Int ernal Pull-Up

R627 10K_0 402_5%~DR6 27 10K_0402_5%~D

+CLK_VD DSRC

R1140 10K_0402_ 5%~D

R634 10K_0 402_5%~DR6 34 10K_0402_5%~D

1 2

@

1 2

12

1

C1052

10U_080 5_10V4Z~D

2

0.1U_040 2_16V4Z~D

Integrated 33oh m Resistor

R1004 0_ 0402_5%~DR1004 0_0402_5%~ D

1 2

R1005 0_ 0402_5%~DR1005 0_0402_5%~ D

1 2

R1006 0_ 0402_5%~DR1006 0_0402_5%~ D

1 2

R1008 0_ 0402_5%~DR1008 0_0402_5%~ D

1 2

R1010 0_ 0402_5%~DR1010 0_0402_5%~ D

1 2

R1011 0_ 0402_5%~DR1011 0_0402_5%~ D

1 2

Integrated 33oh m Resistor

H_STP_C PU#

REF_0/CP U_SEL

1

C979

C1053

0.1U_040 2_16V4Z~D

2

+CLK_VD DSRC +CLK_VD D

+CLK_VD D

CLK_BUF _DREF_96M_R CLK_BUF _DREF_96M#_R

CLK_BUF _PCIE_SATA_R CLK_BUF _PCIE_SATA#_RCLK_BUF _PCIE_SATA#

CLK_BUF _CPU_DMI_RCLK_BUF_C PU_DMI CLK_BUF _CPU_DMI#_RCLK_BUF _CPU_DMI#

H_STP_C PU#

1

CU53

@C U53

@

47P_040 2_50V8J~D

2

Clock Generator

U49

1

VDD_USB_48

2

VSS_48M

3

DOT_96

4

DOT_96#

5

VDD_27

6

27MHZ

7

27MHZ_SS

8

USB_48

9

VSS_27M

10

SATA

11

SATA#

12

VSS_SRC

13

SRC_1

14

SRC_1#

15

VDD_SRC_IO

16

CPU_STOP#

33

TGND

SLG8SP5 87VTR_QFN32_ 5X5

IDT: 9LRS3191AKLFT SILEGO: SLG8SP585

REF_0/CPU_SEL

CKPWRGD/PD#

+3VS

SCL SDA

VDD_REF

XTAL_IN

XTAL_OUT

VSS_REF

VDD_CPU

CPU_0

CPU_0#

VSS_CPU

CPU_1

CPU_1#

VDD_CPU_IO

VDD_SRC

L80

FBMA-L11 -201209-221LMA 30T_0805

1

C1065

C1065 10U_080 5_10V4Z~D

10U_080 5_10V4Z~D

2

+CLK_VD DSRC

32 31 30 29 28 27 26 25

24 23 22 21 20 19 18 17

SMBCLK SMBDATA REF_0/CP U_SEL

CLK_XTA L_IN CLK_XTA L_OUT

CK505_P WRGD

CLK_BUF _CPU_BCLK_R CLK_BUF _CPU_BCLK#_R

IDT Have Intern al Pull-Down

CPU_1PIN 30 CPU_0

(Default)

0 133MHz

1

100MHz 100MHz

133MHz

+CLK_VD D

0.1U_040 2_16V4Z~D

12

0.1U_040 2_16V4Z~D

1

C1061

2

10U_080 5_10V4Z~D

R633 33_04 02_5%~DR633 33_04 02_5%~D

1 2

R1.0 modify

R1007 0_ 0402_5%~DR1007 0_0402_5%~ D

1 2

R1009 0_ 0402_5%~DR1009 0_0402_5%~ D

1 2

Integrated 33oh m Resistor

+CLK_VD D

R631

R631 10K_040 2_5%~D

10K_040 2_5%~D

1 2

CK505_P WRGD

13

D

2

G

Q45

S

2N7002L T1G_SOT23-3

CLK_XTA L_IN

1M_0402 _5%~D

CLK_XTA L_OUT

0.1U_040 2_16V4Z~D

1

C1055

C1054

2

0.1U_040 2_16V4Z~D

C1109

12

R1141

@R1141

@

1

C1056

2

0.1U_040 2_16V4Z~D

10P_040 2_50V8J~D

1 2

@

CLK_BUF _CPU_BCLK CLK_BUF _CPU_BCLK#

R632

R632 0_0402_ 5%~D

0_0402_ 5%~D

@

1 2

CLK_ENA BLE# <46>

C1059 33 P_0402_50V8 J~DC1059 33P_0402_50 V8J~D

12

Y6

14.31818 MHz_20P_FSX8L 14.318181M20F DB~OK

C1060 33 P_0402_50V8 J~DC1060 33P_0402_50 V8J~D

C1057

2

VGATE < 17,31,46>

12

1

C1058

0.1U_040 2_16V4Z~D

2

1

2

SMBCLK <11,12,14,16>

SMBDATA <11 ,12,14,16>

CLK_BUF _ICH_14M <1 6>

CLK_BUF _CPU_BCLK <16> CLK_BUF _CPU_BCLK# <16>

CU54

@C U54

@

47P_040 2_50V8J~D

4 4

Security Class ification

2009/09/ 21 2010/09/ 21

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2009/09/ 21 2010/09/ 21

Compal Secret Data

Deciphered Date

E

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Custom

Date: Sheet of

F

Date: Sheet of

Compal Electronics, Inc.

Clock Generator (CK505)

NAT02 M/B LA-5154P Schematic

G

13 49Thursday, November 26, 2 009

H

1.0

FAN Control circuit

EN_DFAN1<31>

FAN_SPEED1<31>

0.1U_0402_16V4Z~D

EN_DFAN1

+3VS

R141

10K_0402_5%~D

C98

12

2

1

+FAN1_POWER

C77

10U_1206_16V4Z~D

12

C91

1000P_0402_50V7K~D

12

+5VS

40mil

+FAN1_POWER

1 2

C96 10U_1206_16V4Z~DC96 10U_1206_16V4Z~D

U7

1

VEN

2 3 4

MOLEX_53261-0371~D

GND

VIN

GND GND

VO

GND

VSET

RT9027BPS_SO8

JFAN1

1

2

G

33G

CONN@

4 5

Free Fall Sensor

2

1

+3VS

1

C1067

C1067 10U_0805_10V4Z~D

10U_0805_10V4Z~D

2

+3VS +3VS_ACL_IO

8 7 6 5

+3VS_ACL_IO

+3VS

ACCEL_INT#<19>

SMBDATA<11,12,13,16>

SMBCLK<11,12,13,16>

+3VS

1 2

R1135 10K_0402_5%~D

R1134

1 2

0_0603_5%~D

12 13 14

U50

DE351DLTR

1

VDD_IO

6

VDD

8

INT 1 INT 29GND

SDO SDA / SDI / SDO SCL / SPC

7

RSVD

CS

RSVD

DE351DLTR_LGA14_3X5

GND GND GND

2 4 5 10

3 11

C1066

0.1U_0402_16V4Z~D

+3VS

Must be placed in the center o f the system.

P/N : SA000039C 00 (S IC DE351D LTR LGA 14P MO TION SENSOR)

Power Button

for debug only

5

6

3

4

SWO1

@

SMT1-05_4P

1

2

TOPBTN

SWO2

5

6

@

SMT1-05_4P

3

4

1

2

PWR_ON-OFF_BTN#

PWR_ON-OFF_BTN# <32>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/09/21 2010/09/21

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

Compal Electronics, Inc.

FAN & Screw Hole

NAT02 M/B LA-5154P Schematic

14 49Thursday, November 26, 2009

1.0

5

+RTCVCC

1 2

R46

R46 20K_040 2_1%~D

20K_040 2_1%~D

PCH_RTC RST#

RC Delay 18~25mS

close to RAM door

12

CMOS1@CMOS1

@

C15

1U_0603 _10V6K~D

D D

+RTCVCC

close to RAM door

1 2

R36

R36 20K_040 2_1%~D

20K_040 2_1%~D

ME1 @ME1 @

C13

1U_0603 _10V6K~D

1 2

12

32.768KH Z_12.5PF_Q13M C14610002

PCH_SRT CRST#

RC Delay 18~25mS

3

2

+RTCVCC

INTVRMEN - Integrated SUS 1.1V VRM Enable High - Enable Internal VRs

HDA for AUDIO

HDA_BITCL K_AUDIO<25>

HDA_SYNC_ AUDIO<25>

HDA_RST _AUDIO#<25>

HDA_SDO UT_AUDIO<25>

C C

HDA_BITCL K_AUDIO

1 2

R1083 33_0402_5% ~DR1083 33_0402_ 5%~D

1 2

R1084 33_0402_5% ~DR1084 33_0402_ 5%~D

1 2

R1085 33_0402_5% ~DR1085 33_0402_ 5%~D

1 2

R1086 33_0402_5% ~DR1086 33_0402_ 5%~D

10P_040 2_50V8J~D

1 2

C1110

@

HDA_BITCL K_PCH

HDA_SYNC_ PCH

HDA_RST _PCH#

HDA_SDO UT_PCH

TOUCHKE Y_TINT<31,32 >

GPIO33 pull dow n only for ME d isable

4

C398

18P_040 2_50V8J~D

12

X2

OSC

NC

OSC

NC

C402

12

18P_040 2_50V8J~D

R64 1M_0402_5 %~DR64 1M_0402_5 %~D

1 2

R51 330K_0402 _5%~DR51 330K_0402 _5%~D

1 2

PCH_SPK R<2 5>

HDA_SDIN0<25>

PCH_RTC X1

4

1

R1024 0_0402_ 5%~DR 1024 0_0402_5%~D R1232 1K_0402 _5%~D@R1232 1K_0402_5 %~D@

R1100

10M_040 2_5%~D

PCH_RTC X2

1 2 1 2

12

PCH_RTC RST#

PCH_SRT CRST#

SM_INTRUD ER#

PCH_INTVR MEN

HDA_BITCL K_PCH

HDA_SYNC_ PCH

PCH_SPK R

HDA_RST _PCH#

HDA_SDO UT_PCH

PCH_JTA G_TCK

PCH_JTA G_TMS

PCH_JTA G_TDI

PCH_JTA G_TDO

PCH_JTA G_RST#

U47A

B13

RTCX1

D13

RTCX2

C14

RTCRST#

D17

SRTCRST#

A16

INTRUDER#

A14

INTVRMEN

A30

HDA_BCLK

D29

HDA_SYNC

P1

SPKR

C30

HDA_RST#

G30

HDA_SDIN0

F30

HDA_SDIN1

E32

HDA_SDIN2

F32

HDA_SDIN3

B29

HDA_SDO

H32

HDA_DOCK_EN# / GPIO33

J30

HDA_DOCK_RST# / GPIO13

M3

JTAG_TCK

K3

JTAG_TMS

K1

JTAG_TDI

J2

JTAG_TDO

J4

TRST#

REV1.0

3

RTCIHDA

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

FWH4 / LFRAME#

LDRQ1# / GPIO23

LPC

SATA0RXN SATA0RXP SATA0TXN

SATA0TXP

SATA1RXN SATA1RXP SATA1TXN

SATA1TXP

SATA2RXN SATA2RXP SATA2TXN

SATA2TXP

SATA3RXN SATA3RXP SATA3TXN

SATA3TXP

SATA4RXN SATA4RXP SATA4TXN

SATA

SATA4TXP

SATA5RXN SATA5RXP SATA5TXN

SATA5TXP

SATAICOMPO

SATAICOMPI

LDRQ0#

SERIRQ

D33 B33 C32 A32

C34

A34 F34

AB9

AK7 AK6 AK11 AK9

AH6 AH5 AH9 AH8

AF11 AF9 AF7 AF6

AH3 AH1 AF3 AF1

AD9 AD8 AD6 AD5

AD3 AD1 AB3 AB1

AF16

AF15

2

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

LPC_FRA ME#

SERIRQ

SATA_ITX_ DRX_N0

SATA_ITX_ DRX_P0

SATA_ITX_ DRX_N1 SATA_ITX_ DRX_P1

From PCH EDS 5. 16, SATA port2 & 3 are not availa ble in all sku.

SATA_ITX_ DRX_N4

SATA_ITX_ DRX_P4

SATA_ITX_ DRX_N5

SATA_ITX_ DRX_P5

SATA_CO MP

LPC_AD0 <27,31> LPC_AD1 <27,31> LPC_AD2 <27,31> LPC_AD3 <27,31>

LPC_FRA ME# <27 ,31>

SERIRQ <31>

C963 0 .01U_0402_16V 7K~DC963 0 .01U_0402_16V 7K~D C964 0 .01U_0402_16V 7K~DC964 0 .01U_0402_16V 7K~D

R139 37.4_0 402_1%~OKR139 37.4_0 402_1%~OK

1 2

1

SATA_IRX_ DTX_N0 < 29>

C9610.01 U_0402_16V7K ~D C9610.01U_ 0402_16V7K~D

1 2

C9620.01 U_0402_16V7K ~D C9620.01U_ 0402_16V7K~D

1 2

12 12

C9650.01 U_0402_16V7K ~D C9650.01U_ 0402_16V7K~D

1 2

C9660.01 U_0402_16V7K ~D C9660.01U_ 0402_16V7K~D

1 2

C9670.01 U_0402_16V7K ~D C9670.01U_ 0402_16V7K~D

1 2

C9680.01 U_0402_16V7K ~D C9680.01U_ 0402_16V7K~D

1 2

+1.05VS

SATA_IRX_ DTX_P0 <29> SATA_ITX_ C_DRX_N0 <29> SATA_ITX_ C_DRX_P0 <29>

SATA_IRX_ DTX_N1 < 29>

SATA_IRX_ DTX_P1 <29> SATA_ITX_ C_DRX_N1 <29> SATA_ITX_ C_DRX_P1 <29>

SATA_IRX_ DTX_N4 < 29>

SATA_IRX_ DTX_P4 <29> SATA_ITX_ C_DRX_N4 <29> SATA_ITX_ C_DRX_P4 <29>

SATA_IRX_ DTX_N5 < 30>

SATA_IRX_ DTX_P5 <30> SATA_ITX_ C_DRX_N5 <30> SATA_ITX_ C_DRX_P5 <30>

SATA for HDD1

SATA for HDD2

SATA for ODD

SATA for eSATA

PCH_SPI_C LK_1 PCH_SPI_C LK_2

+3VS

B B

A A

R1120

R1120 1K_0402 _5%~D

1K_0402 _5%~D

1 2

R115

R115 10K_040 2_5%~D

10K_040 2_5%~D

PCH_JTA G_TMS

PCH_JTA G_TDO

PCH_JTA G_TDI

PCH_JTA G_RST#

PCH_SPI_M OSI

enable iTPM: SPI_MOSI High

PCH_SPK R

@

SERIRQ

R1130 51_0402_1 %~D@R 1130 51 _0402_1%~D@

1 2

R1101 200_0402_ 5%~DR 1101 20 0_0402_5%~D

1 2

R1102 100_0402_ 1%~DR 1102 10 0_0402_1%~D

1 2

R1131 51_0402_1 %~D@R 1131 51 _0402_1%~D@

1 2

R1104 200_0402_ 5%~D R1104 200_040 2_5%~D

1 2

R1105 100_0402_ 1%~DR 1105 10 0_0402_1%~D

1 2

R1132 51_0402_1 %~D@R 1132 51 _0402_1%~D@

1 2

R1106 200_0402_ 5%~DR 1106 20 0_0402_5%~D

1 2

R1107 100_0402_ 1%~DR 1107 10 0_0402_1%~D

1 2

R1133 51_0402_1 %~D@R 1133 51 _0402_1%~D@

1 2

R1108 20K_0402_ 1%~DR1108 20K_0402 _1%~D

1 2

R1109 10K_0402_ 5%~DR1109 10K_0402 _5%~D

1 2

R173 1K_04 02_5%~D@R1 73 1K_0402_5%~D@

1 2

5

PCH_SPI_C S0#

PCH_SPI_C S1# PCH_SPI_CS 1#_R

PCH_SPI_M OSI_1 PCH_SPI_M OSI_2 PCH_SPI_M ISO_1 P CH_SPI_MISO PCH_SPI_M ISO_2

+3V

+1.05VS

2008 Intel MOW3 6/MOW50

TDO: Reserved on ES1 Sample Mount R1104, R1 105 on ES2 Samp le

MP mount R1130, R1131, R1132, R1133 an d remove others

+3VS

PCH_JTA G_TCK

R584 0_040 2_5%~DR584 0_040 2_5%~D

1 2

RU86 0_0402_5%~D@RU86 0_0402_5% ~D@

1 2

R571 15_04 02_5%~DR571 15_04 02_5%~D

1 2

RU87 15_0402_5%~D@RU87 15_0402_5% ~D@

1 2

R575 15_04 02_5%~DR575 15_04 02_5%~D

1 2

RU88 15_0402_5%~D@RU88 15_0402_5% ~D@

1 2

R565 33_04 02_5%~DR565 33_04 02_5%~D

1 2

RU89 33_0402_5%~D@RU89 33_0402_5% ~D@

1 2

R1111 4.7K_040 2_5%~DR1111 4.7K_040 2_5%~D

CRB 1.0 Change to 4.7K

1 2

4

PCH_SPI_C LKP CH_SPI_CLK

PCH_SPI_C S0#_R

PCH_SPI_M OSI

PCH_SPI_M ISO

BA2

SPI_CLK

AV3

SPI_CS0#

AY3

SPI_CS1#

AY1

SPI_MOSI

AV1

SPI_MISO

IBEXPEAK-M_ FCBGA1071~D

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SPI JTAG

+3VS

2009/09/ 21 2010/09/ 21

3

SATALED#

SATA0GP / GPIO21

SATA1GP / GPIO19

RU91

1 2

3.3K_040 2_5%~D@

R1110

1 2

3.3K_040 2_5%~D

PCH_SPI_C S1# PCH_SPI_M ISO_2

SPI_WP 2#

PCH_SPI_C S0#

PCH_SPI_M ISO_1

SPI_WP 1#

Compal Secret Data

PCH_SAT ALED#

T3

Y9

V1

Deciphered Date

R129 10K_0 402_5%~DR1 29 10K_0402_5%~D

1 2

@

PAD

T110

@

PAD

T111

U68

1

CS#

2 3 4

1

2

3

4

VCC

SO

HOLD#

WP#

SCLK

GND

MX25L16 05AM2C-12G_SO 8@

U29

/CS

DO

/WP

GND

MX25L32 05DM2I-12G_SO8~ D

SI

VCC

/HOLD

CLK

DIO

8 7 6 5

8

7

6

5

2

10K_040 2_5%~D

+3VS

SPI_HOLD2 # PCH_SPI_C LK_2 PCH_SPI_M OSI_2

+3VS

SPI_HOLD1 #

PCH_SPI_C LK_1

PCH_SPI_M OSI_1

R111

+3VS

R77 10K_0402_ 5%~D@R77 10K_0402 _5%~D@

1 2

R116 10K_0 402_5%~D@R11 6 10K_0402_5%~D@

1 2

12

R82

10K_040 2_5%~D

RU903.3K_040 2_5%~D

12

+3VS

@

SPI Flash (32Mbit/4Mbyte)

R11223.3 K_0402_5%~D R11223 .3K_0402_5%~D

12

+3VS

Change to SA000021A0L

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Custom

NAT02 M/B LA-5154P Schematic

Date: Sheet of

Compal Electronics, Inc.

PCH (1/9) SATA,HDA,SPI, LPC

1

1.0

15 49Thursday, November 26, 2 009

5

MiniWWAN -->

MiniWLAN -->

D D

MiniWPAN -->

Card Reader -->

Express card -->

10/100/1G LAN -->

C C

MiniWWAN -->

MiniWLAN -->

MiniWPAN -->

Card Reader -->

Express card -->

B B

10/100/1G LAN -->

PCH_GPIO20 PCH_GPIO18

PCIE_IRX_WANTX_N1<27>

PCIE_IRX_WANTX_P1<27> PCIE_ITX_C_WANRX_N 1<27> PCIE_ITX_C_WANRX_P 1<27>

PCIE_IRX_WLANTX_N2<27>

PCIE_IRX_WLANTX_P2<27> PCIE_ITX_C_WLANRX_N 2<27> PCIE_ITX_C_WLANRX_P 2<27>

PCIE_IRX_WPANTX_N3<28>

PCIE_IRX_WPANTX_P3<28> PCIE_ITX_C_WPANRX_ N3<28> PCIE_ITX_C_WPANRX_ P3<28>

PCIE_IRX_CBTX_N4<30>

PCIE_IRX_CBTX_P4<30> PCIE_ITX_C_CBRX_N4<30> PCIE_ITX_C_CBRX_P4<30>

PCIE_IRX_EXPTX_N5<28> PCIE_IRX_EXPTX_P5<28>

PCIE_ITX_C_EXPRX_N5<28> PCIE_ITX_C_EXPRX_P5<28>

PCIE_IRX_GLANTX_N6<24>

PCIE_IRX_GLANTX_P6<24> PCIE_ITX_C_GLANRX_N6<24> PCIE_ITX_C_GLANRX_P6<24>

CLK_PCIE_WAN#<27> CLK_PCIE_WAN<27>

WWAN_CLK REQ#<27>

CLK_PCIE_WLAN#<27> CLK_PCIE_WLAN<27>

WLAN_CLKREQ#< 27>

PAD

T112

CLK_PCIE_WPAN#<28> CLK_PCIE_WPAN<28>

WPAN_CLKREQ#<28>

PAD

T113

CLK_PCIE_CB#<30> CLK_PCIE_CB<30>

CB_CLKREQ#<30>

CLK_PCIE_EXPR#<28> CLK_PCIE_EXPR< 28>

EXP_CLKREQ#<28>

CLK_PCIE_GLAN#<24> CLK_PCIE_GLAN< 24>

GLAN_CLKREQ#<24>

R1112 10K_0402_5%~DR1112 10K_0402_5%~D

1 2

R1022 10K_0402_5%~DR1022 10K_0402_5%~D

1 2

C1021 0.1U_0402_16V7K~DC1021 0.1U_0402_16V7K~D C1022 0.1U_0402_16V7K~DC1022 0.1U_0402_16V7K~D

C1023 0.1U_0402_16V7K~DC1023 0.1U_0402_16V7K~D C1024 0.1U_0402_16V7K~DC1024 0.1U_0402_16V7K~D

C969 0.1U_0402_16V7K~DC969 0.1U_0402_16V7K~D C970 0.1U_0402_16V7K~DC970 0.1U_0402_16V7K~D

C971 0.1U_0402_16V7K~DC971 0.1U_0402_16V7K~D C972 0.1U_0402_16V7K~DC972 0.1U_0402_16V7K~D

C973 0.1U_0402_16V7K~DC973 0.1U_0402_16V7K~D C974 0.1U_0402_16V7K~DC974 0.1U_0402_16V7K~D

C1025 0.1U_0402_16V7K~DC1025 0.1U_0402_16V7K~D C1026 0.1U_0402_16V7K~DC1026 0.1U_0402_16V7K~D

R551 0_040 2_5%~DR551 0_0402_5%~D

1 2

R550 0_040 2_5%~DR550 0_0402_5%~D

1 2

R76 0_ 0402_5%~DR76 0_0402_5%~D

1 2

R1123 0_0402_5%~DR1123 0_0 402_5%~D

1 2

R1124 0_0402_5%~DR1124 0_0 402_5%~D

1 2

R93 0_ 0402_5%~DR93 0_0402_5%~D

1 2

R1012 0_0402_5%~DR1012 0_0 402_5%~D

1 2

R1013 0_0402_5%~DR1013 0_0 402_5%~D

1 2

R1014 0_0402_5%~DR1014 0_0 402_5%~D

1 2

R1015 0_0402_5%~DR1015 0_0 402_5%~D

1 2

R1016 0_0402_5%~DR1016 0_0 402_5%~D

1 2

R1017 0_0402_5%~DR1017 0_0 402_5%~D

1 2

R558 0_040 2_5%~DR558 0_0402_5%~D

1 2

R563 0_040 2_5%~DR563 0_0402_5%~D

1 2

R1018 0_0402_5%~DR1018 0_0 402_5%~D

1 2

R1019 0_0402_5%~DR1019 0_0 402_5%~D

1 2

R1020 0_0402_5%~DR1020 0_0 402_5%~D

1 2

R1021 0_0402_5%~DR1021 0_0 402_5%~D

1 2

+3VS

@

12 12

4

PCIE_IRX_WANTX_N1 PCIE_IRX_WANTX_P1 PCIE_ITX_WANRX_N1 PCIE_ITX_WANRX_P1

PCIE_IRX_WLANTX_N2 PCIE_IRX_WLANTX_P2 PCIE_ITX_WLANRX_N2 PCIE_ITX_WLANRX_P2

PCIE_IRX_WPANTX_N3 PCIE_IRX_WPANTX_P3 PCIE_ITX_WPANRX_N3 PCIE_ITX_WPANRX_P3

PCIE_IRX_CBTX_N4 PCIE_IRX_CBTX_P4 PCIE_ITX_CBRX_N4 PCIE_ITX_CBRX_P4

PCIE_IRX_EXPTX_N5 PCIE_IRX_EXPTX_P5 PCIE_ITX_EXPRX_N5 PCIE_ITX_EXPRX_P5

PCIE_IRX_GLANTX_N6 PCIE_IRX_GLANTX_P6 PCIE_ITX_GLANRX_N6 PCIE_ITX_GLANRX_P6

R_CLK_PCIE_WAN# R_CLK_PCIE_WAN

PCH_GPIO73

R_CLK_PCIE_WLAN# R_CLK_PCIE_WLAN

PCH_GPIO18

R_CLK_PCIE_WPAN# R_CLK_PCIE_WPAN

PCH_GPIO20

R_CLK_PCIE_CB# R_CLK_PCIE_CB

PCH_GPIO25

R_CLK_PCIE_EXPR# R_CLK_PCIE_EXPR

PCH_GPIO26

R_CLK_PCIE_GLAN# R_CLK_PCIE_GLAN

PCH_GPIO44

PCH_GPIO56

U47B

BG30

PERN1

BJ30

PERP1

BF29

PETN1

BH29

PETP1

AW30

PERN2

BA30

PERP2

BC30

PETN2

BD30

PETP2

AU30

PERN3

AT30

PERP3

AU32

PETN3

AV32

PETP3

BA32

PERN4

BB32

PERP4

BD32

PETN4

BE32

PETP4

BF33

PERN5

BH33

PERP5

BG32

PETN5

BJ32

PETP5

BA34

PERN6

AW34

PERP6

BC34

PETN6

BD34

PETP6

AT34

PERN7

AU34

PERP7

AU36

PETN7

AV36

PETP7

BG34

PERN8

BJ34

PERP8

BG36

PETN8

BJ36

PETP8

AK48

CLKOUT_PCIE0N

AK47

CLKOUT_PCIE0P

P9

PCIECLKRQ0# / GP IO73

AM43

CLKOUT_PCIE1N

AM45

CLKOUT_PCIE1P

U4

PCIECLKRQ1# / GP IO18

AM47

CLKOUT_PCIE2N

AM48

CLKOUT_PCIE2P

N4

PCIECLKRQ2# / GP IO20

AH42

CLKOUT_PCIE3N

AH41

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GP IO25

AM51

CLKOUT_PCIE4N

AM53

CLKOUT_PCIE4P

M9

PCIECLKRQ4# / GP IO26

AJ50

CLKOUT_PCIE5N

AJ52

CLKOUT_PCIE5P

H6

PCIECLKRQ5# / GP IO44

AK53

CLKOUT_PEG_B_N

AK51

CLKOUT_PEG_B_P

P13

PEG_B_CLKRQ# / GPIO56

IBEXPEAK-M_FCBGA1071~D

REV1.0

SMBALERT# / GP IO11

SML0ALERT# / GP IO60

SML1ALERT# / GP IO74

SMBus

PCI-E*

Link

Controller

PEG_A_CLKRQ# / GPIO47

PEG

CLKOUT_DP_N / C LKOUT_BCLK1_N CLKOUT_DP_P / C LKOUT_BCLK1_P

From CLK BUFFER

CLKIN_SATA_N / CKS SCD_N CLKIN_SATA_P / CKS SCD_P

CLKIN_PCILOOPBACK

CLKOUTFLEX0 / G PIO64

CLKOUTFLEX1 / G PIO65

CLKOUTFLEX2 / G PIO66

CLKOUTFLEX3 / G PIO67

Clock Flex

3

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK / GPIO58

SML1DATA / GPIO7 5

CL_CLK1

CL_DATA1

CL_RST1#

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_BCLK_N CLKIN_BCLK_P

CLKIN_DOT_96N CLKIN_DOT_96P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

EC_LID_OUT#

B9

H14

C8

PCH_GPIO60

J14

C6

G8

PCH_GPIO74

M14

PCH_SML1CLK

E10

PCH_SML1DAT

G12

T13

T11

T9

PEG_CLKREQ#_R

H1

Remove

AD43 AD45

AN4 AN2

AT1 AT3

AW24 BA24

AP3 AP1

F18 E18

AH13 AH12

P41

J42

AH51 AH53

XCLK_RCOMP

AF38

T45

P43

T42

N50

XTAL25_IN XTAL25_OUT

EC_LID_OUT# <31>

PCH_SMBCLK <6,11,12>

PCH_SMBDATA <6,11,12>

R43 10 K_0402_5%~DR43 10K_0402_5%~D

1 2

CLK_CPU_DMI# <6> CLK_CPU_DMI <6>

CLK_CPU_DP# <6> CLK_CPU_DP <6>

CLK_BUF_CPU_DMI# <13> CLK_BUF_CPU_DMI <13>

CLK_BUF_CPU_BCLK# <13> CLK_BUF_CPU_BCLK <13>

CLK_BUF_DREF_96M# <13> CLK_BUF_DREF_96M <13>

CLK_BUF_PCIE_SATA# <13> CLK_BUF_PCIE_SATA <13>

CLK_BUF_ICH_14M <13>

CLK_PCI_FB <19>

R127 90.9_0402_1%~DR127 90.9_0402_1%~D

1 2

2

1. Connect Directly XDCP of DDR3

2. Level Shift1, Pull-Up to +3VS CLOCK GEN, DIMM1, DIMM2, FFS

3. Level Shift2, Pull-Up to +3VS CPU & PCH XDP

+3VS

2

G

1 3

D

+3VS

2

1 3

D

+3VS

2

1 3

D

+3VS

2

1 3

D

G

12

+3V

R53

2.2K_0402_5%~D

R52

2.2K_0402_5%~D

PCH_SMBCLK

R1147

2.2K_0402_5%~D

PCH_SML1CLK

R1149

2.2K_0402_5%~D

PCH_SML1DAT

Buffer Mode check is need or not

C1027

C1027 27P_0402_50V8J~D

27P_0402_50V8J~D

1 2

12

Y2

+1.05VS

R548

1M_0402_5%~D

Y2

25MHZ_20P

1 2

C1028

C1028 27P_0402_50V8J~D

27P_0402_50V8J~D

Note: ADD 25MHz crystal for Display Clock Integration

1

R638

4.7K_0402_5%~D

1 2

S

Q47

Q47 2N7002LT1G_SOT23-3

2N7002LT1G_SOT23-3

R635

4.7K_0402_5%~D

1 2

S

Q46

Q46 2N7002LT1G_SOT23-3

2N7002LT1G_SOT23-3

EC_SMB_CK2

S

Q57

Q57 2N7002LT1G_SOT23-3

2N7002LT1G_SOT23-3

EC_SMB_DA2

S

Q58

Q58 2N7002LT1G_SOT23-3

2N7002LT1G_SOT23-3

R0.3 Modify

XTAL25_IN should be pulled to GND using a 0Ω resistor. (Calpella_Schematic_Checklist_Rev1.6)

SMBDATAPCH_SMBDATA

SMBCLK

+3VS

SMBDATA <11,12,13,14>

+3VS

SMBCLK <11,12,13,14>

EC_SMB_CK2 <27,28,31>

EC_SMB_DA2 <27,28,31>

@

+3V

EC_LID_OUT#

PCH_GPIO73

A A

PCH_GPIO60 PCH_GPIO25 PCH_GPIO26

PCH_GPIO74

PCH_GPIO44 PCH_GPIO56

R1113 10K_0402_5%~DR1113 10K_0402_5%~D

1 2

R81 10K_0402_ 5%~DR81 10K_0402_5%~D

1 2

R78 10K_0402_ 5%~DR78 10K_0402_5%~D

1 2

R1087 10K_0402_5%~DR1087 10K_0402_5%~D

1 2

R1023 10K_0402_5%~DR1023 10K_0402_5%~D

1 2

R84 10K_0402_ 5%~DR84 10K_0402_5%~D

1 2

R54 10K_0402_ 5%~DR54 10K_0402_5%~D

1 2

R95 10K_0402_ 5%~DR95 10K_0402_5%~D

1 2

5

+3VS

WWAN_CLK REQ# PCH_GPIO73

+3VS

CB_CLKREQ# PCH_GPIO25

@

1 2

R1203 10K_0402_5%~D

@

1 2

R1206 10K_0402_5%~D

@

1 2

R1209 10K_0402_5%~D

@

1 2

R1210 10K_0402_5%~D

G

S

@

G

S

@

4

2

Q64

13

D

2N7002LT1G_SOT23-3

2

Q67

13

D

2N7002LT1G_SOT23-3

+3VS +3VS

EXP_CLKREQ# PCH_GPIO26 GLAN_CLKREQ# PC H_GPIO44

@

1 2

R1204 10K_0402_5%~D

@

1 2

R1207 10K_0402_5%~D

Security Classification

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CON TAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CON TAINS CONFIDENTIAL AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

G

2

S

@

Issued Date

Q65

13

D

2N7002LT1G_SOT23-3

3

2009/09/21 2010/09/21

@

1 2

R1205 10K_0402_5%~D

1 2

R1208 10K_0402_5%~D@ R1208 10K_0402_5%~D@

Compal Secret Data

Deciphered Date

G

S

@

2

Q66

13

D

2N7002LT1G_SOT23-3

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PCH (2/9) PCIE, SMBUS, CLK

NAT02 M/B LA-5154P Schematic

1

16 49Thursday, November 26, 2009

1.0

5

D D

+3VS

@

1 2

R110 10K_0 402_5%~D

@

1 2

R1125 8.2K_0402_5%~ D

1 2

R1211 10K_0402_5%~ DR12 11 10K _0402_5%~D

1 2

R1088 8.2K_0402_5%~ DR1088 8.2K_0402_5%~ D

@

1 2

R69 10K _0402_5%~D

C C

B B

A A

R69 10K _0402_5%~D

1 2

R1114 10K_0402_5%~ DR11 14 10K _0402_5%~D

1 2

R72 10K _0402_5%~DR72 10K _0402_5%~D

1 2

R55 1K_ 0402_5%~DR55 1K_0402 _5%~D

10/2 Intel sugg estion change t o 10K

XDP_DBR ESET#

PM_CLKR UN#

PCH_GPIO7 2

PM_SLP_ LAN#

SUS_PW R_ACK

EC_SW I#

ICH_PCIE_W AKE#

+3V

ACIN<25,31,40,41 >

SYS_PW ROK

5

SYS_PW ROK VGATE

R66 10K _0402_5%~DR66 10K _0402_5%~D

CH751H-4 0PT_SOD323-2~ D

R37 0 _0402_5%~D@R37 0_0 402_5%~D@

SYS_PW ROK

ICH_PW ROK

LAN_RST #

No used Integrated LAN, connecting LAN_RST# to GND

DMI_HTX_P RX_N0<5 > DMI_HTX_P RX_N1<5 > DMI_HTX_P RX_N2<5 > DMI_HTX_P RX_N3<5 >

DMI_HTX_P RX_P0<5> DMI_HTX_P RX_P1<5> DMI_HTX_P RX_P2<5> DMI_HTX_P RX_P3<5>

DMI_PTX_H RX_N0<5 > DMI_PTX_H RX_N1<5 > DMI_PTX_H RX_N2<5 > DMI_PTX_H RX_N3<5 >

DMI_PTX_H RX_P0<5> DMI_PTX_H RX_P1<5> DMI_PTX_H RX_P2<5> DMI_PTX_H RX_P3<5>

+1.05VS+3V

R590

49.9_040 2_1%~D

1 2

XDP_DBR ESET#<6>

R58 0_0402_5% ~DR 58 0_0402_ 5%~D R70 0 _0402_5%~D@R70 0_0 402_5%~D@

1 2

+3VS

4

Y

1 2

R31 1 0K_0402_5%~DR31 10 K_0402_5%~D

1 2

R41 1 0K_0402_5%~DR41 10 K_0402_5%~D

1 2

R1115 1 0K_0402_5%~DR1115 10 K_0402_5%~D

12 12

PM_DRAM _PWRGD<6>

SUS_PW R_ACK<31>

PBTN_OU T#<6,31>

21

D50

12

5

U2

2

P

B

1

A

G

TC7SH08 FUF_SSOP5

3

ICH_PW ROK

VGATE

4

DMI_COMP

XDP_DBR ESET#

SYS_PW ROK_R

SYS_PW ROK

LAN_RST #

PCH_RSM RST#

SUS_PW R_ACK

PBTN_OU T#

PCH_ACIN

PCH_GPIO7 2

EC_SW I#

ICH_PW ROK <31>

VGATE <13,31,46 >

4

U47C

BC24

DMI0RXN

BJ22

DMI1RXN

AW20

DMI2RXN

BJ20

DMI3RXN

BD24

DMI0RXP

BG22

DMI1RXP

BA20

DMI2RXP

BG20

DMI3RXP

BE22

DMI0TXN

BF21

DMI1TXN

BD20

DMI2TXN

BE18

DMI3TXN

BD22

DMI0TXP

BH21

DMI1TXP

BC20

DMI2TXP

BD18

DMI3TXP

BH25

DMI_ZCOMP

BF25

DMI_IRCOMP

T6

SYS_RESET#

M6

SYS_PWROK

B17

PWROK

K5

MEPWROK

A10

LAN_RST#

D9

DRAMPWROK

C16

RSMRST#

M1

SUS_PWR_DN_ACK / GPIO30

P5

PWRBTN#

P7

ACPRESENT / GPIO31

A6

BATLOW# / GPIO72

F14

RI#

IBEXPEAK-M_ FCBGA1071~D

3

EC_TX_P 80_DATA<27,31>

UMA

REV1.0

FDI_FSYNC0

DMI

FDI

DMI

FDI

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

System Power Management

SLP_LAN# / GPIO29

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7

FDI_INT

WAKE#

SLP_S4#

SLP_S3#

SLP_M#

TP23

PMSYNCH

BA18 BH17 BD16 BJ16 BA16 BE14 BA14 BC12

BB18 BF17 BC16 BG16 AW16 BD14 BB14 BD12

BJ14

BF13

BH13

BJ12

BG14

ICH_PCIE_W AKE#

J12

PM_CLKR UN#

Y1

PCH_GPIO6 1

P8

PCH_GPIO6 2

F3

SLP_S5#

E4

H7

P12

PM_SLP_ M#

K8

PM_SLP_ DSW#

N2

BJ10

PM_SLP_ LAN#

F6

2009/09/ 21 2010/09/ 21

3

H_FDI_TXN 0 H_FDI_TXN 1 H_FDI_TXN 2 H_FDI_TXN 3 H_FDI_TXN 4 H_FDI_TXN 5 H_FDI_TXN 6 H_FDI_TXN 7

H_FDI_TXP 0 H_FDI_TXP 1 H_FDI_TXP 2 H_FDI_TXP 3 H_FDI_TXP 4 H_FDI_TXP 5 H_FDI_TXP 6 H_FDI_TXP 7

ICH_PCIE_W AKE# <24,27,28,31>

@

PAD

T4

@

PAD

T7

PM_SLP_ S4# <11>

SLP_S3# < 31>

@

PAD

T2

@

PAD

T8

H_PM_SYNC <6>

Compal Secret Data

Deciphered Date

H_FDI_TXN 0 <5> H_FDI_TXN 1 <5> H_FDI_TXN 2 <5> H_FDI_TXN 3 <5> H_FDI_TXN 4 <5> H_FDI_TXN 5 <5> H_FDI_TXN 6 <5> H_FDI_TXN 7 <5>

H_FDI_TXP 0 <5> H_FDI_TXP 1 <5> H_FDI_TXP 2 <5> H_FDI_TXP 3 <5> H_FDI_TXP 4 <5> H_FDI_TXP 5 <5> H_FDI_TXP 6 <5> H_FDI_TXP 7 <5>

H_FDI_INT <5>

H_FDI_FSYNC0 <5>

H_FDI_FSYNC1 <5>

H_FDI_LSYNC0 <5>

H_FDI_LSYNC1 <5>

2

PCH_RSM RST#

2

R1234

R30 0 _0402_5%~D

Q50

Q50 MMBT390 6_SOT23-3

MMBT390 6_SOT23-3

12

R32

R32 10K_040 2_5%~D

10K_040 2_5%~D

1

+3V

C1125

@

0_0402_ 5%~D

12

PM_SLP_ S4#

SLP_S5#

@

12

123

C

E

B

1 2

R27 4.7K _0402_5%~DR27 4 .7K_0402_5%~D

D3A

1

2

BAV99DW -7_SOT363

D3B

4

5

BAV99DW -7_SOT363

Title

PCH (3/9) DMI, FDI, PM

Size Document Num ber Rev

Custom

NAT02 M/B LA-5154P Schematic

Date: Sheet of

C1125

1 2

0.1U_040 2_10V6K~D

5

U62

1

P

IN1

4

O

2

IN2

G

74AHC1G 08GW_SOT3 53-5~D

3

12

R1233 0_ 0402_5%~D@ R1233 0_0 402_5%~D@

EC_RSMR ST# <31>

+3V

6

3

12

R39

2.2K_040 2_5%~D

Compal Electronics, Inc.

17 49Thursday, November 26, 2 009

1

PM_SLP_ S5# <31>

1.0

5

RU85 100K_0402_5%~ DRU85 100 K_0402_5%~D

D D

C C

B B

1 2

RU2 1 00K_0402_5%~ DRU2 100K_ 0402_5%~D

1 2

+3VS

change to 2.2k follow Intel ch ecklist ver.1. 6

RU6 2 .2K_0402_5%~DRU 6 2.2K_0402 _5%~D

1 2

RU7 2 .2K_0402_5%~DRU 7 2.2K_0402 _5%~D

1 2

RU8 1 0K_0402_5%~DRU8 1 0K_0402_5%~D

1 2

RU9 1 0K_0402_5%~DRU9 1 0K_0402_5%~D

1 2

RU10 2.2K_0402_5%~DR U10 2.2K_04 02_5%~D

1 2

RU11 2.2K_0402_5%~DR U11 2.2K_04 02_5%~D

1 2

RU94 2.2K_0402_5%~DR U94 2.2K_04 02_5%~D

1 2

RU95 2.2K_0402_5%~DR U95 2.2K_04 02_5%~D

1 2

RU101 2.2K _0402_5%~DRU10 1 2.2K _0402_5%~D

1 2

RU102 2.2K _0402_5%~DRU10 2 2.2K _0402_5%~D

1 2

RU12 150_0402_1%~DRU12 150 _0402_1%~D

RU13 150_0402_1%~DRU 13 150_04 02_1%~D

RU14 150_0402_1%~DRU 14 150_04 02_1%~D

VGA_LVD DEN

IGPU_BKLT _EN

1 2

LVDS_DD C_CLK

LVDS_DD C_DATA

LCTLA_C LK

LCTLB_D ATA

CRT_DDC _CLK

CRT_DDC _DATA

SDVO_SD ATA

DP_DDC_ DATA

SDVO_SC LK

DP_DDC_ CLK

VGA_CRT _B

VGA_CRT _G

VGA_CRT _R

4

1 2

IGPU_BKLT _EN

LVDS_DD C_CLK LVDS_DD C_DATA

LCTLA_C LK LCTLB_D ATA

LVDS_IBG

LVD_VRE F

LVDS_AC LKLVDS_AC LK+

LVDS_A0 LVDS_A1 LVDS_A2 -

LVDS_A0 + LVDS_A1 + LVDS_A2 +

LVDS_BC LKLVDS_BC LK+

LVDS_B0 LVDS_B1 LVDS_B2 -

LVDS_B0 + LVDS_B1 + LVDS_B2 +

VGA_CRT _B VGA_CRT _G VGA_CRT _R

CRT_DDC _CLK CRT_DDC _DATA

12

AB48

AB46

AP39 AP41

AV53 AV51

BB47 BA52 AY48 AV47

BB48 BA50 AY49 AV48

AP48 AP47

AY53

AU52

AY51

AU50

AA52 AB53 AD53

CRT_IREF

AD48 AB51

R126

R126 1K_0402 _0.5%~D

1K_0402 _0.5%~D

IGPU_BKLT _EN<31>

VGA_LVD DEN<3 5>

VGA_PW M<3 5>

LVDS_DD C_CLK<35>

LVDS_DD C_DATA< 35>

RU3 2.37K_ 0402_1%~DRU3 2.37K _0402_1%~D

RU4 0_040 2_5%~DRU4 0_0402_ 5%~D

LVDS_AC LK-<35> LVDS_AC LK+<35>

LVDS_A0 -<35> LVDS_A1 -<35> LVDS_A2 -<35>

LVDS_A0 +<35> LVDS_A1 +<35> LVDS_A2 +<35>

LVDS_BC LK-<35> LVDS_BC LK+<35>

LVDS_B0 -<35> LVDS_B1 -<35> LVDS_B2 -<35>

LVDS_B0 +<35> LVDS_B1 +<35> LVDS_B2 +<35>

VGA_CRT _B<35> VGA_CRT _G<3 5> VGA_CRT _R<35>

CRT_DDC _CLK<35> CRT_DDC _DATA<35 >

CRT_HSYNC<35> CRT_VSYNC<35>

3

U47D

T48

L_BKLTEN

T47

L_VDD_EN

Y48

L_BKLTCTL

L_DDC_CLK

Y45

L_DDC_DATA

L_CTRL_CLK

V48

L_CTRL_DATA

LVD_IBG LVD_VBG

AT43

LVD_VREFH

AT42

LVD_VREFL

LVDSA_CLK# LVDSA_CLK

LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3

LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3

LVDSB_CLK# LVDSB_CLK

LVDSB_DATA#0

AT49

LVDSB_DATA#1 LVDSB_DATA#2

AT53

LVDSB_DATA#3

LVDSB_DATA0

AT48

LVDSB_DATA1 LVDSB_DATA2

AT51

LVDSB_DATA3

CRT_BLUE CRT_GREEN CRT_RED

V51

CRT_DDC_CLK

V53

CRT_DDC_DATA

Y53

CRT_HSYNC

Y51

CRT_VSYNC

DAC_IREF CRT_IRTN

IBEXPEAK-M_ FCBGA1071~D

LVDS

CRT

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_CTRLDATA

DDPC_CTRLDATA

Digital Display Interface

DDPD_CTRLDATA

REV1.0

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

SDVO_CTRLCLK

DDPB_AUXN

DDPB_AUXP

DDPB_HPD

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_CTRLCLK

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DDPC_0N

DDPC_0P

DDPC_1N

DDPC_1P

DDPC_2N

DDPC_2P

DDPC_3N

DDPC_3P

DDPD_CTRLCLK

DDPD_AUXN DDPD_AUXP

DDPD_HPD

DDPD_0N

DDPD_0P

DDPD_1N

DDPD_1P

DDPD_2N

DDPD_2P

DDPD_3N

DDPD_3P

BJ46 BG46

BJ48 BG48

BF45 BH45

T51 T53

BG44 BJ44 AU38

BD42 BC42 BJ42 BG42 BB40 BA40 AW38 BA38

Y49 AB49

BE44 BD44 AV40

BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36

U50 U52

BC46 BD46 AT38

BJ40 BG40 BJ38 BG38 BF37 BH37 BE36 BD36

PCH_DPB _HPD

PCH_DPB _N0 PCH_DPB _P0 PCH_DPB _N1 PCH_DPB _P1 PCH_DPB _N2 PCH_DPB _P2 PCH_DPB _N3 PCH_DPB _P3

DP_DDC_ CLK DP_DDC_ DATA

DP_AUX# DP_AUX DP_HPD

2

RU5 1 00K_0402_5%~ DRU5 100K_ 0402_5%~D

1 2

CU7 0.1U_0402 _16V7K~DCU7 0.1U_04 02_16V7K~D

12

CU8 0.1U_0402 _16V7K~DCU8 0.1U_04 02_16V7K~D

12

CU9 0.1U_0402 _16V7K~DCU9 0.1U_04 02_16V7K~D

12

CU10 0.1U_0402 _16V7K~DCU10 0.1U_0 402_16V7K~D

12

CU11 0.1U_0402 _16V7K~DCU11 0.1U_0 402_16V7K~D

12

CU12 0.1U_0402 _16V7K~DCU12 0.1U_0 402_16V7K~D

12

CU13 0.1U_0402 _16V7K~DCU13 0.1U_0 402_16V7K~D

12

CU14 0.1U_0402 _16V7K~DCU14 0.1U_0 402_16V7K~D

12

DP_DDC_ CLK <37> DP_DDC_ DATA <37>

DP_AUX# <37> DP_AUX < 37> DP_HPD <37>

DISP_A0N_ VGA <37> DISP_A0P_ VGA <37 > DISP_A1N_ VGA <37> DISP_A1P_ VGA <37 > DISP_A2N_ VGA <37> DISP_A2P_ VGA <37 > DISP_A3N_ VGA <37> DISP_A3P_ VGA <37 >

SDVO_SC LK <36> SDVO_SD ATA <36>

PCH_DPB _HPD <36>

PCH_TMD S_D2# <36 > PCH_TMD S_D2 <36> PCH_TMD S_D1# <36 > PCH_TMD S_D1 <36> PCH_TMD S_D0# <36 > PCH_TMD S_D0 <36> PCH_TMD S_CK# < 36> PCH_TMD S_CK <3 6>

Display Port

1

HDMI D2

HDMI D1

HDMI D0

HDMI CLK

A A

Security Class ification

2009/09/ 21 2010/09/ 21

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/09/ 21 2010/09/ 21

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PCH (4/9) LVDS, CRT, DPI

Size Document Num ber Rev

Custom

NAT02 M/B LA-5154P Schematic

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

18 49Thursday, November 26, 2 009

1

1.0

5

+3VS

RP5

PCI_PIRQA#

1 8

PCI_PIRQG#

2 7

PCI_PIRQC#

3 6

PCI_SERR#

4 5

8.2K_1206_8P4R_5%~D

RP4

D D

C C

B B

RP4

PCI_PLOCK#

1 8

PCI_PERR#

2 7

PCI_PIRQH#

3 6

PCI_STOP#

4 5

8.2K_1206_8P4R_5%~D

RP9

PCI_REQ0#

1 8

PCI_PIRQB#

2 7

PCI_PIRQF#

3 6

PCI_REQ3#

4 5

8.2K_1206_8P4R_5%~D

RP6

1 8 2 7 3 6 4 5

1 2

R1239 8.2K_0402_5%~D

PCI_IRDY# PCI_PIRQD# PCI_REQ2# PCI_DEVSEL#

8.2K_1206_8P4R_5%~D

RP8

PCI_FRAME# PCI_REQ1#

PCI_TRDY#

8.2K_1206_8P4R_5%~D

ACCEL_INT#

Link to INT of G sensor

@

CLK_PCI_EC

CLK_PCI_FB

CLK_DEBUG_PORT<27>

@

10P_0402_50V8J~D

1 2

C1111

10P_0402_50V8J~D

1 2

C1112

@

CLK_PCI_EC<31> CLK_PCI_FB<16>

ACCEL_INT#<14>

PCI_PLTRST#<6>

R1031 22_0402_5%~DR1031 22_0402_5%~D

1 2

R1116 22_0402_5%~DR1116 22_0402_5%~D

1 2

R99 22_0402_5%~DR99 22_0402_5%~D

1 2

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

PCI_REQ0# PCI_REQ1# PCI_REQ2# PCI_REQ3#

PCI_GNT0# PCI_GNT1#

PCI_GNT3#

PCI_PIRQF# PCI_PIRQG# PCI_PIRQH#

PCI_SERR# PCI_PERR#

PCI_IRDY#

PCI_DEVSEL# PCI_FRAME#

PCI_PLOCK#

PCI_STOP# PCI_TRDY#

PCI_PLTRST#

R_CLK_DEBUG_PORT R_CLK_PCI_EC R_CLK_PCI_FB

2008/1/6 2009MOW01 change to 22 ohm

Boot BIOS Strap

PCI_GNT#0 PCI_GNT#1

0 0

A A

0 1

1 0

1 1

*

A16 swap override Strap/Top-Block

Swap Override jumper

PCI_GNT#3

Low = A16 swap High = Default

Boot BIOS Location

LPC

Reserved (NAND)

PCI

SPI

5

PCI_GNT0#

PCI_GNT1#

PCI_GNT3#

4

U47E

H40

AD0

N34

AD1

C44

AD2

A38

AD3

C36

AD4

J34

AD5

A40

AD6

D45

AD7

E36

AD8

H48

AD9

E40

AD10

C40

AD11

M48

AD12

M45

AD13

F53

AD14

M40

AD15

M43

AD16

J36

AD17

K48

AD18

F40

AD19

C42

AD20

K46

AD21

M51

AD22

J52

AD23

K51

AD24

L34

AD25

F42

AD26

J40

AD27

G46

AD28

F44

AD29

M47

AD30

H36

AD31

J50

C/BE0#

G42

C/BE1#

H47

C/BE2#

G34

C/BE3#

G38

PIRQA#

H51

PIRQB#

B37

PIRQC#

A44

PIRQD#

F51

REQ0#

A46

REQ1# / GPIO50

B45

REQ2# / GPIO52

M53

REQ3# / GPIO54

F48

GNT0#

K45

GNT1# / GPIO51

F36

GNT2# / GPIO53

H53

GNT3# / GPIO55

B41

PIRQE# / GPIO2

K53

PIRQF# / GPIO3

A36

PIRQG# / GPIO4

A48

PIRQH# / GPIO5

K6

PCIRST#

E44

SERR#

E50

PERR#

A42

IRDY#

H44

PAR

F46

DEVSEL#

C46

FRAME#

D49

PLOCK#

D41

STOP#

C48

TRDY#

M7

PME#

D5

PLTRST#

N52

CLKOUT_PCI0

P53

CLKOUT_PCI1

P46

CLKOUT_PCI2

P51

CLKOUT_PCI3

P48

CLKOUT_PCI4

IBEXPEAK-M_FCBGA1071~D

R75 1K_0402_5 %~D@R75 1K_0402_5%~D@

1 2

R83 1K_0402_5 %~D@R83 1K_0402_5%~D@

1 2

R1117 1K_0402_5%~D@R1117 1K_0402_5%~D@

1 2

4

REV1.0

PCI

NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3

NV_DQS0 NV_DQS1

NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8

NV_DQ9 / NV_IO9 NV_DQ10 / NV_IO10 NV_DQ11 / NV_IO11

NVRAM

NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15

NV_ALE

NV_CLE

NV_RCOMP

NV_RB#

NV_WR# 0_RE# NV_WR# 1_RE#

NV_WE#_C K0 NV_WE#_C K1

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P

USB

USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43

OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14

3

AY9 BD1 AP15 BD8

AV9 BG8

AP7 AP6 AT6 AT9 BB1 AV6 BB3 BA4 BE4 BB6 BD6 BB7 BC8 BJ8 BJ6 BG6

BD3 AY6

AU2

AV7

AY8 AY5

AV11 BF5

H18 J18 A18 C18 N20 P20 J20 L20 F20 G20 A20 C20 M22 N22 B21 D21 H22 J22 E22 F22 A22 C22 G24 H24 L24 M24 A24 C24

B25

D25

N16 J16 F16 L16 E14 G16 F12 T15

NV_ALE NV_CLE

NV_RCOMP

USBP0USBP0+ USBP1USBP1+ USBP2USBP2+ USBP3USBP3+ USBP4USBP4+ USBP5USBP5+

USBP8USBP8+ USBP9USBP9+ USBP10USBP10+ USBP11USBP11+

USB_BIAS

USB_OC0#_R USB_OC1#_R USB_OC2#_R USB_OC3# USB_OC4# USB_OC5# USB_OC6# USB_OC7#

Danbury Technology Enabled

NV_ALE

DMI Termination Voltage

NV_CLE

R167 1K_0402_5%~D@R167 1K_0402_5%~D@

1 2

R172 1K_0402_5%~D@R172 1K_0402_5%~D@

1 2

R153 32.4_0402_ 1%~OKR153 32.4_0402_1%~OK

1 2

USBP0- <30> USBP0+ <30> USBP1- <30> USBP1+ <30> USBP2- <30> USBP2+ <30> USBP3- <28> USBP3+ <28> USBP4- <27> USBP4+ <27> USBP5- <27>

From PCH EDS 5.18, USB port6 & 7 are not available in all sku.

USBP5+ <27>

USBP8- <28> USBP8+ <28> USBP9- <32> USBP9+ <32> USBP10- <30> USBP10+ <30> USBP11- <30> USBP11+ <30>

1 2

R63

22.6_0402_1%~D

R48 0_ 0402_5%~DR48 0_0402_5%~D

1 2

R67 0_ 0402_5%~DR67 0_0402_5%~D

1 2

R28 0_ 0402_5%~DR28 0_0402_5%~D

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CON TAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CON TAINS CONFIDENTIAL AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

High = Enabled

Low = Disabled

Set to Vss when LOW

Set to Vcc when HIGH

+VCCQ_NAND

EHCI 1

EHCI 2

@

@ @

@

OC[0..3] use for EHCI 1 OC[4..7] use for EHCI 2

2009/09/21 2010/09/21

ESATA_USB_OC# <30> USB_OC1# <30> USB_OC2# <30>

PAD

T114

PAD

T115

PAD

T116

PAD

T117

PAD

T118

Compal Secret Data

PCI_PLTRST#

Deciphered Date

2

C976

0.1U_0402_16V4Z~D

@

R1030 0_0402_5%~D

USB Port

0

1

2

3

4

5

6

7

8

9

10

11

USB&ESATA Reader board

USB board

WPAN WLAN WWAN

NC NC

Express

Touch screen Bluetooth

Camera

2

1

2

1

12

Device

+3VS

5

B

A

3

1

U44

P

Y

G

MC74VHC1G08DFT2G SC70 5P

PLT_RST#

4

12

R1139

R1139 1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

USB_OC0#_R USB_OC1#_R USB_OC2#_R USB_OC3#

USB_OC4# USB_OC5# USB_OC6# USB_OC7#

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

PCH (5/9) PCI, USB, VRAM

NAT02 M/B LA-5154P Schematic

PLT_RST# <6,24,27,28,30,31>

RP10

1 8 2 7 3 6 4 5

10K_1206_8P4R_5%~D

RP7

1 8 2 7 3 6 4 5

10K_1206_8P4R_5%~D

1

+3V

1.0

19 49Thursday, November 26, 2009

1.0

5

4

3

2

1

+3VS

PCH_GPIO0

@

PAD

T119

R107 10K_0 402_5%~DR1 07 10K_0402_5%~D

1 2

R62 1 0K_0402_5%~DR62 10 K_0402_5%~D

1 2

R1126 10K_0402_ 5%~DR1126 10K_0402 _5%~D

1 2

R73 1 0K_0402_5%~DR73 10 K_0402_5%~D

1 2

R87 1 0K_0402_5%~DR87 10 K_0402_5%~D

D D

C C

B B

1 2

R1127 10K_0402_ 5%~DR1127 10K_0402 _5%~D

1 2

R1128 10K_0402_ 5%~DR1128 10K_0402 _5%~D

1 2

R133 10K_0 402_5%~DR1 33 10K_0402_5%~D

1 2

R128 10K_0 402_5%~DR1 28 10K_0402_5%~D

1 2

R120 10K_0 402_5%~DR1 20 10K_0402_5%~D

1 2

R1129 10K_0402_ 5%~DR1129 10K_0402 _5%~D

1 2

R61 1 0K_0402_5%~DR61 10 K_0402_5%~D

1 2

R100 10K_0 402_5%~DR1 00 10K_0402_5%~D

1 2

R1032 10K_0402_ 5%~DR1032 10K_0402 _5%~D

1 2

+3V

R59 1 0K_0402_5%~DR59 10 K_0402_5%~D

1 2

R47 1 0K_0402_5%~DR47 10 K_0402_5%~D

1 2

R86 1 K_0402_5%~DR86 1K _0402_5%~D

1 2

10/7 Not Use PCH_GPIO15 PU 1K to +3V

R117 10K_0 402_5%~DR1 17 10K_0402_5%~D

1 2

R1118 10K_0402_ 5%~DR1118 10K_0402 _5%~D

1 2

R1119 10K_0402_ 5%~DR1119 10K_0402 _5%~D

1 2

C1559 0.047U_0402 _16V4Z~DC1559 0.047U_0402 _16V4Z~D

1 2

R106 10K_0 402_5%~DR1 06 10K_0402_5%~D

1 2

R68 1 0K_0402_5%~DR68 10 K_0402_5%~D

1 2

R134 10K_0 402_5%~D@R134 10K_0402 _5%~D@

1 2

GPIO27 (Have internal Pull-High) High: VCCVRM VR Enable Low: VCCVRM VR Disable

PCH_GPIO0

PCH_GPIO1 6 GPIO17 PCH_GPIO2 2 VGA_PRS NT_R# VGA_PRS NT_L# PCH_GPIO3 6 PCH_GPIO3 7 PCH_GPIO4 8 PCH_GPIO4 9 LAN_LOP WEN PCH_GPIO3 4 LAN_CAB DT

EC_SCI# EC_SMI#

PCH_GPIO1 5

PCH_GPIO2 8

PCH_GPIO4 5 PCH_GPIO4 6

R1.0 modify

PCH_GPIO3 5 PCH_GPIO5 7

PCH_GPIO2 7

(Rev:1.0 GPIO24 Only)

T119

LAN_LOP WEN<24>

LAN_CAB DT< 24>

EC_SMI#<31>

EC_SCI#<31>

PAD

T120

PAD

T121

PAD

T122

PAD

T123

DDR_RST _GATE< 6,11,12>

PCH_GPIO4 9<31 >

@

PCH_GPIO1PCH_GPIO1

LAN_LOP WEN

LAN_CAB DT

EC_SMI#

EC_SCI#

PCH_GPIO1 5

PCH_GPIO1 6

GPIO17

PCH_GPIO2 2

PCH_GPIO2 7

PCH_GPIO2 8

PCH_GPIO3 4

PCH_GPIO3 5

PCH_GPIO3 6

PCH_GPIO3 7

VGA_PRS NT_R#

VGA_PRS NT_L#

PCH_GPIO4 5

PCH_GPIO4 6

PCH_GPIO4 8

PCH_GPIO4 9

PCH_GPIO5 7

U47F

Y3

BMBUSY# / GPIO0

C38

TACH1 / GPIO1

D37

TACH2 / GPIO6

J32

TACH3 / GPIO7

F10

GPIO8

K9

LAN_PHY_PWR_CTRL / GPIO12

T7

GPIO15

AA2

SATA4GP / GPIO16

F38

TACH0 / GPIO17

Y7

SCLOCK / GPIO22

H10

GPIO24

AB12

GPIO27

V13

GPIO28

M11

STP_PCI# / GPIO34

V6

SATACLKREQ# / GPIO35

AB7

SATA2GP / GPIO36

AB13

SATA3GP / GPIO37

V3

SLOAD / GPIO38

P3

SDATAOUT0 / GPIO39

H3

PCIECLKRQ6# / GPIO45

F1

PCIECLKRQ7# / GPIO46

AB6

SDATAOUT1 / GPIO48

AA4

SATA5GP / GPIO49

F8

GPIO57

A4

VSS_NCTF_1

A49

VSS_NCTF_2

A5

VSS_NCTF_3

A50

VSS_NCTF_4

A52

VSS_NCTF_5

A53

VSS_NCTF_6

B2

VSS_NCTF_7

B4

VSS_NCTF_8

B52

VSS_NCTF_9

B53

VSS_NCTF_10

BE1

VSS_NCTF_11

BE53

VSS_NCTF_12

BF1

VSS_NCTF_13

BF53

VSS_NCTF_14

BH1

VSS_NCTF_15

BH2

VSS_NCTF_16

BH52

VSS_NCTF_17

BH53

VSS_NCTF_18

BJ1

VSS_NCTF_19

BJ2

VSS_NCTF_20

BJ4

VSS_NCTF_21

BJ49

VSS_NCTF_22

BJ5

VSS_NCTF_23

BJ50

VSS_NCTF_24

BJ52

VSS_NCTF_25

BJ53

VSS_NCTF_26

D1

VSS_NCTF_27

D2

VSS_NCTF_28

D53

VSS_NCTF_29

E1

VSS_NCTF_30

E53

VSS_NCTF_31

IBEXPEAK-M_ FCBGA1071~D

MISC

CLKOUT_BCLK0_N / CLKOUT_PCIE8N

CLKOUT_BCLK0_P / CLKOUT_PCIE8P

GPIO

CPU

NCTF

RSVD

REV1.0

CLKOUT_PCIE6N

CLKOUT_PCIE6P

CLKOUT_PCIE7N

CLKOUT_PCIE7P

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

TP10

TP11

TP12

TP13

TP14

TP15

TP16

TP17

TP18

TP19

NC_1

NC_2

NC_3

NC_4

NC_5

INIT3_3V#

TP24

AH45 AH46

AF48 AF47

U2

AM3

AM1

BG10

T1

BE10

BD10

BA22

TP1

AW22

TP2

BB22

TP3

AY45

TP4

AY46

TP5

AV43

TP6

AV45

TP7

AF13

TP8

M18

TP9

N18

AJ24

AK41

AK42

M32

N32

M30

N30

H12

AA23

AB45

AB38

AB42

AB41

T39

(Do not pull hi gh)

P6

C10

GATEA20

KB_RST#

TP24_SS T

GATEA20 <31 >

CLK_CPU _BCLK# <6>

CLK_CPU _BCLK <6>

H_PECI <6>

KB_RST# <31>

H_CPUPW RGD <6 >

WW46 Platform/Design Updates 2008/11/17 54.9 1% ->56 5%

@

PAD

T6

12

R175 56_0402_1%~ DR175 56_0402_1% ~D

H_THERM TRIP#THRMTRIP_ PCH#

+1.1VS_V TT

GATEA20

KB_RST#

12

R183 56_0402_1%~ DR183 56_0402_1% ~D

R184

330_040 2_5%~D@

1 2

H_THERM TRIP#

R101 10K_0 402_5%~DR1 01 10K_0402_5%~D

1 2

R121 10K_0 402_5%~DR1 21 10K_0402_5%~D

1 2

H_THERM TRIP# < 6>

+1.1VS_V TT

MAINPW ON <42 ,47>

1

C

Q51

2

B

E

2SC2411 K_SOT23

3

@

+3VS

A A

Security Class ification

2009/09/ 21 2010/09/ 21

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/09/ 21 2010/09/ 21

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PCH (6/9) GPIO, CPU, MISC

Size Document Num ber Rev

Custom

NAT02 M/B LA-5154P Schematic

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

20 49Thursday, November 26, 2 009

1

1.0

5

4

3

2

1

+1.05VS

POWER

U47G

1U_0402 _6.3V4Z~D

10U_080 5_10V4Z~D

D D

All Ibex Peak-M Power rails with netnames +1.1VS and +1.1V rails are actually +1.05VS and +1.05V rails

Intel suggest follow CRB 8/21

+1.05VS

1uH inductor, 405mA

DG 0.8 is 1uH Inductor (Page 291)

C C

10U_080 5_10V4Z~D

C114

Top Side

Have Internal VRM (DG0.8 Page 293)

+1.05VS

1

2

Near AN20

C80

1U_0402 _6.3V4Z~D

1

2

1U_0402 _6.3V4Z~D

C85

1

2

1

2

Near AB24 Top Side

L81

@L81

@

1 2

1UH_CBC 2012T1R0M_20 %~D

C90

1U_0402 _6.3V4Z~D

Near AN35

Follow Intel suggestion 8/21

B B

+1.05VS

L40

1 2

1UH_CBC 2012T1R0M_20 %~D

1uH inductor, 405mA

Change to 0 ohm for discrete

DG 0.8 is 1uH Inductor (Page 291) Have Internal VRM (DG0.8 Page 293)

C94

C978

C978 10U_080 5_10V4Z~D

10U_080 5_10V4Z~D

@

1U_0402 _6.3V4Z~D

C63

C107

Near AB24

10U_080 5_10V4Z~D

1U_0402 _6.3V4Z~D

1

C83

2

0.1U_040 2_16V4Z~D

12

+VCCVRM

1

2

1

2

+1.05VS

+VCCAPL L_EXP

1

C1029

@

2

1

2

+3VS

+VCCAPL L_FDI

+1.05VS

U47G

AB24

VCCCORE[1]

AB26

VCCCORE[2]

AB28

VCCCORE[3]

AD26

VCCCORE[4]

AD28

VCCCORE[5]

AF26

VCCCORE[6]

AF28

VCCCORE[7]

AF30

VCCCORE[8]

AF31

VCCCORE[9]

AH26

VCCCORE[10]

AH28

VCCCORE[11]

AH30

VCCCORE[12]

AH31

VCCCORE[13]

AJ30

VCCCORE[14]

AJ31

VCCCORE[15]

AK24

VCCIO[24]

42mA

BJ24

VCCAPLLEXP

AN20

VCCIO[25]

AN22

VCCIO[26]

AN23

VCCIO[27]

AN24

VCCIO[28]

AN26

VCCIO[29]

AN28

VCCIO[30]

BJ26

VCCIO[31]

BJ28

VCCIO[32]

AT26

VCCIO[33]

AT28

VCCIO[34]

AU26

VCCIO[35]

AU28

VCCIO[36]

AV26

VCCIO[37]

AV28

VCCIO[38]

AW26

VCCIO[39]

AW28

VCCIO[40]

BA26

VCCIO[41]

BA28

VCCIO[42]

BB26

VCCIO[43]

BB28

VCCIO[44]

BC26

VCCIO[45]

BC28

VCCIO[46]

BD26

VCCIO[47]

BD28

VCCIO[48]

BE26

VCCIO[49]

BE28

VCCIO[50]

BG26

VCCIO[51]

BG28

VCCIO[52]

BH27

VCCIO[53]

AN30

VCCIO[54]

AN31

VCCIO[55]

AN35

VCC3_3[1]

AT22

VCCVRM[1]

BJ18

VCCFDIPLL

AM23

VCCIO[1]

IBEXPEAK-M_ FCBGA1071~D

POWER

1524mA

3208mA

35mA

6mA

VCC CORE

PCI E*

FDI

69mA

CRTLVDS

HVCMOS

DMI

NAND / SPI

REV1.0

VCCADAC[1]

VCCADAC[2]

VSSA_DAC[1]

VSSA_DAC[2]

300mA

VCCALVDS

VSSA_LVDS

59mA

VCCTX_LVDS[1] VCCTX_LVDS[2] VCCTX_LVDS[3] VCCTX_LVDS[4]

VCC3_3[2]

VCC3_3[3]

VCC3_3[4]

35mA

VCCVRM[2]

61mA

VCCDMI[1]

VCCDMI[2]

156mA

VCCPNAND[1] VCCPNAND[2] VCCPNAND[3] VCCPNAND[4] VCCPNAND[5] VCCPNAND[6] VCCPNAND[7] VCCPNAND[8] VCCPNAND[9]

85mA

VCCME3_3[1] VCCME3_3[2] VCCME3_3[3] VCCME3_3[4]

+VCCADA C

AE50

AE52

AF53

AF51

+VCCA_L VDS

AH38

AH39

AP43 AP45 AT46

+VCCTX_ LVDS

AT45

0.01U_04 02_16V7K~D

AB34

AB35

AD35

1

C58

0.1U_040 2_16V4Z~D

2

+VCCVRM

AT24

AT16

+VCC_DM I

AU16

AM16 AK16 AK20 AK19 AK15 AK13 AM12 AM13 AM15

AM8 AM9 AP11 AP9

12

R125

R125 0_0402_ 5%~D

0_0402_ 5%~D

@

RU15 0.022_0805_1%~ OKRU15 0.022_0805_1%~ OK

Near AP43

1

CU15

2

+3VS

Near AB34

R174 0_080 5_5%~D@R 174 0_0805_5%~D@

R182 0_080 5_5%~D@R 182 0_0805_5%~D@

R188 0.022_ 0805_1%~OKR188 0.022_ 0805_1%~OK

1

C95

C95 1U_0402 _6.3V4Z~D

1U_0402 _6.3V4Z~D

2

Near AT16

1

C79

0.1U_040 2_16V4Z~D

2

Near AK13

+3VS

1

C97

0.1U_040 2_16V4Z~D

2

Near AM8

0.01U_04 02_16V7K~D

1

C72

1 2

0.01U_04 02_16V7K~D

1 2

C69

0.1U_040 2_16V4Z~D

2

1

CU16

2

R181 0.022_ 0805_1%~OKR181 0.022_ 0805_1%~OK

R189 0.022_ 0805_1%~OK@R189 0.022_08 05_1%~OK@

R138 0.022_ 0805_1%~OKR138 0.022_ 0805_1%~OK

1

2

1 2

60mA

1

C64

C64 47U_080 5_4V6M~D

47U_080 5_4V6M~D

2

Near AE50

change to 47U

+3VS

0.1UH_ML F1608DR10KT_ 10%_1608

CU17

22U_080 5_6.3V6M~OK

0.1UH_ML F1608DR10KT_ 10%_1608

0.1uH inductor, 200mA

+1.05VS

+1.5VS

+1.8VS

+1.1VS_V TT

+1.05VS

+1.8VS+VCCQ_N AND

LU1

L9

1 2

2_0603_ 5%~D

1

2

2_0603_ 5%~D

change to 2ohm

12

+3VS

CRB 0.9 is 180 ohm @ 100MHz DG0.8 is 600 ohm FB (Page 290)

UMA

+1.8VS

A A

Security Class ification

2009/09/ 21 2010/09/ 21

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/09/ 21 2010/09/ 21

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PCH (7/9) PWR

NAT02 M/B LA-5154P Schematic

21 49Thursday, November 26, 2 009

1

1.0

5

+1.05VS

L13

@L13

DG 0.8 is 10uH Inductor (Page 290) Have Internal VRM (DG0.8 Page 293)

+1.05VS

R124

@R124

@

1 2

0_0603_ 5%~D

D D

0_0402_ 5%~D

10uH inductor, 120mA

12

R131

@

1 2

10UH_LB 2012T100MR_2 0%~D

C92

C92 10U_080 5_10V4Z~D

10U_080 5_10V4Z~D

@

1

C65

C65 1U_0402 _6.3V4Z~D

1U_0402 _6.3V4Z~D

2

@

Near AF23

+1.05VS

22U_080 5_6.3V6M~OK

1

C48

2

22U_080 5_6.3V6M~OK

All Ibex Peak-M Power rails with netnames +1.1VS and +1.1V rails are actually +1.05VS and +1.05V rails

1

C60

2

Near AD38 Near V39

Follow Intel suggestion

1

C70

2

1U_0402 _6.3V4Z~D

C40

C40 22U_080 5_6.3V6M~OK

22U_080 5_6.3V6M~OK

Near V9

C C

+1.05VS

1U_0402 _6.3V4Z~D

+1.05VS

LU9

1 2

10UH_LB 2012T100MR_2 0%~D

CU64

1U_0402 _6.3V4Z~D

B B

A A

Follow Intel design

1U_0402 _6.3V4Z~D

5

2

1

CU65

2

1U_0402 _6.3V4Z~D

+1.1VS_V TT

C113

4.7U_080 5_10V4Z~D

+RTCVCC

1U_0402 _6.3V4Z~D

1

C73

1U_0402 _6.3V4Z~D

1

C74

2

1U_0402 _6.3V4Z~D

1

CU66

2

+3V

0.1U_040 2_16V4Z~D

+3VS

0.1U_040 2_16V4Z~D

1

C89

2

0.1U_040 2_16V4Z~D

1

C24

C19

2

0.1U_040 2_16V4Z~D

+1.1VS_V CCACLK

1

2

Near AP51

1

C57

0.1U_040 2_16V4Z~D

2

1

2

C51

0.1U_040 2_16V4Z~D

1 2

+VCCVRM

+VCCADP LLA

+VCCADP LLB

Near AH23Near AJ35Near AH35

1

C78

C78 1U_0402 _6.3V4Z~D

1U_0402 _6.3V4Z~D

2

1U_0402 _6.3V4Z~D

1

2

0.1U_040 2_16V4Z~D

1

C46

2

1

C53

2

1

0.1U_040 2_16V4Z~D

2

1

0.1U_040 2_16V4Z~D

2

4

1

C86

C86 1U_0402 _6.3V4Z~D

1U_0402 _6.3V4Z~D

2

@

+PCH_VC CD6W

Near Y20

1

C49

2

1U_0402 _6.3V4Z~D

+VCCRTC EXT

+VCCSST

1 2

C50

C56

1 2

Near V12

+VCCSUS

Near Y22

Near P18

Near V15

1

C99

2

Near AT18

1

C25

2

Near A12

4

3

POWER

U47J

52mA

AP51

VCCACLK[1]

AP53

VCCACLK[2]

344mA

AF23

VCCLAN[1]

AF24

VCCLAN[2]

Y20

DCPSUSBYP

1998mA

AD38

VCCME[1]

AD39

VCCME[2]

AD41

VCCME[3]

AF43

VCCME[4]

AF41

VCCME[5]

AF42

VCCME[6]

V39

VCCME[7]

V41

VCCME[8]

V42

VCCME[9]

Y39

VCCME[10]

Y41

VCCME[11]

Y42

VCCME[12]

V9

DCPRTC

AU24

VCCVRM[3]

BB51

VCCADPLLA[1]

BB53

VCCADPLLA[2]

BD51

VCCADPLLB[1]

BD53

VCCADPLLB[2]

AH23

VCCIO[21]

AJ35

VCCIO[22]

AH35

VCCIO[23]

AF34

VCCIO[2]

AH34

VCCIO[3]

AF32

VCCIO[4]

V12

DCPSST

Y22

DCPSUS

P18

VCCSUS3_3[29]

U19

VCCSUS3_3[30]

U20

VCCSUS3_3[31]

U22

VCCSUS3_3[32]

V15

VCC3_3[5]

V16

VCC3_3[6]

Y16

VCC3_3[7]

> 1mA

AT18

V_CPU_IO[1]

AU18

V_CPU_IO[2]

2mA

A12

VCCRTC

IBEXPEAK-M_ FCBGA1071~D

POWER

REV1.0

VCCSUS3_3[1] VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4] VCCSUS3_3[5] VCCSUS3_3[6] VCCSUS3_3[7] VCCSUS3_3[8]

VCCSUS3_3[9] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13]

USB

VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16]

163mA

VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] VCCSUS3_3[20] VCCSUS3_3[21] VCCSUS3_3[22] VCCSUS3_3[23] VCCSUS3_3[24] VCCSUS3_3[25] VCCSUS3_3[26] VCCSUS3_3[27]

VCCSUS3_3[28]

>1mA

V5REF_SUS

72mA

Clock and Miscellaneous

Issued Date

Clock and Miscellaneous

PCI/GPIO/LPC

SATA

CPU

RTC PCI/GPIO/LPC

HDA

VCC3_3[10]

VCC3_3[11]

VCC3_3[12]

VCC3_3[13]

VCC3_3[14]

VCCSATAPLL[1] VCCSATAPLL[2]

VCCVRM[4]

VCCME[13] VCCME[14] VCCME[15] VCCME[16]

VCCSUSHDA

3

73mA

Security Class ification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

V24

VCCIO[5]

V26

VCCIO[6]

Y24

VCCIO[7]

Y26

VCCIO[8]

V28 U28 U26 U24 P28 P26 N28 N26 M28 M26 L28 L26 J28 J26 H28 H26 G28 G26 F28 F26 E28 E26 C28 C26 B27 A28 A26

U23

V23

VCCIO[56]

F24

>1mA

K49

V5REF

357mA

J38

VCC3_3[8]

L38

VCC3_3[9]

M36

N36

P36

U35

AD13

32mA

AK3 AK1

AH22

VCCIO[9]

AT20

AH19

VCCIO[10]

AD20

VCCIO[11]

AF22

VCCIO[12]

AD19

VCCIO[13]

AF20

VCCIO[14]

AF19

VCCIO[15]

AH20

VCCIO[16]

AB19

VCCIO[17]

AB20

VCCIO[18]

AB22

VCCIO[19]

AD22

VCCIO[20]

AA34 Y34 Y35 AA35

6mA

L30

2009/09/ 21 2010/09/ 21

+1.05VS

+VCC5RE FSUS

+VCC5RE F

Near J38

+VCCSAT APLL

PCH_VCC ME13 PCH_VCC ME14 PCH_VCC ME15 PCH_VCC ME16

Compal Secret Data

1

C54

C54 1U_0402 _6.3V4Z~D

1U_0402 _6.3V4Z~D

2

Near V24

1

C1031

0.1U_040 2_16V4Z~D

2

Near A26

+3V

D48

21

CH751H-4 0PT_SOD323-2~ D

1 2

C28

12

1U_0402 _6.3V6K~D

Near F24

Change to 1U fo r power sequence issue on ICH9

+3VS

1

C38

0.1U_040 2_16V4Z~D

2

1 2

C84

+1.05VS

C37 1 U_0402_6.3V4Z ~DC37 1U_0402_6.3V 4Z~D

Deciphered Date

C84 10U_080 5_10V4Z~D

10U_080 5_10V4Z~D

@

+VCCVRM

+1.05VS

1

C66

C66 1U_0402 _6.3V4Z~D

1U_0402 _6.3V4Z~D

2

Near AB19

R118 0_060 3_5%~DR118 0_060 3_5%~D

1 2

R92 0 _0603_5%~DR92 0_060 3_5%~D

1 2

R102 0_060 3_5%~DR102 0_060 3_5%~D

1 2

R109 0_060 3_5%~DR109 0_060 3_5%~D

1 2

2

+1.05VS

+3V

1

C47

0.1U_040 2_16V4Z~D

2

Near U23

R49

R49 10_0402 _5%~D

10_0402 _5%~D

+3VS

Near AD13

C67

0.1U_040 2_16V4Z~D

1

2

+1.05VS

+3V

Near L30

2

Follow Intel Suggestion 8/21

+5V

Near K49

L84

@L84

@

1 2

10UH_LB 2012T100MR_2 0%~D

1

10uH inductor, 120mA

C75

C75 1U_0402 _6.3V4Z~D

1U_0402 _6.3V4Z~D

2

@

Near AK1

1

12

Near BD51

+5VALW

S

G

D

1 3

+5V

22 49Thursday, November 26, 2 009

+VCCADP LLA

R569

R569 0_0402_ 5%~D

0_0402_ 5%~D

@

+VCCADP LLB

+1.05VS

1

+

2

1

+

2

+5VS

R1156

R1156 0_0402_ 5%~D

0_0402_ 5%~D

12

C1074

Near BB51

1

C104

C104 1U_0402 _6.3V4Z~D

1U_0402 _6.3V4Z~D

2

1

C109

C109 1U_0402 _6.3V4Z~D

1U_0402 _6.3V4Z~D

2

Q62

1

AO3413_ SOT23-3

2

1

L82

1 2

10UH_LB 2012T100MR_2 0%~D

10uH inductor, 120mA

C1030

220U_D2 _4VM_R15~D

L83

1 2

10UH_LB 2012T100MR_2 0%~D

10uH inductor, 120mA

C1032

220U_D2 _4VM_R15~D

+3VS

21

D49

D49 CH751H-4 0PT_SOD323-2~ D

CH751H-4 0PT_SOD323-2~ D

R97

R97 10_0402 _5%~D

10_0402 _5%~D

1 2

C36

12

1U_0402 _6.3V6K~D

SBPW R_EN#<33>

Title

PCH (8/9) PWR

Size Document Num ber Rev

Custom

NAT02 M/B LA-5154P Schematic

Date: Sheet of

Follow Intel Suggestion 8/21

+1.05VS

DG 0.8 is 10uH Inductor (Page 291) Have Internal VRM (DG0.8 Page 293)

0.1U_040 2_16V4Z~D

Compal Electronics, Inc.

1.0

5

U47I

AY7

VSS[159]

B11

VSS[160]

B15

VSS[161]

B19

VSS[162]

B23

VSS[163]

B31

VSS[164]

B35

VSS[165]

B39

VSS[166]

B43

VSS[167]

B47

VSS[168]

B7

VSS[169]

D D

C C

B B

A A

BG12

VSS[170]

BB12

VSS[171]

BB16

VSS[172]

BB20

VSS[173]

BB24

VSS[174]

BB30

VSS[175]

BB34

VSS[176]

BB38

VSS[177]

BB42

VSS[178]

BB49

VSS[179]

BB5

VSS[180]

BC10

VSS[181]

BC14

VSS[182]

BC18

VSS[183]

BC2

VSS[184]

BC22

VSS[185]

BC32

VSS[186]

BC36

VSS[187]

BC40

VSS[188]

BC44

VSS[189]

BC52

VSS[190]

BH9

VSS[191]

BD48

VSS[192]

BD49

VSS[193]

BD5

VSS[194]

BE12

VSS[195]

BE16

VSS[196]

BE20

VSS[197]

BE24

VSS[198]

BE30

VSS[199]

BE34

VSS[200]

BE38

VSS[201]

BE42

VSS[202]

BE46

VSS[203]

BE48

VSS[204]

BE50

VSS[205]

BE6

VSS[206]

BE8

VSS[207]

BF3

VSS[208]

BF49

VSS[209]

BF51

VSS[210]

BG18

VSS[211]

BG24

VSS[212]

BG4

VSS[213]

BG50

VSS[214]

BH11

VSS[215]

BH15

VSS[216]

BH19

VSS[217]

BH23

VSS[218]

BH31

VSS[219]

BH35

VSS[220]

BH39

VSS[221]

BH43

VSS[222]

BH47

VSS[223]

BH7

VSS[224]

C12

VSS[225]

C50

VSS[226]

D51

VSS[227]

E12

VSS[228]

E16

VSS[229]

E20

VSS[230]

E24

VSS[231]

E30

VSS[232]

E34

VSS[233]

E38

VSS[234]

E42

VSS[235]

E46

VSS[236]

E48

VSS[237]

E6

VSS[238]

E8

VSS[239]

F49

VSS[240]

F5

VSS[241]

G10

VSS[242]

G14

VSS[243]

G18

VSS[244]

G2

VSS[245]

G22

VSS[246]

G32

VSS[247]

G36

VSS[248]

G40

VSS[249]

G44

VSS[250]

G52

VSS[251]

AF39

VSS[252]

H16

VSS[253]

H20

VSS[254]

H30

VSS[255]

H34

VSS[256]

H38

VSS[257]

H42

VSS[258]

IBEXPEAK-M_ FCBGA1071~D

REV1.0

5

VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[326] VSS[327] VSS[328] VSS[329] VSS[330] VSS[331] VSS[332] VSS[333] VSS[334] VSS[335] VSS[336] VSS[337] VSS[338] VSS[339] VSS[340] VSS[341] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352] VSS[353] VSS[354] VSS[355] VSS[356] VSS[366]

H49 H5 J24 K11 K43 K47 K7 L14 L18 L2 L22 L32 L36 L40 L52 M12 M16 M20 N38 M34 M38 M42 M46 M49 M5 M8 N24 P11 AD15 P22 P30 P32 P34 P42 P45 P47 R2 R52 T12 T41 T46 T49 T5 T8 U30 U31 U32 U34 P38 V11 P16 V19 V20 V22 V30 V31 V32 V34 V35 V38 V43 V45 V46 V47 V49 V5 V7 V8 W2 W52 Y11 Y12 Y15 Y19 Y23 Y28 Y30 Y31 Y32 Y38 Y43 Y46 P49 Y5 Y6 Y8 P24 T43 AD51 AT8 AD47 Y47 AT12 AM6 AT13 AM5 AK45 AK39 AV14

4

U47H

AB16

VSS[0]

AA19

VSS[1]

AA20

VSS[2]

AA22

VSS[3]

AM19

VSS[4]

AA24

VSS[5]

AA26

VSS[6]

AA28

VSS[7]

AA30

VSS[8]

AA31

VSS[9]

AA32

VSS[10]

AB11

VSS[11]

AB15

VSS[12]

AB23

VSS[13]

AB30

VSS[14]

AB31

VSS[15]

AB32

VSS[16]

AB39

VSS[17]

AB43

VSS[18]

AB47

VSS[19]

AB5

VSS[20]

AB8

VSS[21]

AC2

VSS[22]

AC52

VSS[23]

AD11

VSS[24]

AD12

VSS[25]

AD16

VSS[26]

AD23

VSS[27]

AD30

VSS[28]

AD31

VSS[29]

AD32

VSS[30]

AD34

VSS[31]

AU22

VSS[32]

AD42

VSS[33]

AD46

VSS[34]

AD49

VSS[35]

AD7

VSS[36]

AE2

VSS[37]

AE4

VSS[38]

AF12

VSS[39]

Y13

VSS[40]

AH49

VSS[41]

AU4

VSS[42]

AF35

VSS[43]

AP13

VSS[44]

AN34

VSS[45]

AF45

VSS[46]

AF46

VSS[47]

AF49

VSS[48]

AF5

VSS[49]

AF8

VSS[50]

AG2

VSS[51]

AG52

VSS[52]

AH11

VSS[53]

AH15

VSS[54]

AH16

VSS[55]

AH24

VSS[56]

AH32

VSS[57]

AV18

VSS[58]

AH43

VSS[59]

AH47

VSS[60]

AH7

VSS[61]

AJ19

VSS[62]

AJ2

VSS[63]

AJ20

VSS[64]

AJ22

VSS[65]

AJ23

VSS[66]

AJ26

VSS[67]

AJ28

VSS[68]

AJ32

VSS[69]

AJ34

VSS[70]

AT5

VSS[71]

AJ4

VSS[72]

AK12

VSS[73]

AM41

VSS[74]

AN19

VSS[75]

AK26

VSS[76]

AK22

VSS[77]

AK23

VSS[78]

AK28

VSS[79]

IBEXPEAK-M_ FCBGA1071~D

4

3

AK30

VSS[80]

AK31

VSS[81]

AK32

VSS[82]

AK34

VSS[83]

AK35

VSS[84]

AK38

VSS[85]

AK43

VSS[86]

AK46

VSS[87]

AK49

VSS[88]

AK5

VSS[89]

AK8

VSS[90]

AL2

VSS[91]

AL52

VSS[92]

AM11

VSS[93]

BB44

VSS[94]

AD24

VSS[95]

AM20

VSS[96]

AM22

VSS[97]

AM24

VSS[98]

AM26

VSS[99]

AM28

VSS[100]

BA42

VSS[101]

AM30

VSS[102]

AM31

VSS[103]

AM32

VSS[104]

AM34

VSS[105]

AM35

VSS[106]

AM38

VSS[107]

AM39

VSS[108]

AM42

VSS[109]

AU20

VSS[110]

AM46

VSS[111]

AV22

VSS[112]

AM49

VSS[113]

AM7

VSS[114]

AA50

VSS[115]

BB10

VSS[116]

AN32

VSS[117]

AN50

VSS[118]

AN52

VSS[119]

AP12

VSS[120]

AP42

VSS[121]

AP46

VSS[122]

AP49

VSS[123]

AP5

VSS[124]

AP8

VSS[125]

AR2

VSS[126]

AR52

VSS[127]

AT11

VSS[128]

BA12

VSS[129]

AH48

VSS[130]

AT32

VSS[131]

AT36

VSS[132]

AT41

VSS[133]

AT47

VSS[134]

AT7

VSS[135]

AV12

VSS[136]

AV16

VSS[137]

AV20

VSS[138]

AV24

VSS[139]

AV30

VSS[140]

AV34

VSS[141]

AV38

VSS[142]

AV42

VSS[143]

AV46

VSS[144]

AV49

VSS[145]

AV5

VSS[146]

AV8

VSS[147]

AW14

VSS[148]

AW18

VSS[149]

AW2

VSS[150]

BF9

VSS[151]

AW32

VSS[152]

AW36

VSS[153]

AW40

VSS[154]

AW52

VSS[155]

AY11

VSS[156]

AY43

VSS[157]

REV1.0

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

VSS[158]

AY47

Compal Secret Data

2009/09/ 21 2010/09/ 21

3

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PCH (9/9) VSS

NAT02 M/B LA-5154P Schematic

1

1.0

23 49Thursday, November 26, 2 009

1

A

B

C

D

E

W=60mils

1U_0603_10V6K~D

R236

LAN_CABDT<20>

LAN_CKTAL1

LAN_CKTAL2

2

1

V_DAC LAN_MDIN3 LAN_MDIP3

V_DAC LAN_MDIN2 LAN_MDIP2

V_DAC LAN_MDIN1 LAN_MDIP1

V_DAC LAN_MDIN0 LAN_MDIP0

12

2

G

12

C319

C319 33P_0402_50V8J~D

33P_0402_50V8J~D

B+_BIAS

470K_0402_5%

1 1

PCIE_IRX_GLANTX_P6<16>

PCIE_IRX_GLANTX_N6<16>

PCIE_ITX_C_GLANRX_P6<16>

PCIE_ITX_C_GLANRX_N6<16>

2 2

+3VS

LAN_LOPWEN<20>

2

25MHZ_20P_1BX25000CK1A

C318

C318 33P_0402_50V8J~D

33P_0402_50V8J~D

1

3 3

C320 0.01U_0402_16V7K ~DC320 0.01U_0402_16V7K~D

1 2

C321 0.01U_0402_16V7K ~DC321 0.01U_0402_16V7K~D

1 2

C322 0.01U_0402_16V7K~DC322 0.01U_0402_16V7K~D

1 2

C324 0.01U_0402_16V7K ~DC324 0.01U_0402_16V7K~D

1 2

470K_0402_5%

EN_WOL#<31>

C304 0.1U_0402_16V7K~DC304 0.1U_0402_16V7K~D

C305 0.1U_0402_16V7K~DC305 0.1U_0402_16V7K~D

CLK_PCIE_GLAN<16> CLK_PCIE_GLAN#<16>

GLAN_CLKREQ#<16>

PLT_RST#<6,19,27,28,30,31>

ICH_PCIE_WAKE#<17,27,28,31>

R240 1K_0402_5%~DR240 1K_0402_5%~D

1 2

R241 0_0402_5%~D@R241 0_0402_5%~D@

1 2

R242 15K_0402_5%R242 15K_0402_5%

1 2

Y3

1 2

+3VALW

1

C284

2

EN_WOL

12

1.5M_0402_5%~D

13

D

S

1.5M_0402_5%~D

Q4

PMF3800SN_SC70-3

PCIE_IRX_C_GLANTX_P6

PCIE_IRX_C_GLANTX_N6

PCIE_ITX_C_GLANRX_P6

PCIE_ITX_C_GLANRX_N6

R239 2.49K_0402_1%R239 2.49K_0402_1%

1 2

R1033 0_0402_5%~D

1 2

@

TS1

1

TCT1

MCT1

2

TD1+

MX1+

3

TD1-

MX1-

4

TCT2

MCT2

5

TD2+

MX2+

TD2-6MX2-

7

TCT3

MCT3

8

TD3+

MX3+

9

TD3-

MX3-

10

TCT4

MCT4

11

TD4+

MX4+

12

TD4-

MX4-

BOTH_GST5009-LF

R1142

24 23 22

21 20 19

18 17 16

15 14 13

6

2 1

ISOLATEB

LAN_CKTAL1 LAN_CKTAL2

FBMA-L11-322513-201LMA40T_1210

D

S

45

Q3

G

SI3456BDV-T1-E3_TSOP6~D

3

1

C958

C958 2200P_0402_50V7K~D

2200P_0402_50V7K~D

2

20

21

15

16

17 18

25

27

46

26 28

41 42

23 24

14 31 47

22

RJ45_TX3RJ45_TX3+

RJ45_TX2RJ45_TX2+

RJ45_RX1RJ45_RX1+

RJ45_TX0RJ45_TX0+

R0.3 Modify

L10

1 2

U9

HSOP

HSON

HSIP

HSIN

REFCLK_P REFCLK_N

CLKREQB

PERSTB

RSET

LANWAKEB ISOLATEB

CKTAL1 CKTAL2

GPO NC

7

GND GND GND GND

EGND

RTL8111DL-GR_LQFP48_7X7

1

2

RTL8111DL

RP1

45 36 27 18

75_1206_8P4R_5%

W=60mils

C285

@

22U_1206_6.3V6M~D

2

C323

C323 1000P_1206_2KV7K

1000P_1206_2KV7K

1

22U_1206_6.3V6M~D

1

2

+LAN_IO

C286

1

2

LED3/EEDO

LED2/EEDI/AUX

LED1/EESK

MDIP0 MDIN0 MDIP1 MDIN1 MDIP2 MDIN2 MDIP3 MDIN3

SROUT12

EVDD12 DVDD12 DVDD12 DVDD12 AVDD12

AVDD12

VDDSR VDDSR

VDD33 VDD33

AVDD33 AVDD33

0.1U_0402_10V6K~D

EECS

LED0

FB12

ENSR

C287

3.6K_0402_5%

LAN_LED3

33

LAN_LED2

34

LAN_LED1

35 32

LAN_LED0

38

LAN_MDIP0

2

LAN_MDIN0

3

LAN_MDIP1

5

LAN_MDIN1

6

LAN_MDIP2

8

LAN_MDIN2

9

LAN_MDIP3

11

LAN_MDIN3

12

4

48

19 30 36 13 10

39

44 45

29 37

1 40 43

+LAN_IO

12

R947

+LAN_DVDD12

W=60mils

W=40mils

+LAN_IO

LAN_LED2

CH751H-40PT_SOD323-2~D

LAN_LED3

CH751H-40PT_SOD323-2~D

W=60mils

L11

4.7UH_1008HC-472EJFS-A_5%_1008

1 2

0.1U_0402_10V6K~D

C306

1

2

These components close to U9: Pin 48

( Should be place within 200 mils )

W=30mils W=30mils

C310 1U_ 0603_10V6K~DC310 1U_0603_10V6K~D

C311 1U_ 0603_10V6K~DC311 1U_0603_10V6K~D

1 2

R884

These caps close to U9: Pin 19

+LAN_DVDD12

C293

0.1U_0402_10V6K~D

C293

C296

0.1U_0402_10V6K~D

C296

0.1U_0402_10V6K~D

C295

0.1U_0402_10V6K~D

C295

0.1U_0402_10V6K~D

1

2

0.1U_0402_10V6K~D

C294

0.1U_0402_10V6K~D

C294

0.1U_0402_10V6K~D

1

2

These caps close to U9: Pin 10, 13, 30, 36, 39

These caps close to U9: Pin 44.45

( Should be place within 200 mils )

C308

22U_1206_6.3V6M~D

C308

22U_1206_6.3V6M~D

1

2

These caps close to U9: Pin 1.29, 37, 40

C289

0.1U_0402_10V6K~D

C289

0.1U_0402_10V6K~D

C288

0.1U_0402_10V6K~D

C288

0.1U_0402_10V6K~D

1

2

D4

21

D5

21

LAN_LED1

LAN_LED3

CH751H-40PT_SOD323-2~D

+LAN_VDD

1

C307

C307 22U_1206_6.3V6M~D

22U_1206_6.3V6M~D

2

12

+LAN_VDD

0_0603_5%~D

+LAN_DVDD12

R235

C292

0.1U_0402_10V6K~D

C292

0.1U_0402_10V6K~D 0_0603_5%~D

0_0603_5%~D

1

2

R942 0_0805_5%~DR942 0_0805_5%~D

1

2

12

C309

0.1U_0402_10V6K~D

+LAN_IO

C291

0.1U_0402_10V6K~D

C291

0.1U_0402_10V6K~D

C290

0.1U_0402_10V6K~D

C290

0.1U_0402_10V6K~D

1

2

D6

LED1_LED3LED2_LED3

CH751H-40PT_SOD323-2~D

21

D7

21

12

+LAN_IO

+LAN_VDD

These caps close to U9: Pin 4

+LAN_DVDD12

1

2

R246

R245

2

1

+LAN_IO

C302

@C302

@

0.1U_0402_10V6K~D

220_0402_5%~D

LAN_LED0 LAN_ACTIVITY#

1 2

R244

R244 220_0402_5%~D

220_0402_5%~D

LED1_LED3 LINK_100_1000#

1 2

+LAN_IO

220_0402_5%~D

LED2_LED3 LINK_10_1000#

1 2

12/11 reserve for EMI as Dell Tony request.

LAN_MDIN3

LAN_MDIP3

LAN_MDIN1

LAN_MDIN2

LAN_MDIP2

LAN_MDIP1

LAN_MDIN0

LAN_MDIP0

C873 6.8PF_0402_50V9~ DC8 73 6.8PF _0402_50V9~D

C874 6.8PF_0402_50V9~ DC8 74 6.8PF _0402_50V9~D

C875 6.8PF_0402_50V9~ DC8 75 6.8PF _0402_50V9~D

C876 6.8PF_0402_50V9~DC876 6.8PF_0402_50V9~D

C877 6.8PF_0402_50V9~DC877 6.8PF_0402_50V9~D

C878 6.8PF_0402_50V9~DC878 6.8PF_0402_50V9~D

C879 6.8PF_0402_50V9~ DC8 79 6.8PF _0402_50V9~D

C880 6.8PF_0402_50V9~ DC8 80 6.8PF _0402_50V9~D

C303

@C303

@

0.01U_0402_16V7K~D

RJ45_TX3-

RJ45_TX3+

RJ45_RX1-

RJ45_TX2-

RJ45_TX2+

RJ45_RX1+

RJ45_TX0-

RJ45_TX0+

1 2

LINK OK

JRJ45

13

Yellow LED-

12

Yellow LED+

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

11

Orange LED-

10

Yellow LED+

9

Green LED-

FOX_JM3611A-R4953B-7F

CONN@

GND

14

15

4 4

A

LEDS1-0

LED0

LED1

LED2

LED3

0 0 0 1 1 0 1 1

Tx / Rx

LINK100

LINK10

LINK1000

Tx / Rx

LINK10 /100 / 1000

LINK10 / 100

LINK1000

B

Tx

LINK

Rx

FULL

LINK10 / ACT

LINK100 / ACT

FULL

LINK1000 / ACT

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009/09/21 2010/09/21

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Gigabit LAN_RTL8111DL

NAT02 M/B LA-5154P Schematic

E

24 49Thursday, November 26, 2009

1.0

A

R0.3 Modify

R1217 20K_0402_ 1%~DR1217 20K_0402 _1%~D

1 2

+3VS

EC_SPK_HP_MUTE#<31>

1 1

EC_SUB_MUTE#<31>

EA_EC_SPK_MUTE#

HP_JD

EA_EC_SUB_MUTE#

2 2

HP_JD

3 3

MIC_JD

2N7002DW-7-F_SOT363-6~D

4 4

+3VS

HP1_JD

HP2_JD

R1220

10K_0402_5%~D

HP_JD

2

G

SENSE_B

+3VS +3VS

100K_0402_5%~D

12

R978

SENSE_A

+3VS

100K_0402_5%~D

12

HP1_JD

EAPD#

EC_SPK_HP_MUTE#

1 2

R1218 10K_0402_5%~DR1218 10K_0402_5%~D

EAPD#

EC_SUB_MUTE#

1 2

R1219 10K_ 0402_5%~DR1219 10K_0402_5%~D

+3VS

C1117

1 2

0.1U_0402_10V6K~D

5

U58

1

P

IN1

4

O

2

IN2

G

74AHC1G08GW_SOT353-5~D

3

+3VS

C1118

1 2

0.1U_0402_10V6K~D

5

U59

1

P

IN1

4

O

2

IN2

G

74AHC1G08GW_SOT353-5~D

3

+3VS

C1075

0.1U_0402_10V6K~D

1 2

5

U53

1

P

INB

4

Y

2

INA

G

TC7SZ02FU_SSOP5

3

12

EA_EC_SPK_MUTE#

HP_JD#

13

D

Q69

Q69 PMF3800SN_SC70-3

PMF3800SN_SC70-3

S

20K_0402_1%~D

39.2K_0402_1%

12

R546

R547

3

61

2

Q42A

R971

2

G

A

Q42B

4

2N7002DW-7-F_SOT363-6~D

39.2K_0402_1%

1

12

R544

2

13

D

Q43

Q43 PMF3800SN_SC70-3

PMF3800SN_SC70-3

S

1

2

1

2

SPK_AMP_MUTE# <26>

DMIC_CLK<30>

SUB_AMP_MUTE# <26>

HP_JD

1

IN1

2

IN2

R545

5.1K_0402_1%~D

1 2

1000P_0402_50V7K~D

1

C866

2

5

+AVDD_AUDIO

R543

5.1K_0402_1%~D

1 2

1000P_0402_50V7K~D

C865

B

+3VS

C1086

1 2

0.1U_0402_16V4Z~D

5

U56

P

IN1

EA_EC_SPK_MUTE#

4

O

IN2

G

74AHC1G08GW_SOT353-5~D

3

+3VS

C1087

1 2

5

U57

0.1U_0402_16V4Z~D

P

IN1

EA_EC_SUB_MUTE#

4

O

IN2

G

74AHC1G08GW_SOT353-5~D

3

HDA_BITCLK_AUDIO<15>

HDA_SDOUT_AUDIO<15>

HDA_SYNC_AUDIO<15>

HDA_RST_AUDIO#<15>

DMIC0<30>

+3VS+3VS

C1119

1 2

0.1U_0402_10V6K~D

5

U60

P

HP_AMP_MUTE#

4

O

G

74AHC1G08GW_SOT353-5~D

3

+AVDD_AUDIO

100K_0402_5%~D

12

R979

HP2_JD

BEEP#<31> PC_BEEP <26>

PCH_SPKR<15>

B

HDA_SDIN0<15>

1 2

R1240 0_0402_5%~DR1240 0_0402_5%~D

1 2

R1241 0_0402_5%~DR1241 0_0402_5%~D

2.2U_0805_10V7K~D

HP2_CD_R

HP2_CD_L

2.2U_0805_10V7K~D

R1.0 Modify

0.1U_0402_16V4Z~D

C

R247

0_0603_5%~D

1 2

R249 33_0402_5%~DR249 33_0402_5%~D

100P_0402_50V8J~D

@

C341

1

2

C342

2

Int. 60k pull up.

Reserved for TEST

GND AGND

C354

HP2_CD_L1

C355

C945

1 2

C946

BEEP_C#

SB_SPKR_C

499K_0402_1%~D

1 2

499K_0402_1%~D

C

+DVDD_AUDIO+3VS +5VS+AVDD_AUDIO

12

1

2

HDA_SDIN0_R

SENSE_A SENSE_B

PC_BEEP

EAPD#

R268 0_0805_5%~DR268 0_0805_5%~D

1 2

R269 0_0805_5%~D@R269 0_0805_5%~D@

1 2

R270 0_0805_5%~D@R270 0_0805_5%~D@

1 2

R1221

2K_0402_1%~D

1 2

R1222

2K_0402_1%~D

R264

R266

1U_0402_6.3V6K~D

C326

0.1U_0402_10V6K~D

C326

0.1U_0402_10V6K~D

1

2

75mA

U11

6

BITCLK

8

SDI_CODEC

5

SDO

10

SYNC

11

RESET#

2

VOL_UP/DMIC_CLK/GPIO1

4

VOL_DN/DMIC_0/GPIO2

30

DMIC1/GPIO5

13

SENSE_A

34

SENSE_B

32

SENSE_C

12

PCBEEP

47

EAPD/SPDIF IN/GPIO0

18

PORTI_L

19

PORTI_C

20

PORTI_R

7

DVSS

26

AVSS1

42

AVSS2

92HD73C1X5PRGXC1X8_QFP48_7X7

C1120 270P_0402_50V 7K~DC1120 270P_0402_50V7K~D

1 2

HP2_CD_R2HP2_CD_R1

HP2_CD_L2

C1121 270P_0402_50V 7K~DC1121 270P_0402_50V7K~D

1 2

C358 1U_0603_10V 4Z~DC358 1U_0603_10V4Z~D

1 2

PC_BEEP

R267

R267 10K_0402_5%~D@

10K_0402_5%~D@

1 2

D

+3VS

C331

0.1U_0402_10V6K~D

C331

0.1U_0402_10V6K~D

C330

1

2

3

DVDD_IO

9

DVDD_CORE1DVDD_CORE

C332

10U_0603_6.3V6M~D

C332

10U_0603_6.3V6M~D

1

2

38

AVDD125AVDD2

VREFOUT-A

VREFOUT-B

VREFOUT-C

VREFOUT-E

SPDIF OUT0

SPDIF OUT1/GPIO3

U12

14

SHDNR#

18

SHDNL#

15

INR

13

INL

1

C1P

3

C1N

D

+AVDD_AUDIO

10U_0603_6.3V6M~D

C327

0.1U_0402_10V6K~D

C327

0.1U_0402_10V6K~D

C333

1U_0402_6.3V6K~D

C333

1U_0402_6.3V6K~D

1

2

1

2

132mA

HP1_CD_L

39

PORTA_L

PORTA_R

PORTB_L

PORTB_R

PORTC_L

PORTC_R

PORTD_L

PORTD_R

PORTE_L PORTE_R

PORTF_L PORTF_R

PORTG_L

PORTG_R

PORTH_L

PORTH_R

VREFFILT

CAP2

C360

1U_0603_10V4Z~D

C360

1U_0603_10V4Z~D

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HP1_CD_R

41 37

21 22 28

23 24 29

SPK_CD_L

35

SPK_CD_R

36

MIC_CD_L

14

MIC_CD_R

15 31

HP2_CD_L

16

HP2_CD_R

17

43 44

45 46

R1214 10K_0402_5%~DR1214 10K_0402_5%~D

D53

D53 CH751H-40PT_SOD323-2~D

CH751H-40PT_SOD323-2~D

48 40

1 2

R1163 0_0402_5%~D

27 33

1

C347

2

+3VS

2

1

10

19

SVDD

PVDD

PGND

PVss

SVss

SGND

2

5

7

17

1

2

Issued Date

Int. Speaker and Sub woofer

2 1

@

C351

C351 1U_0603_10V4Z~D

1U_0603_10V4Z~D

OUTR

OUTL

NC-4

NC-6

NC-8

NC-12

NC-16

NC-20

MAX4411ETP+T_TQFN20_4X4

E

R248

12

0_0603_5%~D

C334

1

2

0_0603_5%~D

C335

1U_0402_6.3V6K~D

C335

1U_0402_6.3V6K~D

C328

0.1U_0402_10V6K~D

C328

0.1U_0402_10V6K~D

1

2

C336

2.2U_0805_10V7K~D

HP1_CD_R

HP1_CD_L

HP1_CD_R1

HP1_CD_L1

C337

2.2U_0805_10V7K~D

R1.0 Modify

SPK_CD_L <26> SPK_CD_R <26>

R251

+MIC1_VREFO

2.2U_0603_10V7K~D

1 2

2.2U_0603_10V7K~D

D32

1

PACDN042Y3R_SOT23-3~D@

68_0603_1%~D

1 2

68_0603_1%~D

D33

1

PACDN042Y3R_SOT23-3~D@

Deciphered Date

R251 68_0603_1%~D

68_0603_1%~D

1 2

R252

R252 68_0603_1%~D

68_0603_1%~D

C349

MIC_CD_L1

MIC_CD_R1

C350

3

2

R261

R262

3

2

+MIC1_VREFO

+3VS

1 2

1

C348

2

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

HP2_AMP_R

11

HP2_AMP_LHP_AMP_MUTE#

9

21

PAD

4

6

8

12

16

20

2009/09/21 2010/09/21

E

Front

HP1_AMP_L HP1_AMP_L1_JKHP1_AMP_L1

HP1_AMP_R

ACIN <17,31,40,41>

+MIC1_VREFO W=10 mil

Rear or MIC

MIC_CD_R

Center

HP2_AMP_L HP2_AMP_L1_JKHP2_AMP_L1

HP2_AMP_R

Compal Secret Data

F

U10

14

SHDNR#

18

L14

L15

SHDNL#

15

INR

13

INL

1

C1P

3

C1N

C339

12

1U_0603_10V4Z~D

HP1_JD

C1107

C1107 270P_0402_50V7K~D

R1212

2K_0402_1%~D

1 2

R1213

2K_0402_1%~D

270P_0402_50V7K~D

1 2

HP1_CD_R2

HP1_CD_L2

C1108

C1108 270P_0402_50V7K~D

270P_0402_50V7K~D

C338 1U_0603_10V 4Z~DC338 1U_0603_10V4Z~D

1 2

BLM18BD601SN1D_0603~D

1 2

HP1_AMP_R1 HP1_AMP_ R1_JK

1 2

BLM18BD601SN1D_0603~D

Place close to Jack

D31

1

PACDN042Y3R_SOT23-3~D@

R256

4.7K_0402_5%~D

12

BLM18BD601SN1D_0603~D

HP1_AMP_L1_JK

3

HP1_AMP_R1_JK

2

C345 1000P _0402_50V7K~DC345 1000P_0402_50V7K~D

12

R257

4.7K_0402_5%~D

BLM18BD601SN1D_0603~D

1 2

R0.3 Modify

1 2

L16

MIC_CD_L1_JKMIC_CD_L

MIC_CD_R1_JK

L17

Place close to Jack

MIC_CD_L1_JK

MIC_CD_R1_JK

L19

BLM18BD601SN1D_0603~D

HP2_AMP_R1 HP2_AMP_R1_JK

1 2

L18

BLM18BD601SN1D_0603~D

HP2_JD

Place close to Jack

R0.3 Modify

HP2_AMP_L1_JK

HP2_AMP_R1_JK

F

G

+3VS

2

C325

C325 1U_0603_10V4Z~D

1U_0603_10V4Z~D

1

10

19

HP1_AMP_R

11

OUTR

SVDD

PVDD

OUTL

PAD

NC-4

NC-6

NC-8

NC-12

NC-16

NC-20

PGND

PVss

SVss

SGND

MAX4411ETP+T_TQFN20_4X4

2

5

7

17

1226 Modify

C343

1000P_0402_50V7K~D

C343

1000P_0402_50V7K~D

C344

1000P_0402_50V7K~D

C344

1000P_0402_50V7K~D

1

2

MIC_JD

Title

Size Document Number Rev

Custom

Date: Sheet of

G

1226 Modify

100P_0402_50V8J~D

C352

100P_0402_50V8J~D

C352

100P_0402_50V8J~D

1

2

1226 Modify

C357

1000P_0402_50V7K~D

C357

1000P_0402_50V7K~D

C356

1000P_0402_50V7K~D

C356

1000P_0402_50V7K~D

1

2

Compal Electronics, Inc.

HD Audio_IDT92HD73C

NAT02 M/B LA-5154P Schematic

9

21

4

6

8

12

16

20

C353

HP1_AMP_LHP_AMP_MUTE#

JHP1

1 2 6 3

4

5

FOX_JA6333L-B5S4-7F

CONN@

JMIC1

1 2 6 3

4

5

FOX_JA6333L-B5S4-7F

CONN@

JHP2

1 2 6 3

4

5

FOX_JA6333L-B5S4-7F

CONN@

H

SHLD1

SHLD1 SHLD2

SHLD2

NPTH1

NPTH1 NPTH2

NPTH2

25 49Thursday, November 26, 2009

H

SHLD1

SHLD1 SHLD2

SHLD2

NPTH1

NPTH1 NPTH2

NPTH2

SHLD1

SHLD1 SHLD2

SHLD2

NPTH1

NPTH1 NPTH2

NPTH2

7 8 9 10

1.0

5

R0.3 Modify

D D

SPK_CD_L<25>

PC_BEEP<25>

SPK_CD_R<25>

PC_BEEP<25>

R0.3 Modify

1 2

C911

1U_0603_10V6K~D

PC_BEEP

1 2

C908 0.1U_0402_10V6K~DC908 0.1U_0402_10V6K~D

SPK_CD_R SPK_CD_R4

1 2

C915

PC_BEEP PC_BEEP_2

1 2

C912 0.1U_0402_10V6K~DC912 0.1U_0402_10V6K~D

B+

SPK_CD_L1

PC_BEEP_1

1U_0603_10V6K~D

19V

1A/40mil

2

C901

C901 22U_1210_25V6K~D

22U_1210_25V6K~D

1

1 2

16.5K_0402_1%

1 2

182K_0402_1%

1 2

16.5K_0402_1%

1 2

182K_0402_1%

R903

R901

R908

R906

2

C902

C902 22U_1210_25V6K~D

22U_1210_25V6K~D

1

SPK_CD_L2

1 2

R904 17.8K_0402_1%R904 17.8K_0402_1%

SPK_CD_R2

C913

2200P_0402_25V7K~D

1 2

R909 17.8K_0402_1%R909 17.8K_0402_1%

C909

2200P_0402_25V7K~D

1 2

High-Pass Filiter,fc=500Hz, Av=1.45V/V

D59

R0.3 add

SPK_AMP_MUTE#<25>

C C

B B

SPK_CD_R<25>

SPK_CD_L<25>

SPK_CD_L

D59

1 2

SDMK0340L-7-F_SOD323-2~D

R1567

1 2

330K_0402_5%

2

1

R0.3 Modify

C1095

SUB_FB_L SUB_FB_L1

1 2

1U_0603_10V6K~D

1 2

C1098 0.47U_0603_10V7K~DC1098 0.47U_0603_10V7K~D

1 2

C1100 0.47U_0603_10V7K~DC1100 0.47U_0603_10V7K~D

SPK_AMP_MUTE_R#

C1553

2.2U_0603_10V6K~D

SUB_CD_R

SUB_CD_L

B+

2

22U_1210_25V6K~D

1

R1195

1 2

10K_0402_1%~D

R1199

9.09K_0402_1%~D

1 2

R1201

9.09K_0402_1%~D

1A/40mil

C1089

For filterless modualation/spread-spectrum mode

High-Pass Filiter,fc=100 Hz, 500Hz, Av=1.45V/V

D60

R1.0 add

A A

SUB_AMP_MUTE#<25>

5

D60

1 2

SDMK0340L-7-F_SOD323-2~D

R1568

1 2

330K_0402_5%

2

C1558

2.2U_0603_10V6K~D

1

SUB_AMP_MUTE_R#

4

2

C903

C903 22U_1210_25V6K~D

22U_1210_25V6K~D

1

1 2

11K_0402_1%

SPK_CD_R3SPK_CD_R1

1 2

0.047U_0402_16V7K~D

1

C904

0.1U_0603_50V4Z~D

2

R900

1 2

11K_0402_1%

C910

1 2

0.022U_0402_25V7K~D

R905

SPK_CD_R2_FBL

C914

1 2

0.022U_0402_25V7K~D

+3VS

For filterless modualation/spread-spectrum mode

Mono Select. Set MONO high for mono mode.

1

C923

C925

2

1U_0603_25V6-K~D

2

C1090

22U_1210_25V6K~D

1

SUB_FB_L2

C1096

SUB_FB_L3

R1197

R1197 20K_0402_1%~D

20K_0402_1%~D

1 2

2

C1101

0.1U_0402_16V7K~D

1

4

1

C905

0.1U_0603_50V4Z~D

2

SPKER_CD_L2_FBL

R902

1 2

182K_0402_1%

SPK_CD_L4SPK_CD_L3SPK_CD_L

R907

1 2

182K_0402_1%

SPK_AMP_MUTE# SPK_AMP_MUTE_R#

R910 0_0402_5%~DR910 0_0402_5%~D

1 2

Internal Regulator Output.

Internal 2V Bias.

1

C924

1

0.1U_0603_50V4Z~D

2

1U_0603_25V6-K~D

C1091

22U_1210_25V6K~D

1 2

11.5K_0402_1%

1 2

6.49K_0402_1%~D

R1200

+3VS

1U_0603_25V6-K~D

1

2

R1194

R1198

SUB_CD_R2SUB_CD_R1SPK_CD_R

C1104

2

1

2

C926

1U_0603_25V6-K~D

2

1

C1097

1 2

0.047U_0402_16V7K~D

1 2

15.8K_0402_1%

U13

27

PVDD1

30

PVDD2

28

PGND2

29

PGND1

5

FB_L

6

IN_L

19

FB_R

18

IN_R

10

SHDN#

11

REGEN

9

MUTE#

20

MODE

4

MONO

16

VS

15

REG

12

COM

21

C1N

22

C1P

13

AGND

14

AGND

MAX9736AETJ+T_TQFN32_7X7

1

C1092

0.1U_0603_50V4Z~D

2

1 2

100K_0402_1%~D

C1099 0.01U_0402_16V7K~DC1099 0.01U_0402_16V7K~D

R1202 0_0402_5%~DR1202 0_0402_5%~D

1 2

Internal Regulator Output.

Internal 2V Bias.

1U_0603_25V6-K~D

1

C1105

2

1

C1093

0.1U_0603_50V4Z~D

2

SUB_FB_L4 AMP_SW+ AMP_SW_JK+

R1196

SUB_IN_L

SUB_FB_L

1 2

SUB_IN_R

SUB_AMP_MUTE# SUB_AMP_MUTE_R#

1U_0603_25V6-K~D

1

C1103

C1106

0.1U_0603_50V4Z~D

2

3

1

OUTL-1

2

OUTL-2

31

OUTL+1

32

OUTL+2

7

NC1

8

NC2

17

NC3

25

OUTR+1

26

OUTR+2

23

OUTR-1

24

OUTR-2

3

BOOT

33

EP

U14

27

PVDD1

30

PVDD2

28

PGND2

29

PGND1

5

FB_L

6

IN_L

19

FB_R

18

IN_R

10

SHDN#

11

REGEN

9

MUTE#

20

MODE

4

MONO

16

VS

15

REG

12

COM

21

C1N

22

C1P

13

AGND

14

AGND

MAX9736AETJ+T_TQFN32_7X7

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPE RTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SE CRET INFORMATION. THIS SHEET MAY NOT B E TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS

DEPARTMENT EX CEPT AS AUTHORIZ ED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INFORMA TION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

L67

L67 BLM18PG181SN1_0603~D

BLM18PG181SN1_0603~D

AMP_SPKL-

1 2

L68

L68 BLM18PG181SN1_0603~D

BLM18PG181SN1_0603~D

1 2

L69

BLM18PG181SN1_0603~D

1 2

L70

L70 BLM18PG181SN1_0603~D

BLM18PG181SN1_0603~D

AMP_SPKR-

1 2

C922

12

0.1U_0805_50V7M~D

OUTL-1 OUTL-2

OUTL+1 OUTL+2

NC1 NC2 NC3

OUTR+1 OUTR+2

OUTR-1 OUTR-2

BOOT

EP

2009/09/21 2010/09/21

AMP_SPK_JK_L-

1

C906

C906 330P_0402_50V7K~D

330P_0402_50V7K~D

2

AMP_SPKL+_LAMP_SPKL+

1

C907

C907 330P_0402_50V7K~D

330P_0402_50V7K~D

2

AMP_SPKR+_R

1

C917

C917 330P_0402_50V7K~D

330P_0402_50V7K~D

2

AMP_SPK_JK_R-

1

C921

C921 330P_0402_50V7K~D

330P_0402_50V7K~D

2

AMP_SW-

1 2

31 32

7 8 17

25 26

23 24

3

33

Compal Secret Data

1 2

BLM18PG181SN1_0603~D

1 2

BLM18PG181SN1_0603~D

AMP_SW+

AMP_SW-

C1102

12

0.1U_0805_50V7M~D

Deciphered Date

2

L85

1 2

22UH_LQH55PN220MR0L_0.85A_20%~D

L86

1 2

22UH_LQH55PN220MR0L_0.85A_20%~D

L87

L88

AMP_SPK_JK_L+

AMP_SPK_JK_R+AMP_SPKR+

PESD24VS2UT_SOT23-3~D

AMP_SW_JK-

1

C1088

C1088 330P_0402_50V7K~D

330P_0402_50V7K~D

2

1

C1094

C1094 330P_0402_50V7K~D

330P_0402_50V7K~D

2

SUB WOOFER amp impedance of JBL is 4 ohm.

2

AMP_SPK_JK_LAMP_SPK_JK_L+ AMP_SPK_JK_RAMP_SPK_JK_R+

D20

@D20

@

1

Speaker amp impedance of JBL is 4 ohm.

Speaker Connector

JSPK1

15 mils trace

2

3

1

MOLEX_53398-0271~D

Title

Size Document Number Rev

Custom

NAT02 M/B LA-5154P Schematic

Date: Sheet of

2

3

1

JWFER1

1

2

3

G1

4

G2

Compal Electronics, Inc.

Sub woofer / Speaker AMP

JSPK1

1

2

3

G5

4

G6

MOLEX_53261-0471

CONN@

D21

@D21

@

PESD24VS2UT_SOT23-3~D

1

5 6

26 49Thursday, November 26, 2009

1.0

A

+3VS

WWAN

1 1

ICH_PCIE_W AKE#<1 7,24,28,31>

WW AN_CLKREQ#<16>

CLK_PCIE_ WAN#<16 > CLK_PCIE_ WAN<16>

PCIE_IRX_W ANTX_N1<16> PCIE_IRX_W ANTX_P1<16>

PCIE_ITX_C_W ANRX_N1<16> PCIE_ITX_C_W ANRX_P1<16>

2 2

EC_TX_P 80_DATA<17,31> EC_RX_P 80_DATA<3 1>

For EC debug pin

C1113

47P_0402_50V8J~D@C1113

47P_0402_50V8J~D

1

@

2

R323 100K_ 0402_5%~DR32 3 1 00K_0402_5%~ D

R287 0_0402_5%~DR287 0_0402_5%~D R286 0_0402_5%~DR286 0_0402_5%~D

C403

0.01U_0402_16V7K~D

C403

0.01U_0402_16V7K~D

1

2

ICH_PCIE_W AKE#

WW AN_CLKREQ#

CLK_PCIE_ WAN# CLK_PCIE_ WAN

PCIE_IRX_W ANTX_N1 PCIE_IRX_W ANTX_P1

PCIE_ITX_C_W ANRX_N1 PCIE_ITX_C_W ANRX_P1

1 2

1 2 1 2

C405

4.7U_0805_10V4Z~D

C405

4.7U_0805_10V4Z~D

C404

.1U_0402_16V7K~D

C404

.1U_0402_16V7K~D

1

2

+3VS

C956

330U_D2E_6.3VM_R25~D+C956

330U_D2E_6.3VM_R25~D

1

+

2

1 3 5 7

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

53

B

+1.5VS

C1114

47P_0402_50V8J~D@C1114

47P_0402_50V8J~D

1

@

2

JWW AN1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

GND1

GND2

TYCO_1775 838-1~D

CONN@

C407

0.01U_0402_16V7K~D

C407

0.01U_0402_16V7K~D

1

2

+1.5VS +3VS

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

54

.1U_0402_16V7K~D

1

2

C409

4.7U_0805_10V4Z~D

C409

4.7U_0805_10V4Z~D

C408

1

2

Don't forget to remove R287 or disble debug port when doing SIM Pre-test and before RTS.

+UIM_PW R

UIM_DATA UIM_CLK UIM_RST

R285 0_0402_5%~DR285 0_0402_5%~D

1 2

WW AN_RADIO_OFF # PLT_RST #

R911 0_0402_5%~DR911 0_0402_5%~D

1 2

R912 0_0402_5%~DR912 0_0402_5%~D

1 2

USBP5_D USBP5_D +

C

UIM_VPP

WW AN_RADIO_OFF # <31 > PLT_RST # <6,19,24,2 8,30,31>

EC_SMB_ CK2 <16,28,3 1> EC_SMB_ DA2 <16,28,3 1>

DLW 21SN121SQ2L_4 P~D

USBP5_D +

USBP5_D -

DLW 21SN121SQ2L_4 P~D

L71

@L7 1

@

2

3

1 2

R913 0_04 02_5%~DR91 3 0_0 402_5%~D

1 2

R914 0_04 02_5%~DR91 4 0_0 402_5%~D

UIM_VPP UIM_DATA

33P_040 2_50V8J~D

1

4

C410

USBP5+ < 19>

USBP5- <19>

D

D41

1

2

3

SRV05-4.T CT_SOT23-6~D

JSIM1

5

GND

6

VPP

7

I/O

8

NC

9

GND

10

GND

MOLEX_4 75531001

CONN@

Link ok

VCC RST

CLK

6

5

4

1 2 3 4

NC

Place as close as JSIM1

R02 Modify

UIM_RST UIM_CLK

C411

C411 33P_040 2_50V8J~D

33P_040 2_50V8J~D

4.7U_080 5_10V4Z~D

+UIM_PW R

C412

E

1

2

1

C413

C413 .1U_0402 _16V7K~D

.1U_0402 _16V7K~D

2

WLAN

+3V_W LAN +1.5VS + 3V_WLAN

JWL AN1

ICH_PCIE_W AKE#<1 7,24,28,31>

COEX2_W LAN_ACTIVE<28,30 >

3 3

4 4

WPAN _ACTIVE< 28>

BT_ACTIVE<30>

A

WLA N_CLKREQ#<16>

CLK_PCIE_ WLAN#<16> CLK_PCIE_ WLAN<16 >

CLK_DEB UG_PORT< 19>

PCIE_IRX_W LANTX_N2<16> PCIE_IRX_W LANTX_P2<16>

PCIE_ITX_C_W LANRX_N2< 16> PCIE_ITX_C_W LANRX_P2<16>

WPAN _ACTIVE

BT_ACTIVE

PLT_RST #< 6,19,24,28,30,31>

D40

2

3

BAT54C-7 -F_SOT23~D

ICH_PCIE_W AKE#

R291 0_0402_5%~DR291 0_0402_5%~D

1 2

COEX1_W LAN_ACTIVE WLA N_CLKREQ#

CLK_PCIE_ WLAN# CLK_PCIE_ WLAN

R918 0_0402_5%~DR918 0_0402_5%~D

1 2

R921 0_0402_5%~DR921 0_0402_5%~D

1 2

PCIE_IRX_W LANTX_N2 PCIE_IRX_W LANTX_P2

PCIE_ITX_C_W LANRX_N2 PCIE_ITX_C_W LANRX_P2

COEX1_W LAN_ACTIVE

1

12

R997

R997 10K_040 2_5%~D

10K_040 2_5%~D

B

JWL AN1

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

GND1

TYCO_1775 838-1~D

CONN@

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

GND2

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R919 0_0402_5%~DR919 0_0402_5%~D

1 2

R920 0_0402_5%~DR920 0_0402_5%~D

1 2

R915 0_0402_5%~DR915 0_0402_5%~D

1 2

R916 0_0402_5%~DR916 0_0402_5%~D

1 2

R917 0_0402_5%~DR917 0_0402_5%~D

1 2

WLA N_RADIO_OFF#

R922 0_0402_5%~DR922 0_0402_5%~D

1 2

R923 0_0402_5%~DR923 0_0402_5%~D

1 2

USBP4_D USBP4_D +

USBP4_D +

USBP4_D -

2009/09/ 21 2010/09/ 21

C

LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

WLA N_RADIO_OFF# <31> PLT_RST # <6,19,24,2 8,30,31>

L72

@L7 2

@

DLW 21SN121SQ2L_4 P~D

2

3

1 2

R924 0_04 02_5%~DR92 4 0_0 402_5%~D

1 2

R925 0_04 02_5%~DR92 5 0_0 402_5%~D

Compal Secret Data

1

4

Deciphered Date

EC_SMB_ CK2 <16,28,3 1> EC_SMB_ DA2 <16,28,3 1>

1

4

LPC_FRA ME# <15 ,31>

LPC_AD[0 ..3] <15,3 1>

USBP4+ < 19>

USBP4- <19>

D

+3V_W LAN

1 2

C415

.1U_0402_16V7K~D

C415

.1U_0402_16V7K~D

4.7U_0805_10V4Z~D

C414

0.01U_0402_16V7K~D

C414

0.01U_0402_16V7K~D

C1115

47P_0402_50V8J~D@C1115

47P_0402_50V8J~D

1

@

2

1

@

2

Title

Size Document Num ber Rev

Date: Sheet of

Mini Card_WLAN/WWAN

Custom

NAT02 M/B LA-5154P Schematic

4.7U_0805_10V4Z~D

1

2

+1.5VS

C1116

47P_0402_50V8J~D@C1116

47P_0402_50V8J~D

0.01U_0402_16V7K~D

1

2

Compal Electronics, Inc.

JP10@ JP10@

C416

C417

C418

0.01U_0402_16V7K~D

C418

0.01U_0402_16V7K~D

1

2

E

+3VS

27 49Thursday, November 26, 2 009

1.0

5

4

3

2

1

+1.5VS

C419

0.047U_0402_16V4Z~D

C419

D D

ICH_PCIE_WAKE#<17,24,27,31>

COEX2_WLAN_ACTIVE<27,30>

WPAN_ACTIVE<27>

WPAN_CLKREQ#<16>

CLK_PCIE_WPAN#<16> CLK_PCIE_WPAN<16>

PCIE_IRX_WPANTX_N3<16> PCIE_IRX_WPANTX_P3<16>

PCIE_ITX_C_WPANRX_ P3<16>

C C

ICH_PCIE_WAKE#

R292 0_0402_5%~DR292 0_0402_5%~D

1 2

R293 0_0402_5%~DR293 0_0402_5%~D

1 2

WPAN_CLKREQ#

CLK_PCIE_WPAN# CLK_PCIE_WPAN

PCIE_IRX_WPANTX_N3 PCIE_IRX_WPANTX_P3

PCIE_ITX_C_WPANRX_ N3 PCIE_ITX_C_WPANRX_ P3

WPAN_ACTIVE_R

WPAN Card

JWPAN1

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

GND1

TYCO_1775838-1~D

GND2

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

+1.5VS

+3VS+3VS

WPAN_RADIO_OFF#

1 2

R1162 0_0402_5%~DR1162 0_0402_5%~D

R294 0_0402_5%~DR294 0_0402_5%~D

1 2

R298 0_0402_5%~DR298 0_0402_5%~D

1 2

USBP3_DUSBP3_D+

USBP3_D-

USBP3_D+

WPAN_RADIO_OFF# <31>

PLT_RST# <6,19,24,27,30,31>

EC_SMB_CK2 <16,27,31> EC_SMB_DA2 <16,27,31>PCIE_ITX_C_WPANRX_ N3<16>

DLW21SN121SQ2L_4P~D

2

3

L26

2

3

@L26

@

1

4

12

R2950_0402_5%~D R2950_0402_5%~D

12

R2960_0402_5%~D R2960_0402_5%~D

0.047U_0402_16V4Z~D

1

2

USBP3- <19>

USBP3+ <19>

+3VS

C420

0.047U_0402_16V4Z~D

C420

0.047U_0402_16V4Z~D

1

2

C421

0.047U_0402_16V4Z~D

C421

0.047U_0402_16V4Z~D

1

2

C423

0.1U_0402_16V4Z~D

C423

0.1U_0402_16V4Z~D

C424

0.1U_0402_16V4Z~D

C424

0.1U_0402_16V4Z~D

C425

4.7U_0603_6.3V6M~D

C425

C422

0.047U_0402_16V4Z~D

C422

0.047U_0402_16V4Z~D

1

2

4.7U_0603_6.3V6M~D

1

2

Express Card Power

+3VS_CARD

Switch

+3VALW

B B

A A

+1.5VS

C433

0.1U_0402_16V4Z~D

C433

0.1U_0402_16V4Z~D

1

2

0.1U_0402_16V4Z~D

1

2

PLT_RST#<6,19,24,27,30,31>

SYSON<31,33,44>

SUSP#<31,33,43,44,45>

+3VS

C432

0.1U_0402_16V4Z~D

C432

0.1U_0402_16V4Z~D

1

C431

2

U16

2

3.3Vin

17

3.3Vin

PLT_RST#

CPPE#

EXPR_CPUSB#

+1.5V_CARD Max. 650mA , Average 500mA +3V_CARD Max. 1300mA, Average 1000mA

AUX_IN12AUX_OUT

6

SYSRST#

20

SHDNZ

1

STBYZ

10

CPPE#

9

CPUSB#

18

RCLKEN

P2231NL E2_QFN20_4X4

3.3Vout

OCZ

PERSTZ

GND

3 15

11

19

PERST#

8

4

NC

5

NC

13

NC

14

NC

16

NC

7

(1A)

(0.5A)

C429

0.1U_0402_16V4Z~D

C429

0.1U_0402_16V4Z~D

1

2

+3VS_CARD_AUX

C434

0.1U_0402_16V4Z~D

C434

0.1U_0402_16V4Z~D

1

2

+1.5VS_CARD

C427

0.1U_0402_16V4Z~D

C427

0.1U_0402_16V4Z~D

1

2

4.7U_0805_10V4Z~D

1

2

C435

4.7U_0805_10V4Z~D

C435

4.7U_0805_10V4Z~D

1

2

C428

4.7U_0805_10V4Z~D

C428

4.7U_0805_10V4Z~D

1

2

PCIE_IRX_EXPTX_N5<16> PCIE_IRX_EXPTX_P5<16>

PCIE_ITX_C_EXPRX_N5<1 6> PCIE_ITX_C_EXPRX_P5<16>

USBP8-<19> USBP8+<19>

EC_SMB_CK2<16,27,31> EC_SMB_DA2<16,27,31>

+1.5VS_CARD

ICH_PCIE_WAKE#<17,24,27,31>

+3VS_CARD_AUX

EXP_CLKREQ#<16>

CLK_PCIE_EXPR#<16> CLK_PCIE_EXPR<16>

+3VS_CARD

EXP_CLKREQ# CPPE# CLK_PCIE_EXPR# CLK_PCIE_EXPR

PCIE_IRX_EXPTX_N5 PCIE_IRX_EXPTX_P5

PCIE_ITX_C_EXPRX_N5 PCIE_ITX_C_EXPRX_P5

USBP8USBP8+ EXPR_CPUSB#

EC_SMB_CK2 EC_SMB_DA2

PERST#

C430

Express Card

4.7U_0805_10V4Z~D

C430

JEXP1

1

GND

2

USB-

3

USB+

4

CPUSB#

5

REV

6

REV

7

SMBCLK

8

SMBDATE

9

+1.5V

10

+1.5V

11

WAKE#

12

+3.3VAUX

13

PERST#

14

+3.3V

15

+3.3V

16

CLKREQ#

17

CPPE#

18

REFCLK-

19

REFCLK+

20

GND

21

PERn0

22

PERp0

23

GND

24

PETn0

25

PETp0

26

GND

27

G1

28

G2

29

G3

30

G4

TAITW_PXPXAE-000LBS2ZZ 4N0_NR

CONN@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/09/21 2010/09/21

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Mini Card_WPAN / Express

NAT02 M/B LA-5154P Schematic

1

28 49Thursday, November 26, 2009

1.0

A

Place close U67 pin 2 & pin3

SATA_ITX_C_DRX_P0 SATA_ITX_C_DRX_N0

SATA_IRX_DTX_P0 SATA_IRX_DTX_N0

1 1

Output Swing Control

SEL2_ [A:B]

0

* *

1

SATA_ITX_C_DRX_P0<15> SATA_ITX_C_DRX_N0<15>

SATA_IRX_DTX_P0<15>

SATA_IRX_DTX_N0<15>

+SATA_PWR

2 2

3 3

SATA_ITX_C_DRX_P1<15> SATA_ITX_C_DRX_N1<15>

SATA_IRX_DTX_P1<15>

SATA_IRX_DTX_N1<15>

+SATA_PWR1

4 4

+SATA_PWR1

SEL0_ [A:B] SEL1_ [A:B]

CU46 0.01U_0402_16V7K~DCU46 0.01U_0402_16V7K~D

CU45 0.01U_0402_16V7K~DCU45 0.01U_0402_16V7K~D RU65 0_0402_5%~DRU65 0_0402_5%~D RU67 0_0402_5%~DRU67 0_0402_5%~D

RU70 0_0402_5%~D@RU70 0_0402_5%~D@ RU68 0_0402_5%~D@RU68 0_0402_5%~D@

RU69 0_0402_5%~DRU69 0_0402_5%~D RU71 0_0402_5%~DRU 71 0_0402_5%~D

RU73 0_0402_5%~DRU73 0_0402_5%~D RU75 0_0402_5%~DRU 75 0_0402_5%~D

RU77 5.1K_0402_1%~DRU77 5.1K_0402_1%~D RU79 5.1K_0402_1%~DRU79 5.1K_0402_1%~D

RU80 470_0402_5%~D@ RU80 470_0402_5%~D@

+SATA_PWR

RU81 0_0402_5%~D@RU81 0_0402_5%~D@

RU82 0_0402_5%~D@ RU82 0_0402_5%~D@

Place close U55 pin 2 & pin3

SATA_ITX_C_DRX_P1 SATA_ITX_C_DRX_N1

SATA_IRX_DTX_P1 SATA_IRX_DTX_N1

C1083 0.01U_0402_16V7 K~DC1 083 0.01U_0402_16V7K~D

C1084 0.01U_0402_16V7 K~DC1 084 0.01U_0402_16V7K~D

R1176 0_0402_5%~DR1176 0_0402_5%~D R1177 0_0402_5%~DR1177 0_0402_5%~D

R1178 0_0402_5%~D@R1178 0_0402_5%~D@ R1179 0_0402_5%~D@R1179 0_0402_5%~D@

R1180 0_0402_5%~DR1180 0_0402_5%~D R1181 0_0402_5%~DR1181 0_0402_5%~D

R1183 0_0402_5%~DR1183 0_0402_5%~D R1185 0_0402_5%~DR1185 0_0402_5%~D

R1187 5.1K_0402_1%~DR1187 5.1K_0402_1%~D R1189 5.1K_0402_1%~DR1189 5.1K_0402_1%~D

R1190 470_0402_5%~D@R 1190 470_0402_5%~D@

R1191 0_0402_5%~D@R1191 0_0402_5%~D@ R1192 0_0402_5%~D@R1192 0_0402_5%~D@

Equalizer Selection

0 0

0 1

*

1 1 1

0

RU57 0_0402_5%~D@RU57 0_0402_5%~D@

1 2

RU59 0_0402_5%~D@RU59 0_0402_5%~D@

1 2

RU63 0_0402_5%~D@RU63 0_0402_5%~D@

1 2

RU62 0_0402_5%~D@RU62 0_0402_5%~D@

1 2

+1.8VS +SATA_PWR

Swing

1x

1.2x

SATA_ITX_C_DRX_P0 SATA_ITX_C_DRX_N0

SATA_IRX_C_DTX_P0

1 2

SATA_IRX_C_DTX_N0

1 2

1 2 1 2

1 2

1 2 1 2

R1168 0_0402_5%~D@ R1168 0_0402_5%~D@

1 2

R1170 0_0402_5%~D@ R1170 0_0402_5%~D@

1 2

R1172 0_0402_5%~D@ R1172 0_0402_5%~D@

1 2

R1174 0_0402_5%~D@ R1174 0_0402_5%~D@

1 2

+1.8VS +SATA_PWR1

SATA_ITX_C_DRX_P1 SATA_ITX_C_DRX_N1

SATA_IRX_C_DTX_P1

1 2

SATA_IRX_C_DTX_N1

1 2

1 2 1 2

1 2

R0.3 depop

1 2 1 2

Compliance Channel

no equalization

[0:2.5dB] @ 1.6 GHz

[2.5:4.5dB] @ 1.6 GHz

[4.5:6.5dB] @ 1.6 GHz

A

JP12@JP12

1 2

@

Output De-emphasis Adjustment

JP11@JP11

1 2

@

SATA_ITX_R_DRX_P0 SATA_ITX_R_DRX_N0

SATA_IRX_R_DTX_P0 SATA_IRX_R_DTX_N0

SEL3_ [A:B]

De-emphasis

0

1

U67

2

AI+

3

AI-

7

BO+

8

BO-

34

SEL0_A

13

SEL0_B

33

SEL1_A

14

SEL1_B

32

SEL2_A

15

SEL2_B

31

SEL3_A

16

SEL3_B

30

EN_A

29

EN_B

19

IREF

11

CLKIN+

12

CLKIN-

PI2EQX3201BZFEX_TQFN36_6X5

R0.3 change to SA00002YQ0 L (S IC PI2EQX3201BLZFEX TQFN 36P)

SATA_ITX_R_DRX_P1 SATA_ITX_R_DRX_N1

SATA_IRX_R_DTX_P1 SATA_IRX_R_DTX_N1

U55

2

AI+

3

AI-

7

BO+

8

BO-

34

SEL0_A

13

SEL0_B

33

SEL1_A

14

SEL1_B

32

SEL2_A

15

SEL2_B

31

SEL3_A

16

SEL3_B

30

EN_A

29

EN_B

19

IREF

11

CLKIN+

12

CLKIN-

PI2EQX3201BZFEX_TQFN36_6X5

R0.3 change to SA00002YQ0 L (S IC PI2EQX3201BLZFEX TQFN 36P)

0dB

-3.5dB

VDD VDD VDD VDD VDD

AVDD

AO+

OUT+

OUT-

SD_A SD_B

GND GND GND GND

AGND

PAD

VDD VDD VDD VDD VDD

AVDD

AO+

AO-

BI-

BI+

OUT+

OUT-

SD_A SD_B

GND GND GND GND

AGND

PAD

1 6 10 23 28 5

27 26

AO-

21

BI-

22

BI+

17 18

36 35

25 20 9 4 24

37

R1169 0_0402_5%~D@ R1169 0_0402_5%~D@ R1171 0_0402_5%~D@ R1171 0_0402_5%~D@

R1173 0_0402_5%~D@ R1173 0_0402_5%~D@ R1175 0_0402_5%~D@ R1175 0_0402_5%~D@

1 6 10 23 28 5

27 26

21 22

17 18

36 35

25 20 9 4 24

37

B

RU58 0_0402_5%~D@RU58 0_0402_5%~D@

1 2

RU60 0_0402_5%~D@RU60 0_0402_5%~D@

1 2

RU61 0_0402_5%~D@RU61 0_0402_5%~D@

1 2

RU64 0_0402_5%~D@RU64 0_0402_5%~D@

1 2

+SATA_PWR

ESATA_ITX_DRX_P0 ESATA_ITX_DRX_N0

ESATA_IRX_DTX_N0 ESATA_IRX_DTX_P0

RU72 0_0402_5%~D@RU72 0_0402_5%~D@ RU74 0_0402_5%~D@RU74 0_0402_5%~D@

RU76 0_0402_5%~D@RU76 0_0402_5%~D@ RU78 0_0402_5%~D@RU78 0_0402_5%~D@

1 2 1 2

+SATA_PWR1

ESATA_ITX_DRX_P1 ESATA_ITX_DRX_N1

ESATA_IRX_DTX_N1

ESATA_IRX_DTX_P1

R1182 0_0402_5%~D@ R1182 0_0402_5%~D@ R1184 0_0402_5%~D@ R1184 0_0402_5%~D@

R1186 0_0402_5%~D@ R1186 0_0402_5%~D@ R1188 0_0402_5%~D@ R1188 0_0402_5%~D@

B

ESATA_ITX_C_DRX_P0 ESATA_ITX_C_DRX_N0

ESATA_IRX_DTX_P0

CU38

10U_1206_16V4Z~D

1

C1076

2

10U_1206_16V4Z~D

ESATA_IRX_DTX_N0

1

CU40

CU39

2

0.1U_0402_16V4Z~D

12

RU66

RU66 470_0402_5%~D

470_0402_5%~D

ESATA_ITX_C_DRX_P1 ESATA_ITX_C_DRX_N1

ESATA_IRX_DTX_P1 ESATA_IRX_DTX_N1

1

C1078

C1077

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D C1082

C1082 4700P_0402_25V7K~D

4700P_0402_25V7K~D

12

R1193

R1193 470_0402_5%~D

470_0402_5%~D

C1085

C1085 4700P_0402_25V7K~D

4700P_0402_25V7K~D

1

CU41

2

0.1U_0402_16V4Z~D

CU44

CU44 4700P_0402_25V7K~D

4700P_0402_25V7K~D

ESATA_ITX_C_DRX_P0

12

CU47

CU47 4700P_0402_25V7K~D

4700P_0402_25V7K~D

ESATA_ITX_C_DRX_N0

12

1

C1079

2

0.1U_0402_16V4Z~D

ESATA_ITX_C_DRX_P1

12

ESATA_ITX_C_DRX_N1

12

Place close U67 pin 21 & pin22

1

2

1 2 1 2

Place close U55 pin 21 & pin22

1

2

1 2 1 2

C

SATA HDD

ESATA_ITX_C_DRX_P1 ESATA_ITX_C_DRX_N1

C437 0.01U_040 2_16V7K~DC437 0.01U_0402_16V7K~D

1 2

C436 0.01U_040 2_16V7K~DC436 0.01U_0402_16V7K~D

1 2

1

CU42

CU43

2

0.1U_0402_16V4Z~D

ESATA_IRX_C_DTX_N1ESATA_IRX_DTX_N1 ESATA_IRX_C_DTX_P1ESATA_IRX_DTX_P1

SATA HDD (On board)

ESATA_ITX_C_DRX_P0 ESATA_ITX_C_DRX_N0

ESATA_IRX_DTX_N0 ESATA_IRX_DTX_P0 ES ATA_IRX_C_DTX_P0

1

C1080

C1081

2

0.1U_0402_16V4Z~D

SATA_IRX_DTX_N4<15> SATA_IRX_DTX_P4<15>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

CU48 0.01U_0402_25V7K~DCU48 0.01U_0402_25V7K~D CU49 0.01U_0402_25V7K~DCU49 0.01U_0402_25V7K~D

12 12

由由由由由由由由

Kink pin

因因因因因因因因將將將將原原原原即即即即即即即即即即即即即即即即即即即即改改改改

尺尺尺尺尺尺尺尺尺尺尺尺由由由由

HDD Conn.(REV.) –FOXCONN–SP01000LC0L layout

SATA ODD CONN

SATA_ITX_C_DRX_P4<15> SATA_ITX_C_DRX_N4<15>

C449 0.01U_040 2_25V7K~DC449 0.01U_0402_25V7K~D C450 0.01U_040 2_25V7K~DC450 0.01U_0402_25V7K~D

2009/09/21 2010/09/21

12 12

Compal Secret Data

ESATA_IRX_C_DTX_N0

kink hole

腳腳腳腳腳腳腳腳腳腳腳腳腳腳腳腳腳腳腳腳腳腳腳腳

SATA_ITX_C_DRX_P4 SATA_ITX_C_DRX_N4

SATA_IRX_C_DTX_N4 SATA_IRX_C_DTX_P4

Deciphered Date

D

MOLEX_47662-2000_22P-T

JSATA1

SP010812230

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

V33

9

V33

10

V33

11

GND

12

GND

13

GND

+5VS

14

V5

15

V5

16

V5

17

GND

18

Reserved

19

GND

20

V12

21

V12

22

V12

MOLEX_47662-2000_NR

CONN@

JSATA2

1

GND

2

RX+

3

RX-

4

GND

5

TX-

6

TX+

7

GND

8

3.3V

9

3.3V

10

3.3V

11

GND

12

GND

13

GND

14

5V

15

5V

16

5V

17

GND

18

Reserved

19

GND

20

12V

21

12V

22

GND1

12V

GND2

TYCO_1770615-3~D

，，，，將將將將將將將將將將將將將將將將將將將將將將將將將將將將，，，，也也也也也也也也也也也也也也也也也也也也

JODD1

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

DP

+5VS

D

9

V5

10

V5

11

MD

12

GND

13

GND

MOLEX_47639-3000_13P

CONN@

E

+5VS

Close to JSATA1.

C446

0.1U_0402_16V7K~D

C446

0.1U_0402_16V7K~D

C445

10U_0805_10V4Z~D

C445

23

GND

24

GND

25

GND

23 24

腳腳腳腳腳腳腳腳腳腳腳腳。。。。

改改改改改改改改

Tyco–SP01000E70L layout

14

G1

15

G2

16

G3

10U_0805_10V4Z~D

1

2

+5VS

Close to JSATA2.

C452

10U_0805_10V4Z~D

C452

10U_0805_10V4Z~D

1

2

+5VS

C438

10U_0805_10V4Z~D

C438

10U_0805_10V4Z~D

1

2

1

2

1

2

C447

0.1U_0402_16V7K~D

C447

0.1U_0402_16V7K~D

1

2

C453

0.1U_0402_16V7K~D

C453

0.1U_0402_16V7K~D

C454

0.1U_0402_16V7K~D

C454

0.1U_0402_16V7K~D

1

2

C439

1U_0603_10V4Z~D

C439

1U_0603_10V4Z~D

1000P_0402_50V7K~D

C440

0.1U_0402_16V4Z~D

C440

0.1U_0402_16V4Z~D

1

2

Close to ODD Co nn

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

ODD/SATA HDD

NAT02 M/B LA-5154P Schematic

E

29 49Thursday, November 26, 2009

C448

1000P_0402_50V7K~D

C448

1000P_0402_50V7K~D

C455

1000P_0402_50V7K~D

C455

1000P_0402_50V7K~D

C441

1.0

Place close U40 pin 2 & pin3

+1.8VS +ESATA_PWR

JP13@JP13

1 2

@

Output Swing Control

SEL2_ [A:B]

0

1

*

SATA_ITX_C_DRX_P5<15> SATA_ITX_C_DRX_N5<15>

SATA_IRX_DTX_P5<15>

SATA_IRX_DTX_N5<15>

+ESATA_PWR

USB_DETECT#

C942 0.01U_0402_16V7K~DC942 0.01U_0402_16V 7K~D

C943 0.01U_0402_16V7K~DC943 0.01U_0402_16V 7K~D R954 0_0402_5%~DR954 0_0402_5%~D R955 0_0402_5%~DR955 0_0402_5%~D

R956 0_0402_5%~D@R956 0_0402_5%~D@ R957 0_0402_5%~D@R957 0_0402_5%~D@

R958 0_0402_5%~D@R958 0_0402_5%~D@ R959 0_0402_5%~D@R959 0_0402_5%~D@

R961 0_0402_5%~DR961 0_0402_5%~D

R963 0_0402_5%~DR963 0_0402_5%~D

R965 10K_0402_1%~DR965 10K _0402_1%~D

1 2

R967 10K_0402_1%~DR967 10K _0402_1%~D

1 2

R968 470_0402_5%~D@ R968 470_0402_5%~D@

+ESATA_PWR

R969 0_0402_5%~D@R969 0_0402_5%~D@

R970 0_0402_5%~D@R970 0_0402_5%~D@

USB_DETECT

13

D

2

G

PMF3800SN_SC70-3

S

SATA_ITX_C_DRX_P5 SATA_ITX_C_DRX_N5

SATA_IRX_C_DTX_P5

1 2

SATA_IRX_C_DTX_N5

1 2

1 2 1 2

USB_DETECT

1 2

1 2 1 2

R0.3 depop

Q63

@

Q63

@

R0.3 depop

SATA_ITX_C_DRX_P5 SATA_ITX_C_DRX_N5

SATA_IRX_DTX_P5 SATA_IRX_DTX_N5

Swing

1x

1.2x

R1164 0_0402_5%~D@ R1164 0_0402_5%~D@

1 2

R1165 0_0402_5%~D@ R1165 0_0402_5%~D@

1 2

R951 0_0402_5%~D@R951 0_0402_5%~D@

1 2

R952 0_0402_5%~D@R952 0_0402_5%~D@

1 2

Output De-emphasis Adjustment

SEL3_ [A:B]

0

*

1

U40

2

AI+

3

AI-

7

BO+

8

BO-

34

SEL0_A

13

SEL0_B

33

SEL1_A

14

SEL1_B

32

SEL2_A

15

SEL2_B

31

SEL3_A

16

SEL3_B

30

EN_A

29

EN_B

19

IREF

11

CLKIN+

12

CLKIN-

PI2EQX3201BZFEX_TQFN36_6X5

SATA_ITX_R_DRX_P5 SATA_ITX_R_DRX_N5

SATA_IRX_R_DTX_P5 SATA_IRX_R_DTX_N5

De-emphasis

0dB

-3.5dB

1

VDD

6

VDD

10

VDD

23

VDD

28

VDD

5

AVDD

27

AO+

26

AO-

21

BI-

22

BI+

17

OUT+

18

OUT-

36

SD_A

35

SD_B

25

GND

20

GND

9

GND

4

GND

24

AGND

37

PAD

+ESATA_PWR

1

2

ESATA_ITX_DRX_P ESATA_ITX_DRX_N

ESATA_IRX_DTX_N ESATA_IRX_DTX_P

R960 0_0402_5%~D@R960 0_0402_5%~D@

1 2

R962 0_0402_5%~D@R962 0_0402_5%~D@

1 2

R964 0_0402_5%~D@R964 0_0402_5%~D@

1 2

R966 0_0402_5%~D@R966 0_0402_5%~D@

1 2

R949 0_0402_5%~D@R949 0_0402_5%~D@

1 2

R950 0_0402_5%~D@R950 0_0402_5%~D@

1 2

R1166 0_0402_5%~D@ R1166 0_0402_5%~D@

1 2

R1167 0_0402_5%~D@ R1167 0_0402_5%~D@

1 2

1

C936

C935

2

10U_0805_10V4Z~D

0.1U_0402_16V4Z~D

12

R953

R953 390_0402_5%

390_0402_5%

R0.3 change to SA00002YQ0 L (S IC PI2EQX3201BLZFEX TQFN 36P)

Equalizer Selection

SEL0_ [A:B] SEL1_ [A:B]

0 0

*

0 1

1 1 1

Compliance Channel

no equalization

[0:2.5dB] @ 1.6 GHz

0

[2.5:4.5dB] @ 1.6 GHz

[4.5:6.5dB] @ 1.6 GHz

ESATA_ITX_C_DRX_P ESATA_ITX_C_DRX_N

ESATA_IRX_DTX_P

Place close U40 pin 21 & pin22

1

C937

2

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D C941

C941 4700P_0402_25V7K~D

4700P_0402_25V7K~D

C944

C944 4700P_0402_25V7K~D

4700P_0402_25V7K~D

ESATA_IRX_DTX_N

1

C938

C939

2

0.1U_0402_16V4Z~D

ESATA_ITX_C_DRX_P

12

ESATA_ITX_C_DRX_N

12

D34

1

CH1

2

Vn

3

CH2

CM1293-04SO_SOT23-6@

C940

0.1U_0402_16V4Z~D

CH4

CH3

Place close JESA1

4

5

Vp

6

PWRSHARE_EN #<31>

+5V_CHGUSB

R301

43.2K_0402_1%~D

R304

49.9K_0402_1%~D

USBP0_D-

+5V_CHGUSB

USBP0_D+

1 2

+5VALW

10U_0805_10V4Z~D

0.1U_0402_16V4Z~D

C462

1

2

R302

R302 75K_0402_1%

75K_0402_1%

1 2

R305

49.9K_0402_1%~D

1 2

USBP0+<19>

USBP0-<19>

USB_CHARGE_D+

USB_CHARGE_D- USBP0_R_D-

USBP0_R_D-

USBP0_R_D+

U17

1

GND

2

IN

3

EN1#

4

EN2#

TPS2062ADR_SO8~D

C463

4

1

L89 WCM2012F2S-900T04_0805@L89 WCM 2012F2S-900T04_0805@ R1571 0_0402_5%~DR1571 0_0402_5%~D

R1572 0_0402_5%~DR1572 0_0402_5%~D

R1.0 modify

+5V_CHGUSB

ESATA_USB_OC#

8

OC1#

7

OUT1

6

OUT2

5

OC2#

U18

1

1D+

2

1D-

3

2D+

4

2D-

5

GND

TS3USB221RSER_QFN10_2x1P5~D

VCC

OE#

10

9

S

8

D+

7

D-

6

S Logic"1" Work from BKT

3

2

1 2

ESATA_IRX_DTX_N

ESATA_IRX_DTX_P

C466

0.1U_0402_16V4Z~D

1 2

+3VALW

PWRSHARE_OE#

USBP0_R_D+

+5V_CHGUSB

1

+

2

C464 4700P_0402_25V7K~DC464 4700P_0402_25V7K~D

C465 4700P_0402_25V7K~DC465 4700P_0402_25V7K~D

USB_DETECT#<32>

ESATA_USB_OC# <19>

12

R303

R303 100K_0402_5%~D

100K_0402_5%~D

C460

C460 150U_D2_6.3VM~D

150U_D2_6.3VM~D

USBP0_DUSBP0_D+

ESATA_ITX_C_DRX_P ESATA_ITX_C_DRX_N

ESATA_IRX_C_DTX_N

12

ESATA_IRX_C_DTX_P

12

PWRSHARE_OE# <31>

S Function

OE#

H

X

L

H

1

C461

0.1U_0402_16V4Z~D

2

1 2 3 4

5 6 7 8

9 10 11

12 13

Disconnect

D=1D

D=2D

ESATA

JESA1

USB

VBUS DD+ GND

GND A+

ESATA

A-

14

GND

15

B-

GND

16

B+

GND

17

GND

DET1 DET2

FOX_3Q3813C-RB1C3B-7F

CONN@

USBP_P11

USBP_N11

USBP11+ USBP11-

USBP11+<19> USBP11-<19>

+3VS

DMIC_CLK< 25>

DMIC0<25>

Layout note: Pin5 thru individual via to GND layer

Place close JCAM1

L27 WCM2012F2S-900T04_0805@L27 WCM2012F2S-900T04_0805@

1

2

4

R297 0_0402_5%~DR297 0_0402_5%~D R299 0_0402_5%~DR299 0_0402_5%~D L28 BLM 18BB221SN1D_2P~DL28 BLM18BB221SN1D_2P~D

D35

1

CH1

2

Vn

3

CH2

CM1293-04SO_SOT23-6@

3

4

12 12 12

4

CH4

5

Vp

6

CH3

2

3

C458

100P_0402_50V8J~D

C458

100P_0402_50V8J~D

1

2

DMIC_CLK

+3VS

DMIC0

Camera Conn

USBP_P11 USBP_N11

DMIC_CLK

DMIC0

C459

100P_0402_50V8J~D

C459

100P_0402_50V8J~D

1

2

JCAM1

1

2

3

4

5

6

7

8

GND

9

GND

MOLEX_48227-0701

CONN@

Cardreader Connector

FOX_GS12301-1011A-9F~D

30

USB_EN#<31>

CB_CLKREQ#<16>

PLT_RST#<6,19,24,27,28,31>

Deciphered Date

USB_OC1#<19>

USBP1+<19> USBP1-<19>

+5VALW

+3VS

PCIE_ITX_C_CBRX_P4

PCIE_ITX_C_CBRX_N4

PCIE_IRX_CBTX_P4 PCIE_IRX_CBTX_N4

CLK_PCIE_CB CLK_PCIE_CB#

CB_CLKREQ# PLT_RST#

JBT1

BT_DET#<31>

COEX2_WLAN_ACTIVE<27,28>

BT_RADIO_OFF#<31>

BT_OFF#<31>

R995

@R995

@

10K_0402_5%~D

1 2

USBP10-

USBP10+

BT_DET# BT_ACTIVE COEX2_WLAN_ACTIVE

BT_OFF# USBP10+ BT_RADIO_OFF# USBP10 -

BT_ACTIVE

@

C457 47P_0402_50V 8J~D

1 2

@

C456 47P_0402_50V 8J~D

1 2

JBT1

2

112

4

334

6

556

8

778

10

9910

12

111112

14

131314

16

GND15GND

HRS_DF12(3.0)-14DP-0.5V(86)~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

BT_ACTIVE <27>

+3VS

USBP10+ <19>

USBP10- <19>

PCIE_ITX_C_CBRX_P4<16> PCIE_ITX_C_CBRX_N4<16>

PCIE_IRX_CBTX_P4<16> PCIE_IRX_CBTX_N4<16>

CLK_PCIE_CB<16> CLK_PCIE_CB#<16>

Compal Secret Data

2009/09/21 2010/09/21

Compal Secret Data

29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

JCARD1

CONN@

34

G4

33

G3

32

G2

31

G1

USBP2-<19> USBP2+<19>

USB_EN#<31>

USB_OC2#<19> BATT_CHG_LED#<31> BATT_LOW_LED#<31>

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

USB/BlueTooth/Camera/ESATA

NAT02 M/B LA-5154P Schematic

to Single USB boardBluetooth

+5VALW

FCI_10089709-010010-LF

10

11 12

1 2 3 4 5 6 7 8 9

JSUSB1

1 2 3 4 5 6 7 8 9 10

G1 G2

CONN@

30 49Thursday, November 26, 2009

1.0

+3VALW

R0.3 Modify

Add 47K pu ll high

R306 10K_0402_5%~DR 306 10K_0402_5%~D

R322 47K_0402_5%R322 47K_0402_5%

1 2

R307 470_0402_5%~DR307 470_0402_5 %~D

1 2

R1237 10K_0402_5%~D@R1237 10K _0402_5%~D@

R926 10K_0402_5%~DR 926 10K_0402_5%~D

R314 2.2K_0402_5%~DR314 2.2K_0402_5%~D

R315 2.2K_0402_5%~DR315 2.2K_0402_5%~D

R324 10K_0402_5%~DR 324 10K_0402_5%~D

R308 47K_0402_5%R308 47K_0402_5%

R309 47K_0402_5%R309 47K_0402_5%

12

1 2

For ENE strape pin

R0.3 Modify

+3VS

R317 2.2K_0402_5%~DR317 2.2K_0402_5%~D

R318 2.2K_0402_5%~DR318 2.2K_0402_5%~D

R319 4.7K_0402_5%~D@ R319 4.7K_0402_ 5%~D@

R320 4.7K_0402_5%~DR320 4.7K_0402_5%~D

R339 4.7K_0402_5%~DR339 4.7K_0402_5%~D

R342 4.7K_0402_5%~DR342 4.7K_0402_5%~D

+5VS

R325 4.7K_0402_5%~DR325 4.7K_0402_5%~D

R326 4.7K_0402_5%~DR326 4.7K_0402_5%~D

R948 200K_0402_5%R948 200K_0402_5%

12

1 2

EC Adam_Yang request

ICH_PCIE_WAKE#<17,24,27,28>

CLK_PCI_EC

12

R327

@ R327

@

10_0402_5%~D

1

C478

@C478

@

15P_0402_50V8J~D

2

12

PCIE_PME#

KSI4

EC_RST#

C475 0.1U_0402_16V4Z~DC475 0.1U_0402_16V4Z~D

12

USB_DET#_DELAY

EN_KBL#

EC_SMB_DA1

EC_SMB_CK1

MSEN#

KSO2

KSO1

EC_SMB_DA2

EC_SMB_CK2

LCD_TST

BT_RADIO_OFF#

EC_FB_SCLK

EC_FB_SDATA

TP_DATA

TP_CLK

KSO5

R977 0_0402_5%~DR977 0_0402_5%~D

1 2

C479

33P_0402_50V8J~D

C479

33P_0402_50V8J~D

C467

0.1U_0402_16V4Z~D

C467

0.1U_0402_16V4Z~D

1

2

KB_RST#<20>

LPC_FRAME#<15,27>

CLK_PCI_EC<19> PLT_RST#<6,19,24,27,28,30>

EC_SCI#<20>

TOUCHKEY_TINT<15,32>

KSI[0..7]<32>

KSO[0..18]<32>

EC_SMB_CK1<47> EC_SMB_DA1<47> EC_SMB_CK2<16,27,28> EC_SMB_DA2<16,27,28>

SLP_S3#<17>

PM_SLP_S5#<17>

EC_SMI#<20>

LID_SW#<32> EC_FB_SCLK<32> EC_FB_SDATA<32>

KB_BL_PWM#<32>

FAN_SPEED1<14>

WLAN_RADIO_OFF#<27>

EC_TX_P80_DATA<17,27>

EC_RX_P80_DATA<27>

ON_OFF<32>

PWR_BTN_LED#<32>

EN_KBL#<32>

R328

1 2

20M_0603_5%@

Y5

1

2

32.768KHZ_12.5PF_QTFM28-32768K1

XCLKIXCLKO

4

3

GG

+3VALW

C472

1000P_0402_50V7K~D

C472

1000P_0402_50V7K~D

C471

1000P_0402_50V7K~D

C471

C469

0.1U_0402_16V4Z~D

C469

0.1U_0402_16V4Z~D

C468

0.1U_0402_16V4Z~D

1

2

GATEA20<20>

SERIRQ<15>

LPC_AD3<15,27> LPC_AD2<15,27> LPC_AD1<15,27> LPC_AD0<15,27>

GATEA20 KB_RST# SERIRQ LPC_FRAME#LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

CLK_PCI_EC PLT_RST#

EC_RST# EC_SCI# TOUCHKEY_TINT

KSI[0..7]

KSO[0..18]

EC_SMB_CK1

EC_SMB_DA1

EC_SMB_CK2

EC_SMB_DA2

SLP_S3# EC_RSMRST# PM_SLP_S5# EC_SMI# EC_ON LID_SW# BT_RADIO_OFF# EC_FB_SCLK

EC_FB_SDATA

PCIE_PME# KB_BL_PWM# FAN_SPEED1 WLAN_RADIO_OFF# EC_TX_P80_DATA EC_RX_P80_DATA ON_OFF

PWR_BTN_LED# EN_KBL#

XCLKI XCLKO

C481

33P_0402_50V8J~D

C481

33P_0402_50V8J~DC468

1000P_0402_50V7K~D

C470

0.1U_0402_16V4Z~D

C470

1

2

0.1U_0402_16V4Z~D

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14

KSO15 KSO16 KSO17 KSO18

1

2

U19

1

GA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ#

4

LFRAME#

5

LAD3

7

LAD2

8

LAD1

10

LPC & MISC

LAD0

12

PCICLK

13

PCIRST#/GPIO05

37

ECRST#

20

SCI#/GPIO0E

38

CLKRUN#/GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

SCL1/GPIO44

78

SDA1/GPIO45

79

SCL2/GPIO46

80

SDA2/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

LID_SW#/GPIO0A

17

SUSP#/GPIO0B

18

PBTN_OUT#/GPIO0C

19

EC_PME#/GPIO0D

25

EC_THERM#/GPIO11

28

FAN_SPEED1/FANFB1/GPIO14

29

FANFB2/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

ON_OFF/GPIO18

34

PWR_LED#/GPIO19

36

NUMLED#/GPIO1A

122

XCLK1

123

XCLK0

KB926QFD3_LQFP128

Int. K/B

Int. K/B Matrix

Matrix

SM Bus

9

22

33

VCC

PWM Output

DA Output

PS2 Interface

SPI Device Interface

GPIO

GND

11

24

D3 Version : P/N : SA00001J580

+EC_AVCC

96

111

125

VCC

INVT_PWM/PWM 1/GPIO0F

ACOFF/FANPWM2/GPIO13

AD Input

TP_DATA/PSDAT3/GPIO4F

SPI Flash ROM

BATT_CHGI_LED#/GPIO52

GPIO

BATT_LOW_LED#/GPIO54

GPO

GPI

GND

35

94

113

67

AVCC

BEEP#/PWM2/GPIO10

FANPWM1/GPIO12

BATT_TEMP/AD0/GPIO38

BATT_OVP/AD1/GPIO39

ADP_I/AD2/GPIO3A

AD3/GPIO3B

AD4/GPIO42

SELIO2#/AD5/GPIO43

DAC_BRIG/DA0/GPIO3C

EN_DFAN1/DA1/GPIO3D

IREF/DA2/GPIO3E

DA3/GPIO3F

PSCLK1/GPIO4A PSDAT1/GPIO4B PSCLK2/GPIO4C PSDAT2/GPIO4D

TP_CLK/PSCLK3/GPIO4E

SDICS#/GPXOA00 SDICLK/GPXOA01

SDIDO/GPXOA02

SDIDI/GPXID0

SPIDI/RD#

SPIDO/WR#

SPICLK/GPIO58

SPICS#

CIR_RX/GPIO40

CIR_RLC_TX/GPIO41

FSTCHG/SELIO#/GPIO50

CAPS_LED#/GPIO53

SUSP_LED#/GPIO55

SYSON/GPIO56

VR_ON/XCLK32K/GPIO57

AC_IN/GPIO59

EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04

EC_ON/GPXO05

EC_SWI#/GPXO06

ICH_PWROK/GPXO06

BKOFF#/GPXO08

WL_OFF#/GPXO09

GPXO10 GPXO11

PM_SLP_S4#/GPXID1

ENBKL/GPXID2

GPXID3 GPXID4 GPXID5 GPXID6 GPXID7

V18R

AGND

69

ECAGND

1000P_0402_50V7K~D

ECAGND

EC_PWM

21

BEEP#

23

PWRSHARE_EN #

26

ACOFF

27

63 64

ADP_I

65

AD_BID

66

MSEN#

75

SUS_PWR_ACK_R

76

EC_SUB_MUTE#

68

EN_DFAN1

70

IREF

71 72

LCD_TST

83

USB_EN#

84

GFXVR_PWRGD

85

KSO5

86

TP_CLK

87

TP_DATA

88

WPAN_RADIO_OFF#

97

EN_WOL#

98

BT_OFF#

99

VGATE

109

FRD#SPI_SO

119

FWR#SPI_SI

120

SPI_CLK

126

FSEL#SPICS#

128

EC_SPK_HP_MUTE#

73

USB_DET#_DELAY

74

FSTCHG

89

BATT_CHG_LED#

90

PWRSHARE_OE#

91

BATT_LOW_LED#

92

BKLT_KB_DET#

93

SYSON

95

VR_ON

121

EC_ACIN

127

100

EC_LID_OUT#

101 102 103

ICH_PWROK

104

BKOFF#

105

WWAN_RA DIO_OFF#

106

LCD_VCC_TEST_EN

107

CP_SEL

108

PCH_GPIO49

110

EC_ENBKL

112

BT_DET#

114

SBPWR_EN

115

SUSP#

116 117

PS_ID

118

124

R0.3 modify

1

C473

2

R0.3 modify

C522 0.01U_0402_16V7K ~DC522 0.01U_0402_16V7K~D

C476 0.01U_0402_16V7K ~DC476 0.01U_0402_16V7K~D

BATT_TEMP BATT_OVP

PBTN_OUT#

C480 1U_0603_10V 4Z~DC480 1U_0603_10V4Z~D

1 2

C482 0.1U_0402_16V4Z ~DC482 0.1U_0402_16V4Z~D

12

L29

L29 BLM18BD601SN1D_0603~D

BLM18BD601SN1D_0603~D

2

C474

0.1U_0402_16V4Z~D

1

BLM18BD601SN1D_0603~D

EC_PWM <35> BEEP# <25> PWRSHARE_EN # <30> ACOFF <41>

1 2 1 2

BATT_TEMP <47> BATT_OVP <47> ADP_I <41>

MSEN# <35>

1 2

R1569 0_0402_5%~DR1569 0_0402_5%~D

EC_SUB_MUTE# <25> EN_DFAN1 <14> IREF <41> CHGVADJ <41>

LCD_TST <35> USB_EN# <30> GFXVR_PWRGD <48> KSO5 <32> TP_CLK <32> TP_DATA <32>

WPAN_RADIO_OFF# <28> EN_WOL# < 24> BT_OFF# <30> VGATE <13,17,46>

EC_SPK_HP_MUTE# <25> USB_DET#_DELAY <32> FSTCHG <41> BATT_CHG_LED# <30> PWRSHARE_OE# <30> BATT_LOW_LED# <30> BKLT_KB_DET# <32> SYSON <28,33,44> VR_ON <46>

EC_RSMRST# <17> EC_LID_OUT# <16> EC_ON <32> BT_RADIO_OFF# <30> ICH_PWROK < 17> BKOFF# <35> WWAN_RA DIO_OFF# <27> LCD_VCC_TEST_EN <35> CP_SEL <41>

PCH_GPIO49 <20>

BT_DET# <30> SBPWR_EN <33> SUSP# <28,33,43,44,45> PBTN_OUT# <6,17> PS_ID <40>

12

L30

+3VALW+EC_AVCC

Board ID

R1.0 modify

*

ECAGND ECAGND

Board ID

X00

SUS_PWR_ACK <17>

R1.0 modify

X01

*

X02

MP UMA 33K +/- 5% 0.819V

*

Follow the suggestion of EC team to follow JAT10 setting.

place close U19

R333

15_0402_5%~D

SPI_CLK_R

12

1

22P_0402_50V8J~D

22P_0402_50V8J~D C1122

C1122

2

*

EC_ACIN

SPI_CS#

*

SPI_SO +SPI_R

*

SPI Flash (1Mbit/128Kbyte)

R331

R331 15_0402_5%~D

FSEL#SPICS#

15_0402_5%~D

1 2

R332

R332 15_0402_5%~D

15_0402_5%~D

12

SPI_CS# SPI_SOFRD#SPI_SO

Place under u20

+3VALW

R311

R311 100K_0402_5%~D

100K_0402_5%~D

Ra

1 2

Rb

AD_BID

R312

R312 33K_0402_5%~D

33K_0402_5%~D

1 2

1

C477

0.1U_0402_16V4Z~D

2

VCC 3.3V+/-5% 0.6V~1.6V

Ra

VGA

UMA

R1215

20mils

100K

Rb

0 +/- 5%

8.2K+/- 5%

18K +/- 5%

R557

R557 0_0402_5%~D

112 334 556 778

+SPI_R

CS# SO WP# GND

0_0402_5%~D

1 2

10K_0402_5%~D

2 4 6 8

SPI_CLK_R

R329

R329 10K_0402_5%~D

10K_0402_5%~D

12

VCC

HOLD#

SCLK

SI

EC_ENBKL

1 2

2 1

D54

D54 CH751H-40PT_SOD323-2~D

CH751H-40PT_SOD323-2~D

JP1

E&T_2941-G08N-00E~D

CONN@

U20

1 2 3 4

MX25L1005AMC-12G_SO8

0 V

0.250V

0.503V

+3VALW

ACIN <17,25,40,41>

+SPI_R SPI_CLK_R SPI_SI

R330

R330 22_0402_5%~D

22_0402_5%~D

+3VALW

8 7

SPI_CLK_R

6 5

+3VALW

12

2

1

R0.3 modify

IGPU_BKLT_EN <18>

22P_0402_50V8J~D

12

C483

C484

0.1U_0402_16V4Z~D

1 2

R334

R334 15_0402_5%~D

15_0402_5%~D

FWR#SPI_SISPI_SI

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/09/21 2010/09/21

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

EC_KB926/BIOS/Reed SW

NAT02 M/B LA-5154P Schematic

31 49Thursday, November 26, 2009

1.0

A

B

C

D

E

To power board

R896

200_0402_5%~D

PWR_LED+

1 2

+5VALW

PWR_BTN_LED#<31>

1 1

D30

1

PESD24VS2UT_SOT23-3~D

PWR_BTN_LED# PWR_ON-OFF_BTN#

PWR_ON-OFF_BTN#

3

2

JPBTN1

1

2

3

G5

4

G6

MOLEX_53261-0471

CONN@

5 6

Power Button Circuit

R0.3 Modify

PWR_ON-OFF_BTN#<14>

EC_ON<31>

EC_ON

12

R337

R337 10K_0402_5%~D

10K_0402_5%~D

1 2

1

BAT54C-7-F_SOT23~D

R336

R336 0_0402_5%~D

0_0402_5%~D

+3VALW

R335

1 2

D11

2

100K_0402_5%~D

51ON#

3

13

D

Q6

2

PMF3800SN_SC70-3

G

S

ON_OFF <31>

51ON# <40>

KSI[0..7]<31>

KSO[0..18]<31>

KSI[0..7]

KSO[0..18]

Place close JPBTN1

RTCVREF RTCVREF R TCVREF RTCVREF

2 2

USB_DETECT#<30>

USB_DETECT#

12

R1143

10K_0402_1%~D R1143

10K_0402_1%~D

2.2U_0603_10V7K~D

C1069

220K_0402_5%

12

R1144

12

D51

SDMK0340L-7-F

D51

SDMK0340L-7-F

2 1

U51

TC7SZ14FU_SSOP5~D

U51

SDMK0340L-7-F

1

NC

2

A

G

3

2 1

D52

1

2

5

P

4

Y

R1145

100K_0402_5%~D

CLOSE TO U48

C1068

0.1U_0402_16V4Z~D

2

G

12

1 2

D58

@ D5 8

@

SDMK0340L-7-F

51ON#

13

D

Q56

Q56 2N7002LT1G_SOT23-3

2N7002LT1G_SOT23-3

S

0_0402_5%~D

R1238

USB_DET#_DELAY

21

R0.3 Modify

51ON# <40>

USB_DET#_DELAY <31>

Touch Screen Connector

D36

1

2

3

CH1

Vn

CH2

CH4

Vp

CH3

CM1293-04SO_SOT23-6@

Place close JTCH1

Touch PAD/B Conn.

Power share

3 3

Keyboard back light

+5VS

1U_0603_10V6K~D

R928

300K_0402_5%

R928

300K_0402_5%

1 2

13

D

Q40

PMF3800SN_SC70-3

S

A

1U_0603_10V6K~D

C928

EN_KBL

B+_BIAS

EN_KBL#<31>

4 4

2

G

Q38

SI3456BDV-T1-E3 1N TSOP6 W/D

D

6

S

1

2

S

2 1

G

3

2M_0402_5%~D

1 2

0.75A_24V_1812L075-24DR~OK

45

20mil

R931

1 2

0_0805_5%~D

KB_BL_PWM#<31>

@

F1

R929

+5VS_KBL

12

BKLT_KB_DET

20mil

12

R930

R930 100K_0402_5%~D

100K_0402_5%~D

BKLT_KB_DET

KB_BL_PWM

13

D

2

G

S

B

+3VS

12

13

D

2

G

S

+5VS_KBL

1 2 3

20mil

Q41

Q41 MMBF170LT1G 1N SOT23-3

MMBF170LT1G 1N SOT23-3

20mil

R927

R927 10K_0402_5%~D

10K_0402_5%~D

BKLT_KB_DET#

Q39

Q39 MMBF170LT1G 1N SOT23-3

MMBF170LT1G 1N SOT23-3

JKBL1

1 2

5

3

GND

6

44GND

TYCO_2041084-4

CONN@

BKLT_KB_DET# <31>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VALW

R933 0_0402_5%~DR933 0_0402_5%~D

R934 10K_0402_5%~DR934 10K_0402_5%~D

1

2

Cap Sensor

2009/09/21 2010/09/21

C

+HALL_VCC

1 2

C521

0.1U_0402_16V4Z~D

C959

33P_0402_50V8J~D

1 2

C960

33P_0402_50V8J~D

1 2

LID_SW#

EC_FB_SDATA<31>

EC_FB_SCLK<31>

TOUCHKEY_TINT<15,31>

FB_SDATA

FB_SCLK

Compal Secret Data

KSI7 KSI6 KSI4 KSI2 KSI5 KSI1 KSI3 KSI0 KSO5 KSO4 KSO7 KSO6 KSO8 KSO3 KSO1 KSO2 KSO0 KSO12 KSO16 KSO15 KSO13 KSO14 KSO9 KSO11 KSO10 KSO17 KSO18

USBP9-

4

5

USBP9+

6

0.1U_0402_16V4Z~D

Deciphered Date

JAE_FL4S030HB3R3000

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

+3VS

9 8 7 6 5 4 3 2 1

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

JKB1

CONN@

C512

GND GND

+5VS

32 31

KSI0

KSI1

KSI2

KSI3

KSI4

KSI5

KSI6

KSI7

KSO0

KSO1

KSO2

KSO3

KSO4

KSO5

R0.3 Modify

+3VS

R1236 0_0402_5%~DR1236 0_0402_5%~D

USBP9-<19> USBP9+<19>

TP_CLK<31> LID_SW#<31> TP_DATA<31>

1

2

PESD5V2S2UT_SOT23-3~D

R0.3 Modify

L77 BLM18BD601SN1D _0603~DL77 BLM18BD601SN1D _0603~D

1 2

L78 BLM18BD601SN1D _0603~DL78 BLM18BD601SN1D _0603~D

1 2

TOUCHKEY_TINT

PESD5V2S2UT_SOT23-3~D

R0.3 Modify

D

C485 100P_0402_50V8J~D@ C485 100P _0402_50V8J~D@

C487 100P_0402_50V8J~D@ C487 100P _0402_50V8J~D@

C489 100P_0402_50V8J~D@ C489 100P _0402_50V8J~D@

C493 100P_0402_50V8J~D@ C493 100P _0402_50V8J~D@

C495 100P_0402_50V8J~D@ C495 100P _0402_50V8J~D@

C497 100P_0402_50V8J~D@ C497 100P _0402_50V8J~D@

C499 100P_0402_50V8J~D@ C499 100P _0402_50V8J~D@

C501 100P_0402_50V8J~D@ C501 100P _0402_50V8J~D@

C503 100P_0402_50V8J~D@ C503 100P _0402_50V8J~D@

C505 100P_0402_50V8J~D@ C505 100P _0402_50V8J~D@

C507 100P_0402_50V8J~D@ C507 100P _0402_50V8J~D@

C509 100P_0402_50V8J~D@ C509 100P _0402_50V8J~D@

C511 100P_0402_50V8J~D@ C511 100P _0402_50V8J~D@

JTCH1

10

1

G2

2

1 2

USBP9-

USBP9+

3

4

5

6

7

8

G1

9

JST_SM08B-SURS-TF(LF)(SN)~D

CONN@

TP_CLK LID_SW# TP_DATA

+HALL_VCC

2

3

C513

100P_0402_50V8J~D

C513

100P_0402_50V8J~D

D55

1

R1003 0_0402_5%~D@R1003 0_0402_5%~D@

2

3

D56

1

Title

PWROK/BTN/KB/Touch Pad

Size Document Number Rev

Custom

NAT02 M/B LA-5154P Schematic

Date: Sheet of

1

2

+5VS +3VS

FB_SDATA FB_SCLK

1 2

Compal Electronics, Inc.

KSO6

C486 100P_0402_50V8J~D@ C486 100P _0402_50V8J~D@

KSO7

C488 100P_0402_50V8J~D@ C488 100P _0402_50V8J~D@

KSO8

C490 100P_0402_50V8J~D@ C490 100P _0402_50V8J~D@

KSO9

C492 100P_0402_50V8J~D@ C492 100P _0402_50V8J~D@C491 100P_0402_50V8J~D@ C491 100P_0402_50 V8J~D@

KSO10

C494 100P_0402_50V8J~D@ C494 100P _0402_50V8J~D@

KSO11

C496 100P_0402_50V8J~D@ C496 100P _0402_50V8J~D@

KSO12

C498 100P_0402_50V8J~D@ C498 100P _0402_50V8J~D@

KSO13

C500 100P_0402_50V8J~D@ C500 100P _0402_50V8J~D@

KSO14

C502 100P_0402_50V8J~D@ C502 100P _0402_50V8J~D@

KSO15

C504 100P_0402_50V8J~D@ C504 100P _0402_50V8J~D@

KSO16

C506 100P_0402_50V8J~D@ C506 100P _0402_50V8J~D@

KSO17

C508 100P_0402_50V8J~D@ C508 100P _0402_50V8J~D@

KSO18

C510 100P_0402_50V8J~D@ C510 100P _0402_50V8J~D@

For EMI

+3VS

1

C927

0.1U_0402_16V4Z~D

2

C514

100P_0402_50V8J~D

C514

100P_0402_50V8J~D

1

2

E

JTP1

1

2

3

4

5

7

5

G1

6

8

6

G2

TYCO_2041084-6~D

CONN@

JCAP1

6

8

6

G2

5

7

5

G1

4

3

2

1

TYCO_2041084-6

CONN@

32 49Thursday, November 26, 2009

1.0

INT_KB_Conn.1

A

B

C

D

E

+3VALW to +3VS Transfer

B+_BIAS

12

R338

330K_0402_5%

1 1

SUSP

2

G

1

2

13

D

Q7

PMF3800SN_SC70-3

S

U21

8

10U_0805_10V4Z~D

7

C515

5

AO4468 1N SO8

4

R0.3 modify

1

12

R340

2

2M_0402_5%~D

+3VS+3VALW

8.73A

3 2 16

1

2

C524

0.01U_0402_25V7K~D

C517

10U_0805_10V4Z~D

C517

10U_0805_10V4Z~D

C516

0.1U_0402_16V4Z~D

C516

0.1U_0402_16V4Z~D

1

2

+3VALW to +3V Transfer (PCH AUX Power)

B+_BIAS

R1152

330K_0402_5%

SBPWR_EN#

2

G

+3VALW +3V

U52

U52 SI4800BDY-T1-E3_SO8

SI4800BDY-T1-E3_SO8

1

C1070

2

10U_0805_10V4Z~D

C1073

8 7

5

3V_GATE

1

2

12

1 2

R1153

R1153 0_0402_5%~D

0_0402_5%~D

13

D

Q60

PMF3800SN_SC70-3

S

JP9@ JP9@

1 2

169mA

10U_0805_10V4Z~D

1 2 36

1

C1071

C1072

4

12

0.1U_0402_16V4Z~D

R1235

2M_0402_5%~D

0.01U_0402_25V7K~D

C1072

2

100K_0402_5%~D

SYSON#

SYSON

R355

R355 10K_0402_5%~D

10K_0402_5%~D

1 2

+5VALW

R354

2

G

12

13

D

Q16

Q16 PMF3800SN_SC70-3

PMF3800SN_SC70-3

S

+5VALW

12

R1151

100K_0402_5%~D

SBPWR_EN#<2 2>

SBPWR_EN<31>

SBPWR_EN#

SBPWR_EN

2

G

R1154

R1154 10K_0402_5%~D

10K_0402_5%~D

1 2

13

D

Q59

Q59 PMF3800SN_SC70-3

PMF3800SN_SC70-3

S

SYSON<28,31,44>

+5VALW to +5VS Transfer

3 2 16

7.69A

+5VS+5VALW

C519

0.1U_0402_16V4Z~D

C519

0.1U_0402_16V4Z~D

C520

10U_0805_10V4Z~D

C520

10U_0805_10V4Z~D

1

2

100K_0402_5%~D

SUSP

B+_BIAS

10U_0805_10V4Z~D

12

C518

R1216

330K_0402_5%

2 2

SUSP

2

G

1

2

13

D

Q68

PMF3800SN_SC70-3

S

U22

8 7

5

AO4468 1N SO8

12

@

R341

390K_0402_5%

4

R0.3 modify

1

C525

0.01U_0402_25V7K~D

2

R379

2

G

+3VALW

12

13

D

Q75

Q75 PMF3800SN_SC70-3

PMF3800SN_SC70-3

S

C1147

SUSP

1 2

+5VALW

12

R360

100K_0402_5%~D

13

D

2

G

S

R361

R361 10K_0402_5%~D

10K_0402_5%~D

Q21

Q21 PMF3800SN_SC70-3

PMF3800SN_SC70-3

+3VALW

C1146

1 2

0.1U_0402_10V6K~D

5

U64

1

P

IN1

4

O

2

IN2

G

74AHC1G08GW_SOT353-5~D

1

2

0.01U_0402_25V7K~D

74AHC1G08GW_SOT353-5~D

3

@

12

R1252 0_0402_5%~D

R396

1 2

100K_0402_5%~D

C1148

1.5VS_DDR_PWRGD <44>

1

13

D

SUSP

2

G

2

G

Q13

S

0.01U_0402_25V7K~D

PMF3800SN_SC70-3

SUSP#<28,31,43,44,45>

SUSP#

+1.5V to +1.5VS Transfer

B+_BIAS

12

3 3

13

D

SUSP

D

2

G

S

+1.5V

R344

R344 470K_0402_5%

470K_0402_5%

Q10

PMF3800SN_SC70-3

Q55

8 7

5

Si4634 1N SO8

12

R1157

2M_0402_5%~D

3 2 16

4

R1.0 modify

1

C532

470P_0402_50V7K~D

2

+1.5V to +1.5VS_DDR Transfer

B+_BIAS +1.5V +1.5V_CPU_DD R

12

R346

R346 470K_0402_5%

470K_0402_5%

4 4

SUSP

2

G

13

D

Q11

PMF3800SN_SC70-3

S

Q73

S

D

S

D

S

D

G

D

Si4634 1N SO8

R1158

2M_0402_5%~D

1 2 3 4

R1.0 modify

1

C534

470P_0402_50V7K~D

2

8 7 6 5

12

A

+1.5VS

10U_0805_10V4Z~D

R345

20K_0402_1%~D

R345

20K_0402_1%~D

12

C531

1

2

10U_0805_10V4Z~D

R349

20K_0402_1%~D

R349

20K_0402_1%~D

12

C536

1

2

B

Discharge Circuit

+1.5V +1.05VS +1.1VS_VTT

12

R353

470_0402_5%~D

13

D

2

G

+1.5V_CPU_DDR

2

G

C

D

Q15

S

PMF3800SN_SC70-3

12

220_0402_5%~D

220_0402_5%~D R364

R364

13

D

Q74

S

PMF3800SN_SC70-3

2009/09/21 2010/09/21

SBPWR_EN#

SUSP

SYSON#

SUSP

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CON TAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CON TAINS CONFIDENTIAL AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3V

12

R1155

470_0402_5%~D

13

D

2

G

Q61

S

PMF3800SN_SC70-3

+0.75VS

12

R358

R358 470_0603_5%

470_0603_5%

13

D

2

G

Q19

S

PMF3800SN_SC70-3

Compal Secret Data

Deciphered Date

SUSP

SUSP SUSP

D

2

G

+5VS

2

G

12

R352

470_0402_5%~D

13

D

Q12

S

PMF3800SN_SC70-3

12

R359

470_0402_5%~D

13

D

Q20

S

PMF3800SN_SC70-3

Title

Size Document Number Rev

Custom

NAT02 M/B LA-5154P Schematic

Date: Sheet of

SUSP

Compal Electronics, Inc.

DC/DC Interface

2

G

+3VS

2

G

E

R1034

470_0603_5%

1 2

13

D

Q54

S

PMF3800SN_SC70-3

12

R356

470_0402_5%~D

13

D

Q17

S

PMF3800SN_SC70-3

1.0

33 49Thursday, November 26, 2009

1.0

5

FD2

FD1

FD1 FIDUCAL

FIDUCAL

@

D D

FD2 FIDUCAL

FIDUCAL

@

1

FD3

FD3 FIDUCAL

FIDUCAL

@

1

4

FD4

FD4 FIDUCAL

FIDUCAL

@

1

3

ZZZ

PCB

2

1

H_2P5

H6 HOLEA@H6HOLEA@

H_2P2

1

H_3P1

C C

H_1P6N

H_3P0

H_3P2

B B

H_4P0

H_3P0X4P0

H2 HOLEA@H2HOLEA@

H7 HOLEA@H7HOLEA@

H17

H17 HOLEA@

HOLEA@

H25

H25 HOLEA@

HOLEA@

H29

H29 HOLEA@

HOLEA@

1

H9

H10

H8 HOLEA@H8HOLEA@

H26

H26 HOLEA@

HOLEA@

H18

H18 HOLEA@

HOLEA@

H3 HOLEA@H3HOLEA@

1

H27

H27 HOLEA@

HOLEA@

1

HOLEA@H9HOLEA@

H19

H19 HOLEA@

HOLEA@

H4 HOLEA@H4HOLEA@

H10 HOLEA@

HOLEA@

1

H24

H24 HOLEA@

HOLEA@

1

H20

H20 HOLEA@

HOLEA@

1

H28

H28 HOLEA@

HOLEA@

1

H11

H11 HOLEA@

HOLEA@

H21

H21 HOLEA@

HOLEA@

H12

H5

H14

H15

H16

HOLEA@

HOLEA@H5HOLEA@

HOLEA@

1

H23

H23 HOLEA@

HOLEA@

1

HOLEA@

H35

H35 HOLEA@

HOLEA@

H16 HOLEA@

HOLEA@

1

H36

H36 HOLEA@

HOLEA@

1

A A

Security Class ification

2009/09/ 21 2010/09/ 21

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/09/ 21 2010/09/ 21

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Screws

NAT02 M/B LA-5154P Schematic

34 49Thursday, November 26, 2 009

1

1.0

5

C R T

LU6 BLM18BB470S N1D_2P~DLU6 BLM18BB470SN1D_2P~D

D D

C C

VGA_CRT_R<18>

VGA_CRT_G<18>

VGA_CRT_B<18>

CRT_DDC_DATA<18>

CRT_DDC_CLK<18>

CU56

10P_0402_50V8J~D@CU56

10P_0402_50V8J~D

12

@

1 2

LU7 BLM18BB470S N1D_2P~DLU7 BLM18BB470SN1D_2P~D

1 2

LU8 BLM18BB470S N1D_2P~DLU8 BLM18BB470SN1D_2P~D

1 2

CU58

10P_0402_50V8J~D@CU58

10P_0402_50V8J~D

CU57

10P_0402_50V8J~D@CU57

10P_0402_50V8J~D

12

@

+3VS +CRT_VCC+ 3VS +CRT_VCC+3VS

2.2K_0402_5%~D

2.2K_0402_5%~D R370

R370

R369

2.2K_0402_5%~D

R369

2.2K_0402_5%~D

1 2

S

G

2

PMF3800SN_SC70-3

13

D

S

D

S

Q23

PMF3800SN_SC70-3

R366

150_0402_1%~D

R366

150_0402_1%~D

R367

150_0402_1%~D

R367

150_0402_1%~D

12

R371

2K_0402_1%~D

R371

2K_0402_1%~D

G

1 2

2

13

D

Q22

CRT_R

CRT_G

CRT_B

R368

150_0402_1%~D

R368

150_0402_1%~D

1

12

2

2K_0402_1%~D

1 2

CRT_DDC_DATA_C

CRT_DDC_CLK_C

4

DAN217_SC59-3

+3VS

CU550.1U_0402_16V4Z~D CU550.1U_0402_16V4Z~D

12

L31 BLM18BB470SN1D_2P~ DL31 BLM18B B470SN1D_2P~D

1 2

L32 BLM18BB470SN1D_2P~ DL32 BLM18B B470SN1D_2P~D

1 2

L33 BLM18BB470SN1D_2P~ DL33 BLM18B B470SN1D_2P~D

22P_0402_50V8J~D

C537

C538

1

2

@

R372

1 2

22P_0402_50V8J~D

C539

1

2

@

CRT_HSYNC<18>

CRT_VSYNC<18>

CRT_R_L

CRT_G_L

CRT_B_L

For EMI

10P_0402_50V8J~D

12

C545

0.1U_0402_16V4Z~D

1 2

CRT_HSYNC

C546

0.1U_0402_16V4Z~D

1 2

CRT_VSYNC

D14

DAN217_SC59-3

1

2

3

C540

12

+CRT_VCC

1

5

P

A2Y

G

74AHCT1G125GW_SOT353-5

3

+CRT_VCC

1

5

P

A2Y

G

3

D15

2

C541

10P_0402_50V8J~D

C541

10P_0402_50V8J~D

OE#

U26

OE#

U27

U27 74AHCT1G125GW_SOT353-5

74AHCT1G125GW_SOT353-5

1

3

4

D16

D16 DAN217_SC59-3

DAN217_SC59-3

1

2

C542

10P_0402_50V8J~D

C542

10P_0402_50V8J~D

12

R373

10K_0402_5%~D

1 2

2

3

MSEN#<31>

R1160

D_CRT_HSYNC HSYNC_L

D_CRT_VSYNC

R1160

1 2

R1161

1 2

0_0603_5%~D

+5VS

W=40mils

MSEN# CRT_R_L

CRT_DDC_DATA_C CRT_G_L

HSYNC_L CRT_B_L

VSYNC_L

CRT_DDC_CLK_C

100P_0402_50V8J~D

VSYNC_L

C547

15P_0402_50V8J~D

C547

15P_0402_50V8J~D

1

2

C543

2 1 3

100P_0402_50V8J~D

1

2

1

2

C544

15P_0402_50V8J~D

D17

W=40mils

NC

BAT1000-7-F_SOT23-3~D

1

2

C548

+CRT_VCC

1

2

6

11

1 7

12

2 8

13

3 9

14

4 10 15

5

C535

1U_0603_10V6K~D

JCRT1

16

G

17

G

TYCO_1775763-2

CONN@

1

R381 0_0805_5%~D@R381 0_0805_5%~D@

+LCDVDD +5V

R376

R376 470_0805_5%

R0.3 Modify

B B

SSM3K7002FU_SC70-3~D

D37

VGA_LVDDEN<18>

LCD_VCC_TEST_EN<31>

A A

BKOFF#<31>

LCD_VCC_TEST_EN

BKOFF# DISPOFF#

CH751H-40PT_SOD323-2~D

5

2

3

BAT54C-7-F_SOT23~D

D19

21

1

+3VS

12

R382

4.7K_0402_5%~D

470_0805_5%

1 2 13

D

Q24

S

R380

10K_0402_5%~D

G

R377

R377 47K_0402_5%

47K_0402_5%

1 2

R378

R378 56K_0402_5%

13

D

Q26

Q26 BSS138_SOT23~D

BSS138_SOT23~D

S

56K_0402_5%

12

2

G

12

R0.3 Modify

VGA_PWM<18>

EC_PWM<31>

4

W=60mils

+3VS

S

AO3413_SOT23-3

G

Q25

2

C549

0.1U_0402_16V4Z~D

C549

0.1U_0402_16V4Z~D

1

2

1

2

74AHC1G32GW_SOT353-5~D

D

1 3

1

C550

4.7U_0805_10V4Z~D

2

+3VS +3VS

5

U54

P

INA

4

O

INB

G

3

R944

@R944

@

0_0402_5%~D

12

R945

@R945

@

0_0402_5%~D

12

6.5

W=60mils

+LCDVDD

12

R394

@R394

@

10K_0402_5%~D

INVT_PWM

R02: Add

1

C551

0.1U_0402_16V4Z~D

2

1

CU63

@CU63

@

470P_0402_50V7K~D

2

+LCDVDD

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B+ +INV_PWR _SRC

40mil

B+

R1242

100K_0402_5%~D

R1242

100K_0402_5%~D

C1126

1000P_0402_50V7K~D

C1126

1000P_0402_50V7K~D

12

PWR_SRC_ON

12

R1243

R1243 100K_0402_5%~D

100K_0402_5%~D

13

D

Q71

2

G

SSM3K7002FU_SC70-3~D

G

SSM3K7002FU_SC70-3~D

S

reserve fo r RF reque st

3

1 2

LVDS_DDC_CLK<18>

Q70

Q70 SI3457BDV-T1-E3_TSOP6~D

SI3457BDV-T1-E3_TSOP6~D

D

6

S

4 5

2 1

G

1

3

2

40mil

+INV_PWR_SRC

C1127

0.1U_0603_50V4Z~D

LVDS_DDC_DATA<18>

R1.0 Modify

R02: Reserve for EMI (Place close to JLVDS1)

Compal Secret Data

2009/09/21 2010/09/21

Compal Secret Data

Deciphered Date

2

LCD_TST<31>

@

1 2

C1128 5P_0402_50V 8C

@

1 2

C1129 5P_0402_50V 8C

@

1 2

C1130 5P_0402_50V 8C

@

1 2

C1131 5P_0402_50V 8C

+LCDVDD

R374 0_0402_5%~DR374 0_0402_5%~D R375 0_0402_5%~DR375 0_0402_5%~D

+INV_PWR_SRC

+3VS

12 12

LVDS_A0-<18> LVDS_A0+<18>

LVDS_A1-<18> LVDS_A1+<18>

LVDS_A2-<18> LVDS_A2+<18>

LVDS_ACLK-<18> LVDS_ACLK+<18>

LVDS_B0-<18> LVDS_B0+<18>

LVDS_B1-<18> LVDS_B1+<18>

LVDS_B2-<18> LVDS_B2+<18>

LVDS_BCLK-<18> LVDS_BCLK+<18>

LCD_TST EDID_CLK_LCD

EDID_DATA_LCD LVDS_A0LVDS_A0+

LVDS_A1LVDS_A1+

LVDS_A2LVDS_A2+

LVDS_ACLK-

LVDS_ACLK++LCDVDDVGA_LVDDEN

LVDS_B0LVDS_B0+

LVDS_B1LVDS_B1+

LVDS_B2LVDS_B2+

LVDS_BCLK-

LVDS_BCLK+

INVT_PWM DISPOFF#

W=60mils

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

VGA / LVDS

NAT02 M/B LA-5154P Schematic

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

JLVDS1

JLVDS1 JAE_FI-G40SB-VF25-R2000

JAE_FI-G40SB-VF25-R2000

CONN@

1

49

G9

48

G8

47

G7

46

G6

45

G5

44

G4

43

G3

42

G2

41

G1

1.0

35 49Thursday, November 26, 2009

1.0

5

+3VS

0.1U_040 2_16V4Z~D

CU21

SDVO_SD ATA<1 8>

SDVO_SC LK<18>

0.1U_040 2_16V4Z~D

1

CU22

2

+3VS

HDMI_TX2+

HDMI_TX1+

HDMI_CLK+

HDMI_TX0+

RU47 10K_04 02_5%~D@RU47 10K _0402_5%~D@

1 2

RU48

1 2

0_0402_ 5%~D

RU49 10K_04 02_5%~D@RU49 10K _0402_5%~D@

1 2

0.1U_040 2_16V4Z~D

1

2

1

CU23

CU18

2

0.1U_040 2_16V4Z~D

1

2

internal pull down

RU21 10K_04 02_5%~D@RU21 10K _0402_5%~D@

1 2

RU25 4.7K_04 02_5%~DRU25 4.7K_04 02_5%~D

1 2

RU29 3.4K_04 02_1%~DRU29 3.4K_04 02_1%~D

1 2

+3VS

RU103 68_ 0402_5%~D

RU104 68_ 0402_5%~D

RU105 68_ 0402_5%~D

RU106 68_ 0402_5%~D

RU34 2.2K_04 02_5%~DRU34 2.2K_04 02_5%~D

RU36 2.2K_04 02_5%~DRU36 2.2K_04 02_5%~D

RU37 4.7K_04 02_5%~D@R U37 4.7K_04 02_5%~D@

1 2

@

1 2

@

1 2

@

1 2

@

1 2

EC_DVI_DE T

1 2

CU59 0 .5P_0402_50V8

@

1 2

CU60 0 .5P_0402_50V8

@

1 2

CU61 0 .5P_0402_50V8

@

1 2

CU62 0 .5P_0402_50V8

1

CU24

2

0.1U_040 2_16V4Z~D

EC_DVI_DE T

12

SDVO_SD ATA

12

SDVO_SC LK

HDMI_TX2-

HDMI_TX1-

HDMI_CLK-

HDMI_TX0-

0.1U_040 2_16V4Z~D

1

CU19

2

0.1U_040 2_16V4Z~D

D D

CU20

1

2

0.1U_040 2_16V4Z~D

Add RU25 4.7K pull down for AS M1442

Change RU29 to 3.4K for ASM144 2

C C

Reserve RU37 4.7K pull high fo r ASM1442

B B

+3VS

PCH_DPB _HPD<18 >

+3VS

OC_S0 OC_S1

OC_S2

4

U63

2

VCC3V

11

VCC3V

15

VCC3V

21

VCC3V

26

VCC3V

33

VCC3V

40

VCC3V

46

VCC3V

3

FUNCTION1

4

FUNCTION2

6

ANALOG1(REXT)

7

HPD_SOURCE

8

SDA_SOURCE

9

SCL_SOURCE

OC_S3

10

ANALOG2

13

OUT_D4+

14

OUT_D4-

16

OUT_D3+

17

OUT_D3-

19

OUT_D2+

20

OUT_D2-

22

OUT_D1+

23

OUT_D1-

1

GND

5

GND

12

GND

18

GND

24

GND

27

GND

31

GND

36

GND

37

GND

43

GND

ASM1442 _QFN48_7X7

Change U63 to SA00003GT00

OE*

SCL_SINK

SDA_SINK

HPD_SINK

DDC_EN

FUNCTION3 FUNCTION4

IN_D4+

IN_D4-

IN_D3+

IN_D3-

IN_D2+

IN_D2-

IN_D1+

IN_D1-

THERMAL_GND

2N7002L T1G_SOT23-3

OE#

RU19 0_0402 _5%~D@RU1 9 0_0402_ 5%~D@

25

HDMI_SCLK

28

HDMI_SDAT A

29

HDMI_HPD

30

RU27 0_0402 _5%~DRU27 0_0402_ 5%~D

32

EQ_S0

34

EQ_S1

35

Unpop RU28,RU32 Pop RU30,RU33

IN_D4+

48 47

45 44

42 41

39 38

49

RU107 0_0 402_5%~DRU107 0 _0402_5%~D

IN_D4-

RU108 0_0 402_5%~DRU108 0 _0402_5%~D

IN_D3+

RU109 0_0 402_5%~DRU109 0 _0402_5%~D

IN_D3-

RU110 0_0 402_5%~DRU110 0 _0402_5%~D

IN_D2+

RU111 0_0 402_5%~DRU111 0 _0402_5%~D

IN_D2-

RU112 0_0 402_5%~DRU112 0 _0402_5%~D

IN_D1+

RU113 0_0 402_5%~DRU113 0 _0402_5%~D

IN_D1-

RU114 0_0 402_5%~DRU114 0 _0402_5%~D

3

+3VS

12

RU17

RU17 10K_040 2_5%~D

10K_040 2_5%~D

OE#

13

D

QU1

1 2

RU28 10K_04 02_5%~D@RU28 10K _0402_5%~D@ RU30 10K_04 02_5%~DRU3 0 10K_040 2_5%~D RU32 10K_04 02_5%~D@RU32 10K _0402_5%~D@ RU33 10K_04 02_5%~DRU3 3 10K_040 2_5%~D

1 2 1 2

2

G

S

0.1U_040 2_16V4Z~D

RU20 2.2K_04 02_5%~DRU20 2.2K_04 02_5%~D

RU22 2.2K_04 02_5%~DRU22 2.2K_04 02_5%~D

1 2 1 2 1 2 1 2

CU26

12

+3VS

HDMI_HPD

12

1

RU18

RU18 100K_04 02_5%~D

100K_04 02_5%~D

2

+3VS

PCH_TMD S_D2 <18> PCH_TMD S_D2# <18 >

PCH_TMD S_D1 <18> PCH_TMD S_D1# <18 >

PCH_TMD S_CK <1 8> PCH_TMD S_CK# < 18>

PCH_TMD S_D0 <18> PCH_TMD S_D0# <18 >

+5VS

2

0_1206_ 5%

CU50

1U_0402 _6.3V6K~D

1 2

MURATA D LW21SN900 HQ2L

1

+5VS

12

FU1

@F U1

RU92

HDMI_CLK+ HDMI_R_CK+

HDMI_TX0+ HDMI_R_D0 +

HDMI_TX1+ HDMI_R_D1 +

HDMI_TX2+ HDMI_R_D2 +

@

1.5A_6V_ 1206L150PR~D

1 2

HDMI_HPD

+5VS_HD MI

HDMI_SDAT A HDMI_SCLK

HDMI_R_CK -

HDMI_R_CK + HDMI_R_D0 -

HDMI_R_D0 + HDMI_R_D1 -

HDMI_R_D1 + HDMI_R_D2 -

HDMI_R_D2 +

RU24 0_0402 _5%~D@RU2 4 0_0402_ 5%~D@

1

LU2

4

RU31 0_0402 _5%~D@RU3 1 0_0402_ 5%~D@

RU35 0_0402 _5%~D@RU3 5 0_0402_ 5%~D@

1

LU3

4

RU38 0_0402 _5%~D@RU3 8 0_0402_ 5%~D@

RU40 0_0402 _5%~D@RU4 0 0_0402_ 5%~D@

1

LU4

4

RU44 0_0402 _5%~D@RU4 4 0_0402_ 5%~D@

RU45 0_0402 _5%~D@RU4 5 0_0402_ 5%~D@

1

LU5

4

RU46 0_0402 _5%~D@RU4 6 0_0402_ 5%~D@

1 2

JHDMI1

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

FOX_QJ5 119L-NVBT-7F

CONN@

2

3

2

3

2

3

2

3

GND GND GND GND

20 21 22 23

HDMI_R_CK -HDMI_CLK-

HDMI_R_D0 -HDMI_TX0 -

HDMI_R_D1 -HDMI_TX1 -

HDMI_R_D2 -HDMI_TX2 -

A A

Security Class ification

2009/09/ 21 2010/09/ 21

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/09/ 21 2010/09/ 21

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Num ber Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

HDMI

NAT02 M/B LA-5154P Schematic

36 49Thursday, November 26, 2 009

1

1.0

5

D D

4

3

2

1

+5VS

4

DISP_A0N DISP_A0P

DISP_A1N DISP_A1P

DISP_A2N DISP_A2P

DISP_A3N DISP_A3P

0.1U_0402_10V7K~D

DP_AUX_SW DP_AUX#_SW

+3VS

0.1U_0402_10V7K~D

5NC1

P

A2Y

G

U66

3

CU34

12

CU36

0.1U_0402_10V7K~D

1 2

CU37

12

Place close JDP1

D38

@8D38

@

1

2

DISP_A1N DISP_A1N

DISP_A2P DISP_A2P

DISP_A2N DISP_A2N

DISP_A3P DISP_A3P

DISP_A3N DISP_A3N

4

5

3

8

RCLAMP0524P.TCT~D

D39

@8D39

@

1

2

4

5

3

8

RCLAMP0524P.TCT~D

Reserve ne ar connect or

100K_0402_5%~D

DISP_HD

DP_HPD<18>

RU98

@RU98

@

2

G

DISP_A0PDISP_A0P

10

DISP_A0NDISP_A0N

9

DISP_A1PDISP_A1P

7

6

10

9

7

6

+3VS +3VS

12

2

G

13

D

BSS138_SOT23~D

S

RU116

@RU116

@

0_0402_5%~D

1 2

12

RU99

@RU99

@

10K_0402_5%~D

13

D

BSS138_SOT23~D

S

QU5

@

QU5

@

Co-lay

F2

+3VS

DP_HPD <18>

QU6

@

QU6

@

DISP_HD

1 2

1.5A_6V_1206L150PR~D

R409 0_1206_5%~D@R409 0_1206_5 %~D@

DISP_A0P

DISP_A0N DISP_A1P

DISP_A1N DISP_A2P

DISP_A2N DISP_A3P

DISP_A3N DP_CA_DET DISP_CEC DP_AUX_SW

DP_AUX#_SW DISP_HD

+3VS_DP

12

R416 5.1M_0402_5%R 416 5.1M_0402_5%

12

R943 1M_0402_5%~DR943 1M_0402_5%~D12C573 22U_ 0805_6.3V6M~DC57 3 22U_0805_6.3V6M~D

+3VS_DP

C952

10U_0805_10V4Z~D

C952

10U_0805_10V4Z~D

C953

0.1U_0402_16V4Z~D

C953

0.1U_0402_16V4Z~D

1

2

JDP1

1

LANE0_P

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20

21

C572 0.1U_0402 _10V6K~DC572 0.1U_0402_10V6K~D

1

2

22 23 24

GND

LANE0_N

LANE1_P

GND

LANE1_N

LANE2_P

GND

LANE2_N

LANE3_P

GND

LANE3_N

CONFIG1

CONFIG2

AUXCH_P

GND

AUXCH_N

HPD

RETURN

DP_PWR

GROUND

FOX_3V102P1-RB2BT-8F

CONN@

C561 0.1U_0402_10V6K~DC561 0.1U_0402_10V6K~D

DISP_A0N_VGA<18> DISP_A0P_VGA<18>

DISP_A1N_VGA<18> DISP_A1P_VGA<18>

DISP_A2N_VGA<18> DISP_A2P_VGA<18>

DISP_A3N_VGA<18> DISP_A3P_VGA<18>

C C

DP_HPD<18>

RU100

100K_0402_5%~D

+5VS

G

S

12

QU4

QU4 BSS138_SOT23~D

BSS138_SOT23~D

2

12

C562 0.1U_0402_10V6K~DC562 0.1U_0402_10V6K~D

12

C563 0.1U_0402_10V6K~DC563 0.1U_0402_10V6K~D

12

C564 0.1U_0402_10V6K~DC564 0.1U_0402_10V6K~D

12

C566 0.1U_0402_10V6K~DC566 0.1U_0402_10V6K~D

12

C568 0.1U_0402_10V6K~DC568 0.1U_0402_10V6K~D

12

C569 0.1U_0402_10V6K~DC569 0.1U_0402_10V6K~D

12

C570 0.1U_0402_10V6K~DC570 0.1U_0402_10V6K~D

12

Vgs <=1.5 V

DISP_HDDISP_HD

13

D

12

RU115

@RU115

@

110K_0402_1%~D

Follow Int el HPD des ign rev 1. 6

SW for MB side

RU96 100K_0402_5%~DRU96 100K_0402_5%~D

B B

DP_AUX<18>

DP_AUX#<18>

A A

1 2

CU33

0.1U_0402_10V7K~D

CU35

0.1U_0402_10V7K~D

RU97 100K_0402_5%~DRU97 100K_0402_5%~D

1 2

+3VS

DP_DDC_CLK<18> DP_DDC_DATA<18>

+3VS

RU55

2.2K_0402_5%~D

RU56

2.2K_0402_5%~D

DP_AUX_C

12

DP_AUX#_C

12

DP_DDC_CLK

12

DP_DDC_DATA

12

DP_DDC_CLK DP_DDC_DATA

1225 modify it.

U70

2

1A 2A51B

1

1OE#

7

2OE#

SN74CBTD3306CPW R_TSSOP8~D

U65

2

1A 2A51B

1

1OE#

7

2OE#

SN74CBTD3306CPW R_TSSOP8~D

DP_CA_DET# DP_CA_DET

DPB_CA_DET= 1 TMDS Signaling DPB_CA_DET= 0 DP Signaling

8

VCC

3 6

2B

4

GND

8

VCC

3 6

2B

4

GND

NC7SZ04P5X_NL_SC70-5~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/09/21 2010/09/21

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Display Port

NAT02 M/B LA-5154P Schematic

1

37 49Thursday, November 26, 2009

1.0

5

R e qu e st

Ite m

Ite m Issu e D escrip t io n

Ite mI t e m

P a ge# T itle

P a ge#Pa ge#

Title

TitleTitle

D ate

D ateD ate

R e qu e stR eq ues t

O w ner

O w nerO wn e r

4

V ersion C h ang e L ist ( P. I. R . L ist )

V ersion C h ang e L ist ( P. I. R . L ist )V ersion C h ang e L ist ( P. I. R . L ist )

Issu e D escrip t io nD ate

Issu e D escrip t io nI ssu e D es c rip tio n

3

Pag e 1

Pag e 1Pag e 1

2

So l u tion D esc r ip tio n

So l u tion D esc r ip tio n R e v.

So l u tion D esc r ip tio nS o lu tio n D escr ip tio n

1

R e v.P a ge#

R e v.R e v.

01 08

D D

02 16

04 09

05 11

06 12

C C

07 20

08 33

09 15

10

24,31

11

12

B B

13

11,12

14

15

PROCESSOR (4/6) PWR,Bypass

PCH (2/9) PCIE, SMBUS, CLK

0603

26

33

35

+1.5V and resert

Separate +1.5V power

VrefDQ

DDR_RST_GATE

VDDQ

GPIO1D

Sub woofer / Speaker AMP

PROCESSOR (2/6) CLK,JTAG

6

DC/DC Interface

VGA / LVDS

2009/08/10 Compal

2009/08/18 Compal

2009/08/25 Compal

2009/08/25

2009/08/25 Compal

Compal2009/07/22

Compal2009/08/25

Compal

Design change for IMVP6.5 current gain

XTAL25_IN should be pulled to GND using a 0Ω resistor. Pop C1027 with a 0 ohm resister

Reduce S3 state Power Add U63,Q36,R290,R310,R1103,R1136,C1142

Reduce S3 state Power Add PJP12,PJP13,PJP14,C1033,C1143,C1144,C1145

VrefDQ should be Maintained within SPEC during S3 Add Q37,R313

VrefDQ should be Maintained within SPEC during S3 Add Q44,R321

DDR_RST_GATE from GPIO46 Add GPIO46

Processor VDDQ should be turned off in S3 Add Q73,Q11,R346,R349,R1158,C534,C536

ADD EC GPIO1D to PCH GPIO33 Add GPIO33

Reserve Subwoofer delay circuit for mute Reserve D60, R1568, C1558

Follow crystal vendor's recommend

Intel S3 solution disable POP R1054,R1055,R1121; Depop Q36,R290,R1103

Intel S3 solution disable

to improve +LCDVDD voltage quality. Pop C550

R343 un-pop,R1072 pop,R1074 pop,R1073 unpop,R1075 pop,R1076 un-pop

C318,C319,C479,C481 BOM change to SE071330J8L (S CER CAP 33P 50V +-5% NPO 0402)

Depop Q37,Q44,R56

Depop Q73 Q73 BOM change to SB000001Y8L R358 BOM change to SD013470080 (S RES 1/10W 470 +-5% 0603)

Rev02 (X01)

16

17 31

18

19

20

A A

EC_KB926/BIOS/Reed SW

31

EC_KB926/BIOS/Reed SW

35

20

30

5

2009/08/25 Compal

Compal2009/09/01

2009/09/21 Compal

Board ID change R312 BOM change to 8.2K

Reserve a 0ohm resister on SUS_PWR_ACK from PCH to EC Reserve R1569 on SUS_PWR_ACK

In common with MV

S3 POWER Reduction update from Intel Reserve C1559 on DDR_RST_GATE

Reserve common choke on USB0

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/09/21 2010/09/21

Q71 BOM change to SB00000960L

Reserve L89,R1571,R1572

Compal Secret Data

Deciphered Date

Rev02 (X01)

Rev03 (X02)

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

HW PIR

NAT02 M/B LA-5154P Schematic

38 49Thursday, November 26, 2009

1

1.0

5

R e qu e st

Ite m

Ite m Issu e D escrip t io n

Ite mI t e m

D D

P a ge# T itle

P a ge#Pa ge#

01

02

30

33

ESATA

Title

TitleTitle

D ate

D ateD ate

2009/09/21 Compal

R e qu e stR eq ues t

O w ner

O w nerO wn e r

4

V ersion C h ang e L ist ( P. I. R . L ist )

V ersion C h ang e L ist ( P. I. R . L ist )V ersion C h ang e L ist ( P. I. R . L ist )

Issu e D escrip t io nD ate

Issu e D escrip t io nI ssu e D es c rip tio n

Add ESATA re-driver

3

2

Pag e 1

Pag e 1Pag e 1

So l u tion D esc r ip tio n

So l u tion D esc r ip tio n R ev.

So l u tion D esc r ip tio nS o lu tio n D escr ip tio n

Unpop R1164,R1165,R1166,R1167,R949,R950,R951,R952 pop JP13,C941,C944,C942,C943

Q55,Q73 BOM change to SB00000DA0L

1

R e v.P a ge#

R e v.R e v.

Rev03 (X02)

03

04

05

06

07

08

09

C C

10

11

12

13

14

15

16

17

B B

18

8

25

26

37

22

11,12

31

17

19

31

32

36

30

27

9

26

HD Audio_IDT92HD73C

Sub woofer/Speaker AMP

Display Port

PCH (8/9) PWR

DDRIII SO-DIMM

EC

PCH

EC

Touch Screen

HDMI

Camera

WLAN

PWR Intel sugg est to red uce GFX vo ltage ove rshoot

Sub woofer/Speaker Amp

2009/09/21 Compal

2009/10/08 Compal

2009/10/12 Compal

2009/10/15 Compal

2009/10/16 Compal

2009/10/22 Compal

2009/11/02 Compal

Compal2009/11/24

2009/11/02 Compal

2009/11/05 Compal

2009/11/16 Compal

BOM reason C1009,C1010 BOM change to SGA00002U1L

BOM change for C336,C337,C354,C355

implement Subwoofer delay circuit for mute Pop D60,C1558 R1568 change to 330K

Follow Int el HPD des ign

Follow Int el design Add LU9,CU64,CU65,CU66

Add M3 sol ution Pop R166,R178

Bom reason Change U2 SA007080B9 0 to SA007 080100

Design fol low NAT01 Change R11 39 SD02810 038L to SE 000000K8L

Change Boa rd ID Change R312 S D02882018L to SD0281 8028L

Add for To uch Screen issue

improve 88 8MHZ noise Add C458,C 459

for EC deb ug pin Add R323 1 00K pull d own

Follow NAT 01 design Change C92 2 & C1102 to 0.1uF

remove RU98,RU99;add RU115; change QU4 to SB50138008L

Add R322 4 7K ohm pul l highFor ENE is sue

Add R1236

Unpop RU28 ,RU32 , Po p RU30,RU3 3For HDMI D eep color mode

Change RU9 3 to 470oh m

Rev03 (X02)

Rev10 (A00)

19

20

21

22

23

24

25

A A

31

36

EC

HDMI

5

2009/11/19 Compal

2009/11/24 Compal

2009/11/24

2009/11/24 Compal

Compal

Change Boa rd ID Change R312 S D02818028L to SD0283 3028L

Change HDM I level sh ift Change U63 to SA0000 3GT00

For HDMI D eep color mode

For HDMI L evel shift ASM1442 Change RU2 9 to 3.4K for ASM144 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/09/21 2010/09/21

Add RU25 4 .7K pull d own for AS M1442

Reserve RU 37 4.7K pu ll high fo r ASM1442

Compal Secret Data

Deciphered Date

2

Rev10 (A00)

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

HW PIR

NAT02 M/B LA-5154P Schematic

1

39 49Thursday, November 26, 2009

1.0

5

7

6

5

D D

C C

5

4

3

2

1

MOLEX_87438-0743

PJPDC1

@PJPDC1

@

12

PL2

BLM18BD102SN1D_0603~D

DOCK_PSIDPSID

12

PC2

100P_0402_50V8J~D

4

ADPIN

PL1

PC5

1 2

1000P_0402_50V7K~D

PL1

12

PC6

100P_0402_50V8J~D

FBMA-L18-453215-900LMA90T_1812~D

12

PC3

1000P_0402_50V7K~D

12

PC4

100P_0402_50V8J~D

3

VIN

12

PC7

1000P_0402_50V7K~D

DOCK_PSID

2

1

3

PD5

@PD5

@

SM24_SOT23

PR18

1 2

100K_0402_1%~D

PR20

1 2

15K_0402_1%~D

2

PR15

@PR15

@

1 2

0_0402_5%~D

D

1 3

G

2

C

PQ3

2

B

MMST3904-7-F_SOT323~D

E

3 1

PD4

PR17

33_0402_5%~D

S

1 2

PQ2

PQ2 FDV301N_NL_SOT23-3~D

FDV301N_NL_SOT23-3~D

1

+3VALW+5VALW

2

3

DA204U_SOT323~D

1

+5VALW

12

PR19

10K_0402_1%~D

PR21

@PR21

@

1 2

10K_0402_1%~D

PR16

1 2

2.2K_0402_5%~D

+5VALW

2

3

PD6

@

DA204U_SOT323~D

1

PS_ID <31>

VIN

PD2

PJP1

PD3

BATT+

B B

51ON#<32>

RTCVREF

12

PC13

A A

PC13

4.7U_0805_6.3V6K~D

5

PU3

3

OUT

4

5/3+

12

RLS4148_LL34-2

CHGRTCP

PR11

100K_0402_5%~D

PR12

22K_0402_5%~D

1 2

1

IN

MAX1615_#SHDN

5

#SHDN

GND

MAX1615EUK+_SOT23-5~D

2

12

MAX1615_IN

PJP1 JUMP_43X118@

JUMP_43X118@

112

1 2

PC11

0.22U_0603_25V7K~D

1 2

PR14 0_0402_5%~DPR14 0_0402_5%~D

2

TP0610K-T1-E3_SOT23-3

27.4

12

4

1 2 12

68_1206_5%~D

PQ1

13

12

PC14

PC14 1U_0805_25V4Z~D

1U_0805_25V4Z~D

PD2

RLS4148_LL34-2

PR10

PC12

0.1U_0603_25V7K~D

12

PR13

PR13 200_0805_5%

200_0805_5%

12

PR208

68_1206_5%~D

VS

PC194

@

.1U_0402_16V7K~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

VIN

12

PR191

@PR191

@

82.5K_0402_1%~D

PR193

@PR193

@

22K_0402_1%~D

1 2

12

PR206

+

-

19.6K_0402_1%~D

8

@ PU 17B

@

P

G

4

O

LM393DR_SO8

12

PU17B

7

Compal Secret Data

12

@

32.3

5

6

2009/09/21 2010/09/21

PC193

@

2200P_0402_50V7K~D

1 2

VinDe_IN3N41

VinDe_Ref

PC191

@PC191

@

1000P_0402_50V7K~D

@PR204

@

56K_0402_5%~D

1 2

PR202

@ PR2 02

@

1M_0402_1%~D

1 2

VS

8

3

P

+

2

-

G

LM393DR_SO8

4

PR201

@PR201

@

10K_0402_5%~D

12

PR204

PC192

@

O

PU17A

@PU17A

@

12

0.01U_0402_25V7K~D

1

RLZ4.3B_LL34

RTCVREF

@PD1

@

3.3V

Vin Detector

Max. typ. Min.

L-->H 18.234 17.841 17.449 H-->L 17.597 17.210 16.813

Deciphered Date

2

PD1

VIN

12

PR205

@PR205

@

10K_0402_5%~D

12

Title

Size Document Number Rev

Custom

Date: Sheet of

PR192

@PR192

@

1K_0402_5%~D

1 2

VinDe_Out

12

PR203

@PR203

@

10K_0402_5%~D

NAT02 M/B LA-5154P Schematic

ACIN <17,25,31,41>

Compal Electronics, Inc.

DCIN/Precharger

1

1.0

40 49Thursday, November 26, 2009

1.0

A

VIN

12

PR23

1 1

3.3_1210_5%~D

12

PR27

3.3_1210_5%~D

PC19

2.2U_0805_25V6K

1 2

PC16

0.01U_0603_50V7K~D

1 2

PQ4

8

D

7

D

6

D

5

D

FDS6675BZ_SO8

PR28

PR28 340K_0402_1%~D

340K_0402_1%~D

1 2

ACDET

1

S

2

S

3

S

4

G

CP setting

PR31

54.9K_0402_1%

1 2

CP_SEL<3 1>

PR34

PR34 340K_0402_1%~D

340K_0402_1%~D

1 2

OVPSET

2 2

PR35

54.9K_0402_1%

1 2

90W adapter

Icharge=(Vsrset/Vvdac)*(0.1/PR29)=3.3A

Iadapter=(Vacset/Vvdac)*(0.1/PR22)=4.16A

Input OVP : 22.3V

Input UVP : 16.98V

Fsw : 300KHz

3 3

PR46

1 2

B+

100_0805_5%~D

+5VALW

PR48

1 2

12

470K_0402_5%~D

PD8

1SS355TE-17_SOD323-2

PR52

1 2

220K_0402_5%

12

4 4

PC47

PR54

0.1U_0603_25V7K~D

470K_0402_5%~D

1 2

220K_0402_5%

A

2

G

TP0610K-T1-E3_SOT23-3

32.8

13

D

PQ15

PQ15 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

S

13

PQ12

PC44

CHGVADJ<31>

1 2

0.1U_0805_25V7M~N

CP_SEL

@

SI2301BDS-T1-E3_SOT23-3

PR36

100K_0402_1%~D

GATE

1 2

PC40

0.1U_0603_25V7K~D

ACGOOD#

PR44

210K_0402_1%~D

1 2

B+_BIAS

100K_0402_1%~D

ACOFF

1 2

PC45

.1U_0402_16V7K~D

REGN

12

1 2

PC25

0.022U_0603_50V7~D

0.022U_0603_50V7~D PC100 1000P_0603_50V7~D@PC100 1000P_0603_50V7~D@

PR37 1K_0603_5%~DPR37 1K _0603_5%~D

PQ25

2

G

12

PC190

0.1U_0402_10V7K~D

2

12

ACSET

12

PR45

PR45 499K_0402_1%~D

499K_0402_1%~D

VREF

12

PR50

12

340K_0402_1%~D

B

1 2 3 4

PR26

100K_0402_1%~D

12

PR89

PR89 143K_0402_1%~D

143K_0402_1%~D

1 2 13

D

S

PQ9

PR43

PR43 0_0402_5%~D@

0_0402_5%~D@

VADJ

2

G

PR53

B

PQ5

S

D

S

D

S

D

G

D

SI4459ADY_SO8

12

PR30

60.4K_0402_1%

+3VALW

SSM3K7002FU_SC70-3

1U_0603_10V6K~D

+3VALW

1 3

VREF

12

PR49

PR49 200K_0402_1%~D

200K_0402_1%~D

13

D

PQ14

PQ14 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

S

PR22

0.015_2512_1%

8 7 6

1

5

2

PC24

.1U_0402_16V7K~D

1 2

PC26

0.1U_0603_25V7K~D

ACDRV_CHG#

12

PR33

PR33 100K_0402_1%~D

100K_0402_1%~D

PC33

@ PC33

@

0.01U_0402_25V7K~D

VREF

PC39

1 2

PR87

0_0402_5%~D

GATE

13

D

PQ13

2

G

SSM3K7002FU_SC70-3

S

PR90 4.7_1206_5%~DPR90 4.7_1206_ 5%~D

4

3

CHGEN#

12

PC27

0.1U_0603_25V7K~D

ACN ACP

ACSET

1 2

PC34

0.47U_0603_16V7K~D

12

VADJ

/BATDRV

C

Issued Date

PVCC_CHG

PVCC

BTST

HIDRV

PH

REGN

LODRV

PGND

LEARN

CELLS

SRP

SRN

BAT

TP

SRSET

IADAPT

ADP_I<31>

+COINCELL

RTCVREF

2

PD9

BAT54CW_SOT323~D

C

B+

PJP17

2

112

JUMP_43X118@

PC20

0.022U_0603_50V7~D

1 2

28

PR25

2.2_0603_5%~D

1 2

27

DH_CHG

26

LX_CHG

25

PD7

RLS4148_LL34-2

REGN

24

12

PC29

PC29 1U_0603_10V6K~D

1U_0603_10V6K~D

DL_CHG

23

22

21

0_0402_5%~D

CELLS

1 2

20

SRP

19

SRN

18

17

12

PC41

0.1U_0603_25V7K~D

29

SRSET

16

1 2

15

PR39

10_0603_5%~D

PC43

100P_0402_50V8J~D

12

PR47

PR47 1K_0402_5%~D

1K_0402_5%~D

Z4012

3

+RTCVCC

1

PC46

PC46 1U_0603_10V4Z~D

1U_0603_10V4Z~D

2

2009/09/21 2010/09/21

FDS8884_SO8

1 2

12

0.1U_0603_25V7K~D

FDS6690AS_NL_SO8

ACOFF <31>

PR88

ICHG setting

12

PR40

PR40 100K_0402_1%~D

100K_0402_1%~D

12

Compal Secret Data

578

PQ6

3 6

241

PC28

578

PQ8

3 6

241

51.1K_0402_1%~D

12

@PC42

@

0.01U_0402_25V7K~D

IREF Current

3.3V 3.3A

COIN RTC Battery

+COINCELL

Deciphered Date

12

PU4

1

CHGEN

2

ACN

3

ACP

4

ACDRV

5

ACDET

6

ACSET

7

ACOP

8

OVPSET

9

AGND

10

VREF

PR86

PR86 0_0402_5%~D@

0_0402_5%~D@

11

VDAC

12

VADJ

13

ACGOOD

14

BATDRV

BQ24751ARHDR_QFN28_5X5

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PC1892200P_0402_5 0V7K~D PC 1892200P_0402_50V7K~D

PR38

12

PC42

PJPRTC

@PJPRTC

@ 1 2 3 4

MOLEX_53398-0271_2P

D

CHG_B+

PC1880.1U_0603_25V7K~D PC 1880.1U_0603_25V7K ~D

12

10U_919AS-100M-P3_4.5A_20%

12

PR32

4.7_1206_5%~D

12

PC35

680P_0603_50V7K~D

IREF <31>

1 2 G1 G2

D

PC234.7U_0805_25V6K~D P C234.7U_0805_25V6K~D

1 2

PL3

1 2

E

12

PR24

PR24 100K_0402_1%~D

PC224.7U_0805_25V6K~D P C224.7U_0805_25V6K~D

PC214.7U_0805_25V6K~D P C214.7U_0805_25V6K~D

1 2

PC30

1 2

10U_1206_25V6M~D

12

PC37

0.1U_0603_25V7K~D

47K_0402_1%~D

FSTCHG<31>

Title

Size Document Number Rev

B

Date: Sheet of

PC181000P_0402_50V7K ~D PC181000P_0402_5 0V7K~D

PC171000P_0402_50V7K ~D PC171000P_0402_5 0V7K~D

12

PR29

0.02_2512_1%

1

2

PC36

.1U_0402_16V7K~D

1 2

RTCVREF

12

PR41

ACGOOD#

NAT02 M/B LA-5154P Schematic

2

G

2

G

Compal Electronics, Inc.

Charger

1 2

PC15

/BATDRV

4

3

VREF

1 2

13

D

S

VREF

1 2

13

D

S

100K_0402_1%~D

0.01U_0402_25V7K~D

12

PC38

0.1U_0603_25V7K~D

PR42

47K_0402_1%~D

PQ11

PQ11 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

PR51

PR51 47K_0402_1%~D

47K_0402_1%~D

CHGEN#

PQ16

PQ16 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

E

5

3G4

S1S2S

PQ7

D8D7D6D

FDS6675BZ_SO8

BATT+

12

PC31

PC32

10U_1206_25V6M~D

ACIN <17,25,31,40>

41 49Thursday, November 26, 2009

1.0

5

4

3

2

1

B+

PL23

D D

+3VALWP

PC60

330U_D_ 6.3VM_R18M~D

C C

B+

B B

PR91

100K_0402_5%~D

@

PR93

@P R93

@

100K_04 02_5%~D

1 2

VS

+5VALW P

A A

+3VALW P

1 2

FBMA-L18 -453215-900LMA 90T_1812

1

12

+

PC79

2

0.1U_0402_10V7K~D

PQ24

@

TP0610K -T1-E3_SOT23-3

2 12

@

13

2

13

PR92

100K_0402_5%~D

PQ10

@P Q10

@

DTC115E UA_SC70-3

VS

+5VALW

+3VALW

12

2

PJP5

PJP5 JUMP_43 X118@

JUMP_43 X118@

112

PJP7

PJP7 JUMP_43 X118@

JUMP_43 X118@

112

PJP11

PJP11 JUMP_43 X118@

JUMP_43 X118@

112

PJP9

PJP9 JUMP_43 X118@

JUMP_43 X118@

112

5

12

PC84

0.1U_0603_25V7K~D

2.2UH_MP LC1040L2R2_1 1A_20%~D

PR57

0_0402_5%~D

1 2

PR62

@

1 2

10K_0402_1%~D

PJP24

@P JP24

@

2 1

PAD-OPEN 2x2m~D

1 2

PD17

@P D17

@

1SS355T E-17_SOD323-2

PC48

1 2

4.7U_0805_25V6K~D

PL4

1 2

PC49

1 2

4.7U_0805_25V6K~D

PD10

RLZ5.1B_ LL34

1 2

1 3

PC50

3.3VALWP Thermal Design Current=8.5A OCP min=11A Fsw=300K

Rds(on) = 11.5m ohm(max) Rds(on) = 9m ohm(typical)

12

2200P_0402_50V7K~D

PR56

4.7_1206_5%~D

PC58

680P_0603_50V7K~D

2

1 2

PD11

PD11 1SS355T E-17_SOD323-2

1SS355T E-17_SOD323-2

TPS51427_B+

578

3 6

241

8

12

TP0610K -T1-E3_SOT23-3

S

2

1

PR66

100K_04 02_1%~D

1 2

<20,47>

MAINPW ON

PQ21

4

D6D5D7D

G

S

3

PR67

PQ17

PQ17 SI4686DY-T1-E3 _SO8

SI4686DY-T1-E3 _SO8

PQ19

PQ19 FDS6670 AS_NL_SO8

FDS6670 AS_NL_SO8

4

PC65

0.22U_06 03_25V7K~D

1 2

VL

200K_0402_5%~D

PR72

PR73

1 2

12

0_0402_ 5%~D

PR55

0_0805_ 5%

1 2

VL

PC54

0.1U_060 3_25V7K~D

PR59

1 2

2.2_0603 _5%~D

PC57

0.1U_060 3_25V7K~D

1 2

0.1U_060 3_25V7K~D

BST3A

LX3

DL3

FB3

VL

1 2

PU5

33

TP

26

UGATE2

24

BOOT2

25

PHASE2

23

LGATE2

30

OUT2

32

REFIN2

1 2

PC55

3

6

VIN

VCC

2VREF_TPS51427

TPS5142 7_EN2

1 2

PR71

1 2

12

2VREF_TPS51427

1

REF

8

LDOREFIN

20

NC

4

EN_LDO

14

EN1

27

EN2

TON

NC

2

5

0_0402_5%~D

12

@

PC66

1U_0603_10V6K~D

2009/09/ 21 2010/09/ 21

3

@

0_0402_ 5%~D

2VREF_TPS51427

1 2

PC64 0.22U_06 03_10V7K~DPC64 0.22U _0603_10V7K~ D

EN_LDO

TPS5142 7_EN1

PR70

@P R70

@

0_0402_ 5%~D

PR74

@P R74

@

47K_040 2_5%~D

806K_0603_1%

1 2

12

PC67

PC68

@

0.047U_0603_16V7K~D

0.047U_0402_16V7K~N

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

PC56

1U_0603_10V6K~D

7

4.7U_0805_6.3V6K~D

19

LDO

PVCC

15

UGATE1

17

BOOT1

16

PHASE1

18

LGATE1

22

PGND

10

OUT1

11

FB1

9

BYP

29

SKIP

28

POK2

13

POK1

12

ILIM1

31

ILIM2

GND

ISL6237IRZ-T_ QFN32_5X5

21

PR75

Compal Secret Data

Deciphered Date

PC59

1U_0603 _10V6K~D

1 2

DH5DH3

PR60

BST5A

1 2

2.2_0603 _5%~D

0.1U_060 3_25V7K~D

LX5

DL5

FB5

PR64 0_0402_5% ~D@ PR64 0_ 0402_5%~D@

PR65 0_0402_5% ~DPR65 0_0402_ 5%~D

1 2

ILM1

ILIM2

PC61

1 2

12

PR68

210K_04 02_1%~D

PR69

255K_04 02_1%~D

12

2

4

578

3 6

D6D5D7D

G

S

3

VL

PQ18

241

SI4686DY-T1-E3_SO8

8

PQ20

S

2

1

FDS6670AS_NL_SO8

5VALWP Thermai Design Current=6.88A OCP min=9A Fsw=400K

Rds(on) = 11.5m ohm(max) ; Rds(on) = 9m ohm(typical)

TPS51427_B+

12

PC52

PC51

1 2

4.7U_0805_25V6K~D

2.2UH_MP LC1040L2R2_1 1A_20%~D

12

PR58

4.7_1206_5%~D

12

PC62

680P_0603_50V7K~D

Title

Size Document Num ber Rev

Custom

NAT02 M/B LA-5154P Schematic

Date: Sheet of

PC53

1 2

2200P_0402_50V7K~D

4.7U_0805_25V6K~D

PL5

12

Compal Electronics, Inc.

+3VALWP/+5VALWP

12

PC197

0.1U_0603_25V7K~D

+5VALWP

PR61

1 2

61.9K_0402_1%~D

PR63

1 2

10K_0402_1%~D

42 49Thursday, November 26, 2 009

1

12

+

PC80

2

0.1U_0402_10V7K~D

PC63

330U_D_6.3VM_R18M~D

1.0

A

+1.05VSP Thermal Desig Current=5A OCP min=9A Fsw=300KHz

1 1

PR77

0_0402_5%~D

SUSP#<28,31,33, 44,45>

PR80

PR80 300_0603_5%~D

300_0603_5%~D

+5VALW

2 2

1 2

12

PR79

30.1K_0402_1%~D

12

PC76

1U_0603_10V6K~D

21.5K_0402_1%~D

12

@PC7 2

@

.1U_0402_16V7K~D

12

PR85

12

PC72

PC78

@PC7 8

@

47P_0402_50V8J~D

12

PR84

8.66K_0402_1%~D

TON_VCCP

V5FILT_VCCP

FB_VCCP

12

EN_VCCP

PU6

2

TON

3

VOUT

4

V5FILT

5

VFB

6

PGOOD

B

PR76

267K_0402_1%~D

1 2

1

EN_PSV

GND7PGND

PR78

BST_VCCP

1 2

2.2_0603_5%~D

14TP15

DRVH

TRIP

DRVL

UG_VCCP

13

LX_VCCP

12

LL

TRIP_VCCP

11

V5DRV_VCCP

10

9

VBST

V5DRV

TPS51117RGYR_QFN14_3. 5x3.5

8

1 2

PC71 0. 1U_0603_25V7K~DPC71 0.1U_0603_25V7K~D

PR81

1 2

10K_0402_1%~D

+5VALW

12

PR82

PR82 0_0603_5%~D

0_0603_5%~D

12

PC77

4.7U_0805_10V6K~D

C

4

578

G

VCCP_B++

3 6

241

D6D5D7D

S

3

2

PQ22

PQ22 SI4686DY-T1-E3_SO8

SI4686DY-T1-E3_SO8

8

PQ23

S

FDS6670AS_NL_SO8

1

12

PR83

4.7_1206_5%~D

12

680P_0603_50V7K~D

12

PC70

PC69

PC70

10U_1206_25V6M~D

PC75

10U_1206_25V6M~D

PL6

2.2UH_MPLC1040L2R2_11A_2 0%~D

PL6

1 2

D

PJP20

@PJ P20

@

12

PAD-OPEN 4x4m

12

PC85

12

PC86

2200P_0402_50V7K~D

0.1U_0603_25V7K~D

1

12

+

PC73

PC74

2

220U_D2_4VM

4.7U_0805_6.3V6K~D

B+

+1.05VSP

12

PC81

0.1U_0402_10V7K~D

PJP23

@PJ P23

@

JUMP_43X118

PJP10

@PJ P10

@

JUMP_43X118

3 3

4 4

+1.05VSP

+1.8VSP

JUMP_43X118

112

PJP25

@PJ P25

@

JUMP_43X118

112

PJP28

@PJ P28

@

JUMP_43X118

112

A

2

+1.05VS

+1.8VS

+3VALW

SUSP#<28,31,33,44,45 >

JUMP_43X118

112

1 2

PR95 0_04 02_5%~DPR95 0_0402 _5%~D

PC171

@PC1 71

@

0.1U_0402_16V7K~D

2

+5VALW

12

B

12

PC172

10U_1206_25V6M~D

5

PU13 RT9025PU13 RT9025

NC

ADJ

PGOOD

GND

8

Issued Date

6

7

1

1000P_0402_50V7K~D

2009/09/21 2010/09/21

12

PC87

+1.8VSP Thermal Desig Current=0.69A

Compal Secret Data

12

PR96

1K_0402_1%~D

12

PR97

806_0402_1%~D

Deciphered Date

C

12

PC126

VIN3VOUT

2

EN

4

VDD

GND

9

PC170

1U_0402_6.3V6K~D

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+1.8VSP

12

PC88

PC88 10U_1206_25V6M~D

10U_1206_25V6M~D

Compal Electronics, Inc.

Title

Size D ocument Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

+1.05VSP/+1.8VSP

NAT02 M/B LA-5154P Schematic

D

43 49Thursday, November 26, 2009

1.0

A

PL24

B+

1 1

2 2

1 2

FBMA-L18-453215-900LM A90T_1812

12

PC211

0.1U_0603_25V7K~D

0_0402_5%~D

SYSON<28,31,33>

1 2

PR225

12

PC212

2200P_0402_50V7K~D

12

0.1U_0603_25V7K~D

PC213

@PC2 17

@

12

10U_1206_25V6M~D

PC217

@

12

PC222

.1U_0402_16V7K~D

12

PC214

10U_1206_25V6M~D

0_0603_5%~D

6268_1.5VP

12

PC218

2.2U_0603_6.3V6K~D

PR222

6268_1.5VP_B+

6268_1.5VP

1.5V_PW RGD< 6>

12

PC224

68P_0402_50V8J~D

10K_0402_1%~D

3

VIN

4

VCC

5

EN

PC227

2200P_0402_50V7K~D

B

PR220

8

GND

COMP6FB7FSET

12

PR228

33K_0402_1%~D

12

2

1UG16

PHASE

PGOOD

PR229

45.3K_0402_1%~D

PHASE_1.5VP

9

12

PR221

1 2

2.2_0603_5%~D

BOOT_1.5VP

15

BOOT

14

PVCC

13

LG

12

PGND

11

ISEN

VO

PU19

10

ISL6268CAZ-T_SSOP16

12

PC228

0.01U_0402_25V7K~D

UG_1.5VP

1 2

+5VALW

12

PR223

0_0603_5%~D

PR224 4.7_0603_5%~DPR224 4.7_0603_5%~D

1 2

PC216

1 2

2.2U_0603_6.3V6K~D

LG_1.5VP

PR226

ISEN_1.5VP

1 2

3.01K_0402_1%~D

PC215

0.1U_0603_25V7K~D

6268_1.5VP

C

1.5VP Thermal Design Current=12.8A OCP min=16A Fsw=300KHz

PQ50

FDMS8692_POW ER56-8-5~D

PL15

3 5

241

PQ51

4

123 5

FDMS8670S_ POWER56-8~D

1UH_FDUE1040D-1R0M -P3_21.3A_20%

PQ52

123 5

FDMS8670S_ POWER56-8~D

PL15

1 2

12

PR227

4.7_1206_5%~D

12

PC223

680P_0603_50V7K~D

1.5K_0402_1%~D

PR230

1 2

D

+1.5VP

PC219

PC225

+1.5VP

12

PC220

10U_0805_6.3V6M~D

1

+

PC226

2

330U_Y_2.5VM

12

PC221

0.1U_0402_10V7K~D

10U_0805_6.3V6M~D

1

+

2

330U_Y_2.5VM

12

PR231

1K_0402_1%~D

3 3

PU10

RT9026_MSOP10

PJP18

@PJ P18

@

+1.5VP

+0.75VSP

PC141

PJP22

@PJ P22

@

JUMP_43X118

2

4 4

+1.5VP

+0.75VSP

112

PJP35

@PJ P35

@

JUMP_43X118

112

PJP21

@PJ P21

@

2 1

PAD-OPEN 2x2m~D

A

2

+1.5V

+0.75VS

112

JUMP_43X118

12

10U_0805_10V6K~D

2

12

PC142

10U_0805_10V6K~D

12

PC139

PC138

@

4.7U_0805_6.3V6K~D

B

RT9026_MSOP10

1

VDDQSNS

2

VLDOIN

3

VTT

5

VTTSNS

10

VIN

PC140

8

GND

6

VTTREF

PR130

9

S5

7

S3

PGND

GND

4

11

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

12

PR130

0_0402_5%~D

12

PR131

@PR1 31

@

0_0402_5%~D

12

PC144

@PC1 44

@

0.1U_0402_16V7K~D

2009/09/21 2010/09/21

PC140

1U_0603_10V6K~D

12

PC143

0.1U_0402_16V7K~D

1.5VS_DDR_PW RGD <33>

SUSP# <28,31,33, 43,45>

Compal Secret Data

Deciphered Date

C

+3VALW

12

+0.75VSP Thermal Design Current:0.7A Peak current:1A Vout=VDDQSNS/2=1.5V/2=0.75V

Compal Electronics, Inc.

Title

Size D ocument Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

+1.5VSP/+0.75VSP

NAT02 M/B LA-5154P Schematic

D

44 49Thursday, November 26, 2009

1.0

5

PL22

FBMA-L18-453215-900LMA90T_1812

B+

D D

C C

1 2

SUSP#<28,31,33,43,44>

12

PC229

0.1U_0603_25V7K~D

PR237

0_0402_5%~D

1 2

12

PC230

2200P_0402_50V7K~D

12

0.1U_0603_25V7K~D

12

PC231

10U_1206_25V6M~D

PC235

@PC235

@

12

PC240

@PC240

@

.1U_0402_16V7K~D

12

PC286

PC232

10U_1206_25V6M~D

6268_1.1VS_VTTP

12

PC236

2.2U_0603_6.3V6K~D

10U_1206_25V6M~D

12

PR234

PR234 0_0603_5%~D

0_0603_5%~D

<6>

H_VTTPWRGD

4

6268_1.1VS_VTTP_B+

6268_1.1VS_VTTP

2.7K_0402_1%~D

12

PC242

68P_0402_50V8J~D

PR232

9.31K_0402_1%~D

12

PR327

3

VIN

4

VCC

5

EN

12

PR240

12

PC245

2200P_0402_50V7K~D

12

2

1UG16

8

GND

PHASE

PGOOD

COMP6FB7FSET

33K_0402_1%~D

PR241

PHASE_1.1VS_VTTP

9

12

45.3K_0402_1%~D

PR233

1 2

2.2_0603_5%~D

BOOT_1.1VS_VTTP

15

BOOT

14

PVCC

13

LG

12

PGND

11

ISEN

VO

10

PU20

PU20 ISL6268CAZ-T_SSOP16

ISL6268CAZ-T_SSOP16

12

PC246

0.01U_0402_25V7K~D

3

UG_1.1VS_VTTP

1 2

+5VALW

12

PR235

0_0603_5%~D

PR236 4.7_0603_5%~DPR236 4.7_0603_5%~D

1 2

PC234

1 2

2.2U_0603_6.3V6K~D

LG_1.1VS_VTTP

ISEN_1.1VS_VTTP

1 2

PR238

4.75K_0402_1%~D

PC233

0.1U_0603_25V7K~D

6268_1.1VS_VTTP

2

1.1VS_VTTP Thermal Design Current=18A OCP min=24A Fsw=300KHz

PQ53

PQ53 FDMS8692_POWER56-8-5~D

FDMS8692_POWER56-8-5~D

PL16

3 5

241

PQ54

4

123 5

FDMS8670S_ POWER56-8~D

1UH_FDUE1040D-1R0M-P3_21.3A_20%

PQ55

123 5

FDMS8670S_ POWER56-8~D

PL16

1 2

12

PR239

4.7_1206_5%~D

12

PC241

680P_0603_50V7K~D

1.5K_0402_1%~D

PR242

+1.1VS_VTTP

12

PR305

10_0402_5%~D

1 2

12

PC237

PC238

10U_0805_6.3V6M~D

1

+

PC244

PC243

2

330U_Y_2.5VM

1

+1.1VS_VTTP

12

PC239

0.1U_0402_10V7K~D

10U_0805_6.3V6M~D

1

+

2

330U_Y_2.5VM

12

PR243

2K_0402_1%~D

B B

PJP31

PJP31 JUMP_43X118@

JUMP_43X118@

+1.1VS_VTTP

A A

2

112

PJP32

PJP32 JUMP_43X118@

JUMP_43X118@

2

112

PJP33

PJP33 JUMP_43X118@

JUMP_43X118@

2

112

5

+1.1VS_VTT

H_VTTVID1 = "High" , Vo = 1.05V H_VTTVID1 = "Low" , Vo = 1.1V

PR250

H_VTTVID1<8>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

PR250

1 2

10K_0402_5%~D

2009/09/21 2010/09/21

PR248

PR248 10K_0402_5%~D

10K_0402_5%~D

1 2

12

PC248

1 2

0.01U_0402_16V7K~D

Compal Secret Data

Deciphered Date

PQ57

2

G

PR251

PR251 100K_0402_5%~D

100K_0402_5%~D

+3VS

PR246

PR246 10K_0402_5%~D

10K_0402_5%~D

1 2

13

D

SSM3K7002FU_SC70-3

S

2

PR249

1 2

10K_0402_5%~D

PR247

17.8K_0402_1%~D

1 2

PQ56

13

D

2

G

SSM3K7002FU_SC70-3

S

PC247

0.068U_0402_16V7K~D

1 2

Title

Size Document Number Rev

Custom

NAT02 M/B LA-5154P Schematic

Date: Sheet of

PR244

1 2

0_0402_5%~D

PR245

@PR245

@

1 2

17.8K_0402_1%~D

Compal Electronics, Inc.

+1.1VS_VTTP

1

VTT_SENSE <8>

H_VTTVID1 <8>

45 49Thursday, November 26, 2009

1.0

8

H H

CPU_VID0<8>

CPU_VID1<8>

CPU_VID2<8>

CPU_VID3<8>

CPU_VID4<8>

CPU_VID5<8>

CPU_VID6<8>

G G

H_DPRSLPVR<8>

CLK_ENABLE#<13>

F F

E E

12

PR278

249K_0402_1%~D

@ PR278

@

D D

150P_0402_50V8J~D

Layout Note: PH3 place near Phase1 L-MOS

C C

B B

+CPU_CORE

PR252 0_0402_5%~DPR252 0_0402_5%~D

PR253 0_0402_5%~DPR253 0_0402_5%~D

PR254 0_0402_5%~DPR254 0_0402_5%~D

PR255 0_0402_5%~DPR255 0_0402_5%~D

PR256 0_0402_5%~DPR256 0_0402_5%~D

PR257 0_0402_5%~DPR257 0_0402_5%~D

PR258 0_0402_5%~DPR258 0_0402_5%~D

PR260 0_0402_5%~DPR260 0_0402_5%~D

VR_ON<31>

PR261 499_0402_1%~DPR261 499_0402_1%~D

+3VS

PR269

PR269 0_0402_5%~D

0_0402_5%~D

VGATE<13,17,31>

1 2

PR272

1 2

147K_0402_1%~D

+1.1VS_VTT

H_PROCHOT#<6>

PC259 56P_0402_50V8~D@PC259 56P_0402_50V8~D@

1 2

PR276 4.02K_0402_1%~DPR276 4.02K_0402_1%~D

1 2

470K_0402_5%_ERTJ0EV474J~D

12

PR279

8.06K_0402_1%~D

1 2

PC264

10P_0402_50V8J~D

1 2

PC265

412K_0402_1%~D

PR289 10_0402_5%~DPR289 10_0402_5%~D

VCCSENSE <8>

PR292 0_0402_5%~DPR292 0_0402_5%~D

VSSSENSE<8>

PR265

1.91K_0402_1%~D

12

+1.1VS_VTT

H_PSI#<8>

PR273 68_0402_5%~DPR273 68_0402_5%~D

PR274 0_0402_5%~DPR274 0_0402_5%~D

PC261

1 2

1000P_0402_50V7K~D

ISEN2

ISEN1

PR285

1 2

PR302 0_0402_5%~DPR302 0_0402_5%~D

1 2

PR268

1.91K_0402_1%~D

PR270 100K_0402_5%~D@ PR270 100K_0402_5%~D@

PR271 0_0402_5%~DPR271 0_0402_5%~D

1 2

12

PH4

PR280

562_0402_1%~D

390P_0402_50V7K~D

PR282

3.4K_0402_1%~D

1 2

PR284 0_0402_5%~DPR284 0_0402_5%~D

1 2

PR286 0_0402_5%~DPR286 0_0402_5%~D

PR303 10_0402_5%~DPR303 10_0402_5%~D

1 2

22P_0402_50V8J~D

PC263

1 2

330P_0402_50V7K~D

1000P_0402_50V7K~D

H_PROCHOT#_R

1 2

PC260

12

PC266

PC279

PC281

0.22U_0402_10V6K~D

7

CLK_ENABLE#

PU21

1

PGOOD

2

PSI#

3

RBIAS

4

VR_TT#

5

NTC

6

VW

7

COMP

8

FB

9

ISEN3

10

ISEN2

41

AGND

12

PC267

0.22U_0402_10V6K~D

12

1200P_0402_50V7K~D

39

40

CLK_EN#

ISEN111VSEN12RTN13ISUM-14ISUM+15VDD

PC282

330P_0402_50V7K~D

PC284

@PC284

@

DPRSLPVR

PR290

38

VR_ON

37

12

1 2

35

VID4

VIN

IMON18BOOT119UGATE1

17

16

12

PC268

1U_0603_10V6K~D

82.5_0402_1%~D

PC280

0.01U_0402_16V7K~D

PR298

1.15K_0402_1%~D

1 2

PR304

@PR304

@

100_0402_1%~D

VID031VID132VID233VID334VID536VID6

BOOT2 UGATE2 PHASE2

VSSP2

LGATE2

PWM3

LGATE1

VSSP1

PHASE1

20

12

6

OCP calculation : Assume DCR=0. 88mOhm G1=Rn/(Rn+Rsum/ 3), where Rn=PR224/ /(PR171+PH5); R sum=PR143,PR215 DROOP=2*(DCR/2) *G1*Rdroop/Ri=1 .896mOhm where Rdroop=PR 161;Ri=PR212 Iocp=42.7u*Rdro op/DROOP=~68A.

PC258

PC258 1U_0603_10V6K~D

1U_0603_10V6K~D

1 2

30 29 28 27 26

PR277 0_0402_5%~DPR277 0_0402_5%~D

25

VCCP

24 23 22 21

ISL62883HRZ-T_QFN40_5X5~D

12

PC262

PR283 0_0402_5%~DPR283 0_0402_5%~D

1 2

PR287 1_0402_5%~DPR287 1_0402_5%~D

1 2

PC269

12.1K_0402_1%~D

0.22U_0603_25V7K~D

12

PC277

PC276

2700P_0402_50V7K~D

0.33U_0603_10V7K~D

PR299

0_0402_5%~D

1 2

1U_0603_10V6K~D

+CPU_B+

+5VS

PR288

VSSSENSE

12

PC278

0.022U_0603_25V7K~D

12

PR300

PC285

PR275

PR275 0_0402_5%~D

0_0402_5%~D

1 2

PR281 0_0402_5%~DPR281 0_0402_5%~D

1 2

IMVP_IMON<8>

12

PC270

0.033U_0603_16V7K~D

VSUM+

12

PR293

2.87K_0402_1%~D

12

PH5

PH5 10K_0603_1%_ERTJ1VG103FA~D

10K_0603_1%_ERTJ1VG103FA~D

1 2

Layout Note:

11K_0402_1%~D

Place near Phase1 Choke

5

BOOT2 BOOT2_2

+5VS

BOOT1

VSUM-

PR259

2.2_0603_5%~D

UGATE1

PHASE1

LGATE1

12

LGATE2

PR291

2.2_0603_5%~D

0.22U_0603_10V7K~D

1 2

UGATE2

BOOT1_1

12

4

PC256

PC275

0.22U_0603_10V7K~D

1 2

3

+CPU_B+

12

PC249

PQ58

4

2

G

2

4

123 5

FDMS8692_POWER56-8-5~D

3

D

S

1

4

G

3

2

G

1

PQ59

FDMS8670S_ POWER56-8~D

PQ61

4

123 5

FDMS8692_POWER56-8-5~D

3

D

2

S

1

PQ62

FDMS8670S_ POWER56-8~D

PC249

PQ64

0.1U_0603_25V7K~D

123 5

FDMS8692_POWER56-8-5~D

PHASE2

D

PR262

4.7_1206_5%~D

S

PQ60

FDMS8670S_ POWER56-8~D

PC257

680P_0603_50V7K~D

PQ65

PC271

0.1U_0603_25V7K~D

123 5

FDMS8692_POWER56-8-5~D

3

D

G

S

PC283

1

PQ63

FDMS8670S_ POWER56-8~D

PC251

PC250

10U_1206_25V6K~D

2200P_0402_50V7K~D

12

PR263

3.65K_0603_1%~D

12

VSUM+

ISEN2

12

PC273

PC272

10U_1206_25V6K~D

2200P_0402_50V7K~D

12

PR294

4.7_1206_5%~D

12

PR295

680P_0603_50V7K~D

VSUM+

2

12

PC287

PC252

10U_1206_25V6K~D

PL18

0.36UH_ETQP4LR36ZFC_28A_20%~D

4

3

12

PR267

@ PR267

@

PR266

0_0402_5%~D

1 2

10K_0402_5%~D

+CPU_B+

12

PC274

10U_1206_25V6K~D

PL19

0.36UH_ETQP4LR36ZFC_28A_20%~D

4

3

12

PR296

3.65K_0603_1%~D

3.65K_0603_1%~D 10K_0402_5%~D

10K_0402_5%~D

ISEN1

FBMA-L18-453215-900LMA90T_1812~D

1 2

1

+

PC253

2

100U_25V_M~D

1

2

1

2

PR301

@ PR301

@

0_0402_5%~D

1 2

V1N

1

+

PC255

PC254

@

2

100U_25V_M~D

Iccmax= TBD I_TDC=TDB OCP=68A, Intel spec=TDB

V2N

VSUM-

V1N

V2N

VSUM-

PL17

+CPU_CORE

12

PR264

PR264 1_0402_5%~D

1_0402_5%~D

+CPU_CORE

12

PR297

PR297 1_0402_5%~D

1_0402_5%~D

1

B+

.1U_0402_16V7K~D

A A

8

7

6

.1U_0402_16V7K~D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

5

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

4

2009/09/21 2010/09/21

Compal Secret Data

Deciphered Date

3

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet of

2

Compal Electronics, Inc.

+CPU_CORE

NAT02 M/B LA-5154P Schematic

46 49Thursday, November 26, 2009

1

1.0

5

4

3

2

1

Battery Connect/OTP

+3VALWP

D D

2

3

PD12

@

1 2

PR179

PR180

@

PR175

PR175 1K_0402_5%~D

1K_0402_5%~D

DA204U_SOT323~D

1

BATT_B/I

BATT_SMD

BATT_SMC

EC_SMB_DA1 <31>

EC_SMB_CK1 <31>

BATT+

PL13

FBMA-L18-453215-900LMA90T_1812~D

BATT+

12

PC161

100P_0402_50V8J~D

PJPB1 battery connector

SMART

SMARTSMART Battery:

Battery:

Battery:Battery:

C C

9.BAT+

9.BAT+9.BAT+

8.BAT+

8.BAT+8.BAT+

7.ID

7.ID7.ID

6.B/I

6.B/I6.B/I

5.TS

5.TS5.TS

4.SMD

4.SMD4.SMD

3.SMC

3.SMC3.SMC

2.GND

2.GND2.GND

1.GND

1.GND1.GND

PL13

1 2

PC163

0.01U_0402_25V7K~D

SUYIN_200275MR009F50PZR~D

BATT++

12

PC162

PC162 1000P_0402_50V7K~D

1000P_0402_50V7K~D

GND GND

PJPB1

9 8 7 6 5 4 3 2 1

BATT++

12

PC164

100P_0402_50V8J~D

11 10 9 8 7 6 5 4 3 2 1

1 2

100_0402_5%~D

1 2

100_0402_5%~D

3

PD13

@

DA204U_SOT323~D

PR177

1K_0402_5%~D

12

2

1

3

PD14

@

DA204U_SOT323~D

@

1

Place clsoe to EC pin

BATT_TEMP

1 2

PR176

1K_0402_5%~D

1 2

PR178

6.49K_0402_1%~D

2

3

PD15

DA204U_SOT323~D

1

BATT_TEMP <31>

PC165

@PC165

@

.1U_0402_16V7K~D

+3VALWP

1000P_0402_50V7K~D

PC168

PH3 under CPU botten side :

CPU thermal protection at 90 +-3 degree C Recovery at 50 +-3 degree C

VL VS

12

CPU

12

PR182

10.7K_0402_1%~D

PR186

61.9K_0402_1%~D

OTP_IN OTP_IN+

61.9K_0402_1%~D

1 2

VL

PR188

12

PH3

PH3 100K_0402_1%_NCP15WF104F0 3RC

100K_0402_1%_NCP15WF104F0 3RC

PR188

150K_0402_1%~D

PR190

150K_0402_1%~D

CPU

PR184

147K_0402_1%~D

1 2

OTP_IN-

12

8

3

P

+

0

2

-

G

PU12A

4

LM358ADR_SO8

PC169

PC169 1U_0603_10V6K~D

1U_0603_10V6K~D

PC166

0.1U_0603_25V7K~D

1 2

OTP_OUT

1 2

1

1SS355TE-17_SOD323-2

PD16

VL

PR185

PR185 205K_0402_1%~D

205K_0402_1%~D

1 2

MAINPWON <20,42>

BATT+

12

PR181

PR181 453K_0402_1%~D

0.01U_0402_25V7K~D

4

453K_0402_1%~D

12

PR183

499K_0402_1%~D

BATT_IN

12

PR189

86.6K_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/09/21 2010/09/21

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

BATTERY CONN

NAT02 M/B LA-5154P Schematic

1

47 49Thursday, November 26, 2009

1.0

B B

BATT_OUT

BATT_OVP<31>

A A

5

1 2

PR187

10K_0402_1%~D

7

PU12B

LI-3S :13.5V----BATT_OVP=1.126V

BATT_OVP=0.08338*BATT+

0

VS

8

LM358ADR_SO8

5

P

+

6

-

G

4

12

PC167

5

PL20

1 2

B+

10_0402 _5%~D

1 2

10_0402 _5%~D

PL20

PR211

PR213

100P_04 02_50V8J~D

12

PC300

2200P_0402_50V7K~D

PR306

9.76K_04 02_1%~D

PR309

12

4.87K_04 02_1%~D

PC200

GFX_B+

12

PC301

PC289

10U_1206_25V6M~D

1 2

PC298

PC298 1000P_0 402_50V7K~D

1000P_0 402_50V7K~D

1 2

PC299

330P_04 02_50V7K~D

PR307

825K_04 02_1%~D

12

1 2

15P_040 2_50V8J~D

12

PC290

10U_1206_25V6M~D

12

1 2

PC177

68P_040 2_50V8J~D

PC182

1 2

GFXVR_P WRGD<31>

12

PC292

0.1U_0603_25V7K~D

PC174

PC174 330P_04 02_50V7K~D

330P_04 02_50V7K~D

PC178

1000P_0 402_50V7K~D

1 2

12

PR310

8.06K_04 02_1%~D

FBMA-L18 -453215-900LMA 90T_1812~D

D D

VSS_AXG _SENSE<9>

VCC_AXG _SENSE<9>

+VGFX_C ORE

C C

B B

4

0_0603_ 5%~D

1_0603_ 5%~D

+5VALW

PR215

47K_040 2_1%~D

+VGFX_C ORE

PR209

12

PC294

PC294 1U_0603 _10V6K~D

1U_0603 _10V6K~D

7

VSEN

6

FB

5

COMP

4

VW

3

RBIAS

2

PGOOD

1

CLK_EN#

29

0_0603_ 5%~D

ISUM+

ISUM-

10

9

8

RTN

ISUM

AGND

PU22

PU22 ISL62881H RZ-T_QFN28_4X 4

ISL62881H RZ-T_QFN28_4X 4

28

12

PR314

10K_0402_1%~D

ISUM+

VID626VR_ON27DPRSLPVR

PR326

11

25

3

1 2 12

12

13

VIN

VDD

IMON

VID5

VID323VID4

24

PC295

0.22U_0603_25V7K~D

BST_GFX

14

BOOT

UGATE

PHASE

VSSP

LGATE

VCCP

VID0

VID1

VID2

22

12

PR210

24K_0402_1%~D

PR212

1 2

2.2_0603 _5%~D

DH_GFX

15

LX_GFX

16

17

DL_GFX

18

19

20

21

GFXVR_IMO N <9>

12

PC296

0.033U_0603_16V7K~D

0.33U_06 03_10V7K~D

1 2

PR217

0_0603_ 5%~D

1 2

12

PC179

0.22U_04 02_10V5K~D

1 2

VSS_AXG _SENSE <9>

PC297

4

+5VALW

4

PR3130_04 02_5%~D PR3130_ 0402_5%~D

PR3150_04 02_5%~D PR3150_ 0402_5%~D

PR3160_04 02_5%~D PR3160_ 0402_5%~D

PR3170_04 02_5%~D PR3170_ 0402_5%~D

PR3180_ 0402_5%~D PR3180_0 402_5%~D

PR3190_ 0402_5%~D PR3190_0 402_5%~D

PR3200_ 0402_5%~D PR3200_0 402_5%~D

PR3230_ 0402_5%~D PR3230_0 402_5%~D

PR3250_ 0402_5%~D PR3250_0 402_5%~D

2

PQ43

4

123 5

FDMS8692_POWER56-8-5~D

PQ44

4

FDMS8670S_ POWER56-8~D

123 5

GFXVR_V ID_0 <9>

GFXVR_V ID_1 <9>

GFXVR_V ID_2 <9>

GFXVR_V ID_3 <9>

GFXVR_V ID_4 <9>

GFXVR_V ID_5 <9>

GFXVR_V ID_6 <9>

GFXVR_E N < 9>

GFXVR_D PRSLPVR <9>

1

PJP36

+VGFX_C OREP +VGFX_CORE

PQ46

@

2

JUMP_43 X118

@

PJP37

2

JUMP_43 X118@

112

123 5

FDMS8692_POWER56-8-5~D

12

PR216

PQ45

12

FDMS8670S_ POWER56-8~D

PC180

123 5

680P_0603_50V7K~D

ISUM+

ISUM-

PL21

0.45UH_E TQP4LR45XFC_ 25A_20%

4

3

12

PR218

3.65K_08 05_1%~D

4.7_1206_5%~D

1 2

PR308

2.61K_04 02_1%~D

0.1U_040 2_10V7K~D

PR324

82.5_040 2_1%~D

1 2

1

2

1 2

10KB_06 03_5%_ERTJ1V R103J

PR311

1 2

11K_040 2_1%~D

PC183

0.22U_04 02_10V5K~D

1 2

PC184

@P C184

@

1 2

PR321

1.87K_04 02_1%~D

1 2

PC185

0.01U_04 02_16V7K~D

PH6

12

PR219

PR219 0_0402_ 5%

0_0402_ 5%

1 2

1

PC105

2

330U_Y_2VM

+

PC106

330U_Y_2VM

+VGFX_COREP

1

12

+

PC302

PC288

2

10U_0603_6.3V6M~D

0.1U_0402_10V7K~D

1 2

+GFX_COREP TDC 15.4 A OCP Current 27A

A A

Security Class ification

2009/09/ 21 20 10/09/21

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2009/09/ 21 20 10/09/21

3

Compal Secret Data

Deciphered Date

Title

Size Document Num ber Rev

NAT02 M/B LA-5154P Schematic

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

+GFX_COREP

Thursday, November 26, 2009

1

48 49

1.0

5

R e qu e st

Ite m

Ite m Issu e D escrip t io n

Ite mI t e m

P a ge# T itle

P a ge#Pa ge#

Title

TitleTitle

D ate

D ateD ate

R e qu e stR eq ues t

O w ner

O w nerO wn e r

4

V ersion C h ang e L ist ( P. I. R . L ist )

V ersion C h ang e L ist ( P. I. R . L ist )V ersion C h ang e L ist ( P. I. R . L ist )

Issu e D escrip t io nD ate

Issu e D escrip t io nI ssu e D es c rip tio n

3

Pag e 1

Pag e 1Pag e 1

2

So l u tion D esc r ip tio n

So l u tion D esc r ip tio n R e v.

So l u tion D esc r ip tio nS o lu tio n D escr ip tio n

1

R e v.P a ge#

R e v.R e v.

01 P51 +1.1VS_VTTP 08/31 Lin Will Slove EMI Add PL22 and Change PR233 form 0 ohm to 2.2 ohm.

D D

02 P53 +CPU_Core 08/31 Lin Will Slove EMI Change PR259 and PR291 from 0 ohm to 2.2 ohm.

03 P55 +GFX_COREP 08/31 Lin Will Adjust load-line and Imon

04 P55 +GFX_COREP 08/31 Lin Will Adjust output voltage ripple and thermal dispation

05 P43 +1.05VSP/+0.75VSP 10/14 Lin Will Slove the IC input power sequence.

06 P42 +3VALWP/+5VALWP 10/14 Lin Will Slove EMI.

C C

07 P44 +1.5VSP/+0.75VSP 10/14 Lin Will Slove EMI.

08 P45 +1.1VS_VTTP 11/20 Lin Will Low down the power consumption.

09 P41/P42

10 P42 +3VALWP/+5VALWP 11/20 Lin Will

Charger +3VALWP/+5VALWP

11/20 Lin Will 1206 size shortage issue.

When adapter inserts and pulls out quickly two twice, it will make TPS51427 out of electricity.

Change PR306 form 9.54K to 9.76K, PR210 from 22.3K to 24K and PC296 from 0.22uF to 0.033uF.

Add PQ46 and change PC289, PC290, PC301 from 4.7uF to 10uF, and PC105, PC106 from 330uF 9mohm to 330uF 6mohm.

Change TPS51117 V5FILT and V5DRV from 5VS to 5VALW.

Change PJP19 to PL23, and PR59, PR60 from 0 ohm to

2.2 ohm.

Change PJP29 to PL24.

Change PR232 from 43.2K to 9.31K, and add PR327 2.7K.

Change SE142475K8L(1206) to SE000006R8L(0805), and SE041224K8L(1206) to SE000005Z8L(0603).

Add PR91,PR92,PR93 100K, PQ24 TP0610K, PQ10 DTC115EUA, and PD17 1SS355TE-17. But all unpop. Change PU5 to ISL6237, and add PJP24.

X01

X02

X03

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2009/09/21 2010/09/21

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PWR PIR-1

NAT02 M/B LA-5154P Schematic

49 49Thursday, November 26, 2009

1

1.0

DELL 1749 Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual