DELL 1749 Schematics
A
1 1
B
C
D
E
Compal Confidential
2 2
NAT02 M/B Schematics Document
Intel Arrandale Processor with DDRIII + Ibex Peak-M
3 3
2009-11-26
REV:1.0
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2009/09/21 2010/09/21
2009/09/21 2010/09/21
2009/09/21 2010/09/21
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
Cover Page
Cover Page
Cover Page
NAT02 M/B LA-5154P Schematic
NAT02 M/B LA-5154P Schematic
NAT02 M/B LA-5154P Schematic
1 49Thursday, November 26, 2009
1 49Thursday, November 26, 2009
1 49Thursday, November 26, 2009
E
1.0
1.0
1.0
5
Block Diagram
Compal confidential
Model : NAT01
D D
CRT CONN
+5VS
LVDS CONN
+LCDVDD
+3.3V_ALW
P.35
P.35
DP CONN
+5VS
P.37
HDMI CONN
+5VS
C C
To Card-reader subboard
8 IN 1 CONN
+3VS
IEEE1394
P.36
+3VS
+1.8VS
FFS
+3VS
VGA
LVDS
DPD
DPB
HDMI
Level Shift
CardBus
OZ888GS0
P.14
P.36
P.30
FAN
+5VS
+3VS
4
P.14
+CPU_CORE
+1.1VS_VTT
Arrandale
(UMA)
Processor
rPGA988A
FDI x8
(UMA)
100MHz
2.7GT/s
Ibex Peak-M
100MHz
PCI-Express x 8 (ABD PCIE1 2.5GT/S CKD PCIE1/2 2.5/5GT/S)
+1.05VS
page 15,16,17 18,19,
20,21,22,23
LPC BUS
+3VS
33MHz
3
Intel
page 5,6,7,8,9,10
Intel
PCH
DMI x4
100MHz
1GB/s x4
USBx14
SATA x 6
(GEN1 1.5GT/S ,GEN2 3GT/S)
HD Audio
SPI
SPI ROM x1
32Mbit
page 15
Clock Generator
IDT: 9LRS3199AKLFT
SILEGO: SLG8SP587
133/120/100/96/14.318MHZ to PCH
48MHZ to CardReader
Memory BUS(DDRIII)
Dual Channel
1.5V DDRIII 800/1066/1333
6.4G/8.5G/10.6G
100M/133M/166M(CFD)
3.3V 48MHz
100MHz
3.3V 24MHz
2
page 13
Right Front Side.
Right behind side.
port 5
DDRIII-DIMM X2
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 ,8
+1.5V
+0.75VS
USB Port X1
+5V_ALW
USB Port1 X1
+5V_ALW
Bluetooth
Touch Screen
Camera
P.11,12
P.30
P.30
P.30
P.32
P.30
Charge USB/E-SATA
Ports X1
+5VALW
1
CPU XDP
133MHz
page 06
To Card-reader
subboard
To Single USB
subboard
P.30
Express Card
P.28
B B
RJ45
Mini Card 3
TV Tuner
+3VS
DC/DC Interface
A A
P.28 P.27 P.27
BATT IN
P.33 P.47
1.1VS_VTTPower Sequence
DC IN
5
RTL8111DL
+3VALW
Mini Card 2
WLAN
+3VS
+1.5VS+1.5VS
USB[x]
P.45
P.40
P.24
PCIE1PCIE2PCIE3
Mini Card 1
WWAN
+3VS
+1.5VS
USB[x]USB[x]
VCORE
CHARGER
1.5V/0.75V
P.46 P.44
3V/5V
GFX_Core/1.05V 1.05V/1.8V
4
Int.KBD &
BL
P.42P.41
P.43P.48
ENE KBC
KB926QFD3
+RTC_CELL
+3VALW
P.31
SPI
SB3526
+3VS
To Cap Sensor
subboard
page 32
Touch Pad
P.32P.32
Flash ROM
16Mx1sector
P.31
+3VS
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2009/09/21 2010/09/21
2009/09/21 2010/09/21
2009/09/21 2010/09/21
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Azalia Codec
92HD73C
+3VS
+VDDA
AMP
MAX4411x2
HeadPhone &
MIC Jack
2
PCI Express BUS
P.25
P.25
port 4
E-ODD
+3VS
+5VS
S-HDD-2
P.29 P.29 P.29
+5VS
AMP
MAX9736A
P.26
P.25
B+
AMP
MAX9736A
P.26
B+
Dig. MIC
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
NAT02 M/B LA-5154P Schematic
NAT02 M/B LA-5154P Schematic
NAT02 M/B LA-5154P Schematic
port 1port 0
S-HDD-1
+5VS
Speaker
Subwoofer
P.30
Block Diagrams
Block Diagrams
Block Diagrams
1
1.0
1.0
2 49Thursday, November 26, 2009
2 49Thursday, November 26, 2009
2 49Thursday, November 26, 2009
1.0
A
Voltage Rails
Power Plane Description
VIN
1 1
2 2
B+
+CPU_CORE
+VGFX_CORE
+0.75VS 0.75V switched power rail for DDR terminator
+1.05VS
+1.1VS_VTT 1.1V switched power rail (1.05 for AUB CPU) ON OFF OFF
+1.1VS
+1.5V 1.5V power rail for DDRIII ON ON OFF
+1.5VS
+1.8VS 1.8V switched power rail
+3VALW 3.3V always on power rail
+LAN_IO 3.3V power rail for LAN ON ON
+3VS
+5VALW
+5VS
B+_BIAS B+ always on power rail ON ON*
+RTCVCC RTC power
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
Core voltage for Graphic ON OFFOFF
1.05V switched power rail for PCH
1.1V power rail for PCIE of GUP
1.5V switched power rail
3.3V switched power rail
5V always on power rail
5V switched power rail
B
S1 S3 S5
N/A N/A N/A
ON
ON OFF
ON OFF OFF
ON OFF OFF
ON OFF OFF
ON
ON
ON
ON
ON
ON
N/AN/AN/A
OFF
OFF
OFF
OFF
OFF
ON ON*
ON*
OFF
OFF
ON ON*
OFF
OFFON
ONON
Board ID
X00
X01
X02
MP
X00
X01
X02
MP
C
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
SIGNAL
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
HIGH HIGH HIGH HIGH
LOW
LOW
LOW
HIGH
LOWLOWLOW
HIGHHIGHHIGH
HIGH
HIGH
LOW LOW LOW LOW
Board ID / SKU ID Table for AD channel
Vcc 3.3V +/- 5%
VGA
M96
M96
M96
M96
Madison
Madison
Madison
Madison
100K +/- 1%Ra
Rb V min
AD_BID
0
8.2K +/- 1%
18K +/- 1%
33K +/- 1%
56K +/- 1%
100K +/- 1%
200K +/- 1%
NC
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
1.036 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
0 V
D
ON
ON
ON
ON
ON
ON
ON
OFF
ON
OFF
V typ
AD_BID
V
AD_BID
0 V 0.100 V
0.503 V
0.819 V
0.538 V
0.875 V
1.185 V 1.264 V
2.200 V
3.300 V
2.341 V
3.300 V
ON ON
ON
OFF
OFF
OFF
max
E
LOW
OFF
OFF
OFF
External PCI Devices
Device IDSEL#
REQ#/GNT#
Interrupts
USB Port Table
EC SM Bus1 address
3 3
Device
Smart Battery
Address Address
0001 011X b
EC SM Bus2 address
Device
WWAN
WLAN
Express Card
USB Port
0
1
2
3
4
5
6
7
Ibex SM Bus address
Device
Clock Generator
(9LRS3191AKLFT, SLG8S P585)
DDR DIMM0
DDR DIMM1
Free Fall Sensor
4 4
CPU XDP
PCH XDP
XDCP_ISL90727
XDCP_ISL90728
A
Address
1101 0010b
1001 000Xb
1001 010Xb
remove
0101 110Xb
0111 110Xb
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
8
9
10
11
2009/09/21 2010/09/21
2009/09/21 2010/09/21
2009/09/21 2010/09/21
C
Device
USB&ESATA
Reader/BD
USB board
WPAN
WLAN
WWAN
NC
NC
Express
Touch screen
Bluetooth
Camera
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
BTO Option Table
BTO Item BOM Structure
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
NAT02 M/B LA-5154P Schematic
NAT02 M/B LA-5154P Schematic
NAT02 M/B LA-5154P Schematic
Notes List
Notes List
Notes List
E
1.0
1.0
3 49Thursday, November 26, 2009
3 49Thursday, November 26, 2009
3 49Thursday, November 26, 2009
1.0
5
4
3
2
1
D D
SUSP#
TPS51117RGYR
(PU7)
SUSP#
ISL6268CAZ-T
(PU8)
ADAPTER
VR_ON
ISL62883HRZ-T
(PU13)
BATTERY
B+
GFXVR_PWRGD
SYSON
ISL62881HRZ-T
(PU22)
ISL6268CAZ-T
(PU10)
C C
SUSP#
CHARGER
SUSP#
TPS51117RGYR
(PU6)
TPS51427
2500mA
15000mA
65000mA
15000mA
12800mA
5700mA
+1.8VS
+1.1VS_VTT
+CPU_CORE
+GFX_CORE
+1.5V
+1.05VS
SUSP#
0 Ohm
SI4800BDY
(U25)
RT9025
(PU12)
RT9026
(PU10)
+1.05VS_CK505
8881mA
+1.5VS
913mA
+1.1VS
?mA
+0.75VS
(PU5)
+5VALW
8400mA
RUNON
SI4800BDY
(U22)
2000mA 8677mA160mA 20mA
USB_EN#
TPS2062ADR
(U17)
EN_EOL#
SI3456BDY
(Q3)
+LAN_IO
B B
+5VS
+5V_CHGUSB
EN_EOL#
RTL8111DL
FUSE
0 Ohm
0 Ohm
+CRT_VCC
+AVDD_AUDIO
+5VS_KBL
(U9)
+LAN_VDD
+3VALW
SUSP
FBM-11-160808-601-T
(L29)
+EC_AVCC
SUSP
SI4800BDY
(U21)
+3VS
0 Ohm
0 Ohm
0 Ohm
0 Ohm
+3VS_CK505
+DVDD_AUDIO
+3V_WLAN
+3V_WLAN
VDDEN
SI2310BDS-T1-E3
(Q25)
+LCDVDD
EN_EOL#
SI2310BDS
(Q34)
+3VS_DELAY
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2009/09/21 2010/09/21
2009/09/21 2010/09/21
2009/09/21 2010/09/21
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
Power Rail
Power Rail
Power Rail
NAT02 M/B LA-5154P Schematic
NAT02 M/B LA-5154P Schematic
NAT02 M/B LA-5154P Schematic
1
4 49Thursday, November 26, 2009
4 49Thursday, November 26, 2009
4 49Thursday, November 26, 2009
1.0
1.0
1.0
5
JCPU1A
JCPU1A
DMI_PTX_HRX_N0<17>
DMI_PTX_HRX_N1<17>
DMI_PTX_HRX_N2<17>
DMI_PTX_HRX_N3<17>
DMI_PTX_HRX_P0<17>
DMI_PTX_HRX_P1<17>
DMI_PTX_HRX_P2<17>
UMA
DMI_PTX_HRX_P3<17>
DMI_HTX_PRX_N0<17>
DMI_HTX_PRX_N1<17>
DMI_HTX_PRX_N2<17>
DMI_HTX_PRX_N3<17>
DMI_HTX_PRX_P0<17>
DMI_HTX_PRX_P1<17>
DMI_HTX_PRX_P2<17>
DMI_HTX_PRX_P3<17>
H_FDI_TXN0<17>
H_FDI_TXN1<17>
H_FDI_TXN2<17>
H_FDI_TXN3<17>
H_FDI_TXN4<17>
H_FDI_TXN5<17>
H_FDI_TXN6<17>
H_FDI_TXN7<17>
H_FDI_TXP0<17>
H_FDI_TXP1<17>
H_FDI_TXP2<17>
H_FDI_TXP3<17>
H_FDI_TXP4<17>
H_FDI_TXP5<17>
H_FDI_TXP6<17>
H_FDI_TXP7<17>
H_FDI_FSYNC0<17>
H_FDI_FSYNC1<17>
H_FDI_LSYNC0<17>
H_FDI_LSYNC1<17>
H_FDI_TXN0
H_FDI_TXN1
H_FDI_TXN2
H_FDI_TXN3
H_FDI_TXN4
H_FDI_TXN5
H_FDI_TXN6
H_FDI_TXN7
H_FDI_TXP0
H_FDI_TXP1
H_FDI_TXP2
H_FDI_TXP3
H_FDI_TXP4
H_FDI_TXP5
H_FDI_TXP6
H_FDI_TXP7
H_FDI_INT< 17>
D D
C C
B B
A24
DMI_RX#[0]
C23
DMI_RX#[1]
B22
DMI_RX#[2]
A21
DMI_RX#[3]
B24
DMI_RX[0]
D23
DMI_RX[1]
B23
DMI_RX[2]
A22
DMI_RX[3]
D24
DMI_TX#[0]
G24
DMI_TX#[1]
F23
DMI_TX#[2]
H23
DMI_TX#[3]
D25
DMI_TX[0]
F24
DMI_TX[1]
E23
DMI_TX[2]
G23
DMI_TX[3]
E22
FDI_TX#[0]
D21
FDI_TX#[1]
D19
FDI_TX#[2]
D18
FDI_TX#[3]
G21
FDI_TX#[4]
E19
FDI_TX#[5]
F21
FDI_TX#[6]
G18
FDI_TX#[7]
D22
FDI_TX[0]
C21
FDI_TX[1]
D20
FDI_TX[2]
C18
FDI_TX[3]
G22
FDI_TX[4]
E20
FDI_TX[5]
F20
FDI_TX[6]
G19
FDI_TX[7]
F17
FDI_FSYNC[0]
E17
FDI_FSYNC[1]
C17
FDI_INT
F18
FDI_LSYNC[0]
D17
FDI_LSYNC[1]
IC,AUB_CFD_rPGA,R0P9
IC,AUB_CFD_rPGA,R0P9
CONN@
CONN@
DMI Intel(R) FDI
DMI Intel(R) FDI
PCI EXPRESS -- GRAPHICS
PCI EXPRESS -- GRAPHICS
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RBIAS
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
4
R605
B26
A26
B27
A25
K35
J34
J33
G35
G32
F34
F31
D35
E33
C33
D32
B32
C31
B28
B30
A31
J35
H34
H33
F35
G33
E34
F32
D34
F33
B33
D31
A32
C30
A28
B29
A30
L33
M35
M33
M30
L31
K32
M29
J31
K29
H30
H29
F29
E28
D29
D27
C26
L34
M34
M32
L30
M31
K31
M28
H31
K28
G30
G29
F28
E27
D28
C27
C25
PEG_IRCOMP
EXP_RBIAS
UMA
Remove PCI E-16X
R605
1 2
R613
R613
1 2
49.9_0402_1%~D
49.9_0402_1%~D
750_0402_1%~D
750_0402_1%~D
3
R1035
R1035
3.01K_0402_1%~D @
3.01K_0402_1%~D @
R1036
R1036
3.01K_0402_1%~D @
3.01K_0402_1%~D @
R1037
3.01K_0402_1%~D
3.01K_0402_1%~D
R1038
3.01K_0402_1%~D
3.01K_0402_1%~D
WW41 Recommend not pull down
PCIE2.0 Jitter is over on ES1
H_DIMMA_REF<11>
H_DIMMB_REF<12>
1 2
1 2
@R1037
@
1 2
@R1038
@
1 2
R212
R212
0_0402_5%~D
0_0402_5%~D
1 2
1 2
R213
R213
0_0402_5%~D
0_0402_5%~D
2
JCPU1E
JCPU1E
RSVD32
AP25
RSVD1
AL25
RSVD2
AL24
RSVD3
AL22
RSVD4
AJ33
RSVD5
AG9
RSVD6
M27
RSVD7
L28
RSVD8
J17
(SA_DIMM_VREF)
RSVD9
H17
(SB_DIMM_VREF)
RSVD10
G25
RSVD11
G17
RSVD12
E31
RSVD13
E30
RSVD14
CFG0
AM30
AM28
AP31
AL32
AL30
AM31
AN29
AM32
AK32
AK31
AK28
AJ28
AN30
AN32
AJ32
AJ29
AJ30
AK30
H16
B19
A19
A20
B20
AC9
AB9
A34
A33
C35
B35
U9
T9
C1
A3
J29
J28
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
RSVD_TP_86
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD_NCTF_23
RSVD_NCTF_24
RSVD26
RSVD27
RSVD_NCTF_28
RSVD_NCTF_29
RSVD_NCTF_30
RSVD_NCTF_31
RESERVED
RESERVED
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
@
@
@
@
RSVD33
RSVD34
RSVD35
RSVD36
RSVD_NCTF_37
RSVD38
RSVD39
RSVD_NCTF_40
RSVD_NCTF_41
RSVD_NCTF_42
RSVD_NCTF_43
RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
RSVD53
RSVD_NCTF_54
RSVD_NCTF_55
RSVD_NCTF_56
RSVD_NCTF_57
RSVD58
RSVD_TP_59
RSVD_TP_60
KEY
RSVD62
RSVD63
RSVD64
RSVD65
RSVD_TP_66
RSVD_TP_67
RSVD_TP_68
RSVD_TP_69
RSVD_TP_70
RSVD_TP_71
RSVD_TP_72
RSVD_TP_73
RSVD_TP_74
RSVD_TP_75
RSVD_TP_76
RSVD_TP_77
RSVD_TP_78
RSVD_TP_79
RSVD_TP_80
RSVD_TP_81
RSVD_TP_82
RSVD_TP_83
RSVD_TP_84
RSVD_TP_85
VSS
AJ13
AJ12
AH25
AK26
AL26
AR2
AJ26
AJ27
AP1
AT2
AT3
AR1
AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33
AT33
AT34
AP35
AR35
AR32
E15
F15
A2
D15
C15
AJ15
AH15
AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3
V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9
AP34
@
@
@
@
@
@
@
@
@
@
@
@
R649
R649
0_0402_5%~D
0_0402_5%~D
R648
R648
0_0402_5%~D
0_0402_5%~D
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
1
T97
T97
T98
T98
T99
T99
T100
T100
T101
T101
T102
T102
@
@
12
@
@
12
IC,AUB_CFD_rPGA,R0P9
IC,AUB_CFD_rPGA,R0P9
CONN@
CONN@
CFG0 - PCI-Expr ess Configurati on Select
*1:Single PEG
0:Bifurcation e nabled
CFG3 - PCI-Expr ess Static Lane Reversal
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2009/09/21 2010/09/21
2009/09/21 2010/09/21
2009/09/21 2010/09/21
Compal Secret Data
Compal Secret Data
Compal Secret Data
*1 :Normal Oper ation
0 :Lane Numbers Reversed
15 -> 0, 14 -> 1, ...
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
CFG4 - Display Port Presence
*1:Disabled; No Physical Displ ay Port
attached to Embedded Displa y Port
0:Enabled; An e xternal Display Port
device is co nnected to the Embedded
Display Port
*:Default
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
PROCESSOR (1/6) DMI,FDI,PEG
PROCESSOR (1/6) DMI,FDI,PEG
PROCESSOR (1/6) DMI,FDI,PEG
NAT02 M/B LA-5154P Schematic
NAT02 M/B LA-5154P Schematic
NAT02 M/B LA-5154P Schematic
1
5 49Thursday, November 26, 2009
5 49Thursday, November 26, 2009
5 49Thursday, November 26, 2009
1.0
1.0
1.0
5
JCPU1B
H_COMP3
H_COMP2
H_COMP1
H_COMP0
SKTOCC#_R
@
@
PAD
PAD
T5
R1039
R1039
1 2
0_0402_5%~D
0_0402_5%~D
R1042
R1042
1 2
0_0402_5%~D
0_0402_5%~D
R300
R300
0_0402_5%~D
0_0402_5%~D
R263
R263
0_0402_5%~D
0_0402_5%~D
R1043
R1043
0_0402_5%~D
0_0402_5%~D
R1045
R1045
1 2
0_0402_5%~D
0_0402_5%~D
R316
R316
0_0402_5%~D
0_0402_5%~D
R289
R289
1 2
1.5K_0402_1%~D
1.5K_0402_1%~D
T5
1 2
1 2
1 2
1 2
H_CATERR#
H_PECI_R
H_PROCHOT#
H_THERMTRIP#_R
H_CPURST#
H_PM_SYNC_R
H_CPUPWRGD_1
H_CPUPWRGD_0
PM_DRAM_PWRGD_R
PLT_RST#_R
12
R1052
R1052
750_0402_1%~D
750_0402_1%~D
D D
H_PECI<20>
H_PROCHOT#<46>
H_THERMTRIP#<20>
H_PM_SYNC<17>
C C
H_CPUPWRGD<20>
PM_DRAM_PWRGD<17>
H_VTTPWRGD<45>
H_PWRGD_XDP H_PWRGD_XDP_R
PLT_RST#<19,24,27,28,30,31>
JCPU1B
AT23
COMP3
AT24
COMP2
G16
COMP1
AT26
COMP0
AH24
SKTOCC#
AK14
CATERR#
AT15
PECI
AN26
PROCHOT #
AK15
THERMTR IP#
AP26
RESET_O BS#
AL15
PM_SYNC
AN14
VCCPW RGOOD_1
AN27
VCCPW RGOOD_0
AK13
SM_DRAM PWROK
AM15
VTTPW RGOOD
AM26
TAPPW RGOOD
AL14
RSTIN#
IC,AUB_CFD_rPGA,R0P9
IC,AUB_CFD_rPGA,R0P9
CONN@
CONN@
4
MISC THERMAL
MISC THERMAL
DPLL_RE F_SSCLK
DPLL_RE F_SSCLK#
CLOCKS
CLOCKS
SM_DRAM RST#
SM_RCOM P[0]
SM_RCOM P[1]
SM_RCOM P[2]
PM_EXT_ TS#[0]
PM_EXT_ TS#[1]
DDR3
MISC
DDR3
MISC
PWR MANAGEMENT
PWR MANAGEMENT
JTAG & BPM
JTAG & BPM
BCLK
BCLK#
BCLK_ITP
BCLK_ITP#
PEG_CLK
PEG_CLK #
PRDY#
PREQ#
TCK
TMS
TRST#
TDO
TDI_M
TDO_M
DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
A16
B16
AR30
AT30
E16
D16
A18
A17
F6
AL1
AM1
AN1
AN15
AP15
AT28
AP27
AN28
AP28
AT27
AT29
TDI
AR27
AR29
AP29
AN25
AJ22
AK22
AK24
AJ24
AJ25
AH22
AK23
AH23
3
CLK_CPU_BCLK_R
CLK_CPU_BCLK#_R
CLK_CPU_ITP_R
CLK_CPU_ITP#_R
CLK_CPU_DMI_R
CLK_CPU_DMI#_R
CLK_CPU_DP_R
CLK_CPU_DP#_R
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
PM_EXTTS#0
PM_EXTTS#1_R
XDP_PRDY#
XDP_PREQ#
XDP_TCLK
XDP_TMS
XDP_TRST#
XDP_TDI_R
XDP_TDO_R
XDP_TDI_M
XDP_TDO_M
XDP_DBR#_R
R1060 0_0402_5%~DR1060 0_0402_5%~D
R1044 0_0402_5%~DR1044 0_0402_5%~D
R1046 0_0402_5%~DR1046 0_0402_5%~D
R1047 0_0402_5%~DR1047 0_0402_5%~D
R1048 0_0402_5%~DR1048 0_0402_5%~D
R1049 0_0402_5%~DR1049 0_0402_5%~D
R1050 0_0402_5%~DR1050 0_0402_5%~D
R1051 0_0402_5%~DR1051 0_0402_5%~D
R284 0_0402_5%~DR284 0_0402_5%~D
R609 0_0402_5%~DR609 0_0402_5%~D
1 2
R610 0_0402_5%~DR610 0_0402_5%~D
1 2
R655 0_0402_5%~DR655 0_0402_5%~D
1 2
R654 0_0402_5%~DR654 0_0402_5%~D
1 2
R606 0_0402_5%~DR606 0_0402_5%~D
1 2
R607 0_0402_5%~DR607 0_0402_5%~D
1 2
RU83 0_0402_5%~DRU83 0_0402_5%~D
1 2
RU84 0_0402_5%~DRU84 0_0402_5%~D
1 2
R1121 0_0402_5%~D@ R1121 0_0402_5%~D@
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
G
G
2
13
D
S
D
S
1 2
R1040 10K_0402_5%~DR1040 10K_0402_5%~D
1 2
R288 10K_0402_5%~DR288 10K_0402_5%~D
1 2
R1041 0_0402_5%~DR1041 0_0402_5%~D
1 2
XDP_DBRESET#
XDP_OBS0XDP_OBS0_R
XDP_OBS1XDP_OBS1_R
XDP_OBS2XDP_OBS2_R
XDP_OBS3XDP_OBS3_R
XDP_OBS4XDP_OBS4_R
XDP_OBS5XDP_OBS5_R
XDP_OBS6XDP_OBS6_R
XDP_OBS7XDP_OBS7_R
CLK_CPU_XDP
CLK_CPU_XDP#
Q36BSS138_SOT23~D
Q36BSS138_SOT23~D
CLK_CPU_BCLK <20>
CLK_CPU_BCLK# <20>
CLK_CPU_DMI <16>
CLK_CPU_DMI# <16>
CLK_CPU_DP <16>
CLK_CPU_DP# <16>
DDR_RST_GATE <11,12,20>
SM_DRAMRST# <11,12>
+1.1VS_VTT
PM_EXTTS#0_1 <11,12>
XDP_DBRESET# <17>
2
+3VALW
C1142
R1136
R1136
1 2
10K_0402_5%~D
10K_0402_5%~D
1.5V_PWRGD<44>
74AHC1G08GW_SOT353-5~D
74AHC1G08GW_SOT353-5~D
XDP_TMS
XDP_TDI_R
XDP_PREQ#
XDP_TCLK
XDP_TRST#
XDP_TDI_R XDP_TDI
XDP_TDI_M
XDP_TDO_R
C1142
1 2
0.1U_0402_10V6K~D
0.1U_0402_10V6K~D
5
U69
U69
1
P
IN1
4
O
1.5K_0402_1%~D
IN2
G
3
1 2
1 2
1 2
1 2
1 2
1 2
1 2
@
@
1 2
1 2
1.5K_0402_1%~D
2
R657 51_0402_1%~D@R657 51_0402_1%~D@
R653 51_0402_1%~D@R653 51_0402_1%~D@
R656 51_0402_1%~D@R656 51_0402_1%~D@
R669 51_0402_1%~D@R669 51_0402_1%~D@
R651 51_0402_1%~DR651 51_0402_1%~D
R661 0_0402_5%~DR661 0_0402_5%~D
R662 0_0402_5%~D@R662 0_0402_5%~D@
12
R663
R663
0_0402_5%~D
0_0402_5%~D
R667 0_0402_5%~D
R667 0_0402_5%~D
R668 0_0402_5%~DR668 0_0402_5%~D
1
R290
R290
12
750_0402_1%~D
750_0402_1%~D
+1.1VS_VTT
PM_DRAM_PWRGD_R
R1103
R1103
1 2
XDP_TDOXDP_TDO_M
JTAG MAPPING
Scan Chain
(Default)
CPU Only
GMCH Only
STUFF -> R653, R657, R662
NO STUFF -> R655, R660
STUFF -> R653, R655
NO STUFF -> R657, R660, R662
STUFF -> R660, R662
NO STUFF -> R653, R655, R657
WW51.4 CRB Board Rework/workaround- Rev 0.1
has changed the resistors in RSTIN#
PAD
PAD
PAD
PAD
XDP_PREQ#
XDP_PRDY#
XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3
XDP_OBS4
XDP_OBS5
XDP_OBS6
XDP_OBS7
H_PWRGOOD_R
PBTN_OUT#_XDP
H_PWRGD_XDP
SMB_DATA_S3
@
@
SMB_CLK_S3
@
@
XDP_TCLK
2009/09/21 2010/09/21
2009/09/21 2010/09/21
2009/09/21 2010/09/21
3
B B
+1.5V
PM_DRAM_PWRGD_R
A A
5
[Calpella] Platform – Design Guide Addendum / Update – Rev. 1.52
12
R1054
@R1054
@
1.1K_0402_1%~D
1.1K_0402_1%~D
12
R1055
@R1055
@
3K_0402_1%~D
3K_0402_1%~D
H_CATERR#
H_PROCHOT#
H_CPURST#
H_COMP0
H_COMP1
H_COMP2
H_COMP3
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
PCH_SMBDATA<11,12,16>
PCH_SMBCLK<11,12,16>
R1053 49.9_0402_1%~DR1053 49.9_0402_1%~D
R1061 68_0402_5%~DR1061 68_0402_5%~D
R1062 68_0402_5%~D@R1062 68_0402_5%~D@
R650 49.9_0402_1%~DR650 49.9_0402_1%~D
1 2
R234 49.9_0402_1%~DR234 49.9_0402_1%~D
1 2
R659 20_0402_1%~DR659 20_0402_1%~D
1 2
R658 20_0402_1%~DR658 20_0402_1%~D
1 2
R645 100_0402_1%~DR645 100_0402_1%~D
1 2
R646 24.9_0402_1%~DR646 24.9_0402_1%~D
1 2
R647 130_0402_1%~DR647 130_0402_1%~D
1 2
1 3
1 3
1 2
1 2
1 2
+3VS
2
G
G
D
S
D
S
Q52
Q52
2N7002LT1G_SOT23-3
2N7002LT1G_SOT23-3
+3VS
2
G
G
D
S
D
S
Q53
Q53
2N7002LT1G_SOT23-3
2N7002LT1G_SOT23-3
R480
R480
4.7K_0402_5%~D
4.7K_0402_5%~D
1 2
SMB_DATA_S3
R1099
R1099
4.7K_0402_5%~D
4.7K_0402_5%~D
1 2
SMB_CLK_S3
4
+1.1VS_VTT
+3VS
+3VS
PBTN_OUT#<17,31>
+1.1VS_VTT
C315
C315
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
@
@
R365
R365
1K_0402_5%~D
1K_0402_5%~D
H_CPUPWRGD
1
2
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF CO MPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF CO MPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF CO MPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
1 2
1 2
R363 0_0402_5%~DR363 0_0402_5%~D
T103
T103
T104
T104
Issued Date
Issued Date
Issued Date
XDP Connector
JP8
JP8
1
GND0
3
OBSFN_A 0
5
OBSFN_A 1
7
GND2
9
OBSDATA _A0
11
OBSDATA _A1
13
GND4
15
OBSDATA _A2
17
OBSDATA _A3
19
GND6
21
OBSFN_B 0
23
OBSFN_B 1
25
GND8
27
OBSDATA _B0
29
OBSDATA _B1
31
GND10
33
OBSDATA _B2
35
OBSDATA _B3
37
GND12
39
PWRG OOD/HOOK0
41
HOOK1
43
VCC_OBS _AB
45
HOOK2
47
HOOK3
49
GND14
51
SDA
53
SCL
55
TCK1
57
TCK0
59
GND16
Compal Secret Data
Compal Secret Data
Compal Secret Data
SAMTE_BSH-030-01-L-D-ACONN@
SAMTE_BSH-030-01-L-D-ACONN@
Deciphered Date
Deciphered Date
Deciphered Date
GND1
OBSFN_C 0
OBSFN_C 1
GND3
OBSDATA _C0
OBSDATA _C1
GND5
OBSDATA _C2
OBSDATA _C3
GND7
OBSFN_D 0
OBSFN_D 1
GND9
OBSDATA _D0
OBSDATA _D1
GND11
OBSDATA _D2
OBSDATA _D3
GND13
ITPCLK/HOO K4
ITPCLK#/HO OK5
VCC_OBS _CD
RESET#/H OOK6
DBR#/HOO K7
GND15
TRST#
TMS
GND17
TD0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
TDI
58
60
2
H_RESET#_R
CLK_CPU_XDP
CLK_CPU_XDP#
H_RESET#_R
XDP_DBRESET#
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
R1063
R1063
1K_0402_5%~D
1K_0402_5%~D
1 2
1 2
R362
R362
0_0402_5%~D
0_0402_5%~D
1 2
1 2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
H_CPURST#
@
@
R1064
R1064
1K_0402_5%~D
1K_0402_5%~D
R1065
R1065
51_0402_1%~D
51_0402_1%~D
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
PROCESSOR (2/6) CLK,JTAG
PROCESSOR (2/6) CLK,JTAG
PROCESSOR (2/6) CLK,JTAG
NAT02 M/B LA-5154P Schematic
NAT02 M/B LA-5154P Schematic
NAT02 M/B LA-5154P Schematic
PCI_PLTRST# <19>
+1.1VS_VTT
Leakage Issue
+3VS
+1.1VS_VTT
1
6 49Thursday, November 26, 2009
6 49Thursday, November 26, 2009
6 49Thursday, November 26, 2009
1.0
1.0
1.0
5
JCPU1C
C10
D10
H10
G10
AH5
AF5
AK6
AK7
AF6
AG5
AJ10
AL10
AK12
AK8
AK11
AN8
AM10
AR11
AL11
AM9
AN9
AT11
AP12
AM12
AN12
AM13
AT14
AT12
AL13
AR14
AP14
AC3
AB2
AE1
AB3
AE9
A10
B10
E10
F10
J10
AJ7
AJ6
AJ9
AL7
AL8
C7
A7
A8
D8
E6
E9
B7
E7
C6
G8
K7
G7
M6
M8
K8
N8
P9
U7
F7
J8
J7
L7
L9
L6
JCPU1C
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_BS[0]
SA_BS[1]
SA_BS[2]
SA_CAS#
SA_RAS#
SA_WE#
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
DDR_A_D [0..63]<11>
DDR_A_D M[0..7]<11>
DDR_A_D QS#[0..7]<1 1>
DDR_A_D QS[0..7]<11>
DDR_A_M A[0..15]< 11>
DDR_A_D 0
DDR_A_D 1
D D
C C
B B
DDR_A_B S0<11>
DDR_A_B S1<11>
DDR_A_B S2<11>
DDR_A_C AS#<11>
DDR_A_R AS#<11>
DDR_A_W E#<11>
DDR_A_D 2
DDR_A_D 3
DDR_A_D 4
DDR_A_D 5
DDR_A_D 6
DDR_A_D 7
DDR_A_D 8
DDR_A_D 9
DDR_A_D 10
DDR_A_D 11
DDR_A_D 12
DDR_A_D 13
DDR_A_D 14
DDR_A_D 15
DDR_A_D 16
DDR_A_D 17
DDR_A_D 18
DDR_A_D 19
DDR_A_D 20
DDR_A_D 21
DDR_A_D 22
DDR_A_D 23
DDR_A_D 24
DDR_A_D 25
DDR_A_D 26
DDR_A_D 27
DDR_A_D 28
DDR_A_D 29
DDR_A_D 30
DDR_A_D 31
DDR_A_D 32
DDR_A_D 33
DDR_A_D 34
DDR_A_D 35
DDR_A_D 36
DDR_A_D 37
DDR_A_D 38
DDR_A_D 39
DDR_A_D 40
DDR_A_D 41
DDR_A_D 42
DDR_A_D 43
DDR_A_D 44
DDR_A_D 45
DDR_A_D 46
DDR_A_D 47
DDR_A_D 48
DDR_A_D 49
DDR_A_D 50
DDR_A_D 51
DDR_A_D 52
DDR_A_D 53
DDR_A_D 54
DDR_A_D 55
DDR_A_D 56
DDR_A_D 57
DDR_A_D 58
DDR_A_D 59
DDR_A_D 60
DDR_A_D 61
DDR_A_D 62
DDR_A_D 63
DDR_A_B S0
DDR_A_B S1
DDR_A_B S2
DDR_A_C AS#
DDR_A_R AS#
DDR_A_W E#
SA_CK[0]
SA_CK#[0]
SA_CKE[0]
SA_CK[1]
SA_CK#[1]
SA_CKE[1]
SA_CS#[0]
SA_CS#[1]
SA_ODT[0]
SA_ODT[1]
SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
4
AA6
AA7
P7
Y6
Y5
P6
AE2
AE8
AD8
AF9
B9
D7
H7
M7
AG6
AM7
AN10
AN13
C9
F8
J9
N9
AH7
AK9
AP11
AT13
C8
F9
H9
M9
AH8
AK10
AN11
AR13
Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9
DDR_A_D M0
DDR_A_D M1
DDR_A_D M2
DDR_A_D M3
DDR_A_D M4
DDR_A_D M5
DDR_A_D M6
DDR_A_D M7
DDR_A_D QS#0
DDR_A_D QS#1
DDR_A_D QS#2
DDR_A_D QS#3
DDR_A_D QS#4
DDR_A_D QS#5
DDR_A_D QS#6
DDR_A_D QS#7
DDR_A_D QS0
DDR_A_D QS1
DDR_A_D QS2
DDR_A_D QS3
DDR_A_D QS4
DDR_A_D QS5
DDR_A_D QS6
DDR_A_D QS7
DDR_A_M A0
DDR_A_M A1
DDR_A_M A2
DDR_A_M A3
DDR_A_M A4
DDR_A_M A5
DDR_A_M A6
DDR_A_M A7
DDR_A_M A8
DDR_A_M A9
DDR_A_M A10
DDR_A_M A11
DDR_A_M A12
DDR_A_M A13
DDR_A_M A14
DDR_A_M A15
DDR_A_C LK0 <11>
DDR_A_C LK0# <11>
DDR_A_C KE0 <11>
DDR_A_C LK1 <11>
DDR_A_C LK1# <11>
DDR_A_C KE1 <11>
DDR_A_C S0# <11>
DDR_A_C S1# <11>
DDR_A_O DT0 <1 1>
DDR_A_O DT1 <1 1>
3
DDR_B_D [0..63]<12>
DDR_B_D M[0..7]<12>
DDR_B_D QS#[0..7]<1 2>
DDR_B_D QS[0..7]<12>
DDR_B_M A[0..15]<12>
DDR_B_D 0
DDR_B_D 1
DDR_B_D 2
DDR_B_D 3
DDR_B_D 4
DDR_B_D 5
DDR_B_D 6
DDR_B_D 7
DDR_B_D 8
DDR_B_D 9
DDR_B_D 10
DDR_B_D 11
DDR_B_D 12
DDR_B_D 13
DDR_B_D 14
DDR_B_D 15
DDR_B_D 16
DDR_B_D 17
DDR_B_D 18
DDR_B_D 19
DDR_B_D 20
DDR_B_D 21
DDR_B_D 22
DDR_B_D 23
DDR_B_D 24
DDR_B_D 25
DDR_B_D 26
DDR_B_D 27
DDR_B_D 28
DDR_B_D 29
DDR_B_D 30
DDR_B_D 31
DDR_B_D 32
DDR_B_D 33
DDR_B_D 34
DDR_B_D 35
DDR_B_D 36
DDR_B_D 37
DDR_B_D 38
DDR_B_D 39
DDR_B_D 40
DDR_B_D 41
DDR_B_D 42
DDR_B_D 43
DDR_B_D 44
DDR_B_D 45
DDR_B_D 46
DDR_B_D 47
DDR_B_D 48
DDR_B_D 49
DDR_B_D 50
DDR_B_D 51
DDR_B_D 52
DDR_B_D 53
DDR_B_D 54
DDR_B_D 55
DDR_B_D 56
DDR_B_D 57
DDR_B_D 58
DDR_B_D 59
DDR_B_D 60
DDR_B_D 61
DDR_B_D 62
DDR_B_D 63
DDR_B_B S0<12>
DDR_B_B S1<12>
DDR_B_B S2<12>
DDR_B_C AS#<12>
DDR_B_R AS#<12>
DDR_B_W E#<12>
DDR_B_BS0
DDR_B_B S1
DDR_B_B S2
DDR_B_C AS#
DDR_B_R AS#
DDR_B_W E#
AG1
AG4
AG3
AM6
AM4
AM3
AR10
AT10
AF3
AJ3
AK1
AJ4
AH4
AK3
AK4
AN2
AK5
AK2
AP3
AN5
AT4
AN6
AN4
AN3
AT5
AT6
AN7
AP6
AP8
AT9
AT7
AP9
AB1
AC5
AC6
B5
A5
C3
B3
E4
A6
A4
C4
D1
D2
F2
F1
C2
F5
F3
G4
H6
G2
J6
J3
G1
G5
J2
J1
J5
K2
L3
M1
K5
K4
M4
N5
W5
R7
Y7
JCPU1D
JCPU1D
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CAS#
SB_RAS#
SB_WE#
2
W8
SB_CK[0]
W9
SB_CK#[0]
M3
SB_CKE[0]
V7
SB_CK[1]
V6
SB_CK#[1]
M2
SB_CKE[1]
AB8
SB_CS#[0]
AD6
SB_CS#[1]
AC7
SB_ODT[0]
AD1
SB_ODT[1]
DDR_B_D M0
D4
SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
SB_DM[4]
SB_DM[5]
SB_DM[6]
SB_DM[7]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
DDR SYSTEM MEMORY - B
DDR SYSTEM MEMORY - B
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
E1
H3
K1
AH1
AL2
AR4
AT8
D5
F4
J4
L4
AH2
AL4
AR5
AR8
C5
E3
H4
M5
AG2
AL5
AP5
AR7
U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1
DDR_B_D M1
DDR_B_D M2
DDR_B_D M3
DDR_B_D M4
DDR_B_D M5
DDR_B_D M6
DDR_B_D M7
DDR_B_D QS#0
DDR_B_D QS#1
DDR_B_D QS#2
DDR_B_D QS#3
DDR_B_D QS#4
DDR_B_D QS#5
DDR_B_D QS#6
DDR_B_D QS#7
DDR_B_D QS0
DDR_B_D QS1
DDR_B_D QS2
DDR_B_D QS3
DDR_B_D QS4
DDR_B_D QS5
DDR_B_D QS6
DDR_B_D QS7
DDR_B_M A0
DDR_B_M A1
DDR_B_M A2
DDR_B_M A3
DDR_B_M A4
DDR_B_M A5
DDR_B_M A6
DDR_B_M A7
DDR_B_M A8
DDR_B_M A9
DDR_B_M A10
DDR_B_M A11
DDR_B_M A12
DDR_B_M A13
DDR_B_M A14
DDR_B_M A15
1
DDR_B_C LK0 <12>
DDR_B_C LK0# <12>
DDR_B_C KE0 <12>
DDR_B_C LK1 <12>
DDR_B_C LK1# <12>
DDR_B_C KE1 <12>
DDR_B_C S0# <12>
DDR_B_C S1# <12>
DDR_B_O DT0 <1 2>
DDR_B_O DT1 <1 2>
IC,AUB_CFD _rPGA,R0P9
IC,AUB_CFD _rPGA,R0P9
CONN@
CONN@
A A
Security Class ification
Security Class ification
Security Class ification
2009/09/ 21 2010/09/ 21
2009/09/ 21 2010/09/ 21
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2009/09/ 21 2010/09/ 21
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
IC,AUB_CFD _rPGA,R0P9
IC,AUB_CFD _rPGA,R0P9
CONN@
CONN@
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
PROCESSOR (3/6) DDRIII
PROCESSOR (3/6) DDRIII
PROCESSOR (3/6) DDRIII
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
B
B
B
Date: Sheet
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
NAT02 M/B LA-5154P Schematic
NAT02 M/B LA-5154P Schematic
NAT02 M/B LA-5154P Schematic
1
of
7 49Thursday, November 26, 2 009
7 49Thursday, November 26, 2 009
7 49Thursday, November 26, 2 009
1.0
1.0
1.0
5
JCPU1F
JCPU1F
+CPU_CORE
WW15 MOW
48A Continuous 18A
AG35
VCC1
AG34
VCC2
AG33
VCC3
AG32
D D
C C
B B
A A
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
Y35
VCC51
Y34
VCC52
Y33
VCC53
Y32
VCC54
Y31
VCC55
Y30
VCC56
Y29
VCC57
Y28
VCC58
Y27
VCC59
Y26
VCC60
V35
VCC61
V34
VCC62
V33
VCC63
V32
VCC64
V31
VCC65
V30
VCC66
V29
VCC67
V28
VCC68
V27
VCC69
V26
VCC70
U35
VCC71
U34
VCC72
U33
VCC73
U32
VCC74
U31
VCC75
U30
VCC76
U29
VCC77
U28
VCC78
U27
VCC79
U26
VCC80
R35
VCC81
R34
VCC82
R33
VCC83
R32
VCC84
R31
VCC85
R30
VCC86
R29
VCC87
R28
VCC88
R27
VCC89
R26
VCC90
P35
VCC91
P34
VCC92
P33
VCC93
P32
VCC94
P31
VCC95
P30
VCC96
P29
VCC97
P28
VCC98
P27
VCC99
P26
VCC100
1.1V RAIL POWER
1.1V RAIL POWER
CPU CORE SUPPLY
CPU CORE SUPPLY
POWER
POWER
CPU VIDS
CPU VIDS
SENSE LINES
SENSE LINES
Peak 21A
VTT0_1
VTT0_2
VTT0_3
VTT0_4
VTT0_5
VTT0_6
VTT0_7
VTT0_8
VTT0_9
VTT0_10
VTT0_11
VTT0_12
VTT0_13
VTT0_14
VTT0_15
VTT0_16
VTT0_17
VTT0_18
VTT0_19
VTT0_20
VTT0_21
VTT0_22
VTT0_23
VTT0_24
VTT0_25
VTT0_26
VTT0_27
VTT0_28
VTT0_29
VTT0_30
VTT0_31
VTT0_32
VTT0_33
VTT0_34
VTT0_35
VTT0_36
VTT0_37
VTT0_38
VTT0_39
VTT0_40
VTT0_41
VTT0_42
VTT0_43
VTT0_44
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
PROC_DPRSLPVR
VTT_SELECT
ISENSE
VCC_SENSE
VSS_SENSE
VTT_SENSE
VSS_SENSE_VTT
4
AH14
AH12
AH11
AH10
J14
J13
H14
H12
G14
G13
G12
G11
F14
F13
F12
F11
E14
E12
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15
AN33
PSI#
AK35
AK33
AK34
AL35
AL33
AM33
AM35
AM34
H_VTTVID1
G15
H_VTTVID1 = low, 1.1V
H_VTTVID1 = high, 1.05V
AN35
1 2
C1557 1000P_0402_50 V7K~D@C1557 1000P_0402_50V7K~D@
VCCSENSE_R
AJ34
VSSSENSE_R
AJ35
B15
VSS_SENSE_VTT
A15
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
1
1
C183
C183
C174
C174
2
2
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
C222
C222
22U_0805_6.3V6M~OK
22U_0805_6.3V6M~OK
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
330U_X_2VM_R6M~OK
330U_X_2VM_R6M~OK
1
+
+
C1010
C1010
C1009
C1009
2
330U_X_2VM_R6M~OK
330U_X_2VM_R6M~OK
22U_0805_6.3V6M~OK
22U_0805_6.3V6M~OK
1
1
C240
C240
2
2
IMVP_IMON <46>
R0.3 modify
R641 0_0402_5%~DR641 0_0402_5%~D
1 2
R642 0_0402_5%~DR642 0_0402_5%~D
1 2
R608 0_0402_5%~DR608 0_0402_5%~D
1 2
close to CPU side.
3
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
1
C192
C192
2
+1.1VS_VTT
1
+
+
C1011
C1011
2
330U_X_2VM_R6M~OK
330U_X_2VM_R6M~OK
+1.1VS_VTT
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
1
1
C203
C203
C195
C195
2
2
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
1
+
+
R1.0 modify
@
@
2
H_PSI# <46>
CPU_VID0 <46>
CPU_VID1 <46>
CPU_VID2 <46>
CPU_VID3 <46>
CPU_VID4 <46>
CPU_VID5 <46>
CPU_VID6 <46>
H_DPRSLPVR <46>
H_VTTVID1 <45>
1
C211
C211
2
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
CSC (Curre nt Sense C onfigurati on)
8/25
VTT Rail
Auburndale +1.1VS_VT T=1.05V
Clarksfiel d +1.1VS_V TT=1.1V
1 2
R643 100_0402_1%~DR643 100_0402_1%~D
VCCSENSE
VSSSENSE
1 2
VTT_SENSE <45>
R644 100_0402_1%~DR644 100_0402_1%~D
+1.1VS_VTT
1
C159
C159
2
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
H_DPRSLPVR
H_PSI#
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
R1066 1K_0402_1%~DR1066 1K_0402_1%~D
1 2
R1067 1K_0402_1%~D@R10 67 1K_0402_1%~D@
1 2
R1068 1K_0402_1%~DR1068 1K_0402_1%~D
1 2
R1069 1K_0402_1%~D@R10 69 1K_0402_1%~D@
1 2
R1070 1K_0402_1%~DR1070 1K_0402_1%~D
1 2
R1071 1K_0402_1%~D@R10 71 1K_0402_1%~D@
1 2
R343 1K_0402_1%~D@R343 1K_0402_1%~D@
1 2
R1072 1K_0402_1%~DR1072 1K_0402_1%~D
1 2
R1073 1K_0402_1%~D@R10 73 1K_0402_1%~D@
1 2
R1074 1K_0402_1%~DR1074 1K_0402_1%~D
1 2
R1075 1K_0402_1%~DR1075 1K_0402_1%~D
1 2
R1076 1K_0402_1%~D@R10 76 1K_0402_1%~D@
1 2
R1077 1K_0402_1%~D@R10 77 1K_0402_1%~D@
1 2
R1078 1K_0402_1%~DR1078 1K_0402_1%~D
1 2
R347 1K_0402_1%~DR347 1K_0402_1%~D
1 2
R1079 1K_0402_1%~D@R10 79 1K_0402_1%~D@
1 2
R348 1K_0402_1%~D@R348 1K_0402_1%~D@
1 2
R1080 1K_0402_1%~DR1080 1K_0402_1%~D
1 2
470U_D2_2VM_R4.5M~OK
470U_D2_2VM_R4.5M~OK
+CPU_CORE
VCCSENSE <46>
VSSSENSE <46>
+CPU_CORE
1
C191
C191
2
+1.1VS_VTT
+CPU_CORE
C1044
C1044
2
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
1
C201
C201
2
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
(Place these capacitors between inductor and socket on Bottom)
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
4 x 470uF(4.5mohm@100kHz; 4.0mohm@SRF)
1
+
+
2
C251
C251
470U_D2_2VM_R4.5M~OK
470U_D2_2VM_R4.5M~OK
TOP side (under inductor)
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
1
2
+CPU_CORE
1
2
1
+
+
2
+CPU-CORE
Decoupling
SPCAP,Polymer
MLCC 0805 X5R
1
C213
C213
2
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
1
C185
C185
2
(Place these capacitors under CPU socket, top layer)
+CPU_CORE
22U_0805_6.3V6M~OK
22U_0805_6.3V6M~OK
1
C1034
C1034
2
22U_0805_6.3V6M~OK
22U_0805_6.3V6M~OK
(Place these capacitors on CPU cavity, Bottom Layer)
+CPU_CORE
22U_0805_6.3V6M~OK
22U_0805_6.3V6M~OK
1
C1039
C1039
2
22U_0805_6.3V6M~OK
22U_0805_6.3V6M~OK
C1012
C1012
470U_D2_2VM_R4.5M~OK
470U_D2_2VM_R4.5M~OK
1
C233
C233
C194
C194
C1035
C1035
C1040
C1040
(Place these capacitors on CPU cavity, Bottom Layer)
C245
C245
2
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
1
C199
C199
2
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
1
C1036
C1036
2
22U_0805_6.3V6M~OK
22U_0805_6.3V6M~OK
1
C1041
C1041
2
22U_0805_6.3V6M~OK
22U_0805_6.3V6M~OK
1
+
+
2
C533
C533
470U_D2_2VM_R4.5M~OK
470U_D2_2VM_R4.5M~OK
1
2
1
2
C,uF
4X470uF 4m ohm/4
16X22uF
16X10uF 3m ohm/16
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
1
C190
C190
2
1
C208
C208
2
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
22U_0805_6.3V6M~OK
22U_0805_6.3V6M~OK
1
C1037
C1037
2
22U_0805_6.3V6M~OK
22U_0805_6.3V6M~OK
1
C1042
C1042
2
1
+
+
2
470U_D2_2VM_R4.5M~OK
470U_D2_2VM_R4.5M~OK
ESR, mohm
3m ohm/12
1
C200
C200
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
C214
C214
1
C1062
C1062
2
1
C1063
C1063
2
1
+
+
2
1
2
1
2
22U_0805_6.3V6M~OK
22U_0805_6.3V6M~OK
22U_0805_6.3V6M~OK
22U_0805_6.3V6M~OK
470U_D2_2VM_R4.5M~OK
470U_D2_2VM_R4.5M~OK
1
2
1
2
22U_0805_6.3V6M~OK
22U_0805_6.3V6M~OK
22U_0805_6.3V6M~OK
22U_0805_6.3V6M~OK
C263
C263
@
@
Stuffing Option
2X470uF
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
C212
C212
C223
C223
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
1
C1038
C1038
2
1
C1043
C1043
2
C167
C167
@
@
1
C232
C232
2
1
C239
C239
2
1
+
+
2
Security Classification
Security Classification
IC,AUB_CFD_rPGA,R0P9
IC,AUB_CFD_rPGA,R0P9
CONN@
CONN@
5
4
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2009/09/21 2010/09/21
2009/09/21 2010/09/21
2009/09/21 2010/09/21
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR (4/6) PWR,Bypass
PROCESSOR (4/6) PWR,Bypass
PROCESSOR (4/6) PWR,Bypass
NAT02 M/B LA-5154P Schematic
NAT02 M/B LA-5154P Schematic
NAT02 M/B LA-5154P Schematic
8 49Thursday, November 26, 2009
8 49Thursday, November 26, 2009
8 49Thursday, November 26, 2009
1
1.0
1.0
1.0
5
4
3
2
1
UMA
+VGFX_C ORE
JCPU1G
330U_X_ 2VM_R6M~OK
330U_X_ 2VM_R6M~OK
1
CU51
@+CU51
D D
C C
B B
@
2
1
+
+
+
CU52
CU52
2
330U_X_ 2VM_R6M~OK
330U_X_ 2VM_R6M~OK
22U_080 5_6.3V6M~OK
22U_080 5_6.3V6M~OK
22U_080 5_6.3V6M~OK
22U_080 5_6.3V6M~OK
22U_0805_6.3V6M~OK
22U_0805_6.3V6M~OK
CU4
CU4
1
2
+1.1VS_V TT
C179
C179
+1.1VS_V TT
C177
C177
22U_0805_6.3V6M~OK
22U_0805_6.3V6M~OK
1
2
1
2
1
2
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
CU5
CU5
CU1
CU1
1
1
2
2
1
C178
C178
22U_080 5_6.3V6M~OK
22U_080 5_6.3V6M~OK
2
1
C176
C176
22U_080 5_6.3V6M~OK
22U_080 5_6.3V6M~OK
2
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
CU6
CU6
JCPU1G
AT21
VAXG1
AT19
VAXG2
AT18
VAXG3
AT16
VAXG4
AR21
VAXG5
AR19
VAXG6
AR18
VAXG7
AR16
VAXG8
AP21
VAXG9
AP19
VAXG10
AP18
VAXG11
AP16
VAXG12
AN21
VAXG13
AN19
VAXG14
AN18
VAXG15
AN16
VAXG16
AM21
VAXG17
AM19
VAXG18
AM18
VAXG19
AM16
VAXG20
AL21
VAXG21
AL19
VAXG22
AL18
VAXG23
AL16
VAXG24
AK21
VAXG25
AK19
VAXG26
AK18
VAXG27
AK16
VAXG28
AJ21
VAXG29
AJ19
VAXG30
AJ18
VAXG31
AJ16
VAXG32
AH21
VAXG33
AH19
VAXG34
AH18
VAXG35
AH16
VAXG36
J24
VTT1_45
J23
VTT1_46
H25
VTT1_47
K26
VTT1_48
J27
VTT1_49
J26
VTT1_50
J25
VTT1_51
H27
VTT1_52
G28
VTT1_53
G27
VTT1_54
G26
VTT1_55
F26
VTT1_56
E26
VTT1_57
E25
VTT1_58
IC,AUB_CFD _rPGA,R0P9
IC,AUB_CFD _rPGA,R0P9
CONN@
CONN@
15A
VAXG_SENSE
VSSAXG_SENSE
SENSE
LINES
SENSE
LINES
GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
3A
GRAPHICS VIDs
GRAPHICS VIDs
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]
GFX_VR_EN
GFX_DPRSLPVR
GFX_IMON
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
DDR3 - 1.5V RAILS
DDR3 - 1.5V RAILS
VTT0_59
VTT0_60
VTT0_61
VTT0_62
VTT1_63
VTT1_64
VTT1_65
1.1V1.8V
1.1V1.8V
VTT1_66
VTT1_67
VTT1_68
VCCPLL1
VCCPLL2
VCCPLL3
GRAPHICS
GRAPHICS
FDI PEG & DMI
FDI PEG & DMI
POWER
POWER
0.6A
11/17 follow In tel suggest to change RU93 to 470 ohm
UMA
AR22
AT22
AM22
AP22
AN22
AP23
AM23
AP24
AN24
AR25
AT25
AM24
AJ1
AF1
AE7
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1
P10
N10
L10
K10
J22
J20
J18
H21
H20
H19
L26
L27
M26
VCC_AXG _SENSE <48 >
VSS_AXG _SENSE <48>
GFXVR_V ID_0 <48 >
GFXVR_V ID_1 <48 >
GFXVR_V ID_2 <48 >
GFXVR_V ID_3 <48 >
GFXVR_V ID_4 <48 >
GFXVR_V ID_5 <48 >
GFXVR_V ID_6 <48 >
GFXVR_D PRSLPVR_R
C193
C193
1U_0402 _6.3V4Z~D
1U_0402 _6.3V4Z~D
+1.1VS_V TT
1
2
+1.8VS_V CCSFR
C175
C175
1U_0402 _6.3V4Z~D
1U_0402 _6.3V4Z~D
RU93 470_0402_5%~DRU93 470 _0402_5%~D
1 2
1 2
RU1 0_0402_5%~DRU1 0_ 0402_5%~D
1U_0402 _6.3V4Z~D
1U_0402 _6.3V4Z~D
1
C196
C196
2
+1.1VS_V TT
C158
C158
22U_080 5_6.3V6M~OK
22U_080 5_6.3V6M~OK
1
C182
C182
2
1U_0402 _6.3V4Z~D
1U_0402 _6.3V4Z~D
1U_0402 _6.3V4Z~D
1U_0402 _6.3V4Z~D
1
1
C202
C202
C209
C209
2
2
1U_0402 _6.3V4Z~D
1U_0402 _6.3V4Z~D
1
C160
C160
10U_080 5_6.3V6M~D
10U_080 5_6.3V6M~D
2
2.2U_060 3_6.3V6K~D
2.2U_060 3_6.3V6K~D
1
1
C180
C180
C168
C168
2
2
4.7U_080 5_10V4Z~D
4.7U_080 5_10V4Z~D
GFXVR_E N < 48>
GFXVR_D PRSLPVR <48>
GFXVR_IMO N <48>
22U_080 5_6.3V6M~OK
22U_080 5_6.3V6M~OK
1
1
C184
C184
C216
C216
2
2
1U_0402 _6.3V4Z~D
1U_0402 _6.3V4Z~D
1
1
C165
C165
2
2
22U_080 5_6.3V6M~OK
22U_080 5_6.3V6M~OK
+1.5V_CP U_DDR +1.5V
1
1
C224
C224
2
2
22U_080 5_6.3V6M~OK
22U_080 5_6.3V6M~OK
R228
R228
0.022_08 05_1%~OK
0.022_08 05_1%~OK
1 2
C1033
C1033
1 2
0.1U_040 2_16V7K~D
0.1U_040 2_16V7K~D
C1143
C1143
1 2
0.1U_040 2_16V7K~D
0.1U_040 2_16V7K~D
C1144
C1144
1 2
0.1U_040 2_16V7K~D
0.1U_040 2_16V7K~D
C1145
C1145
1 2
0.1U_040 2_16V7K~D
0.1U_040 2_16V7K~D
PJP12
PJP12
JUMP_43 X118@
JUMP_43 X118@
2
1
+
+
C250
C250
2
330U_D2_2V_Y~OK
330U_D2_2V_Y~OK
+1.8VS
112
PJP13
PJP13
JUMP_43 X118@
JUMP_43 X118@
112
PJP14
PJP14
JUMP_43 X118@
JUMP_43 X118@
112
2
2
A A
Security Class ification
Security Class ification
Security Class ification
2009/09/ 21 2010/09/ 21
2009/09/ 21 2010/09/ 21
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2009/09/ 21 2010/09/ 21
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
PROCESSOR (5/6) PWR
PROCESSOR (5/6) PWR
PROCESSOR (5/6) PWR
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
Custom
Custom
Custom
NAT02 M/B LA-5154P Schematic
NAT02 M/B LA-5154P Schematic
NAT02 M/B LA-5154P Schematic
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
9 49Thursday, November 26, 2 009
9 49Thursday, November 26, 2 009
9 49Thursday, November 26, 2 009
1
1.0
1.0
1.0
5
JCPU1H
JCPU1H
AT20
VSS1
AT17
VSS2
AR31
VSS3
AR28
VSS4
AR26
VSS5
AR24
VSS6
D D
C C
B B
AR23
AR20
AR17
AR15
AR12
AR9
AR6
AR3
AP20
AP17
AP13
AP10
AP7
AP4
AP2
AN34
AN31
AN23
AN20
AN17
AM29
AM27
AM25
AM20
AM17
AM14
AM11
AM8
AM5
AM2
AL34
AL31
AL23
AL20
AL17
AL12
AL9
AL6
AL3
AK29
AK27
AK25
AK20
AK17
AJ31
AJ23
AJ20
AJ17
AJ14
AJ11
AJ8
AJ5
AJ2
AH35
AH34
AH33
AH32
AH31
AH30
AH29
AH28
AH27
AH26
AH20
AH17
AH13
AH9
AH6
AH3
AG10
AF8
AF4
AF2
AE35
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
4
VSS
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30
3
JCPU1I
JCPU1I
K27
VSS161
K9
VSS162
K6
VSS163
K3
VSS164
J32
VSS165
J30
VSS166
J21
VSS167
J19
VSS168
H35
VSS169
H32
VSS170
H28
VSS171
H26
VSS172
H24
VSS173
H22
VSS174
H18
VSS175
H15
VSS176
H13
VSS177
H11
VSS178
H8
VSS179
H5
VSS180
H2
VSS181
G34
VSS182
G31
VSS183
G20
VSS184
G9
VSS185
G6
VSS186
G3
VSS187
F30
VSS188
F27
VSS189
F25
VSS190
F22
VSS191
F19
VSS192
F16
VSS193
E35
VSS194
E32
VSS195
E29
VSS196
E24
VSS197
E21
VSS198
E18
VSS199
E13
VSS200
E11
VSS201
E8
VSS202
E5
VSS203
E2
VSS204
D33
VSS205
D30
VSS206
D26
VSS207
D9
VSS208
D6
VSS209
D3
VSS210
C34
VSS211
C32
VSS212
C29
VSS213
C28
VSS214
C24
VSS215
C22
VSS216
C20
VSS217
C19
VSS218
C16
VSS219
B31
VSS220
B25
VSS221
B21
VSS222
B18
VSS223
B17
VSS224
B13
VSS225
B11
VSS226
B8
VSS227
B6
VSS228
B4
VSS229
A29
VSS230
A27
VSS231
A23
VSS232
A9
VSS233
2
VSS
VSS
NCTF
NCTF
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
AT35
AT1
AR34
B34
B2
B1
A35
1
IC,AUB_CFD _rPGA,R0P9
IC,AUB_CFD _rPGA,R0P9
IC,AUB_CFD _rPGA,R0P9
CONN@
CONN@
A A
Security Class ification
Security Class ification
Security Class ification
2009/09/ 21 2010/09/ 21
2009/09/ 21 2010/09/ 21
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2009/09/ 21 2010/09/ 21
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
IC,AUB_CFD _rPGA,R0P9
CONN@
CONN@
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR (6/6) VSS
PROCESSOR (6/6) VSS
PROCESSOR (6/6) VSS
NAT02 M/B LA-5154P Schematic
NAT02 M/B LA-5154P Schematic
NAT02 M/B LA-5154P Schematic
10 49Thursday, November 26, 2 009
10 49Thursday, November 26, 2 009
10 49Thursday, November 26, 2 009
1
1.0
1.0
1.0
5
M1 Circuit M3 Circuit
+1.5V
12
R170
R170
1K_0402_1%~D
1K_0402_1%~D
12
D D
+V_DDR3_DIMMA_REF
+V_DDR3_DIMMA_REF
R169
R169
1K_0402_1%~D
1K_0402_1%~D
M2 Circuit
+3V
1
C164
@C164
@
1U_0402_6.3V4Z~D
1U_0402_6.3V4Z~D
C C
Layout Note:
Place near JDIMM1
B B
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
Layout Note:
Place near JDIMM1.203 & JDIMM1.204
A A
PCH_SMBCLK
PCH_SMBDATA
PM_SLP_S4#<17>
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
1
C204
C204
C186
C186
2
+0.75VS
1U_0603_10V4Z~D
1U_0603_10V4Z~D
2
C1015
C1015
1
1U_0603_10V4Z~D
1U_0603_10V4Z~D
2
+1.5V
1
2
U45
@U45
@
1
VDD
2
GND
3
SCL
ISL90727WIE627Z-TK_SC70-6
ISL90727WIE627Z-TK_SC70-6
Layout Note: Place these 4 Caps near Command
and Control signals of DIMMA
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
1
C187
C187
C171
C171
2
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
1U_0603_10V4Z~D
1U_0603_10V4Z~D
2
2
C280
C280
C1016
C1016
1
1
1U_0603_10V4Z~D
1U_0603_10V4Z~D
5
6
RH
5
RW
4
SDA
+5VALW
12
R226
@R226
@
100K_0402_5%~D
100K_0402_5%~D
3
Q48B
@Q48B
@
2N7002DW-7-F_SOT363-6~D
2N7002DW-7-F_SOT363-6~D
5
4
1
1
C170
C170
2
2
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
1
2
C1017
C1017
C281
C281
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
2
1
VREF_RW_POT0
PP_S4GT
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
C205
C205
1 2
0_0402_5%~D
0_0402_5%~D
+1.5V
12
R223
@R223
@
12.1K_0402_1%~D
12.1K_0402_1%~D
12
R222
@R222
@
12.1K_0402_1%~D
12.1K_0402_1%~D
1
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
DDR_A_DQS#[0..7]<7>
DDR_A_D[0..63]<7>
DDR_A_DM[0..7]<7>
DDR_A_DQS[0..7]<7>
DDR_A_MA[0..15]<7>
PCH_SMBCLK<6,12,16>
PCH_SMBDATA<6,12,16>
+V_DDR3_DIMMA_REF2 +V_DD R3_DIMMB_REF2
R1245
R1245
@
@
+5VALW
C153
@C153
@
1 2
8
3
P
+
1
0
2
-
G
U46A
@ U46A
@
LM358DT_SO8
LM358DT_SO8
4
VREF_OPAMP_POT0
PP_S4GT<12>
12
R230
@R230
@
1M_0402_5%~D
1M_0402_5%~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
C1045
C1045
C1013
C1013
2
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
+V_DDR3_DIMMA_REF
PCH_SMBCLK
PCH_SMBDATA
R1229
R1229
1 2
0_0402_5%~D
0_0402_5%~D
@
@
1U_0402_6.3V4Z~D
1U_0402_6.3V4Z~D
R221
@R221
@
2.2_0402_5%~D
2.2_0402_5%~D
1 2
10_0402_5%~D
10_0402_5%~D
PP_S4GT
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
1
C1046
C1046
2
2
1 3
Q37
Q37
D
D
BSS138_SOT23~D
BSS138_SOT23~D
4
H_DIMMA_REF<5>
+V_DDR3_DIMMA_REF
+V_DDR3_DIMMB_REF+V_DDR3_DIMMA_REF
R1246
R1246
1 2
0_0402_5%~D
0_0402_5%~D
@
@
2008/9/8 #40075 5
Calpella Clarks field
DDR3 SO-DIMM
VREFDQ Platform
Design Guide Ch ange Details
VREF_POT0_R
12
1
C163
@C163
R220
@R220
@
2
C1064
C1064
2
G
G
4
S
S
@
1U_0402_6.3V4Z~D
1U_0402_6.3V4Z~D
2
PP_S4GT_Q_0
61
Q48A
@Q48A
@
2N7002DW-7-F_SOT363-6~D
2N7002DW-7-F_SOT363-6~D
1
+
+
C197
C197
330U_D2_2V_Y~OK
330U_D2_2V_Y~OK
2
R313
@ R 313
@
100K_0402_5%~D
100K_0402_5%~D
1 2
VREF_POT0_R
M1 Circuit
1K_0402_1%~D
1K_0402_1%~D
DDR_RST_GATE <6,12,20>
H_DIMMA_REF <5>
3
R178 0_0402_5%~DR178 0_0402_5%~D
1 2
R179 0_0402_5%~DR179 0_0402_5%~D
1 2
R227 0_0402_5%~D@R227 0_0402_5%~D@
1 2
1
1
C112
C124
C124
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
+1.5V
12
R1247
R1247
12
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+V_DDR3_DIMMA_REF2
+V_DDR3_DIMMA_REF2
R1248
R1248
1K_0402_1%~D
1K_0402_1%~D
+3VS
2.2U_0603_6.3V4Z~D
2.2U_0603_6.3V4Z~D
Issued Date
Issued Date
Issued Date
C112
2.2U_0805_16V4Z~D
2.2U_0805_16V4Z~D
2
2
DDR_A_CKE0<7>
DDR_A_BS2<7>
DDR_A_CLK0<7>
DDR_A_CLK0#<7>
DDR_A_BS0<7>
DDR_A_WE#<7>
DDR_A_CAS#<7> DDR_A_ODT0 <7>
DDR_A_CS1#<7>
1
C1014
C1014
2
2009/09/21 2010/09/21
2009/09/21 2010/09/21
2009/09/21 2010/09/21
3
VREF_DQA
DDR_A_D0
DDR_A_D1
DDR_A_DM0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27 DDR_A_D31
DDR_A_CKE0
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_CLK0
DDR_A_CLK0#
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDR_A_CS1#
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
R1057 10K_0402_5%~DR1057 10K_0402_5%~D
1 2
1
C276
C276
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
+1.5V +1.5V
11
13
15
17
19
21
23
25
27
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
12
R1081
R1081
10K_0402_5%~D
10K_0402_5%~D
Compal Secret Data
Compal Secret Data
Compal Secret Data
203
205
Deciphered Date
Deciphered Date
Deciphered Date
2
JDIMM1
JDIMM1
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS129RESET#
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS2261DQS#3
DM3
VSS23
DQ26
DQ27
VSS25
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
G1
FOX_AS0A626-U4RN-7F
FOX_AS0A626-U4RN-7F
CONN@
CONN@
2
DQS#0
VSS10
VSS12
VSS14
VSS16
VSS17
VSS19
VSS21
VSS24
VSS26
VDD10
VDD12
VDD14
VDD16
VDD18
VREF_CA
VSS28
VSS30
VSS31
VSS33
VSS35
DQS#5
VSS38
VSS40
VSS42
VSS43
VSS45
VSS47
DQS#7
VSS50
VSS52
EVENT#
DQ4
DQ5
VSS3
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
DM1
DQ14
DQ15
DQ20
DQ21
DM2
DQ22
DQ23
DQ28
DQ29
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
CK1#
RAS#
ODT0
ODT1
NC2
DQ36
DQ37
DM4
DQ38
DQ39
DQ44
DQ45
DQS5
DQ46
DQ47
DQ52
DQ53
DM6
DQ54
DQ55
DQ60
DQ61
DQS7
DQ62
DQ63
SDA
VTT2
CK1
BA1
SCL
1
2
DDR_A_D4
4
DDR_A_D5
6
8
DDR_A_DQS#0
10
DDR_A_DQS0
12
14
DDR_A_D6
16
DDR_A_D7
18
20
DDR_A_D12
22
DDR_A_D13
24
26
DDR_A_DM1
28
SM_DRAMRST#
30
32
DDR_A_D14
34
DDR_A_D15
36
38
DDR_A_D20
40
DDR_A_D21
42
44
DDR_A_DM2
46
48
DDR_A_D22
50
DDR_A_D23
52
54
DDR_A_D28
56
DDR_A_D29
58
60
DDR_A_DQS#3
62
DDR_A_DQS3
64
66
DDR_A_D30
68
70
72
DDR_A_CKE1
74
76
DDR_A_MA15
78
A15
A14
A11
A7
A6
A4
A2
A0
S0#
G2
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_CLK1
DDR_A_CLK1#
DDR_A_BS1
DDR_A_RAS#
DDR_A_CS0#
DDR_A_ODT0
DDR_A_ODT1
DDR_VREF_CA_DIMMA
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
PM_EXTTS#0_1
SMBDATA
SMBCLK
+0.75VS
+1.5V
R56
R56
1K_0402_5%~D
1K_0402_5%~D
1 2
DDR_A_CKE1 <7>
DDR_A_CLK1 <7>
DDR_A_CLK1# <7>
DDR_A_BS1 <7>
DDR_A_RAS# <7>
DDR_A_CS0# <7>
DDR_A_ODT1 <7>
R1056 0_0402_5%~DR1056 0_0402_5%~D
1 2
2.2U_0603_6.3V4Z~D
2.2U_0603_6.3V4Z~D
PM_EXTTS#0_1 <6,12>
SMBDATA <12,13,14,16>
SMBCLK <12,13,14,16>
SM_DRAMRST# <6,12>
1
C230
C230
2
+V_DDR3_DIMMA_REF2
1
C220
C220
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
DDR3 SO-DIMM A
Standard Type
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DDRIII-SODIMM SLOT1
DDRIII-SODIMM SLOT1
DDRIII-SODIMM SLOT1
NAT02 M/B LA-5154P Schematic
NAT02 M/B LA-5154P Schematic
NAT02 M/B LA-5154P Schematic
1
1.0
1.0
1.0
of
11 49Thursday, November 26, 2009
11 49Thursday, November 26, 2009
11 49Thursday, November 26, 2009
5
M1 Circuit
+1.5V
12
R1230
R1230
1K_0402_1%~D
1K_0402_1%~D
D D
+V_DDR3_DIMMB_REF
M2 Circuit
C C
B B
A A
@C156
@
1U_0402_6.3V4Z~D
1U_0402_6.3V4Z~D
PCH_SMBCLK
PCH_SMBDATA
C172
C172
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
Layout Note:
Place near JDIMM2.203 & JDIMM2.204
1U_0603_10V4Z~D
1U_0603_10V4Z~D
12
Q44
Q44
BSS138_SOT23~D
BSS138_SOT23~D
+3V
1
C156
2
Layout Note:
Place near JDIMM2
+1.5V
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
1
1
C188
C188
2
2
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
+0.75VS
C1018
C1018
C282
C282
2
1
1U_0603_10V4Z~D
1U_0603_10V4Z~D
+V_DDR3_DIMMB_REF
+V_DDR3_DIMMB_REF
R1231
R1231
1K_0402_1%~D
1K_0402_1%~D
2
G
G
1 3
D
S
D
S
R321
@ R321
@
100K_0402_5%~D
100K_0402_5%~D
1 2
U8
@U8
@
1
VDD
2
GND
3
SCL
ISL90728WIE627Z-TK_SC70-6
ISL90728WIE627Z-TK_SC70-6
1
C206
C206
2
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
1U_0603_10V4Z~D
1U_0603_10V4Z~D
C283
C283
2
2
1
1
5
6
RH
5
RW
4
SDA
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
1
C173
C173
C189
C189
2
C1019
C1019
2
1
1U_0603_10V4Z~D
1U_0603_10V4Z~D
1
2
C298
C298
1
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
2
2008/9/8 #40075 5
Calpella Clarks field
DDR3 SO-DIMM
VREFDQ Platform
Design Guide Ch ange Details
DDR_RST_GATE <6,11,20>
H_DIMMB_REF <5>
+1.5V
12
R196
@R196
@
12.1K_0402_1%~D
12.1K_0402_1%~D
VREF_RW_POT1
12
R197
@R197
@
12.1K_0402_1%~D
12.1K_0402_1%~D
Layout Note: Place these 4 Caps near Command
and Control signals of DIMMA
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1
C1047
C1047
C207
C207
2
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
+5VALW
8
5
P
+
6
-
G
4
VREF_OPAMP_POT1
PP_S4GT<11>
1
1
C1048
C1048
2
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
DDR_B_DQS#[0..7]<7>
DDR_B_D[0..63]<7>
DDR_B_DM[0..7]<7>
DDR_B_DQS[0..7]<7>
DDR_B_MA[0..15]<7>
PCH_SMBDATA<6,11,16>
U46B
@U46B
@
LM358DT_SO8
LM358DT_SO8
7
0
PP_S4GT
1
C1049
C1049
2
4
PCH_SMBCLK<6,11,16>
R193
@R193
@
1 2
2.2_0402_5%~D
2.2_0402_5%~D
R194
@R194
@
10_0402_5%~D
10_0402_5%~D
2
G
G
1
C1050
C1050
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
4
+V_DDR3_DIMMB_REF
H_DIMMB_REF<5>
PCH_SMBCLK
PCH_SMBDATA
VREF_POT1_R
12
1
2
PP_S4GT_Q_1
13
D
D
Q49
@
Q49
@
2N7002LT1G_SOT23-3
2N7002LT1G_SOT23-3
S
S
1
+
+
C198
C198
330U_D2_2V_Y~OK
330U_D2_2V_Y~OK
2
VREF_POT1_R
C128
@C128
@
1U_0402_6.3V4Z~D
1U_0402_6.3V4Z~D
3
M1 Circuit
R166 0_0402_5%~DR166 0_0402_5%~D
1 2
M3 Circuit
R165 0_0402_5%~DR165 0_0402_5%~D
1 2
R186 0_0402_5%~D@R186 0_0402_5%~D@
1 2
C110
C110
2.2U_0805_16V4Z~D
2.2U_0805_16V4Z~D
DDR_B_BS2<7>
DDR_B_BS0<7>
DDR_B_WE#<7>
DDR_B_CAS#<7> DDR_B_ODT0 <7>
DDR_B_CS1#<7>
+3VS
C1020
C1020
2.2U_0603_6.3V4Z~D
2.2U_0603_6.3V4Z~D
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
VREF_DQB
DDR_B_D0
DDR_B_D1
DDR_B_DM0
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
1
1
C122
C122
2
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
DDR_B_CLK0<7>
DDR_B_CLK0#<7>
1
1
C277
C277
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
2
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_CLK0
DDR_B_CLK0#
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_B_CS1#
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_DM7
DDR_B_D58
DDR_B_D59
R1059 10K_0402_5%~DR1059 10K_0402_5%~D
1 2
1 2
R1082 10K_0402_5%~DR1082 10K_0402_5%~D
2009/09/21 2010/09/21
2009/09/21 2010/09/21
2009/09/21 2010/09/21
+1.5V
3
5
7
9
11
13
15
17
19
21
23
25
27
33
35
39
41
45
47
49
51
53
55
57
59
63
67
69
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
JDIMM2
JDIMM2
FOX_AS0A626-U8RN-7F
FOX_AS0A626-U8RN-7F
CONN@
CONN@
2
VREF_DQ1VSS1
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS129RESET#
VSS1131VSS12
DQ10
DQ11
VSS1337VSS14
DQ16
DQ17
VSS1543VSS16
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS2261DQS#3
DM3
VSS2365VSS24
DQ26
DQ27
VSS2571VSS26
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
G1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
DQ14
DQ15
DQ20
DQ21
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
VDD10
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
VTT2
2
CK1
BA1
SCL
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
A15
80
A14
82
84
A11
86
A7
88
90
A6
92
A4
94
96
A2
98
A0
100
102
104
106
108
110
112
114
S0#
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
G2
+1.5V
DDR_B_D4
DDR_B_D5
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13
DDR_B_DM1
SM_DRAMRST#
DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDR_B_CKE1DDR_B_CKE0
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_CLK1
DDR_B_CLK1#
DDR_B_BS1
DDR_B_RAS#
DDR_B_CS0#
DDR_B_ODT0
DDR_B_ODT1
DDR_VREF_CA_DIMMB
DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
PM_EXTTS#0_1
SMBDATA
SMBCLK
1
SM_DRAMRST# <6,11>
DDR_B_CKE1 <7>DDR_B_CKE0<7>
DDR_B_CLK1 <7>
DDR_B_CLK1# <7>
DDR_B_BS1 <7>
DDR_B_RAS# <7>
DDR_B_CS0# <7>
DDR_B_ODT1 <7>
R1058 0_0402_5%~DR1058 0_0402_5%~D
1 2
2.2U_0603_6.3V4Z~D
2.2U_0603_6.3V4Z~D
M1 Circuit
1K_0402_1%~D
1K_0402_1%~D
PM_EXTTS#0_1 <6,11>
SMBDATA <11,13,14,16>
+0.75VS
SMBCLK <11 ,13,14,16>
R1249
R1249
+V_DDR3_DIMMB_REF2
1
C231
C231
2
+1.5V
12
+V_DDR3_DIMMB_REF2
12
R1250
R1250
1K_0402_1%~D
1K_0402_1%~D
1
C221
C221
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
+V_DDR3_DIMMB_REF2
DDR3 SO-DIMM B
Standard Type
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DDRIII-SODIMM SLOT2
DDRIII-SODIMM SLOT2
DDRIII-SODIMM SLOT2
NAT02 M/B LA-5154P Schematic
NAT02 M/B LA-5154P Schematic
NAT02 M/B LA-5154P Schematic
12 49Thursday, November 26, 2009
12 49Thursday, November 26, 2009
12 49Thursday, November 26, 2009
1
1.0
1.0
1.0
A
B
C
D
E
F
G
H
+CLK_VD DSRC
L80
L79
+1.05VS
1 1
CLK_BUF _DREF_96M<16>
CLK_BUF _DREF_96M#<16>
2 2
3 3
CLK_BUF _PCIE_SATA<16>
CLK_BUF _PCIE_SATA#<16>
CLK_BUF _CPU_DMI< 16>
CLK_BUF _CPU_DMI#<16>
L79
FBMA-L11 -201209-221LMA 30T_0805
FBMA-L11 -201209-221LMA 30T_0805
1
C1051
C1051
10U_080 5_10V4Z~D
10U_080 5_10V4Z~D
2
CLK_BUF _DREF_96M
CLK_BUF _DREF_96M#
CLK_BUF _PCIE_SATA
+CLK_VD D
Silego Have Int ernal Pull-Up
R627 10K_0 402_5%~DR6 27 10K_0402_5%~D
+CLK_VD DSRC
R1140 10K_0402_ 5%~D
R1140 10K_0402_ 5%~D
R634 10K_0 402_5%~DR6 34 10K_0402_5%~D
1 2
@
@
1 2
1 2
12
1
C1052
C1052
10U_080 5_10V4Z~D
10U_080 5_10V4Z~D
2
0.1U_040 2_16V4Z~D
0.1U_040 2_16V4Z~D
Integrated 33oh m Resistor
R1004 0_ 0402_5%~DR1004 0_0402_5%~ D
1 2
R1005 0_ 0402_5%~DR1005 0_0402_5%~ D
1 2
R1006 0_ 0402_5%~DR1006 0_0402_5%~ D
1 2
R1008 0_ 0402_5%~DR1008 0_0402_5%~ D
1 2
R1010 0_ 0402_5%~DR1010 0_0402_5%~ D
1 2
R1011 0_ 0402_5%~DR1011 0_0402_5%~ D
1 2
Integrated 33oh m Resistor
H_STP_C PU#
REF_0/CP U_SEL
1
1
C979
C979
C1053
C1053
0.1U_040 2_16V4Z~D
0.1U_040 2_16V4Z~D
2
2
+CLK_VD DSRC +CLK_VD D
+CLK_VD D
CLK_BUF _DREF_96M_R
CLK_BUF _DREF_96M#_R
CLK_BUF _PCIE_SATA_R
CLK_BUF _PCIE_SATA#_RCLK_BUF _PCIE_SATA#
CLK_BUF _CPU_DMI_RCLK_BUF_C PU_DMI
CLK_BUF _CPU_DMI#_RCLK_BUF _CPU_DMI#
H_STP_C PU#
1
CU53
@C U53
@
47P_040 2_50V8J~D
47P_040 2_50V8J~D
2
Clock Generator
U49
U49
1
VDD_USB_48
2
VSS_48M
3
DOT_96
4
DOT_96#
5
VDD_27
6
27MHZ
7
27MHZ_SS
8
USB_48
9
VSS_27M
10
SATA
11
SATA#
12
VSS_SRC
13
SRC_1
14
SRC_1#
15
VDD_SRC_IO
16
CPU_STOP#
33
TGND
SLG8SP5 87VTR_QFN32_ 5X5
SLG8SP5 87VTR_QFN32_ 5X5
IDT: 9LRS3191AKLFT
SILEGO: SLG8SP585
REF_0/CPU_SEL
CKPWRGD/PD#
+3VS
SCL
SDA
VDD_REF
XTAL_IN
XTAL_OUT
VSS_REF
VDD_CPU
CPU_0
CPU_0#
VSS_CPU
CPU_1
CPU_1#
VDD_CPU_IO
VDD_SRC
L80
FBMA-L11 -201209-221LMA 30T_0805
FBMA-L11 -201209-221LMA 30T_0805
1
C1065
C1065
10U_080 5_10V4Z~D
10U_080 5_10V4Z~D
2
+CLK_VD DSRC
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
SMBCLK
SMBDATA
REF_0/CP U_SEL
CLK_XTA L_IN
CLK_XTA L_OUT
CK505_P WRGD
CLK_BUF _CPU_BCLK_R
CLK_BUF _CPU_BCLK#_R
IDT Have Intern al Pull-Down
CPU_1PIN 30 CPU_0
(Default)
0 133MHz
1
100MHz 100MHz
133MHz
+CLK_VD D
0.1U_040 2_16V4Z~D
12
0.1U_040 2_16V4Z~D
1
C1061
C1061
2
10U_080 5_10V4Z~D
10U_080 5_10V4Z~D
R633 33_04 02_5%~DR633 33_04 02_5%~D
1 2
R1.0 modify
R1007 0_ 0402_5%~DR1007 0_0402_5%~ D
1 2
R1009 0_ 0402_5%~DR1009 0_0402_5%~ D
1 2
Integrated 33oh m Resistor
+CLK_VD D
R631
R631
10K_040 2_5%~D
10K_040 2_5%~D
1 2
CK505_P WRGD
13
D
D
2
G
G
Q45
Q45
S
S
2N7002L T1G_SOT23-3
2N7002L T1G_SOT23-3
CLK_XTA L_IN
1M_0402 _5%~D
1M_0402 _5%~D
CLK_XTA L_OUT
0.1U_040 2_16V4Z~D
0.1U_040 2_16V4Z~D
1
1
C1055
C1055
C1054
C1054
2
2
0.1U_040 2_16V4Z~D
0.1U_040 2_16V4Z~D
C1109
C1109
12
R1141
@R1141
@
1
1
C1056
C1056
2
0.1U_040 2_16V4Z~D
0.1U_040 2_16V4Z~D
10P_040 2_50V8J~D
10P_040 2_50V8J~D
1 2
@
@
CLK_BUF _CPU_BCLK
CLK_BUF _CPU_BCLK#
R632
R632
0_0402_ 5%~D
0_0402_ 5%~D
@
@
1 2
CLK_ENA BLE# <46>
C1059 33 P_0402_50V8 J~DC1059 33P_0402_50 V8J~D
12
Y6
Y6
14.31818 MHz_20P_FSX8L 14.318181M20F DB~OK
14.31818 MHz_20P_FSX8L 14.318181M20F DB~OK
C1060 33 P_0402_50V8 J~DC1060 33P_0402_50 V8J~D
C1057
C1057
2
VGATE < 17,31,46>
12
12
1
C1058
C1058
0.1U_040 2_16V4Z~D
0.1U_040 2_16V4Z~D
2
1
2
SMBCLK <11,12,14,16>
SMBDATA <11 ,12,14,16>
CLK_BUF _ICH_14M <1 6>
CLK_BUF _CPU_BCLK <16>
CLK_BUF _CPU_BCLK# <16>
CU54
@C U54
@
47P_040 2_50V8J~D
47P_040 2_50V8J~D
4 4
Security Class ification
Security Class ification
Security Class ification
2009/09/ 21 2010/09/ 21
2009/09/ 21 2010/09/ 21
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
2009/09/ 21 2010/09/ 21
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
E
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
F
Date: Sheet of
Compal Electronics, Inc.
Clock Generator (CK505)
Clock Generator (CK505)
Clock Generator (CK505)
NAT02 M/B LA-5154P Schematic
NAT02 M/B LA-5154P Schematic
NAT02 M/B LA-5154P Schematic
G
13 49Thursday, November 26, 2 009
13 49Thursday, November 26, 2 009
13 49Thursday, November 26, 2 009
H
1.0
1.0
1.0
FAN Control circuit
EN_DFAN1<31>
FAN_SPEED1<31>
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
EN_DFAN1
+3VS
R141
R141
10K_0402_5%~D
10K_0402_5%~D
C98
C98
12
2
1
+FAN1_POWER
C77
C77
10U_1206_16V4Z~D
10U_1206_16V4Z~D
12
C91
C91
1000P_0402_50V7K~D
1000P_0402_50V7K~D
12
+5VS
40mil
+FAN1_POWER
1 2
C96 10U_1206_16V4Z~DC96 10U_1206_16V4Z~D
U7
U7
1
VEN
2
3
4
MOLEX_53261-0371~D
MOLEX_53261-0371~D
GND
VIN
GND
GND
VO
GND
VSET
RT9027BPS_SO8
RT9027BPS_SO8
JFAN1
JFAN1
1
1
2
2
G
33G
CONN@
CONN@
4
5
Free Fall Sensor
2
1
+3VS
1
C1067
C1067
10U_0805_10V4Z~D
10U_0805_10V4Z~D
2
+3VS +3VS_ACL_IO
8
7
6
5
+3VS_ACL_IO
+3VS
ACCEL_INT#<19>
SMBDATA<11,12,13,16>
SMBCLK<11,12,13,16>
+3VS
1 2
R1135 10K_0402_5%~D
R1135 10K_0402_5%~D
R1134
R1134
1 2
0_0603_5%~D
0_0603_5%~D
12
13
14
U50
U50
DE351DLTR
DE351DLTR
1
VDD_IO
6
VDD
8
INT 1
INT 29GND
SDO
SDA / SDI / SDO
SCL / SPC
7
RSVD
CS
RSVD
DE351DLTR_LGA14_3X5
DE351DLTR_LGA14_3X5
GND
GND
GND
2
4
5
10
3
11
C1066
C1066
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
+3VS
Must be placed in the center o f the system.
P/N : SA000039C 00 (S IC DE351D LTR LGA 14P MO TION SENSOR)
Power Button
for debug only
5
6
3
4
SWO1
SWO1
@
@
SMT1-05_4P
SMT1-05_4P
1
2
TOPBTN
SWO2
SWO2
5
6
@
@
SMT1-05_4P
SMT1-05_4P
3
4
1
2
PWR_ON-OFF_BTN#
PWR_ON-OFF_BTN# <32>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2009/09/21 2010/09/21
2009/09/21 2010/09/21
2009/09/21 2010/09/21
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
FAN & Screw Hole
FAN & Screw Hole
FAN & Screw Hole
NAT02 M/B LA-5154P Schematic
NAT02 M/B LA-5154P Schematic
NAT02 M/B LA-5154P Schematic
14 49Thursday, November 26, 2009
14 49Thursday, November 26, 2009
14 49Thursday, November 26, 2009
1.0
1.0
1.0
5
+RTCVCC
1 2
R46
R46
20K_040 2_1%~D
20K_040 2_1%~D
PCH_RTC RST#
RC Delay 18~25mS
close to RAM door
12
CMOS1@CMOS1
@
C15
C15
1U_0603 _10V6K~D
1U_0603 _10V6K~D
D D
+RTCVCC
close to RAM door
1 2
1 2
R36
R36
20K_040 2_1%~D
20K_040 2_1%~D
ME1 @ME1 @
C13
C13
1U_0603 _10V6K~D
1U_0603 _10V6K~D
1 2
12
32.768KH Z_12.5PF_Q13M C14610002
32.768KH Z_12.5PF_Q13M C14610002
PCH_SRT CRST#
RC Delay 18~25mS
3
2
+RTCVCC
INTVRMEN - Integrated SUS 1.1V VRM Enable
High - Enable Internal VRs
HDA for AUDIO
HDA_BITCL K_AUDIO<25>
HDA_SYNC_ AUDIO<25>
HDA_RST _AUDIO#<25>
HDA_SDO UT_AUDIO<25>
C C
HDA_BITCL K_AUDIO
1 2
R1083 33_0402_5% ~DR1083 33_0402_ 5%~D
1 2
R1084 33_0402_5% ~DR1084 33_0402_ 5%~D
1 2
R1085 33_0402_5% ~DR1085 33_0402_ 5%~D
1 2
R1086 33_0402_5% ~DR1086 33_0402_ 5%~D
10P_040 2_50V8J~D
10P_040 2_50V8J~D
1 2
C1110
C1110
@
@
HDA_BITCL K_PCH
HDA_SYNC_ PCH
HDA_RST _PCH#
HDA_SDO UT_PCH
TOUCHKE Y_TINT<31,32 >
GPIO33 pull dow n only for ME d isable
4
C398
C398
18P_040 2_50V8J~D
18P_040 2_50V8J~D
12
X2
X2
OSC
NC
OSC
NC
C402
C402
12
18P_040 2_50V8J~D
18P_040 2_50V8J~D
R64 1M_0402_5 %~DR64 1M_0402_5 %~D
1 2
R51 330K_0402 _5%~DR51 330K_0402 _5%~D
1 2
PCH_SPK R<2 5>
HDA_SDIN0<25>
PCH_RTC X1
4
1
R1024 0_0402_ 5%~DR 1024 0_0402_5%~D
R1232 1K_0402 _5%~D@R1232 1K_0402_5 %~D@
R1100
R1100
10M_040 2_5%~D
10M_040 2_5%~D
PCH_RTC X2
1 2
1 2
12
PCH_RTC RST#
PCH_SRT CRST#
SM_INTRUD ER#
PCH_INTVR MEN
HDA_BITCL K_PCH
HDA_SYNC_ PCH
PCH_SPK R
HDA_RST _PCH#
HDA_SDO UT_PCH
PCH_JTA G_TCK
PCH_JTA G_TMS
PCH_JTA G_TDI
PCH_JTA G_TDO
PCH_JTA G_RST#
U47A
U47A
B13
RTCX1
D13
RTCX2
C14
RTCRST#
D17
SRTCRST#
A16
INTRUDER#
A14
INTVRMEN
A30
HDA_BCLK
D29
HDA_SYNC
P1
SPKR
C30
HDA_RST#
G30
HDA_SDIN0
F30
HDA_SDIN1
E32
HDA_SDIN2
F32
HDA_SDIN3
B29
HDA_SDO
H32
HDA_DOCK_EN# / GPIO33
J30
HDA_DOCK_RST# / GPIO13
M3
JTAG_TCK
K3
JTAG_TMS
K1
JTAG_TDI
J2
JTAG_TDO
J4
TRST#
REV1.0
REV1.0
3
RTCIHDA
RTCIHDA
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
FWH4 / LFRAME#
LDRQ1# / GPIO23
LPC
LPC
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA
SATA
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATAICOMPO
SATAICOMPI
LDRQ0#
SERIRQ
D33
B33
C32
A32
C34
A34
F34
AB9
AK7
AK6
AK11
AK9
AH6
AH5
AH9
AH8
AF11
AF9
AF7
AF6
AH3
AH1
AF3
AF1
AD9
AD8
AD6
AD5
AD3
AD1
AB3
AB1
AF16
AF15
2
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRA ME#
SERIRQ
SATA_ITX_ DRX_N0
SATA_ITX_ DRX_P0
SATA_ITX_ DRX_N1
SATA_ITX_ DRX_P1
From PCH EDS 5. 16, SATA port2 & 3
are not availa ble in all sku.
SATA_ITX_ DRX_N4
SATA_ITX_ DRX_P4
SATA_ITX_ DRX_N5
SATA_ITX_ DRX_P5
SATA_CO MP
LPC_AD0 <27,31>
LPC_AD1 <27,31>
LPC_AD2 <27,31>
LPC_AD3 <27,31>
LPC_FRA ME# <27 ,31>
SERIRQ <31>
C963 0 .01U_0402_16V 7K~DC963 0 .01U_0402_16V 7K~D
C964 0 .01U_0402_16V 7K~DC964 0 .01U_0402_16V 7K~D
R139 37.4_0 402_1%~OKR139 37.4_0 402_1%~OK
1 2
1
SATA_IRX_ DTX_N0 < 29>
C9610.01 U_0402_16V7K ~D C9610.01U_ 0402_16V7K~D
1 2
C9620.01 U_0402_16V7K ~D C9620.01U_ 0402_16V7K~D
1 2
12
12
C9650.01 U_0402_16V7K ~D C9650.01U_ 0402_16V7K~D
1 2
C9660.01 U_0402_16V7K ~D C9660.01U_ 0402_16V7K~D
1 2
C9670.01 U_0402_16V7K ~D C9670.01U_ 0402_16V7K~D
1 2
C9680.01 U_0402_16V7K ~D C9680.01U_ 0402_16V7K~D
1 2
+1.05VS
SATA_IRX_ DTX_P0 <29>
SATA_ITX_ C_DRX_N0 <29>
SATA_ITX_ C_DRX_P0 <29>
SATA_IRX_ DTX_N1 < 29>
SATA_IRX_ DTX_P1 <29>
SATA_ITX_ C_DRX_N1 <29>
SATA_ITX_ C_DRX_P1 <29>
SATA_IRX_ DTX_N4 < 29>
SATA_IRX_ DTX_P4 <29>
SATA_ITX_ C_DRX_N4 <29>
SATA_ITX_ C_DRX_P4 <29>
SATA_IRX_ DTX_N5 < 30>
SATA_IRX_ DTX_P5 <30>
SATA_ITX_ C_DRX_N5 <30>
SATA_ITX_ C_DRX_P5 <30>
SATA for HDD1
SATA for HDD2
SATA for ODD
SATA for eSATA
PCH_SPI_C LK_1
PCH_SPI_C LK_2
+3VS
B B
A A
R1120
R1120
1K_0402 _5%~D
1K_0402 _5%~D
1 2
1 2
R115
R115
10K_040 2_5%~D
10K_040 2_5%~D
PCH_JTA G_TMS
PCH_JTA G_TDO
PCH_JTA G_TDI
PCH_JTA G_RST#
PCH_SPI_M OSI
enable iTPM: SPI_MOSI High
PCH_SPK R
@
@
SERIRQ
R1130 51_0402_1 %~D@R 1130 51 _0402_1%~D@
1 2
R1101 200_0402_ 5%~DR 1101 20 0_0402_5%~D
1 2
R1102 100_0402_ 1%~DR 1102 10 0_0402_1%~D
1 2
R1131 51_0402_1 %~D@R 1131 51 _0402_1%~D@
1 2
R1104 200_0402_ 5%~D R1104 200_040 2_5%~D
1 2
R1105 100_0402_ 1%~DR 1105 10 0_0402_1%~D
1 2
R1132 51_0402_1 %~D@R 1132 51 _0402_1%~D@
1 2
R1106 200_0402_ 5%~DR 1106 20 0_0402_5%~D
1 2
R1107 100_0402_ 1%~DR 1107 10 0_0402_1%~D
1 2
R1133 51_0402_1 %~D@R 1133 51 _0402_1%~D@
1 2
R1108 20K_0402_ 1%~DR1108 20K_0402 _1%~D
1 2
R1109 10K_0402_ 5%~DR1109 10K_0402 _5%~D
1 2
R173 1K_04 02_5%~D@R1 73 1K_0402_5%~D@
1 2
5
PCH_SPI_C S0#
PCH_SPI_C S1# PCH_SPI_CS 1#_R
PCH_SPI_M OSI_1
PCH_SPI_M OSI_2
PCH_SPI_M ISO_1 P CH_SPI_MISO
PCH_SPI_M ISO_2
+3V
+1.05VS
2008 Intel MOW3 6/MOW50
TDO:
Reserved on ES1 Sample
Mount R1104, R1 105 on ES2 Samp le
MP mount R1130, R1131,
R1132, R1133 an d remove
others
+3VS
PCH_JTA G_TCK
R584 0_040 2_5%~DR584 0_040 2_5%~D
1 2
RU86 0_0402_5%~D@RU86 0_0402_5% ~D@
1 2
R571 15_04 02_5%~DR571 15_04 02_5%~D
1 2
RU87 15_0402_5%~D@RU87 15_0402_5% ~D@
1 2
R575 15_04 02_5%~DR575 15_04 02_5%~D
1 2
RU88 15_0402_5%~D@RU88 15_0402_5% ~D@
1 2
R565 33_04 02_5%~DR565 33_04 02_5%~D
1 2
RU89 33_0402_5%~D@RU89 33_0402_5% ~D@
1 2
R1111 4.7K_040 2_5%~DR1111 4.7K_040 2_5%~D
CRB 1.0 Change to 4.7K
1 2
4
PCH_SPI_C LKP CH_SPI_CLK
PCH_SPI_C LKP CH_SPI_CLK
PCH_SPI_C S0#_R
PCH_SPI_M OSI
PCH_SPI_M OSI
PCH_SPI_M ISO
BA2
SPI_CLK
AV3
SPI_CS0#
AY3
SPI_CS1#
AY1
SPI_MOSI
AV1
SPI_MISO
IBEXPEAK-M_ FCBGA1071~D
IBEXPEAK-M_ FCBGA1071~D
Security Class ification
Security Class ification
Security Class ification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
SPI JTAG
SPI JTAG
+3VS
+3VS
2009/09/ 21 2010/09/ 21
2009/09/ 21 2010/09/ 21
2009/09/ 21 2010/09/ 21
3
SATALED#
SATA0GP / GPIO21
SATA1GP / GPIO19
RU91
RU91
1 2
3.3K_040 2_5%~D@
3.3K_040 2_5%~D@
R1110
R1110
1 2
3.3K_040 2_5%~D
3.3K_040 2_5%~D
PCH_SPI_C S1#
PCH_SPI_M ISO_2
SPI_WP 2#
PCH_SPI_C S0#
PCH_SPI_M ISO_1
SPI_WP 1#
Compal Secret Data
Compal Secret Data
Compal Secret Data
PCH_SAT ALED#
T3
Y9
V1
Deciphered Date
Deciphered Date
Deciphered Date
R129 10K_0 402_5%~DR1 29 10K_0402_5%~D
1 2
@
@
PAD
PAD
T110
T110
@
@
PAD
PAD
T111
T111
U68
U68
1
CS#
2
3
4
1
2
3
4
VCC
SO
HOLD#
WP#
SCLK
GND
MX25L16 05AM2C-12G_SO 8@
MX25L16 05AM2C-12G_SO 8@
U29
U29
/CS
DO
/WP
GND
MX25L32 05DM2I-12G_SO8~ D
MX25L32 05DM2I-12G_SO8~ D
SI
VCC
/HOLD
CLK
DIO
8
7
6
5
8
7
6
5
2
10K_040 2_5%~D
10K_040 2_5%~D
+3VS
SPI_HOLD2 #
PCH_SPI_C LK_2
PCH_SPI_M OSI_2
+3VS
SPI_HOLD1 #
PCH_SPI_C LK_1
PCH_SPI_M OSI_1
R111
R111
+3VS
+3VS
R77 10K_0402_ 5%~D@R77 10K_0402 _5%~D@
1 2
R116 10K_0 402_5%~D@R11 6 10K_0402_5%~D@
1 2
12
12
R82
R82
10K_040 2_5%~D
10K_040 2_5%~D
RU903.3K_040 2_5%~D
RU903.3K_040 2_5%~D
12
+3VS
@
@
SPI Flash
(32Mbit/4Mbyte)
R11223.3 K_0402_5%~D R11223 .3K_0402_5%~D
12
+3VS
Change to SA000021A0L
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
Custom
Custom
Custom
NAT02 M/B LA-5154P Schematic
NAT02 M/B LA-5154P Schematic
NAT02 M/B LA-5154P Schematic
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PCH (1/9) SATA,HDA,SPI, LPC
PCH (1/9) SATA,HDA,SPI, LPC
PCH (1/9) SATA,HDA,SPI, LPC
1
1.0
1.0
1.0
15 49Thursday, November 26, 2 009
15 49Thursday, November 26, 2 009
15 49Thursday, November 26, 2 009
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