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1530
Schematics
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Schematics
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Schematics
57 pgs1.34 Mb0

Dell 1530 Schematics

A
B
C
D
E
BATTERY CHARGER
Hawke Intel Discrete Block Diagram
Project code : 91.4W101.001
RGB CRT
LVDS
HDMI
SVIDEO
CLK GEN
ICS9LPRS365
VRAM 16Mbx32x2
GDDRIII 700MHz
1394
Ricoh R5C833
CardReader
HEADPHONE AMP
MAX4411
Azalia CODEC
Sigmatel STAC 9228
4
VRAM
51 52
16Mbx32x2
GDDRIII 700MHz
nVidia NB8P (256MB)
OR nVidia NB8M (128MB)
47, 48, 49, 50
PCI
32
31
PCIe x 16
AZALIA
Intel Mobile CPU
Merom 4M FSB:667 or 800 MHz
5, 6, 7
Host BUS 667/800MHz
Crestline-PM
AGTL+ CPU I/F DDR Memory I/F EXTERNAL GRAHPICS
8, 9, 10, 11, 12, 13
DMI I/F 100MHz
INTEL
ICH8-M
10 USB 2.0/1.1 ports 6 PCI Express ports
High Definition Audio
ATA 66/100
SATA ACPI 1.1 LPC I/F
PCI/PCI BRIDGE
SATA
19, 20, 21, 22
PATA
PCB P/N : 48.4W101.0SA Revision : 07212-SA
DDRII 667 Channel A
DDR II 667 Channel B
PCIE x 1
PCIE
USB 2.0
LPC Bus
KBC
Winbond WPC8763L
DDRII 533/667
DDRII 533/667
33
Slot 0
14
Slot 1
15
PCIE x 1 & USB 2.0 x 1
10/100 NIC
Marvell 88E8040
PCIE x 1
PCIE x 2 & USB 2.0 x 2
SPI
26
USB 2.0 x 1
USB 2.0 x 1
USB 2.0 x 1
USB 2.0 x 3
Power SW
TI TPS2231
New Card
RJ45 CONN
Mini-Card x 1
802.11a/b/g
Mini-Card x 2
27
27
27
28
29
WWAN&BT&Robson
Camera
Biometic reader
Bluetooth 2.1
Lift Side: USB x 2
Right Side:USB x 1
18
30
30
37
34
1 1
CRT
17
LCD
18
HDMI
16
2 2
S-Video
1394
25
SD/SDIO/MMC MS/MS Pro/XD
3 3
HP2
25 24, 25
MIC IN
Digital Mic Array
HP1
MAX8731A
INPUTS
AD+ BAT+
OUTPUTS
DCBATOUT
SYSTEM DC/DC
TPS51120
INPUTS
DCBATOUT
OUTPUTS
5V_AUX_S5 3D3V_AUX_S5 5V_S5 3D3V_S5
SYSTEM DC/DC
TPS5117
INPUTS
DCBATOUT
OUTPUTS
1D05V_S0 1D8V_S3
SYSTEM DC/DC
TPS51100
INPUTS
1D8V_S3
OUTPUTS
0D9V_S3
SYSTEM DC/DC
RT9018
INPUTS
1D8V_S3 1D8V_S3 1D25V_S0
OUTPUTS
1D5V_S0
VGA DC/DC
TPS5117
INPUTS
OUTPUTS
VCC_GFX_CORE_S0DCBATOUT
CPU DC/DC
ISL6262A
INPUTS
DCBATOUT
OUTPUTS
VCC_CORE
PCB LAYER
L1:TOP L2:GND L3:Signal L4:Signal L5:VCC L6:Singal
38
39
42, 43
44
44
53
40
L7:GND
4 4
2CH SPEAKER
A
OP AMP
MAX9789A
32
B
HDD
ODD
23 23 36 36 3530 30 30
Capacity Button
Touch Pad
C
Int. KB
S/W CIR
Thermal & Fan
G792
Flash ROM
1MB
D
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
Date: Sheet of
System Block Diagram
System Block Diagram
System Block Diagram
L8:BOT
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Hawke-Intel SA
Hawke-Intel SA
Hawke-Intel SA
155Tuesday, May 08, 2007
155Tuesday, May 08, 2007
155Tuesday, May 08, 2007
of
E
of
A
B
C
D
E
Adapter
Input Signal
AD_OFF
1 1
AD_JK
5V_AUX_S5
(I)
Input Power
VCC(I)
VCC(I)
Output Signal
(O)
Output Power
VCC(O)
AD_IN
AD+
PM_SLP_S4#
DCBATOUT
Input Signal
EN_PSV(I / 5V)
Input Power Output Power5V_S5
VCC
VIN
TPS51117 1D8V
Output Signal
Input Signal
EN_PSV(I / 5V)
Input Power
VCC
VIN
(O)
CPUCORE_ON
PM_SLP_S3#
5V_S5 Output Power
1D8V_S3(19A)
(O) (O)
DCBATOUT
TPS51117 1D05V
Output Signal
(O)
CPUCORE_ON
1D05V_S0(5A)
TI TPS51100 0.9V/DDR_VREF_S3
Charger_ISL6255
CHARGE_OFF
BT_TH
BAT+SENSE
BT_SCL_5
BT_SDA_5
2 2
FLASH_GPIO1
FLASH_GPIO2
AC_IN
AD+
CLS (I / 3.3V)
THM (I / 3.3V)
BATT (I / 3.3V)
SCL (IO / 5V)
SDA (IO / 5V)
RESET#/PB5 (I/5V)
PB0/MOSI/AIN0
PB0/MOSI/AIN0
Input Power
DCIN (I)
Output SignalInput Signal
LDO (O / 5.4V)
XTAL2/PB4 (O/5V)
XTAL1/PB3 (O/5V)
Output Power
VCC (O)
VCC (O)
AD_IN
CHARGE_LED#
BL2#
DCBATOUT
BT+
PM_SLP_S4#
PM_SLP_S4#
5V_S5
1D8V_S3 DDR_VERF_S0
5V_S5
1D8V_S3
TI TPS51120 3D3V/5V
Input Signal
3V/5V_EN
3 3
3V/5V_EN
51120_EN2
51120_EN1
FOR
3.3V FOR
5.0V
Input Power
DCBATOUT
5V_AUX_S5
4 4
VIN
REG5V_IN(I / 5V)
A
Output Signal
PGOUT(OD / 5V)
Output Power
5V(O)
3D3V(O)
CPUCORE_ON
5V_AUX_S5
3D3V_AUX_S5
5V_S5 (6A)
3D3V_S5 (5A)
PM_SLP_S3#
5V_S5
1D8V_S3
PM_SLP_S3# CPUCORE_ON
DCBATOUT
B
Input Signal
S5
S3
Input Power Output Power
VCC(I)
VN(I)
VCC(O)
VCC(O)
RT9018A 1D5V
Input Signal
EN(I / 5V)
VCC
VIN
Output Signal
Output PowerInput Power
RT9018A 1D25V
Output SignalInput Signal
EN(I / 5V)
Input Power Output Power
VCC
VIN
TPS51117 VGA_CORE
Input Signal
EN_PSV(I / 5V)
Input Power
VCC
VIN
Output Signal
Output Power5V_S5
C
CPUCORE_ONPM_SLP_S3#
(O)
1D5V_S0(2.2A)
(O)
CPUCORE_ON
(O)
1D25V_S0(2.7A)
(O)
(O)
VCC_GFX_CORE_S0 (18.4A)
(O)
DDR_VREF_S3
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
CPUCORE_ON
VCC_SENSE
VSS_SENSE
DCBATOUT
5V_S0
3D3V_S0
D
ISL6262A CPU_CORE
VID Setting
VID0(I / 3.3V)
VID1(I / 3.3V)
VID2(I / 3.3V)
VID3(I / 3.3V)
VID4(I / 3.3V)
VID5(I / 3.3V)
VID6(I / 3.3V)
Input Signal
EN (I / 3.3V)
Voltage Sense
VSEN(I / Vcore)
RGND(I / Vcore)
Input Power
VCC(I)
VCC(I)
VCC(I)
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
Date: Sheet of
Power Block Diagram
Power Block Diagram
Power Block Diagram
Output Signal
VROK()
Output Power
VCC_CORE_PWR(O)
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Hawke-Intel SA
Hawke-Intel SA
Hawke-Intel SA
255Tuesday, May 08, 2007
255Tuesday, May 08, 2007
255Tuesday, May 08, 2007
E
VGATE_PWRGD
VCC_CORE_S0 (Imax=47A)
of
of
A
B
C
D
E
INTEL ICH8-M STRAP PIN
Signal Usage/When Sampled
HDA_SDOUT XOR Chain Entrance/
1 1
HDA_SYNC
GNT2#
GPIO20
GNT3#
GNT0# SPI_CS1#
INTVRMEN
2 2
LAN100_SLP
SATALED#
SPKR
TP3
GPIO33/ HDA_DOCK_EN#
3 3
PCIE Port Config 1 bit1, Rising Edge of PWROK
PCIE Port Config 1 bit0, Rising Edge of PWROK.
PCIE Port Config 2 bit0, Rising Edge of PWROK.
Reserved
Top-Block Swap Override. Rising Edge of PWROK.
Boot BIOS Destination Selection. Rising Edge of PWROK.
Integrated VccSus1_05 VccSus1_5 and VccCL1_5 VRM Enable/Disable.Always sampled.
Integrated VccLAN1_05 VccCL1_05 VRM enable /Disable. Always sampled.
PCIE LAN REVERSAL.Rising Edge of PWROK.
No Reboot. Rising Edge of PWROK.
XOR Chain Entrance. Rising Edge of PWROK.
Flash Descriptor Security Override Strap Rising Edge of PWROK.
Allows entrance to XOR Chain testing when TP3 pulled low at rising edge of PWROK.When TP3 not pulled low at rising edge of PWROK,sets bit1 of RPC.PC(Config Registers:offset 224h) Sets bit0 of RPC.PC(Config Registers:Offset 224h)
Sets bit2 of RPC.PC(Config Registers:Offset 224h)
Weak Internal PULL-DOWN.NOTE:This signal should not be pull HIGH.
Sampled low:Top-Block Swap mode(inverts A16 for all cycles targeting FWH BIOS space). Note: Software will not be able to clear the Top-Swap bit until the system is rebooted without GNT3# being pulled down.
Controllable via Boot BIOS Destination bit (Config Registers:Offset 3410h:bit 11:10). GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC.
Enables integrated VccSus1_05,VccSus1_5 and VccCL1_5 VRM when sampled high
Enables integrated VccLAN1_05,VccCL1_05 VRM when sampled high
This signal has weak internal pull-up. set bit27 of MPC.LR(Device28:Function0:Offset D8)
If sampled high, the system is strapped to the "No Reboot" mode(ICH8M will disable the TCO Timer system reboot feature). The status is readable via the NO REBOOT bit.(Offset:3410h:bit5)
This signal should not be pull low unless using XOR Chain testing.
Internal Pull-Up.If sampled low,the Flash Descriptor Security will be overidden.if high,the Security measures defined in the Flash Descriptor will be in effect. This should only be used in manufacturing environments
Comment
INTEL CRESTLINE STRAP PIN
CFG Strap HIGH 1LOW 0
CFG 5 CFG 8
Low Power PCI Express Normal Low Power mode
CFG 9
PCI Express Graphics Lane Reversal
CFG 16
FSB Dynamic ODT Disabled Enabled
CFG 19
DMI Lane Reserved Normal Operation Reserved Lane
CFG 20
Concurrent SDVO/PCIE
SDVO_CTRL_DATA
4 4
SDVO Present
CFG 12 CFG 13
LL(00) LH(01) HL(10) HH(11)
A
DMI X 2 DMI X 4
★
Lane Reversal Normal Mode(Lanes
Only PCIE or SDVO is operation
NO SDVO Card Present
★
★
★
★
number in order)
★
PCIE and SDVO are operation simultaneous
SDVO Card Present
XOR/ALL-Z
Reserved XOR Mode Enabled All Z Mode Enabled Normal Operation
★
B
XOR Chain Entrance Strap
ICH_RSVD
A16 swap override strap
PCI_GNT#3
BOOT BIOS Strap
PCI_GNT#0 BOOT BIOS Location
integrated VccSus1_05,VccSus1_5,VccCL1_5
SM_INTVRMEN
integrated VccLan1_05VccCL1_05
LAN100_SLP
AZ_DOUT_ICH
tp3
0 0 10
10 1
0 1
11
low = A16 swap override enable high = default
SPI_CS#1
1
Description
Normal Operation(default) Set PCIE port cofig bit1
SPI10 PCI LPC(Default)
High=Enable Low=Disable
High=Enable Low=Disable
RSVD Enter XOR Chain
DEFAULE HIGH
No Reboot Strap
LOW = DefauleSPKR
High=No Reboot
INTEL ICH8-M INTEGRATED PULL-UPS and PULL-DOWNS
8.2K PULL HIGH
SIGNAL Resistor Type/Value
HDA_BIT_CLK HDA_RST# HDA_SDIN[3:0] HDA_SDOUT HDA_SYNC GNT[3:0] GPIO[20] LDA[3:0]#/FHW[3:0]# LAN_RXD[2:0] LDRQ[0] LDRQ[1]/GPIO23 PME# PWRBTN# SATALED# SPI_CS1# SPI_CLK SPI_MOSI SPI_MISO TACH_[3:0] SPKR TP[3] USB[9:0][P,N] CL_RST#
C
PULL-DOWN 20K NONE PULL-DOWN 20K PULL-DOWN 20K PULL-DOWN 20K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-UP 20K PULL-DOWN 20K PULL-UP 20K PULL-DOWN 15K TBD
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
D
Date: Sheet
+RTCVCC20,22
1D05V_S05,6,7,8,10,11,12,20,22,33,42,46
1D25V_S08,11,22,44,47,48,49
1D2V_LAN_S526
1D5V_NEW_S027
1D5V_S06,11,20,21,22,27,28,29,44
1D8V_S38,11,12,14,15,43,44,45,46
2D5V_LAN_S526,27
3D3V_AUX_S520,30,33,35,38,39,46 3D3V_LAN_S526,27
3D3V_S04,8,11,14,15,16,18,19,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,40,42,45,46,47,49,50,53
3D3V_S519,21,22,26,27,30,37,39,45,46
5V_AUX_S518,38,39,46
5V_S016,17,18,22,23,30,32,34,35,36,40,44,45,46
5V_S522,29,30,34,36,37,39,42,43,44,45,53
AD+37,38,46
DCBATOUT18,38,39,40,41,42,43,45,46,53 DDR_VREF_S014,15,44,46 DDR_VREF_S38,14,15,44
+LCDVDD18 VCC_CORE_S06,7,41
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Table of Content
Table of Content
Table of Content
Hawke-Intel SA
Hawke-Intel SA
Hawke-Intel SA
E
355Tuesday, May 08, 2007
355Tuesday, May 08, 2007
355Tuesday, May 08, 2007
+RTCVCC 1D05V_S0 1D25V_S0 1D2V_LAN_S5 1D5V_NEW_S0 1D5V_S0 1D8V_S3 2D5V_LAN_S5
3D3V_AUX_S5 3D3V_LAN_S5 3D3V_S0 3D3V_S5 5V_AUX_S5
5V_S0 5V_S5 AD+ DCBATOUT DDR_VREF_S0 DDR_VREF_S3
+LCDVDD VCC_CORE_S0
of
of
of
3D3V_S0 3D3V_S0_CK505
L15
L15
1 2
0R0603-PAD
0R0603-PAD
12
C439
C439
SC1U10V3KX-3GP
SC1U10V3KX-3GP
A
12
C436
C436
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
12
12
C824
C824
C429
C429
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
12
C437
C437
C383
C383
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1 1
B
12
C396
C396
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
X4
X4
1 2
X-14D31818M-36GP
X-14D31818M-36GP
12
C399
C399 SC27P50V2JN-2-GP
SC27P50V2JN-2-GP
CLK_XTAL_OUTCLK_XTAL_IN
C
12
C392
C392 SC27P50V2JN-2-GP
SC27P50V2JN-2-GP
D
3D3V_S0_CK505_IO3D3V_S0_CK505
U22
4
9
46
62
16
23
33
43
52
56
19
27
U22
E
3D3V_S0
L16
L16
1 2
0R0603-PAD
12
0R0603-PAD
C445
C445
SC1U10V3KX-3GP
SC1U10V3KX-3GP
DY
DY
12
C435
C435
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
12
12
C426
C426
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C811
C811
12
C821
C821
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2 2
CLKSATAREQ#21
CLKREQ#_B8
PCLK_PCM24 PCLK_KBC33 CLK_PCI_ICH19
CLK_14M_ICH21
3D3V_S0_CK505
12
R436
R436 10KR2J-3-GP
10KR2J-3-GP
PCI2_TME
DY
DY
12
R435
R435 10KR2J-3-GP
10KR2J-3-GP
3 3
3D3V_S0_CK505_IO
C837 SC4D7P50V2CN-1GPC837 SC4D7P50V2CN-1GP
12
12
C384
C384
C438
C438
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
12
C413
C413
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
CLK_48M_ICH21
12
C419
C419
C416
C416
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
1 2
H_STP_PCI#21 H_STP_CPU#21
ICH_SMBCLK14,15,21,28,29
ICH_SMBDATA14,15,21,28,29
CK_PWRGD21
12
C822
C822
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
Main source : 71.09365.003 ICS9LPRS365CKLFT 2nd source : 71.00875.A03 RTM875M-606-LF
PCI2_TME Output
0
1
Overclocking of CPU and SRC allowed
Overclocking of CPU and SRC not allowed
CLK_XTAL_IN CLK_XTAL_OUT
R448
R448
1 2
33R2J-2-GP
33R2J-2-GP
R184 33R2J-2-GPR184 33R2J-2-GP
1 2
R186 33R2J-2-GPR186 33R2J-2-GP
1 2
R187 33R2J-2-GPR187 33R2J-2-GP
1 2
R432
R432
1 2
33R2J-2-GP
33R2J-2-GP
FSA
PCI2_TME PCLK_PCM_R 27_SEL ITP_EN
FSB FSC
3
X1
2
X2
17
USB_48MHZ/FSLA
45
PCI_STOP#
44
CPU_STOP#
7
SCLK
6
SDATA
63
CK_PWRGD/PD#
8
PCI0/CR#_A
10
PCI1/CR#_B
11
PCI2/TME
12
PCI3
13
PCI4/27_SELECT
14
PCI_F5/ITP_EN
64
FSLB/TEST_MODE
5
REF0/FSLC/TEST_SEL
55
NC#55
FS_C FS_B FS_A CPU
1 0 1 100M 0 0 1 133M 0 1 0 200M 0 1 1 166M
VDDREF
GND48
15
18
VDD48
GNDPCI
1
VDDPCI
VDDSRC
VDDCPU
VDDPLL3
VDD96_IO
VDDSRC_IO
VDDSRC_IO
VDDSRC_IO
VDDCPU_IO
VDDPLL3_IO
27MHZ_NONSS/SRCT1/SE1
27MHZ_SS/SRCC1/SE2
GNDREF
GND
GND
GNDSRC
GNDSRC
GNDSRC
GNDCPU
GND
22
26
30
36
49
59
65
ICS9LPRS365CKLFT-GP
ICS9LPRS365CKLFT-GP
CPUT0 CPUC0
CPUT1_F CPUC1_F
CPUT2_ITP/SRCT8
CPUC2_ITP/SRCC8
SRCT7/CR#_F
SRCC7/CR#_E
SRCT6 SRCC6
SRCT10 SRCC10
SRCT11/CR#_H
SRCC11/CR#_G
SRCT9 SRCC9
SRCT4 SRCC4
SRCT3/CR#_C
SRCC3/CR#_D
SRCT2/SATAT
SRCC2/SATAC
SRCT0/DOTT_96
SRCC0/DOTC_96
CLK_CPU_BCLK1
61
CLK_CPU_BCLK1#
60
CLK_MCH_BCLK1
58
CLK_MCH_BCLK1#
57
CLK_PCIE_MINI3_1
54
CLK_PCIE_MINI3_1#
53
CLK_PCIE_LAN1
51
CLK_PCIE_LAN1#
50
CLK_PCIE_MINI1_1
48
CLK_PCIE_MINI1_1#
47
CLK_PCIE_NEW1
41
CLK_PCIE_NEW1#
42 40
39
CLK_PCIE_MINI2_1
37
CLK_PCIE_MINI2_1#
38
CLK_MCH_3GPLL1
34
CLK_MCH_3GPLL1#
35
CLK_PCIE_ICH1
31
CLK_PCIE_ICH1#
32
CLK_PCIE_SATA1CLK_PCIE_SATA1
28
CLK_PCIE_SATA1#CLK_PCIE_SATA1#
29
CLK_VGA_27M_NSS1
24
CLK_VGA_27M_SS1
25
CLK_PCIE_VGA1
20
CLK_PCIE_VGA1#
21
For Discrete: Rename for GPU clock.
For Discrete
3D3V_S0_CK505
12
R440
R440 10KR2J-3-GP
10KR2J-3-GP
27_SEL
1 2 3
1 2 3
1 2 3
1 2 3
1 2 3
2 3 1
2 3 1
2 3 1
2 3 1
2 3 1
2 3 1
2 3 1
RN25
RN25
4
SRN0J-6-GP
SRN0J-6-GP
RN26
RN26
4
SRN0J-6-GP
SRN0J-6-GP
RN27
RN27
4
SRN0J-6-GP
SRN0J-6-GP
RN28
RN28
4
SRN0J-6-GP
SRN0J-6-GP
RN29
RN29
4
SRN0J-6-GP
SRN0J-6-GP
RN30
RN30
SRN0J-6-GP
SRN0J-6-GP
4
1 2
R434 10KR2J-3-GPR434 10KR2J-3-GP R183
R183
1 2
DY
DY
RN31
RN31
SRN0J-6-GP
SRN0J-6-GP
4
RN32
RN32
SRN0J-6-GP
SRN0J-6-GP
4
RN34
RN34
SRN0J-6-GP
SRN0J-6-GP
4
RN33
RN33
SRN0J-6-GP
SRN0J-6-GP
4
RN35
RN35
SRN0J-6-GP
SRN0J-6-GP
4
RN36
RN36
SRN0J-6-GP
SRN0J-6-GP
4
CLK_VGA_27M_NSS CLK_VGA_27M_SS
CLK_CPU_BCLK 5 CLK_CPU_BCLK# 5
CLK_MCH_BCLK 8 CLK_MCH_BCLK# 8
CLK_PCIE_MINI3 29 CLK_PCIE_MINI3# 29
CLK_PCIE_LAN 26 CLK_PCIE_LAN# 26
CLK_PCIE_MINI1 28 CLK_PCIE_MINI1# 28
CLK_PCIE_NEW 27 CLK_PCIE_NEW# 27
NEWCARD_CLKREQ# 27
10KR2J-3-GP
10KR2J-3-GP
CLK_PCIE_MINI2 29 CLK_PCIE_MINI2# 29
CLK_MCH_3GPLL 8 CLK_MCH_3GPLL# 8
CLK_PCIE_ICH 21 CLK_PCIE_ICH# 21
CLK_PCIE_SATA 20 CLK_PCIE_SATA# 20
CLK_VGA_27M_NSS 49 CLK_VGA_27M_SS 49
CLK_PCIE_VGA 47 CLK_PCIE_VGA# 47
12
12
C840
C840
C839
C839
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
3D3V_S0
FSC FSB FSA
27_SEL strap 0:For 965GM, 1:For 965PM
27_SEL PIN 20 PIN 21 PIN 24 PIN 25
0 DOT96T DOT96C SRCT1/LCDT_100 SRCT1/LCDT_100 1 SRCT0 SRCC0 27M_NSS 27M_SS
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Clock generator ICS9LPRS365
Clock generator ICS9LPRS365
Clock generator ICS9LPRS365
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
Date: Sheet
Hawke-Intel SA
Hawke-Intel SA
Hawke-Intel SA
455Tuesday, May 08, 2007
455Tuesday, May 08, 2007
455Tuesday, May 08, 2007
of
of
of
965GM 965PM
12
ITP_EN
R444
R444 10KR2J-3-GP
10KR2J-3-GP
ITP_EN Output
0 SRC8 1 CPU_ITP
CPU_BSEL26,8 CPU_BSEL16,8 CPU_BSEL06,8
1 2
R431 10KR2J-3-GPR431 10KR2J-3-GP
1 2
R426 0R2J-2-GPR426 0R2J-2-GP
1 2
R449 2K2R2J-2-GPR449 2K2R2J-2-GP
4 4
Design Note:
1. All of Input pin didn't have internal pull up resistor.
2. Clock Request (CR) function are enable by registers.
3. ICS9LPRS365 integrated serial resistor of differential clock, so put 0 ohm serial resistor in the schematic.
A
B
C
D
E
H_A#[3..35]8
H_A#3
1 1
H_ADSTB#08 H_REQ#08
H_REQ#18 H_REQ#28 H_REQ#38 H_REQ#48
2 2
H_ADSTB#18
H_A20M#20 H_FERR#20 H_IGNNE#20
H_STPCLK#20 H_INTR20 H_NMI20 H_SMI#20
TP14TPAD28 TP14TPAD28 TP17TPAD28 TP17TPAD28 TP8TPAD28 TP8TPAD28 TP12TPAD28 TP12TPAD28 TP6TPAD28 TP6TPAD28 TP7TPAD28 TP7TPAD28
3 3
TP3TPAD28 TP3TPAD28 TP20TPAD28 TP20TPAD28 TP10TPAD28 TP10TPAD28 TP18TPAD28 TP18TPAD28
TP2TPAD28 TP2TPAD28
H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16
H_ADSTB#0
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
H_ADSTB#1 H_A20M#
H_FERR# H_IGNNE#
H_SMI#
CPU_RSVD01 CPU_RSVD02 CPU_RSVD03 CPU_RSVD04 CPU_RSVD05 CPU_RSVD06 CPU_RSVD07 CPU_RSVD08 CPU_RSVD09 CPU_RSVD10
CPU_RSVD11
U47A
U47A
J4
A3#
L5
A4#
L4
A5#
K5
A6#
M3
A7#
N2
A8#
J1
A9#
N3
A10#
P5
A11#
P2
A12#
L2
A13#
P4
A14#
P1
A15#
R1
A16#
M1
ADSTB0#
K3
REQ0#
H2
REQ1#
K2
REQ2#
J3
REQ3#
L1
REQ4#
Y2
A17#
U5
A18#
R3
A19#
W6
A20#
U4
A21#
Y5
A22#
U1
A23#
R4
A24#
T5
A25#
T3
A26#
W2
A27#
W5
A28#
Y4
A29#
U2
A30#
V4
A31#
W3
A32#
AA4
A33#
AB2
A34#
AA3
A35#
V1
ADSTB1#
A6
A20M#
A5
FERR#
C4
IGNNE#
D5
STPCLK#
C6
LINT0
B4
LINT1
A3
SMI#
M4
RSVD#M4
N5
RSVD#N5
T2
RSVD#T2
V3
RSVD#V3
B2
RSVD#B2
C3
RSVD#C3
D2
RSVD#D2
D22
RSVD#D22
D3
RSVD#D3
F6
RSVD#F6
B1
KEY_NC
BGA479-SKT6-GPU3
BGA479-SKT6-GPU3
1 OF 4
1 OF 4
ADDR GROUP 0
ADDR GROUP 0
ADDR GROUP 1
ADDR GROUP 1
XDP/ITP SIGNALS CONTROL
XDP/ITP SIGNALS CONTROL THERMAL
THERMAL
PROCHOT#
ICH
ICH
THERMTRIP#
HCLK
HCLK
RESERVED
RESERVED
ADS# BNR#
BPRI#
DEFER#
DRDY# DBSY#
BR0#
IERR#
INIT#
LOCK#
RESET#
RS0# RS1# RS2#
TRDY#
HIT#
HITM#
BPM0# BPM1# BPM2# BPM3# PRDY# PREQ#
TCK
TDO TMS
TRST#
DBR#
THRMDA THRMDC
BCLK0 BCLK1
H_ADS#
H1
H_BNR#
E2
H_BPRI#
G5
H_DEFER#
H5
H_DRDY#
F21
H_DBSY#
E1
H_BR0#
F1
H_IERR#
D20
H_INIT#
B3
H_LOCK#
H4
H_RESET#
C1
H_RS#0
F3
H_RS#1
F4
H_RS#2
G3
H_TRDY#
G2
H_HIT#
G6
H_HITM#
E4
XDP_BPM#0
AD4
XDP_BPM#1
AD3
XDP_BPM#2
AD1
XDP_BPM#3
AC4
XDP_BPM#4
AC2
XDP_BPM#5
AC1
XDP_TCK
AC5
XDP_TDI
AA6
TDI
AB3 AB5 AB6 C20
D21 A24 B25
C7
A22 A21
XDP_TDO XDP_TMS XDP_TRST# XDP_DBRESET#
CPU_PROCHOT H_THERMDA H_THERMDC
H_THERMTRIP#
CLK_CPU_BCLK CLK_CPU_BCLK#
H_ADS# 8 H_BNR# 8
H_BPRI# 8 H_DEFER# 8
H_DRDY# 8 H_DBSY# 8
H_BR0# 8
H_INIT# 20
H_LOCK# 8
H_RESET# 8
H_RS#0 8 H_RS#1 8 H_RS#2 8
H_TRDY# 8
H_HIT# 8 H_HITM# 8
TP16TP16 TP11TP11 TP4TP4 TP15TP15 TP9TP9 TP1TP1
R39 27D4R2F-L1-GPR39 27D4R2F-L1-GP
1 2
R36 150R2J-L1-GP-UR36 150R2J-L1-GP-U
1 2
TP13TP13
R37 39D2R2F-L-GPR37 39D2R2F-L-GP
1 2
R38 680R2J-3-GPR38 680R2J-3-GP
1 2
TP19TP19
H_THERMTRIP# 8,20,33,45
CLK_CPU_BCLK 4 CLK_CPU_BCLK# 4
layout note:Zo =55 ohm , 0.5" MAX for GTLREF
1D05V_S0
12
R272
R272 56R2J-4-GP
56R2J-4-GP
1D05V_S0
R74
R74 56R2J-4-GP
56R2J-4-GP
1 2
H_THERMDA 35 H_THERMDC 35
H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil
DY
DY
R73
R73
12
0R2J-2-GP
0R2J-2-GP
CPU_PROCHOT# 40
Change to 62.10040.221 04/12 '07
4 4
A
B
C
D
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
Date: Sheet
Meron(1/3)-AGTL+/XDP
Meron(1/3)-AGTL+/XDP
Meron(1/3)-AGTL+/XDP
Hawke-Intel
Hawke-Intel
Hawke-Intel
5
5
5
E
of
of
of
SA
SA
SA
55Tuesday, May 08, 2007
55Tuesday, May 08, 2007
55Tuesday, May 08, 2007
A
B
C
D
E
H_D#[0..63]8
H_D#0 H_D#1 H_D#2 H_D#3
1 1
H_DSTBN#08 H_DSTBP#08
H_DINV#08
Close to CPU pin AD26 Z0=55 ohm with in 500mils .
1D05V_S0
2 2
R309
R309 1KR2F-3-GP
1KR2F-3-GP
1 2 12
R308
R308 2KR2F-3-GP
2KR2F-3-GP
3 3
C617
C617
1 2
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
PLACE C617 close to the TEST4 PIN, make sure TEST3,TEST4,TEST5 trace routing is reference to GND and away other noisy signals
DY
DY
H_DSTBN#18 H_DSTBP#18 H_DINV#18
CPU_BSEL04,8 CPU_BSEL14,8 CPU_BSEL24,8
H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14
H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1
V_CPU_GTLREF
TEST1
TP21TPAD28 TP21TPAD28
TEST2
TP23TPAD28 TP23TPAD28
TEST3
TP22TPAD28 TP22TPAD28
TEST4 TEST5
TP5TPAD28 TP5TPAD28
TEST6
TP24TPAD28 TP24TPAD28
CPU_BSEL0 CPU_BSEL1 CPU_BSEL2
AD26
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0
166
200
0
00
1
U47B
U47B
E22
D0#
F24
D1#
E26
D2#
G22
D3#
F23
D4#
G25
D5#
E25
D6#
E23
D7#
K24
D8#
G24
D9#
J24
D10#
J23
D11#
H22
D12#
F26
D13#
K22
D14#
H23
D15#
J26
DSTBN0#
H26
DSTBP0#
H25
DINV0#
N22
D16#
K25
D17#
P26
D18#
R23
D19#
L23
D20#
M24
D21#
L22
D22#
M23
D23#
P25
D24#
P23
D25#
P22
D26#
T24
D27#
R24
D28#
L25
D29#
T25
D30#
N25
D31#
L26
DSTBN1#
M26
DSTBP1#
N24
DINV1# GTLREF
C23
TEST1
D25
TEST2
C24
TEST3
AF26
TEST4
AF1
TEST5
A26
TEST6
B22
BSEL0
B23
BSEL1
C21
BSEL2
BGA479-SKT6-GPU3
BGA479-SKT6-GPU3
11
2 OF 4
2 OF 4
DATA GRP0 DATA GRP1
DATA GRP0 DATA GRP1
DATA GRP2DATA GRP3
DATA GRP2DATA GRP3
DSTBN2#
DSTBP2#
DSTBN3# DSTBP3#
MISC
MISC
DPRSTP#
PWRGOOD
D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47#
DINV2#
D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63#
DINV3# COMP0
COMP1 COMP2 COMP3
DPSLP#
DPWR#
SLP#
PSI#
Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22
AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20
R26 U26 AA1 Y1
E5 B5 D24 D6 D7 AE6
H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46
H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3
COMP0
R311 27D4R2F-L1-GPR311 27D4R2F-L1-GP
COMP1
R310 54D9R2F-L1-GPR310 54D9R2F-L1-GP
COMP2
R42 27D4R2F-L1-GPR42 27D4R2F-L1-GP
COMP3
R41 54D9R2F-L1-GPR41 54D9R2F-L1-GP
H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGOOD H_CPUSLP# PSI#
H_DSTBN#2 8 H_DSTBP#2 8 H_DINV#2 8
H_DSTBN#3 8 H_DSTBP#3 8 H_DINV#3 8
1 2 1 2 1 2 1 2
H_DPRSTP# 8,20,40 H_DPSLP# 20
H_DPWR# 8 H_PWRGOOD 20,45 H_CPUSLP# 8
PSI# 40
Resistor Placed within 0.5" of CPU pin. Trace should be at least 25 mils away from any other toggling signal . COMP[0,2] trace width is 18 mils. COMP[1,3] trace width is 4 mils .
VCC_CORE_S0 VCC_CORE_S0
3 OF 4
3 OF 4
U47C
U47C
A7
VCC
A9
VCC
A10
VCC
A12
VCC
A13
VCC
A15
VCC
A17
VCC
A18
VCC
A20
VCC
B7
VCC
B9
VCC
B10
VCC
B12
VCC
B14
VCC
B15
VCC
B17
VCC
B18
VCC
B20
VCC
C9
VCC
C10
VCC
C12
VCC
C13
VCC
C15
VCC
C17
VCC
C18
VCC
D9
VCC
D10
VCC
D12
VCC
D14
VCC
D15
VCC
D17
VCC
D18
VCC
E7
VCC
E9
VCC
E10
VCC
E12
VCC
E13
VCC
E15
VCC
E17
VCC
E18
VCC
E20
VCC
F7
VCC
F9
VCC
F10
VCC
F12
VCC
F14
VCC
F15
VCC
F17
VCC
F18
VCC
F20
VCC
AA7
VCC
AA9
VCC
AA10
VCC
AA12
VCC
AA13
VCC
AA15
VCC
AA17
VCC
AA18
VCC
AA20
VCC
AB9
VCC
AC10
VCC
AB10
VCC
AB12
VCC
AB14
VCC
AB15
VCC
AB17
VCC
AB18
VCC
BGA479-SKT6-GPU3
BGA479-SKT6-GPU3
VCCSENSE
VSSSENSE
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP
VCCA VCCA
VID0 VID1 VID2 VID3 VID4 VID5 VID6
AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20
G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21
B26 C26
AD6 AF5 AE5 AF4 AE3 AF3 AE2
AF7
AE7
CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6
VCC_SENSE
VSS_SENSE
1D05V_S0
12
C24
C24 SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
layout note: place C618 near PIN B26
CPU_VID[0..6] 40
VCC_SENSE 40
VSS_SENSE 40
VCC_SENSE
VSS_SENSE
1 2
R47 100R2F-L1-GP-UR47 100R2F-L1-GP-U
1 2
R48 100R2F-L1-GP-UR48 100R2F-L1-GP-U
1D5V_S0
12
12
C618
C618
C620
C620 SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
Length match within 25 mils . The trace
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
width/space/other is 20/7/25 .
VCC_CORE_S0
Close to CPU pin within 500mils
4 4
A
B
C
D
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
Date: Sheet of
Meron(2/3)-AGTL+/PWR
Meron(2/3)-AGTL+/PWR
Meron(2/3)-AGTL+/PWR
Hawke-Intel
Hawke-Intel
Hawke-Intel
6
6
6
E
of
of
SA
SA
SA
55Tuesday, May 08, 2007
55Tuesday, May 08, 2007
55Tuesday, May 08, 2007
A
B
C
VCC_CORE_S0
D
E
12
C64
C64
SC10U6D3V5KX-1GP
VCC_CORE_S0
12
C49
C49
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
4 OF 4
4 OF 4
U47D
U47D
1 1
2 2
3 3
4 4
A4
VSS
A8
VSS
A11
VSS
A14
VSS
A16
VSS
A19
VSS
A23
VSS
AF2
VSS
B6
VSS
B8
VSS
B11
VSS
B13
VSS
B16
VSS
B19
VSS
B21
VSS
B24
VSS
C5
VSS
C8
VSS
C11
VSS
C14
VSS
C16
VSS
C19
VSS
C2
VSS
C22
VSS
C25
VSS
D1
VSS
D4
VSS
D8
VSS
D11
VSS
D13
VSS
D16
VSS
D19
VSS
D23
VSS
D26
VSS
E3
VSS
E6
VSS
E8
VSS
E11
VSS
E14
VSS
E16
VSS
E19
VSS
E21
VSS
E24
VSS
F5
VSS
F8
VSS
F11
VSS
F13
VSS
F16
VSS
F19
VSS
F2
VSS
F22
VSS
F25
VSS
G4
VSS
G1
VSS
G23
VSS
G26
VSS
H3
VSS
H6
VSS
H21
VSS
H24
VSS
J2
VSS
J5
VSS
J22
VSS
J25
VSS
K1
VSS
K4
VSS
K23
VSS
K26
VSS
L3
VSS
L6
VSS
L21
VSS
L24
VSS
M2
VSS
M5
VSS
M22
VSS
M25
VSS
N1
VSS
N4
VSS
N23
VSS
N26
VSS
P3
VSS
BGA479-SKT6-GPU3
BGA479-SKT6-GPU3
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25
Place these capacitors on L1 (North side ,Secondary Layer)
Place these capacitors on L1 (North side ,Secondary Layer)
1D05V_S0
C586
C588
C588 SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1 2
C586 SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1 2
C581
C581 SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1 2
12
12
C43
C43
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
12
C42
C42
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C587
C587 SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1 2
C53
C53
C63
C63
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C54
C54
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C65
C65
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C580
C580 SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1 2
12
C45
C45
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C44
C44
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
DY
DY
12
DY
DY
C50
C50
C59
C59
12
C47
C47
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
DY
DY
12
C58
C58
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
DY
DY
12
C62
C62
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C52
C52
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
Mid Frequencd Decoupling
C579
C579 SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1 2
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
Place these inside socket cavity on L1 (North side Secondary)
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
A
B
C
D
Date: Sheet of
Meron(3/3)-GND&Bypass
Meron(3/3)-GND&Bypass
Meron(3/3)-GND&Bypass
Hawke-Intel
Hawke-Intel
Hawke-Intel
7
7
7
E
SA
SA
SA
55Tuesday, May 08, 2007
55Tuesday, May 08, 2007
55Tuesday, May 08, 2007
of
of
A
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12
H_SWNG
54D9R2F-L1-GP
54D9R2F-L1-GP
H_RCOMP H_SCOMP
H_SCOMP# H_RESET#
H_CPUSLP#
12
C643
C643
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
A
H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
H_RCOMP
12
R314
R314 24D9R2F-L-GP
24D9R2F-L-GP
1 1
2 2
1D05V_S0
12
12
R313
R313
3 3
layout note : Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces
Layout Note : H_RCOMP / H_VREF / H_SWNG trace width and spacing is 10/20
4 4
Layout Note : Place C643 within 100 mils of NB
54D9R2F-L1-GP
54D9R2F-L1-GP
H_RESET#5
H_CPUSLP#6
H_VREF
1D05V_S0
12
R325
R325 1KR2F-3-GP
1KR2F-3-GP
12
R324
R324 2KR2F-3-GP
2KR2F-3-GP
R312
R312
U57A
U57A
E2
H_D#0
G2
H_D#1
G7
H_D#2
M6
H_D#3
H7
H_D#4
H3
H_D#5
G4
H_D#6
F3
H_D#7
N8
H_D#8
H2
H_D#9
M10
H_D#10
N12
H_D#11
N9
H_D#12
H5
H_D#13
P13
H_D#14
K9
H_D#15
M2
H_D#16
W10
H_D#17
Y8
H_D#18
V4
H_D#19
M3
H_D#20
J1
H_D#21
N5
H_D#22
N3
H_D#23
W6
H_D#24
W9
H_D#25
N2
H_D#26
Y7
H_D#27
Y9
H_D#28
P4
H_D#29
W3
H_D#30
N1
H_D#31
AD12
H_D#32
AE3
H_D#33
AD9
H_D#34
AC9
H_D#35
AC7
H_D#36
AC14
H_D#37
AD11
H_D#38
AC11
H_D#39
AB2
H_D#40
AD7
H_D#41
AB1
H_D#42
Y3
H_D#43
AC6
H_D#44
AE2
H_D#45
AC5
H_D#46
AG3
H_D#47
AJ9
H_D#48
AH8
H_D#49
AJ14
H_D#50
AE9
H_D#51
AE11
H_D#52
AH12
H_D#53
AJ5
H_D#54
AH5
H_D#55
AJ6
H_D#56
AE7
H_D#57
AJ7
H_D#58
AJ2
H_D#59
AE5
H_D#60
AJ3
H_D#61
AH2
H_D#62
AH13
H_D#63
B3
H_SWING
C2
H_RCOMP
W1
H_SCOMP
W2
H_SCOMP#
B6
H_CPURST#
E5
H_CPUSLP#
B9
H_AVREF
A9
H_DVREF
CRESTLINE-GP-U-NF
CRESTLINE-GP-U-NF
100R2F-L1-GP-U
100R2F-L1-GP-U
1 OF 10
1 OF 10
H_ADSTB#0 H_ADSTB#1
HOST
HOST
H_DEFER#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3
H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
1D05V_S0
R320
R320
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8
H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
H_ADS#
H_BNR#
H_BPRI#
H_BREQ# H_DBSY#
H_DRDY#
H_HIT#
H_HITM# H_LOCK# H_TRDY#
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
H_RS#0 H_RS#1 H_RS#2
12
12
R321
R321 221R2F-2-GP
221R2F-2-GP
J13 B11 C11 M11 C15 F16 L13 G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17 B15 E17 C18 A19 B19 N19
G12 H17 G20 C8 E8 F12 D6 C10 AM5 AM7 H8 K7 E4 C6 G10 B7
K5 L2 AD13 AE13
M7 K3 AD2 AH11
L7 K2 AC2 AJ10
M14 E13 A11 H13 B12
E12 D7 D8
12
C634
C634 SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
Layout Note : Place C634 near pin B3 of NB
B
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BR0# H_DEFER#
H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM# H_LOCK# H_TRDY#
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3
H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
H_SWNGH_VREF
B
H_A#[3..35] 5H_D#[0..63]6
H_ADS# 5 H_ADSTB#0 5 H_ADSTB#1 5 H_BNR# 5
H_BPRI# 5
H_BR0# 5
H_DEFER# 5
H_DBSY# 5 CLK_MCH_BCLK 4 CLK_MCH_BCLK# 4
H_DPWR# 6
H_DRDY# 5
H_HIT# 5
H_HITM# 5 H_LOCK# 5 H_TRDY# 5
H_DINV#0 6 H_DINV#1 6 H_DINV#2 6 H_DINV#3 6
H_DSTBN#0 6 H_DSTBN#1 6 H_DSTBN#2 6 H_DSTBN#3 6
H_DSTBP#0 6 H_DSTBP#1 6 H_DSTBP#2 6 H_DSTBP#3 6
H_REQ#0 5 H_REQ#1 5 H_REQ#2 5 H_REQ#3 5 H_REQ#4 5
H_RS#0 5 H_RS#1 5 H_RS#2 5
PM_PWROK21,35
VGATE_PWRGD21,40
1D8V_S3
12
12
C668
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
SM_RCOMP_VOH
SM_RCOMP_VOL
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
CFG[17:3] have internal pull up CFG[19:18] have internal pull down
C668
12
C680
C680
PLT_RST1#19,23,27,28,29,33,47
R128 0R2J-2-GP
R128 0R2J-2-GP
1 2 1 2
R129 0R2J-2-GPR129 0R2J-2-GP
PM_EXTTS#0 PM_EXTTS#1
CLKREQ#_B
R103 100R2J-2-GPR103 100R2J-2-GP
DY
DY
12
C672
C672
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
12
12
12
C683
C683
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
PM_BMBUSY#21 H_DPRSTP#6,20,40 PM_EXTTS#014 PM_EXTTS#115
12
H_THERMTRIP#5,20,33,45
RN21
RN21
1 2 3
SRN10KJ-5-GP
SRN10KJ-5-GP
1 2
R113 10KR2J-3-GPR113 10KR2J-3-GP
C
R329
R329 1KR2F-3-GP
1KR2F-3-GP
R330
R330 3K01R2F-3-GP
3K01R2F-3-GP
R332
R332 1KR2F-3-GP
1KR2F-3-GP
CPU_BSEL04,6 CPU_BSEL14,6 CPU_BSEL24,6
DPRSLPVR21,40
PM_POK_R
4
C
TP58TP58 TP62TP62 TP59TP59 TP52TP52 TP53TP53 TP63TP63 TP61TP61 TP60TP60 TP57TP57
TP54TP54 TP67TP67
TP69TP69 TP70TP70
3D3V_S0
CPU_BSEL0 CPU_BSEL1 CPU_BSEL2
CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13
CFG16 CFG18
CFG19 CFG20
PM_BMBUSY# H_DPRSTP# PM_EXTTS#0 PM_EXTTS#1 PM_POK_R PLT_RST_R# H_THERMTRIP# DPRSLPVR
D
2 OF 10
2 OF 10
U57B
U57B
P36
RSVD#P36
P37
RSVD#P37
R35
RSVD#R35
N35
RSVD#N35
AR12
RSVD#AR12
AR13
RSVD#AR13
AM12
RSVD#AM12
AN13
RSVD#AN13
J12
RSVD#J12
AR37
RSVD#AR37
AM36
RSVD#AM36
AL36
RSVD#AL36
AM37
RSVD#AM37
D20
RSVD#D20
H10
RSVD#H10
B51
RSVD#B51
BJ20
RSVD#BJ20
BK22
RSVD#BK22
BF19
RSVD#BF19
BH20
RSVD#BH20
BK18
RSVD#BK18
BJ18
RSVD#BJ18
BF23
RSVD#BF23
BG23
RSVD#BG23
BC23
RSVD#BC23
BD24
RSVD#BD24
BH39
RSVD#BH39
AW20
RSVD#AW20
BK20
RSVD#BK20
B44
RSVD#B44
C44
RSVD#C44
A35
RSVD#A35
B37
RSVD#B37
B36
RSVD#B36
B34
RSVD#B34
C34
RSVD#C34
P27
CFG0
N27
CFG1
N24
CFG2
C21
CFG3
C23
CFG4
F23
CFG5
N23
CFG6
G23
CFG7
J20
CFG8
C20
CFG9
R24
CFG10
L23
CFG11
J23
CFG12
E23
CFG13
E20
CFG14
K23
CFG15
M20
CFG16
M24
CFG17
L32
CFG18
N33
CFG19
L35
CFG20
G41
PM_BM_BUSY#
L39
PM_DPRSTP#
L36
PM_EXT_TS#0
J36
PM_EXT_TS#1
AW49
PWROK
AV20
RSTIN#
N20
THERMTRIP#
G36
DPRSLPVR
BJ51
NC#BJ51
BK51
NC#BK51
BK50
NC#BK50
BL50
NC#BL50
BL49
NC#BL49
BL3
NC#BL3
BL2
NC#BL2
BK1
NC#BK1
BJ1
NC#BJ1
E1
NC#E1
A5
NC#A5
C51
NC#C51
B50
NC#B50
A50
NC#A50
A49
NC#A49
BK2
NC#BK2
CRESTLINE-GP-U-NF
CRESTLINE-GP-U-NF
RSVD
RSVD
DDR MUXING
DDR MUXING
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_VREF#AR49
SM_VREF#AW4
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
CLK
CLK
DMI
DMI
CFG PM NC
CFG PM NC
SDVO_CTRL_CLK
SDVO_CTRL_DATA
MISC ME GRAPHICS VID
MISC ME GRAPHICS VID
SM_RCOMP#
GFX_VR_EN
SM_CK0 SM_CK1 SM_CK3 SM_CK4
SM_CK#0 SM_CK#1 SM_CK#3 SM_CK#4
SM_CKE0 SM_CKE1 SM_CKE3 SM_CKE4
SM_CS#0 SM_CS#1 SM_CS#2 SM_CS#3
SM_ODT0 SM_ODT1 SM_ODT2 SM_ODT3
SM_RCOMP
PEG_CLK
PEG_CLK#
DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3
DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3
DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
GFX_VID0 GFX_VID1 GFX_VID2 GFX_VID3
CL_CLK
CL_DATA
CL_PWROK
CL_RST# CL_VREF
CLKREQ#
ICH_SYNC#
TEST1 TEST2
AV29 BB23 BA25 AV23
AW30 BA23 AW25 AW23
BE29 AY32 BD39 BG37
BG20 BK16 BG16 BE13
BH18 BJ15 BJ14 BE16
BK31 BL31
BL15 BK14
AR49 AW4
B42 C42 H48 H47
K44 K45
AN47 AJ38 AN42 AN46
AM47 AJ39 AN41 AN45
AJ46 AJ41 AM40 AM44
AJ47 AJ42 AM39 AM43
E35 A39 C38 B39 E36
AM49 AK50 AT43 AN49 AM50
H35 K36 G39 G40
A37 R32
0921 P/N CHANGE TO 71.CREST.M02
D
E
M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3
M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3
DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB
DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB#
M_ODT0 M_ODT1 M_ODT2 M_ODT3
SM_RCOMP_VOH SM_RCOMP_VOL
SM_RCOMP SM_RCOMP#
CLK_MCH_3GPLL CLK_MCH_3GPLL#
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3
DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3
DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3
DFGT_VID0 DFGT_VID1 DFGT_VID2 DFGT_VID3 DFGT_VR_EN
CL_VREF
For Discrete: Short to GND.
MCH_ICH_SYNC#
TEST1_GMCH TEST2_GMCH
R108
R108 20KR2J-L2-GP
20KR2J-L2-GP
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev Custom
Custom
Custom Date: Sheet
Date: Sheet
Date: Sheet
M_CLK_DDR0 14 M_CLK_DDR1 14 M_CLK_DDR2 15 M_CLK_DDR3 15
M_CLK_DDR#0 14 M_CLK_DDR#1 14 M_CLK_DDR#2 15 M_CLK_DDR#3 15
DDR_CKE0_DIMMA 14 DDR_CKE1_DIMMA 14 DDR_CKE2_DIMMB 15 DDR_CKE3_DIMMB 15
DDR_CS0_DIMMA# 14 DDR_CS1_DIMMA# 14 DDR_CS2_DIMMB# 15 DDR_CS3_DIMMB# 15
M_ODT0 14 M_ODT1 14 M_ODT2 15 M_ODT3 15
1D8V_S3
1 2
R328 20R2F-GPR328 20R2F-GP
1 2
R327 20R2F-GPR327 20R2F-GP
For Discrete: Short to GND.
DMI_TXN0 21 DMI_TXN1 21 DMI_TXN2 21 DMI_TXN3 21
DMI_TXP0 21 DMI_TXP1 21 DMI_TXP2 21 DMI_TXP3 21
DMI_RXN0 21 DMI_RXN1 21 DMI_RXN2 21 DMI_RXN3 21
DMI_RXP0 21 DMI_RXP1 21 DMI_RXP2 21 DMI_RXP3 21
TP72TP72 TP113TP113 TP112TP112 TP114TP114 TP71TP71
R122
R122
1 2
0R0402-PAD
0R0402-PAD
CLKREQ#_B 4 MCH_ICH_SYNC# 21
DDR_VREF_S3
CLK_MCH_3GPLL 4 CLK_MCH_3GPLL# 4
CL_CLK0 21 CL_DATA0 21
PM_POK_RCLPWROK_MCH
CL_RST# 21
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
R338
R338
1 2
0R0402-PAD
0R0402-PAD
Hawke-Intel
Hawke-Intel
Hawke-Intel
1D25V_S0
12
C749
C749
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
8
8
8
E
DDR_VREF_S3
1 2
CRESTLINE(1/6)-AGTL+/DMI/DDR2
CRESTLINE(1/6)-AGTL+/DMI/DDR2
CRESTLINE(1/6)-AGTL+/DMI/DDR2
R366
R366 1KR2F-3-GP
1KR2F-3-GP
1 2 12
R365
R365 392R2F-GP
392R2F-GP
SA
SA
SA
55Tuesday, May 08, 2007
55Tuesday, May 08, 2007
55Tuesday, May 08, 2007
of
of
of
A
B
C
D
E
DDR_A_D[0..63] 14
SA_BS0 SA_BS1 SA_BS2
SA_CAS#
SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7
SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6
SA_DQS7 SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7
SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8
SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14
SA_RAS#
SA_WE#
DDR_A_BS[0..2] 14 DDR_A_DM[0..7] 14 DDR_A_DQS[0..7] 14 DDR_A_DQS#[0..7] 14 DDR_A_MA[0..14] 14
5 OF 10
5 OF 10
U57E
U57E
DDR_A_BS0
BB19
DDR_A_BS1
BK19
DDR_A_BS2
BF29
DDR_A_CAS#
BL17
DDR_A_DM0
AT45
DDR_A_DM1
BD44
DDR_A_DM2
BD42
DDR_A_DM3
AW38
DDR_A_DM4
AW13
DDR_A_DM5
BG8
DDR_A_DM6
AY5
DDR_A_DM7
AN6
DDR_A_DQS0
AT46
DDR_A_DQS1
BE48
DDR_A_DQS2
BB43
DDR_A_DQS3
BC37
DDR_A_DQS4
BB16
DDR_A_DQS5
BH6
DDR_A_DQS6
BB2
DDR_A_DQS7
AP3
DDR_A_DQS#0
AT47
DDR_A_DQS#1
BD47
DDR_A_DQS#2
BC41
DDR_A_DQS#3
BA37
DDR_A_DQS#4
BA16
DDR_A_DQS#5
BH7
DDR_A_DQS#6
BC1
DDR_A_DQS#7
AP2
DDR_A_MA0
BJ19
DDR_A_MA1
BD20
DDR_A_MA2
BK27
DDR_A_MA3
BH28
DDR_A_MA4
BL24
DDR_A_MA5
BK28
DDR_A_MA6
BJ27
DDR_A_MA7
BJ25
DDR_A_MA8
BL28
DDR_A_MA9
BA28
DDR_A_MA10
BC19
DDR_A_MA11
BE28
DDR_A_MA12
BG30
DDR_A_MA13
BJ16
DDR_A_MA14 DDR_B_MA14
BJ29
DDR_A_RAS#
BE18
SA_RCVEN#
AY20
DDR_A_WE#
BA19
DDR_A_CAS# 14 DDR_B_CAS# 15
DDR_A_RAS# 14
TP56TP56 TP51TP51
DDR_A_WE# 14
DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6
DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63
AP49
SB_DQ0
AR51
SB_DQ1
AW50
SB_DQ2
AW51
SB_DQ3
AN51
SB_DQ4
AN50
SB_DQ5
AV50
SB_DQ6
AV49
SB_DQ7
BA50
SB_DQ8
BB50
SB_DQ9
BA49
SB_DQ10
BE50
SB_DQ11
BA51
SB_DQ12
AY49
SB_DQ13
BF50
SB_DQ14
BF49
SB_DQ15
BJ50
SB_DQ16
BJ44
SB_DQ17
BJ43
SB_DQ18
BL43
SB_DQ19
BK47
SB_DQ20
BK49
SB_DQ21
BK43
SB_DQ22
BK42
SB_DQ23
BJ41
SB_DQ24
BL41
SB_DQ25
BJ37
SB_DQ26
BJ36
SB_DQ27
BK41
SB_DQ28
BJ40
SB_DQ29
BL35
SB_DQ30
BK37
SB_DQ31
BK13
SB_DQ32
BE11
SB_DQ33
BK11
SB_DQ34
BC11
SB_DQ35
BC13
SB_DQ36
BE12
SB_DQ37
BC12
SB_DQ38
BG12
SB_DQ39
BJ10
SB_DQ40
BL9
SB_DQ41
BK5
SB_DQ42
BL5
SB_DQ43
BK9
SB_DQ44
BK10
SB_DQ45
BJ8
SB_DQ46
BJ6
SB_DQ47
BF4
SB_DQ48
BH5
SB_DQ49
BG1
SB_DQ50
BC2
SB_DQ51
BK3
SB_DQ52
BE4
SB_DQ53
BD3
SB_DQ54
BJ2
SB_DQ55
BA3
SB_DQ56
BB3
SB_DQ57
AR1
SB_DQ58
AT3
SB_DQ59
AY2
SB_DQ60
AY3
SB_DQ61
AU2
SB_DQ62
AT2
SB_DQ63
CRESTLINE-GP-U-NF
CRESTLINE-GP-U-NF
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
1 1
4 OF 10
4 OF 10
U57D
U57D
DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8
DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15
2 2
3 3
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63
AR43
SA_DQ0
AW44
SA_DQ1
BA45
SA_DQ2
AY46
SA_DQ3
AR41
SA_DQ4
AR45
SA_DQ5
AT42
SA_DQ6
AW47
SA_DQ7
BB45
SA_DQ8
BF48
SA_DQ9
BG47
SA_DQ10
BJ45
SA_DQ11
BB47
SA_DQ12
BG50
SA_DQ13
BH49
SA_DQ14
BE45
SA_DQ15
AW43
SA_DQ16
BE44
SA_DQ17
BG42
SA_DQ18
BE40
SA_DQ19
BF44
SA_DQ20
BH45
SA_DQ21
BG40
SA_DQ22
BF40
SA_DQ23
AR40
SA_DQ24
AW40
SA_DQ25
AT39
SA_DQ26
AW36
SA_DQ27
AW41
SA_DQ28
AY41
SA_DQ29
AV38
SA_DQ30
AT38
SA_DQ31
AV13
SA_DQ32
AT13
SA_DQ33
AW11
SA_DQ34
AV11
SA_DQ35
AU15
SA_DQ36
AT11
SA_DQ37
BA13
SA_DQ38
BA11
SA_DQ39
BE10
SA_DQ40
BD10
SA_DQ41
BD8
SA_DQ42
AY9
SA_DQ43
BG10
SA_DQ44
AW9
SA_DQ45
BD7
SA_DQ46
BB9
SA_DQ47
BB5
SA_DQ48
AY7
SA_DQ49
AT5
SA_DQ50
AT7
SA_DQ51
AY6
SA_DQ52
BB7
SA_DQ53
AR5
SA_DQ54
AR8
SA_DQ55
AR9
SA_DQ56
AN3
SA_DQ57
AM8
SA_DQ58
AN10
SA_DQ59
AT9
SA_DQ60
AN9
SA_DQ61
AM9
SA_DQ62
AN11
SA_DQ63
CRESTLINE-GP-U-NF
CRESTLINE-GP-U-NF
DDR SYSTEM MEMORRY A
DDR SYSTEM MEMORRY A
SA_RCVEN#
SB_BS0 SB_BS1 SB_BS2
SB_CAS#
SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7
SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6
SB_DQS7 SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7
SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8
SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14
SB_RAS#
SB_RCVEN#
SB_WE#
DDR_B_D[0..63] 15 DDR_B_BS[0..2] 15 DDR_B_DM[0..7] 15 DDR_B_DQS[0..7] 15 DDR_B_DQS#[0..7] 15 DDR_B_MA[0..14] 15
DDR_B_BS0
AY17
DDR_B_BS1
BG18
DDR_B_BS2
BG36
DDR_B_CAS#
BE17
DDR_B_DM0
AR50
DDR_B_DM1
BD49
DDR_B_DM2
BK45
DDR_B_DM3
BL39
DDR_B_DM4
BH12
DDR_B_DM5
BJ7
DDR_B_DM6
BF3
DDR_B_DM7
AW2
DDR_B_DQS0
AT50
DDR_B_DQS1
BD50
DDR_B_DQS2
BK46
DDR_B_DQS3
BK39
DDR_B_DQS4
BJ12
DDR_B_DQS5
BL7
DDR_B_DQS6
BE2
DDR_B_DQS7
AV2
DDR_B_DQS#0
AU50
DDR_B_DQS#1
BC50
DDR_B_DQS#2
BL45
DDR_B_DQS#3
BK38
DDR_B_DQS#4
BK12
DDR_B_DQS#5
BK7
DDR_B_DQS#6
BF2
DDR_B_DQS#7
AV3
DDR_B_MA0
BC18
DDR_B_MA1
BG28
DDR_B_MA2
BG25
DDR_B_MA3
AW17
DDR_B_MA4
BF25
DDR_B_MA5
BE25
DDR_B_MA6
BA29
DDR_B_MA7
BC28
DDR_B_MA8
AY28
DDR_B_MA9
BD37
DDR_B_MA10
BG17
DDR_B_MA11
BE37
DDR_B_MA12
BA39
DDR_B_MA13
BG13 BE24
DDR_B_RAS#
AV16
SB_RCVEN#
AY18
DDR_B_WE#
BC17
DDR_B_RAS# 15
DDR_B_WE# 15
4 4
A
B
C
D
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CRESTLINE(2/6)-DDR2 A/B CH
CRESTLINE(2/6)-DDR2 A/B CH
CRESTLINE(2/6)-DDR2 A/B CH
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
Date: Sheet
Hawke-Intel
Hawke-Intel
Hawke-Intel
E
of
of
of
9
9
9
SA
SA
SA
55Tuesday, May 08, 2007
55Tuesday, May 08, 2007
55Tuesday, May 08, 2007
A
1D05V_S0
3 OF 10
3 OF 10
U57C
U57C
J40
L_BKLT_CTRL
H39
L_BKLT_EN
E39
L_CTRL_CLK
E40
L_CTRL_DATA
C37
L_DDC_CLK
D35
L_DDC_DATA
K40
N41 N40 D46 C45 D44 E42
G51 E51 F49 C48
G50 E50 F48 D47
G44 B47 B45
E44 A47 A45
E27 G27 K27
F27
M35 P33
H32 G32 K29
F29 E29
K33 G35 E33 C32 F33
L41 L43
J27 L27
J29
L_VDD_EN LVDS_IBG
LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK
LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3
LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3
LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2
LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2
TVA_DAC TVB_DAC TVC_DAC
TVA_RTN TVB_RTN TVC_RTN
TV_DCONSEL0 TV_DCONSEL1
CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED#
CRT_DDC_CLK CRT_DDC_DATA CRT_VSYNC CRT_TVO_IREF CRT_HSYNC
1 1
2 2
3 3
PEG_COMPI
PEG_COMPO
LVDS
LVDS
PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15
TV VGA
TV VGA
PEG_TX#10
PCI_EXPRESS GRAPHICS
PCI_EXPRESS GRAPHICS
PEG_TX#11 PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15
PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8 PEG_RX#9
PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8
PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15
PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9
PEG_TX0
PEG_TX1
PEG_TX2
PEG_TX3
PEG_TX4
PEG_TX5
PEG_TX6
PEG_TX7
PEG_TX8
PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15
N43 M43
J51 L51 N47 T45 T50 U40 Y44 Y40 AB51 W49 AD44 AD40 AG46 AH49 AG45 AG41
J50 L50 M47 U44 T49 T41 W45 W41 AB50 Y48 AC45 AC41 AH47 AG49 AH45 AG42
N45 U39 U47 N51 R50 T42 Y43 W46 W38 AD39 AC46 AC49 AC42 AH39 AE49 AH44
M45 T38 T46 N50 R51 U43 W42 Y47 Y39 AC38 AD47 AC50 AD43 AG39 AE50 AH43
R119
R119
1 2
24D9R2F-L-GP
24D9R2F-L-GP
PEGCOMP
PCIE_MRX_GTX_N0 PCIE_MRX_GTX_N1 PCIE_MRX_GTX_N2 PCIE_MRX_GTX_N3 PCIE_MRX_GTX_N4 PCIE_MRX_GTX_N5 PCIE_MRX_GTX_N6 PCIE_MRX_GTX_N7 PCIE_MRX_GTX_N8 PCIE_MRX_GTX_N9 PCIE_MRX_GTX_N10 PCIE_MRX_GTX_N11 PCIE_MRX_GTX_N12 PCIE_MRX_GTX_N13 PCIE_MRX_GTX_N14 PCIE_MRX_GTX_N15
PCIE_MRX_GTX_P0 PCIE_MRX_GTX_P1 PCIE_MRX_GTX_P2 PCIE_MRX_GTX_P3 PCIE_MRX_GTX_P4 PCIE_MRX_GTX_P5 PCIE_MRX_GTX_P6 PCIE_MRX_GTX_P7 PCIE_MRX_GTX_P8 PCIE_MRX_GTX_P9 PCIE_MRX_GTX_P10 PCIE_MRX_GTX_P11 PCIE_MRX_GTX_P12 PCIE_MRX_GTX_P13 PCIE_MRX_GTX_P14 PCIE_MRX_GTX_P15
PCIE_MTX_GRX_C_N0 PCIE_MTX_GRX_C_N1 PCIE_MTX_GRX_C_N2 PCIE_MTX_GRX_C_N3 PCIE_MTX_GRX_C_N4 PCIE_MTX_GRX_C_N5 PCIE_MTX_GRX_C_N6 PCIE_MTX_GRX_C_N7 PCIE_MTX_GRX_C_N8 PCIE_MTX_GRX_C_N9 PCIE_MTX_GRX_C_N10 PCIE_MTX_GRX_C_N11 PCIE_MTX_GRX_C_N12 PCIE_MTX_GRX_C_N13 PCIE_MTX_GRX_C_N14 PCIE_MTX_GRX_C_N15
PCIE_MTX_GRX_C_P0 PCIE_MTX_GRX_C_P1 PCIE_MTX_GRX_C_P2 PCIE_MTX_GRX_C_P3 PCIE_MTX_GRX_C_P4 PCIE_MTX_GRX_C_P5 PCIE_MTX_GRX_C_P6 PCIE_MTX_GRX_C_P7 PCIE_MTX_GRX_C_P8 PCIE_MTX_GRX_C_P9 PCIE_MTX_GRX_C_P10 PCIE_MTX_GRX_C_P11 PCIE_MTX_GRX_C_P12 PCIE_MTX_GRX_C_P13 PCIE_MTX_GRX_C_P14 PCIE_MTX_GRX_C_P15
B
PEGCOMP trace width and spacing is 20/25 mils.
PCIE_MRX_GTX_N[0..15]
PCIE_MRX_GTX_P[0..15]
C159 SCD1U10V2KX-4GPC159 SCD1U10V2KX-4GP
12
C649 SCD1U10V2KX-4GPC649 SCD1U10V2KX-4GP
12
C652 SCD1U10V2KX-4GPC652 SCD1U10V2KX-4GP
12
C190 SCD1U10V2KX-4GPC190 SCD1U10V2KX-4GP
12
C654 SCD1U10V2KX-4GPC654 SCD1U10V2KX-4GP
12
C659 SCD1U10V2KX-4GPC659 SCD1U10V2KX-4GP
12
C664 SCD1U10V2KX-4GPC664 SCD1U10V2KX-4GP
12
C667 SCD1U10V2KX-4GPC667 SCD1U10V2KX-4GP
12
C674 SCD1U10V2KX-4GPC674 SCD1U10V2KX-4GP
12
C679 SCD1U10V2KX-4GPC679 SCD1U10V2KX-4GP
12
C684 SCD1U10V2KX-4GPC684 SCD1U10V2KX-4GP
12
C689 SCD1U10V2KX-4GPC689 SCD1U10V2KX-4GP
12
C696 SCD1U10V2KX-4GPC696 SCD1U10V2KX-4GP
12
C701 SCD1U10V2KX-4GPC701 SCD1U10V2KX-4GP
12
C710 SCD1U10V2KX-4GPC710 SCD1U10V2KX-4GP
12
C717 SCD1U10V2KX-4GPC717 SCD1U10V2KX-4GP
12
C164 SCD1U10V2KX-4GPC164 SCD1U10V2KX-4GP
12
C648 SCD1U10V2KX-4GPC648 SCD1U10V2KX-4GP
12
C651 SCD1U10V2KX-4GPC651 SCD1U10V2KX-4GP
12
C182 SCD1U10V2KX-4GPC182 SCD1U10V2KX-4GP
12
C653 SCD1U10V2KX-4GPC653 SCD1U10V2KX-4GP
12
C656 SCD1U10V2KX-4GPC656 SCD1U10V2KX-4GP
12
C661 SCD1U10V2KX-4GPC661 SCD1U10V2KX-4GP
12
C666 SCD1U10V2KX-4GPC666 SCD1U10V2KX-4GP
12
C669 SCD1U10V2KX-4GPC669 SCD1U10V2KX-4GP
12
C677 SCD1U10V2KX-4GPC677 SCD1U10V2KX-4GP
12
C681 SCD1U10V2KX-4GPC681 SCD1U10V2KX-4GP
12
C686 SCD1U10V2KX-4GPC686 SCD1U10V2KX-4GP
12
C691 SCD1U10V2KX-4GPC691 SCD1U10V2KX-4GP
12
C697 SCD1U10V2KX-4GPC697 SCD1U10V2KX-4GP
12
C706 SCD1U10V2KX-4GPC706 SCD1U10V2KX-4GP
12
C715 SCD1U10V2KX-4GPC715 SCD1U10V2KX-4GP
12
PCIE_MRX_GTX_N[0..15] 47
PCIE_MRX_GTX_P[0..15] 47
PCIE_MTX_GRX_N0 PCIE_MTX_GRX_N1 PCIE_MTX_GRX_N2 PCIE_MTX_GRX_N3 PCIE_MTX_GRX_N4 PCIE_MTX_GRX_N5 PCIE_MTX_GRX_N6 PCIE_MTX_GRX_N7 PCIE_MTX_GRX_N8 PCIE_MTX_GRX_N9 PCIE_MTX_GRX_N10 PCIE_MTX_GRX_N11 PCIE_MTX_GRX_N12 PCIE_MTX_GRX_N13 PCIE_MTX_GRX_N14 PCIE_MTX_GRX_N15
PCIE_MTX_GRX_P0 PCIE_MTX_GRX_P1 PCIE_MTX_GRX_P2 PCIE_MTX_GRX_P3 PCIE_MTX_GRX_P4 PCIE_MTX_GRX_P5 PCIE_MTX_GRX_P6 PCIE_MTX_GRX_P7 PCIE_MTX_GRX_P8 PCIE_MTX_GRX_P9 PCIE_MTX_GRX_P10 PCIE_MTX_GRX_P11 PCIE_MTX_GRX_P12 PCIE_MTX_GRX_P13 PCIE_MTX_GRX_P14 PCIE_MTX_GRX_P15
PCIE_MTX_GRX_N[0..15]
PCIE_MTX_GRX_P[0..15]
C
PCIE_MTX_GRX_N[0..15] 47
PCIE_MTX_GRX_P[0..15] 47
D
Strap Pin Table
CFG[2:0] FSB Freq select
CFG5 (DMI select)
CFG6 Reserved
CFG7 (CPU Strap)
CFG8 (Low power PCIE)
(PCIE Graphics Lane Reversal)
CFG[13:12] (XOR/ALLZ)
CFG16 (FSB Dynamic ODT)
CFG19(DMI Lane Reversal)
CFG20(PCIE/SDVO consurrent)
CFG9
CFG[11:10] Reserved
CFG[15:14] Reserved
CFG[18:17] Reversed
SDVO_CTRLDATA 0 = No SDVO Device Present *
E
010 = FSB 800MHz 011 = FSB 667MHz Others = Reserved
0 = DMI x 2 1 = DMI x 4 *
0 = Reserved 1 = Mobile CPU *
0 = Normal mode 1 = Low Power mode *
0 = Reverse Lane 1 = Normal Operation *
00 = Reserved 01 = XOR Mode Enabled 10 = All Z Mode Enabled 11 = Normal Operation (Default)*
0 = Disable 1 = Enable *
1 = SDVO Device Present
0 = Normal Operation * (Lane number in Order) 1 = Reverse lane
0 = Only PCIE or SDVO is operational * 1 = PCIE/SDVO are operating simu.
CRESTLINE-GP-U-NF
For Discrete
4 4
CRESTLINE-GP-U-NF
A
For Discrete
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CRESTLINE(3/6)-VGA/LVDS/TV
CRESTLINE(3/6)-VGA/LVDS/TV
CRESTLINE(3/6)-VGA/LVDS/TV
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3
Tuesday, May 08, 2007
Date: Sheet
Tuesday, May 08, 2007
Date: Sheet
Tuesday, May 08, 2007
B
C
D
Date: Sheet of
Hawke-Intel
Hawke-Intel
Hawke-Intel
E
of
of
10 55
10 55
10 55
SA
SA
SA
A
1 1
120ohm 100MHz 200mA 0.2ohm DC
1D25V_S0 1D25V_S0_HPLL
1D25V_S0 1D25V_S0_MPLL
2 2
120ohm 100MHz 200mA 0.2ohm DC
1D25V_S0 1D25V_S0_PEGPLL
3 3
4 4
L36
L36
BLM18AG121SN-1GP
BLM18AG121SN-1GP
12
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C757
C757
12
L8
L8
L9
L9
1D25V_S0
12
TC16
TC16
ST100U6D3VBM-9GP
ST100U6D3VBM-9GP
DY
DY
1D25V_S0
12
C243
C243
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1 2
BLM18AG121SN-1GP
BLM18AG121SN-1GP
120ohm 100MHz 200mA 0.2ohm DC
BLM18AG121SN-1GP
BLM18AG121SN-1GP
1D5V_S0
C95
C95
C86
C86
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C244
C244
C231
C231
SCD022U16V2KX-3GP
SCD022U16V2KX-3GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
12
12
12
C624
C624
B
12
C119
C119 SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C96
C96 SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
3D3V_S0
C747
C747
12
C181
C181
C169
C169
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
12
C251
C251
C207
C207
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
1D25V_S0
1 2
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C311
C311
12
12
12
C748
C748 SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C644
C644
C192
C192
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C236
C236
C239
C239
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1 2
For Discrete
For Discrete
20mil
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
For Discrete
For Discrete
U57H
U57H
J32
VCC_SYNC
A33
VCCA_CRT_DAC
B33
VCCA_CRT_DAC
A30
VCCA_DAC_BG
B32
VSSA_DAC_BG
B49
VCCA_DPLLA
H49
VCCA_DPLLB
AL2
VCCA_HPLL
AM2
VCCA_MPLL
A41
VCCA_LVDS
B41
VSSA_LVDS
K50
VCCA_PEG_BG
K49
VSSA_PEG_BG
U51
VCCA_PEG_PLL
AW18
VCCA_SM
AV19
VCCA_SM
AU19
VCCA_SM
AU18
VCCA_SM
AU17
VCCA_SM
AT22
VCCA_SM
AT21
VCCA_SM
AT19
VCCA_SM
AT18
VCCA_SM
AT17
VCCA_SM
AR17
VCCA_SM_NCTF
AR16
VCCA_SM_NCTF
BC29
VCCA_SM_CK
BB29
VCCA_SM_CK
C25
VCCA_TVA_DAC
B25
VCCA_TVA_DAC
C27
VCCA_TVB_DAC
B27
VCCA_TVB_DAC
B28
VCCA_TVC_DAC
A28
VCCA_TVC_DAC
M32
VCCD_CRT
L29
VCCD_TVDAC
0.06A
N28
VCCD_QDAC
AN2
VCCD_HPLL
U48
VCCD_PEG_PLL
J41
VCCD_LVDS
H42
VCCD_LVDS
CRESTLINE-GP-U-NF
CRESTLINE-GP-U-NF
8 OF 10
8 OF 10
0.05A
0.05A
0.015A
0.15A
0.25A
POWER
POWER
A LVDS PLL CRT
A LVDS PLL CRT
A PEG
A PEG
0.1A
0.735A
TV A CK A SM
TV A CK A SM
0.1A
LVDS TV/CRT
LVDS TV/CRT
C
0.2A
AXD
AXD
VCC_AXD_NCTF
AXF
AXF
0.35A
0.2A
VCC_SM_CK VCC_SM_CK VCC_SM_CK VCC_SM_CK
SM CK
SM CK
VCC_TX_LVDS
HV
HV
1.2A
PEG
PEG
VCC_RXR_DMI VCC_RXR_DMI
DMI
DMI
0.25A
0.85A
VTT
VTT
VCC_AXD VCC_AXD VCC_AXD VCC_AXD VCC_AXD VCC_AXD
VCC_AXF VCC_AXF VCC_AXF
VCC_DMI
0.1A
VCC_HV VCC_HV
0.1A
VCC_PEG VCC_PEG VCC_PEG VCC_PEG VCC_PEG
VTTLF VTTLF VTTLF
VTTLF
VTTLF
VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT
U13 U12 U11 U9 U8 U7 U5 U3 U2 U1 T13 T11 T10 T9 T7 T6 T5 T3 T2 R3 R2 R1
AT23 AU28 AU24 AT29 AT25 AT30
AR29
B23 B21 A21
AJ50
BK24 BK23 BJ24 BJ23
A43
C40 B40
AD51 W50 W51 V49 V50
AH50 AH51
A7 F2 AH1
1D05V_S0
For Discrete
VTTLF1 VTTLF2 VTTLF3
12
DY
DY
1
1
2
2
12
C219
C219
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
C760
C760 SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
12
12
C625
C625
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
TC5
TC5
ST220U2D5VBM-2GP
ST220U2D5VBM-2GP
12
C619
C619
SCD47U6D3V2KX-GP
SCD47U6D3V2KX-GP
1 2
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
3D3V_S0
12
12
C626
C626
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
D
1D05V_S0
12
C160
C160
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
C254
C254
C261
C261
1 2
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
C202
C202
1D25V_S0
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C662
C662
C714
C714 SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C751
C751 SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
20mil
C642
C642
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
RB751V-40-1-GP
RB751V-40-1-GP
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
1D25V_S0
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
12
C750
C750 SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1 2
C756
C756 SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1 2
D27
D27
21
C647
C647
C660
C660 SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
1 2
12
1D25V_S0
12
1 2
1D8V_S3
1D05V_S0
TC22
TC22
ST220U2D5VBM-2GP
ST220U2D5VBM-2GP
DY
DY
<Core Design>
<Core Design>
<Core Design>
3D3V_S01D05V_S0_D
R346
R346
12
10R2J-2-GP
10R2J-2-GP
C650
C650 SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
E
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CRESTLINE(4/6)-PWR
CRESTLINE(4/6)-PWR
CRESTLINE(4/6)-PWR
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
A
B
C
D
Date: Sheet of
Hawke-Intel
Hawke-Intel
Hawke-Intel
E
of
of
11
11
11
SA
SA
SA
55Tuesday, May 08, 2007
55Tuesday, May 08, 2007
55Tuesday, May 08, 2007
A
B
C
D
E
1D05V_S0
AT35 AT34 AH28 AC32 AC31 AK32
1 1
1D8V_S3
12
C267
C267
SC10U6D3V5KX-1GP
2 2
3 3
4 4
SC10U6D3V5KX-1GP
Place on the Edge
FOR VCC SM
12
12
TC19
TC19
ST330U2D5VDM-9GP
ST330U2D5VDM-9GP
C263
C263
DY
DY
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
Place CAP where LVDS and DDR2 taps
A
12
C259
C259
AH32 AH31 AH29
AU32 AU33 AU35
AV33 AW33 AW35
AY35
BA32
BA33
BA35
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BG32
BG33
BG35
BH32
BH34
BH35
BK32
BK33
BK34
BK35
AU30
AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AA31
AH20
AH21
AH23
AH24
AH26
AD31
AN14
U57F
U57F
VCC VCC VCC VCC VCC VCC
AJ31
VCC
AJ28
VCC VCC VCC VCC
AF32
VCC
R30
VCC
VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM
BF33
VCC_SM
BF34
VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM
BJ32
VCC_SM
BJ33
VCC_SM
BJ34
VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM
BL33
VCC_SM VCC_SM
R20
VCC_AXG
T14
VCC_AXG
W13
VCC_AXG
W14
VCC_AXG
Y12
VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG
AF21
VCC_AXG
AF26
VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG
AJ20
VCC_AXG VCC_AXG
CRESTLINE-GP-U-NF
CRESTLINE-GP-U-NF
6 OF 10
6 OF 10
VCC CORE
VCC CORE
POWER
POWER
VCC SM
VCC SM
VCC GFX
VCC GFX
VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF
VCC GFX NCTF
VCC GFX NCTF
VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF
VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF
VCC SM LF
VCC SM LF
B
T17 T18 T19 T21 T22 T23 T25 U15 U16 U17 U19 U20 U21 U23 U26 V16 V17 V19 V20 V21 V23 V24 Y15 Y16 Y17 Y19 Y20 Y21 Y23 Y24 Y26 Y28 Y29 AA16 AA17 AB16 AB19 AC16 AC17 AC19 AD15 AD16 AD17 AF16 AF19 AH15 AH16 AH17 AH19 AJ16 AJ17 AJ19 AK16 AK19 AL16 AL17 AL19 AL20 AL21 AL23 AM15 AM16 AM19 AM20 AM21 AM23 AP15 AP16 AP17 AP19 AP20 AP21 AP23 AP24 AR20 AR21 AR23 AR24 AR26 V26 V28 V29 Y31
AW45 BC39 BE39 BD17 BD4 AW8 AT6
VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7
1D05V_S0
TC21
ST220U6D3VDM-13GP
ST220U6D3VDM-13GP
370 mils from the Edge
TC21
DY
DY
Signal Group Supply Icc-max +1.05V_VCCP VCC 1.31A +1.05V_VCCP +1.05V_VCCP +1.05V_VCCP +1.05V_VCCP +1.05V_VCCP +1.8V_SUS +1.8V_SUS 0.2A +1.25V_RUN +1.25V_RUN
VCC_NCTF A
VTT 0.85A
VCC_PEG 1.2A
VCC_RXR_DMI 0.25A
VCC_ATX 84.15mA
VCC_SM 2.4A
VCC_SM_CK
VCCA_HPLL 0.05A
VCCA_MPLL 0.15A +1.25V_RUN +1.25V_RUN +1.25V_RUN +1.25V_RUN
VCCD_HPLL 0.25A +1.25V_RUN +1.25V_RUN +1.25V_RUN VCCA_PEG_PLL
12
12
12
C142
C142
C136
C136
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C129
C129
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
/VCCD_PEG_PLL
1D05V_S0
12
12
1
1
C194
C194
C280
C280
2
2
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD47U6D3V2KX-GP
SCD47U6D3V2KX-GP
C
SC10U6D3V5KX-1GP
12
SC10U6D3V5KX-1GP
C266
C266
1 2
(Non-AMT)
0.735AVCCA_SM
(667MHz)
AVCCA_SM_NCTF
0.015AVCCA_SM_CK
(667MHz)
0.2AVCCA_AXD AVCCA_AXD_NCTF
0.1A
0.35AVCCA_AXF+1.25V_RUN
0.1AVCCA_DMI+1.25V_RUN
0.06AVCCD_TVDAC+1.5V_RUN
0.005AVCCA_PEG_BG+3.3V_RUN
0.1AVCC_HV+3.3V_RUN
12
12
C172
C172
C270
C622
C622
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C270
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
Place on the Edge
FOR VCC AXM NCTF AND VCC AXM
12
C292
C292
C279
C279
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
FOR VCC CORE AND VCC NCTF
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
C104
C104
C180
C180
1 2
1 2
Coupling CAP
12
C209
C209
C229
C229
1 2
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
Coupling CAP Inside MCH cavity
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
C274
C274
1 2
C246
C246
1 2
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
D
7 OF 10
7 OF 10
U57G
U57G
AB33
VCC_NCTF
AB36
VCC_NCTF
AB37
VCC_NCTF
AC33
VCC_NCTF
AC35
VCC_NCTF
AC36
VCC_NCTF
AD35
VCC_NCTF
AD36
VCC_NCTF
AF33
VCC_NCTF
AF36
VCC_NCTF
AH33
VCC_NCTF
AH35
VCC_NCTF
AH36
VCC_NCTF
AH37
VCC_NCTF
AJ33
VCC_NCTF
AJ35
VCC_NCTF
AK33
VCC_NCTF
AK35
VCC_NCTF
AK36
VCC_NCTF
AK37
VCC_NCTF
AD33
VCC_NCTF
AJ36
VCC_NCTF
AM35
VCC_NCTF
AL33
VCC_NCTF
AL35
VCC_NCTF
AA33
VCC_NCTF
AA35
VCC_NCTF
AA36
VCC_NCTF
AP35
VCC_NCTF
AP36
VCC_NCTF
AR35
VCC_NCTF
AR36
VCC_NCTF
Y32
VCC_NCTF
Y33
VCC_NCTF
Y35
VCC_NCTF
Y36
VCC_NCTF
Y37
VCC_NCTF
T30
VCC_NCTF
T34
VCC_NCTF
T35
VCC_NCTF
U29
VCC_NCTF
U31
VCC_NCTF
U32
VCC_NCTF
U33
VCC_NCTF
U35
VCC_NCTF
U36
VCC_NCTF
V32
VCC_NCTF
V33
VCC_NCTF
V36
VCC_NCTF
V37
VCC_NCTF
AL24
VCC_AXM_NCTF
AL26
VCC_AXM_NCTF
AL28
VCC_AXM_NCTF
AM26
VCC_AXM_NCTF
AM28
VCC_AXM_NCTF
AM29
VCC_AXM_NCTF
AM31
VCC_AXM_NCTF
AM32
VCC_AXM_NCTF
AM33
VCC_AXM_NCTF
AP29
VCC_AXM_NCTF
AP31
VCC_AXM_NCTF
AP32
VCC_AXM_NCTF
AP33
VCC_AXM_NCTF
AL29
VCC_AXM_NCTF
AL31
VCC_AXM_NCTF
AL32
VCC_AXM_NCTF
AR31
VCC_AXM_NCTF
AR32
VCC_AXM_NCTF
AR33
VCC_AXM_NCTF
CRESTLINE-GP-U-NF
CRESTLINE-GP-U-NF
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
CRESTLINE(5/6)-PWR/GND
CRESTLINE(5/6)-PWR/GND
CRESTLINE(5/6)-PWR/GND
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
Date: Sheet of
VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF
VSS NCTF
VSS NCTF
VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF
VCC NCTF
VCC NCTF
POWER
POWER
VSS SCBVSS AXM
VSS SCBVSS AXM
VSS AXM NCTF
VSS AXM NCTF
T27 T37 U24 U28 V31 V35 AA19 AB17 AB35 AD19 AD37 AF17 AF35 AK17 AM17 AM24 AP26 AP28 AR15 AR19 AR28
A3
VSS_SCB
B2
VSS_SCB
C1
VSS_SCB
BL1
VSS_SCB
BL51
VSS_SCB
A51
VSS_SCB
AT33
VCC_AXM
AT31
VCC_AXM
AK29
VCC_AXM
AK24
VCC_AXM
AK23
VCC_AXM
AJ26
VCC_AXM
AJ23
VCC_AXM
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Hawke-Intel
Hawke-Intel
Hawke-Intel
12
12
12
E
TP107 TPAD28TP107 TPAD28 TP108 TPAD28TP108 TPAD28 TP75 TPAD28TP75 TPAD28 TP117 TPAD28TP117 TPAD28
1D05V_S0
of
of
SA
SA
SA
55Tuesday, May 08, 2007
55Tuesday, May 08, 2007
55Tuesday, May 08, 2007
A
U57I
U57I
A13
VSS
A15
VSS
A17
VSS
1 1
2 2
3 3
4 4
A
A24
VSS
AA21
VSS
AA24
VSS
AA29
VSS
AB20
VSS
AB23
VSS
AB26
VSS
AB28
VSS
AB31
VSS
AC10
VSS
AC13
VSS
AC3
VSS
AC39
VSS
AC43
VSS
AC47
VSS
AD1
VSS
AD21
VSS
AD26
VSS
AD29
VSS
AD3
VSS
AD41
VSS
AD45
VSS
AD49
VSS
AD5
VSS
AD50
VSS
AD8
VSS
AE10
VSS
AE14
VSS
AE6
VSS
AF20
VSS
AF23
VSS
AF24
VSS
AF31
VSS
AG2
VSS
AG38
VSS
AG43
VSS
AG47
VSS
AG50
VSS
AH3
VSS
AH40
VSS
AH41
VSS
AH7
VSS
AH9
VSS
AJ11
VSS
AJ13
VSS
AJ21
VSS
AJ24
VSS
AJ29
VSS
AJ32
VSS
AJ43
VSS
AJ45
VSS
AJ49
VSS
AK20
VSS
AK21
VSS
AK26
VSS
AK28
VSS
AK31
VSS
AK51
VSS
AL1
VSS
AM11
VSS
AM13
VSS
AM3
VSS
AM4
VSS
AM41
VSS
AM45
VSS
AN1
VSS
AN38
VSS
AN39
VSS
AN43
VSS
AN5
VSS
AN7
VSS
AP4
VSS
AP48
VSS
AP50
VSS
AR11
VSS
AR2
VSS
AR39
VSS
AR44
VSS
AR47
VSS
AR7
VSS
AT10
VSS
AT14
VSS
AT41
VSS
AT49
VSS
AU1
VSS
AU23
VSS
AU29
VSS
AU3
VSS
AU36
VSS
AU49
VSS
AU51
VSS
AV39
VSS
AV48
VSS
AW1
VSS
AW12
VSS
AW16
VSS
CRESTLINE-GP-U-NF
CRESTLINE-GP-U-NF
9 OF 10
9 OF 10
VSS
VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
B
AW24 AW29 AW32 AW5 AW7 AY10 AY24 AY37 AY42 AY43 AY45 AY47 AY50 B10 B20 B24 B29 B30 B35 B38 B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12 BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40 BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23 BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24 BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8 BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29 BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37 BL47 C12 C16 C19 C28 C29 C33 C36 C41
B
C
10 OF 10
10 OF 10
U57J
U57J
C46
VSS
C50
VSS
C7
VSS
D13
VSS
D24
VSS
D3
VSS
D32
VSS
D39
VSS
D45
VSS
D49
VSS
E10
VSS
E16
VSS
E24
VSS
E28
VSS
E32
VSS
E47
VSS
F19
VSS
F36
VSS
F4
VSS
F40
VSS
F50
VSS
G1
VSS
G13
VSS
G16
VSS
G19
VSS
G24
VSS
G28
VSS
G29
VSS
G33
VSS
G42
VSS
G45
VSS
G48
VSS
G8
VSS
H24
VSS
H28
VSS
H4
VSS
H45
VSS
J11
VSS
VSS
VSS
J16
VSS
J2
VSS
J24
VSS
J28
VSS
J33
VSS
J35
VSS
J39
VSS
K12
VSS
K47
VSS
K8
VSS
L1
VSS
L17
VSS
L20
VSS
L24
VSS
L28
VSS
L3
VSS
L33
VSS
L49
VSS
M28
VSS
M42
VSS
M46
VSS
M49
VSS
M5
VSS
M50
VSS
M9
VSS
N11
VSS
N14
VSS
N17
VSS
N29
VSS
N32
VSS
N36
VSS
N39
VSS
N44
VSS
N49
VSS
N7
VSS
P19
VSS
P2
VSS
P23
VSS
P3
VSS
P50
VSS
R49
VSS
T39
VSS
T43
VSS
T47
VSS
U41
VSS
U45
VSS
U50
VSS
V2
VSS
V3
VSS
CRESTLINE-GP-U-NF
CRESTLINE-GP-U-NF
C
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS
W11 W39 W43 W47 W5 W7 Y13 Y2 Y41 Y45 Y49 Y5 Y50 Y11 P29 T29 T31 T33 R28
AA32 AB32 AD32 AF28 AF29 AT27 AV25 H50
D
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
CRESTLINE(6/6)-PWR/GND
CRESTLINE(6/6)-PWR/GND
CRESTLINE(6/6)-PWR/GND
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
D
Date: Sheet of
Hawke-Intel
Hawke-Intel
Hawke-Intel
E
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
55Tuesday, May 08, 2007
55Tuesday, May 08, 2007
55Tuesday, May 08, 2007
of
of
13
13
13
E
SA
SA
SA
A
DDR_A_DQS#[0..7]9
DDR_A_D[0..63]9
DDR_A_DM[0..7]9
DDR_A_DQS[0..7]9
DDR_A_MA[0..14]9
C116
C116
C90
C90
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DDR_A_BS[0..2]9
C132
C132
C88
C88
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
12
C83
C83
C632
C632
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
12
12
1 1
2 2
Layout Note: Place near DM1
1D8V_S3
C94
C94
C78
C78
C155
C155
C91
C91
SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
12
Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS
DDR_VREF_S0
C628
C628
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
DY
DY
12
12
C610
C610
C97
C97
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
12
12
SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
C121
C121
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
12
C93
C93
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
12
change to 8P4R
3 3
DDR_VREF_S0
RN41
DDR_A_MA5 DDR_A_MA8 DDR_A_MA9 DDR_A_MA12
DDR_A_BS0 DDR_A_MA10 DDR_A_MA1 DDR_A_MA3
M_ODT1 DDR_CS1_DIMMA# DDR_A_CAS# DDR_A_WE#
4 4
RN41
1 2 3 4 5
SRN56J-5-GP
SRN56J-5-GP
RN40
RN40
1 2 3 4 5
SRN56J-5-GP
SRN56J-5-GP
RN39
RN39
1 2 3 4 5
SRN56J-5-GP
SRN56J-5-GP
A
8 7 6
8 7 6
8 7 6
RN15
RN15
1 2 3 4 5
SRN56J-5-GP
SRN56J-5-GP
RN13
RN13
1 2 3 4 5
SRN56J-5-GP
SRN56J-5-GP
RN6
RN6
1 2 3 4 5
SRN56J-5-GP
SRN56J-5-GP
RN18
RN18
1 2 3 4 5
SRN56J-5-GP
SRN56J-5-GP
DDR_A_MA14
8
DDR_A_MA11
7
DDR_A_MA7
6
DDR_A_MA6
DDR_A_MA4
8
DDR_A_MA2
7
DDR_A_MA0
6
DDR_A_BS1
DDR_CS0_DIMMA#
8
DDR_A_RAS#
7
M_ODT0
6
DDR_A_MA13
DDR_CKE1_DIMMA
8
DDR_CKE0_DIMMA
7
DDR_A_BS2
6
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C106
C106
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
12
C77
C77
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
C616
C616
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
B
Layout Note: Place these resistors closely DM1,all trace length Max=1.5"
B
DDR_VREF_S3
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C312
C312
M_ODT08 M_ODT18
12
C
DM2
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14
DDR_A_BS2 DDR_A_DM0 DDR_A_BS0
DDR_A_BS1 DDR_A_D0
DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63
DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7
DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7
M_ODT0 M_ODT1
DDR_VREF_S3
12
C313
C313 SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
C
DM2
102
A0
101
A1
100
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
105
A10/AP
90
A11
89
A12
116
A13
86
A14
84
A15
85
A16/BA2
107
BA0
106
BA1
5
DQ0
7
DQ1
17
DQ2
19
DQ3
4
DQ4
6
DQ5
14
DQ6
16
DQ7
23
DQ8
25
DQ9
35
DQ10
37
DQ11
20
DQ12
22
DQ13
36
DQ14
38
DQ15
43
DQ16
45
DQ17
55
DQ18
57
DQ19
44
DQ20
46
DQ21
56
DQ22
58
DQ23
61
DQ24
63
DQ25
73
DQ26
75
DQ27
62
DQ28
64
DQ29
74
DQ30
76
DQ31
123
DQ32
125
DQ33
135
DQ34
137
DQ35
124
DQ36
126
DQ37
134
DQ38
136
DQ39
141
DQ40
143
DQ41
151
DQ42
153
DQ43
140
DQ44
142
DQ45
152
DQ46
154
DQ47
157
DQ48
159
DQ49
173
DQ50
175
DQ51
158
DQ52
160
DQ53
174
DQ54
176
DQ55
179
DQ56
181
DQ57
189
DQ58
191
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
11
/DQS0
29
/DQS1
49
/DQS2
68
/DQS3
129
/DQS4
146
/DQS5
167
/DQS6
186
/DQS7
13
DQS0
31
DQS1
51
DQS2
70
DQS3
131
DQS4
148
DQS5
169
DQS6
188
DQS7
114
ODT0
119
ODT1
1
VREF
2
VSS
202
GND
DDR2-200P-11-GP-U
DDR2-200P-11-GP-U
62.10017.891
62.10017.891
CKE0 CKE1
VDDSPD
NC#50 NC#69 NC#83
NC#120
NC#163/TEST
/RAS
/WE
/CAS /CS0
/CS1
CK0
/CK0
CK1
/CK1 DM0
DM1 DM2 DM3 DM4 DM5 DM6 DM7
SDA
SCL
SA0 SA1
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
GND
108 109 113
110 115
79 80
30 32
164 166
10 26 52 67 130 147 170 185
195 197
199 198
200 50
69 83 120 163
81 82 87 88 95 96 103 104 111 112 117 118
3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196
201
D
DDR_A_RAS# DDR_A_WE# DDR_A_CAS#
DDR_CS0_DIMMA# DDR_CS1_DIMMA#
DDR_CKE0_DIMMA DDR_CKE1_DIMMA
M_CLK_DDR0 M_CLK_DDR#0
M_CLK_DDR1 M_CLK_DDR#1
DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7
ICH_SMBDATA ICH_SMBCLK
1D8V_S3
D
E
M_CLK_DDR0 M_CLK_DDR#0
DDR_A_RAS# 9
DDR_A_WE# 9
DDR_A_CAS# 9 DDR_CS0_DIMMA# 8
DDR_CS1_DIMMA# 8 DDR_CKE0_DIMMA 8
DDR_CKE1_DIMMA 8 M_CLK_DDR0 8
M_CLK_DDR#0 8 M_CLK_DDR1 8
M_CLK_DDR#1 8
ICH_SMBDATA 4,15,21,28,29 ICH_SMBCLK 4,15,21,28,29
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
PM_EXTTS#0 8
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev Custom
Custom
Custom Date: Sheet
Date: Sheet
Date: Sheet
DDRII-SODIMM SLOT1
DDRII-SODIMM SLOT1
DDRII-SODIMM SLOT1
12
put near connector
C57
C57
1 2
DUMMY-C2
DUMMY-C2 C56
C56
1 2
DUMMY-C2
DUMMY-C2
12
12
C37
C37
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Hawke-Intel
Hawke-Intel
Hawke-Intel
12
C245
C245 DUMMY-C2
DUMMY-C2
3D3V_S0
C35
C35 SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
DY
DY
14
14
14
E
C255
C255 DUMMY-C2
DUMMY-C2
of
of
of
SA
SA
SA
55Tuesday, May 08, 2007
55Tuesday, May 08, 2007
55Tuesday, May 08, 2007
5
DDR_B_DQS#[0..7]9
DDR_B_D[0..63]9
DDR_B_DM[0..7]9
DDR_B_DQS[0..7]9
C71
C71
SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
12
C79
C79
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
DDR_VREF_S0
DDR_B_MA[0..14]9 DDR_B_BS[0..2]9
C81
C81
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C75
C75
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
RN14
RN14
1 2 3 4 5
SRN56J-5-GP
SRN56J-5-GP
RN16
RN16
1 2 3 4 5
SRN56J-5-GP
SRN56J-5-GP
RN7
RN7
1 2 3 4 5
SRN56J-5-GP
SRN56J-5-GP
RN17
RN17
1 2 3 4 5
SRN56J-5-GP
SRN56J-5-GP
C108
C108
12
C105
C105
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
8 7 6
8 7 6
8 7 6
8 7 6
C85
C85
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C87
C87
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
DDR_B_MA5 DDR_B_MA8 DDR_B_MA9 DDR_B_MA12
DDR_B_MA11 DDR_B_MA7 DDR_B_MA6
DDR_CS2_DIMMB# DDR_B_BS1 M_ODT2 DDR_B_MA13
DDR_CKE3_DIMMB DDR_B_BS2 DDR_CKE2_DIMMB
D D
C C
B B
A A
Layout Note: Place near DM2
1D8V_S3
C145
C145
C147
12
C117
C117
12
5
SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
12
C80
C80
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
RN11
RN11
1 2 3 4 5
SRN56J-5-GP
SRN56J-5-GP
RN12
RN12
1 2 3 4 5
SRN56J-5-GP
SRN56J-5-GP
RN5
RN5
1 2 3 4 5
SRN56J-5-GP
SRN56J-5-GP
C147
SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
C99
C99
12
8 7 6
8 7 6
8 7 6
C72
C72
SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
12
Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS
DDR_VREF_S0
C122
C122
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
DY
DY
DDR_B_MA3 DDR_B_MA1 DDR_B_MA10 DDR_B_BS0
DDR_B_RAS# DDR_B_MA14 DDR_B_MA0 DDR_B_MA2 DDR_B_MA4
DDR_B_WE# DDR_B_CAS# DDR_CS3_DIMMB# M_ODT3
4
C92
C92
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SC10U6D3V5KX-1GP
SC10U6D3V5KX-1GP
12
C98
C98
C107
C107
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
12
Layout Note: Place these resistors closely DM2,all trace length Max=1.5"
DDR_VREF_S3
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
4
C294
C294
3
DM1
DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14
DDR_B_BS2 DDR_B_BS0
DDR_B_BS1
DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63
DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7
DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7
12
M_ODT2 M_ODT3
DDR_VREF_S3
12
C293
C293 SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
M_ODT28 M_ODT38
3
DM1
102
A0
101
A1
100
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
105
A10/AP
90
A11
89
A12
116
A13
86
A14
84
A15
85
A16/BA2
107
BA0
106
BA1
5
DQ0
7
DQ1
17
DQ2
19
DQ3
4
DQ4
6
DQ5
14
DQ6
16
DQ7
23
DQ8
25
DQ9
35
DQ10
37
DQ11
20
DQ12
22
DQ13
36
DQ14
38
DQ15
43
DQ16
45
DQ17
55
DQ18
57
DQ19
44
DQ20
46
DQ21
56
DQ22
58
DQ23
61
DQ24
63
DQ25
73
DQ26
75
DQ27
62
DQ28
64
DQ29
74
DQ30
76
DQ31
123
DQ32
125
DQ33
135
DQ34
137
DQ35
124
DQ36
126
DQ37
134
DQ38
136
DQ39
141
DQ40
143
DQ41
151
DQ42
153
DQ43
140
DQ44
142
DQ45
152
DQ46
154
DQ47
157
DQ48
159
DQ49
173
DQ50
175
DQ51
158
DQ52
160
DQ53
174
DQ54
176
DQ55
179
DQ56
181
DQ57
189
DQ58
191
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
11
DQS0#
29
DQS1#
49
DQS2#
68
DQS3#
129
DQS4#
146
DQS5#
167
DQS6#
186
DQS7#
13
DQS0
31
DQS1
51
DQS2
70
DQS3
131
DQS4
148
DQS5
169
DQS6
188
DQS7
114
OTD0
119
OTD1
1
VREF
2
VSS
202
GND
MH1
MH1
DDR2-200P-25-GP-U1
DDR2-200P-25-GP-U1
62.10017.B51
62.10017.B51
RAS# CAS#
CS0# CS1#
CKE0 CKE1
CK0#
CK1#
VDDSPD
NC#50 NC#69 NC#83
NC#120
NC#163/TEST
WE#
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
GND MH2
2
M_CLK_DDR2 M_CLK_DDR#2
DDR_B_RAS#
108
DDR_B_WE#
109
DDR_B_CAS#
113
DDR_CS2_DIMMB#
110
DDR_CS3_DIMMB#
115
DDR_CKE2_DIMMB
79
DDR_CKE3_DIMMB
80
M_CLK_DDR2
30
CK0
CK1
SDA SCL
SA0 SA1
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
2
32 164
166 10
26 52 67 130 147 170 185
195 197
199 198
200 50
69 83 120 163
81 82 87 88 95 96 103 104 111 112 117 118
3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196
201 MH2
M_CLK_DDR#2 M_CLK_DDR3
M_CLK_DDR#3 DDR_B_DM0
DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7
ICH_SMBDATA ICH_SMBCLK
1 2
R46 10KR2J-3-GPR46 10KR2J-3-GP
1D8V_S3
DDR_B_RAS# 9
DDR_B_WE# 9
DDR_B_CAS# 9 DDR_CS2_DIMMB# 8
DDR_CS3_DIMMB# 8 DDR_CKE2_DIMMB 8
DDR_CKE3_DIMMB 8 M_CLK_DDR2 8
M_CLK_DDR#2 8 M_CLK_DDR3 8
M_CLK_DDR#3 8
ICH_SMBDATA 4,14,21,28,29
ICH_SMBCLK 4,14,21,28,29
3D3V_S0
PM_EXTTS#1 8
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev Custom
Custom
Custom Date: Sheet
Date: Sheet
Date: Sheet
DDRII-SODIMM SLOT2
DDRII-SODIMM SLOT2
DDRII-SODIMM SLOT2
1
12
C707
C707 DUMMY-C2
DUMMY-C2
put near connector
C60
C60
1 2
DUMMY-C2
DUMMY-C2 C55
C55
1 2
DUMMY-C2
DUMMY-C2
3D3V_S0
12
12
C38
C38
C46
C46
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
DY
DY
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Hawke-Intel
Hawke-Intel
Hawke-Intel
15
15
15
1
12
of
of
of
C708
C708 DUMMY-C2
DUMMY-C2
SA
SA
SA
55Tuesday, May 08, 2007
55Tuesday, May 08, 2007
55Tuesday, May 08, 2007
A
HDMI I/F & CONNECTOR
R345 0R3-0-U-GPR345 0R3-0-U-GP
HDMI_TXD#149 HDMI_TXD#049
1 1
HDMI_TXD149
HDMI_TXD#249
2 2
HDMI_TXD249
HDMI_TXD#1
HDMI_TXD1
HDMI_TXD#2
HDMI_TXD2
1 2
1
2
1 2
R347 0R3-0-U-GPR347 0R3-0-U-GP
R350 0R3-0-U-GPR350 0R3-0-U-GP
1 2
1
2
1 2
R352 0R3-0-U-GPR352 0R3-0-U-GP
HDMI_TXD#1_C
L30
L30
ACM2012H-900-GP
ACM2012H-900-GP
DY
DY
3 4
HDMI_TXD1_C
HDMI_TXD#2_C
L31
L31
ACM2012H-900-GP
ACM2012H-900-GP
DY
DY
3 4
HDMI_TXD2_C
HDMI_TXD049
HDMI_TX#C49
HDMI_TXC49
B
R339 0R3-0-U-GPR339 0R3-0-U-GP
HDMI_TXD#0
HDMI_TXD0
HDMI_TX#C
1 2
1
2
1 2
R344 0R3-0-U-GPR344 0R3-0-U-GP
R336 0R3-0-U-GPR336 0R3-0-U-GP
1 2
1
2
1 2
R337 0R3-0-U-GPR337 0R3-0-U-GP
HDMI_TXD#0_C
L29
L29
ACM2012H-900-GP
ACM2012H-900-GP
DY
DY
3 4
HDMI_TXD0_C
HDMI_TX#C_C
L28
L28
ACM2012H-900-GP
ACM2012H-900-GP
DY
DY
3 4
HDMI_TXC_CHDMI_TXC
C
5V_S0 3D3V_S0
12
R117
R117 10KR2J-3-GP
10KR2J-3-GP
DY
DY
U8
U8
1
HDMI_SDATA_C HDMI_SDATA
2 3 4
2N7002SPT
2N7002SPT
DY
DY
HDMI CONN
HDMI1
HDMI1
HDMI_TXD#0_C HDMI_TXD0_C
HDMI_TXD#1_C HDMI_TXD1_C
HDMI_TXD#2_C HDMI_TXD2_C
HDMI_TX#C_C HDMI_TXC_C
9
TMDS_DATA0-
7
TMDS_DATA0+
6
TMDS_DATA1-
4
TMDS_DATA1+
3
TMDS_DATA2-
1
TMDS_DATA2+
12
TMDS_CLOCK-
10
TMDS_CLOCK+
8
TMDS_DATA0_SHIELD
5
TMDS_DATA1_SHIELD
2
TMDS_DATA2_SHIELD
11
TMDS_CLOCK_SHIELD
SKT-USB-169-GP
SKT-USB-169-GP
62.10027.661
62.10027.661
1
23
4
6 5
HOT_PLUG_DETECT
DDC/CEC_GROUNG
RN23
RN23
SRN2K2J-1-GP
SRN2K2J-1-GP
DY
DY
HDMI_SCLK_CHDMI_SCLK
+5V_POWER
SDA
SCL
CEC
RESERVED#14
GND GND GND GND
D
18
16 15 13 14 19 17
20 21 22 23
+5V_HDMI
HDMI_SDATA_C HDMI_SCLK_C HDMI_CEC_R
R334 0R2J-2-GP
R334 0R2J-2-GP
HDMI_CNC HDMI_DP_C2
D12
D12
2 1
RB751V-40-1-GP
RB751V-40-1-GP
1
23
RN20
RN20 SRN1KJ-7-GP
SRN1KJ-7-GP
4
R111 0R2J-2-GPR111 0R2J-2-GP R112 0R2J-2-GPR112 0R2J-2-GP
DY
DY
TP68 TPAD28TP68 TPAD28
1 2
12
R331
R331
10KR2J-3-GP
10KR2J-3-GP
12 12
5V_S0
HDMI_SDATA HDMI_SCLK
HDMI_CEC 50
HDMI_HDP
R333
R333 100KR2J-1-GP
100KR2J-1-GP
1 2
E
HDMI_SDATA 50 HDMI_SCLK 50
HDMI_HDP 50
3 3
4 4
A
B
C
D
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
HDMI
HDMI
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
Date: Sheet
HDMI
Hawke-Intel SA
Hawke-Intel SA
Hawke-Intel SA
16 55Tuesday, May 08, 2007
16 55Tuesday, May 08, 2007
16 55Tuesday, May 08, 2007
of
of
E
of
A
CRT I/F & CONNECTOR
1 1
M_RED50
M_GREEN50
M_BLUE50
R50
R50
12
12
12
C40
R44
R44
C40
SC10P50V2JN-4GP
SC10P50V2JN-4GP
DY
DY
150R2F-1-GP
150R2F-1-GP
R45
R45
150R2F-1-GP
150R2F-1-GP
150R2F-1-GP
150R2F-1-GP
12
12
C33
C33
C27
C27
SC10P50V2JN-4GP
SC10P50V2JN-4GP
DY
DY
B
L4 BLM18BA100SN1DGPL4 BLM18BA100SN1DGP
1 2
L2 BLM18BA100SN1DGPL2 BLM18BA100SN1DGP
1 2
L1 BLM18BA100SN1DGPL1 BLM18BA100SN1DGP
1 2
12
SC10P50V2JN-4GP
SC10P50V2JN-4GP
DY
DY
C41
C41
C
5V_CRT_S0 5V_S0
12
C565
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
12
12
12
SC10P50V2JN-4GP
SC10P50V2JN-4GP
C30
C30
C23
C23
SC10P50V2JN-4GP
SC10P50V2JN-4GP
SC10P50V2JN-4GP
SC10P50V2JN-4GP
C565
CRT_R
CRT_G DDC_DATA_CON CRT_B
10
D
D24
D24
2 1
CH551H-30PT-GP
CH551H-30PT-GP
CRT1
CRT1
17
6 1
11
7 2
12 8 3
13 9 4
14 5
15
16
VIDEO-15-47-GP-U
VIDEO-15-47-GP-U
20.20392.015
20.20392.015
JVGA_HS JVGA_VS DDC_CLK_CON
DY
12
C570
SC22P50V2JN-4GPDYC570
SC22P50V2JN-4GP
12
DY
C48
C48
SC22P50V2JN-4GP
SC22P50V2JN-4GP
C572
SC22P50V2JN-4GPDYC572
SC22P50V2JN-4GP
5V_CRT_S0
1
23
4
12
12
E
RN4
RN4
SRN2K2J-1-GP
SRN2K2J-1-GP
DDC_DATA_CON 50 DDC_CLK_CON 50
C20
C20 SC22P50V2JN-4GP
SC22P50V2JN-4GP
2 2
3 3
Hsync & Vsync level shift
VGA_HSYNC50
VGA_VSYNC50
Layout Note: Pi-filter & 150 Ohm pull-down resistors should be as close as to CRT CONN. RGB will hit 75 Ohm first, pi-filter, then CRT CONN.
5V_S0
12
C584
C584 SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
14
1
U52A
U52A
HSYNC_5
VSYNC_5
RN37
RN37
1 2 3
SRN33J-5-GP-U
SRN33J-5-GP-U
JVGA_HS
4
JVGA_VS
14
4
U52B
U52B
5 6
TSAHCT125PW-GP
TSAHCT125PW-GP
7
2 3
TSAHCT125PW-GP
TSAHCT125PW-GP
7
DDC_DATA_CON
DDC_CLK_CON
CRT_R
CRT_G
CRT_B
D8
D8
3
DY
DY
BAV99-7-F-GP
BAV99-7-F-GP
D4
D4
3
DY
DY
BAV99-7-F-GP
BAV99-7-F-GP
D7
D7
3
DY
DY
BAV99-7-F-GP
BAV99-7-F-GP
D6
D6
3
DY
DY
BAV99-7-F-GP
BAV99-7-F-GP
D5
D5
3
DY
DY
BAV99-7-F-GP
BAV99-7-F-GP
5V_CRT_S0
2
1
2
1
2
1
2
1
2
1
4 4
A
B
C
D
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CRT Connector
CRT Connector
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
Date: Sheet
CRT Connector
Hawke-Intel SA
Hawke-Intel SA
Hawke-Intel SA
17 55Tuesday, May 08, 2007
17 55Tuesday, May 08, 2007
17 55Tuesday, May 08, 2007
of
of
E
of
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