Page 1
A
COMPAL CONFIDENTIAL
B
C
D
E
MODEL NAME :
PCB NO :
1 1
BOM P/N :
LA-4596P (DA60000B710)
11
KML50
Half Penny Bridge 15.4
2 2
Compal Confidential
Schematic Document
Cantiga + ICH9
2009 / 01 / 14
3 3
4 4
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
http://laptop-motherboard-schematic.blogspot.com/
MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Rev:1.0(A00)
2007/1/15 2008/1/15
C
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
D
Date: Sheet
Compal Electronics, Inc.
Cover Sheet
LA-4592P
E
143Thursday, February 19, 2009
0.2
of
Page 2
A
B
C
D
E
Compal confidential
Half Penny Bridge 15.4
File Name : LA-4596P
ZZZ1
PCB
1 1
+CRT_VCC
CRT
LVDS Panel Interface
+LCDVDD
+3VS
B+
2 2
P.16
P.16
CardBus Controller
O2MICRO OZ888
+1.8VS_CB
+3VS_PHY
1394
EMC1402-2-ACZL-TR
+3VS
Fan conn
+5VS
P.29
Media Card
+3VS_CR
P.4
P.4
DMI X4
PCI-E BUS
Thermal Sensor
10/100/1000 LAN
REALTEK
3 3
RTL8111C-GR
+LAN_IO
P.21
(WLAN)
+1.5VS
+3VS
P.23 P.25
Mini-Card-2
Express Card
+1.5VS
+3VS
RJ45/11 CONN
Penryn -4MB (Socket P)
uFCPGA-478 CPU
+CPU_CORE
+VCCP
+1.5VS
H_A#(3..35)
H_D#(0..63)
P.4,5,6
FSB
1066/800MHz 1.05V
Intel Cantiga MCH
+3VS_DAC_CRT
+3VS_DAC_BG
+1.05VS_DPLLA
+1.05VS_DPLLB
+VCCP
+1.8V_TXLVDS
1329pin BGA
P.7,8,9,10,11,12
Intel ICH9-M
+RTCVCC
+1.5VS
+VCCP
+3VALW
676pin BGA
P.17,18,19,20
LPC BUS
LPC BUS
C-Link
USB2.0
Azalia
SATA 0
SATA 1
TPM
SLB 9635
+3VALW
DDR2 667/800MHz 1.8V
Dual Channel
P.27
DDR2-SO-DIMM X2
BANK 0, 1, 2, 3
+1.8V
+0.9VS
P.13,14
USB conn x 4
+5VALW
FingerPrinter
+3VS
Felica Conn
+5VS
BT Conn
Camera
+5VS +3VS
Express Card
+3VS +1.5VS
Mini-Card-2
+1.5VS +3VS
P.28
P.28
P.28
P.28
P.25
P.23
P.28
Digital Mic
CK505
SM IC -72
Clock Generator
CS9LPRS387BKLFT
+1.05VS_CK505
+3VS_CK505
P.28
P.15
Mini-Card-1
+1.5VS
+3VS
Power On/Off CKT.
+3VALW
4 4
DC/DC Interface CKT.
+3VS
+5VS
Power Circuit DC/DC
P.27
P.30
P.32~P.39
A
RTC CKT.
+RTCVCC
P.18
P.23
Touch Pad CONN. Int.KBD
+5VS
B
http://laptop-motherboard-schematic.blogspot.com/
ENE KB926
+3VALW +EC_AVCC
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
P.26
BIOS(System/EC)
+3VALW
2007/1/15 2008/1/15
C
P.26P.27P.27
Compal Secret Data
Deciphered Date
Audio CODEC
92HD81
+3VS +5VS
P.24
SATA HDD Connector
+5VS
CDROM Conn.
+5VS
D
Audio Jack
P.22
P.22
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
Block diagram
LA-4592P
P.24
of
243Thursday, February 19, 2009
E
0.2
Page 3
Voltage Rails
O MEANS ON X MEANS OFF
A
Symbol Note :
: means Digital Ground
: means Analog Ground
@ : means just reserve , no build
CONN@ : means ME CONN compont.
TPM@:TPM compont
DESTINATION
SOURCE
KB926
KB926
Cantiga
INVERTER BATT EEPROM
X
VV
X
XX
X
X
XX
SATA
Lane 0
Lane 1
Lane 4
Lane 5 NA
SERIAL SENSOR
THERMAL
(CPU)
XX
V
X
X
XX
DESTINATION
HDD
ODD
NA
X
X
MINI CARD
XX
X
SODIMM CLK CHIP
X
VVV
XX
X
LCD
X
X
V
State
power
plane
+B
+5VALW
+3VALW
+5VS
+3VS
+1.5VS+1.8V
+0.9V
+VCCP
+CPU_CORE
+1.8VS
PCI EXPRESS
S0
S1
S3
S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery
don't exist
1 1
USB PORT#
O
O
O
O
O
X
0
1
2
3
ICH9-M
4
5
O
O
O
O
X
O
XX
X
XX X
DESTINATION
JUSBP1
CAMERA
JUSBP3
Felica
Blue Tooth
Finger Printer
Top
OO
OO
X
X
Lane 1
Lane 2
Lane 3
Lane 4
Lane 5
Lane 6
SMBUS Control Table
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
SMB_CK_CLK1
SMB_CK_DAT1 ICH9
LCD_CLK
LCD_DAT
MINI CARD-1 WWAN
GLAN RTL8111DL
MINI CARD-2 WLAN
EXPRESS CARD
CARD READER OZ888
NA
6
7
8
9
10
11
I2C / SMBUS ADDRESSING
DEVICE
DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)
HEX
A0
D2
JMINI2-WLAN
Express card
JUSBP3
JMINI1-WWAN
JUSBP4
NA
ADDRESS
1 0 1 0 0 0 0 0
1 0 1 0 0 1 0 0A4
1 1 0 1 0 0 1 0
Bottom
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
http://laptop-motherboard-schematic.blogspot.com/
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
2005/03/10 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
Notes List
LA-4592P
of
343Thursday, February 19, 2009
0.2
Page 4
5
D D
H_A#[3..16]7
H_ADSTB#07
H_REQ#07
H_REQ#17
H_REQ#27
H_REQ#37
H_REQ#47
C C
B B
A A
H_A#[17..35]7
H_ADSTB#17
H_A20M#18
H_FERR#18
H_IGNNE#18
H_STPCLK#18
H_INTR18
H_NMI18
H_SMI#18
+VCCP
B
H_PROCHOT# OCP#
H_IERR#
E
3 1
Q2
@
MMBT3904_SOT23
+VCCP
12
@
R17
56_0402_5%
2
C
R18
56_0402_5%
1 2
5
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1
H_A20M#
H_FERR#
H_IGNNE#
H_STPCLK#
H_INTR
H_NMI
H_SMI#
CONN@
JCPU1A
J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1
K3
H2
K2
J3
L1
Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1
A6
A5
C4
D5
C6
B4
A3
M4
N5
T2
V3
B2
D2
D22
D3
F6
Penryn
OCP# 19
A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#
A20M#
FERR#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#
RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]
ADDR GROUP_0
ADDR GROUP_1
THERMAL
ICH
THERMTRIP#
RESERVED
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
CONTROL
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HIT#
HITM#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TRST#
DBR#
XDP/ITP SIGNALS
PROCHOT#
THERMDA
THERMDC
H CLK
BCLK[0]
BCLK[1]
TCK
TDO
TMS
H1
E2
G5
H5
F21
E1
F1
D20
B3
H4
C1
F3
F4
G3
G2
G6
E4
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
TDI
AB3
AB5
AB6
C20
D21
A24
B25
C7
A22
A21
4
H_ADS#
H_BNR#
H_BPRI#
H_DEFER#
H_DRDY#
H_DBSY#
H_BR0#
H_IERR#
H_INIT#
H_LOCK#
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
H_HIT#
H_HITM#
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#
H_PROCHOT#
H_THERMDC_R
H_THERMTRIP#
CLK_CPU_BCLK
CLK_CPU_BCLK#
4
H_ADS# 7
H_BNR# 7
H_BPRI# 7
H_DEFER# 7
H_DRDY# 7
H_DBSY# 7
H_BR0# 7
H_INIT# 18
H_LOCK# 7
H_RESET# 7
H_RS#0 7
H_RS#1 7
H_RS#2 7
H_TRDY# 7
H_HIT# 7
H_HITM# 7
T84
XDP_DBRESET# 19
R146 68_0402_5%
R57 100_0402_5%
R53 100_0402_5%
H_THERMTRIP# 7,18
CLK_CPU_BCLK 15
CLK_CPU_BCLK# 15
12
1 2
1 2
H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil
http://laptop-motherboard-schematic.blogspot.com/
+VCCP
H_THERMDAH_THERMDA_R
H_THERMDC
3
C5
1 2
+3VS
+3VS
1
C13
2
0.1U_0402_16V4Z
2200P_0402_50V7K
R16
1 2
10K_0402_5%
2
H_THERMDA
H_THERMDC
L_THERM#
FAN Control circuit
C94
2
EN_DFAN1
+3VS
12
1
2
EN_DFAN126
FAN_SPEED126
4.7P_0402_50V8C
For FAN Test Fail
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
1
XDP_TDI
XDP_TMS
XDP_TRST#
XDP_TCK
R5 54.9_0402_1%
1 2
R4 54.9_0402_1%
1 2
R11 54.9_0402_1%
1 2
R35 54.9_0402_1%
1 2
This shall place near CPU
Thermal Sensor EMC1402-1-ACZL-TR
1
2
3
EMC1402-2-ACZL-TR MSOP 8P
Address:100_1100
R61
2.2K_0402_5%
2
3
1
U2
VDD
SCLK
D+
SDATA
ALERT#
DTHERM#4GND
C76
10U_1206_16V4Z~N
C88
1000P_0402_50V7K~N
FAN1_POWER
D61
PJSOT24C_SOT23-3
@
Title
Size Document Number Rev
Custom
Date: Sheet
EC_SMB_CK2
8
EC_SMB_DA2
7
6
5
12
+5VS
12
40mil
C77 10U_1206_16V4Z~N
U3
1
VEN
2
VIN
3
VO
4
VSET
RT9027BPS SO 8P
JFAN1
1
1
2
2
3
3
4
GND
5
GND
ACES_85205-03001
conn@
FAN1
Compal Electronics, Inc.
Penryn(1/3)-AGTL+/ITP-XDP
LA-4592P
1 2
GND
GND
GND
GND
1
8
7
6
5
EC_SMB_CK2 16,26
EC_SMB_DA2 16,26
+VCCP
443Thursday, February 19, 2009
0.2
of
Page 5
5
4
3
2
1
H_D#[0..15]7
D D
H_DSTBN#07
H_DSTBP#07
H_DINV#07
H_D#[16..31]7
C C
R52 1K_0402_5%@
R22 1K_0402_5%@
H_DSTBN#17
H_DSTBP#17
H_DINV#17
1 2
1 2
CPU_BSEL015
CPU_BSEL115
CPU_BSEL215
T2
T3
T4
T5
T6
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1
+V_CPU_GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
layout note: Rout H_DPRSTP# from ICH9 to IMVP6 then to GMCH & CPU
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs
CPU_BSEL CPU_ BSEL2 CPU_BSEL1
B B
166
200
01
0
1
266000
CONN@
JCPU1B
E22
D[0]#
F24
D[1]#
E26
D[2]#
G22
D[3]#
F23
D[4]#
G25
D[5]#
E25
D[6]#
E23
D[7]#
K24
D[8]#
G24
D[9]#
J24
D[10]#
J23
D[11]#
H22
D[12]#
F26
D[13]#
K22
D[14]#
H23
D[15]#
J26
DSTBN[0]#
H26
DSTBP[0]#
H25
DINV[0]#
N22
D[16]#
K25
D[17]#
P26
D[18]#
R23
D[19]#
L23
D[20]#
M24
D[21]#
L22
D[22]#
M23
D[23]#
P25
D[24]#
P23
D[25]#
P22
D[26]#
T24
D[27]#
R24
D[28]#
L25
D[29]#
T25
D[30]#
N25
D[31]#
L26
DSTBN[1]#
M26
DSTBP[1]#
N24
DINV[1]#
AD26
GTLREF
C23
TEST1
D25
TEST2
C24
TEST3
AF26
TEST4
AF1
TEST5
A26
TEST6
C3
TEST7
B22
BSEL[0]
B23
BSEL[1]
C21
BSEL[2]
Penryn
CPU_BSEL0
DATA GRP 0
MISC
DATA GRP 1
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
DATA GRP 2DATA GRP 3
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
COMP[0]
COMP[1]
COMP[2]
COMP[3]
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
R26
U26
AA1
Y1
E5
B5
D24
D6
D7
AE6
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3
COMP0
COMP1
COMP2
COMP3
H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#
H_D#32
Y22
1
0
+VCCP
12
R27
+V_CPU_GTLREF
1K_0402_1%
12
R29
2K_0402_1%
H_D#[32..47] 7
H_DSTBN#2 7
H_DSTBP#2 7
H_DINV#2 7
H_D#[48..63] 7
H_DSTBN#3 7
H_DSTBP#3 7
H_DINV#3 7
H_DPRSTP# 7,18,39
H_DPSLP# 18
H_DPWR# 7
H_PWRGOOD 18
H_CPUSLP# 7
H_PSI# 39
R24
12
27.4_0402_1%
R25
12
54.9_0402_1%
27.4_0402_1%
R23
12
54.9_0402_1%
Resistor placed within
0.5" of CPU pin.Trace
should be at least 25
mils away from any other
toggling signal.
COMP[0,2] trace width is
18 mils. COMP[1,3] trace
width is 4
For 6 layer
Z=27.4 ohm
VCCSENSE, VSSSENSE/ 14mils (MS),
16mils (SL) width, 7mils space, 25mils
space to other signals Mismatch =25mils.
+CPU_CORE +CPU_CORE
R26
12
CONN@
JCPU1C
A7
VCC[001]
VCC[068]
VCC[002]
VCC[069]
VCC[003]
VCC[070]
VCC[004]
VCC[071]
VCC[005]
VCC[072]
VCC[006]
VCC[073]
VCC[007]
VCC[074]
VCC[008]
VCC[075]
VCC[009]
VCC[076]
VCC[010]
VCC[077]
VCC[011]
VCC[078]
VCC[012]
VCC[079]
VCC[013]
VCC[080]
VCC[014]
VCC[081]
VCC[015]
VCC[082]
VCC[016]
VCC[083]
VCC[017]
VCC[084]
VCC[018]
VCC[085]
VCC[019]
VCC[086]
VCC[020]
VCC[087]
VCC[021]
VCC[088]
VCC[022]
VCC[089]
VCC[023]
VCC[090]
VCC[024]
VCC[091]
VCC[025]
VCC[092]
VCC[026]
VCC[093]
VCC[027]
VCC[094]
VCC[028]
VCC[095]
VCC[029]
VCC[096]
VCC[030]
VCC[097]
VCC[031]
VCC[098]
VCC[032]
VCC[099]
VCC[033]
VCC[100]
VCC[034]
VCC[035]
VCCP[01]
VCC[036]
VCCP[02]
VCC[037]
VCCP[03]
VCC[038]
VCCP[04]
VCC[039]
VCCP[05]
VCC[040]
VCCP[06]
VCC[041]
VCCP[07]
VCC[042]
VCCP[08]
VCC[043]
VCCP[09]
VCC[044]
VCCP[10]
VCC[045]
VCCP[11]
VCC[046]
VCCP[12]
VCC[047]
VCCP[13]
VCC[048]
VCCP[14]
VCC[049]
VCCP[15]
VCC[050]
VCCP[16]
VCC[051]
VCC[052]
VCCA[01]
VCC[053]
VCCA[02]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCCSENSE
VCC[065]
VCC[066]
VCC[067]
VSSSENSE
Penryn
For 8 layer condition
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AC10
AB10
AB12
AB14
AB15
AB17
AB18
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AB9
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
B26
C26
AD6
AF5
AE5
AF4
AE3
AF3
AE2
VCCSENSE
AF7
VSSSENSE
AE7
.
Length match within 25 mils.
CPU_VID0 39
CPU_VID1 39
CPU_VID2 39
CPU_VID3 39
CPU_VID4 39
CPU_VID5 39
CPU_VID6 39
VCCSENSE 39
No stuff 27.4 pull down near IMVP for testing
VSSSENSE 39
220U_D2_4VY_R15M
+VCCP
C10
10U_0805_6.3V6M
1
+
2
1
C12
2
+1.5VS
1
C11
2
0.01U_0402_16V7K
Near pin B26
The trace width/space/other is
20/7/25.
+CPU_CORE
R28 100_0402_1%
1 2
R30 100_0402_1%
1 2
VCCSENSE
VSSSENSE
Close to CPU pin AD26
within 500mils.
A A
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
http://laptop-motherboard-schematic.blogspot.com/
MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
2
Close to CPU pin
within 500mils.
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
Penryn(2/3)-AGTL+/ITP-XDP
LA-4592P
1
of
543Thursday, February 19, 2009
0.2
Page 6
5
High Frequence Decoupling
10uF 0805 X5R -> 85 degree.
Place these caps inside
the CPU socket cavity.
D D
C C
B B
CONN@
JCPU1D
A4
VSS[001]
A8
VSS[002]
A11
VSS[003]
A14
VSS[004]
A16
VSS[005]
A19
VSS[006]
A23
VSS[007]
AF2
VSS[008]
B6
VSS[009]
B8
VSS[010]
B11
VSS[011]
B13
VSS[012]
B16
VSS[013]
B19
VSS[014]
B21
VSS[015]
B24
VSS[016]
C5
VSS[017]
C8
VSS[018]
C11
VSS[019]
C14
VSS[020]
C16
VSS[021]
C19
VSS[022]
C2
VSS[023]
C22
VSS[024]
C25
VSS[025]
D1
VSS[026]
D4
VSS[027]
D8
VSS[028]
D11
VSS[029]
D13
VSS[030]
D16
VSS[031]
D19
VSS[032]
D23
VSS[033]
D26
VSS[034]
E3
VSS[035]
E6
VSS[036]
E8
VSS[037]
E11
VSS[038]
E14
VSS[039]
E16
VSS[040]
E19
VSS[041]
E21
VSS[042]
E24
VSS[043]
F5
VSS[044]
F8
VSS[045]
F11
VSS[046]
F13
VSS[047]
F16
VSS[048]
F19
VSS[049]
F2
VSS[050]
F22
VSS[051]
F25
VSS[052]
G4
VSS[053]
G1
VSS[054]
G23
VSS[055]
G26
VSS[056]
H3
VSS[057]
H6
VSS[058]
H21
VSS[059]
H24
VSS[060]
J2
VSS[061]
J5
VSS[062]
J22
VSS[063]
J25
VSS[064]
K1
VSS[065]
K4
VSS[066]
K23
VSS[067]
K26
VSS[068]
L3
VSS[069]
L6
VSS[070]
L21
VSS[071]
L24
VSS[072]
M2
VSS[073]
M5
VSS[074]
M22
VSS[075]
M25
VSS[076]
N1
VSS[077]
N4
VSS[078]
N23
VSS[079]
N26
VSS[080]
VSS[081]P3VSS[162]
Penryn
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[163]
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
.
( Left side on Top ).
Place these caps inside
the CPU socket cavity.
( Right side on Top side).
Place these caps inside
the CPU socket cavity.
( Left side on Bottom ).
Place these caps inside
the CPU socket cavity.
( Right side on Bottom ).
Place these caps inside
the CPU socket.
+VCCP
4
+CPU_CORE
1
2
+CPU_CORE
1
2
+CPU_CORE
1
2
+CPU_CORE
1
2
+CPU_CORE
1
C196
+
2
C202
10U_0805_6.3V6M
C190
10U_0805_6.3V6M
C501
10U_0805_6.3V6M
C502
10U_0805_6.3V6M
330U_D2E_2.5VM_R9
C198
1
2
+
330U_D2E_2.5VM_R9
1
C204
10U_0805_6.3V6M
2
1
C197
10U_0805_6.3V6M
2
1
C508
10U_0805_6.3V6M
2
1
C510
10U_0805_6.3V6M
2
1
C259
+
2
330U_D2E_2.5VM_R9
330U_D2E_2.5VM_R9
1
C255
+
2
3
1
C529
10U_0805_6.3V6M
2
1
C254
10U_0805_6.3V6M
2
1
C514
10U_0805_6.3V6M
2
1
C515
10U_0805_6.3V6M
2
1
C232
10U_0805_6.3V6M
2
1
C193
10U_0805_6.3V6M
2
1
C519
10U_0805_6.3V6M
2
1
C520
10U_0805_6.3V6M
2
Place these caps inside
the CPU socket.
( Right side on Top side).( Left side on Top ).
1
C258
10U_0805_6.3V6M
2
1
C203
10U_0805_6.3V6M
2
1
C522
10U_0805_6.3V6M
2
1
C526
10U_0805_6.3V6M
2
1
C505
10U_0805_6.3V6M
2
1
C200
10U_0805_6.3V6M
2
1
C533
10U_0805_6.3V6M
2
1
C532
10U_0805_6.3V6M
2
ESR <= 1.5m ohm
Capacitor > 880 uF
Place these inside
socket cavity on L8
(North side
Secondary)
2
1
2
1
2
C504
10U_0805_6.3V6M
C192
10U_0805_6.3V6M
1
C257
10U_0805_6.3V6M
2
1
C199
10U_0805_6.3V6M
2
1
C261
10U_0805_6.3V6M
2
1
C208
10U_0805_6.3V6M
2
1
Place these caps inside
the CPU socket.
1
( Left side on Top ).
C214
10U_0805_6.3V6M
2
Place these caps inside
the CPU socket.
1
( Right side on Top ).
C226
10U_0805_6.3V6M
2
4
1
C209
0.1U_0402_10V6K
2
1
C212
0.1U_0402_10V6K
2
http://laptop-motherboard-schematic.blogspot.com/
1
C213
0.1U_0402_10V6K
A A
5
2
1
C185
0.1U_0402_10V6K
2
1
C183
0.1U_0402_10V6K
2
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
1
C184
0.1U_0402_10V6K
2
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
2
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
Penryn(3/3)-AGTL+/ITP-XDP
LA-4592P
1
of
643Thursday, February 19, 2009
0.2
Page 7
5
H_D#[0..63]5
D D
C C
H_RESET#4
H_CPUSLP#5
B B
Layout Note:
H_RCOMP / H_VREF / H_SWNG
trace width and spacing is 10/20
+VCCP
12
R45
1K_0402_1%
A A
12
R46
2K_0402_1%
1
2
0.1U_0402_16V4Z
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_SWNG
H_RCOMP
H_RESET#
H_CPUSLP#
+H_VREF
+H_VREF
@
C391
U4A
F2
G8
F8
E6
G2
H6
H2
F6
D4
H3
M9
M11
J1
J2
N12
J6
P2
L2
R2
N9
L6
M5
J3
N2
R1
N5
N6
P13
N8
L7
N10
M3
Y3
AD14
Y6
Y10
Y12
Y14
Y7
W2
AA8
Y9
AA13
AA9
AA11
AD11
AD10
AD13
AE12
AE9
AA2
AD8
AA3
AD3
AD7
AE14
AF3
AC1
AE3
AC3
AE11
AE8
AG2
AD6
C5
E3
C12
E11
A11
B11
CANTIGA_1p0
H_RCOMP
12
R324
24.9_0402_1%
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
H_SWING
H_RCOMP
H_CPURST#
H_CPUSLP#
H_AVREF
H_DVREF
+VCCP
12
R322
221_0603_1%
12
R323
100_0402_1%
HOST
H_SWNG
1
C386
2
0.1U_0402_16V4Z
H_ADSTB#_0
H_ADSTB#_1
H_DEFER#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
Near B3 pinwithin 100 mils from NB
5
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
H_ADS#
H_BNR#
H_BPRI#
H_BREQ#
H_DBSY#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_RS#_0
H_RS#_1
H_RS#_2
4
H_A#3
A14
H_A#4
C15
H_A#5
F16
H_A#6
H13
H_A#7
C18
H_A#8
M16
H_A#9
J13
H_A#10
P16
H_A#11
R16
H_A#12
N17
H_A#13
M13
H_A#14
E17
H_A#15
P17
H_A#16
F17
H_A#17
G20
H_A#18
B19
H_A#19
J16
H_A#20
E20
H_A#21
H16
H_A#22
J20
H_A#23
L17
H_A#24
A17
H_A#25
B17
H_A#26
L16
H_A#27
C21
H_A#28
J17
H_A#29
H20
H_A#30
B18
H_A#31
K17
H_A#32
B20
H_A#33
F21
H_A#34
K21
H_A#35
L20
H_ADS#
H12
H_ADSTB#0
B16
H_ADSTB#1
G17
H_BNR#
A9
H_BPRI#
F11
H_BR0#
G12
H_DEFER#
E9
H_DBSY#
B10
CLK_MCH_BCLK
AH7
CLK_MCH_BCLK#
AH6
H_DPWR#
J11
H_DRDY#
F9
H_HIT#
H9
H_HITM#
E12
H_LOCK#
H11
H_TRDY#
C9
H_DINV#0
J8
H_DINV#1
L3
H_DINV#2
Y13
H_DINV#3
Y1
H_DSTBN#0
L10
H_DSTBN#1
M7
H_DSTBN#2
AA5
H_DSTBN#3
AE6
H_DSTBP#0
L9
H_DSTBP#1
M8
H_DSTBP#2
AA6
H_DSTBP#3
AE5
H_REQ#0
B15
H_REQ#1
K13
H_REQ#2
F13
H_REQ#3
B13
H_REQ#4
B14
H_RS#0
B6
H_RS#1
F12
H_RS#2
C8
ICH_PWROK19,26
VGATE19,26,39
Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.
+V_DDR_MCH_REF13,14
4
3
H_A#[3..35] 4
+1.8V
1
+SMRCOMP_VOH
H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPRI# 4
H_BR0# 4
H_DEFER# 4
H_DBSY# 4
CLK_MCH_BCLK 15
CLK_MCH_BCLK# 15
H_DPWR# 5
H_DRDY# 4
H_HIT# 4
H_HITM# 4
H_LOCK# 4
H_TRDY# 4
H_DINV#0 5
H_DINV#1 5
H_DINV#2 5
H_DINV#3 5
H_DSTBN#0 5
H_DSTBN#1 5
H_DSTBN#2 5
H_DSTBN#3 5
H_DSTBP#0 5
H_DSTBP#1 5
H_DSTBP#2 5
H_DSTBP#3 5
H_REQ#0 4
H_REQ#1 4
H_REQ#2 4
H_REQ#3 4
H_REQ#4 4
H_RS#0 4
H_RS#1 4
H_RS#2 4
PLT_RST#17,26,29
H_THERMTRIP#4,18
DPRSLPVR19,39
1 2
R408 0_0402_5%
1 2
R407 0_0402_5%@
+V_DDR_MCH_REF
1
C398
2.2U_0603_6.3V4Z
2
1
C403
2
2.2U_0603_6.3V4Z
1
C121
2
0.1U_0402_16V4Z
12
C400
0.01U_0402_25V7K
2
12
12
1
C404
2
0.01U_0402_25V7K
PM_E XTTS#0
PM_E XTTS#1
1 2
R56 0_0402_5%
PM_PWROK_R
+1.8V
12
R42
1K_0402_1%
12
R43
1K_0402_1%
R331
1K_0402_1%
R332
3.01K_0402_1%
NA lead free
R333
1K_0402_1%
MCH_CLKSEL015
MCH_CLKSEL115
MCH_CLKSEL215
PM_BMBUSY#19
1 2
R523 100_0402_5%
R82
1 2
10K_0402_5%
R83
1 2
10K_0402_5%
CFG59
CFG69
CFG79
CFG99
CFG169
CFG199
CFG209
H_DPRSTP#5,18,39
PM_EXTTS#013
PM_EXTTS#114
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
http://laptop-motherboard-schematic.blogspot.com/
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
T7
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T24
T25
T26
T27
T28
T41
T44
T73
T74
+3VS
MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
T8PAD
T9PAD
CFG5
CFG6
CFG7
T37PAD
CFG9
T65PAD
T40PAD
CFG12
T67PAD
CFG13
T47PAD
T10PAD
T66PAD
CFG16
T68PAD
T39PAD
CFG19
CFG20
PM_BMBUSY#
H_DPRSTP#
PM_E XTTS#0
PM_E XTTS#1
PM_PWROK_R
PLT_RST#_NBPLT_RST#
THERMTRIP#
DPRSLPVR
H_DPRSTP#
1
@
C1816
2
18P_0402_50V8J
2006/02/13 2006/03/10
U4B
M36
RSVD1
N36
RSVD2
R33
RSVD3
T33
RSVD4
AH9
RSVD5
AH10
RSVD6
AH12
RSVD7
AH13
RSVD8
K12
RSVD9
AL34
RSVD10
AK34
RSVD11
AN35
RSVD12
AM35
RSVD13
T24
RSVD14
B31
RSVD15
B2
RSVD16
M1
RSVD17
AY21
RSVD20
BG23
RSVD22
BF23
RSVD23
BH18
RSVD24
BF18
RSVD25
T25
CFG_0
R25
CFG_1
P25
CFG_2
P20
CFG_3
P24
CFG_4
C25
CFG_5
N24
CFG_6
M24
CFG_7
E21
CFG_8
C23
CFG_9
C24
CFG_10
N21
CFG_11
P21
CFG_12
T21
CFG_13
R20
CFG_14
M20
CFG_15
L21
CFG_16
H21
CFG_17
P29
CFG_18
R28
CFG_19
T28
CFG_20
R29
PM_SYNC#
B7
PM_DPRSTP#
N33
PM_EXT_TS#_0
P32
PM_EXT_TS#_1
AT40
PWROK
AT11
RSTIN#
T20
THERMTRIP#
R32
DPRSLPVR
BG48
NC_1
BF48
NC_2
BD48
NC_3
BC48
NC_4
BH47
NC_5
BG47
NC_6
BE47
NC_7
BH46
NC_8
BF46
NC_9
BG45
NC_10
BH44
NC_11
BH43
NC_12
BH6
NC_13
BH5
NC_14
BG4
NC_15
BH3
NC_16
BF3
NC_17
BH2
NC_18
BG2
NC_19
BE2
NC_20
BG1
NC_21
BF1
NC_22
BD1
NC_23
BC1
NC_24
F1
NC_25
A47
NC_26
CANTIGA_1p0
Compal Secret Data
Deciphered Date
2
M_CLK_DDR0
AP24
SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1
SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1
SA_CKE_0
SA_CKE_1
RSVD
CFG
PM
NC
SB_CKE_0
SB_CKE_1
SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1
SA_ODT_0
SA_ODT_1
SB_ODT_0
SB_ODT_1
SM_RCOMP
SM_RCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#
DPLL_REF_CLK
DDR CLK/ CONTROL/COMPENSATION
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
PEG_CLK
PEG_CLK#
CLK
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI
DMI_TXP_3
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4
GFX_VR_EN
GRAPHICS VID
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF
MEHDA
DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLKREQ#
ICH_SYNC#
TSATN#
MISC
HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC
2
M_CLK_DDR1
AT21
M_CLK_DDR2
AV24
M_CLK_DDR3
AU20
M_CLK_DDR#0
AR24
M_CLK_DDR#1
AR21
M_CLK_DDR#2
AU24
M_CLK_DDR#3
AV20
DDR_CKE0_DIMMA
BC28
DDR_CKE1_DIMMA
AY28
DDR_CKE2_DIMMB
AY36
DDR_CKE3_DIMMB
BB36
DDR_CS0_DIMMA#
BA17
DDR_CS1_DIMMA#
AY16
DDR_CS2_DIMMB#
AV16
DDR_CS3_DIMMB#+SMRCOMP_VOL
AR13
M_ODT0
BD17
M_ODT1
AY17
M_ODT2
BF15
M_ODT3
AY13
SMRCOMP
BG22
SMRCOMP#
BH21
+SMRCOMP_VOH
BF28
+SMRCOMP_VOL
BH28
+V_DDR_MCH_REF
AV42
AR36
SM_REXT
BF17
TP_SM_DRAMRST#
BC36
CLK_MCH_DREFCLK
B38
CLK_MCH_DREFCLK#
A38
MCH_SSCDREFCLK
E41
MCH_SSCDREFCLK#
F41
CLK_MCH_3GPLL
F43
CLK_MCH_3GPLL#
E43
DMI_MRX_ITX_N0
AE41
DMI_MRX_ITX_N1
AE37
DMI_MRX_ITX_N2
AE47
DMI_MRX_ITX_N3
AH39
DMI_MRX_ITX_P0
AE40
DMI_MRX_ITX_P1
AE38
DMI_MRX_ITX_P2
AE48
DMI_MRX_ITX_P3
AH40
DMI_MTX_IRX_N0
AE35
DMI_MTX_IRX_N1
AE43
DMI_MTX_IRX_N2
AE46
DMI_MTX_IRX_N3
AH42
DMI_MTX_IRX_P0
AD35
DMI_MTX_IRX_P1
AE44
DMI_MTX_IRX_P2
AF46
DMI_MTX_IRX_P3
AH43
B33
B32
G33
F33
E33
C34
CL_CLK0
AH37
CL_DATA0
AH36
M_PWROK
AN36
CL_RST#
AJ35
+CL_VREF +CL_VREF
AH34
N28
M28
G36
E36
CLKREQ#_7
K36
MCH_ICH_SYNC#
H36
B12
B28
B30
B29
C29
A28
0905 Add test point
Title
Size Document Number Rev
Custom
Date: Sheet
1
M_CLK_DDR0 13
M_CLK_DDR1 13
M_CLK_DDR2 14
M_CLK_DDR3 14
M_CLK_DDR#0 13
M_CLK_DDR#1 13
M_CLK_DDR#2 14
M_CLK_DDR#3 14
DDR_CKE0_DIMMA 13
DDR_CKE1_DIMMA 13
DDR_CKE2_DIMMB 14
DDR_CKE3_DIMMB 14
DDR_CS0_DIMMA# 13
DDR_CS1_DIMMA# 13
DDR_CS2_DIMMB# 14
DDR_CS3_DIMMB# 14
M_ODT0 13
M_ODT1 13
M_ODT2 14
M_ODT3 14
R328 80.6_0402_1%
1 2
R329 80.6_0402_1%
1 2
R39 10K_0402_1%
1 2
R40 499_0402_1%
1 2
T29 PAD
CLK_MCH_DREFCLK 15
CLK_MCH_DREFCLK# 15
MCH_SSCDREFCLK 15
MCH_SSCDREFCLK# 15
CLK_MCH_3GPLL 15
CLK_MCH_3GPLL# 15
DMI_MRX_ITX_N0 19
DMI_MRX_ITX_N1 19
DMI_MRX_ITX_N2 19
DMI_MRX_ITX_N3 19
DMI_MRX_ITX_P0 19
DMI_MRX_ITX_P1 19
DMI_MRX_ITX_P2 19
DMI_MRX_ITX_P3 19
DMI_MTX_IRX_N0 19
DMI_MTX_IRX_N1 19
DMI_MTX_IRX_N2 19
DMI_MTX_IRX_N3 19
DMI_MTX_IRX_P0 19
DMI_MTX_IRX_P1 19
DMI_MTX_IRX_P2 19
DMI_MTX_IRX_P3 19
T30
T31
T32
T33
T34
T35
CL_CLK0 19
CL_DATA0 19
M_PWROK 19
CL_RST# 19
1
C181
0.1U_0402_16V4Z
T36
R1430
1 2
56_0402_5%
T99
T100
T101
T102
T103
T48
T63
T64
CLKREQ#_7 15
MCH_ICH_SYNC# 19
+VCCP
2
Compal Electronics, Inc.
Cantiga(1/6)-AGTL/DMI/DDR
LA-4592P
1
+VCCP
12
12
743Thursday, February 19, 2009
+1.8V
R100
1K_0402_1%
R99
511_0402_1%
of
0.2
Page 8
5
D D
DDR_A_D[0..63]13
C C
B B
DDR_A_D0 DDR_B_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
AJ38
AJ41
AN38
AM38
AJ36
AJ40
AM44
AM42
AN43
AN44
AU40
AT38
AN41
AN39
AU44
AU42
AV39
AY44
BA40
BD43
AV41
AY43
BB41
BC40
AY37
BD38
AV37
AT36
AY38
BB38
AV36
AW36
BD13
AU11
BC11
BA12
AU13
AV13
BD12
BC12
AU10
BA11
AN10
AM11
AM5
AN12
AM13
AJ11
AJ12
BB9
BA9
AV9
BD9
AY8
BA6
AV5
AV7
AT9
AN8
AU5
AU6
AT5
AJ9
AJ8
U4D
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
CANTIGA_1p0
DDR SYSTEM MEMORY A
SA_BS_0
SA_BS_1
SA_BS_2
SA_RAS#
SA_CAS#
SA_WE#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
4
DDR_A_BS#0
BD21
BG18
AT25
BB20
BD20
AY20
AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5
AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7
AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8
BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25
DDR_A_BS#1
DDR_A_BS#2
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_BS#0 13
DDR_A_BS#1 13
DDR_A_BS#2 13
DDR_A_RAS# 13
DDR_A_CAS# 13
DDR_A_WE# 13
DDR_A_DM[0..7] 13
DDR_A_DQS[0..7] 13
DDR_A_DQS#[0..7] 13
DDR_A_MA[0..14] 13
3
DDR_B_D[0..63]14
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
AK47
AH46
AP47
AP46
AJ46
AJ48
AM48
AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43
BF43
BE45
BC41
BF40
BF41
BG38
BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11
BG8
BH12
BF11
BF8
BG7
BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1
AH1
AM2
AM3
AH3
AL1
AL2
AJ1
AJ3
U4E
CANTIGA_1p0
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
2
DDR_B_BS#0
BC16
SB_BS_0
SB_BS_1
SB_BS_2
SB_RAS#
SB_CAS#
SB_WE#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
DDR SYSTEM MEMORY B
BB17
BB33
AU17
BG16
BF14
AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2
AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5
AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33
DDR_B_BS#1
DDR_B_BS#2
DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
1
DDR_B_BS#0 14
DDR_B_BS#1 14
DDR_B_BS#2 14
DDR_B_RAS# 14
DDR_B_CAS# 14
DDR_B_WE# 14
DDR_B_DM[0..7] 14
DDR_B_DQS[0..7] 14
DDR_B_DQS#[0..7] 14
DDR_B_MA[0..14] 14
A A
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
http://laptop-motherboard-schematic.blogspot.com/
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
Cantiga(2/6)-DDR2 A/B CH
LA-4592P
1
0.2
of
843Thursday, February 19, 2009
Page 9
5
1 2
1 2
T145
T146
T147
T148
3VDDCCL
3VDDCDA
CRT_HSYNC
CRT_VSYNC
GMCH_ENBKL
GMCH_EDID_CLK_LCD
GMCH_EDID_DAT_LCD
GMCH_LVDDEN
R94 2.4K_0402_1%~D
GMCH_LVDSACGMCH_LVDSAC+
GMCH_LVDSBCGMCH_LVDSBC+
GMCH_LVDSA0GMCH_LVDSA1GMCH_LVDSA2GMCH_LVDSA3-
GMCH_LVDSA0+
GMCH_LVDSA1+
GMCH_LVDSA2+
GMCH_LVDSA3+
GMCH_LVDSB0GMCH_LVDSB1GMCH_LVDSB2GMCH_LVDSB3-
GMCH_LVDSB0+
GMCH_LVDSB1+
GMCH_LVDSB2+
GMCH_LVDSB3+
CRT_B
CRT_G
CRT_R
R74
1 2
150_0402_1%
1 2
1 2
1 2
1 2
R76
1 2
150_0402_1%
CTRL_CLK
CTRL_DATA
R150775_0402_1%
R150875_0402_1%
R150975_0402_1%
R75
1 2
150_0402_1%
12
R334
1K_0402_1%
GMCH_ENBKL16,26
GMCH_EDID_CLK_LCD16
GMCH_EDID_DAT_LCD16
GMCH_LVDDEN16
GMCH_LVDSAC-16
GMCH_LVDSAC+16
GMCH_LVDSBC-16
GMCH_LVDSBC+16
GMCH_LVDSA0-16
GMCH_LVDSA1-16
GMCH_LVDSA2-16
GMCH_LVDSA0+16
GMCH_LVDSA1+16
GMCH_LVDSA2+16
GMCH_LVDSB0-16
GMCH_LVDSB1-16
GMCH_LVDSB2-16
GMCH_LVDSB0+16
GMCH_LVDSB1+16
GMCH_LVDSB2+16
3VDDCCL16
3VDDCDA16
CRT_HSYNC16
CRT_VSYNC16
R81 10K_0402_5%
R80 10K_0402_5%
CRT_B16
CRT_G16
CRT_R16
+3VS
D D
C C
L32
G32
M32
M33
K33
J33
M29
C44
B43
E37
E38
C41
C40
B37
A37
H47
E46
G40
A40
H48
D45
F40
B40
A41
H38
G37
J37
B42
G38
F37
K37
F25
H25
K25
H24
C31
E32
E28
G28
J28
G29
H32
J32
J29
E29
L29
4
U4C
L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK
LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA#_3
LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSA_DATA_3
LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA#_3
LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
LVDSB_DATA_3
TVA_DAC
TVB_DAC
TVC_DAC
TV_RTN
TV_DCONSEL_0
TV_DCONSEL_1
CRT_BLUE
CRT_GREEN
CRT_RED
CRT_IRTN
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC
CANTIGA_1p0
LVDS
TV
VGA
PEG_COMPI
PEG_COMPO
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PCI-EXPRESS GRAPHICS
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
R56 within 500 mils from
pin T37,T36
T37
T36
H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39
H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40
J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46
J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46
R95
1 2
49.9_0402_1%
3
PEGCOMP trace width
+VCC_PEG
and spacing is 20/25 mils.
2
1
Strap Pin Table
CFG[2:0] FSB Freq select
CFG[4:3] Reserved
CFG5 (DMI select)
CFG6
CFG6
CFG7 (Intel Management
Engine Crypto strap)
CFG8
CFG9
(PCIE Graphics Lane Reversal)
CFG10 (PCIE Lookback enable)
CFG11
CFG[13:12] (XOR /A LLZ)
CFG16 (FSB Dynamic ODT)
CFG19 (DMI Lane Reversal)
CFG20 (PCIE/SDVO concurrent)
CFG57
CFG67
CFG77
CFG97
CFG167
000 = FSB 1066MHz
010 = FSB 800MHz
011 = FSB 667MHz
Others = Reserved
0 = DMI x 2
1 = DMI x 4
0 = The iTPM Host Interface is enable
1 = The iTPM Host I nterface is disable
0 =(TLS)chiper suite with no confidentiality
1 =(TLS)chipe r s u ite with confidentiality
*
Reserved
0 = Reverse Lane,15->0, 14->1
1 = Normal Operation,Lane Number in order
0 = Enable
1 = Disable
*
Reserved
00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
ReservedCFG[15:14]
0 = Disabled
1 = Enabled
*
ReservedCFG[18:17]
0 = Normal Operation
(Lane number in Order)
1 = Reverse Lane
0 = Only PCIE or SDVO is operational.
1 = PCIE/SDVO are operating simu.
R66 2.21K_0402_1%~D@
1 2
R58 2.21K_0402_1%~D@
1 2
R59 2.21K_0402_1%~D@
1 2
R55 2.21K_0402_1%~D@
1 2
R70 2.21K_0402_1%~D@
1 2
*
*
*
(Default)11 = Normal Operation
*
*
*
CFG[5:16] have internal pullup
+3VS
B B
A A
R483 2.2K_0402_5%
R484 2.2K_0402_5%
1 2
1 2
GMCH_EDID_CLK_LCD
GMCH_EDID_DAT_LCD
5
Security Classification
Issued Date
THIS SHEET OF ENGI NEERING DRAWING I S T HE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CON FIDENTIAL
http://laptop-motherboard-schematic.blogspot.com/
4
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY COMPAL E LECTRONIC S, INC. NEITH ER THIS SHEET NOR THE INF ORMATION IT C ONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CO NSENT OF CO MPAL ELECTR ONICS, INC.
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
2
CFG197
CFG207
R72 4.02K_0402_1%~D@
1 2
R73 4.02K_0402_1%~D@
1 2
CFG[19:20] have internal pulldown
Compal Electronics, Inc.
Title
Cantiga(3/6)-VGA/LVDS/TV
Size Document Number Rev
Custom
LA-4592P
Date: Sheet
+3VS
1
943Thursday, Fe b ruary 19, 2009
0.2
of
Page 10
5
+3VS_DAC_CRT
47U_1206_6.3V6M
0.01U_0402_25V7K~N
C411
C407
C1835
1
2
SolveCRT Voltage ripple
D D
+3VS_DAC_BG
C C
+3VS_DAC_CRT
B B
C401
1
2
0.01U_0402_25V7K~N
C408
C405
1
2
+1.5VS
+VCCP
0.01U_0402_25V7K~N
C402
1
1
2
2
1
2
R836 0_0402_5%~D
1
2
R71
1 2
0_0603_5%
0.1U_0402_10V4Z
L15
1 2
0_0603_5%
0.1U_0402_10V4Z
1 2
COIL 2.2U +-2 0% I HL P-2525CZ-ER-2R2-M-01 8A
L114
@
+3VS_DAC_CRT
1 2
0.1U_0402_10V4Z
1
2
100U_D2E_6.3VM_R15M~D
R50
1 2
0_0805_5%
1
+
C68
2
+1.05VS_HPLL
+1.05VS_PEGPLL
C1780 0.1U _0402_16V4Z
2
1
+3VS
+1.8V_TXLVDS
C175
0.1U_0402_16V4Z
+1.05VS_A_SM
22U_0805_6.3V6M~D
C82
1
C83
4.7U_0805_10V4Z
2
+1.05VS_A_SM_CK
22U_0805_6.3V6M~D
C104
1
2
+3VS_DAC_CRT
HDMI disable connected to GND
C233 0.1U_0402_16V4Z
2
1
+1.05VS_DPLLA
+1.05VS_DPLLB
+1.05VS_HPLL
+1.05VS_MPLL
1
C413
1000P_0402_50V7K
2
+1.05VS_PEGPLL
1
2
1U_0603_10V4Z
0.1U_0402_16V4Z
C123
1
2
+1.5VS_TVDAC
+1.5VS_QDAC
+1.8V_LVDS
+3VS_DAC_CRT
+3VS_DAC_BG
1
C72
2
TVA 24.15mA
TVB 39.48mA
TVX 24.15mA
58.67mA
48.363mA
157.2mA
60.31mA
4
U4H
73mA
B27
VCCA_CRT_DAC_1
A26
VCCA_CRT_DAC_2
2.68mA
A25
VCCA_DAC_BG
B25
VSSA_DAC_BG
64.8mA
F47
64.8mA
139.2mA
13.2mA
720mA
50mA
VCCA_DPLLA
L48
VCCA_DPLLB
24mA
AD1
VCCA_HPLL
AE1
VCCA_MPLL
J48
VCCA_LVDS
J47
VSSA_LVDS
414uA
AD48
VCCA_PEG_BG
50mA
AA48
VCCA_PEG_PLL
AR20
VCCA_SM_1
AP20
VCCA_SM_2
AN20
VCCA_SM_3
AR17
VCCA_SM_4
AP17
VCCA_SM_5
AN17
VCCA_SM_6
AT16
VCCA_SM_7
AR16
VCCA_SM_8
AP16
VCCA_SM_9
26mA 321.35mA
AP28
VCCA_SM_CK_1
AN28
VCCA_SM_CK_2
AP25
VCCA_SM_CK_3
AN25
VCCA_SM_CK_4
AN24
VCCA_SM_CK_5
AM28
VCCA_SM_CK_NCTF_1
AM26
VCCA_SM_CK_NCTF_2
AM25
VCCA_SM_CK_NCTF_3
AL25
VCCA_SM_CK_NCTF_4
AM24
VCCA_SM_CK_NCTF_5
AL24
VCCA_SM_CK_NCTF_6
AM23
VCCA_SM_CK_NCTF_7
AL23
VCCA_SM_CK_NCTF_8
B24
VCCA_TV_DAC_1
A24
VCCA_TV_DAC_2
A32
VCC_HDA
CRTPLLA PEGA SM
A LVDS
POWER
A CK
TV
AXF
VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4
SM CK
VCC_TX_LVDS
HV
HDA
M25
50mA
AA47
L28
AF1
M38
L37
VCCD_TVDAC
VCCD_QDAC
VCCD_HPLL
VCCD_PEG_PLL
VCCD_LVDS_1
VCCD_LVDS_2
PEG
D TV/CRT
DMI
LVDS
CANTIGA_1p0
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25
VCC_AXF_1
VCC_AXF_2
VCC_AXF_3
VCC_HV_1
VCC_HV_2
VCC_HV_3
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5
VCC_DMI_1
VCC_DMI_2
VCC_DMI_3
VCC_DMI_4
VTTLF1
VTTLF2
VTTLF3
VTTLF
U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1
B22
B21
A21
BF21
BH20
BG20
BF20
K47
C35
B35
A35
V48
U48
V47
U47
U46
AH48
AF48
AH47
AG47
A8
L1
AB2
852mA
124mA
118.8mA
1732mA
456mA
20mils
C382
+VCCP
0.47U_0603_10V7K
3
220U_D2_4VY_R15M
+V1.05VS_AXF
+1.8V_SM_CK
+1.8V_TXLVDS
105.3mA
+VCC_PEG
+1.05VS_DMI
0.47U_0603_10V7K
C385
1
2
2
+1.05VS_DPLLA
L17
C173
1
+
2
C178
0.1U_0402_10V4Z
1
2
+1.05VS_HPLL
C388
+1.05VS_MPLL
C63
+1.05VS_PEGPLL
0.1U_0402_16V4Z
0.1U_0402_10V4Z
1
2
10U_0805_10V4Z
1
2
0.1U_0402_16V4Z
1
2
1
2
C176
1
2
0.01U_0402_25V7K~N
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C98
1
2
220U_D2_4VY_R15M
C191
C174
L113
1 2
BLM18PG181SN1D_0603
1
C370
2
1
C383
2
C65
1
2
4.7U_0805_10V4Z
C384
1
+
2
0.47U_0603_10V7K
C373
C410
0.47U_0603_10V7K
1
2
4.7U_0805_10V4Z
1
2
+3VS
1
2
1
C56
2
0.1U_0402_16V4Z
+1.5VS_QDAC
2.2U_0805_16V4Z
C97
1
2
10UH_LB2012T100MR_20%_0805~D
10U_0805_10V4Z
C182
1
2
L16
12
10UH_LB2012T100MR_20%_0805~D
L29
1 2
MBK2012121YZF_0805
4.7U_0805_10V4Z
C1774
1
2
L9
1 2
LQH32CNR15M33L_1210~D
0_0603_5%
R1415
1 2
1
C62
22U_0805_6.3V6M~D
2
L12
1 2
BLM21PG221SN1D_0805~D
R1416
1_0402_5%~D
10U_0805_10V4Z
C179
1
2
+1.5VS
+VCCP+1.05VS_DPLLB
12
+VCCP
+VCCP
+VCCP
+VCCP
+V1.05VS_AXF
10U_0805_10V4Z
+1.5VS_TVDAC
22U_0805_6.3V6M~D
1
2
C113
1
2
+1.8V_SM_CK
C96
1
2
1
C161
2
+VCC_PEG
C1775
1
+
C95
2
+1.05VS_DMI
1
2
1
1U_0603_10V4Z
10U_0805_10V4Z
0.022U_0402_16V7K
C162
C1776
220U_D2_4VY_R15M
1 2
0.1U_0402_16V4Z
C116
C69
1
2
0.1U_0402_16V4Z
0.1U_0402_10V4Z
1
2
4.7U_0805_10V4Z
1
2
R112
0_0805_5%
1 2
C102
1
2
+VCC_PEG
R101
0_0603_5%
R102
1 2
0_0805_5%
R84
1 2
0_0805_5%
PJP28
JUMP_43X118@
112
+VCCP
+1.8V
+1.5VS
+VCCP
2
+1.8V_LVDS
R110
10U_0805_10V4Z
1
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
http://laptop-motherboard-schematic.blogspot.com/
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMAT ION IT CON TAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
2
2
1 2
0_0603_5%
C186
1U_0603_10V4Z
C187
1
2
Title
Cantiga(4/6)-PWR
Size Doc ument Number Rev
Custom
LA-4592P
Date: Sheet
+1.8V_TXLVDS
40 mils
1000P_0402_50V7K
1
2
R350
1 2
0_0603_5%
10U_0805_10V4Z
C414
C418
1
2
Compal Electronics, Inc.
10 43Thursday, February 19, 2009
1
+1.8V+1.8V
0.2
of
Page 11
5
4
3
2
1
W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16
AV44
BA37
AM40
AV21
AY5
AM10
BB13
+VCCP
VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7
330U_D2_2.5VY_R15M
330U_D2_2.5VY_R15M
@
1
C101
+
2
1U_0603_10V4Z~D
1
1
C78
2
2
C67 0.22U_0603_10V7K
C71 0.1U_0402_16V4Z
1
1
2
2
Layout Note:
Place close to GMCH
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
1
1
C100
C57
2
2
C146 0.47U_0402_6.3V6K
C81 0.22U_0603_10V7K
1
1
1
2
2
2
@
1
C86
+
2
0.47U_0402_6.3V4Z~D
1
C99
2
Layout Note: Inside GMCH
cavity for VCC_AXG.
C70 0.1U_0402_16V4Z
1
2
22U_0805_6.3VAM~D
10U_0805_10V4Z~D
1
C80
C79
2
C163 1U_0603_10V4Z
C145 1U_0603_10V4Z
1
2
U4G
Extnal Graphic: 1210.34mA
integrated Graphic: 1930.4mA
+1.8V
1
+
2
330U_V_2.5VM
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
C165
1
C148
2
0317 change value
0.1U_0402_10V7K~D
C147
2
1
C164
1
2
+VCCP
T42PAD
T43PAD
AG34
AC34
AB34
AA34
Y34
V34
U34
AM33
AK33
AJ33
AG33
AF33
AE33
AC33
AA33
Y33
W33
V33
U33
AH28
AF28
AC28
AA28
AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24
AJ23
AH23
AF23
T32
U4F
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
CANTIGA_1p0
VCC CORE
POWER
VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC NCTF
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23
+VCCP
+VCCP
D D
22U_0805_6.3V6M~D
220U_D2_4VY_R15M
C374
C C
B B
0.22U_0402_10V4Z
1
C118
1
+
2
2
0.1U_0402_16V4Z
0.22U_0402_10V4Z
C143
1
2
C120
C119
1
1
2
2
AP33
AN33
BH32
BG32
BF32
BD32
BC32
BB32
BA32
AY32
AW32
AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29
AW29
AV29
AU29
AT29
AR29
AP29
BA36
BB24
BD16
BB21
AW16
AW13
AT13
AE25
AB25
AA25
AE24
AC24
AA24
AE23
AC23
AB23
AA23
AJ21
AG21
AE21
AC21
AA21
AH20
AF20
AE20
AC20
AB20
AA20
AM15
AL15
AE15
AJ15
AH15
AG15
AF15
AB15
AA15
AN14
AM14
AJ14
AH14
Y26
Y24
Y21
T17
T16
Y15
V15
U15
U14
T14
3000mA
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36/NC
VCC_SM_37/NC
VCC_SM_38/NC
VCC_SM_39/NC
VCC_SM_40/NC
VCC_SM_41/NC
VCC_SM_42/NC
6326.84mA
VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42
VCC_AXG_SENSE
VSS_AXG_SENSE
POWER
VCC SMVCC GFX
VCC GFX NCTF
VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
VCC SM LF
A A
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
http://laptop-motherboard-schematic.blogspot.com/
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
Compal Secret Data
CANTIGA_1p0
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
Cantiga(5/6)-PWR/GND
LA-4592P
1
0.2
of
11 43Thursday, February 19, 2009
Page 12
5
4
3
2
1
U4I
AU48
VSS_1
AR48
VSS_2
AL48
VSS_3
BB47
VSS_4
AW47
VSS_5
AN47
VSS_6
AJ47
VSS_7
AF47
D D
C C
B B
A A
AD47
AB47
BD46
BA46
AY46
AV46
AR46
AM46
BF44
AH44
AD44
AA44
M44
BC43
AV43
AU43
AM43
BG42
AY42
AT42
AN42
AJ42
AE42
BD41
AU41
AM41
AH41
AD41
AA41
M41
BG40
BB40
AV40
AN40
AT39
AM39
AJ39
AE39
BH38
BC38
BA38
AU38
AH38
AD38
AA38
BF37
BB37
AW37
AT37
AN37
AJ37
BG36
BD36
AK15
AU36
Y47
T47
N47
L47
G47
V46
R46
P46
H46
F46
Y44
U44
T44
F44
J43
C43
N42
L42
Y41
U41
T41
G41
B41
H40
E40
N39
L39
B39
Y38
U38
T38
J38
F38
C38
H37
C37
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
CANTIGA_1p0
VSS
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6
BG21
AW21
AU21
AP21
AN21
AH21
AF21
AB21
BC20
BA20
AW20
AT20
AJ20
AG20
BG19
BG17
BC17
AW17
AT17
BA16
AU16
AN16
BG15
AC15
W15
BG14
AA14
BG13
BC13
BA13
AN13
AJ13
AE13
BF12
AV12
AT12
AM12
AA12
BD11
BB11
AY11
AN11
AH11
BG10
AV10
AT10
AJ10
AE10
AA10
AM9
L12
R21
M21
J21
G21
Y20
N20
K20
F20
C20
A20
A18
R17
M17
H17
C17
N16
K16
G16
E16
A15
C14
N13
L13
G13
E13
J12
A12
Y11
N11
G11
C11
M10
BF9
BC9
AN9
AD9
BH8
BB8
AV8
AT8
U4J
G9
B9
CANTIGA_1p0
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_235
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS NCTF
VSS_NCTF_15
VSS_NCTF_16
VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5
VSS SCB
NC
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42
AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4
BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1
U24
U28
U25
U29
AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17
BH48
BH1
A48
C1
A3
E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
http://laptop-motherboard-schematic.blogspot.com/
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
Cantiga(6/6)-PWR/GND
LA-4592P
1
0.2
of
12 43Thursday, February 19, 2009
Page 13
5
DDR_A_DQS#[0..7]8
DDR_A_D[0..63]8
DDR_A_DM[0..7]8
DDR_A_DQS[0..7]8
DDR_A_MA[0..13]8
D D
Layout Note:
Place near JDIM1
+1.8V
0.1U_0402_16V4Z
C154
1
2
0.1U_0402_16V4Z
1
1
2
2
C167
C151
DDR_A_BS#2
14
DDR_CKE0_DIMMA
23
DDR_A_MA6
14
DDR_A_MA7
23
DDR_A_MA9
14
DDR_A_MA12
23
DDR_A_MA4
14
DDR_A_MA2
23
DDR_A_BS#1
14
DDR_A_MA0
23
DDR_A_MA13
14
M_ODT0
23
DDR_A_MA11
14
DDR_A_MA14
23
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C131
C130
1
1
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C107
C128
2.2U_0603_6.3V6K
C105
1
2
Layout Note:
C C
Place one cap close to every 2 pullup
resistors terminated to +0.9V
+0.9VS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C106
B B
DDR_A_MA5
DDR_A_MA8
DDR_A_MA1
DDR_A_MA3
DDR_CS0_DIMMA#
DDR_A_RAS#
DDR_A_MA10
A A
DDR_A_BS#0
DDR_A_WE#
DDR_A_CAS#
DDR_CS1_DIMMA#
M_ODT1
DDR_CKE1_DIMMA
C124
1
2
0.1U_0402_16V4Z
1
2
C125
RP14
1 4
2 3
RP13
1 4
2 3
RP7
1 4
2 3
RP6
1 4
2 3
RP5
1 4
2 3
RP1
2 3
1 4
1 2
R96 56_0402_5%
C149
1
2
0.1U_0402_16V4Z
1
1
2
2
C127
C126
56_0404_4P2R_5%
56_0404_4P2R_5%
56_0404_4P2R_5%
56_0404_4P2R_5%
56_0404_4P2R_5%
56_0404_4P2R_5%
5
C166
1
2
0.1U_0402_16V4Z
1
2
C150
+0.9VS
RP22 56_0404_4P2R_5%
RP17 56_0404_4P2R_5%
RP15 56_0404_4P2R_5%
RP16 56_0404_4P2R_5%
RP8 56_0404_4P2R_5%
RP2 56_0404_4P2R_5%
RP23 56_0404_4P2R_5%
C169
1
2
0.1U_0402_16V4Z
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
4
330U 2.5V Y D2
0.1U_0402_16V4Z
1
2
C129
1
C108
1
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C152
Layout Note:
Place these resistor
closely JP41,all
trace length Max=1.5"
4
3
+1.8V
JDIM2
1
VREF
3
DDR_A_D4
DDR_A_D1
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D14
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
+3VS
C58
0.1U_0402_16V4Z
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D29
DDR_A_D24
DDR_A_DM3
DDR_A_D26
DDR_A_D27
DDR_CKE0_DIMMA
DDR_A_BS#2
DDR_A_MA12
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_BS#0
DDR_A_CAS#
DDR_CS1_DIMMA#
M_ODT1
DDR_A_D37
DDR_A_D36
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D35
DDR_A_D34
DDR_A_D40
DDR_A_D44
DDR_A_DM5
DDR_A_D41
DDR_A_D46
DDR_A_D49
DDR_A_D48
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D54
DDR_A_D50
DDR_A_D61
DDR_A_D60
DDR_A_DM7
DDR_A_D59
DDR_A_D58
CLK_SMBDATA
CLK_SMBCLK
1
1
2
2
C59
2.2U_0603_6.3V6K
C84
+
@
DDR_CKE0_DIMMA7
DDR_A_BS#28
DDR_A_BS#08
DDR_A_WE#8
DDR_A_CAS#8
DDR_CS1_DIMMA#7
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C153
1
1
2
2
C1779
C168
M_ODT17
ICH_SM_DA14,15,19,23
ICH_SM_CLK14,15,19,23
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
FOX_ASOA426-M2RN-7F
SO-DIMM A
REVERSE
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
VDD
VDD
BA1
RAS#
VDD
ODT0
NC/A13
VDD
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SA0
SA1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
A11
92
A7
94
A6
96
98
A4
100
A2
102
A0
104
106
108
110
S0#
112
114
116
118
120
NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
2
DDR_A_D5
DDR_A_D0
DDR_A_DM0
DDR_A_D6
DDR_A_D7
DDR_A_D13
DDR_A_D12
DDR_A_DM1
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_D11
DDR_A_D10DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_DM2
DDR_A_D23
DDR_A_D22
DDR_A_D28
DDR_A_D25
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D31
DDR_A_D30
DDR_CKE1_DIMMA
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7DDR_A_MA9
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#DDR_A_WE#
M_ODT0
DDR_A_MA13
DDR_A_D32
DDR_A_D33
DDR_A_DM4
DDR_A_D39
DDR_A_D38
DDR_A_D45
DDR_A_D47
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D43
DDR_A_D42
DDR_A_D52
DDR_A_D53
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_DM6
DDR_A_D51
DDR_A_D55
DDR_A_D57
DDR_A_D56
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
12
R31
R32
10K_0402_5%
10K_0402_5%
Close to VREF pins of SO-DIMM
2.2U_0805_16V4Z
C201
1
2
M_CLK_DDR0 7
M_CLK_DDR#0 7
PM_EXTTS#0 7
DDR_CKE1_DIMMA 7
DDR_A_MA14 8
DDR_A_BS#1 8
DDR_A_RAS# 8
DDR_CS0_DIMMA# 7
M_ODT0 7
M_CLK_DDR1 7
M_CLK_DDR#1 7
12
1
0.1U_0402_16V4Z
C220
1
2
+V_DDR_MCH_REF 7,14
Bottom side
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSE D T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
http://laptop-motherboard-schematic.blogspot.com/
2007/1/15 2008/1/15
3
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
DDR2 SO-DIMM I
LA-4592P
0.2
of
13 43Thursday, February 19, 2009
1
Page 14
5
DDR_B_DQS#[0..7]8
DDR_B_D[0..63]8
DDR_B_DM[0..7]8
DDR_B_DQS[0..7]8
DDR_B_MA[0..13]8
D D
Layout Note:
Place near JDIM2
+1.8V
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
C112
C139
1
1
2
2
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS
C C
+0.9VS
0.1U_0402_16V4Z
1
2
C110
0.1U_0402_16V4Z
1
2
C134
RP18
RP10
RP12
RP11
RP9
RP3
R335 56_0402_5%
0.1U_0402_16V4Z
B B
DDR_B_MA1
DDR_B_MA3
DDR_B_BS#0
DDR_B_MA10
DDR_B_MA0
DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#
A A
DDR_B_CAS#
DDR_B_WE#
DDR_CS3_DIMMB#
M_ODT3
DDR_CKE3_DIMMB
2.2U_0603_6.3V6K
C160
1
2
0.1U_0402_16V4Z
1
2
C135
1 4
2 3
56_0404_4P2R_5%
1 4
2 3
56_0404_4P2R_5%
1 4
2 3
56_0404_4P2R_5%
1 4
2 3
56_0404_4P2R_5%
1 4
2 3
56_0404_4P2R_5%
2 3
1 4
56_0404_4P2R_5%
1 2
5
1
2
C156
2.2U_0603_6.3V6K
1
2
0.1U_0402_16V4Z
1
2
+0.9VS
0.1U_0402_16V4Z
C177
C138
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C157
RP24 56_0404_4P2R_5%
RP26 56_0404_4P2R_5%
RP19 56_0404_4P2R_5%
RP21 56_0404_4P2R_5%
RP20 56_0404_4P2R_5%
RP4 56_0404_4P2R_5%
RP25
56_0404_4P2R_5%
C171
C170
DDR_B_MA9
14
DDR_B_MA12
23
DDR_B_MA14
14
DDR_B_MA11
23
DDR_B_MA8
14
DDR_B_MA5
23
DDR_B_MA7
14
DDR_B_MA6
23
DDR_B_MA4
14
DDR_B_MA2
23
DDR_B_MA13
14
M_ODT2
23
DDR_CKE2_DIMMB
14
DDR_B_BS#2
23
0.1U_0402_16V4Z
C109
C132
1
1
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C136
C111
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C133
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C158
Layout Note:
Place these resistor
closely JP42,all
trace length Max=1.5"
4
330U 2.5V Y D2
1
C189
C155
1
+
@
2
2
DDR_CKE2_DIMMB7
DDR_B_BS#28
DDR_B_BS#08
0.1U_0402_16V4Z
1
2
C137
0.1U_0402_16V4Z
1
1
2
2
C159
C172
DDR_B_CAS#8
DDR_CS3_DIMMB#7
M_ODT37
ICH_SM_DA13,15,19,23
ICH_SM_CLK13,15,19,23
0.1U_0402_16V4Z
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DIS CLOSE D T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
http://laptop-motherboard-schematic.blogspot.com/
3
+1.8V
JDIM1
1
VREF
3
DDR_B_D0
DDR_B_D1
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D17
DDR_B_D20
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D28
DDR_B_D25
DDR_B_DM3
DDR_B_D30
DDR_B_D31
DDR_CKE2_DIMMB
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#
DDR_B_CAS#
DDR_CS3_DIMMB#
M_ODT3
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D51
DDR_B_D50
DDR_B_D56
DDR_B_D61
DDR_B_DM7
DDR_B_D59
DDR_B_D58
CLK_SMBDATA
CLK_SMBCLK
+3VS
1
2
1
C60
2.2U_0603_6.3V6K
2
C61
2007/1/15 2008/1/15
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
FOX_AS0A426-NARN-7F~N
SO-DIMM B
REVERSE
Bottom side
Compal Secret Data
Deciphered Date
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
VDD
VDD
BA1
RAS#
VDD
ODT0
NC/A13
VDD
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
A11
92
A7
94
A6
96
98
A4
100
A2
102
A0
104
106
108
110
S0#
112
114
116
118
120
NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
2
DDR_B_D5
DDR_B_D4
DDR_B_DM0
DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13
DDR_B_DM1
M_CLK_DDR2
M_CLK_DDR#2
DDR_B_D14
DDR_B_D15
DDR_B_D21
DDR_B_D16
DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D29
DDR_B_D24
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D26
DDR_B_D27
DDR_CKE3_DIMMB
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
DDR_B_MA13
DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D39
DDR_B_D38
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D57
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
10K_0402_5%
2
1
Close to VREF pins of SO-DIMM
2.2U_0805_16V4Z
0.1U_0402_16V4Z
1
1
C221
C222
2
2
M_CLK_DDR2 7
M_CLK_DDR#2 7
PM_E XTTS#1 7
DDR_CKE3_DIMMB 7
DDR_B_MA14 8
DDR_B_BS#1 8
DDR_B_RAS# 8
DDR_CS2_DIMMB# 7DDR_B_WE#8
M_ODT2 7
M_CLK_DDR3 7
M_CLK_DDR#3 7
R33
1 2
12
10K_0402_5%
R34
Title
Size Document Number Rev
Custom
Date: Sheet
+3VS
Compal Electronics, Inc.
DDR2 SO-DIMM II
LA-4592P
+V_DDR_MCH_REF 7,13
1
0.2
of
14 43Thursday, February 19, 2009
Page 15
5
PCI
SRC
CPU
CLKSEL1
0
FSA
CLKSEL0
MHz
266
MHz
1000
MHz
MHz
33.30
14.318 96.0 48.0
DOT_96
MHz
FSC FSB REF
CLKSEL2
01000 133 33.31 14.318 96.0 48.0
01001 200 33.30 14.318 96.0 48.0
D D
01001 166 33.31 14.318 96.0 48.0
11000 333 33.30 14.318 96.0 48.0
11000 100 33.31 14.318 96.0 48.0
11001 400 33.30 14.318 96.0 48.0
111
R983
FSA
1 2
2.2K_0402_5%
CPU_BSEL05
C C
CPU_BSEL1
CPU_BSEL15
1 2
R985
1K_0402_5%
1 2
R998
1K_0402_5%
Reserved
MCH_CLKSEL0 7
MCH_CLKSEL1 7
CLK_14M_ICH19
ICH_SM_CLK13,14,19,23
CLK_DEBUG_PORT23
CLK_PCI_EC26
CLK_PCI_TPM27
PCI_CLK17
0905 Connect PCI_CLK
4
USB
MHz
NB
CPU
CK_PWRGD19
ICH_SM_DA13,14,19,23
Routing the tr ace at least 10mil
14.31818MHZ_16P
R1417
0_0402_5%
1 2
Y7
2
C1196
22P_0402_50V8J
CLK_MCH_BCLK#7
CLK_MCH_BCLK7
CLK_CPU_BCLK#4
CLK_CPU_BCLK4
R987 0_0402_5%
R991 33_0402_1%
ICH_SM_DA
ICH_SM_CLK
R1001 33_0402_1%
R1004 33_0402_1%
R1006 33_0402_1%
R1008 33_0402_1%
1 2
1 2
1 2
1 2
1 2
1 2
1
R976 0_0402_5%
R978 0_0402_5%
R980 0_0402_5%
R982 0_0402_5%
T120PAD
CLK_XTAL_OUT
CLK_XTAL_IN
12
2
C1197
22P_0402_50V8J
1
1 2
1 2
12
12
+3VS_CK505
R_CKPWRGD
CPU_BSEL1
CLK_XTAL_OUT
CLK_XTAL_IN
FSC
PCI2_TME
R_CLK_PCI_EC
27_SEL R_CLK_PCIE_MCARD
ITP_EN
3
R_MCH_BCLK#
R_MCH_BCLK
R_CPU_BCLK#
R_CPU_BCLK
U55
1
CKPWRGD/PD#
2
FS_B/TEST_MODE
3
VSS_REF
4
XTAL_OUT
5
XTAL_IN
6
VDD_REF
7
REF_0/FS_C/TEST_
8
REF_1
9
SDA
10
SCL
11
NC
12
VDD_PCI
13
PCI_1
14
PCI_2
15
PCI_3
16
PCI_4/SEL_LCDCL
17
PCIF_5/ITP_EN
18
VSS_PCI
+3VS
+3VS_CK505
73
72
71
70
GND
CPU_0
VDD_CPU
R971
1 2
0_0805_5%
69
68
67
CPU_1
CPU_0#
CPU_1#
VSS_CPU
+3VS_CK505
1
C1189
10U_0805_10V4Z
2
0905 Connect to +VCCP
+1.05VS_CK505
R_CLKREQ#_EXPCARD
65
66
VDD_CPU_IO
64
CLKREQ_7#
SRC_8/CPU_ITP
62
63
61
SRC_7
VDD_SRC_IO
SRC_8#/CPU_ITP#
60
SRC_7#
58
59
57
VSS_SRC
CLKREQ_6#
+VCCP
R_PCIE_EXPR
R_PCIE_EXPR#
55
56
SRC_6
SRC_6#
VDD_SRC
PCI_STOP#
CPU_STOP#
VDD_SRC_IO
CLKREQ_10#
CLKREQ_11#
CLKREQ_9#
CLKREQ_4#
VDD_SRC_IO
CLKREQ_3#
1
C1190
0.1U_0402_16V4Z
2
R972
1 2
0_0805_5%
R977 0_0402_5%
R979 0_0402_5%
R981 0_0402_5%
+3VS_CK505
54
53
52
51
SRC_10#
50
SRC_10
49
48
SRC_11
47
SRC_11#
46
45
SRC_9#
44
SRC_9
43
42
VSS_SRC
41
40
SRC_4#
39
SRC_4
38
37
2
1
C1191
0.1U_0402_16V4Z
2
1
C1198
2
10U_0805_10V4Z
1 2
1 2
1 2
+1.05VS_CK505
H_STP_PCI#
H_STP_CPU#
R_PCIE_SATA
R_PCIE_SATA#
R_CLKSATAREQ#
R_CLK_PCIE_LAN#
R_CLK_PCIE_LAN
R_CLKREQ#_GLAN
R_CLK_PCIE_MCARD#
1
C1192
0.1U_0402_16V4Z
2
Place close to U55
0.1U_0402_16V4Z
1
C1199
2
0.1U_0402_16V4Z
MEDIA_REQ#32 29
CLK_PCIE_MEDIA 29
CLK_PCIE_MEDIA# 29
EXPCARD_REQ#16 25
CLK_PCIE_EXPR 25
CLK_PCIE_EXPR# 25
R992 0_0402_5%
R994 0_0402_5%
R995 0_0402_5%
R996 0_0402_5%
R997 0_0402_5%
R1005 0_0402_5%
R1007 0_0402_5%
1
C1200
2
H_STP_PCI# 19
H_STP_CPU# 19
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1
C1193
0.1U_0402_16V4Z
2
10U_0805_10V4Z
1
C1201
2
0.1U_0402_16V4Z
CardBus OZ888
Express Card
0.1U_0402_16V4Z
1
C1202
2
CPU_STP
1
1
C1194
0.1U_0402_16V4Z
2
+1.05VS_CK505
1
1
C1203
2
2
0.1U_0402_16V4Z
CLK_PCIE_SATA 18
CLK_PCIE_SATA# 18
CLKSATAREQ# 19
CLK_PCIE_LAN# 21
CLK_PCIE_LAN 21
GLAN_REQ#9 21
WLAN_REQ#4 23
CLK_PCIE_MCARD# 23
CLK_PCIE_MCARD 23
1
C1195
0.1U_0402_16V4Z
2
C1204
ICH_SATA
GLAN
MiniCard_WLAN
VDD_4819USB_0/FS_A20USB_1/CLKREQ_A#21VSS_4822VDD_IO23SRC_0/DOT_96
SRC_0#/DOT_96#
VSS_IO26VDD_PLL327LCDCLK/27M
+3VS_CK505
R1013 33_0402_1%
B B
CPU_BSEL25
A A
FSC
R1016
1 2
10K_0402_5%
ITP_EN
27_SEL
PCI2_TME
5
1 2
R1017
1K_0402_5%
ITP_EN
12
R1032
10K_0402_5%
MCH_CLKSEL2 7
0 = SRC8/SRC8#
*
1 = ITP/ITP#
0 = Enable DOT96 & SRC1(UMA)
*
1 = Enable SRC0 & 27MHz(DIS)
0 = Overclocking of CPU and SRC Allowed
1 = Overclocking of CPU and SRC NOT allowed
*
27_SEL
12
R1033
10K_0402_5%
+3VS_CK505
1 2
PCI2_TME
R1031
10K_0402_5%
CLK_48M_ICH19
CLKREQ#_77
CLK_MCH_DREFCLK7
CLK_MCH_DREFCLK#7
4
1 2
R1014 0_0402_5%
1 2
R1019 0_0402_5%
R1021 0_0402_5%
12
12
http://laptop-motherboard-schematic.blogspot.com/
FSA
R_CLKREQ#_7
+1.05VS_CK505
R_MCH_DREFCLK
R_MCH_DREFCLK#
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
24
25
LCDCLK#/27M_SS29VSS_PLL330VDD_PLL3_IO31SRC_232SRC_2#33VSS_SRC34SRC_335SRC_3#
28
S IC ICS9LPRS397AKLFT MLF 72P CLK GEN
36
R_PCIE_ICH#
R_PCIE_ICH
R_MCH_3GPLL#
R_MCH_3GPLL
+1.05VS_CK505
SSCDREFCLK#
SSCDREFCLK
Compal Secret Data
Deciphered Date
R1010 0_0402_5%
1 2
R1012 0_0402_5%
1 2
R1015 0_0402_5%
1 2
R1018 0_0402_5%
1 2
R1022 0_0402_5%
1 2
R1023 0_0402_5%
1 2
2
CLK_PCIE_ICH# 19
CLK_PCIE_ICH 19
CLK_MCH_3GPLL# 7
CLK_MCH_3GPLL 7
MCH_SSCDREFCLK# 7
MCH_SSCDREFCLK 7
EXPCARD_REQ#16
MEDIA_REQ#32
CLKSATAREQ#
GLAN_REQ#9
WLAN_REQ#4
CLKREQ#_7
Title
Size Document Number Rev
Date: Sheet
ICH9
NB_3GPLL
GMCH_27M (UMA)
+3VS
1 2
R90 10K_0402_5%
1 2
R97 10K_0402_5%
1 2
R88 10K_0402_5%
1 2
R87 10K_0402_5%
1 2
R85 10K_0402_5%
1 2
R60 10K_0402_5%
Compal Electronics, Inc.
Clock Generator CK505
LA-4592P
15 43Thursday, February 19, 2009
1
of
0.2
Page 16
A
C R T
1 1
MSEN#26
CRT_R9
CRT_G9
CRT_B9
2 2
MSEN#
CRT_R
CRT_G
CRT_B
12
12
R65
R64
150_0402_1%
150_0402_1%
1 2
C52 0.1U_0402_10V4Z
CRT_HSYNC_B
CRT_HSYNC9
CRT_VSYNC9
12
R631 0_0402_5%
CRT_VSYNC_B
12
R632 0_0402_5%
1
12
@
C45
R63
C46
2
150_0402_1%
22P_0402_50V8J
+CRT_VCC
1
5
P
4
OE#
A2Y
G
U62
74AHCT1G125GW_SOT353-5
3
1 2
C115 0.1U_0402_10V4Z
@
22P_0402_50V8J
1
C47
2
@
22P_0402_50V8J
+CRT_VCC
1
2
B
For NVidia
1 2
L8
BK1608LL121-T 0603
1 2
L10
BK1608LL121-T 0603
1 2
L14
BK1608LL121-T 0603
For EMI
R62 10K_0402_5%
D_CRT_HSYNC
1
5
P
D_CRT_VSYNC
4
OE#
A2Y
G
U63
74AHCT1G125GW_SOT353-5
3
+5VS
CRT_R_L
CRT_G_L
CRT_B_L
1
C48
2
4.7P_0402_50V8C
12
D11
DAN217_SC59-3
1
2
3
@
1
C49
2
4.7P_0402_50V8C
1 2
L11 0_0603_5%
L13 0_0603_5%
D18
DAN217_SC59-3
1
2
3
@
C50
4.7P_0402_50V8C
1 2
DAN217_SC59-3
1
2
D20
1
2
3
@
HSYNC_L
VSYNC_L
1
C55
2
15P_0402_50V8J
+5VS
F1
@
1.1A_6VDC_FUSE
R1496
0_1206_5%~D
1
C144
2
15P_0402_50V8J
21
12
C51
1
C53
2
100P_0402_50V8J
C
W=40mils
D14
2 1
RB411DT146 SOT23
0.1U_0402_10V4Z
DDC_MD2
1
2
1
100P_0402_50V8J
C54
2
@
C43
VGA_DDC_CLK_C
1
100P_0402_50V8J
C140
2
@
+CRT_VCC
W=40mils
1
2
VGA_DDC_DATA_C
100P_0402_50V8J
1
C44
2
@
0.1U_0402_10V4Z
JCRT1
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
SUYIN_070549FR015S208CR
CONN@
D
+3VS+CRT_VCC +3VS+CRT_VCC +3VS
4
原本為
.7K
VGA_DDC_DATA_C
VGA_DDC_CLK_C
16
17
R6
R7
1 2
2K_0402_5%
SSM3K7002FU_SC70-3
1 2
2K_0402_5%
Q3
1 3
D
SSM3K7002FU_SC70-3
2
Q5
R77
G
S
1 3
D
2
1 2
2.2K_0402_5%
G
S
R103
1 2
2.2K_0402_5%
E
3VDDCDA 9
3VDDCCL 9
Close to VGA
+3VS
21
21
LCD_TST
EC_SMB_DA2_R+B+
Deciphered Date
12
R21
4.7K_0402_5%
2
C32
1
0.1U_0603_50V4Z
D
DISPOFF#
LCD_CBL_DET# 26
LCD_TST 26
GMCH_EDID_DAT_LCD 9
GMCH_LVDSA0+ 9
GMCH_LVDSA1- 9
GMCH_LVDSA2+ 9
GMCH_LVDSAC- 9
GMCH_LVDSB0+ 9
GMCH_LVDSB1- 9
GMCH_LVDSB2+ 9
GMCH_LVDSBC- 9
+B+
2
C34
0.1U_0603_50V4Z
1
Compal Electronics, Inc.
Title
CRT CONN/LCD CONN
Size Document Number Rev
Custom
LA-4592P
Date: Sheet
E
16 43Thursday, February 19, 2009
of
0.2
L C D
+LCDVDD +5VALW
R49
1 2
13
R662
0_0402_5%
D
Q7
G
S
R92
12
1 2
R1502 0_0402_5%@
1 2
R1503 0_0402_5%@
3 3
GMCH_LVDDEN9
LCD_VCC_TEST_EN26
4 4
SSM3K7002FU_SC70-3
D9
2 1
CH751H-40PT_SOD323-2
EC_SMB_CK24,26
EC_SMB_DA24,26
R98
1 2
100_0603_1%
2
R54 1K_0402_5%
Q9
SSM3K7002FU_SC70-3
13
D
2
G
S
100K_0402_5%
EC_SMB_CK2_R
EC_SMB_DA2_R
47K_0402_5%
12
C180
0.047U_0402_16V7K
D59
1
PJSOT24C_SOT23-3
@
1
2
3
2
INVT_PWM
ESD EMI
A
W=60mils
+3VS
S
SI2301BDS-T1-E3 1P SOT23
G
Q6
2
D
1 3
1
C188
4.7U_0805_10V4Z
2
B
7.3
+LCDVDD
BKOFF#26
GMCH_ENBKL9,26
W=60mils
+LCDVDD
1
C41
0.1U_0402_10V4Z
2
DISPOFF#
INVT_PWM
DAC_BRIG
C4
C6
C3
100P_0402_25V8K
100P_0402_25V8K
100P_0402_25V8K
http://laptop-motherboard-schematic.blogspot.com/
+LCDVDD +LCDVDD
+3VS
GMCH_EDID_CLK_LCD9
GMCH_LVDSA0-9
GMCH_LVDSA1+9
GMCH_LVDSA2-9
GMCH_LVDSAC+9
GMCH_LVDSB0-9
GMCH_LVDSB1+9
GMCH_LVDSB2-9
GMCH_LVDSBC+9
INVT_PWM26
DAC_BRIG26
+3VS
2
C38
0.1U_0402_16V4Z
1
@
C
BKOFF#
GMCH_ENBKL
GMCH_EDID_CLK_LCD
GMCH_LVDSA0-
GMCH_LVDSA1+ GMCH_LVDSA1GMCH_LVDSA2-
GMCH_LVDSAC+
GMCH_LVDSB0-
GMCH_LVDSB1+ GMCH_LVDSB1GMCH_LVDSB2-
GMCH_LVDSBC+ GMCH_LVD SBCEC_SMB_CK2_R
INVT_PWM
DAC_BRIG
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
R652
100K_0402_5%
@
JLVDS1
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
GND41GND
ACES_88242-4001
2007/1/15 2008/1/15
2
2
4
4
6
6
GMCH_EDID_DAT_LCD
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
D26
CH751H-40_SC76
D25
CH751H-40_SC76@
LCD_CBL_DET#
GMCH_LVDSA0+
GMCH_LVDSA2+
GMCH_LVDSAC-
GMCH_LVDSB0+
GMCH_LVDSB2+
+B+
DISPOFF#
Compal Secret Data
Page 17
5
+3VS
R1035 8.2K_0402_5%
1 2
R1036 8.2K_0402_5%
1 2
R1037 8.2K_0402_5%
1 2
R1038 8.2K_0402_5%
1 2
R1039 8.2K_0402_5%
D D
C C
B B
1 2
R1040 8.2K_0402_5%
1 2
R1041 8.2K_0402_5%
1 2
R1042 8.2K_0402_5%
1 2
+3VS
R1043 8.2K_0402_5%
1 2
R1044 8.2K_0402_5%
1 2
R1045 8.2K_0402_5%
1 2
R1046 8.2K_0402_5%
1 2
R1047 8.2K_0402_5%
1 2
R1048 8.2K_0402_5%
1 2
R1049 8.2K_0402_5%
1 2
R1050 8.2K_0402_5%
R1051 8.2K_0402_5%
R1052 8.2K_0402_5%
R1053 8.2K_0402_5%
R1054 8.2K_0402_5%
12
1 2
1 2
1 2
1 2
A16 swap override Strap
PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#
Low= A16 swap override Enble
PCI_GNT3#
PCI_GNT3#
High= Default
R1431
@
1 2
1K_0402_5%
*
4
PCI_PIRQA#
PCI_PIRQB# PCI_PIRQF#
PCI_PIRQC#
PCI_PIRQD# PCI_PIRQH#
Boot BIOS Strap
PCI_GNT0# SPI_CS#1
0
1
1
SPI_CS1#_R19
0
1
SPI_CS1#_R
PCI_GNT0#
U56B
D11
AD0
C8
D9
E12
E9
C9
E10
B7
C7
C5
G11
F8
F11
E7
A3
D2
F10
D5
D10
B3
F7
C3
F3
F4
C1
G7
H7
D1
G5
H6
G1
H3
J5
E1
J6
C4
PCI
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
Interrupt I/F
PIRQA#
PIRQB#
PIRQC#
PIRQD#
ICH9M REV 1.0
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
Boot BIOS Location
SPI1
PCI
LPC
*
R1058
@
1 2
1K_0402_5%
R1060
@
1 2
1K_0402_5%
REQ0#
GNT0#
C/BE0#
C/BE1#
C/BE2#
C/BE3#
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
PLTRST#
PCICLK
PME#
+3VALW
3
PCI_REQ0#
F1
PCI_GNT0#
G4
PCI_REQ1#
B6
A7
PCI_REQ2#
F13
F12
PCI_REQ3#
E6
PCI_GNT3#
F6
D8
B4
D6
A5
PCI_IRDY#
D3
E3
PCI_PCIRST#
R1
PCI_DEVSEL#
C6
PCI_PERR#
E4
PCI_PLOCK#
C2
PCI_SERR#
J4
PCI_STOP#
A4
PCI_TRDY#
F5
PCI_FRAME#
D7
PCI_PLTRST#
C14
PCI_CLK
D4
R2
H4
K6
F2
G2
EC_PME#
PCI_PIRQE#
PCI_PIRQG#
C2
12
R10 33_0402_5%@
@
22P_0402_50V8J
1 2
PCI_CLK 15
EC_PME# 26
PCI_CLK
PCI_PCIRST#
0.1U_0402_10V4Z
PCI_PLTRST#
2
C1810
@
0.1U_0402_10V4Z
R1067
0_0402_5%
C1808
@
R1061
0_0402_5%
+3VALW
1
2
5
@
2
P
B
1
A
G
MC74VHC1G08DFT2G SC70 5P
3
12
+3VALW
1
2
5
U58
@
2
P
B
Y
1
A
G
MC74VHC1G08DFT2G SC70 5P
3
12
U59
Y
4
PCI_RST#
4
PLT_RST#
1
PCI_RST# 21,23,25,27
PLT_RST# 7,26,29
A A
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
http://laptop-motherboard-schematic.blogspot.com/
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
2
Date: Sheet
Compal Electronics, Inc.
ICH9(1/4)-PCI/INT
LA-4592P
17 43Thursday, February 19, 2009
1
0.2
of
Page 18
5
4
3
2
1
+RTCVCC
1 2
R1062 1M_0402_5%
1 2
R1064 332K_0402_1%~D
1 2
R1065 332K_0402_1%~D
D D
R1069
C C
C1211
12P_0402_50V8J
B B
1
2
1 2
10M_0402_5%
1
IN
2
SM_INTRUDER#
LAN100_SLP
ICH_INTVRMEN
1U_0603_10V4Z
ICH_RTCX1
R1419
0_0402_5%
2
C1212
10P_0402_50V8J
1
4
OUT
Y8
32.768KHZ QTFM28-32768K125P10L
NC3NC
HDD
ODD
+RTCVCC
1 2
R1068 20K_0402_5%
1 2
R1109 20K_0402_5%
C1220
1
JOPEN2
@
1U_0603_10V4Z
1 2
2
C1210
1
1 2
2
Close JOPEN1 and JOPEN2 near JMINI1
12
ICH_RTCX2
ACZ_BITCLK24
ACZ_SYNC24
ACZ_RST#24
ADC_ACZ_SDIN024
ACZ_SDOUT24
PSATA_IRX_DTX_N0_C22
PSATA_IRX_DTX_P0_C22
PSATA_ITX_DRX_N022
PSATA_ITX_DRX_P022
ODD_IRX_DTX_N0_C22
ODD_IRX_DTX_P0_C22
ODD_ITX_DRX_N022
ODD_ITX_DRX_P022
SATA_LED#27
+1.5VS
1 2
+3VS
R1080 10K_0402_5%
PSATA_ITX_DRX_N0
PSATA_ITX_DRX_P0
ODD_ITX_DRX_N0
ODD_ITX_DRX_P0
R1073 24.9_0402_1%
R1074 33_0402_5%
R1076 33_0402_5%
R1077 33_0402_5%
R1079 33_0402_5%
JOPEN1
@
1 2
1 2
1 2
1 2
1 2
T123PAD
T124PAD
ICH_RTCX1
ICH_RTCX2
ICH_RTCRST#
SRTCRST#
SM_INTRUDER#
ICH_INTVRMEN
LAN100_SLP
GLAN_COMP
HDA_BITCLK
HDA_SYNC
HDARST#
HDA_SDIN0
HDA_SDOUT
SATA_LED#
U56A
C23
RTCX1
C24
RTCX2
A25
RTCRST#
F20
SRTCRST#
C22
INTRUDER#
B22
INTVRMEN
A22
LAN100_SLP
E25
GLAN_CLK
C13
LAN_RSTSYNC
F14
LAN_RXD0
G13
LAN_RXD1
D14
LAN_RXD2
D13
LAN_TXD0
D12
LAN_TXD1
E13
LAN_TXD2
B10
GPIO56
B28
GLAN_COMPI
B27
GLAN_COMPO
AF6
HDA_BIT_CLK
AH4
HDA_SYNC
AE7
HDA_RST#
AF4
HDA_SDIN0
AG4
HDA_SDIN1
AH3
HDA_SDIN2
AE5
HDA_SDIN3
AG5
HDA_SDOUT
AG7
HDA_DOCK_EN#/GPIO33
AE8
HDA_DOCK_RST#/GPIO34
AG8
SATALED#
AJ16
SATA0RXN
AH16
SATA0RXP
AF17
SATA0TXN
AG17
SATA0TXP
AH13
SATA1RXN
AJ13
SATA1RXP
AG14
SATA1TXN
AF14
SATA1TXP
ICH9M REV 1.0
RTCLAN / GLANIHDASATA
LPCCPU
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
FWH4/LFRAME#
LDRQ0#
LDRQ1#/GPIO23
A20GATE
A20M#
DPRSTP#
DPSLP#
FERR#
CPUPWRGD
IGNNE#
INIT#
INTR
RCIN#
SMI#
STPCLK#
THRMTRIP#
TP12
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATA_CLKN
SATA_CLKP
SATARBIAS#
SATARBIAS
GATEA20
KB_RST#
LPC_AD0
K5
LPC_AD1
K4
LPC_AD2
L6
LPC_AD3
K2
LPC_FRAME#
K3
LPC_DRQ0#
J3
J1
GATEA20
N7
H_A20M#
AJ27
H_DPRSTP#
AJ25
H_DPSLP#
AE23
R_H_FERR#
AJ26
H_PWRGOOD
AD22
H_IGNNE#
AF25
H_INIT#
AE22
H_INTR
AG25
KB_RST#
L3
H_NMI
AF23
NMI
H_SMI#
AF24
H_STPCLK#
AH27
THRMTRIP_ICH#
AG26
AG27
AH11
AJ11
AG12
AF12
AH9
AJ9
AE10
AF10
CLK_PCIE_SATA#
AH18
CLK_PCIE_SATA
AJ18
AJ7
R1081
AH7
1 2
24.9_0402_1%
Within 500 mils
LPC_AD[0..3] 23,26,27
LPC_FRAME# 23,26,27
T121 PAD
T122 PAD
GATEA20 26
H_A20M# 4
R1072
1 2
H_PWRGOOD 5
H_IGNNE# 4
H_INIT# 4
H_INTR 4
KB_RST# 26
H_NMI 4
H_SMI# 4
H_STPCLK# 4
R1078 54.9_0402_1%
1 2
H_FERR#
56_0402_5%
CLK_PCIE_SATA# 15
CLK_PCIE_SATA 15
+VCCP
1 2
1 2
H_DPRSTP# 5,7,39
H_DPSLP# 5
12
R1075
56_0402_5%
+3VS
R1063
8.2K_0402_5%
R1066
10K_0402_5%
+VCCP
R1070
56_0402_5%
1 2
H_THERMTRIP# 4,7
H_FERR# 4
XOR CHAIN ENTRANCE STRAP:RSVD
+3VS
R1082
@
1 2
1K_0402_5%
R1083
@
1 2
1K_0402_5%
A A
ICH_RSVD
5
ACZ_SDOUT
ICH_RSVD 19
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
http://laptop-motherboard-schematic.blogspot.com/
MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
ICH9(2/4)_LAN,HD,IDE,LPC
LA-4592P
1
0.2
of
18 43Thursday, February 19, 2009
Page 19
5
1 2
1 2
1 2
SERIRQ
PCI_CLKRUN#
EC_THERM#
OCP#
PM_BMBUSY#
EC_SCI#
ICH8 don't have
LAN_CABDT
SB_SPKR
GPIO49
+3VALW
ICH_PCIE_WAKE#21,23,25,26
R1085 2.2K_0402_5%
R1087 2.2K_0402_5%
ICH_SMBCLK25
ICH_SMBDATA25
ICH_PCIE_W AKE# ICH_PCIE_WAKE#_R
VGATE7,26,39
R1102 100K_0402_5%
+3VS
D D
+3VS
1 2
R1084 10K_0402_5%
1 2
R1086 8.2K_0402_5%
1 2
R1088 8.2K_0402_5%@
1 2
R1090 10K_0402_5%
1 2
R1094 8.2K_0402_5%@
1 2
R1095 8.2K_0402_5%@
R313 10K_0402_5%
R1096 10K_0402_5% @
low-->default
High -->No boot
+3VS
R1101 10K_0402_5%@
checklist pull hi
C C
+3VALW
B B
A A
R1108 10K_0402_5%
R1110 8.2K_0402_5%
R1111 10K_0402_5%
R1113 10K_0402_5%
R1114 10K_0402_5%
R1115 10K_0402_5%
R1116 10K_0402_5%
R1117 10K_0402_5%
R1119 8.2K_0402_5%
+3VALW
R1483 10K_0402_5%
R1484 10K_0402_5%
R1485 10K_0402_5%
R1486 10K_0402_5%
R1487 10K_0402_5%
R1488 10K_0402_5%
R1489 10K_0402_5%
R1490 10K_0402_5%
R1492 10K_0402_5%
R1493 10K_0402_5%
R1494 10K_0402_5%
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
CL_RST#1
ICH_LOW_BAT#
ICH_PCIE_WAKE#_R
ICH_RI#
XDP_DBRESET#
ME_EC_CLK1
ME_EC_DATA1
EC_LID_OUT#
EC_SMI#
EC_SWI#
USB_OC#1
USB_OC#2_8
USB_OC#4
USB_OC#7
USB_OC#3
USB_OC#9
USB_OC#0
USB_OC#5
USB_OC#10
USB_OC#11
5
SB_SPKR24
GLAN
WLAN
Express Card
CardBus
+3VS
12
12
2.2K_0402_5%
R11232.2K_0402_5%
R1124
ICH_SM_DA13,14,15,23
ICH_SM_CLK13,14,15,23
+3VS
S
G
2
4
1 2
1 2
XDP_DBRESET#4
PM_BMBUSY#7
EC_LID_OUT#26
H_STP_PCI#15
H_STP_CPU#15
PCI_CLKRUN#26,27
@
SERIRQ26,27
EC_THERM#26
1 2
@
LAN_LOPWEN21
CLKSATAREQ#15
MCH_ICH_SYNC#7
ICH_RSVD18
GLAN_RXN21
GLAN_RXP21
GLAN_TXN21
GLAN_TXP21
PCIE_RXN323
PCIE_RXP323
PCIE_TXN323
PCIE_TXP323
PCIE_RXN425
PCIE_RXP425
PCIE_TXN425
PCIE_TXP425
PCIE_RXN529
PCIE_RXP529
PCIE_TXN529
PCIE_TXP529
SPI_CS1#_R17
Q106
SSM3K7002FU_SC70-3
D
ICH_SMBDATA
13
D
S
ICH_SMBCLK
13
G
Q107
2
SSM3K7002FU_SC70-3
4
T125PAD
R1505
0_0402_5%
1 2
R1099 0_0402_5%
T128PAD
OCP#4
EC_SMI#26
EC_SCI#26
T130PAD
T149PAD
T131PAD
T132PAD
T133PAD
T134PAD
T135PAD
ICH_SMBCLK
ICH_SMBDATA
CL_RST#1
ME_EC_CLK1
ME_EC_DATA1
ICH_RI#
SUS_STAT#
XDP_DBRESET#
PM_BMBUSY#
EC_LID_OUT#
H_STP_PCI#
R_STP_CPU#
PCI_CLKRUN#
12
SERIRQ
EC_THERM#
VRMPWRGD
OCP#
LAN_LOPWEN
EC_SMI#
EC_SCI#
CLKSATAREQ#
GPIO49
SB_SPKR
MCH_ICH_SYNC#
ICH_RSVD
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
0.1U_0402_16V7K~N
USB_OC#028
USB_OC#2_828
EC_SWI#26
USB_OC#928
3
U56C
G16
SMBCLK
A13
SMBDATA
E17
LINKALERT#/GPIO60/CLGPIO4
C17
SMLINK0
B18
SMLINK1
F19
RI#
R4
SUS_STAT#/LPCPD#
G19
SYS_RESET#
M6
PMSYNC#/GPIO0
A17
SMBALERT#/GPIO11
A14
STP_PCI#
E19
STP_CPU#
L4
CLKRUN#
E20
WAKE#
M5
SERIRQ
AJ23
THRM#
D21
VRMPWRGD
A20
TP11
AG19
GPIO1
AH21
GPIO6
AG21
GPIO7
A21
GPIO8
C12
GPIO12
C21
GPIO13
AE18
GPIO17
K1
GPIO18
AF8
GPIO20
AJ22
SCLOCK/GPIO22
A9
GPIO27
D19
GPIO28
L1
SATACLKREQ#/GPIO35
AE19
SLOAD/GPIO38
AG22
SDATAOUT0/GPIO39
AF21
SDATAOUT1/GPIO48
AH24
GPIO49
A8
GPIO57/CLGPIO5
M7
SPKR
AJ24
MCH_SYNC#
B21
TP3
AH20
TP8
AJ20
TP9
AJ21
TP10
C12210.1U_0402_16V7K~N
12
C12220.1U_0402_16V7K~N
12
C12230.1U_0402_16V7K~N
12
C12240.1U_0402_16V7K~N
12
C1225
12
C1226
12
C1228
12
C1227
12
12
Within 500 mils
R1125
22.6_0402_1%
ICH9M REV 1.0
GLAN_RXN
GLAN_RXP
GLAN_TXN_C
GLAN_TXP_C
PCIE_RXN3
PCIE_RXP3
PCIE_C_TXN3
PCIE_C_TXP3
PCIE_RXN4
PCIE_RXP4
PCIE_C_TXN4
PCIE_C_TXP4
PCIE_RXN5
PCIE_RXP5
PCIE_C_TXN5
PCIE_C_TXP5
SPI_CS1#_R
USB_OC#0
USB_OC#1
USB_OC#2_8
USB_OC#3
USB_OC#4
USB_OC#5
EC_SWI#
USB_OC#7
USB_OC#2_8
USB_OC#9
USB_OC#10
USB_OC#11
USBRBIAS
U56D
N29
PERN1
N28
PERP1
P27
PETN1
P26
PETP1
L29
PERN2
L28
PERP2
M27
PETN2
M26
PETP2
J29
PERN3
J28
PERP3
K27
PETN3
K26
PETP3
G29
PERN4
G28
PERP4
H27
PETN4
H26
PETP4
E29
PERN5
E28
PERP5
F27
PETN5
F26
PETP5
C29
PERN6/GLAN_RXN
C28
PERP6/GLAN_RXP
D27
PETN6/GLAN_TXN
D26
PETP6/GLAN_TXP
D23
SPI_CLK
D24
SPI_CS0#
F23
SPI_CS1#/GPIO58/CLGPIO6
D25
SPI_MOSI
E23
SPI_MISO
N4
OC0#/GPIO59
N5
OC1#/GPIO40
N6
OC2#/GPIO41
P6
OC3#/GPIO42
M1
OC4#/GPIO43
N2
OC5#/GPIO29
M4
OC6#/GPIO30
M3
OC7#/GPIO31
N3
OC8#/GPIO44
N1
OC9#/GPIO45
P5
OC10#/GPIO46
P3
OC11#/GPIO47
AG2
USBRBIAS
AG1
USBRBIAS#
ICH9M REV 1.0
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
http://laptop-motherboard-schematic.blogspot.com/
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
SATA0GP/GPIO21
SATA1GP/GPIO19
SATA4GP/GPIO36
SATA5GP/GPIO37
SATA
GPIO
SMBSYS GP IO
Clocks
Power MGTController Link
GPIO
GPIO10/SUS_PWR_ACK
GPIO14/AC_PRESENT
CLK14
CLK48
SUSCLK
SLP_S3#
SLP_S4#
SLP_S5#
S4_STATE#/GPIO26
PWROK
DPRSLPVR/GPIO16
BATLOW#
PWRBTN#
LAN_RST#
RSMRST#
CK_PWRGD
CLPWROK
SLP_M#
CL_CLK0
CL_CLK1
CL_DATA0
CL_DATA1
CL_VREF0
CL_VREF1
CL_RST0#
CL_RST1#
MEM_LED/GPIO24
WOL_EN/GPIO9
MISC
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
DMI_CLKN
PCI-Express
DMI_CLKP
Direct Media Interface
DMI_ZCOMP
DMI_IRCOMP
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
SPI
USBP5P
USBP6N
USB
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
2006/02/13 2006/03/10
GPIO21
AH23
GPIO19
AF19
GPIO36
AE21
GPIO37
AD20
CLK_14M_ICH
H1
CLK_48M_ICH
AF3
ICH_SUSCLK
P1
SLP_S3#
C16
SLP_S4#
E16
SLP_S5#
G17
C10
ICH_PWROK
G20
M2
1 2
ICH_LOW_BAT#
B13
PWRBTN_OUT#
R3
D20
1 2
R1100 0_0402_5%
R_EC_RSMRST#
D22
CK_PWRGD_R
R5
M_PWROK
R6
B16
CL_CLK0
F24
B19
CL_DATA0
F22
C19
CL_VREF0_ICH
C25
A19
CL_RST#
F21
D18
A16
C18
C11
LAN_CABDT
C20
DMI_MTX_IRX_N0
V27
DMI_MTX_IRX_P0
V26
DMI_MRX_ITX_N0
U29
DMI_MRX_ITX_P0
U28
DMI_MTX_IRX_N1
Y27
DMI_MTX_IRX_P1
Y26
DMI_MRX_ITX_N1
W29
DMI_MRX_ITX_P1
W28
DMI_MTX_IRX_N2
AB27
DMI_MTX_IRX_P2
AB26
DMI_MRX_ITX_N2
AA29
DMI_MRX_ITX_P2
AA28
DMI_MTX_IRX_N3
AD27
DMI_MTX_IRX_P3
AD26
DMI_MRX_ITX_N3
AC29
DMI_MRX_ITX_P3
AC28
CLK_PCIE_ICH#
T26
CLK_PCIE_ICH
T25
AF29
DMI_IRCOMP
AF28
USB20_N0
AC5
USB20_P0
AC4
USB20_N1
AD3
USB20_P1
AD2
USB20_N2
AC1
USB20_P2
AC2
USB20_N3
AA5
USB20_P3
AA4
USB20_N4
AB2
USB20_P4
AB3
USB20_N5
AA1
USB20_P5
AA2
USB20_N6
W5
USB20_P6
W4
USB20_N7
Y3
USB20_P7
Y2
USB20_N8
W1
USB20_P8
W2
USB20_N9
V2
USB20_P9
V3
U5
U4
U1
U2
Compal Secret Data
Deciphered Date
R1089 8.2K_0402_5%
CLK_14M_ICH 15
CLK_48M_ICH 15
T126PAD
SLP_S3# 26
SLP_S4# 26
SLP_S5# 26
T127PAD
R10980_0402_5%
DPRSLPVR 7,39
PBTN_OUT# 26
R1104 10K_0402_5%
1 2
R1105 0_0402_5%
1 2
T129PAD
CL_CLK0 7
CL_DATA0 7
CL_RST# 7
ACIN 26,32,33
LAN_CABDT 21
DMI_MTX_IRX_N0 7
DMI_MTX_IRX_P0 7
DMI_MRX_ITX_N0 7
DMI_MRX_ITX_P0 7
DMI_MTX_IRX_N1 7
DMI_MTX_IRX_P1 7
DMI_MRX_ITX_N1 7
DMI_MRX_ITX_P1 7
DMI_MTX_IRX_N2 7
DMI_MTX_IRX_P2 7
DMI_MRX_ITX_N2 7
DMI_MRX_ITX_P2 7
DMI_MTX_IRX_N3 7
DMI_MTX_IRX_P3 7
DMI_MRX_ITX_N3 7
DMI_MRX_ITX_P3 7
CLK_PCIE_ICH# 15
CLK_PCIE_ICH 15
R1120 24.9_0402_1%
1 2
USB20_N0 28
USB20_P0 28
USB20_N1 28
USB20_P1 28
USB20_N2 28
USB20_P2 28
USB20_N3 28
USB20_P3 28
USB20_N4 28
USB20_P4 28
USB20_N5 28
USB20_P5 28
USB20_N6 23
USB20_P6 23
USB20_N7 25
USB20_P7 25
USB20_N8 28
USB20_P8 28
USB20_N9 28
USB20_P9 28
2
1 2
R695 100_0402_5%
2
+3VS
1 2
ICH_PWROK 7,26
R1097 10K_0402_5%
EC_RSMRST#26
Within 500 mils
+1.5VS
JUSBP1
Camera
JUSBP3
Felica
BlueTooth
FingerPrinter
Mini Card 2
Express Card
JUSBP3
JUSBP4
1
12
@
R1091
10_0402_5%
@
1
C1217
4.7P_0402_50V8C
2
M_PWROK
1 2
CK_PWRGD 15
M_PWROK 7
0.1U_0402_16V4Z
1
C1219
2
12
1 2
R1107
453_0402_1%
NA lead free
R1106
3.24K_0402_1%
RSMRST circuit
@
R1103
0_0402_5%
1 2
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
ICH9(3/4)_DMI,USB,GPIO,PCIE
LA-4592P
1 2
1
Place clos ely pin H1Place closely pin AF3
CLK_14M_ICHCLK_48M_ICH
12
@
R1092
10_0402_5%
@
1
C1218
4.7P_0402_50V8C
2
R656
0_0402_5%
R_EC_RSMRST#
19 43Thursday, February 19, 2009
+3VS
POK 34
0.2
of
Page 20
5
+RTCVCC
1
C1229
2
L96
1 2
+1.5VS
D D
100_0402_5%~D
100_0402_5%~D
C C
B B
+3VS
C1268
A A
0.1U_0402_16V4Z
BLM21PG600SN1D_0805~D
+5VS +3VS
21
12
R1127
1
2
+3VALW+5VALW
12
21
D46
R1128
1
2
L99
10UH_LB2012T100MR_20%_0805~D
1 2
+1.5VS
1
+1.5VS
2
L100
1UH_20%_0805~D
D45
CH751H-40PT_SOD323-2
C1241
1U_0603_10V6K~D
CH751H-40PT_SOD323-2
C1306
1U_0603_10V6K~D
1 2
0.1U_0402_16V4Z
C1234
220U_D2_4VM
22U_0805_6.3V6M~D
+ICH_V5REF_RUN
20 mils
+ICH_V5REF_SUS
20 mils
1
C1255
2
1U_0603_10V4Z
1 2
R1129 0_0603_5%
10U_0805_10V4Z
5
1
+
2
+VCCSATAPLL
1
2
20 mils
1U_0603_10V4Z~D
1
1
2
2
0.1U_0402_16V4Z
22U_0805_6.3V6M~D
1
C1236
2
2.2U_0603_6.3V4Z
C1231
1
C1237
2
C1230
40 mils
+VCC1_5_B
C1235
0.1U Change to 1U
+1.5VS
C1254
C1269
1
2
+1.5VS
10U_0805_10V4Z
+1.5VS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C1267
0.1U_0402_16V4Z~D
2.2U_0603_6.3V4Z
1U_0603_10V4Z
+1.5VS
1U_0603_10V4Z
1 2
+VCCGLANPLL
1
C1270
2
C1256
C1258
C1262
C1263
+VCCLAN3_3
G3: 6uA
+ICH_V5REF_RUN
+ICH_V5REF_SUS
646mA
1
2
1
2
1
2
1342mA
1
2
11mA
1
11mA
2
VCC_LAN1_05_INT_ICH_1
19/78/78mA
+1.5VS
1
C1271
2
4.7U_0603_6.3V6M~D
47mA
+3VS
2mA
2mA
23mA
80mA
1mA
AA24
AA25
AB24
AB25
AC24
AC25
AD24
AD25
AE25
AE26
AE27
AE28
AE29
M24
M25
W24
W25
AJ19
AC16
AD15
AD16
AE15
AF15
AG15
AH15
AJ15
AC11
AD11
AE11
AF11
AG10
AG11
AH10
AJ10
AC18
AC19
AC21
AC12
AC13
AC14
4
A23
A6
AE1
F25
G25
H24
H25
J24
J25
K24
K25
L23
L24
L25
N23
N24
N25
P24
P25
R24
R25
R26
R27
T24
T27
T28
T29
U24
U25
V24
V25
U23
K23
Y24
Y25
AC9
G10
G9
AJ5
AA7
AB6
AB7
AC6
AC7
A10
A11
A12
B12
A27
D28
D29
E26
E27
A26
4
U56F
VCCRTC
V5REF
V5REF_SUS
VCC1_5_B[1]
VCC1_5_B[2]
VCC1_5_B[3]
VCC1_5_B[4]
VCC1_5_B[5]
VCC1_5_B[6]
VCC1_5_B[7]
VCC1_5_B[8]
VCC1_5_B[9]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]
VCC1_5_B[47]
VCC1_5_B[48]
VCC1_5_B[49]
VCCSATAPLL
VCC1_5_A[1]
VCC1_5_A[2]
VCC1_5_A[3]
VCC1_5_A[4]
VCC1_5_A[5]
VCC1_5_A[6]
VCC1_5_A[7]
VCC1_5_A[8]
VCC1_5_A[9]
VCC1_5_A[10]
VCC1_5_A[11]
VCC1_5_A[12]
VCC1_5_A[13]
VCC1_5_A[14]
VCC1_5_A[15]
VCC1_5_A[16]
VCC1_5_A[17]
VCC1_5_A[18]
VCC1_5_A[19]
VCC1_5_A[20]
VCC1_5_A[21]
VCC1_5_A[22]
VCC1_5_A[23]
VCC1_5_A[24]
VCC1_5_A[25]
VCCUSBPLL
VCC1_5_A[26]
VCC1_5_A[27]
VCC1_5_A[28]
VCC1_5_A[29]
VCC1_5_A[30]
VCCLAN1_05[1]
VCCLAN1_05[2]
VCCLAN3_3[1]
VCCLAN3_3[2]
VCCGLANPLL
VCCGLAN1_5[1]
VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]
VCCGLAN3_3
ICH9M REV 1.0
CORE
VCCA3GP ATXARX USB CORE
VCCPSUSVCCPUSB
GLAN POWER
0.1U_0402_16V4Z
0.1U_0402_10V4Z
0.1U_0402_16V4Z
+3VS
3
1
C1232
2
0.01U_0402_16V7K
+VCC_DMI
0.1U_0402_10V4Z
1
+3VS
C1247
2
+3VS
C1249
0.1U_0402_10V4Z
C1248
1
1
2
2
T140
T141
T142
+3VALW
+3VALW
0.1U_0402_16V4Z~D
1
C1259
2
1
C1265 1U_0603_10V4Z
2
3
0.1U_0402_16V4Z
1
C1233
2
L97
1
C1239
10U_0805_10V4Z
2
5ohm@100MHz
1 2
L98
BLM18PG181SN1_0603~D
1
C1240
2
0.1U_0402_10V4Z
1
2
C1250
Add 0.1uF
1
2
+3VALW
0.022U_0402_16V7K~D
1
C1260
2
BLM18PG181SN1_0603~D
1 2
+3VS
C1245
1
C1252
2
1
2
C1261
1
C1264
0.1U_0402_10V4Z
2
+VCCDMIPLL
1
C1238
2
22U_0805_6.3VAM
0.1U_0402_10V4Z
0.1U_0402_16V4Z
1
C1253
2
0.022U_0402_16V7K~D
1
2
1
C1266 0.1U_0402_16V4Z~D
2
2006/02/13 2006/03/10
+VCCP
1634mA
A15
VCC1_05[1]
B15
VCC1_05[2]
C15
VCC1_05[3]
D15
VCC1_05[4]
E15
VCC1_05[5]
F15
VCC1_05[6]
L11
VCC1_05[7]
L12
VCC1_05[8]
L14
VCC1_05[9]
VCCDMIPLL
VCC_DMI[1]
VCC_DMI[2]
VCC3_3[1]
VCC3_3[2]
VCC3_3[7]
VCC3_3[3]
VCC3_3[4]
VCC3_3[5]
VCC3_3[6]
VCC3_3[8]
VCC3_3[9]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]
VCC3_3[14]
VCCHDA
VCCCL1_05
VCCCL1_5
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
R29
23mA
W23
Y23
48mA
AB23
AC23
2mA
AG29
AJ6
AC10
AD19
AF20
AG24
AC20
308mA
B9
F9
G3
G6
J2
J7
K7
AJ4
11mA
AJ3
11mA
AC8
F17
+VCCSUS1_5_ICH_1
AD8
+VCCSUS1_5_ICH_2
F18
A18
D16
D17
E22
AF1
212mA
T1
T2
T3
T4
T5
T6
U6
U7
V6
V7
W6
W7
Y6
Y7
T7
+VCCCL1_05_ICH_1
G22
+VCCCL1_5
G23
19/73/73mA
A24
B24
0.1U_0402_10V4Z
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]
V_CPU_IO[1]
V_CPU_IO[2]
VCCP_CORE
PCI
VCCSUSHDA
VCCSUS1_05[1]
VCCSUS1_05[2]
VCCSUS1_5[1]
VCCSUS1_5[2]
VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCCSUS3_3[6]
VCCSUS3_3[7]
VCCSUS3_3[8]
VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
VCCCL3_3[1]
VCCCL3_3[2]
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
http://laptop-motherboard-schematic.blogspot.com/
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+VCCP
+VCCP
4.7U_0603_6.3V6M
+3VS
1
C1246
2
+3VS
T143
C1257
0.1U_0402_10V4Z
T144
Compal Secret Data
Deciphered Date
2
+1.5VS
0.1U_0402_10V4Z
0.1U_0402_10V4Z
C1242
1
2
C1244
C1243
1
1
2
2
(DMI)
Title
Size Document Number Rev
Custom
2
Date: Sheet
U56E
AA26
VSS[1]
AA27
VSS[2]
AA3
VSS[3]
AA6
VSS[4]
AB1
VSS[5]
AA23
VSS[6]
AB28
VSS[7]
AB29
VSS[8]
AB4
VSS[9]
AB5
VSS[10]
AC17
VSS[11]
AC26
VSS[12]
AC27
VSS[13]
AC3
VSS[14]
AD1
VSS[15]
AD10
VSS[16]
AD12
VSS[17]
AD13
VSS[18]
AD14
VSS[19]
AD17
VSS[20]
AD18
VSS[21]
AD21
VSS[22]
AD28
VSS[23]
AD29
VSS[24]
AD4
VSS[25]
AD5
VSS[26]
AD6
VSS[27]
AD7
VSS[28]
AD9
VSS[29]
AE12
VSS[30]
AE13
VSS[31]
AE14
VSS[32]
AE16
VSS[33]
AE17
VSS[34]
AE2
VSS[35]
AE20
VSS[36]
AE24
VSS[37]
AE3
VSS[38]
AE4
VSS[39]
AE6
VSS[40]
AE9
VSS[41]
AF13
VSS[42]
AF16
VSS[43]
AF18
VSS[44]
AF22
VSS[45]
AH26
VSS[46]
AF26
VSS[47]
AF27
VSS[48]
AF5
VSS[49]
AF7
VSS[50]
AF9
VSS[51]
AG13
VSS[52]
AG16
VSS[53]
AG18
VSS[54]
AG20
VSS[55]
AG23
VSS[56]
AG3
VSS[57]
AG6
VSS[58]
AG9
VSS[59]
AH12
VSS[60]
AH14
VSS[61]
AH17
VSS[62]
AH19
VSS[63]
AH2
VSS[64]
AH22
VSS[65]
AH25
VSS[66]
AH28
VSS[67]
AH5
VSS[68]
AH8
VSS[69]
AJ12
VSS[70]
AJ14
VSS[71]
AJ17
VSS[72]
AJ8
VSS[73]
B11
VSS[74]
B14
VSS[75]
B17
VSS[76]
B2
VSS[77]
B20
VSS[78]
B23
VSS[79]
B5
VSS[80]
B8
VSS[81]
C26
VSS[82]
C27
VSS[83]
E11
VSS[84]
E14
VSS[85]
E18
VSS[86]
E2
VSS[87]
E21
VSS[88]
E24
VSS[89]
E5
VSS[90]
E8
VSS[91]
F16
VSS[92]
F28
VSS[93]
F29
VSS[94]
G12
VSS[95]
G14
VSS[96]
G18
VSS[97]
G21
VSS[98]
G24
VSS[99]
G26
VSS[100]
G27
VSS[101]
G8
VSS[102]
H2
VSS[103]
H23
VSS[104]
H28
VSS[105]
H29
VSS[106]
ICH9M REV 1.0
Compal Electronics, Inc.
ICH9(4/4)_POWER&GND
LA-4592P
1
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS_NCTF[1]
VSS_NCTF[2]
VSS_NCTF[3]
VSS_NCTF[4]
VSS_NCTF[5]
VSS_NCTF[6]
VSS_NCTF[7]
VSS_NCTF[8]
VSS_NCTF[9]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]
1
H5
J23
J26
J27
AC22
K28
K29
L13
L15
L2
L26
L27
L5
L7
M12
M13
M14
M15
M16
M17
M23
M28
M29
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
P12
P13
P14
P15
P16
P17
P2
P23
P28
P29
P4
P7
R11
R12
R13
R14
R15
R16
R17
R18
R28
T12
T13
T14
T15
T16
T17
T23
B26
U12
U13
U14
U15
U16
U17
AD23
U26
U27
U3
V1
V13
V15
V23
V28
V29
V4
V5
W26
W27
W3
Y1
Y28
Y29
Y4
Y5
AG28
AH6
AF2
B25
A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29
20 43Thursday, February 19, 2009
0.2
of
Page 21
5
Q128
D
6
S
1U_0603_10V6K
+B+_BIAS
D D
EN_WOL#26
2
G
R1239
470K_0402_5%
1 2
13
D
Q58
SSM3K7002FU_SC70-3
S
2
EN_WOL
1
C1455
45
2
1
SI3456BDV-T1-E3 1N TSOP6
G
3
R1240
1.5M_0402_5%
@
1 2
1
2
4
+LAN_IO
C1456
@
22U_1206_6.3V6M
3
W=60milsW=60mils
+LAN_IO+3VALW
1.5A
1
1
C1457
C1458
2
2
22U_1206_6.3V6M
0.1U_0402_10V7K~N
1
C1459
2
0.1U_0402_10V7K~N
1
C1460
2
0.1U_0402_10V7K~N
+LAN_VDD
1 2
These caps close to U64: Pin 44, 45
R1238
0_0603_5%
2
+LAN_VDD12
1
1
1
C14630.1U_0402_10V7K~N
C14640.1U_0402_10V7K~N
2
2
1
C14650.1U_0402_10V7K~N
C14660.1U_0402_10V7K~N
2
2
1
1
C14680.1U_0402_10V7K~N
C14670.1U_0402_10V7K~N
2
2
These caps close to U64: Pin 4,10,13, 30, 36,39
1
C1474
2
1
+LAN_IO
1
C1475
2
These caps close to U64: Pin 4
0_0603_5%
12
12
R953
1 2
220_0402_5%
@
C1817
220P_0402_50V7K
R1251
1 2
220_0402_5%
R1252
1 2
220_0402_5%
C1819
220P_0402_50V7K
Deciphered Date
+LAN_VDD
1
2
C1743
@
0.1U_0402_10V7K
0.01U_0402_16V7K
L110
12
LAN_ACTIVITY#LAN_LED0
+LAN_IO
1
2
220P_0402_50V7K
LINK_10_1000#
LINK_100_1000#
1
1
2
2
2
1
C1744
W=30mils
+LAN_VDD
1
@
C1818
2
+LAN_IO
C1820
220P_0402_50V7K
2
RJ45_TX3RJ45_TX3+
RJ45_RX1RJ45_TX2RJ45_TX2+
RJ45_RX1+
RJ45_TX0RJ45_TX0+
22U_1206_6.3V6M
0.1U_0402_10V7K~N
These caps close to U64: Pin 44,45
( Should be place within 200 mils )
JLAN1
13
Yellow LED-
12
Yellow LED+
8
PR4-
7
PR4+
6
PR2-
5
PR3-
4
PR3+
3
PR2+
2
PR1-
1
PR1+
11
Green LED-
9
Orange LED-
10
1
2
Green-Orange LED+
C-1775553
C1821
CONN@
220P_0402_50V7K
Title
Size Document Number Rev
Custom
Date: Sheet
Compal Electronics, Inc.
Gigabit LAN_RTL8111C
LA-4592P
GND
GND
15
14
1
0.2
of
21 43Thursday, February 19, 2009
+LAN_IO
W=60mils
L107
1
C1478
1 2
C1486 0.1U_0402_16V7K~N
1 2
C1487 0.1U_0402_16V7K~N
1 2
C1495 0.1U_0402_16V7K~N
1 2
C1496 0.1U_0402_16V7K~N
LED2_LED3
LED1_LED3
1
2
2
0.1U_0402_10V7K~N
L1080_0603_5%
2008/03/21 2009/03/21
+LAN_VDD
C1479
These components close to U64: Pin 48
( Should be place within 200 mils )
W=30mils
22U_1206_6.3V6M
C1484 1U_0402_6.3V
C1485 1U_0402_6.3V
These caps close to U64: Pin 19
12
+LAN_IO
for EMI
These caps close to JLAN1: Pin 13, 12
LED2_LED3
LED1_LED3
for EMI
These caps close to JLAN1: Pin 9, 11
Compal Secret Data
MCT1
MX1+
MX1-
MCT2
MX2+
MCT3
MX3+
MX3-
MCT4
MX4+
MX4-
U64
20
HSOP
21
HSON
15
HSIP
16
HSIN
17
REFCLK_P
18
REFCLK_M
25
CLKREQB
27
PERSTB
46
RSET
26
LANWAKEB
28
ISOLATEB
41
CKTAL1
42
CKTAL2
23
NC
24
NC
7
GND
14
GND
31
GND
47
GND
22
EGND
RTL8111DL-GR_LQFP48
24
RJ45_TX3-
23
RJ45_TX3+
22
21
RJ45_TX2-
20
RJ45_TX2+
19
18
RJ45_RX1-
17
RJ45_RX1+
16
15
RJ45_TX0-
14
RJ45_TX0+
13
LAN_MDIP2
RTL8111DL
75_1206_8P4R_5%
CM1293-04SO_SOT23-6
1
2
3
@
4
CH4
CH1
Vn
CH3
CH2
D28
RP42
Vp
LED3/EEDO
LED2/EEDI/AUX
LED1/EESK
EECS
LED0
MDIP0
MDIN0
MDIP1
MDIN1
MDI P2
MDI N2
MDI P3
MDI N3
FB12
SROUT12
EVDD12
DVDD12
DVDD12
DVDD12
AVDD12
AVDD12
VDDSR
VDDSR
VDD33
VDD33
AVDD33
AVDD33
ENSR
LAN_LED3
33
LAN_LED2
34
LAN_LED1
35
32
38
2
3
5
6
8
9
11
12
4
+LAN_SROUT12
48
+LAN_EVDD12
19
30
36
13
10
39
44
45
29
37
1
40
43
LAN_LED0
LAN_MDIP0
LAN_MDIN0
LAN_MDIP1
LAN_MDIN1
LAN_MDIP2
LAN_MDIN2
LAN_MDIP3
LAN_MDIN3
+LAN_AVDD33
R1241 3.6K_0402_5%
1 2
1 2
4.7UH_1008HC-472EJFS-A_5%_1008
+LAN_VDD12
W=60mils
+LAN_VDD12
+LAN_IO
+LAN_IO
These caps close to U64: Pin 1, 29,37,40
D54
LAN_LED2
CH751H-40PT_SOD323-2
LAN_LED3
CH751H-40PT_SOD323-2
LAN_LED1
CH751H-40PT_SOD323-2
LAN_LED3
CH751H-40PT_SOD323-2
4
5
6
45
36
27
18
LAN_MDIP3
LAN_MDIN3
2
C1493
1000P_1206_2KV7K
1
+3VS+3VS
http://laptop-motherboard-schematic.blogspot.com/
21
D55
21
D56
21
D57
21
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
GLAN_RXP_C
GLAN_RXP19
GLAN_RXN19
C C
+3VS
B B
LAN_LOPWEN19
A A
LAN_MDIN1
LAN_MDIP1
GLAN_TXP19
GLAN_TXN19
CLK_PCIE_LAN15
CLK_PCIE_LAN#15
GLAN_REQ#915
PCI_RST#17,23,25,27
R1245
1 2
1K_0402_5%
2
25MHZ_20P_1BX25000CK1A
C1488
1
27P_0402_50V8J
C1490 0.01U_0402_16V7K
C1491 0.01U_0402_16V7K
C1492 0.01U_0402_16V7K
C1494 0.01U_0402_16V7K
ICH_PCIE_WAKE#19,23,25,26
R1246
15K_0402_5%
1 2
Y9
1 2
LAN_LOPWEN ISOLATEB
1 2
R1374
@
1 2
1 2
1 2
1 2
CM1293-04SO_SOT23-6
1
CH1
2
Vn
3
CH2
D29
@
5
CH4
CH3
12
C1473 0.1U_0402_16V7K~N
C1476 0.1U_0402_16V7K~N
2
1
0_0402_5%
Vp
GLAN_RXN_C
12
GLAN_TXP
GLAN_TXN
PCI_RST#
1 2
R1244 2.49K_0402_1%
ICH_PCIE_W AKE#
ISOLATEB
R1420
0_0402_5%
LAN_CABDT19
1 2
C1489
27P_0402_50V8J
+V_DAC
LAN_MDIN3
LAN_MDIP3
+V_DAC
LAN_MDIN2
LAN_MDIP2
+V_DAC
LAN_MDIN1
LAN_MDIP1
+V_DAC
LAN_MDIN0
LAN_MDIP0
LAN_MDIP0 LAN_MDIN2
4
5
LAN_MDIN0
6
TS1
1
TCT1
2
TD1+
3
TD1-
4
TCT2
5
TD2+
TD2-6MX2-
7
TCT3
8
TD3+
9
TD3-
10
TCT4
11
TD4+
12
TD4-
BOTH_GST5009-LF
LAN_CABDT
Page 22
5
SATA HDD CONN
4
3
2
1
D D
PSATA_ITX_DRX_P018
PSATA_ITX_DRX_N018
PSATA_IRX_DTX_N0_C18
PSATA_IRX_DTX_P0_C18
PSATA_ITX_DRX_P0
PSATA_ITX_DRX_N0
C393 3900P_0402_50V7K
C392 3900P_0402_50V7K
C1214
C1213
PSATA_IRX_DTX_N0
12
PSATA_IRX_DTX_P0
12
0.01U_0402_50V7K
PSATA_ITX_DRX_P0_C
1 2
PSATA_ITX_DRX_N0_C
1 2
0.01U_0402_50V7K
+5VS
+5VS
10U_0805_10V4Z~N
1
1
C C
+
C574
C1777
@
2
150U_B2_6.3VM_R45M
2
C296
0.1U_0402_16V7K~N
1
2
0.1U_0402_16V7K~N
1
C377
2
1
C376
2
1000P_0402_50V7K~N
Close to SATA HDD
JSATA1
1
GND
2
A+
3
A-
4
GND
5
B-
6
B+
7
GND
8
V33
9
V33
10
V33
11
GND
12
GND
13
GND
14
V5
15
V5
16
V5
17
18
19
20
21
22
SUYIN_127043FR022G226ZL_NR
CONN@
GND
Reserved
GND
V12
V12
V12
GND
GND
23
24
+5VS
10U_0805_10V4Z
1
C498
2
1
2
1U_0603_10V4Z
Close to ODD Conn
C506
0.1U_0402_16V4Z
1
C503
2
1
C499
2
1000P_0402_50V7K~N
SATA ODD CONN
ODD_ITX_DRX_P018
ODD_ITX_DRX_N018
ODD_IRX_DTX_N0_C18
ODD_IRX_DTX_P0_C18
close JSATA2
ODD_ITX_DRX_P0
ODD_ITX_DRX_N0
C327 0.01U_0402_50V7K
C326 0.01U_0402_50V7K
C1216 0.01U_0402_50V7K
C1215 0.01U_0402_50V7K
1 2
1 2
1 2
1 2
+5VS
ODD_ITX_DRX_P0_C
ODD_ITX_DRX_N0_C
ODD_IRX_DTX_N0
ODD_IRX_DTX_P0
JODD2
1
GND
2
RX+
3
RX-
4
GND
5
TX-
6
TX+
7
GND
8
DP
9
5V
10
5V
MD
GND
GND
GND
GND
11
12
13
SUYIN_127382FR013S52_NR
14
15
B B
A A
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
http://laptop-motherboard-schematic.blogspot.com/
MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/1/15 2008/1/15
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
HDD/CDROM
LA-4592P
1
22 43Thursday, February 19, 2009
0.2
of
Page 23
A
B
C
D
E
Debug Board
JMINI1
1
1
3
3
5
5
7
R1425 0_0402_5%
EC_RX_P80_DATA26
1 1
2 2
PCI_RST#
1 2
1 2
R1427 0_0402_5%@
CLK_DEBUG_PORT
+3VS
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
GND1
FOX_AS0B226-S52N-7F~N
GND2
+1.5VS
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
PCI_RST#
R1414
1 2
0_0402_5%
+3VS
R1424 0_0402_5%
1 2
R1426 0_0402_5%@
1 2
+3VALW
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
LPC_FRAME# 18,26,27
LPC_AD[0..3] 18,26,27
EC_TX_P80_DATA 26
Power status(Left)
LED1
PWR_BLUE_LED#26,27
PWR_BLUE_LED#
12-21-BHC-ZL1M2RY-2C BLUE
R472
1 2
12
200_0603_5%
+5VALW
Mini-Express Card---WLAN
LED2
Y
3
1
2
B
1
2
1
C489
2
0.1U_0402_16V4Z~N
Compal Electronics, Inc.
Mini-Card/LED
LA-4592P
R471
1 2
200_0603_5%
4.7U_0805_10V4Z~N
1
C456
2
23 43Thursday, February 19, 2009
E
G
Q131
S
3
1 2
BATT_LOW_LED#
BATT_CHG_LED#
12-22/Y2BHC-A30/2C_Y/B~D
+3V_WLAN
45
0.01U_0402_16V7K~N
C500
R1513
1.5M_0402_5%
Title
Size Document Number Rev
Custom
Date: Sheet
3 3
ICH_PCIE_WAKE#
,21,25,26
4 4
CH_DATA28
CH_CLK28
WLAN_REQ#415
CLK_PCIE_MCARD#15
CLK_PCIE_MCARD15
CLK_DEBUG_PORT15
PCIE_RXN319
PCIE_RXP319
PCIE_TXN319
PCIE_TXP319
+3V_WLAN
ICH_PCIE_W AKE#
CH_DATA MINI_PIN3
R380 0_0402_5%@
R381 0_0402_5%@
WLAN_REQ#4
PCI_RST#
1 2
R445 0_0402_5%
1 2
R403 0_0402_5%
1 2
R404 0_0402_5%
A
1 2
1 2
CH_CLK MINI_PIN4
PCIE_RXN3 PCIE_C_RXN3
PCIE_RXP3 PCIE_C_RXP3
PCIE_TXN3 ICH_SM_DA
PCIE_TXP3
JMINI2
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
GND1
ACES_88910-5204
GND2
+3V_WLAN
+1.5VS
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
LED_WWAN#
LED_WLAN#
B
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
WL_OFF#
PCI_RST#
ICH_SM_CLK
@
R411
1 2
0_0805_5%
USB20_N6
USB20_P6
T61 PAD
12
R86100K_0402_5%
http://laptop-motherboard-schematic.blogspot.com/
+3VALW
1
C485
2
0.01U_0402_16V7K~N
WL_OFF# 26
PCI_RST# 17,21,25,27
+3V_WLAN
+1.5VS
ICH_SM_CLK 13,14,15,19
ICH_SM_DA 13,14,15,19
USB20_N6 19
USB20_P6 19
LED_WLAN# 27
+3V_WLAN
+1.5VS
+3V_WLAN
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
WLANPW_EN#26
2007/1/15 2008/1/15
+1.5VS
0.01U_0402_16V7K~N
C488
Compal Secret Data
Deciphered Date
1
2
2
G
1U_0603_10V6K
+B+_BIAS
R1512
470K_0402_5%
1 2
13
D
S
BATT_LOW_LED#26
BATT_CHG_LED#26
W=60mils W=60mils
+3VALW
D
6
1
C1822
Q132
SSM3K7002FU_SC70-3
2
1
2
SI3456BDV-T1-E3 1N TSOP6
WLANPW
D
+5VALW
0.2
of
Page 24
5
4
3
2
1
+3VS
1 2
R128 0_0603_5%
D D
C23 10P_0402_50V8J@
1 2
ACZ_BITCLK18
ADC_ACZ_SDIN018
ACZ_SDOUT18
ACZ_SYNC18
ACZ_RST#18
MIC_CLK28
MIC_SIG28
For IDT
EC_MUTE26
+AVDD_HD
+AVDD_HD
C C
C1826 15P_0402_50V8J @
1 2
1 2
R915 2.49K_0402_1%
HP_JD
1 2
R13 20K_0402_1%
MIC_JD
1 2
R892 10K_0402_1%
C114 1000P_0402_50V7K ~N
ACZ_SDOUT
1
C1399
2
R41 10_0402_5% @
ACZ_BITCLK
R8 33_0402_5%
12
1 2
R126 0_0603_5%
1 2
R127 0_0603_5%
R1539 0_0402_5%@
1 2
C142
1 2
2.2U_0603_6.3V6K
12
For SED TEST
0.1U_0402_16V4Z
C1829
1 2
0.47U_0603_10V7K
AMP_RIGHT
C1830
1 2
0.47U_0603_10V7K
C1831
1 2
B B
0.47U_0603_10V7K
AMP_LEFT
0.47U_0603_10V7K
C1832
1 2
EC_MUTE
1
C1398
2
0.1U_0402_10V6K
12
12
R1495100K_0402_5%
GNDA
C1827
AMP_R
AMP_L
1
C1397
2
1U_0402_6.3V
1
1
2
2
+3VS_DVDD
0.1U_0402_10V6K
6
8
5
10
11
2
4
46
48
47
35
36
14
13
7
42
26
30
33
49
W=40mil
C1828
10U_0805_10V4Z
7
17
9
5
19
9
3
U60
DVDD_IO
HDA_BITCLK
HDA_SDI
HDA_SDO
HDA_SYNC
HDA_RST#
DMIC_CLK/GPIO1
DMIC0/GPIO2
DMIC1/GPIO0/SPDIF_OUT_1
SPDIF_OUT_0
EAPD
CAPCAP+
SENSE_B
SENSE_A
DVSS
PVSS
AVSS
AVSS
AVSS
GND
92HD81B1X5NLGXA1X8 48P
RIN+
RIN-
LIN+
LIN-
SHUTDOWN
GND
20
21
1
C796
2
1
DVDD
DVDD_CORE
SPKR_PORT_D_L+
SPKR_PORT_D_R-
SPKR_PORT_D_R+
15
6
16
VDD
PVDD1
PVDD2
GND41GND311GND213GND1
P3017THF TSSOP 20P
40mil40mil
10U_0603_6.3V
AVDD27AVDD38PVDD39PVDD
HP0_PORT_A_L
HP0_PORT_A_R
VREFOUT_A_or_F
HP1_PORT_B_L
HP1_PORT_B_R
PORT_C_L
PORT_C_R
VREFOUT_C
SPKR_PORT_D_L-
PORT_E_L
PORT_E_R
PORT_F_L
PORT_F_R
PC_BEEP
MONO_OUT
CAP2
VREFFILT
VREG
R1523
1 2
0_0603_5%
U18
GAIN0
GAIN1
ROUT+
ROUT-
LOUT+
LOUT-
NC
BYPASS
1
1
C1403
2
45
28
29
23
31
32
19
20
24
40
41
43
44
15
16
17
18
12
25
22
21
34
V-
37
+5VS
+5VS
2
3
18
14
4
8
12
10
1
C1404
C1405
2
2
1U_0402_6.3V
AMP_LEFT
AMP_RIGHT
HP_LEFT
HP_RIGHT
MIC_LEFT
MIC_RIGHT
SPR_L1
SPR_L2
SPR_R1
SPR_R2
10U_0603_6.3V
0.1U_0402_10V6K
+MIC1_VREFO
R1532
@
1 2
R1533
@
1 2
R1534
@
1 2
R1535
@
1 2
Memo control
1 2
R1189 0_0402_5%
C141
4.7U_0603_6.3V
R1524 10K_0402_5%
1 2
R1525 10K_0402_5%@
1 2
SPK_R1
SPK_R2
SPK_L1
SPK_L2
1
C1833
2
1U_0603_10V4Z
C1406
+AVDD_HD
1
1
C1407
2
2
1U_0402_6.3V
INTSPK_L1
0_0603_5%
0_0603_5%
0_0603_5%
0_0603_5%
1
1
C1414
2
2
1 2
R1528 0_0603_5%
1 2
R1529 0_0603_5%
1 2
R1530 0_0603_5%
1 2
R1531 0_0603_5%
INTSPK_L2
INTSPK_R2
INTSPK_R1
MONO_IN
L6
0.1U_0402_10V6K
2.2U_0603_6.3V6K
R1526 10K_0402_5%
R1527 10K_0402_5%@
1 2
0_0805_5%
1
C66
2
10U_0603_6.3V
1 2
1 2
SPR_L1
SPR_L2
SPR_R1
SPR_R2
1
C1413
2
INTSPK_R1
INTSPK_R2
INTSPK_L1
INTSPK_L2
R14
R115
R116
R117
R118
+5VS
+AVDD_HD
1U_0402_6.3V
1 2
0_0805_5%
1 2
0_0805_5%
1 2
0_0805_5%
1 2
0_0805_5%
1 2
0_0805_5%
@
R1519 10K_0402_5%
@
@
@
1 2
@
1 2
R69610K_0402_5%
R1520 10K_0402_5%
@
HEADPHONE OUT JACK
FOX_JA6333L-B3S0-7F~N
1
2
0.01U_0402_16V7K
C252
@
HPR
13
D
2
2
G
G
SSM3K131TU_UFM-3
S
SSM3K131TU_UFM-3
S
G
G
2
2
D
1 3
12
R1538
@
100K_0402_5%
FOX_JA6333L-B3S 0-7F
5
4
3
6 7
2
1
5
4
3
6 7
2
1
JHP1
13
D
2
2
G
G
Q139
2N7002_SOT23-3
S
@
S
@
2N7002_SOT23-3
Q141
D
1 3
10
9
8
Q134
Q136
JMIC1
MONO_IN
10
9
8
HP_RIGHT HP_R
R1521 10K_0402_5%
R1522 10K_0402_5%
@
@
1 2
1 2
1 2
@
@
@
12
12
R69810K_0402_5%
R69910K_0402_5%
R69710K_0402_5%
1 2
1 2
R360 56_0402_5%
1 2
R361 56_0402_5%
For IDT
+5VALW
R1537
10K_0402_1%
EC_MUTE
2
G
HP_L
1
C1836
2
1000P_0402_50V7K~N
@
1 2
13
D
Q137
SSM3K7002FU_SC70-3
S
L23
1 2
BLM18BD601SN1D_0603~D
1 2
L22
BLM18BD601SN1D_0603~D
1
C1837
2
1000P_0402_50V7K~N
@
2N7002_SOT23-3
2N7002_SOT23-3
Q138
Q140
HPR
HPLHP_LEFT
PACDN042Y3R_SOT23-3
13
D
2
G
SSM3K131TU_UFM-3
S
@
S
@
G
SSM3K131TU_UFM-3
2
D
1 3
HP_JD
2
Q135
1
Q133
1
3
@
D16
2
0.01U_0402_16V7K
C260
@
HPL
13
D
S
S
D
1 3
For pop/click noise from S3/S4/cold boot/warm boot
+MIC1_VREFO
1
C7
@
2
1U_0402_6.3V
4.7K_0402_5%
4.7K_0402_5%
1 2
1 2
R349
MIC_RIGHT
MIC_LEFT
GNDAGND
R348
C24 2.2U_0402_6.3V6
C25 2.2U_0402_6.3V6
1 2
L34 BLM18B D601S N1D _0603~D
1 2
L35 BLM18B D601S N1D _0603~D
EC Beep
BEEP26
ICH Beep
SB_SPKR19
MICROPHONE IN JACK
MIC_JD
C524
@
C525
@
100P_0402_25V8K
100P_0402_25V8K
2
3
D23
@
1
PACDN042Y3R_SOT23-3
C1412 0.1U_0402_16V 4Z
1 2
C1416 0.1U_0402_16V 4Z
1 2
R1183
499K_0402_1%~D
R1188
499K_0402_1%~D
GAINGAIN1GAIN0
00
A A
Change to 100p from 0.01u for EMI
-1012
*
1
0 15.6dB
1
1
1
0
Buzzer need to support ICH/PCM_SPK/Battery_low and WL_on/off
http://laptop-motherboard-schematic.blogspot.com/
5
4
6dB
10dB
21.6dB
Security Cl assification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONT AINS CONFIDENT IAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTOD Y OF THE COMPE TENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NO R THE INFORMAT ION IT CONTAI NS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTR ONICS, INC.
3
2008/05/07 2009/05/07
D12PACDN042Y3R_SOT23-3
2
1
3
1
Compal Secret Data
Deciphered Date
2
D17PACDN042Y3R_SOT23-3
2
3
Speaker Connector
INTSPK_L2
INTSPK_L1
INTSPK_R2
INTSPK_R1
ACES_882 66- 04001
4
4
G2
3
3
G1
2
2
1
1
JSPK1
Compal Electronics, Inc.
Title
Size Docu me n t N u m ber Re v
Date: Sheet
6
5
100P_0402_25V8K
HD CODEC 92HD81B1
LA-4596P
Thursday, February 19, 2009
1
@
@
INTSPK_R2
INTSPK_R1
C9
C8
100P_0402_25V8K
@
INTSPK_L1
C15
100P_0402_25V8K
of
24 43
INTSPK_L2
100P_0402_25V8K
@
C16
0.3
Page 25
5
Express card
4
3
2
1
D D
12
C91 0.1U_0402_16V4Z~N
12
C74 0.1U_0402_16V4Z~N
12
C85 0.1U_0402_16V4Z~N
PCI_RST#17,21,23,27
SYSON26,30,36
SUSP#26, 29,30,35,37 CLK_PCIE_EXPR#15
C C
Express Card Power Switch
+1.5VS
+3VS
+3VALW
PCI_RST#
SYSON
SUSP#
CPPE#
EXPR_CPUSB#
+1.5V_CARD Max. 650mA, Average 500mA
U11
12
1.5Vin
14
1.5Vin
2
3.3Vin
4
3.3Vin
AUX_IN17AUX_OUT
6
SYSRST#
20
SHDN#
1
STBY#
10
CPPE#
9
CPUSB#
18
RCLKEN
P2231NF_QFN20
1.5Vout
1.5Vout
3.3Vout
3.3Vout
OC#
PERST#
GND
NC
+1.5VS_PEC
11
13
3
5
15
19
8
16
7
+3VS_PEC
PERST#
0.1U_0402_16V4Z~N
+3V_PEC
0.1U_0402_16V4Z~N
+3V_CARD Max. 1300mA, Average 1000mA
0.1U_0402_16V4Z~N
C90
C92
C75
+1.5VS_PEC
1
2
+3V_PEC
1
2
+3VS_PEC
1
2
4.7U_0805_10V4Z~N
1
C89
2
4.7U_0805_10V4Z~N
1
C93
2
4.7U_0805_10V4Z~N
1
C73
2
EXPCARD_REQ#1615
USB20_N7
USB20_P7
ICH_SMBCLK19
ICH_SMBDATA19
CLK_PCIE_EXPR15
PCIE_RXN419
PCIE_RXP419
PCIE_TXN419
PCIE_TXP419
+3V_PEC
+3VS_PEC
+1.5VS_PEC
+1.5VS_PEC
EXPR_CPUSB#
ICH_SMBCLK
ICH_SMBDATA
ICH_PCIE_WAKE#
PERST#
EXPCARD_REQ#16
CPPE#
CLK_PCIE_EXPR#
CLK_PCIE_EXPR
PCIE_RXN4
PCIE_RXP4
PCIE_TXN4
PCIE_TXP4
USB20_N719
USB20_P719
ICH_PCIE_WAKE#19,21,23,26
JEXP1
1
GND
2
USB_D-
3
USB_D+
4
CPUSB#
5
RSV
6
RSV
7
SMB_CLK
8
SMB_DATA
9
+1.5V
10
+1.5V
11
WAKE#
12
+3.3VAUX
13
PERST#
14
+3.3V
15
+3.3V
16
CLKREQ#
17
CPPE#
18
REFCLK-
19
REFCLK+
20
GND
21
PERn0
22
PERp0
23
GND
24
PETn0
25
PETp0
26
GND
27
GND
28
GND
29
GND
GND30GND
FOX_1CX41202-KH_26P
conn@
GND
31
32
B B
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLO SED TO ANY THI RD PART Y WITHO UT P RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
http://laptop-motherboard-schematic.blogspot.com/
2007/1/15 2008/1/15
3
Compal Secret Data
Deciphered Date
Title
Size D o cument Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
EXPRESS CARD
LA-4592P
0.2
of
25 43Thursday, February 19, 2009
1
Page 26
ICH_PCIE_W AKE#19,21,23,25
CLK_PCI_EC
12
R272
10_0402_5%@
1
C282
@
15P_0402_50V8J
2
EC_SMB_DA1
EC_SMB_CK1
EC_SMB_DA2
EC_SMB_CK2
LCD_TST
LCD_CBL_DET#
MIC_DIAG
EC_FB_SDATA
EC_FB_SCLK
MSEN#
TP_DATA
TP_CLK
EC_MUTE
KSO1
KSO2
WL_OFF#
10K_0402_5%
R1506
0_0402_5%
+3VALW
R263 4.7K_0402_5%
R262 4.7K_0402_5%
R264 4.7K_0402_5%
R265 4.7K_0402_5%
R269 4.7K_0402_5% @
R276 4.7K_0402_5%
R308 10K_0402_5%
R303 4.7K_0402_5%
R304 4.7K_0402_5%
R309 10K_0402_5%
R312
R1428
@
R1429
@
R1536
@
1 2
1 2
R271
4.7K_0402_5%
1 2
1 2
R270
4.7K_0402_5%
1 2
10K_0402_5%
47K_0402_5%
47K_0402_5%
47K_0402_5%
12
12
12
12
12
12
12
12
EC_FB_SCLK27
EC_FB_SDATA27
+5VS
+3VALW
12
12
12
+3VALW
R405
1 2
EC_PME#
12
R228
1 2
47K_0402_5%
2
C268
0.1U_0402_16V4Z
32.768KHZ_12.5P_1TJS125BJ2A251
+5VALW
+3VS
1
EC_FB_SCLK
EC_FB_SDATA
TOUCHKEY_TINT27
1
C292
2
KSI[0..7]27
KSO[0..15]27
EC_TX_P80_DATA23
EC_RX_P80_DATA23
PWR_BLUE_LED#23,27
18P_0402_50V8J
X2
C281
0.1U_0402_16V4Z~N
GATEA2018
KB_RST#18
SERIRQ19,27
LPC_FRAME#18,23,27
LPC_AD318,23,27
LPC_AD218,23,27
LPC_AD118,23,27
LPC_AD018,23,27
CLK_PCI_EC15
PLT_RST#7,17,29
PCI_CLKRUN#19,27
EC_SMB_CK140
EC_SMB_DA140
EC_SMB_CK24,16
EC_SMB_DA24,16
SLP_S3#19
SLP_S5#19
EC_SMI#19
EC_PME#17
FAN_SPEED14
ON_OFF27
NUMLED#27
R278
1 2
20M_0603_5%@
1
IN
2
+3VALW +EC_AVCC
C269
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
C493
0.1U_0402_16V4Z~N
1
2
10
12
13
37
20
38
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
77
78
79
80
14
15
16
17
18
19
25
28
29
30
31
32
34
36
122
123
1000P_0402_50V7K~N
C291
1000P_0402_50V7K~N
1
1
2
2
U29
1
GA20/GPIO00
2
KBRST#/GPIO01
3
SERIRQ#
4
LFRAME#
5
LAD3
7
LAD2
8
LAD1
LPC & MISC
LAD0
PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
Int. K/B
KSO5/GPIO25
Matrix
KSO6/GPIO26
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47
6
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A
XCLK1
XCLK0
KB926QFA1_LQFP128
9
22
33
96
VCC
VCC
VCC
PWM Output
DA Output
PS2 Interface
SPI Device Interface
SPI Flash ROM
SM Bus
GPIO
GND
GND
11
24
35
VCC
GND
C285
0.1U_0402_16V4Z~N
C277
1
2
EC_SCI#19
4
OUT
NC3NC
0.1U_0402_16V4Z~N
1
1
2
2
GATEA20
KB_RST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0 BATT_OVP
CLK_PCI_EC
PLT_RST#
EC_RST#
EC_SCI#
PCI_CLKRUN#
KSI[0..7]
KSO[0..15]
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
SLP_S3#
SLP_S5#
EC_SMI#
LID_SW#
EC_PME#
FAN_SPEED1
TOUCHKEY_TINT
EC_TX_P80_DATA
EC_RX_P80_DATA
ON_OFF
PWR_BLUE_LED#
NUMLED#
XCLKI
XCLKO
XCLKIXCLKO
R1421
0_0402_5%
1 2
1
C297
2
18P_0402_50V8J
1000P_0402_50V7K~N
111
125
67
VCC
VCC
AVCC
INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
ACOFF/FANPWM2/GPIO13
BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
AD Input
SELIO2#/AD5/GPIO43
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
GPIO
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
VR_ON/XCLK32K/GPIO57
EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
ICH_PWROK/GPXO06
GPO
PM_SLP_S4#/GPXID1
GPI
AGND
GND
GND
69
94
113
FANPWM1/GPIO12
AD3/GPIO3B
AD4/GPIO42
IREF/DA2/GPIO3E
DA3/GPIO3F
PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0
SPIDO/WR#
SPICLK/GPIO58
CIR_RX/GPIO40
SYSON/GPIO56
AC_IN/GPIO59
EC_ON/GPXO05
EC_SWI#/GPXO06
BKOFF#/GPXO08
WL_OFF#/GPXO09
ENBKL/GPXID2
ECAGND
ECAGND
SPIDI/RD#
SPICS#
GPXO10
GPXO11
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7
V18R
C481
1
2
21
BEEP
23
W_DISABLE#
26
ACOFF
27
63
64
ADP_I
65
AD_BID
66
MIC_DIAG
75
POW_MON
76
DAC_BRIG
68
EN_DFAN1
70
IREF
71
M_PWROK_EC
72
EC_MUTE
83
LCD_TST
84
85
LCD_CBL_DET#
86
TP_CLK
87
TP_DATA
88
SPI_PULLDOWNKSO3
97
EN_WOL#
98
BT_OFF#
99
VGATE
109
FRD#SPI_SO
119
FWR#SPI_SI
120
SPI_CLK
126
FSEL#SPICS#
128
WLANPW_EN#
73
MSEN#
74
FSTCHG
89
BATT_CHG_LED#
90
CAPSLED#
91
BATT_LOW_LED#
92
SCRLED#
93
SYSON
95
VR_ON
121
ACIN
127
EC_RSMRST#
100
EC_LID_OUT#
101
EC_ON
102
EC_SWI#
103
ICH_PWROK
104
BKOFF#
105
WL_OFF#
106
LCD_VCC_TEST_EN
107
PSID_DISABLE#
108
SLP_S4#
110
GMCH_ENBKL
112
USB_EN
114
EC_THERM#
115
SUSP#
116
117
PS_ID
118
124
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
http://laptop-motherboard-schematic.blogspot.com/
MAY BE USED BY OR DIS CLOSE D T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
L18
12
FBM-11-160808-601-T_0603
2
C482
0.1U_0402_16V4Z~N
1
R266 0_0402_5%
1 2
C273 0.01U_0402_16V7K
1 2
BATT_TEMP
1 2
R256 0_0402_5%
R274 4.7K_0402_5%
PBTN_OUT#
+V18_R
1 2
C322
C270 0.1U_0402_16V4Z
2007/1/15 2008/1/15
+3VALW+EC_AVCC
12
L19FBM-11-160808-601-T_0603
INVT_PWM 16
BEEP 24
W_DISABLE# 27
ACOFF 33
BATT_TEMP 40
BATT_OVP 40
ADP_I 33
MIC_DIAG 28
POW_MON 39
DAC_BRIG 16
EN_DFAN1 4
IREF 33
EC_MUTE 24
LCD_TST 16
LCD_CBL_DET# 16
TP_CLK 27
TP_DATA 27
12
EN_WOL# 21
BT_OFF# 28
VGATE 7,19,39
WLANPW_EN# 23
MSEN# 16
FSTCHG 33
BATT_CHG_LED# 23
CAPSLED# 27
BATT_LOW_LED# 23
SCRLED# 27
SYSON 25,30,36
VR_ON 39
ACIN 19,32,33
EC_RSMRST# 19
EC_LID_OUT# 19
EC_ON 27
EC_SWI# 19
ICH_PWROK 7,19
BKOFF# 16
WL_OFF# 23
LCD_VCC_TEST_EN 16
PSID_DISABLE# 32
SLP_S4# 19
GMCH_ENBKL 9,16
USB_EN 28
EC_THERM# 19
SUSP# 25,29,30,35,37
PBTN_OUT# 19
PS_ID 32
1U_0603_10V4Z
12
Compal Secret Data
Deciphered Date
ECAGND
CHGVADJ 33
C314
1 2
0.1U_0402_16V4Z~N
FSEL#SPICS# SPI_CS#
FRD#SPI_SO
C1825 0.01U_0402_16V7K
1 2
+3VALW
R437
1 2
LID_SW#
LID_SW#
12
R27515_0402_5%
U10
@
APX9132ATI-TRL_SOT23-3
3
U9
APX9132ATI-TRL_SOT23-3
3
R439 15_0402_5%
0.5A per each pin
Board ID
M/B rev:0.1; 0.2; 0.3; 1.0
Voltage:0.0; 0.4; 0.8; 1.0
ECAGNDBATT_OVP
12
10K_0402_5%
VOUT
VOUT
Title
Size Document Number Rev
Custom
Date: Sheet
20mils
U37
1
CS#
2
SO
HOLD#
3
WP#
4
GND
W25X16-VSSIG SOIC_SO8
2
VDD
GND
1
2
VDD
GND
1
Compal Electronics, Inc.
BIOS & EC I/O Port
LA-4592P
+3VALW
12
2008-08-05 change Brd ID
R232
100K_0402_5%
Ra
AD_BID
1
0.683
0.8519
1.0459
1.1873
1.3758
1.57235
@
1 2
1 2
1 2
C272
0.1U_0402_16V4Z
2
R419
0_0402_5%
R42015_0402_5%
R43815_0402_5%
of
26 43Thursday, February 19, 2009
SPI_CLK_R
FWR#SPI_SI
R231
71.5K_0402_1%
Rb
1 2
3.3V+/-5% 0.6V~1.6VVCC
100k
Ra
Rb
Board ID
26.1K +/-1%
0
34.8K +/-1%
1
46.4K +/-1%
2
56.2K +/-1%
3
71.5K +/-1%
4
91K +/-1%
SPI Flash (8Mb*1)
C507
@
1 2
22P_0402_50V8J
8
VCC
7
SPI_CLK_RSPI_SO
6
SCLK
5
SI
1
C1815
0.1U_0402_16V4Z
2
1
C1809
0.1U_0402_16V4Z
2
SPI_SI
+3VALW
+3VALW
SPI_CLK
0.2
Page 27
A
+3VALW
Power Button
R297
1 2
D15
100K_0402_5%
PWR_ON-OFF_BTN#
1 1
EC_ON26
2 2
EC_ON
PWR_ON-OFF_BTN#
CHN202UPT SC-70
+3VALW
R296
4.7K_0402_5%
@
1 2
1 2
R291
0_0402_5%
SW3
@
SW_1BT002-0121L_4P
3
4
5
2
1
2
G
1
2
6
3
13
D
Q26
SSM3K7002FU_SC70-3
S
POWER SWITCH
51ON#
2
1
ON_OFF 26
51ON# 32
C313
1000P_0402_50V7K~N
12
Regulator for ENE sensor
Wireless_BTN
SW1
1BS003-1211L_3P
11223
3
D60
W_DISABLE#
W_DISABLE#26
3 3
TPM 1.2
4 4
2
3
PJSOT24C_SOT23-3
@
+3VS
+3VALW
1
LPC_FRAME#18,23,26
PCI_RST#17,21,23,25
SERIRQ19,26
CLK_PCI_TPM15
PCI_CLKRUN#19,26
LPC_FRAME#
PCI_RST#
SERIRQ
PCI_CLKRUN#
12mA
+5VS+5VS
JTPM1
1
GND1
3
IAC_SDATA_OUT
5
GND2
7
IAC_SYNC
9
IAC_SDATA_IN
11
IAC_RESET#
C250
LPC_FRAME#
PCI_RST#
SERIRQ
CLK_PCI_TPM
PCI_CLKRUN#
GND13GND14GND15GND16GND17GND
1U_0402_6.3V4Z
1
2
IAC_BITCLK
D13
RLZ20A_LL34
Adjustable Output
R901
1 2
10K_0603_1%
2
RES0
4
RES1
6
3.3V
8
GND3
10
GND4
12
ACES_88018-124L
18
B
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
CLK_PCI_TPM
RT9198-33PBR SOT-23 5P
SHDN#3BP
2
GND
1
VIN
VOUT
U54
LPC_AD0 18,23,26
LPC_AD1 18,23,26
LPC_AD2 18,23,26
LPC_AD3 18,23,26
C
INT_KBD CONN.
KSI[0..7]26
KSO[0..15]26
KSI[0..7]
KSO[0..15]
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
D
JKB1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
G1
28
G2
ACES_88514-2601_26P
CONN@
KSO8
KSI3
KSO9
KSI2
KSI1
KSO10
KSO11
KSI0
KSO12
KSO13
KSO14
KSO15
E
C449 100P_0402_25V8K@
C239 100P_0402_25V8K@
C249 100P_0402_25V8K@
C240 100P_0402_25V8K@
C241 100P_0402_25V8K@
C248 100P_0402_25V8K@
C247 100P_0402_25V8K@
C242 100P_0402_25V8K@
C246 100P_0402_25V8K@
C245 100P_0402_25V8K@
C244 100P_0402_25V8K@
C243 100P_0402_25V8K@
KSI7
KSI6
KSI5
KSO0
KSO1
KSO2
KSI4
KSO3
KSO4
KSO5
KSO6
KSO7
C235 100P_0402_25V8K@
C236 100P_0402_25V8K@
C237 100P_0402_25V8K@
C441 100P_0402_25V8K@
C442 100P_0402_25V8K@
C443 100P_0402_25V8K@
C238 100P_0402_25V8K@
C444 100P_0402_25V8K@
C445 100P_0402_25V8K@
C446 100P_0402_25V8K@
C447 100P_0402_25V8K@
C448 100P_0402_25V8K@
For EMI
Function/B CONN.
R606
JFN1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
GND
18
GND
ACES_88512-1641_16P
CONN@
BTOP_BTN#
SCRLED#26
CAPSLED#26
NUMLED#26
TOUCHKEY_TINT26
PWR_BLUE_LED#23,26
BLUETOOTH_LED#28
KC FBMA-11-100505-301T 0402
LED_WLAN#23
+3VALW
SATA_LED#18
1
C1834
2
10U_0603_6.3V
R880
@
0_0603_5%
1 2
1
EC_FB_SCLK
EC_FB_SDATA
+3VS_FUN
4
5
+3VS_FUN
For ENE ( Close to JFN1 ).
PWR_ON-OFF_BTN#
BTOP_BTN#
EC_FB_SCLK26
EC_FB_SDATA26
+3VS
D58
2
3
PJSOT24C_SOT23-3
@
Touch PAD/B CONN.
TP/B TO M/B
TP_CLK
TP_DATA
1
@
@
C309100P_0402_25V8K
2
C310100P_0402_25V8K
C300
0.01U_0402_16V7K
+5VS
1
TP_CLK26
TP_DATA26
2
SCRLED#
CAPSLED#
NUMLED#
TOUCHKEY_TINT
PWR_BLUE_LED#
BLUETOOTH_LED#
KC FBMA-11-100505-301T 0402
L7
L21
LED_WLAN#
PWR_ON-OFF_BTN#
R622
EC_FN_SCLK
EC_FN_SDATA
33P_0402_50V J NPO
1
2
12
12
1 2
2
3
1
1 2
0_0402_5%
EC_FN_SCLK
EC_FN_SDATA
R_SATA_LED#
0_0402_5%
1
1
C39
C37
33P_0402_50V J NPO
@
@
2
2
CONN@
ACES_88514-0441_4P
6
G2
5
G1
4
4
3
3
2
2
1
1
JP1
D24
SM05T1G_SOT23-3~D
@
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
http://laptop-motherboard-schematic.blogspot.com/
MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2007/1/15 2008/1/15
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
D
Date: Sheet
Compal Electronics, Inc.
PWR_OK/BTN/TP
LA-4592P
E
27 43Thursday, February 19, 2009
0.2
of
Page 28
C228
0.1U_0402_16V4Z
C253
0.1U_0402_16V4Z
C64
0.1U_0402_16V4Z
USB20_N519
USB20_P519
1
2
+5VALW
1
2
+5VALW
1
2
CM1293-04SO_SOT23-6
1
CH1
2
Vn
3
CH2
D27
+3VS
80 mils
USB_EN#
80 mils
USB_EN#
4
CH4
5
Vp
6
CH3
Fingerprint
ACES_88512-0641_6P
80 mils
USB_EN#
USB20_P5
+3VS
USB20_N5
JFP1
7
66G1
5
8
5
G2
4
4
3
3
2
2
1
1
CONN@
U12
1
GND
2
IN
3
IN
4
EN#
RT9711PS SO 8P
U14
1
GND
2
IN
3
IN
4
EN#
RT9711PS SO 8P
+5VS
L111 MBK1608 2 2 1 Y Z F 0 603
+3VS
L112 MBK1608 2 2 1 Y Z F 0 603
+USB_AS+5VALW
1
+USB_CS
OUT
OUT
OUT
OC#
8
7
6
5
+
2
+USB_BS
OUT
OUT
OUT
OC#
OUT
OUT
OUT
OC#
U13
1
GND
2
IN
3
IN
4
EN#
RT9711PS SO 8P
8
7
6
5
8
7
6
5
Check Module pin define
USB20_P119
USB20_N119
12
12
L42, L43 AS CLOSE JCA1 AS POSSIBLE
USB_EN26
USB_EN
MIC_SIG24
MIC_CLK24
MIC_DIAG26
+5VALW
2
G
0.1U_0402_16V4Z
C434
150U_B2_6.3VM_R45M
1
+
C1811
150U_B2_6.3VM_R45M
2
USB20_P1
USB20_N1
MIC_SIG
MIC_CLK
MIC_DIAG
AS CLOSE AS JCA1
100P_0402_50V
R222
10K_0402_5%
1 2
USB_EN#
13
D
Q4
SSM3K7002FU_SC70-3
S
C223
USB_EN#
USB_EN#
C1812
USB_OC#9 19
12
R154
100K_0402_5%
@
2
G
USB_OC#0 19
USB_OC#2_8 19
0.1U_0402_16V4Z
USB_EN#
Camera Conn
1 2
L41 0_0603_5%
1
1
C1770
@
C1771
@
2
2
L41 AS CLOSE JCA1 AS POSSIBLE
100P_0402_50V
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
http://laptop-motherboard-schematic.blogspot.com/
R155
470_0603_5%
1 2
13
D
2
G
S
2
G
R36
470_0603_5%
1 2
13
D
Q8
SSM3K7002FU_SC70-3
S
1
2
3
4
5
6
7
8
9
10
11
12
CH_CLK23
BT_OFF#26
BLUETOOTH_LED#27
Q14
SSM3K7002FU_SC70-3
USB20_N019
USB20_P019
R38
470_0603_5%
1 2
13
D
Q13
SSM3K7002FU_SC70-3
S
USB20_N919
USB20_P919
USB20_N319
USB20_P319
JCA1
1
2
3
4
5
6
7
8
9
10
GND
GND
ACES_88460-1001
USB20_P419
USB20_N419
T62PAD
CH_DATA23
+3VS
2007/1/15 2008/1/15
Bluetooth
BT_ACTIVE
CH_CLK
BT_OFF#
Compal Secret Data
JBT1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
GND
12
GND
ACES_88460-1001
Deciphered Date
CM1293-04SO_SOT23-6
1
CH1
2
Vn
3
CH2
D19
@
USB20_N0
USB20_P0
CM1293-04SO_SOT23-6
1
2
3
D21
@
CH4
CH1
Vn
CH2
Vp
CH3
USB20_P9 USB_P9
R1410 0_0402_5%
R1411 0_0402_5%
12
R1 0_0402_5%
12
R3 0_0402_5%
USB_P9
4
5
+USB_BS
USB_N9
6
12
12
Felica Conn
+5VS
1
2
3
4
LEC
5
ACES_88512-0641_6P
IEEE1394_TPBN029
IEEE1394_TPBP029
IEEE1394_TPAN029
IEEE1394_TPAP029
USB20_P219
USB20_N219
USB20_P819
USB20_N819
Title
Size Document Number Rev
Custom
Date: Sheet
TP1
@
C315
10U_0805_10V4Z
USB20_N3
USB20_P3
1
@
2
USB_P0
4
CH4
5
6
+USB_AS
+USB_AS
USB_N0
W=60mils
+USB_BS
+USB_CS
W=80mils
1
2
3
4
5
6
7
8
JUSBP4
1
VCC
2
USB_N
3
USB_P
4
GND
5
GND
6
GND
7
GND
8
GND
SUYIN_020133MR004S536ZL
CONN@
JUSBP3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ACES_87213-1200G
CONN@
1
2
3
4
5
G2
66G1
JFE1
CONN@
USB_N0
USB_P0
W=60mils
USB_N9USB20_N9
8
7
Vp
CH3
Compal Electronics, Inc.
USB/BlueTooth/FP/Felcia
LA-4592P
JUSBP1
VCC
USB_N
USB_P
GND
GND
GND
GND
GND
SUYIN_020133MR004S536ZL
CONN@
1
2
3
4
5
6
7
8
9
10
11
12
GND1
GND2
of
28 43Thursday, February 19, 2009
0.2
Page 29
5
D D
+1.8V
SUSP30,38
0_0603_5%
+3VS
C C
1 2
R1436
R1434
@
1 2
100K_0402_5%
0.1U_0402_10V6K
1
C1794
2
AO3413_SOT23
C1795
Q130
@
S
@
C1789
0.1U_0402_10V6K
1
2
G
2
1
2
+3VS_PHY
C1796
+1.8VS_CB
D
13
0.01U_0402_16V7K
4.7U_0805_10V4Z
R1432
1 2
0_0402_5%
+1.8VS_CB
C1785
+3VS
+3VS_PHY
4.7U_0805_10V4Z
100mA
1
C1791
2
R1439
1 2
0_0603_5%
1
C1781
2
1
C1786
2
0.1U_0402_10V6K
C1792
2
1
C1782
4.7U_0603_6.3V6K
0.1U_0402_10V7K~N
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C1788
C1787
2
0.1U_0402_10V6K
1
C1793
2
100mA
+PE_3.3VCCA
C1799 4.7U_0805_10V4Z
C1800 0.1U_0402_10V6K
1 2
2
1
C1783
1
2
O2 recommend
4.7U_0805_10V4Z
Add GND For O2
PCIE_TXP519
PCIE_TXN519
1U_0402_6.3V6K
PCIE_RXP519
PCIE_RXN519
CLK_PCIE_MEDIA15
CLK_PCIE_MEDIA#15
PLT_RST#7,17,26
IEEE1394_TPAP0 28
IEEE1394_TPAN0 28
IEEE1394_TPBP0 28
IEEE1394_TPBN0 28
+3VS
R1442
1 2
10K_0402_5%
MEDIA_REQ#3215
B B
IEEE1394_TPBIAS0
56.2_0402_1%
56.2_0402_1%
12
12
R1454
56.2_0402_1%
56.2_0402_1%
12
12
R1480
A A
5.1K_0402_1%
R1482
1 2
270P_0402_50V7K
2
1
R1455
C1806
IEEE1394_TPAP0
IEEE1394_TPAN0
IEEE1394_TPBP0
IEEE1394_TPBN0
R1481
C1807
1
2
Layout Note: Place close to OZ888 Chipset.
5
C1801
C1802
2
1
C1784
0.1U_0402_10V7K~N
0.1U_0402_10V6K
1 2
0_0402_5%
+3.3VCCD
4
+1.8PE_VCCA
0.1U_0402_10V7K~N
300mA
R1435
@
R1517 0_0402_5% @
1 2
R1518
1 2
0_0402_5%
R14401.2K_0402_1%
R14415.1K_0402_1%
12
0.1U_0402_10V6K
12
0.1U_0402_10V6K
4
@
R1433
+VCCD_OUT
12
12
PCIE_C_RXP5
PCIE_C_RXN5
300mA
0_0402_5%
1 2
+VCCA_OUT
U46
7
PE_VCCA
14
PE_VCCA
17
PE_VCCA
1
VCCA_OUT
4
CORE_VCCD
18
CORE_VCCD
24
CORE_VCCD
41
CORE_VCCD
64
CORE_VCCD
20
VCCD_OUT
28
VCCD_OUT
44
3.3VCCD
27
3.3VCCD
19
3.3VCCD
2
3.3VCCA
40
3.3VCCA
35
3.3VCCA
3
PE_3.3VCCA
11
PLL_REF_RETURN
9
PE_RTERM2
10
PE_RTERM1
12
PE_RXP
13
PE_RXN
15
PE_TXP
16
PE_TXN
5
PE_REFCLKP
6
PE_REFCLKN
32
PE_CLKREQ#
31
PE_RST#
65
DGND
OZ888GS0L1N_QFN64_8X8
POWER
PCIe
IEEE1394
MMI_SD_MMC_CD#
CardReader
GND
+3VALW
SUSP#25,26,30,35,37
1394_TPBN
1394_TPBP
1394_TPAN
1394_TPAP
1394_TPBIAS
1394_XI
1394_XO
1394_REF
MMI_VCC
MMI_XD_CD#
MMI_MS_CD#
MS_CLK/XD_CE#
SD_MMC_CLK
MMI_WPI#
MMI_XD_WPO
MMI_XD_RE#
MMI_XD_RB#
MMI_XD_CLE
SD_MMC_CMD
MMI_XD_WE#
MS_BS/XD_ALE
MMC_MS_XD_D7
MMC_MS_XD_D6
MMC_MS_XD_D5
MMC_MS_XD_D4
MS_XD_D3
SD_MMC_D3
MS_XD_D2
SD_MMC_D2
MS_XD_D1
SD_MMC_D1
MS_XD_D0
SD_MMC_D0
AGND
SUSP#
1U_0402_6.3V6K~D
33
34
36
37
38
42
43
39
26
25
29
30
45
46
61
63
62
23
22
48
21
47
49
50
51
52
53
54
55
56
57
58
59
60
8
3
+1.8VS_CB
5
4
1
C1824
22U_0805_6.3V6M~D
R1443 0_0402_5%
R1444 0_0402_5%
R1446 0_0402_5%
R1448 0_0402_5%
R1450 0_0402_5%
R1452 0_0402_5%
R1456 0_0402_5%
R1458 0_0402_5%
R1461 0_0402_5%
R1463 0_0402_5%
R1464 0_0402_5%
R1466 0_0402_5%
R1468 0_0402_5%
R1470 0_0402_5%
R1471 33_0402_5%~D
R1473 0_0402_5%
2
+3VS_CR
200mA
1
C1798
2
4.7U_0603_6.3V6K
1
C1803
1U 10V Z Y5V 0603
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
2008/1/3 2009/01/3
2
Compal Secret Data
VIN
GND
EN
MS_XD_D0
MS_XD_D1
MS_XD_D2
MS_XD_D3
MMC_XD_D4
MMC_XD_D5
MMC_XD_D6
MMC_XD_D7
XD_WE#
MMI_XD_WPO
MSBS_XDALE
XD_CD#
XD_RB#
XD_RE#
MSCLK_XDCE#
XD_CLE
VOUT
SD_CLK
U65
FB
1
2
3
C1823
1
2
RT9043-GB_SOT23-5~D
R1515
@
10K_0402_5%
1 2
IEEE1394_TPBN0
IEEE1394_TPBP0
IEEE1394_TPAN0
IEEE1394_TPAP0
IEEE1394_TPBIAS0
OZ888XI
OZ888XO
R1437 5.9K_0402_1%
1 2
XD_CD#
MS_CD#
SD_CD#
MSCLK_XDCE#
SD_CLK_R
1 2
MMI_WPI#
R1501 0_0402_5%
MMI_XD_WPO
XD_RE#
XD_RB#
XD_CLE
SD_CMD
XD_WE#
MSBS_XDALE
MMC_XD_D7
MMC_XD_D6
MMC_XD_D5
MMC_XD_D4
MS_XD_D3
MMC_SD_D3
MS_XD_D2
MMC_SD_D2
MS_XD_D1
MMC_SD_D1
MS_XD_D0
MMC_SD_D0
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFOR MATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
1 2
12
R1516
100K_0402_1%
+3VS_CR
1
C1804
1U 10V Z Y5V 0603
2
XDD0_MSD0
XDD1_MSD1
XDD2_MSD2
XDD3_MSD3
XDD4_MMCD4
XDD5_MMCD5
XDD6_MMCD6
XDD7_MMCD7
XDWE
XDWP
XDALE_MSBS
XDCD
XDRB
XDRE
XDCE_MSCLK
XDCLE
Deciphered Date
2
R1514
61.9K +-1% 0402
+3VS_CR
2
Layout Note: Place close to
OZ888 and Shield GND.
C1790
1 2
10P_0402_50V8J~D
C1797
1 2
10P_0402_50V8J~D
1
C1805
1U 10V Z Y5V 0603
2
JSD1
3
XD-VCC
32
XD-D0
10
34
33
35
40
39
38
37
36
11
31
41
42
XD-D1
9
XD-D2
8
XD-D3
7
XD-D4
6
XD-D5
5
XD-D6
4
XD-D7
XD-WE
XD-WP
XD-ALE
XD-CD
XD-R/B
XD-RE
XD-CE
XD-CLE
7in1-GND
7in1-GND
7in1-GND
7in1-GND
TAITW_R015-A10-LM
7 IN 1 CONN
1
OZ888XI
X3
24.576MHz_16P_X5H024576FG1H-H
1 2
1 2
0_0402_5%
FOR DELL TEST
OZ888XO
R1438
SD_CLK XDCE_MSCLK
Layout Note: Place close to
J8IN1
+3VS_CR
21
SD-VCC
28
MS-VCC
SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-DAT4
SD-DAT5
SD-DAT6
SD-DAT7
SD-CMD
MS-SCLK
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3
SD-CD
SD-WP
MS-BS
MS-INS
20
14
12
30
29
27
23
18
16
1
2
25
26
13
22
17
15
19
24
SDCLK
SDDAT0
SDDAT1
SDDAT2
SDDAT3
XDD4_MMCD4
XDD5_MMCD5
XDD6_MMCD6
XDD7_MMCD7
SDCD
SDWP
SDCMD
XDCE_MSCLK
XDALE_MSBS
MSINS
XDD0_MSD0
XDD1_MSD1
XDD2_MSD2
XDD3_MSD3
R1498
0_0402_5%
@
1 2
1
C1813
@
1U 10V Z Y5V 0603
2
R1445 33_0402_5%~D
1 2
R1447 0_0402_5%
1 2
R1449 0_0402_5%
1 2
R1451 0_0402_5%
1 2
R1453 0_0402_5%
1 2
R1465 0_0402_5%
1 2
R1467 0_0402_5%
1 2
R1469 0_0402_5%
1 2
R1475 0_0402_5%
1 2
All DATA spacing=8mil, CLK spacing=15mil
Title
Size Document Number Rev
Date: Sheet
OZ888 Card Reader /1394
LA-4592P
Thursday, February 19, 2009
1
R1499
0_0402_5%
@
1 2
1
C1814
1U 10V Z Y5V 0603
2
@
SD_CLK
MMC_SD_D0
MMC_SD_D1
MMC_SD_D2
MMC_SD_D3
SD_CD#
MMI_WPI#
SD_CMD
MS_CD#
of
29 43
0.2
http://laptop-motherboard-schematic.blogspot.com/
Page 30
A
B
C
D
E
+5VALW to +5VS Transfer+3VALW to +3VS Transfer
C264
1
S
2
S
3
S
4
G
+3VS+3VALW
10U_0805_10V4Z~N
1
1
C465
2
2
0.1U_0402_16V4Z~N
C256
U39
8
S
D
7
S
D
6
1
C278
2
10U_0805_10V4Z~N
RUNON 5VS_GATE
D
5
D
SI4800DY_SO8
1 2
R267
47K_0402_5%
S
G
1
2
+B+_BIAS
12
R198
330K_0402_5%
1 1
SUSP
2
G
1
2
RUNON 3VS_GATE
13
D
Q18
SSM3K7002FU_SC70-3
S
U40
8
D
7
D
6
D
5
D
C271
SI4800DY_SO8
10U_0805_10V4Z~N
1 2
R197
100K_0402_5%
1
0.01U_0402_25V7K~N
2
+5VS+5VALW
1
2
3
4
C279
0.01U_0402_25V7K~N
1
2
0.1U_0402_16V4Z~N
C284
1
C283
10U_0805_10V4Z~N
2
+CPU_CORE
100K_0402_5%
SYSON#
SYSON
1 2
SUSP
SUSP#
+3VALW
12
R409
13
2
G
R365
10K_0402_5%
+5VALW
2
G
R338
10K_0402_5%
1 2
D
Q42
SSM3K7002FU_SC70-3
S
12
R340
100K_0402_5%
13
D
Q32
SSM3K7002FU_SC70-3
S
2 2
SYSON25,26,36
3 3
SUSP29,38
SUSP#25,26,29,35,37
1 2
C211 0.1U_0402_16V4Z~N
+VCCP
VGA Discharge circuit
Discharge circuit-1
+1.8VS_CB
R536
@
470_0603_5%
1 2
13
2
G
D
Q50
@
SSM3K7002FU_SC70-3
S
http://laptop-motherboard-schematic.blogspot.com/
4 4
A
SUSP
B
+1.8V
R133
@
470_0603_5%
1 2
13
SYSON#
D
2
G
Q12
S
@
SSM3K7002FU_SC70-3
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2007/1/15 2008/1/15
Compal Secret Data
Deciphered Date
SUSP
+0.9VS
1 2
13
D
2
G
S
R351
@
470_0603_5%
SUSP SUSPSUSP
Q33
@
SSM3K7002FU_SC70-3
D
+5VS
1 2
13
D
2
G
S
+3VS
R391
@
470_0603_5%
Q39
@
SSM3K7002FU_SC70-3
Title
Size Document Number Rev
Custom
Date: Sheet
R383
39_0603_5%
1 2
13
D
2
G
Q38
S
SSM3K7002FU_SC70-3
Compal Electronics, Inc.
DC/DC Circuits
LA-4592P
+1.5VS
1 2
13
D
2
G
S
E
R382
@
470_0603_5%
Q37
@
SSM3K7002FU_SC70-3
of
30 43Thursday, February 19, 2009
0.2
Page 31
5
4
3
2
1
FD2
FD1
FIDUCAL
FIDUCAL
@
@
1
D D
H_3P0
H_3P2
H_3P1
C C
H_3P7
H_4P2
H_4P5
H7
HOLEA@
1
H17
HOLEA@
1
H30
HOLEA@
1
H26
HOLEA@
1
H3
HOLEA@
1
H1
HOLEA@
1
@
1
H8
HOLEA@
1
H18
HOLEA@
1
H4
H5
HOLEA@
HOLEA@
1
H2
HOLEA@
1
FD3
FIDUCAL
1
H9
HOLEA@
1
H25
HOLEA@
1
1
H6
HOLEA@
FD4
FIDUCAL
@
H10
HOLEA@
1
FD5
FIDUCAL
@
1
H11
HOLEA@
1
1
H27
HOLEA@
1
FD6
FIDUCAL
@
1
1
H29
H12
HOLEA@
1
H15
HOLEA@
HOLEA@
1
1
H20
H16
HOLEA@
1
H21
HOLEA@
HOLEA@
1
1
H22
H23
HOLEA@
HOLEA@
1
1
B B
A A
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
http://laptop-motherboard-schematic.blogspot.com/
MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/1/15 2008/1/15
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
Screws
LA-4592P
1
31 43Thursday, February 19, 2009
0.2
of
Page 32
5
4
3
2
1
PJPDC1
TYCO_1566065-2~D
9
GND_4
8
GND_3
7
BATT+
51ON#27
GND_2
6
GND_1
MH1
MH2
@
D D
C C
1
Low_PWR
2
DC+_1
3
DC+_2
4
DC-_1
5
DC-_2
PD4
2 1
CH751H-40PT_SOD323-2
CHGRTCP
12
PR205
100K_0402_5%~D
PR206
22K_0402_1%~D
1 2
PC164
PL16
FBM-L11-160808-601LMT 0603~D
PJP1
JUMP_43X118@
2
112
12
0.22U_1206_25V7K~D
2
DOCK_PSID
12
12
PC313
0.01U_0402_25V7K~D
PQ50
TP0610K-T1-E3_SOT23-3
13
32.8
12
PC311
VIN
1 2
12
68_1206_5%
12
100P_0402_50V8J~D
RLS4148_LL34-2
PR203
12
12
PC312
1000P_0402_50V7K~D
PD3
12
PR204
68_1206_5%
PC165
0.1U_0603_25V7K~D
ADPIN
12
12
PC158
PC314
0.1U_0603_25V7K~D
100P_0402_50V8J~D
SMB3025500YA_2P
PC157
1000P_0402_50V7K~D
PL17
1 2
12
PC160
100P_0402_50V8J~D
VIN
PR189
1M_0402_1%~D@
12
PC159
1000P_0402_50V7K~D
@
PC162
.1U_0402_16V7K~D
VIN
12
PR190
@
82.5K_0402_1%~D
PR193
22K_0402_1%~D@
1 2
@
12
12
5
6
PR194
19.6K_0402_1%~D
+
-
8
@
PU12B
P
7
O
G
LM393DR_SO8
4
12
@
PC163
1000P_0402_50V7K~D
1 2
@
N40N41
3
+
N35
2
-
PR198
@
10K_0402_5%~D
Vin Detector
VS
8
PU12A
P
O
G
LM393DR_SO8
4
12
PC161
1
@
12
0.01U_0402_25V7K~D
RLZ4.3B_LL34
RTCVREF
3.3V
PD1
VIN
12
PR191
10K_0402_5%~D@
12
@
PR192
@
1K_0402_5%~D
1 2
12
@
PR195
10K_0402_5%~D
ACIN 19,26,33
Max. typ. Min.
VS
L-->H 18.234 17.841 17.449
H-->L 17.597 17.210 16.813
2
+1.5VSP
+0.9VSP
+VCCPP
12
PR207
200_0805_5%
12
PC167
1U_0805_25V4Z~D
PJP4
JUMP_43X118@
112
PJP6
JUMP_43X118@
112
PJP8
JUMP_43X118@
112
PJP10
JUMP_43X118@
112
+3VALWP+5VALWP
2
PR212
PD5
DA204U_SOT323
3
1
+5VALWP
12
PR209
1 2
2.2K_0402_5%~D
+5VALWP
2
3
PD6
@
PR214
Title
Size Document Number Rev
Date: Sheet
DA204U_SOT323
10K_0402_1%~D
PR216
1 2
10K_0402_1%~D@
1
DCIN / Vin Detector
LA-4596P
PS_ID 26
PSID_DISABLE# 26
1
0.2Custom
of
32 43Thursday, February 19, 2009
PR208
@
1 2
0_0402_5%~D
PQ53
DOCK_PSID
2
+1.5VS
2
+0.9VS
2
+VCCP
2
2
1
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
http://laptop-motherboard-schematic.blogspot.com/
MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
PR213
3
PD7
SM24_SOT23
100K_0402_1%~D
@
PR215
15K_0402_1%~D
2006/10/1 2007/5/01
FDV301N_NL_SOT23-3~D
1 2
1 2
Compal Secret Data
Deciphered Date
D
1 3
2
B
E
33_0402_5%~D
S
1 2
G
2
C
PQ54
MMST3904-7-F_SOT323-3
3 1
2
PJP3
JUMP_43X118@
112
PJP5
JUMP_43X118@
112
PJP7
JUMP_43X118@
112
PJP9
JUMP_43X118@
112
PJP11
JUMP_43X118@
112
5
RTCVREF
12
PC166
2
2
2
2
2
APL5156-33DI-TRL_SOT89-3
PU14
3
VOUT
GND
1
4.7U_0805_6.3V6K~D
+5VALW
+3VALW
+1.8V
VIN
3.3V
B B
+5VALWP
A A
+3VALWP
+1.8VP
Page 33
A
Charger/RTC BATTERY
KM L 5 0
B
C
D
E
FDS4435BZ_SO8
1
2
3
4
12
PR219
100K_0402_1%~D
0.01U_0402_25V7K~D
115K_0402_1%~D
1 2
0.01U_0402_25V7K~D
@
PQ60
1 3
VREF
12
2
G
12
PR397
340K_0402_1%~D
PQ56
S
D
S
D
S
D
G
D
12
PR224
PC182
1U_0603_10V6K~D
+3VALW
12
PR395
200K_0402_1%~D
13
D
PQ90
SSM3K7002F_SC59-3
S
PR217
0.015_2512_1%
8
7
6
1
5
2
PC175
.1U_0402_16V7K~D
1 2
PC178
0.1U_0603_25V7K~D
12
12
PR225
100K_0402_1%~D
VREF
PC188
1 2
PR371
0_0402_5%~D
GATE
13
D
PQ89
2
G
SSM3K7002F_SC59-3
S
4
3
CHGEN#
12
PC176
0.1U_0603_25V7K~D
ACSET
1 2
PC184
0.47U_0603_16V7K~N
10
12
12
PR370
0_0402_5%~D@
11
VADJ
12
13
/BATDRV
14
PU15
1
CHGEN
2
ACN
3
ACP
4
ACDRV
5
ACDET
6
ACSET
7
ACOP
8
OVPSET
9
AGND
VREF
VDAC
VADJ
ACGOOD
BATDRV
BQ24751ARHDR_QFN28_5X5
BAT54CW_SOT323~D
LODRV
IADAPT
ADP_I26
RTCVREF
2
PD2
27.4
PVCC
BTST
HIDRV
PH
REGN
PGND
LEARN
CELLS
SRP
SRN
BAT
TP
SRSET
100P_0402_50V8J~D
+COINCELL
12
Z4012
3
1
28
27
26
25
24
23
22
21
20
19
18
17
29
16
15
PR1
1K_0402_5%~D
PR226
340K_0402_1%~D
1 2
OVPSET
PR227
54.9K_0402_1%
1 2
210K_0402_1%~D
1 2
0.1U_0805_25V7M~D
PQ55
FDS4435BZ_SO8
8
S
D
7
S
D
6
S
D
5
G
D
PR221
340K_0402_1%~D
1 2
ACDET
PR223
54.9K_0402_1%
1 2
SI2301BDS-T1-E3_SOT23-3
PR228
100K_0402_1%~D
1 2
PC189
0.1U_0603_25V7K~D
REGN
PR53
1 2
+B+_BIAS
ACOFF
1 2
PC362
.1U_0402_16V7K~D
1
2
3
4
PC174
1 2
GATE
2
12
12
PR51
0_0402_5%~D@
VADJ
12
PR54
499K_0402_1%~D
PR396
100K_0402_1%~D
+3VALW
CP setting
ACSET
VREF
VIN
12
1 1
PR339
3.3_1210_5%~D
12
PR272
3.3_1210_5%~D
PC169
2.2U_0805_25V6K
1 2
PC170
0.01U_0603_50V7K~D
1 2
90W adapter
Icharge=(Vsrset/Vvdac)*(0.1/PR34)=3.34A
Iadapter=(Vacset/Vvdac)*(0.1/PR217)=3.1A
Input OVP : 22.3V
2 2
Input UVP : 16.98V
Fsw : 300KHz
VREF
PR229
47K_0402_1%~D
1 2
13
D
S
CELLS
CELLS
2
G
PQ61
SSM3K7002F_SC59-3
GND
VREF
3 Cell
4 Cell
ACGOOD#
3cell/4cell# 40
Cells selector
3 3
PR235
1 2
+B+
100_0805_5%~D
+5VALW
PR236
1 2
12
1 2
1SS355_SOD323-2
220K_0402_5%
470K_0402_5%~D
PQ64
2
G
PD9
PR238
1 2
32.8
220K_0402_5%
4 4
12
PC194
PR239
0.1U_0603_25V7K~D
CHGVADJ26
PQ63
TP0610K-T1-E3_SOT23-3
13
32.8
2
13
D
RHU002N06_SOT323
S
PC193
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
http://laptop-motherboard-schematic.blogspot.com/
MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
+B+
0.1U_0805_25V7K
1 2
PR220
2.2_0603_5%~D
1 2
DH_CHG
LX_CHG
PD8
RLS4148_LL34-2
REGN
12
PC183
1U_0603_10V6K~D
DL_CHG
CELLS
12
PC190
0.1U_0603_25V7K~D
PJP15
2
JUMP_43X118@
PC177
12
0.1U_0603_25V7K~D
FDS6690AS_NL_SO8
ACOFF 26
112
FDS8884_SO8
1 2
PC179
PQ57
PQ59
578
3 6
578
3 6
CHG_B+
PC1714.7U_1206_25V6K~D
1 2
241
10UH_SIL1045RA-100PF_4.5A_30%
1 2
@
12
PR394
12
@
241
PC361
ICHG setting
PR231
12
49.9K_0402_1%~D
12
PC191
0.01U_0402_25V7K~D
@
IREF Current
1 2
PR233
10_0603_5%~D
PC192
12
12
PR234
100K_0402_1%~D
2.968V 3A
COIN RTC Battery
PJP24
+RTCVCC
1
PC1
1U_0603_10V4Z~D
2
2006/10/1 2007/5/01
+COINCELL
Compal Secret Data
1
+
SUYIN_060003FA002G201NL~D
Deciphered Date
@
0.01U_0402_25V7K~D
12
PR218
100K_0402_1%~D
1 2
4
3
G
5
4
3
12
PC187
0.1U_0603_25V7K~D
RTCVREF
PR230
VREF
12
2
G
2
G
PR232
100K_0402_1%~D
1 2
13
D
PQ62
SSM3K7002F_SC59-3
S
VREF
PR237
100K_0402_1%~D
1 2
CHGEN#
13
D
PQ65
SSM3K7002F_SC59-3
S
Compal Electronics, Inc.
PQ58
S1S2S
FDS4435BZ_SO8
D8D7D6D
12
PC181
10U_1206_25V6M~D
E
BATT+
12
PC223
10U_1206_25V6M~D
@
ACIN 19,26,32
of
33 43Thursday, February 19, 2009
0.2
PC3161000P_0402_50V7K~D
PC1734.7U_1206_25V6K~D
1 2
0.02_2512_1%
1
2
10U_1206_25V6M~D
.1U_0402_16V7K~D
100K_0402_1%~D
PC168
/BATDRV
PR222
PC185
1 2
ACGOOD#
4.7_1206_5%~D
680P_0603_50V7K~D
12
PL18
-
PC3151000P_0402_50V7K~D
1 2
IREF 26
2
PC1724.7U_1206_25V6K~D
12
PC180
1 2
12
PC186
0.1U_0603_25V7K~D
FSTCHG26
Title
Size Document Number Rev
B
D
Date: Sheet
Page 34
5
+3VALWP, +5VALWP
4
3
2
1
+B+
PJP20
JUMP_43X118@
2
112
12
D D
+3VALWP
1
+
PC204
330U_D3L_6.3VM_R25M
C C
2
12
PC195
PC215
4.7U_1206_25V6K~D
0.1U_0603_25V7K~D
1 2
3.3UH_1164AY-3R3N-P3_7.5A_30%
PR244
0_0402_5%~D
1 2
PR247
10K_0402_1%~D
1 2
@
PL20
12
12
PC196
PC197
4.7U_1206_25V6K~D
2200P_0402_50V7K~D
PR241
4.7_1206_5%~D
PC206
680P_0603_50V8J~D
Rds(on) = 18m ohm(max) ; Rds(on) = 15m ohm(typical)
3.3VALWP
Imax=6A
VS
PD10
RLZ5.1B_LL34
1 2
Iocp=8.94A
B B
MAINPW O N40
2
1 3
PD16
1 2
A A
1SS355TE-17_SOD323-2
TPS51427_B+
12
12
PR251
100K_0402_1%~D
1 2
PQ74
TP0610K-T1-E3_SOT23-3
3 6
241
3 6
241
578
PQ66
AO4466_SO8
578
PQ68
AO4712_SO8
PR252
1 2
200K_0402_5%~D
PR259
0_0402_5%~D
PC205
0.1U_0603_25V7K~D
1 2
PC212
0.22U_0603_25V7K~D
1 2
VL
PR257
1 2
806K_0603_1%~D
12
1 2
12
PC213
PR240
0_0805_5%~D
1 2
0.1U_0603_25V7K~D
PR243
BST3A BST5A
12
2.2_0603_5%~D
LX3
DL3
FB3
VL
2VREF_TPS51427
1 2
PC211 0.22U_0603_10V7K~D
PR254
@
0_0402_5%~D
1 2
PR260
47K_0402_5%~D@
12
PC214
@
0.047U_0402_16V7K~D
0.047U_0603_16V7K~D
PC201
PR256
1 2
2VREF_TPS51427
1 2
PU16
33
26
24
25
23
30
32
1
8
20
4
14
27
0_0402_5%~D
PC308
6
VIN
TP
DRVH2
VBST2
LL2
DRVL2
VOUT2
REFIN2
VREF2
LDOREFIN
NC
EN_LDO
EN1
EN2
VREF3
5
12
1U_0603_10V6K~D
1 2
PC202
1U_0603_10V6K~D
3
V5FILT
TONSE
2
12
PR258
@
0_0402_5%~D
2VREF_TPS51427
VL
12
PC203
7
4.7U_0805_6.3V6K~D
19
LDO
V5DRV
DRVH1
VBST1
LL1
DRVL1
PGND
VOUT1
FB1
VSW
SKIPSEL
PGOOD2
PGOOD1
TRIP1
TRIP2
GND
SN0806081RHBR_QFN32_5X5
21
DH5DH3
15
17
LX5
16
DL5
18
22
10
FB5
11
9
29
28
13
TRIP1
12
TRIP2
31
578
PQ67
AO4466_SO8
3 6
241
PC207
1U_0603_10V6K~D
1 2
PR245
2.2_0603_5%~D
0.1U_0603_25V7K~D
12
PR249 0_0402_5%~D@
PR250 0_0402_5%~D
1 2
AO4712_SO8
PC208
1 2
12
PR253
309K_0402_1%
PR255
309K_0402_1%
578
PQ69
PR242
3 6
241
VL
POK 19
12
12
Rds(on) = 18m ohm(max) ; Rds(on) = 15m ohm(typical)
5VALWP
Imax=6A
Iocp=8.81A
TPS51427_B+
12
12
PC200
PC199
PC198
4.7U_1206_25V6K~D
4.7U_1206_25V6K~D
PL21
3.3UH_1164AY-3R3N-P3_7.5A_30%
12
4.7_1206_5%~D
12
PC209
680P_0603_50V8J~D
12
12
PC216
2200P_0402_50V7K~D
0.1U_0603_25V7K~D
PR246
1 2
61.9K_0402_1%~D
PR248
1 2
10K_0402_1%~D
12
+5VALWP
1
+
PC210
330U_D3L_6.3VM_R25M
2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLO SED TO ANY THI RD PART Y WITHO UT P RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
http://laptop-motherboard-schematic.blogspot.com/
2006/10/1 2007/05/30
3
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
Size D o cument Number Rev
2
Date: Sheet
LA-4596P
Thursday, February 19, 2009
1
of
34 43
0.2Custom
Page 35
5
D D
4
3
2
1
VCCPP_B++
12
PC217
C C
PR340
267K_0402_1%~D
EN_VCCP
PU23
TON
VOUT
V5FILT
VFB
PGOOD
1 2
1
EN_PSV
GND7PGND
PR342
BST_VCCP
1 2
2.2_0603_5%~D
15
14
TP
VBST
13
DRVH
12
LL
11
TRIP
10
V5DRV
9
DRVL
TPS51117RGYR_QFN14_3.5x3.5
8
UG_VCCP
LX_VCCP
TRIP_VCCP
1 2
10.2K_0402_1%~D
V5DRV_VCCP
LG_VCCP
PC319
1 2
0.1U_0603_25V7K~D
PR347
+5VALW
12
PR345
0_0603_5%~D
12
PC325
4.7U_0805_10V6K~D
PQ80
FDS6676AS_SO8
PR341
0_0402_5%~D
SUSP#25,26,29,30,37
PR344
300_0603_5%~D
+5VALW
B B
1 2
12
PR343
30.1K_0402_1%~D
12
PC324
1U_0603_10V6K~D
21.5K_0402_1%~D
12
PC320
.1U_0402_16V7K~D
@
12
PR349
12
PC326
47P_0402_50V8J~D
12
@
12
PR348
8.66K_0402_1%~D
TON_VCCP
V5FILT_VCCP
FB_VCCP
2
3
4
5
6
578
3 6
5
4
241
D8D7D6D
S1S2S3G
2200P_0402_50V7K~D
PQ79
FDS8884_SO8
PR346
4.7_1206_5%~D
1 2
1 2
12
12
PC318
PC317
10U_1206_25V6M~D
10U_1206_25V6M~D
PL29
1UH_FDUE1040D-1R0M-P3_21.3A_20%
1 2
PC323
680P_0603_50V8J~D
PJP25
12
JUMP_43X118
@
12
PC218
0.1U_0603_25V7K~D
+B+
FDS6676AS
Rds(on)=5.9mohm~7.25mohm
VCCPP
Imax=9A
Iocp=14.04A
Fsw=298KHz
PC321
1
12
+
2
4.7U_0805_6.3V6K~D
PC322
220U_D2_4VM
+VCCPP
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLO SED TO ANY THI RD PART Y WITHO UT P RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
http://laptop-motherboard-schematic.blogspot.com/
2008/2/5 2009/2/5
3
Compal Secret Data
Deciphered Date
Title
Size D o cument Number Rev
2
Date: Sheet
Compal Electronics, Inc.
+VCCPP
Thursday, February 19, 2009
LA-4596P
1
of
35 43
0.1
Page 36
5
D D
4
3
2
1
+1.8VP_B++
12
12
12
578
3 6
D6D5D7D
S
3
<BOM Structure>
FDS8884_SO8
241
8
S
S
2
1
PC219
2200P_0402_50V7K~D
PQ81
C C
PR350
267K_0402_1%~D
EN_1.8
PU24
TON
VOUT
V5FILT
VFB
PGOOD
1 2
15
1
EN_PSV
GND7PGND
PR352
BST_1.8
1 2
2.2_0603_5%~D
14
TP
VBST
DRVH
V5DRV
DRVL
TPS51117RGYR_QFN14_3.5x3.5
8
TRIP
UG_1.8
13
LX_1.8
12
LL
TRIP_1.8
11
V5DRV_1.8
10
LG_1.8
9
PC329
1 2
0.1U_0603_25V7K~D
PR357
1 2
12.1K_0402_1%~D
+5VALW
12
PR355
0_0603_5%~D
12
PC335
4.7U_0805_10V6K~D
PQ82
FDS6670AS_NL_SO8
4
G
PR351
PR354
300_0603_5%~D
1 2
0_0402_5%~D
12
PR353
30.1K_0402_1%~D
12
PC333
1U_0603_10V6K~D
21.5K_0402_1%~D
12
PC330
.1U_0402_16V7K~D
@
12
PR359
12
PC336
47P_0402_50V8J~D
12
@
PR358
30.1K_0402_1%~D
TON_1.8
V5FILT_1.8
FB_1.8
12
2
3
4
5
6
SYSON25,26,30
B B
+5VALW
PC327
PC328
10U_1206_25V6M~D
10U_1206_25V6M~D
PL30
1.8UH_SIL104R-1R8PF_9.5A_30%
1 2
PR356
4.7_1206_5%~D
1 2
PC334
680P_0603_50V8J~D
1 2
PJP26
12
JUMP_43X118
@
12
PC220
0.1U_0603_25V7K~D
+B+
FDS6670AS
Rds(on)=9mohm~11.5mohm
1.8VP
Imax=9A
Iocp=10.95A
Fsw=297KHz
PC331
1
12
+
2
4.7U_0805_6.3V6K~D
PC332
+1.8VP
220U_D2_4VM
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLO SED TO ANY THI RD PART Y WITHO UT P RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
http://laptop-motherboard-schematic.blogspot.com/
2006/10/1 2007/05/30
3
Compal Secret Data
Deciphered Date
Title
Size D o cument Number Rev
2
Date: Sheet
Compal Electronics, Inc.
+1.8VP
Thursday, February 19, 2009
LA-4596P
1
of
36 43
0.2
Page 37
5
D D
4
3
2
1
+1.5VSP_B++
12
12
12
PC221
3 6
3 6
241
241
2200P_0402_50V7K~D
PQ83
AO4466_SO8
C C
PR360
267K_0402_1%~D
EN_1.5
PU25
TON
VOUT
V5FILT
VFB
PGOOD
1 2
1
EN_PSV
GND7PGND
PR362
BST_1.5
1 2
2.2_0603_5%~D
15
14
TP
VBST
13
DRVH
12
LL
11
TRIP
10
V5DRV
9
DRVL
TPS51117RGYR_QFN14_3.5x3.5
8
UG_1.5
LX_1.5
TRIP_1.5
12K_0402_1%~D
V5DRV_1.5
LG_1.5
PC339
1 2
0.1U_0603_25V7K~D
PR365
1 2
+5VALW
12
PR366
0_0603_5%~D
12
PC345
4.7U_0805_10V6K~D
PQ84
AO4712_SO8
PR361
0_0402_5%~D
SUSP#25,26,29,30,35
PR364
300_0603_5%~D
+5VALW
B B
1 2
12
PR363
30.1K_0402_1%~D
12
PC343
1U_0603_10V6K~D
22.1K_0402_1%~D
12
PC340
.1U_0402_16V7K~D
@
12
PR369
12
PC346
47P_0402_50V8J~D
12
@
12
PR368
22.1K_0402_1%~D
TON_1.5
V5FILT_1.5
FB_1.5
2
3
4
5
6
578
578
PC337
PC338
10U_1206_25V6M~D
10U_1206_25V6M~D
2.2UH_PCMC063T-2R2MN_8A_20%
1 2
1 2
PL31
1 2
PR367
4.7_1206_5%~D
PC344
680P_0603_50V8J~D
PJP27
12
JUMP_43X118
@
12
PC222
0.1U_0603_25V7K~D
+B+
AO4712
Rds(on)=15mohm~18mohm
1.5VSP
Imax=3.5A
Iocp=6.87A
Fsw=298KHz
PC341
1
12
+
2
4.7U_0805_6.3V6K~D
+1.5VSP
PC342
220U_D2_4VM
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLO SED TO ANY THI RD PART Y WITHO UT P RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
http://laptop-motherboard-schematic.blogspot.com/
2008/2/5 2009/2/5
3
Compal Secret Data
Deciphered Date
Title
Size D o cument Number Rev
2
Date: Sheet
Compal Electronics, Inc.
+1.5VSP
Thursday, February 19, 2009
LA-4596P
1
of
37 43
0.2
Page 38
5
4
3
2
1
PC272
+1.8V
1
1
2
2
12
PC267
4.7U_0805_6.3V6K~D
2
G
12
PQ78
RHU002N06_SOT323
PJP17
JUMP_43X118@
1K_0402_1%~D
13
D
S
12
PR317
12
PR320
1K_0402_1%~D
12
PC270
.1U_0402_16V7K~D
PU20
VIN1VCNTL
2
GND
3
VREF
4
VOUT
APL5331KAC-TRL_SO8~N
+0.9VSP
12
PC271
1U_0603_10V6K~D
6
5
NC
7
NC
8
NC
9
TP
+3VALW
12
PC268
4.7U_0805_6.3V6K~D
D D
PR318
0_0402_5%~D
SUSP29,30
C C
1 2
@
.1U_0402_16V7K~D
B B
A A
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
http://laptop-motherboard-schematic.blogspot.com/
MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/10/1 2007/05/30
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
Size Document Number Rev
2
Date: Sheet
+0.9VSP
LA-4596P
Thursday, February 19, 2009
1
38 43
0.2Custom
of
Page 39
5
@
D D
DPRSLPVR7,19
H_DPRSTP#5,7,18
CLK_EN#
+3VS
+3VS
PR157
499_0402_1%~D
VGATE7,19,26
H_PSI#5
POW_MON 26
C C
PR165 4.22K_0402_1%@
VR_TT#
1 2
1U_0603_10V6K~D
100K_0603_1%_TH11-4H104FT@
1 2
PC1280.015U_0402_16V7K@
PC131
1000P_0402_50V7K~D
1 2
PC147
1 2
PR164 147K_0402_1%~D
1 2
PH2
1 2
PR166 11.5K_0402_1%~D
1 2
1 2
PR169 8.25K_0402_1%~D
1 2
12
PR156
1.91K_0402_1%~D
PR181 10K_0402_1%~D
1 2
PC1290.068U_0603_50V7K~N
1 2
PR143 499_0402_1%~D
PR144 0_0402_5%~D
PR145 0_0402_5%~D
1 2
PR154 0_0402_5%~D
1 2
12
PC121
1U_0603_10V6K~D
1
2
3
4
5
6
7
8
9
10
11
12
1 2
1 2
PGOOD
PSI#
PMON
RBIAS
VR_TT#
NTC
SOFT
OCSET
VW
COMP
FB
FB2
1 2
PC132 1000P_0402_50V7K~D
PR175 97.6K_0402_1%~D
1 2
B B
PC137 100P_0402_50V8J~D
12
PR184
100K_0402_1%~D
@
VCCSENSE5
PR177
1 2
100_0402_1%~D
PR179 1K_0402_1%~D
VSSSENSE5
PC134 270P_0402_50V7K~D
1 2
PC138 2200P_0402_50V7K~D
1 2
1 2
PR180 0_0402_5%~D
12
1 2
12
PR176
1K_0402_1%~D
PC140 330P_0402_50V7K~D
1 2
12
PC141
330P_0402_50V7K~D
@
1 2
PR183 0_0402_5%~D
PC143 180P_0402_50V8J~D
1 2
1 2
PR186 1K_0402_1%~D
VCC_PRM
A A
PC145
0.22U_0603_16V7K~D
4
PC112
12
5600P_0402_25V7K
48
46
47
49
3V3
GND
CLK_EN#
DPRSTP#
VR_ON
12
PR153
0_0402_5%~D
44
45
VR_ON
DPRSLPVR
ISL6266ACRZ-T_QFN48_7X7
CPU_VID6
12
12
PR1460_0402_5%~D
43
CPU_VID45CPU_VID3
CPU_VID5
12
PR1480_0402_5%~D
PR1470_0402_5%~D
26
12
VDIFF13VSEN14RTN15DROOP16DFB17VO18VSUM19VIN20GND21VDD22ISEN223ISEN1
12
PC139
12
PC142
0.01U_0603_25V7K~D
VSUM
12
1 2
PR187 3.57K_0402_1%~D
PC144 0.068U_0603_50V7K~N
PC146 0.22U_0603_10V7K~D
12
1 2
PR185
12
5
5
5
CPU_VID25CPU_VID15CPU_VID0
12
12
12
PR1490_0402_5%~D
PR1500_0402_5%~D
PR1510_0402_5%~D
BOOT1
PR1520_0402_5%~D
VID037VID138VID239VID340VID441VID542VID6
UGATE1
PHASE1
PGND1
LGATE1
PVCC
LGATE2
PGND2
PHASE2
UGATE2
BOOT2
NC
24
1 2
12
PR174 1_0603_5%~D
PC136
1U_0603_10V6K~D
PR178
1 2
10_0603_5%~D
0.1U_0603_25V7K~D
12
PR182
2.61K_0402_1%~D
PH3
10KB_0603_ERTJ1VR103J
11K_0402_1%~D
1 2
36
35
34
33
32
31
30
29
28
27
26
25
PU11
29.1
ISEN1
ISEN2
5
BOOT_CPU1
UGATE_CPU1
PHASE_CPU1
LGATE_CPU1
BOOT_CPU2
2.2_0603_5%~D
+5VS
+CPU_B+
3
2.2_0603_5%~D
LGATE_CPU2
PHASE_CPU2
UGATE_CPU2
PR167
1 2
12
12
PC118
PC117
1U_0603_10V6K~D
0.01U_0402_25V7K~D
PC122
0.22U_0603_10V7K~D
PR155
1 2
1 2
PC130
1 2
0.22U_0603_10V7K~D
12
PC119
0.01U_0402_25V7K~D
4
SI7636DP-T1-E3_SO8
+5VS
PR142
1_0603_5%~D
1 2
12
PC120
1U_0603_10V6K~D
5
PQ44
@
D
G
S3S
S
2
1
SI7636DP-T1-E3_SO8
PQ46
SI7686DP-T1-E3_SO8
5
PQ47
D
4
G
S3S
S
2
1
2
+CPU_B+
FBMA-L18-453215-900LMA90T_1812
1
12
12
PC114
10U_1206_25V6M~D
PQ43
SI7686DP-T1-E3_SO8
3 5
241
5
PQ45
D
4
G
S3S
S
2
1
3 5
241
5
D
4
G
S3S
12
PR158
12
PC123
SI7636DP-T1-E3_SO8
PC125
12
PQ48
12
S
2
1
SI7636DP-T1-E3_SO8
@
PC116
PC115
@
10U_1206_25V6M~D
4.7_1206_5%~D
680P_0603_50V8J~D
12
12
PC126
10U_1206_25V6M~D
PR168
4.7_1206_5%~D
PC133
680P_0603_50V8J~D
1
12
10U_1206_25V6M~D
P_0.36H_ETQP4LR36WFC_24A_20%
12
PR159
3.65K_1206_1%
VSUM
12
PC127
@
10U_1206_25V6M~D
10U_1206_25V6M~D
P_0.36H_ETQP4LR36WFC_24A_20%
12
PR171
VSUM
+
PC113
2
100U_25V_M
12
PR160
PR162 0_0402_5%~D@
10K_0402_1%~D
ISEN1
0.22U_0603_16V7K~D
12
12
PC227
2200P_0402_50V7K~D
12
PR170
PR173 0_0402_5%~D@
10K_0402_1%~D
3.65K_1206_1%
0.22U_0603_16V7K~D
ISEN2
+
2
1 2
1 2
PC228
1 2
1 2
PC155
100U_25V_M
PL14
PC124
0.1U_0603_25V7K~D
PL15
PC135
12
PC225
12
12
+CPU_B+
12
1 2
12
PC226
0.1U_0603_25V7K~D
2200P_0402_50V7K~D
PR161
1_0402_5%~D
VCC_PRM
12
PR172
1_0402_5%~D
VCC_PRM
1
PL13
+B+
+CPU_CORE
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLO SED TO ANY THI RD PART Y WITHO UT P RIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
http://laptop-motherboard-schematic.blogspot.com/
2007/1/15 2008/1/15
3
Compal Secret Data
Deciphered Date
Title
Size D o cument Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
+CPU_CORE
LA-4596P
0.2
of
39 43Thursday, February 19, 2009
1
Page 40
5
SM A R T
Ba t te r y:
1 .BA T +
2 .BA T +
3. I D
4 .B / I
5 . T S
6. S M D
7. S MC
8. G N D
9. G N D
4
3
2
1
1
PD12
2
3
3cell/4cell# 33
PJSOT24C_SOT23-3
PR326
1K_0402_5%~D
EC_SMB_DA1 26
EC_SMB_CK1 26
D D
C C
BATT+
PL28
SMB3025500YA_2P
BATT+
1 2
12
12
PC278
0.01U_0402_25V7K~D
PC309
100P_0402_50V8J~D
PJPB1 battery connector
12
PC279
PJP19
10
GND
11
GND
SUYIN_200275MR009G186ZL
@
BATT++
1000P_0402_50V7K~D
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
BATT++
12
PC310
100P_0402_50V8J~D
3cell/4cell#
+3VALWP
1 2
1 2
PR328
100_0402_5%~D
1 2
PR329
100_0402_5%~D
PR324
47K_0402_5%~D
1
PD13
PJSOT24C_SOT23-3
2
3
Battery Connect/OTP
Place clsoe to EC pin
BATT_TEMP
1 2
PR325
1K_0402_5%~D
12
1 2
PR327
6.49K_0402_1%~D
PC280
.1U_0402_16V7K~D
1 2
@
+3VALWP
BATT_TEMP 26
CPU
PH1 under CPU botten side :
CPU thermal protection at 90 +-3 degree C
Recovery at 50 +-3 degree C
BATT+
12
PR330
453K_0402_1%~D
VS
12
PR332
499K_0402_1%~D
PC282
0.01U_0402_25V7K~D
12
PR337
86.6K_0402_1%
PC283
1000P_0402_50V7K~D
0
8
LM358ADR_SO8
5
P
+
6
-
G
4
12
B B
PR398
10K_0402_1%~D
PU22B
7
12
BATT_OVP26
VL VS
12
CPU
12
PR331
10.7K_0402_1%~D
PR335
61.9K_0402_1%~D
1 2
1 2
VL
12
PH4
100K_0603_1%_TH11-4H104FT
PR336
150K_0402_1%~D
150K_0402_1%~D
PR338
PR333
147K_0402_1%~D
1 2
12
12
8
3
P
+
0
2
-
G
PU22A
4
LM358ADR_SO8
PC284
1U_0603_10V6K~D
PC281
0.1U_0603_25V7K~D
1 2
PD11
1
1 2
1SS355_SOD323-2
VL
1 2
PR334
205K_0402_1%~D
MAINPWON 34
LI-3S :13.5V----BATT-OVP=1.5V
BATT-OVP=0.111*BATT+
A A
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
http://laptop-motherboard-schematic.blogspot.com/
MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/10/1 2007/05/30
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
BATTERY CONN
Size Document Number Rev
2
Date: Sheet
LA-4596P
Thursday, February 19, 2009
1
40 43
0.2Custom
of
Page 41
5
Page 1/1
Solution Description Rev.Page# Title
Version Change List ( P. I. R. List )
Item Issue DescriptionDate
Request
Owner
4
3
2
1
1
D D
2
3
4
5
6
7
8
9
10
11
12
C C
13
14
15
16
17
18
19
20
21
22
23
B B
24
25
26
27
28
29
30
31
32
33
A A
32
33
40
32 DCIN /Vin Detector 08/12/12 COMPAL
35
36
37
35
36
37
DCIN /Vin Detector
Charger
BATTERY CONN
VCCPP
1.8VP
1.5VSP
VCCPP
1.8VP
1.5VSP
08/12/08
08/12/08
08/12/08
08/12/08
08/12/12
08/12/12
08/12/12
08/12/18
08/12/18
08/12/18
COMPAL
COMPAL
COMPAL
COMPAL
COMPAL
COMPAL
COMPAL
COMPAL
COMPAL
COMPAL
common circuit design modify
design modify
vendor FAE suggest
design modify
increase capacitor for EMI request
change resister for EMI request
change resister for EMI request
change resister for EMI request
add resister and capacitor for EMI request
add resister and capacitor for EMI request
add resister and capacitor for EMI request
change PR203 from 33 to 68 and add PR204 to 68
change PL17 from SM010018880 to SM010008E10
change PR272 PR339 from 1 to 3.3
change PL28 from SM010018210 to SM010008E10
add PC313 at 0.01uf and PC314 at 0.1uf 0.3
change PR342 from 0 to 2.2
change PR352 from 0 to 2.2
change PR362 from 0 to 2.2
add PR346 at 4.7and pc323 at 680p
add PR356 at 4.7and pc334 at 680p
add PR367 at 4.7and pc344 at 680p
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
http://laptop-motherboard-schematic.blogspot.com/
MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/1/15 2008/1/15
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet
Compal Electronics, Inc.
PW PIR-1
LA-4596P
1
0.2
of
41 43Thursday, February 19, 2009
Page 42
5
Page 1/1
Solution Description Rev.
Page# Title
Version Change List ( P. I. R. List )
Item Issue DescriptionDate
Request
Owner
4
3
2
1
D D
C C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
28 Compal_HW2008/12/02U SB/BT/ FP/ Felica/Camera Modify Pin definition of JUSBP3
24 Compal_HWHDA-IDT_92HD81 20 08/12/02 Modify Pin definition of JSPK1
Small USB board no function
R voice and L voice fail
Switch function fail27 PWR_OK/ BTN/ KB / TP/TPM1.2 2008/12/02 Co mpal_HW Modify Pin definition of SW1
Compal_HW2008/12/16LAN-8111D21 EMI LAN test fail Add C1817-C1820 for LAN connector
S5 wake on Wirlesslan failCompal_HW2008/12/1623 Mini-Card/WWAN/Roboson Add U89 to control wirless lan voltage
0.2
0.2
0.2
0.2
0.2
B B
23
24
25
26
27
28
29
30
31
32
A A
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
http://laptop-motherboard-schematic.blogspot.com/
MAY BE USED BY OR DIS CLOSE D TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2008/03/21 2009/03/21
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
EE_PIR-1
Size Document Number Rev
Custom
LA-4592P
2
Date: Sheet
42 43Thursday, February 19, 2009
1
0.2
of
Page 43
5
4
3
2
1
ACIN/BATT-IN
+5VALW/+3VALW
EC_ON
D D
ON/OFF
STB_SB (Control +3V_SB)
+3V_SB
RSMRST#
T1>20ms
WOL_EN(Control +3VLAN)
+3VLAN
SYSON(Control +3V/+1.8V)
C C
+3V/1.8V
T2=40ms
PWRBTN_OUT#
SLP_S5#
T3<110ms
SLP_S4#
SLP_S3#
SUSP#
T4=20ms
+5VS>3VS>1. 5VS>1.25VS>+1.2VS>VCCP>0.9VS
VR_ON#/VGA_ON
B B
+CPU_CORE
VGATE(IMVP to S B for VRMPWRGD/to EC for CPUCORE PWRGD)
CK_PWRGD(SB to CLK-GEN; Local AND of VRMPWRGD and S3 )
PM_PWROK(EC to SB/NB)
T5>30ms
T8>99ms
T9>3ms
T6= ~7ms
100ns>T7>0ns
T10>70ms
H_PWRGOOD(SB t o CPU; Local A ND of VRMPWRGD and PWROK)
PLTRST#(SB to NB/Device)
H_RESET#(NB to CPU)
VGA_ON
A A
41RTCCLK>T11>34RTCCLK
T12>1ms
T13>30ms
+VGA_CORE
VGA_PWGOD(Tur n on 1.8VS for VRAM/VGA)
T14= ~7ms
+1.8VS
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS , INC. AND CONTAINS CO NFIDENTIAL
AND TRADE SECRET IN FO RM AT IO N. TH IS SH EE T M A Y N OT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHE R THIS SHEET NO R THE INFORMAT ION IT CONTAI NS
5
4
http://laptop-motherboard-schematic.blogspot.com/
3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTE N CONSENT OF COMPAL ELEC TRONICS, IN C.
Compal Secret Data
2008/03/21 2009/03/21
2
Deciphered Date
Compal Electronics, Inc.
Title
Power On Sequence
Size Document Number Rev
Custom
LA-4592P
Date: Sheet
1
of
43 43Thursday, Fe bruary 19, 2009
0.2
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