Datasheet WMS7120, WMS7121 Datasheet (winbond)

查询WMS7120供应商

NON-VOLATILE DIGITAL POTENTIOMETERS

PRELIMINARY DATASHEET

WMS7120 / 7121

WITH UP/DOWN (3-WIRE) INTERFACE,

10KOHM, 50KOHM, 100KOHM RESISTANCE

64 TAPS

WITHOUT / WITH OUTPUT BUFFER

Publication Release Date: July 2003

- 1 - Revision 1.0

WMS7120 / 7121

1. GENERAL DESCRIPTION

The WMS7120/7121 is a single channel 64-tap non-volatile linear digital potentiometer available in
10KΩ, 50KΩ and 100KΩ resistance. The device consists of Up/Down serial interface, tap register,
decoder, resistor array, wiper switches, NV memory and control logics.

The WMS7120 device can be configured as a two-terminal variable resistor or a three-terminal voltage
divider without an output buffer, but the WMS7121 device, which has a built-in output buffer, can only
be configured as a three-terminal voltage divider. Both devices can be used in a wide variety of
applications.

The output of the potentiometer is determined by its wiper position, which varies linearly between its
end terminals, R

(

CS , INC and U/ D ) through the Tap Register (TR). In addition, the wiper position can also be

stored into a non-volatile memory location (NVMEM0), which is then automatically recalled upon
power up.

2. FEATURES

and RB/VB. The wiper position, Rw/Vw, is controlled by Up/Down serial interface

A/VA

• Drop-in replacement for many popular parts

• Single linear-taper channel

• 64 taps

• 10K, 50K and 100K end-to-end resistance

• V

• Automatic recall of wiper position when power-on

• Potentiometer control through Up/Down (3-wire) serial interface

• Endurance 100,000 cycles

• Data retention 100 years

• Package options:

• Industrial temperature range: -40° to 85°C

• Single supply operation : 2.7V to 5.5V

to VDD terminal voltages

SS

- 8-pin PDIP, SOIC or MSOP

- 2 -

r

3. BLOCK DIAGRAM

INC

CS

U /D

V

SS

INC

CS

U/D

Up/Down

Serial

Interface

NV Memory

Control

FIGURE 1 – WMS7120 BLOCK DIAGRAM (Rheostat/Divider Mode)

Up/Down

Serial

Interface

V

SS

NV Memory

Control

FIGURE 2 – WMS7121 BLOCK DIAGRAM (Divider Mode)

WMS7120 / 7121

RA/V

A

RW/V

W

Decoder

Tap Register

NV Memory

Tap Register

NVMEM0

Decode

NV Memory

NVMEM0

RB/V

V

DD

V

A

V

W

V

B

V

DD

B

Publication Release Date: July 2003

- 3 - Revision 1.0

WMS7120 / 7121

4. TABLE OF CONTENTS

1. GENERAL DESCRIPTION.................................................................................................................. 2

2. FEATURES ......................................................................................................................................... 2

3. BLOCK DIAGRAM............................................................................................................................... 3

4. TABLE OF CONTENTS ...................................................................................................................... 4

5. PIN CONFIGURATION ....................................................................................................................... 5

6. PIN DESCRIPTION ............................................................................................................................. 6

7. FUNCTIONAL DESCRIPTION............................................................................................................ 7

7.1. Rheostat And Divider Operations ........................................................................................... 7

7.1.1. Rheostat Configuration .......................................................................................................... 7

7.1.2. Divider Configuration.............................................................................................................. 7

7.2. Non-Volatile Memory (NVMEM0) ........................................................................................... 7

7.3. Serial Data Interface ................................................................................................................. 8

7.4. Operation Overview .................................................................................................................. 8

8. TIMING DIAGRAMS............................................................................................................................ 9

9. ABSOLUTE MAXIMUM RATINGS & OPERATING CONDITIONS .................................................. 11

10. ELECTRICAL CHARACTERISTICS ............................................................................................... 12

10.1 Test Circuits ............................................................................................................................ 14

11. TYPICAL APPLICATION CIRCUITS............................................................................................... 15

11.1. Layout Considerations.......................................................................................................... 17

12. PACKAGE DRAWINGS AND DIMENSIONS.................................................................................. 18

13. ORDERING INFORMATION........................................................................................................... 21

14. VERSION HISTORY ....................................................................................................................... 22

- 4 -

5. PIN CONFIGURATION

WMS7120 / 7121

R

INC

U/D

A/VA

V

R

SS

INC

U/D

A/VA

1

2

3

4

8-MSOP

V

8

DD

CS

7

6

R

B/VB

5

Rw/V

W

1

INC

2

U/D

R

3

A/VA

V

45

SS

8

V

DD

CS

7

R

6

B/VB

Rw/V

W

8-SOIC

1

2

3

V

8

DD

7

CS

6

R

B/VB

45

V

SS

8-PDIP

Rw/V

W

Publication Release Date: July 2003

- 5 - Revision 1.0

6. PIN DESCRIPTION

Pin Name Description

WMS7120 / 7121

TABLE 1 – PIN DESCRIPTION

Chip Select: When

CS

U/D

INC

RA/VA

RB/VB

RW/VW

VSS Ground pin, logic ground reference

VDD Power Supply

Notes: The terminology of high and low terminals above references to the relative

position of the terminal with respect to the wiper moving direction and not the
voltage potential of the terminal.

When
standby mode

Up/Down Control: HIGH state enables the wiper to
move towards the R
implies the wiper moves towards the R

Increment Control: When

transition on

either up or down based on the U/

High terminal of the device

Low terminal of the device

Wiper Terminal: Output of the resistor array is determined

by the

CS is HIGH, the part is deselected and is in

INC will move the wiper one increment

INC , U/ D and CS inputs

CS is LOW, the device is enabled.

/ VA terminal, while LOW state

A

/ VB terminal

B

CS is LOW, a HIGH-LOW

D input

- 6 -

WMS7120 / 7121

7. FUNCTIONAL DESCRIPTION

7.1. RHEOSTAT AND DIVIDER OPERATIONS

The WMS7120 device can operate as either a two-terminal variable resistor or a three-terminal
voltage divider without an output buffer. However, the WMS7121 can only operate in a three-terminal
voltage divider with an output buffer.

7.1.1. Rheostat Configuration

In the rheostat mode, the WMS7120 can be configured as a two-terminal resistive element, where one
terminal is connected to one end of the resistor (R

The moving direction of the wiper depends upon the setting of U/

set to Up, then the wiper moves towards R

wiper moves towards R

. The wiper movement to either direction is controlled by toggling the INC

B

A

signal from HIGH to LOW.

This configuration controls the resistance between the wiper and either end. The wiper resistance can
be adjusted by either changing the wiper position or loading a stored wiper position value from
NVMEM0 upon power up.

or RB) and the other terminal is the wiper (RW).

A

D control signal. When the U/ D is

. Conversely, when the U/ D is set to Down, then the

7.1.2. Divider Configuration

Additionally, the WMS7120 can also be configured as a voltage divider. With an input voltage applied
to one end (usually V
cannot exceed the V
to the wiper position with respect to the voltage difference between V

the wiper depends upon the setting of the U/

wiper moves towards V

. The wiper movement to either direction is controlled by toggling the INC signal from HIGH to

V

B

), the ground is connected to the other end (usually VB). These input voltages

A

level or go below the VSS level. The voltage on the wiper, VW, is proportional

DD

and VB. The moving direction of

A

D control signal. When the U/ D is set to Up, then the

. Conversely, when the U/ D is set to Down, then the wiper moves towards

A

LOW.

Nevertheless, the WMS7121 can only be configured as a voltage divider and operate similarly as the
WMS7120 device. The only difference is WMS7121 has an output buffer, but WMS7120 doesn’t have.

Besides, the resistance cannot be directly measured in this configuration.

7.2. NON-VOLATILE MEMORY (NVMEM0)

The WMS7120/7121 has one NVMEM0 location available for storing the current wiper position via the
Up/Down serial interface. This stored value is automatically recalled and loaded into the tap register
upon power up.

Publication Release Date: July 2003

- 7 - Revision 1.0

WMS7120 / 7121

7.3. SERIAL DATA INTERFACE

The WMS7120/7121 device has a 3-wire Up/Down Serial Interface consisting of CS , INC and U/D
control signals. The key features of this interface include:

• Enabling the device

• Determining the moving direction of the wiper

• Increment/Decrement operation on the wiper

• Non-volatile storage of the present wiper position into the NVMEM0 for automatic recall at

power up

• Entering into the standby mode

7.4. OPERATION OVERVIEW

The wiper position can be changed either up or down by operating the CS , U/D and INC control
signals.

When

result, the wiper moves up when U/

U/
device and then move the wiper position either up or down until the desired position is reached.

When the wiper is already at the lowest position, further Down operation won’t change the wiper
position. Similarly, when the wiper is at the highest position, further Up operation won’t change the
wiper position too.

The current wiper position can be automatically stored into the NVMEM0 each time the

from LOW to HIGH while the
HIGH, the wiper position cannot be stored. Meanwhile, the NVMEM0 content is automatically loaded
into the wiper during power on.

When the

changed. Changing the CS to LOW exits the Standby mode and enables the device again.

The operating modes of Up/Down interface are summarized in the table below:

CS is LOW, the device is selected and the wiper can be moved by toggling the INC . As a

D is HIGH and moves down when U/D is LOW. The status of the

D can be changed even though the CS remains LOW. This allows the system to enable the

CS goes

INC remains HIGH. Adversely, if the INC is LOW when the CS goes

CS is held HIGH, the device enters into Standby mode and the wiper position cannot be

CS

LOW HIGH HIGH to LOW Move Wiper toward RA /VA

LOW LOW HIGH to LOW Move Wiper toward RB /VB

U/D INC

Operation

LOW to HIGH x HIGH Store Current Wiper Position

LOW to HIGH x LOW No Store, Return to Standby

HIGH x x Standby

Note: x means don’t care

- 8 -

8. TIMING DIAGRAMS

[2]

[1]

WMS7120 / 7121

Conditions: V

CS

INC

U

/D

Note:

[1]

[2]

wiper position.

V

W

This only applies to the Power-Up sequence.

MI in the AC Timing diagram (Figure 3) refers to the minimum incremental change in the wiper output due to a change in the

= +2.7V to 5.5V, VA = VDD, VB = 0V, T = 25°C

DD

t

PUD

t

C

t

CI

W

t

I

YC

L

t

I

FIGURE 3 –WMS7120/1 TIMING DIAGRAM

t

I H

t

DI

t

ID

t

CI

(store)

t

CPH

90%

10%

t

F

90%

t

R

MI

Publication Release Date: July 2003

- 9 - Revision 1.0

PARAMETERS SYMBOL MIN. MAX. UNITS

CS to INC Setup

U/D to INC Setup

U/D to INC Hold

INC LOW Period

INC HIGH Period

INC Inactive to CS Inactive

CS Deselect Time (NO STORE)

TABLE 10 – TIMING PARAMETERS

t

100 ns

CI

t

50 ns

DI

t

100 ns

ID

t

250 ns

IL

t

250 ns

IH

t

1

IC

t

100 ns

CPH

WMS7120 / 7121

µs

CS Deselect Time (STORE)

INC to Wiper Change

INC Cycle Time

INC Input Rise and Fall Time

Power-Up Delay t

VCC Power-Up rate tR VCC

15 (2.7V)

t

t

t

R

CPH

t

IW

CYC

, t

PUD

30 (5.5V)

5

1

F

500

1 ms

0.2

(13ms

0-2.7V)

ms

50

(54µs

0-2.7V)

µs

µs

µs

V/ms

- 10 -

WMS7120 / 7121

9. ABSOLUTE MAXIMUM RATINGS & OPERATING CONDITIONS

TABLE 11 – ABSOLUTE MAXIMUM RATINGS (PACKAGED PARTS)

Conditions Values

Junction temperature 150ºC

Storage temperature -65º to +150ºC

Voltage applied to any pad (Vss – 0.3V) to (VDD + 0.3V)

Lead temperature (soldering – 10 seconds) 300ºC

VSS – VDD -0.3 to 7.0V

TABLE 12 – OPERATING CONDITIONS (PACKAGED PARTS)

Conditions Values

Industrial operating temperature -40ºC to +85ºC

[1]

Supply voltage (VDD) +2.7V to +5.5V

Ground voltage (VSS) 0V

[1]

Stresses above those listed may cause permanent damage to the device. Exposure to the absolute maximum

ratings may affect device performance and reliability. Functional operation is not implied at these conditions.

Publication Release Date: July 2003

- 11 - Revision 1.0

WMS7120 / 7121

10. ELECTRICAL CHARACTERISTICS

TABLE 12 – ELECTRICAL CHARACTERISTICS (Packaged parts)

Total

[7]

Total

[5]

[7]

PARAMETERS SYMBOL MIN. TYP. MAX. UNITS CONDITIONDS

Rheostat Mode

Nominal Resistance R -20 +20 % T=25ºC, Wiper open

Different Non Linearity

Integral Non Linearity

Tempo

Wiper Resistance

[1]

[2]

[2]

[2]

R-DNL -1

R-INL -1

∆RAB/∆T

300

±0.2

±0.4

+1 LSB

+1 LSB

ppm/°C

RW 50 Ω VDD=5V, I=VDD/R

[6]

[6]

80 Ω VDD=2.7V, I=VDD/R

Wiper Current IW -1 1 mA

Divider Mode

Resolution N 8 Bits

[2]

[2]

[1]

∆W /∆T

Different Non Linearity

Integral Non Linearity

Temperature Coefficient

Full Scale Error V

Zero Scale Error V

DNL -1

INL -1

±0.5

±0.5

+20

-1 0 LSB Wiper at highest position

FSE

0 1 LSB Wiper at lowest position

ZSE

+1 LSB

+1 LSB

ppm/°C

Wiper at center

Resistor Terminal

Voltage Range VA, VB, VW VSS V

[1]

[1]

[1]

CA, CB 30 pF

30 pF

1.5 MHz VDD=5V, B =VSS

10K

50K

200 KHz

100K

300 KHz Wiper at center

Terminal Capacitance

Wiper Capacitance

Dynamic Characteristics

BW

Bandwidth –3dB BW

BW

V

DD

Analog Output (Buffer enables)

Amp Output Current I

Amp Output Resistance Rout

Total Harmonic Distortion

[1]

3 mA VO=1/2 scale

OUT

THD 0.08 %

1 10 Ω I

= 100uA

L

A =2.5V, V
V

=1V

IN

RMS

=5V, f=1kHz,

DD

Digital Inputs/Outputs

Input High Voltage VIH 0.7xVDD V

Input Low Voltage VIL

0.3xVDD V

Output Low Voltage VOL 0.4 V IOL=2mA

- 12 -

WMS7120 / 7121

TABLE 12 – ELECTRICAL CHARACTERISTICS (Packaged parts) – Cont’d

PARAMETERS SYMBOL MIN. TYP. MAX. UNITS CONDITIONDS

Input Leakage Current ILI -1 +1 uA

I

Output Leakage Current

Input Capacitance

Output Capacitance

[1]

[1]

-1 +1 uA

Lo

CIN 25 pF VDD=5V, fc = 1Mhz

C

25 pF VDD=5V, fc = 1Mhz

OUT

CS =V

CS =V

,Vin=Vss ~ VDD

DD

,Vin=VSS ~ VDD

DD

Power Requirements

Operating Voltage VDD 2.7 5.5 V

Operating Current I

, I

DDR

1 2 mA All operations

DDW

[3]

I

0.5 1 mA

SA

Buffer = ON

CS = HIGH, no load

Standby Current

[4]

I

0.1 1 uA

SB

Buffer = OFF

CS = HIGH, no load

[5]

Power Supply Rejection
Ratio

Notes:

[1]

Not subject to production test.

[2]

LSB = (RA/VA – RB/VB) / (T - 1); DNL = (Vi - V

) / LSB - 1 (if decrement); INL = (Vi - i*LSB) / LSB; where i = [0, (T -1)] and T =

V

i+1

# of taps of the device.

[3]

WMS7121 only.

[4]

WMS7120 only.

[5]

Conditions: VCC = 2.7 to 5.5V, T = 25ºC and timing measured at 50% level, unless stated.

[6]

Only guarantee by design.

[7]

R

= end-to-end resistance.

total

PSRR 1 LSB/V

) / LSB + 1 (if increment) or = (Vi -

i+1

V

=5V±10%, Wiper at center

DD

Publication Release Date: July 2003

- 13 - Revision 1.0

10.1 TEST CIRCUITS

y

(

q

W

*

V+ = VDD

V

MS

I

= V

DD

IW

R

= V

W

=

+

VMS*

error

IW

*

/R

Total

/I

MS

W

FIGURE 4 – TEST CIRCUITS

VA

V+

V

V

B

WMS71xx

*Assume infinite input impedance

Potentiometer divider nonlinearit
test circuit

INL, DNL)

No Connection

WMS71xx

RA

R

W

R

B

*Assume infinite input impedance

Resistor position nonlinearity error test
circuit (Rheostat Operation: R-INL, R-DNL)

V

VA

V

W

V

B

WMS71xx

*Assume infinite input impedance

Wiper resistance test circuit

WMS7120 / 7121

V

A

+

V

Power supply sensitivity test circuit (PSS, PSRR)

V

A

V

B

WMS71xx

*Assume infinite input impedance

V

A

W

~

V

IN

2.5V DC
Offset

Capacitance test circuit

~

V

IN

OFFSET

GND

2.5V DC

Gain vs. fre

VA = VDD
V+= VDD ± 10%
PSRR(dB) = 20LOG ( )

PSS(%/% ) =

V

W

∆
∆

VMS*

WMS71xx

VB

+5V

V

W

WMS71xx

V

A

V

W

V

B

+5V

uency test circuit

V
V

MS
DD

V

∆
∆

V
V

OUT

V

MS

DD

OUT

- 14 -

WMS7120 / 7121

A

_

A

_

11. TYPICAL APPLICATION CIRCUITS

Vin

WMS71XX

B

V

R

= - VIN

OUT

R

RA = , RB =

= Total resistance of potentiometer

AB

R

A

R

(64-W)

AB

64 64

W = Wiper setting for WMS71XX

FIGURE 5 – PROGRAMMABLE INVERTING GAIN AMPLIFIER USING THE WMS7120/7121

V

B

V

OUT

= VIN (1+

RAB (64-W)

RA = , RB =

R

= Total resistance of potentiometer

AB

R

)

A

R

64 64

W = Wiper setting for WMS71XX

IN

RA RB

RAB*W

RA R

WMS71XX

R

*W

AB

OP

V

OUT

MP

+

+

OP

MP

B

V

OUT

FIGURE 6 – PROGRAMMABLE NON-INVERTING GAIN AMPLIFIER USING THE WMS7120/7121

Publication Release Date: July 2003

- 15 - Revision 1.0

WMS7120 / 7121

V+

FILTER

V

REF = 5.0v

RF Input

C2

L1
CHOKE

Q1

RF POWER AMP

RF OUT

CS\
INC\

U/D\

WMS71xx

V

REFH

Vout

5V

0V

GND

FIGURE 7 – WMS7121 TRIMMING VOLTAGE REFERENCE

C1

V

RA/V

RB/V

0.1uF

DD

A

W

B

CS\
U/D\

RW/V

INC\
V

SS

WMS71xx WINPOT

FIGURE 8 – WMS7121 RF AMP CONTROL

- 16 -

WMS7120 / 7121

11.1. LAYOUT CONSIDERATIONS

Use a 0.1µF bypass capacitor as close as possible to the VDD pin. This is recommended for best
performance. Often this can be done by placing the surface mount capacitor on the bottom side of the
PC board, directly between the V
digital traces. Sensitive traces should not run under the device or close to the bypass capacitors.

A dedicated plane for analog ground helps in reducing ground noise for sensitive analog signals.

and VSS pins. Care should be taken to separate the analog and

DD

DIGITAL

CONTROL LINES

ANALOG

SIGNAL LINE

R

INC

U/D

A/VA

V

SS

CAP

FIGURE 9 – WMS7120/7121 LAYOUT

V

CS

R

B/VB

RW/V

DD

DIGITAL

CONTROL LINE

ANALOG

SIGNAL LINES

W

Publication Release Date: July 2003

- 17 - Revision 1.0

12. PACKAGE DRAWINGS AND DIMENSIONS

WMS7120 / 7121

8

1

5

E

4

Control demensions are in milmeters .

E

θ

FIGURE 10: 8L 150MIL SOIC

- 18 -

WMS7120 / 7121

8

E

1

D

5

A

L

1

S

4

B

B

1

E

c

2

A

e

1

Symbol

A
A
A
B
B
c
D

E
E

e
L

α

e

S

Dim en sio n in in ch D im ens ion in m m

Min

0.010

1

2

1

0.125

0.016

0.008

1

1

A

0.245

0.100

0.120

15

0

0.335

Base Plane

A

1

Seating Plane

Nom

Max Max

0.175

0.130

0.135

0.018

0.022

0.060 1.52

0.0640.058

0.010

0.014

0.360 0.380

0.310

0.3000.290

0.255

0.250

0.110

0.140

0.130

0.375

0.355

0.045

Min

0.25

3.18

0.41

0.20

7.37

6.22

2.29 2.54 2.790.090

3.05

8.51

Nom

3.30

0.46

0.25

9.14

7.62

3.30

9.02

4.45

3.43

0.56

1.631.47

0.36

9.65

7.87

6.486.35

3.56

150

9.53

1.14

e

A

α

FIGURE 11: 8L 300MIL PDIP

Publication Release Date: July 2003

- 19 - Revision 1.0

WMS7120 / 7121

FIGURE 12: 8L 3MM MSOP

- 20 -

13. ORDERING INFORMATION

Winbond’s WinPot Part Number Description:

WMS71

T B RRR P

WMS7120 / 7121

Winbond WinPot Products w/ Up-Down Interface

Number Of Taps:

2 = 64

For Up/Down interface:

0 : No buffer

1 : With buffer

End-to-end Resistance:

010: 10Kohm

050: 50Kohm

100: 100Kohm

Package:

S: SOIC

P: PDIP

M: MSOP

Output

Buffer

NO

YES

Notes:

Part number with white background: Available for sampling and mass production.

Part numbers with shaded background: Call factory for availability.

End-to-End
Resistance

10K

50K

100K

10K

50K

100K

SOIC PDIP MSOP

WMS7120010S WMS7120010P WMS7120010M

WMS7120050S WMS7120050P WMS7120050M

WMS7120100S WMS7120100P WMS7120100M

WMS7121010S WMS7121010P WMS7121010M

WMS7121050S WMS7121050P WMS7121050M

WMS7121100S WMS7121100P WMS7121100M

For the latest product information, access Winbond’s worldwide website at
http://www.winbond-usa.com

Publication Release Date: July 2003

- 21 - Revision 1.0

WMS7120 / 7121

r

r

r

jury

14. VERSION HISTORY

VERSION DATE DESCRIPTION

1.0 July 2003 Initial issue

The contents of this document are provided only as a guide for the applications of Winbond
products. Winbond makes no representation or warranties with respect to the accuracy o
completeness of the contents of this publication and reserves the right to discontinue or make
changes to specifications and product descriptions at any time without notice. No license, whethe
express or implied, to any intellectual property or other right of Winbond or others is granted by this
publication. Except as set forth in Winbond's Standard Terms and Conditions of Sale, Winbond
assumes no liability whatsoever and disclaims any express or implied warranty of merchantability,
fitness for a particular purpose or infringement of any Intellectual property.

Winbond products are not designed, intended, authorized or warranted for use as components in
systems or equipments intended for surgical implantation, atomic energy control instruments,
airplane or spaceship instruments, transportation instruments, traffic signal instruments,
combustion control instruments, or for other applications intended to support or sustain life.
Further, Winbond products are not intended for applications wherein failure of Winbond products
could result or lead to a situation wherein personal injury, death or severe property o
environmental in

could occur.

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Taipei Office Winbond Electronics Corporation Japan Winbond Electronics (H.K.) Ltd.

9F, No. 480, Pueiguang Rd. 7F Daini-ueno BLDG. 3-7-18 Unit 9-15, 22F, Millennium City,
Neihu District Shinyokohama Kohokuku, No. 378 Kwun Tong Rd.,
Taipei, 114 Taiwan Yokohama, 222-0033 Kowloon, Hong Kong
TEL: [phone] TEL: [phone] TEL: [phone]
FAX: [phone] FAX: [phone] FAX: [phone]

Please note that all data and specifications are subject to change without notice.
All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.
This product incorporates SuperFlash

®

technology licensed from SST.

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