Datasheet VV6850, VV5850 Datasheet (Vision)

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VISION

VV6850 & VV5850 Monolithic Sensors

High resolution CMOS Image Sensor with support for external FPN

PRODUCT DATASHEET Revision 1.0

DISTINCTIVE CHARACTERISTICS

GENERAL DESCRIPTION

cancellation and serial interface control, available in colour (6850) and

BLOCK DIAGRAM

monochrome (5850) versio ns.

The VV6850 and VV5850 are highly inte­grated CMOS camera devices. The devices
both incorporate a 1016 x 804 pixel array
image sensor configured to produce line by
line pixel output for external digitisation and
storage.

The VV6850 is colourised in a Red, Green,
Blue Bayer pattern, whereas the VV5850 is
uncolourised. Both are suitable for still image
capture applications, and applications requir­ing digitisation of the pixel image.

All clocking and sequencing control signals are
user-defined, giving maximum flexibility of u se.
A two way serial interface and internal Control
Register provide further control and monitoring
of camera functions, giving many image
capture operating modes.

Exposure control can be achieved with or
without an electromechanical shutter, and
(external) frame/line buffer ing and processing
enables effective Fixed Patt ern Noise canc ella­tion.

Image Format 800 x 992 pixels
Pixel Size 10.8µm x 10.8µm
Array Size 8.640mm x 10.951mm
Sensitivity (colour) 50mV/lux @ 50ms exp.
S/N Typically 66dB (with FPN

cancellation)

Max. pixel rate 10Mpix/s (5Mpix/s for

0.1% settling)
Power Supply 5v ±5%
Power < 150 mW
Temperature 0

o

C - 40oC

•• High resolution (800K) CMOS sensor
designed for use in Digital Colour Stills
Cameras and Machine Vision applica­tions

• Versatile operating modes, including
Live Video/‘Cine’ mode for viewfinder
applications, and exposure monitoring
modes

• Digital control of pixel reading for flexibil­ity, including external ADC interface

• Control/configuration via serial interface

• External frame/line buffering schemes
offer effective pixel offset cancellation
and low noise operation

• Bayer pattern R,G,B colourisation (other
patterns/colours can be accommodated)

• Monochrome version available - VV5850

- functionally identical to the VV68 50, but
with higher sensitivity

• Low power operation (125mW Typical)

• Industry standard 84 pin LCC package

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VISION

VV6850 & 5850 Sensors: Product Datasheet Revision 1.0

Spectral Response

400

500

600

700

800

900

1000

1100

1.0

0.8

0.6

0.4

0.2

Wavelength, nm

Normalis ed Response

Basic CMOS Response

0

IR Filter (Lens)

Sensor with IR Filter

400

500

600

700

Red

Green

Blue

1.0

0.8

0.6

0.4

0.2

0

with IR Filter only

Sensor Response

Wavelength, nm

350

450

550

650

COLOURISATION
FILTER RESPONSES (of RGB

Normalis ed Response

Bayer Pattern colour set 1).

Response of other
colourisation patterns TBD.

Contents

page
Main Features 3
Sensor Architecture 4
Video Output 8
Operating Modes 12
Control Register & Serial Comms. 20
Detailed Operational Timings 25
Specifications 33
Package Details and Pinout 35
Example Support Circuits 38
Appendix - FPN Schemes 40

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Main Features

MAIN FEATURES

Timing

DSP

I/O Processing

Frame Buffer

Picture
Storage

Lens

Sensor

ADC

Exposure Control

Shutter

Flash

ASIC/DSP

Typical Application

(Image/colour

processing)

Timing & Control

Serial Data

The VV6850 sensor has been developed
specifically for use in image processing appli ­cations requiring pixel by pixel access. Flexi ­ble control options allow many operating
modes, but the VV6850 is ideally suited to
Digital Stills Cameras with elect romechanical
shutter exposure control and a frame store
memory available for pixel offset canc ellation.

Note:

The VV5850 monochrome sensor is
identical in operation to the VV6850, but with
higher sensitivity and simpler image proces s­ing, due to the absence of colour filte rs.

Pixel Array

The pixel array is colourised in a four p ixel,
Red, Green, Blue ‘Bayer’ arrangement. This
provides high colour fidelity images with low
colour aliasing. (Other colourisat ion schemes
can be produced to suit specific application
needs.) The pixel array includes a number of
reference lines, and a useable image area of
992 x 800 ‘valid video’ pixels.

Pixel access is by row and column shift re gis ­ters. Each row of pixels, or l ine, i s read at the
same instant, and stored in a sample-and­hold stage. The columns are then read out
alternately, and multiplexed through four
output channels to the AVO output stage. The
image can then be unshuffled and recon­structed in external buffering and processi ng
circuits.

This scheme provides AVO settling to better
than 0.1% at a sampling rate of 5 Msps.
(Higher sampling rates are possible, with
reduced settling accuracy.

Video Output

The multiplexed column outputs are buffered
to the Analogue Video Output (AVO) pin, as
‘inverted’ video, that is Black is higher than
White. An AVORef output is also generated,
from the internal black reference level , to
provide a pseudo differential output pair.

A DC component is added to the AVO and
AVORef signals at the AC coupled output
stages by CLAMPing these to VCL1 and
VCL2, one of which can be set by an internal
DAC. This allows the AVO level to be
matched to the input range of an external
ADC.

Serial Interface

The serial interface allows an external cont rol­ler to set certain parameters and to determine
the VV6850’s current state. This is done
through the Control Regi ster, whi ch is loaded
from DIN and examined at DOUT.

The VV6850 receives serial data as one 22­bit data word, the 20 msb of whi ch are clocked
into a shift re gister. The shift register contents
can then be latched into the Control Register.

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VV6850 & 5850 Sensors: Product Datasheet Revision 1.0

SENSOR ARCHITECTURE

The VV6850 image sensor comprises an array of 1016 (vertical , ‘lines’) by 804 (horizont al) active
photodiode cells feeding into a row of column source followers at the t op of the pixel array. These
columns are then in turn multiplexed on to four output chan nels, and finall y onto the AVO output.
Exposure, that is pixel integration time, is controlled by a ‘Reset Vertical’ shift register with pixel
readout controlled by the ‘Read Vertical’ and ‘Hori zontal’ shift registers.

The first (‘bottom’) l ine of the array is used internally, and is not read out. The next 6 li nes are black
reference lines. Then there are 8 colour characterisation lines, 992 valid video lines and 8 more
colour characterisation lines. At the top of the pix el array there is one more extr a line which is not
read out. The outer two columns on the left and right sides of the pixel array are also int ernal refer­ences, and not read out. Thus the usabl e image ar ea of the 1016 x 804 array i s 99 2 x 800 pi xels.

5-bit DAC

O/P

FI, FR

LS

Read Vertical Shift Register - Row Select

Reset Vertical Shift Register

Column Amplifiers & Sample/hold

Horizontal Shift Register - Column Select

Pixel Array

(804x1016)

Stage

Output

Buffers

First Pixel to be read out

Black

Reference

8x8 pixels

TOP

AVO

AVORef

‘Line scan’

(0 - 802; 1 - 803)

‘Frame scan’

0-Even

1-Even

2-Even

Serial

Data

0-Odd

1-Odd

1013

0 2 4

1 3 5

First line

}

Second line

}

G

G

R

‘Bayer’
Colourisation

B

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Sensor Architecture

Reset and Read Vertical Shift Registers

The resetting and reading of pixels is performed on a line by line basis, that is a row of column
amplifiers reads a whol e li ne o f pix el volta ges in para llel . The r eset /int egrate/ read cycle f or a li ne
of pixels is controlled by the Reset Vertical and Read Vertical shi ft registers (VSRs).

The length of the ‘Frame Integrate’ pulse, FI, propagating along the Reset Vertical shift register
sets the pixel integration time. FI going high at a point along the VSR releases that line of pixels
from RESET, starting the integration period. The two-line ‘Frame Read’ pulse, FR, which comes
at the end of the integrate period, starts the field readout, which proceeds from ‘bottom’ to ‘top’.
As FR propagates along the Read Vertical shift register, it controls which line is to be read. For
exposure control by means of a shutter mecha nism, FI should be held high thr oughout the f rame
integrate/read cycle.

The Vertical Shift Registers are clocked by the Line Clock pulse, LCK. Within a frame, first an even
line, then an odd line is read. This is controlled by the EVEN clock, which must be half the LCK
frequency and change two PCKs before LS (Line Start) rises. A pair of lines may be ‘skipped over’
(for example as in ‘Cine’ mode—see:

H

ORIZONTAL SHIFT REGISTER

), by inserting two LCK pulses and

one EVEN pulse between line readout sequences. .

Note:

If FR does not rise with the rising edge of EVEN, that is if EVEN is high during the second

line period of the FR pulse, the AVO-valid line readout sequence is offset by one line.
Further control of the VSRs is effected by: VCLRB (Clear Reset and Read ); VSETB (preset Reset

to ones); CDSR (reset row, but do not advance VSRs). The PXRD input to t he Read VSR enables
a line of pixels to be read out. (See:

O

PERATING MODES

for more details.)

The first six lines in the arr ay are blac k reference li nes. The rese t/integrate cycle for the se lines i s
controlled by a third shift register, defined by bits CR[4] and CR[3] in the Control Register (see:

C

ONTROL REGISTER/SERIAL DATA INTERFACE

). This shift register can either hold the black reference
lines in permanent reset, all ow minimum e xposure or have the same i nte gratio n ti me (ex posure)
as the rest of the array.

The readout sequence, initiated by FR going high, is therefore: six black lines followed by eight
colour characterisation lines , 992 valid video lines and anot her eight colour charact erisation lines.
For Cine this becomes: four bl ack lines, four colour chara cterisation, 496 valid video l ines and four
colour characterisation lines

LCK

FI
FR

EVEN

AVO

Valid Video Line

Black Ref Line

AVO Not Valid

1014 Lines

Exposure

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VV6850 & 5850 Sensors: Product Datasheet Revision 1.0

Horizontal Shift Register

The Horizontal Shift Register is clocked by the Pixel Clock, PCK. Co lumns are read out, fr om left
to right, by the Line Start pulse, LS, propagating alo ng the Horizontal Shift Register. The LS pulse
must be four PCK periods long, wi th the firs t valid pixel being s ampled after th e fall ing edg e (see

D

ETAILED TIMING

for exact relationship). To avoid bandwidt h limitations within the output stage
causing cross talk problems between the colours in a colour pixelated sensor , the horizontal shif t
register either reads out the odd or the even columns, under control of the EC signal.

In order to read valid pixel data, the Pixel Read input to the Read VSR, PXRD, must be high. (To
‘skip’ lines, for example a s in Cine mode, PXRD must be held low during the two extra LCK peri­ods.) When reading out either the even columns (EC=1) or the odd columns (EC=0) it is the
central 400 pixels of th e 402 pixels rea d out th at are vali d. I n Cine mode ( Sel ected wi th b it CR[3 ]
in the Control Register), every second pix el within a row is read out ; of the 202 pixels read out for
either EC=1 or EC=0, the central 200 pixels are valid.

The HCLRB input (active low) clears the HSR to all zeros. HCLRB can also be used, for example,
to prematurely end a line scan, perhaps when only part of the image is required.

Note:

The power-on reset signal, RSTB, should be used to drive HCLRB (and VCLRB for the

Vertical Shift Registers) at power up.

PXRD

LCK

LS
EC

EVEN

Even line Odd Line Even line

PXRD

LCK

LS
EC

EVEN

Even line

Odd Line

CINE mode:

AVO

Even pixels Odd pixels

Even pixels Odd pixels

Skip two lines

AVO

Even

Odd Even Odd Even Odd

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Sensor Architecture

Pixel Read Schematic

bit-line, Vx[m]

Pixel Array

AVO

PCK

Reset[n]

Horizontal Shift Register

D

pix

V

pix

Bitline Test/Clamp Circuitry

HCLRB

VRT

Column[m]

Read[n]

CR[0]

Vbltw

CR[1]

C

pix

Pixel[m,n]

CS[m]

LS

CS[401:0]

Output Channel 0
Output Channel 1

Output

Stage

CSo[401:0]

CSe[401:0]

EC

COLsam

Output Channel 2
Output Channel 3

EC

VRT

SAMRef

Line Reference

AVORef

Output

Channel

Clamp

SELRef

CLAMP

CINE

VRT

Read[m]

Read Vertical Shift Register

Reset Vertical Shift Register

FR

FI

LCK

VSETB
VCLRB

PXRD

EVEN

Vbloom

CDSR

Sample/Hold

Source Follower

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VV6850 & 5850 Sensors: Product Datasheet Revision 1.0

VIDEO OUTPUT

The four-PCK long LS pulse initiates output of a line of video, with the fir st valid pixel being
sampled after LS falls, and subsequent pi xels appearing at AVO as LS propagates along the Hori­zontal Shift Register. The AVO output fo r each pi xel shoul d then be s ampled a s cl ose to t he end
of the PCK cycle as possible to allow maximum settling time.

The Video Output Chain

At the top of each column of the array is a sample and hold stage (controlled by COLsam), which
drives the output stage. The pu rpose of t he sample & hold i s to ensure tha t all t he p ixels in a li ne
have the same exposure, as the outputs of a row of pixels are sampled at the same instant. If
COLsam is not used then each pixel will carry on integrating until it is read out. Therefore, since
all pixels within a line are released from reset at the same time, each pixel will have a different
integration time, and hence exposure value.

The columns are read out via four output channels. Eac h channel is multiplexed onto the AVO pin
via an AC coupling stage to restore the DC content. The AVORef pi n provides a pseudo-di fferen­tial output, obtained from an internal black reference. (The pseudo-differential output stage
cancels out leakage across the coupling capacitors since both output channels experience the
same rate of decay.)

Note:

The video at AVO is ‘inverted’, that is Black is higher than White.

Pixel Level Sampling

LS

PCK

AVO

AVO output has settled

PCK [R]

changes pixel

PCK [R]
Samples LS

First Valid pixel after
LS is sampled

on AVO

¼ PCK max. @ 5MHz

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Video Output

AVO Reference

The DC content of the output stage is set by using the SELRef signal to simultaneously put the
internal reference on the AVO and AVORef output channels, and then the CLAMP signal to
charge the amplifier side of the coupling stages to VCL1 and VCL2 respectively. The integrated
5-bit DAC, controlled by Control Register bits CR[15.. 11], can be used to adjust one or other of
these clamping voltages. The CLAMP signal must fall before SELRef falls. The AC Coupling
Capacitors must be refres hed at least on ce every stil l image captur e sequence, or ev ery frame of
a live video.

The sensor’s internal black reference, which drives the AVORef output path, is derived from a
separate 8 by 8 array of pixels connected in parallel. The input voltage to all pixels in the 8 by 8
array is VRT, that is the pixels are in reset. A sample & hold stage controlled by SAMRef allows
the VRT voltage driving the black reference pixels to be sampled, freezing the black reference
value.

Normally the black level referenc e should be updated between every still image capture sequence
or between every frame in li ve video mode. Under ver y high illumination , however, the black refer­ence should be sampled between every line in live video mode.

The internal black reference can be sampled at the beginning of a frame using SAMRef. It can
also be observed line by line by asserting SELRef (without CLAMP) in the dead period between
reading rows of pixels out onto AVO.

AVO

SELRef

White

Black

Peak

CLAMP

AVO

VCL2

VCL1

CLAMP

AVORef

VRT

8x8

Pixels

SAMRef

Pixel Array
+ Columns

Black Reference

SELRef

2:1

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VV6850 & 5850 Sensors: Product Datasheet Revision 1.0

The 5-Bit DAC

The internal five bit r esisti ve lad der DAC is energi sed by a Bias Generator th at is set by the inter ­nal Bandgap Voltage Reference, Vbg, and the external 12K resistor connected from Rset to
AGND. The Vdac output of the DAC, which can be used to set either VCL1 or VCL2, is adjusted
by bits 11 to 15 of the Control Register/Serial Interface.

Note:

The Vbg pin is a high impedance output, and can be o ver-ridden with in the VCL input limit s.

Parameter Definition Value Comment

Vdactop 208/122 * Vbg 2.08V
Vdacbot 176/122 * Vbg 1.76V
Vdac3/4 199/122 * Vbg 1.99V
Vdac CR[15..11] * (32/122 * Vbg) ­Zdac Vdac Output Impedance 21K Ohms ±25%

5-Bit DAC Parameters

32

Analogue

Vdac

CR[15..11]

Resistive Ladder, 32R

AGND

Vdacbot

Vdactop

Vdac3/4

176R

AVCC

I = Vbg/122R

R ~ 100 Ohms

12K

Vbg

Mux(32:1)

Bias

Generator

Rset

5-Bit DAC

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Video Output

Black Reference Lines

There are six lines at the bottom of the pix el ar ray tha t are cover ed wi th opaque maski ng. These
black reference lines have their own reset shift register. A four to one multiplexer, controlled by
Control Register bits CR[4] and CR[3], selects the inp ut to this shift register (FBCK), and hence
the operating mode. The four modes of operation are:

1. Permanent Reset - By setting FBCK low, the black lines are permanently reset to VRT.

2. Minimum Integration - FBCK follows the field read pulse, FR; the black reference lines are
held in minimum exposure.

3. Integration - FBCK follows the field read pulse, FI; the black reference lines theref ore have the
same exposure time as the array.

4. Permanent integration; the reference lines continue to integrate until reset as in 1.

Option 1.

is the most stable as it does not depend on either the quality of the black shield above
the black pixels or any l ight incident on the pixel s. However it is also t he least accur ate as it does
not allow for dark cu rrent or t he br eakthro ugh of the fal ling edge of t he pixel reset s ignal onto the
pixel capacitance. The resulting reference value will be ‘blacker’ than black due to the above
errors.

Option 2.

is more accurate than option 1. as the effect of the pixel reset signal breakthrough is
included, but the effect of tot al dark current is not included s ince the black reference pi xels are not
integrating for the same time as the image section of the pixel array. The r eference is, also, now
sensitive to the effects of light reaching the black line pixels.

Option 3.

includes the effect of d ark current since the bl ack reference pix els are integrati ng for the
same time as the image secti on of the pixel array. The validity of the reference is, however, now
even more sensitive to the effects of light reaching the pixel.

Option 4.

in combination with option 1 al lows the exposur e time for the black referenc e lines to be
controlled independently of the exposure of the rest of the image.

Note:

For best results, it is recommended that the average of the four cent ral lines of the black

reference line group is used to characterise ‘Black’ for the frame.

Exposure Control

Exposure control is achieved either electronically by varying the FI pulse duration, or directly by
means of a shutter arrangeme nt (mechanical, electro-mechanical, el ectro-optical, and so on). The
correct exposure level for any scene can be assessed by processing a ‘trial exposure’ of the
scene, or by utilising the ‘Accumulate’ or ‘Parallel Integration’ operating mode.

See:

O

PERATING MODES

for a full description of exposure control.

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VV6850 & 5850 Sensors: Product Datasheet Revision 1.0

OPERATING MODES

There are five main operating modes for the sensor:

• Still Image Capture with a Frame Buffer

• Correlated Double Sampling (line by line FPN cancellation )

• Live-Video/Cine Modes

• Accumulate

• Parallel Integration

These are explained below in outline. The fol lowing Section provides detailed timing requirements
for the various control signals necessary to operate the sensor.

Removing Noise

In order to obtain high quali ty, low noi se images from the VV6850 s ensor pixel to pixel of fset vari ­ations, or Fixed Pattern Noise (FPN), must be removed. This can be done by reading the image
array more than once, for example re ading in the dark to establ ish a reference for each pi xel, then
reading the exposed array to collect ‘image plus off set’ data, then subtracting to remove the
offsets. To obtain the lowest noise operation the random pix el ‘reset’ noise must also be removed.

Sources of Fixed Pattern Noise

The major sources of Fixed Pattern Noise in the sensor that can be cancelled are:

• Transistor Threshold Offsets

• Dark Current

Each of the above can be effectively cancelled to a much lower residual random noise level by
using the techniques described below. The residual noise sources in the sensor, such as flic ker
noise, dark current shot noise, thermal noise and ADC Quantisat ion noise, that cannot be
cancelled, or are a function of the cancellation techn iques, define the overall camera noise
performance.

Methods of Removing Fixed Pattern Noise

Transistor Threshold Offsets

Each pixel amplifier, each column source follower and each output channel multiplexer, has a
unique offset caused by process variations i n the thres hold voltage of the transi stors. Thi s offset
is independent of exposure, and wi ll be relatively stable with respect to temperature and oper ating
conditions.To remove Transistor Threshol d FPN, the VV6850 is used in conjunction wi th an ADC
and either a frame buffer or a line buffer:

•

Pixel offset removal frame by frame with a shutter:

A frame buffer is used to obtain the pixel
to pixel DC offsets for the whol e image. The offset s are obtained by capturing a dark (FPN)
frame with the shutter closed, and an ‘image’ frame with the shutter open. The ‘clean’
image data can then be extracted by subtraction. (This technique can only be used with a
physical shutter, and with at least one extra dark frame acquisition period.)

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Operating Modes

•

Pixel offset removal frame by frame with a reference frame:

A non-volatile frame buffer is
used to obtain the pixel to pixel DC offsets for the whole image at camera build. These off­sets are then subtracted from the exposed ‘image’ as it is read to obtain the ‘clean’ image
data. (This technique gives the fastest frame acquisition time at the expense of accuracy.)

•

Pixel offset removal line by line:

A line of pixel inf ormation is read an d stored in a line buf fer .
The line is then reset to black using the CDSR signal, before being re- read to obtain the
pixel to pixel DC offsets for that line. As the line is re-read the offset data for each pixel is
subtracted from the value stored in the line buffer, the result being the ‘image’ data. (The
COLsam signal must be used to ensure that samples in the same line have the same inte­gration period.)

With line by line offset r emoval the time for reading out a complete frame is doubled, since each
line has to be read twice. It is also not possible to remove pixel reset noise or dark current, thus
there is a trade off between the fr ame rate and image quality, and the amount of memory required.

Full frame offset removal can be achieved in many ways, depending on what anci llary devices are
available in the camera system, and constraints such as image quality required and acceptable
minimum frame rate.

Dark Current

The ‘dark current’ in a pixel photodiode is the inherent leakage that discharges the integrating
capacitance in the same way as incident light. Hence, Dark Current FPN builds up on the array
whenever the array is rel eased from res et, t hat is when FI is high. This means th at the a mount of
dark signal depends on exposure time, and varies from pixel to pixel.

The same degree of dark current charge build-up occurs in the array whether or not the array is
exposed to light. Therefore, if the array is all owed to integrate (FI high) with no incident light for
the same length of time as for the i mage exposure, the dark current e lement of the exposed image
data can be ascertained and removed f rom the image data by subtraction, l eaving behind the dark
current shot noise.

Since dark current also depends on temperature t he dar k frame shoul d be taken c lose in time to
the image frame, in order to avoid ambient temperature variations.

‘Reset Noise’ Cancellation

One random noise source that can be cancelled is ‘reset noise’ (or ‘kTC’ noise), which is due to
the switching of the photodi ode capacitance when t he pixel is released from reset. This is present
in all subsequent reads of the array (without reset) to the same extent. These can therefore be
extracted by reading the array immediately after reset (when FI goes high) and subtracting the
value obtained from the ‘exposed’ array data. Thi s operation also can cels Pixel Threshold Off sets.

To achieve reset noise cancellation, FR should be taken high for two LCK periods whe n FI goes
high, and 1014 lines read

before

the array is exposed to the r equired i mage. T he pixel data f rom
this pass of FR through the VSRs must be stored in a frame buffer, and subtracted from the
exposed image data. The exposed image is obtained when FR is pulsed high again, coincident
with the last two LCK periods of FI being high after the exposure period.

It is not possible to describe all of the many operating schemes that can be devised for image
capture and FPN reduction. The basic recommended modes for camera operation are descr ibed
below, with detailed timing requirements in the following Section.

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VV6850 & 5850 Sensors: Product Datasheet Revision 1.0

Still Image Capture with a Frame Buffer

This is the recommended operati onal mode for high quality stil l image capture in c amera systems
where there is an electro-mechanical shutter in fr ont of the sensor and a Frame Buffer for tempo­rary image storage. FPN cancellation is central to thi s mode of operation, and is described in
detail. Other operational schemes th at may be devis ed can include all or some of the techni ques
employed in this example, but the elements are essentiall y the same. (See:

A

PPENDIX

, A

PPLICATION

N

OTES

,

for a discussion of variations to this FPN cancellati on scheme.)

Note:

For the simplest possible image capture mode, with no FPN cancellat ion, see the descrip-

tion of the Vertical Shift Registers above.
The basic still image capture cycle starts with the shut ter closed. The array is released fr om reset

by taking the input to the reset vertical shift registers, FI, hi gh. The system contr olling the camera
must then wait for 1014 lines to allow this “integr ate wavefront” to propagate through the shift
register, before opening the shut ter. When FI goes hig h FR should also be pul sed high for 2 lines
to initiate the Read sequence. Reading each pixe l as soon as it is released from reset yields a
reset image which contains both t he fixed pattern noise component for each pixel and the random
reset noise due to that particular reset operation. This image should be stored in a frame buffer.

When the shutter has closed after exposure FR must be pulsed high again for 2 lines to re-read
the array and obtain the exposed image dat a. Again, it wil l take 1014 l ines to read al l of the ar ray
pixels. FI should fall when FR fal ls, t o retu rn the ac tive pi xel arr ay in to res et. As the image f ra me
is read out the appropriate pixel reset val ue, as stored in the frame buff er, i s subtrac ted from the
current pixel value and the result written to the frame store. This removes both pixel reset noise
and pixel to pixel DC offsets from the image.

(See

D

ETAILED OPERATIONAL TIMING

below for exact relationships.)

Due to the relatively long time taken t o read out an i mage (200 ms, assuming a 5 MHz clock rat e),
the dark current in each pixel is a significant part of the image data. To remove the fixed pattern
noise injected by the dark curr ent a ‘dark image’ must be captured with t he same integration t ime
as the exposed image but with the shutter closed. Su btracting the dark image from the exposed
image removes the dark current fixed patter n noise, leaving a ‘clean’ image. This process can be
summarised as follows:

LCK

FI

1014 Lines

FR

EVEN

AVO

T1=Exposure

Integrate=T

1

1014 Lines 1014 Lines

1014 Lines

Image Frame Dark Current Frame

Valid Video Line Black Ref Line AVO Not Valid

Shutter

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Operating Modes

1. With the shutter closed, release the sensor from reset and immediately read a frame into the

buffer memory; this captures the array threshold FPN and reset noise (‘V

Reset

’)

2. After 1014 line periods, open the shutter and expose the sensor to the required scene (the

exposure time can be determined by ‘Parallel Integration’ or ‘Accumulate’ — see below)

3. Close the shutter and immediate ly read the a rray; as each pixel is read, su btr act the val ue for

that position stored in the frame buffer, and overwrite that pixel location with the dif ference —
the memory now contains the image plus dark current FPN (V

im

+ V

Dark

)

4. After the 1014 line periods of the second read, repeat the image capture cycle, but do not

open the shutter; this time, load a

second

frame buffer with first the V

Reset

value and then the

V

Dark

value (after subtraction)

5. After the second integration pe riod, subtr act the V

Dark

value for each pixel that is stored i n the

second frame buffer from the (V

im

+ V

Dark

) value for that position stored in the fir st frame

buffer and overwrite that pixel location with the result.

The frame buffer now contains the corrected image values, which can be proces sed for colour
and so on, then transferred to permanent image storage memory.

The pixel voltages for this method are illustrated schematically below:

Note:

Since the ‘integrate wavefront’ must propagate through the VSR, the point at which the open
shutter exposure occurs will vary progressively from line to line of the array — from close to
‘Read2’ on the bottom line to close to ‘Read1’ at the top.

Reset[n]

Read[n]

V

pix

VRT

V

Black

V

White

V

Reset

Read 2 Read 4

V

Dark1

Vim

V

Dark1

Shutter

Exposure

Not to scale

V

Dark2

V

Dark2

+
+

Image

Read 1 Read 3

V

Dark

= V

Dark1

+ V

Dark2

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Correlated Double Sampling (line by line)

This is an alternative F PN cancellation mode for camera systems where there is only a Line Buf fer
available for temporary image capture, and not necessarily a mechanical shutter in front of the
sensor. The method outlined below, using the CDSR signal, relates to a still image capture in a
shuttered camera system, but the same principle could also be applied to exposure control with
the FI pulse duration in Still Frame and Live Video modes.

Note:

This method does not cancel dark cu rrent FPN, and as the pixel is res et twice, has two lots

of ‘reset’ noise sources.
The array is released from reset by taking the input to the reset vertical shift registers, FI, high.

The system controlling the camera must then wait for 1014 lines to allow this “integrate wavefron t”
to propagate through the shift register, before opening the shutter (or further extending the FI
pulse). After the sensor has been exposed for the appropriate t ime, FR must be pulsed high for 2
lines to read the pixel array and obtain the exposed image data, which is loaded int o the Line
Buffer line by line.

When a line of 804 pixels of image data has been read, the CDSR signal is pulsed high to reset
the line of pixels to Black (without advancing the HSR). COLSam is then pulsed to resample the
row, and as each pixel is read out this ‘Black Offset’ va lue is subtracted from the value stored in
the line buffer and the result passed on as corrected image data.

Note:

During the 992-line image data readout, LCK and EVEN must be at least twice their

minimum periods (with maximum PCK rate of 5.0MHz), to allow for the second line read.

(See

D

ETAILED OPERATIONAL TIMING

below for the exact relationships, and also how CDSR,

COLSam and PXRD should interact.)

LCK

FI

1014 Lines

FR

EVEN

AVO

Exposure

1014 Lines

Read ImageBlack Ref LineAVO Not Valid

Read Black Offset

CDSR

Read Image & Offsets

COLsam

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Operating Modes

Live-Video & Cine Modes

In the ‘Live Video’ mode the effect i s simil ar to a con vent ional vi deo ca mera, wit h a frame rat e of
just under five frames/second (with a 5 MHz pixel cl ock). This can be used, for example, to provide
a moving ‘viewfinder’ display for a stills c amera. ‘Cine ’ mode is similar , but achieves higher frame
rates.

In Live-Video mode the expos ure level for a f rame is co ntroll ed electr onical ly by var ying t he high
duration of the FI waveform. The high duration of FI can be varied from 2 lines (minimum expo­sure) in multiples of 2 lines up to 1012 lines (maximum exposure). The falling edge of FI is fixed
within the frame, therefore it is the leading edge of FI that must be moved to vary exposure.

The field read pulse, FR, must be set high for the 2 lines preceding the falling edge of FI; this
means that the FR waveform is identical to the FI waveform for minimum exposure. The neces­sary signal relationships are i ll ustrated below:

If a frame buffer is being used to store the pixel to pixel DC offsets t he fir st image captured on
entering Live-Video mode should have minimum exposure to obtain and store pi xel offset data.
However, if the offset data already exists in memory this step is not required.

Cine Mode

Selecting Cine mode via the Se rial Data Contro l Register (CR[2] ) subsamples the pixel s in a line,
reading out only every other pixel pair. (See:

H

ORIZONTAL SHIFT REGISTER

for details.) ‘Cine’ mode
enables higher frame rates to be achi eved, f or example 20 fr ames pe r second (at 5MHz) by al so
only reading every other

line pair

. To achieve this, the Vertical Shift Registers must read out 2
lines and then skip the next 2 lines, by inserting 2 extra LCK pulses and one extra EVEN pulse
between every second line read out. (See:

V

ERTICAL SHIFT REGISTERS

for details.)

Note:

It is not essential t o skip l ine pai rs i n Cine mode, i f aspect rati o need not be pr eserved. It is
possible to skip more tha n one line pair, an also to i ncrease PCK (up to 10MHz) to furt her increase
frame rate.

For high frame rates, it is also best to read a dark frame into memory and subtract the Fixed
Pattern Noise as the array is read in order to reduce the frame overhead of either line-rate CDS
or the Shuttered Frame-rate cancellation schemes.

LCK

FI

1014 Lines (1 Frame)

FR

EVEN

AVO

Exposure Exposure

Read Pixel Offsets

Live-Video Frames

Valid Video Line

Black Ref Line

1014 Lines (1 Frame) 1014 Lines (1 Frame)

Exposure

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Parallel Integration

In this mode all of the pixels in t he array are released from reset at the sa me time. This is achieved
using the VCLRB and VSETB signals for the vertical shift registers. ( VSETB only effects t he reset
shift register). This can be used to give a quick but crude esti mate of correct exposure by, for
example, counting lines until a line is reached where all pixels in the line are saturated, then
setting exposure to, say, 50% of the integration time taken to reach that line.

The sequence of operations is as follows:

1. Pulse VCLRB low to reset the Read and Reset vertical shift registers to al l zeros; this forces
all pixels int o res e t

2. Pulse VSETB low , thi s loads the Reset shi ft regis ter with al l ones, which s tarts all of the pixels
integrating.

3. Then FR should be pulsed high for 2 lines to start the array readout.

Note:

VCLRB and VSETB must NEVER be taken low at the same time.

Since all pixels start to integrate at the same time and readout is sequential (line by line), each
line of pixels represents a different exposure value. If the FR pulse occurs on the next video line
after VSETB goes high then the first valid video line readout will have been exposed for 6 lines
(the black reference lines), and the last line of valid video will have been exposed for 1014 lines.

Valid Video LineBlack Ref LineAVO Not Valid

LCK

FI
FR

EVEN

AVO

VSETB

VCLRB

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Operating Modes

Accumulate

In ‘Accumulate’ mode the pixel array is repeatedl y re-read without resett ing the pixels. This mode
is intended for exposure monitori ng in conjunction with a flash when light levels are low, and more
than one frame time is required to obtain sufficient int egration.

The array is released from reset by taking FI high. At the same time FR is pulsed hi gh for 2 li nes
to read out the pixel reset values. Then at t he required intervals (of not less than 1014 l ine periods)
FR is pulsed high for 2 lines to re-read the array. While the array is being repeatedly re-read FI
must stay high. Effectively, the successive reads of the array are monitoring the rate of charge
accumulation in the pixels.

When sufficient integration has occur red to produce, say 50% average saturation, rea ding can be
terminated. The number of f rames of exposure required to ac hieve this can then be us ed to calcu­late the flash energy requi red to correctly exp ose the scene. On the fal ling edge of FR for the f inal
array read, FI should go low, to return the pixel array into reset.

Valid Video Line Black Ref Line AVO Not Valid

LCK

FI

1014 Lines

FR

EVEN

AVO

1014 Lines 1014 Lines

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THE CONTROL REGISTER & SERIAL COMMUNICATION

The VV6850 includes a full du plex serial inter face, and can be control led and configured by a host
processor. Data describing the current configuration of the camera is stored in a 20-bit control
register. This register can be read from the camer a on the serial interface, and can also be writ ten
to from the serial interface to change camera operati on.

When a 22-bit serial interface data word arrives at the camera on DIN, the first 20 (msb) bits are
loaded into a shift register, an d the last two bits (‘R/W’ ) are examined to as certain if a ‘read’ oper ­ation or a ‘write’ operation is requi red. If a ‘write’ is requir ed (‘R/W’ = “00”) the contents of the i nput
shift register are transfer r ed to t he c ontrol re gister . Other wise , the cur rent con tent s of the control
register is output on DOUT. (Note: I n ‘test mode’, that i s with CR[7..5]>0, cer tain other signals are
monitored by DOUT and CR[19..0] is not transmitted.)

The signals used to effect the serial data interface are:

• DIN Serial Data In; DIN is sampled on the rising edge of DCK

• DOUTSerial Data Output

• DCK Serial Data Clock

• DLAT Serial Data Latch; transfers the input data word t o the control register (for ‘write’),

and initiates control regist er output on DOUT (for CR[7..5]=0)

20-bit Shift Register

Control Register CR[19..0]

DIN

DCK

DLAT

DOUT

R/W

20

CR[19..0]

20

20

3

CR[7:5]

8 to 1 Multiplexer

&

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The Control Register & Serial Communication

Serial Communication Protocol

The host must perform the role of a communications master, while the camera act s as a slave
receiver and transmitter. Communicat ion from host to camera takes the form of a 22-bit data word,
with a 20-bit data word returned to the host. Since the serial clock (DCK, ma ximum fr equency
100kHz,) is generated by the host, the host determines the data transfer rate.

The host sends the 20 bit control word, most signifi cant bit first, then either holds DIN hi gh for two
clock cycles, to indicate a ‘read’ , or holds DIN low for two clock cycles, to indicate a ‘write’. The
host also takes DLAT high for one clock cycle, correspondi ng to the last bit of th e R/W pair. This
defines the end of the transfer and latches the data word to the Control Register, if required (R/
W=00). DLAT also (on the next rising edge of DCK) transfers the contents of the Control Register
to the Shift Register, which is then output to DOUT if CR[7..5] = 0.

The data transfer protocol is illustrated below:

DLAT

DCK
DIN

DOUT*

CR[19]

* Only valid when CR[7:5] = 000 (Default)

DIN

DOUT*

Control Register Read Timings:

Control Register Write Timings:

CR[18]

CR[0]CR[1]

CR[19] CR[18] CR[0]CR[1]

20 DCK Cycles

20 DCK Cycles

CR[19] CR[18] CR[0]CR[1]

DLAT

DCK

CR[2]CR[17]

20 DCK Cycles

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The Serial Data Word

The 22-bit Serial Data Word consists of the two-bit wide R/W flag, and the 20 bits of Control Regis­ter data (CR[0..19]. The following tables defines the CR information contained in the messages:

CR
Bit

Function/Comment Default

0 Bit-line Test Enable 0
1 Bit-line Clamp Enable 1
2 Select ‘Cine’ mode: only every other ‘colour’ pixel column is output 0

4,3 Controls the integration mode for black reference lines 0

7..5 Selects the node that DOUT is monitoring 0
8 Enables the Sample & Hold circuits on the four output channels 0
9 Connects the four black reference output channels together; the

default is AVORef cycling through the four channels

0

10 Enable clamping circuitry on the four output channels 1

15..11 D[4..0] - 5-bit Resistive DAC value; D[4] is msb 16
16 Switch in the Output Stage Sample&Hold Capacitors 0

19..17 Reserved 0

D[4]

Read = 11

D[3] D[2] D[1] D[0]SWCP

SWCP

RSH

OCLE

CINE BLECLE R / WBM[0]BM[1]OS[0]OS[1]OS[2]

CR[19]

CR[0]

CR[9]

CR[8]

The 22-bit Serial Data Word (msb first)

Read Data Format

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The Control Register & Serial Communication

Control Register Definitions

The various bits in the Control Register define operating modes and parameters as follows:

CR[0] - Bit-line Test Enable

Enables testing of the pixel column inter connections. This bit should always be 0.

CR[1] - Bit-Line Clamp Enable

The default is the bit-line clamp enabled, CR[1] = 1, which ensures that if a bit-line goes too low
due to a pixel being heavily over-exposed, the bit-l ine i s clamped to Vbltw-Vtn.

Note:

Due to internal variations, the absolute clamp volt age will vary from column to column. Thus,
care must be taken to ensure that the ADC value clips before the bit-line clamp circuits operate
otherwise column to column fixed pattern noise will appear in the saturated white regions of the
image.

CR[2] - ‘Cine’ Mode

Setting CR[2] = 1 forces the horizontal shift register to read out every second red, green or blue
pixel in each odd and even field. In this mode 202 pixels instead of 404 pixels are read out per
colour per line. (Note: The buffer columns on the left and right side of the pixel array are always
read out.)

CR[8] and CR[16] should also both be low for Cine mode.

CR[4:3] - Black Reference Line Integration Mode Select

CR[4] and CR[3] control the selection of the fou r possible integration mod es to the black reference
lines. The Table below defines the code associated with each of the four modes.

(See:

V

IDEO OUTPUT

- B

LACK REFERENCE LINES

for details of these modes.)

CR[7:5] - Select DOUT output

Output to the DOUT pin is multiplexed under the control of CR[7], CR[6] and CR[5] for test
purposes. All three of these bits must be set to zero for image data to be observed on DOUT.

CR[4] CR[3]

Integration Mode for Black reference

Lines

0 0 Permanent Reset.
0 1 Minimum Integration (FR)
1 0 Same integration time as main array (FI)
1 1 Always integrating.

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CR[8] - Output Channel Sample & Hold Enable

The sample and hold circuits in the AVO and AVORef output stages isolate the capacitive back
injection which occurs when an output channel is multiplexed onto the AC Coupling capacitor,
which changes the nature of the back injection:

• Without sample and hold (CR[8] = 0 (default)), the interacti on of the back injection and the
column output results in the AVO overshooting slightly before settling to the desired value

• With sample and hold enabled (CR[8] = 1) the overshoot is eliminated, but t he current pixel
value will contain a very small contribution from the previous pixel value read out on AVO

Note:

CR[16] allows the output channel sample /hold capacitor to be i solated from the signal path.

CR[9] - Common Up the Black Reference Channels

There are two options for operating the four black reference output channels:

1. CR[9]=0 : Operate with the AVORef cycling between each of the four black output channels.
A VORef wil l follow the shape of AVO as the AC coupling capacitor is cycling in the same way
within both output stages. Any mismatch between the black refer ence output channels will
appear as a four-cycle pattern on AVORef.

2. CR[9]=1 : Parallel up the operation of the blac k output channe ls. AVORef represents the aver­age of the four black output channels.

CR[10] - Output Channel Cl amp Enable

Setting CR[10] = 1 (default) clamps the four output channels that are multiplexed onto AVO to
prevent them going beyond the designed operating voltage range. This ensures that each output
channel always has enough time to recover from being inactive before outputing pixel data.

CR[15:11] - 5-Bit Resistive DAC Data Value (D[5:0])

Data for the internal 5-bit Resistive Ladder DAC (default = 16). CR[15] is the MSB.

CR[16] - Switch in Output Stage Sample/Hold Capacitors

Setting CR[16] high isolates the output channel sample/hold capacitors from the signal path. By
isolating these capacitors the output channel s settle to the desired value in a shorter time.

Note:

CR[16] should only be set high when the output channel sample/holds are disabled.

The primary use of this functi on is in Cine mode. In t his mode only two of t he four output channels
are in use. As the two output channels ha ve only half the time to settl e, compared with the normal
readout sequence, CR[16] should be set high to improve settling of the output channels.

CR[19:17] - Reserved for future use

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Detailed Operational Timing

DETAILED OPERATIONAL TIMING

The following Section describes in detail the recommended timing for the primary operating
modes. There are many possible timing schemes, with more flexi ble setup and holds, but the
recommended timings are safe. Specifically, timing diagrams and tables are given for:

• Normal Array Read

• Correlated Double Sampling (line by line)

System Clocks

Line and pixel timing is done in PCK’s, and all signals should change on the fallin g edge of PCK.

The timings in the following tables have been expressed for a 5MHz PCK. The symbols
[T],[R],[F],[H],[L] signify Transitional edge, Rising edge, Falling edge, High Level and Low Level
respectively.

Line Start to PCK Timing

The relative timing of the Line Start pulse, LS, and the Pixel Clock, PCK, is extremely important
for correct sensor operation. LS must be set up at least 20ns after the risi ng edge of PCK, no later
than (PCK Period)/4 after the rising edge of PCK, and must be held for fou r PCK cycles . This is
illustrated below:

Min T yp Max Units

PCK Period 100 200 - nS
PCK Duty Cycle 40 - 60 %
Line Period 1024 1024 - PCK’s
Line Period (CINE Mode) 624 624 - PCK’s

System Clocks.

LS

PCK

PCK [R]

changes pixel

on AVO

min: 20ns
max: (PCK Period)/4

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Initial Power Up Timing

• On powering up the array should be reset by VCLRB and HCLRB, to help the settling of

the internal references. An internal power-on-reset circuit generates RSTB, which can be
used to reset the sensor.

• The references VRT and Vbg must be stab le before the f irst frame; t his wil l be a f unction of

the decoupling.

• The internal reference and AC coupling stages should be put into sampl e mode by making

SELRef, SAMRef, and CLAMP high.

• To ensure that the array is inactive until the first frame on power up FI, FR, LS, PCK, LCK

and EVEN should all be low.

Note:

Serial Data can only be sent after RSTB rises.

Event Timing Min Typ Max Units

Power On Reset trigger Voltage PU1 - 2.7 - V
RSTB pulse width PU2-PU1 100 - - uS
Settling Time PU4-PU3 10 - - mS

Recommended Start-Up Timing.

VDD

FR/FI/LS
HCLRB/

VRT

Other References

VBG

VCLRB
RSTB

4.5V

2.7V

PU0 PU1

PU2

PU3

PU4

(RSTB should be used to drive HCLRB and VCLRB to reset the sensor)

SELRef/

SAMRef/

Power-up

First Frame

CLAMP

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Detailed Operational Timing

Inter-Frame Timing

When a frame is to be taken, the first task is to sample the reference with SAMRef. This signal
should be held high until the first line, which should be for at least 100uS.

If possible, SAMRef should be held high between acquisi tion of still frames. In order to also ensure
that the AC coupling stages do not drift, SELRef and CLAMP should also be held high.

Line Read-Out Timing

The following diagrams and tables define the relat ive timings of the various control signals
required to read a line of pixels. Not all of the signals shown wil l be required for all modes of oper ­ation, but where they are these timing constraints must be observed. Timings for Correlated
Double Sampling (using CDSR) are given after the standard line read definitions.

LCK is the master clock for the vertical shift registers, for reading and resetting rows. LCK is a
latching signal, and latches when high (to be reset on the next PCK).

The EVEN signal transitions must straddle LCK & PXRD, and FI & FR must straddle LCK. PXRD
must be high when COLSam is pulsed. EC & EVEN are not latched, and must therefore remain
high while reading valid pixels. The first line of pixel information is read out when the EVEN and
FR signals are both high. If the EVEN signal is high during the second line per iod of FR pulse, the
line readout sequence will be of fset by one line relat ive to that outline d in the timing speci fication.
This is due to the FR and FI inputs only being sampled when both LCK and EVEN are high.

Event Timing Min Typ Max Units

SAMRef Period F1-F0 100 - - uS
CLAMP overlap of SAMRef[F] F2-F1 1 uS
SELRef overlap of CLAMP[F} F3-F2 0.200 uS

Inter Frame Timings

Inter Frame Timings

F0

SAMRef

CLAMP

SELRef

F1 F2 F3 F4

FRAME

Valid

Pixels

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Valid Video Data

AVO Reference Level

AVO Not Valid

Line Timings for Reading The Array.

Black Level

Peak White

1 Line

l0

l2l3l4l5l6l7l8l1l9

l10

Reference Level

Even Columns (400 pixels) Odd columns (400 pixels)

PXRD

LCK

LS
EC

EVEN

SELRef

AVO

AVO

COLsam

CDSR

l11

l12

l13

l14

l15

l16

l19

l17

l18

CLAMP *

l20

l21

Reference Level

* CLAMP is only used if Line update of AC coupling is required in CINE mode

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Detailed Operational Timing

Description #t PCK Cycles Time (us)

SELRef [R] - Start of Line l0 0 0
CLAMP [R] (only if line CLAMPing is being done) l1 1 0.2
EVEN [T] l2 2 0.4
LCK [R]) l3 4 0.8
LCK [F] l4 5 1.0
PXRD [R] l5 10 2.0
COLsam [R] l6 11 2.2
COLsam [F] l7 206 41.2
CLAMP [F] l8 207 41.4
SELRef [F] l9 208 41.6
EC [R] l10 209 41.8
LS [R] (even pixels) l11 210 42.0
LS [F] (even pixels l12 214 42.8
AVO valid, even pixels, start l13 214.5 42.9
AVO valid, even pixels, end l14 614.5 122.9
EC [F] l15 616 123.2
LS [R] (odd pixels) l16 617 123.4
LS [F] (odd pixels l17 621 124.2
AVO valid, odd pixels, start l18 621.5 124.3
AVO valid, odd pixels, end l19 1021.5 204.3
PXRD [F] l20 1023 204.6
End of line l21 1024 204.8
Line Length l21 - l0 1024 204.8
EVEN [T] - LCK [R] setup time l3 - l2 2 0.4
LCK Duration l4 - l3 1 0.2
LCK [F] - PXRD [R] l5 - l4 5 1
PXRD [R] - COLsam [R], setup l6 - l5 1 0.2
COLsam Duration l7 - l6 195 39.0

Recommended Line timings

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VV6850 & 5850 Sensors: Product Datasheet Revision 1.0

Line Timing using CDSR

The following timing details relate to Correl ated Double Sampling on a line by line basis, that is
using the CDSR signal to reset a line of pixels without advancing the VSR. The image capture
part of the double read is exactly as desc ribed above, and all setup times and durations ot her than
CDSR specific times are also identical.

See:

O

PERATING MODES

- C

ORRELATED DOUBLE SAMPLING

for full details.

COLsam [R] - CLAMP [F] l8 - l7 1 0.2
CLAMP [H] Duration l8 - l1 206 41.2
SELRef [H] Duration l9 - l0 208 41.6
SELRef overlap of CLAMP l1 - l0

l9 - l8

10.2

SELRef [F] - EC [R] l10 -l9 1 0.2
COLsam (F) - EC (R) c10 -c7 3 0.6
EC [T] - LS [R] : even l11 - l10

l16 - l15

10.2

LS [H] Duration 1 (even)
Duration 2 (odd)

l12-l11
l17-l16

4
4

0.8

0.8

LS [F] - First Valid Even Pixel
First Valid Odd Pixel

l13 - l12
l18 - l17

0.5 0.1

Valid pixels - even

- odd

l14 - l13
l19 - l18

400 80.0

PXRD [F] - SELRef [R] (next line) l21 - l20 1 0.2
NOTE 1: All input signals should change on the Falling Edge of PCK

NOTE 2: For CINE mode the Valid pixels is reduced from 400 to 200, giving a reduction in Line time

from 1024 to 624 PCK’s, all other relative timings remain unchanged

Description #t PCK Cycles Time (us)

Recommended Line timings

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Detailed Operat ional Timing

Valid Video Data AVO Reference Level AVO Not Valid

Line Timings for reading pixel data and the black offset data using the CDSR signal.

Black Level

Peak White

1 Line

c10

Reference Level

Even Columns Odd columns

PXRD

LCK

LS
EC

EVEN

SELRef

AVO

AVO

CDSR

Reference

(400 pixels) (400 pixels)Level

(400 pixels)

Black Offsets

Even Columns

Pixel Data Pixel Data

COLsam

c0c2c3c4c5c6c7

c8c1c9

c11

c12

c13

c14

c15

c16

c17

c18

c19

c20

c21

c22

c23

c24

c25

c26

c27

c28

c30

c31

c32

c33

c34

c35

(400 pixels)

Black Offsets

Odd Columns

c36

c37

c29

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VV6850 & 5850 Sensors: Product Datasheet Revision 1.0

Description #t PCK Cycles Time (us)

SELRef [R] - Start of Line c0 0 0
Image Line data (exactly as single image capture) c1 1023 204.6
CDSR [R] c21 1028 205.6
CDSR [F] c22 1053 210.6
PXRD [R] c23 1058 211.6
COLsam [R} c24 1059 211.8
COLsam [F} c25 1254 250.8
EC [R] c26 1257 251.4
LS [R] (even pixels, dark offsets) c27 1258 251.6
LS [F] (even pixels, dark offsets) c28 1262 252.4
AVO valid, dark offsets even pixels, start c29 1262.5 252.5
AVO valid, dark offsets even pixels, end c30 1662.5 332.5
EC [F] c31 1664 332.8
LS [R] (odd pixels) c32 1665 333.0
LS [F] (odd pixels c33 1669 333.8
AVO valid, odd pixels, start c34 1669.5 333.9
AVO valid, odd pixels, end c35 2069.5 413.9
PXRD [F] c36 2071 414.2
End of line c37 2072 414.4
Line Length c37 - c0 2072 414.4

CDSR Setup Times

LS (F) - First Valid Pixel c13 - c12

(etc.)

0.5 0.1

Valid exposed pixels - even

- odd

c14 - c13
c19 - c18

400 80.0

Valid reset pixels - even

- odd

c30 - c29
c35 - c34

400 80.0

CDSR [H] Duration c22 - c21 25 5.0
NOTE: For CINE mode the Valid pixels is reduced from 400 to 200, giving a reduction in Line time

from 2072 to 1272 PCK’s, all other relative timings remain unchanged

Recommended Line timings Using CDSR

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Specifications

SPECIFICATIONS

Absolute Maximum Ratings

Note:

Stresses exceeding the Absolute Maximum Ratings may induce failure. Exposure to absolute
maximum ratings for extended periods may reduce reliability. Functionality at or above these
conditions is not implied.

DC Operating Conditions

Note 1.Digital and Analogue outputs unloaded.

Parameter Value

Supply Voltage -0.5 to +7.0 volts
Voltage on other input pins -0.5 to V

DD

+ 0.5 volts

Temperature under bias -15

o

C to 85oC

Storage Temperature -30

o

C to 125oC

Maximum DC TTL output Current Magnitude 10mA (per o/p, one at a time, 1sec. duration)

Symbol Parameter Min. Typ. Max.

Unit

s

Notes

V

DD

Operating supply voltag e 4.75 5.0 5.25 V

I

DD

Overall supply current

35 mA 1

V

IH

Input Voltage Logic “1” 2.4 VDD+0.5 V

V

IL

Input Voltage Logic “0” -0.5 0.5 V

V

OH

Output Voltage Logic “1” VDD-0.5 V I=1mA

V

OL

Output Voltage Logic “0” 0.5 V I=1mA

I

ILK

Input Leakage current

-1 µA

VIH on input

1 µA

VIL on input

C

load

Digital Input Cap. Load

10 pF

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VV6850 & 5850 Sensors: Product Datasheet Revision 1.0

AC Operating Conditions

Note 1. Recommended clock rate for 0.1% settling of AVO is 5.0MHz.
Note 2. Serial Interface clock must be generated by host processor.

Electrical Characteristics

Video Output Characteristics

Symbol Parameter

Min

.

Typ. Max.

UnitsNote

s

PCK Pixel Clock frequency 5 10 MHz 1
DCK Serial Data Clock 100 KHz 2

Symbol Parameter Min. Typ. Max. Units Notes

VRTref Internal reference for VRT 2.85 3.0 3.15 V Unbuffered
VBLOOMref Internal reference for VBLOOM 1.90 2.0 2.10 V Unbuffered
VBLTWref Internal reference for VBLTW 1.35 1.50 1.65 V Unbuffered
V

BG

Internal bandgap reference 1.15 1.23 1.30 V Decouple with 0.1µF
VCL1,2 Video Output Clamp Voltages 1.30 2.30 V An. Inputs
V

DAC

5-Bit DAC Output 1.76 2.08 V For VCL1 or 2
R

SET

Resistor to set DAC bias current -5% 12K +5% Ohms
I

VRT

Load Current on VRT 1.5 2.5 4.0 mA Buffered from VRTref

Typical conditions, VDD = 5.0 V, TA = 25oC

Symbol Parameter Min. Typical Max. Units

V

black

AVO Black Level VCL1-30mV VCL1 VCL1+30mV V

V

white

AVO Peak White - V

black

-1.0V - V

Pixel Reset to Pixel Reset -0.125 0 0.125 V
AV ORef Pseudo-Diff. AVO Reference VCL2-30mV VCL2 VCL2+30mV V
I

AVO

AVO output current -2mA 4mA mA
F

AVO

AVO bandwidth 33MHz
C

AVO

AVO, AVOref Capaci tiv e Load ing 30 pF
R

AVO

AVO, AVOref Res istiv e loa ding 20K Ohms

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Package Details

PACKAGE DETAILS

Pinout

0.51 TYP

1.0 TYP

2.16

Pin 1

1.016 PITCH TYP

23.37

0.55

0.51

0.42

Glass Lid

Sensor

The optical array is centred within the
package to a tolerance of +/- 0.2 mm, and
rotated no more than +/- 0.5

o

Tolerances on package dimensions +/-0.2
All dimensions in millimetr e s

Viewed from below

Optical Centre

Pin 1 1

Standard 84 Pin LCC

0.864 Min.

‘TOP’

12345679 80 81 82 83 84

32
31
30
29
28
27
26
25
24
23
22
21

47 46 45 44 43 4253 52 51 50 49 48

54
55
56
57
58
59
60
61
62
63
64
65

AVDD2

Vdactop

Vdacbot

AVDD1

AVORef

AVSS1

AVO

Vdac

Vbltwref

Vdac

3/4

VCL2

VCL1

DVDD4

AGND1

AVCC1

DVSS4

SAMref

DOUT

LS

EC

COLsam

CLAMP

SELref

PCK

RSTB

DIN

DLAT

DCK

Viewed from top of package

35 34 3341 40 39 38 37 36

AGND2

AVCC2

DVDD3

DVSS3

66
67
68
69
70
71
72
73
74

HCLRB

EVEN

FR

FI

VSETB

VCLRB

PXRD

LCK

CDSR

18
17
16
15
14
13
12

20
19

AVCC3

Vblwt

AGND3

Vbg

Rset

Vnb

Vbloom

VRTref

Vblmref

75 76 77 78

DVSS1

DVDD1

VRT1

78910

VRT2

DVSS2

11

DVDD2

Index

‘TOP’

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VV6850 & 5850 Sensors: Product Datasheet Revision 1.0

Pin List

Pin Name Type Function/Comment

POWER SUPPLIES

51, 35, 18 AVCC1-3 PWR 5V supply for the Column Source Followers.
50,36, 14 AGND1-3 GND Ground for the Substrate and the Column Source Followers.
28, 32 AVDD1,2 PWR 5V supply for the Output Stage.
30 AVSS1 GND Ground supply for the Output Stage.
75, 11 DVDD1,2 PWR 5V supply for Vertical Shift Registers
76, 10 DVSS1,2 GND Ground for V ertical Shift Registers
33 DVDD3 PWR 5V supply for Output Muxing.
34 DVSS3 GND Ground for Output Muxing.
53 DVDD4 PWR 5V supply for Horizontal Shift Register.
52 DVSS4 GND Ground for Horizontal Shift Register.

POWER-ON-RESET

65 RSTB OD Output of internal power-on-reset cell. Should be applied to

HCLRB and VCLRB at power up.

ANALOGUE VOLTAGE REFERENCES

77, 9 VRT1,2 IA Pixel Reset Voltage and Power Supply.
12 Vbloom IA Anti-blooming pixel reset voltage.
13 Vbltw IA Defines white level for the Bitline test.
19 VRTref OA Unbuffered Internally generated Reference for VRT
20 Vblmref OA Unbuffered Internally generated Reference for Vbloom
21 Vbltwref OA Unbuffered Internally generated Reference for Vbltw.
15 Vbg OA Internal bandgap voltage reference (1.22 V); decouple with 10nF
17 Vnb IA Decoupling (10nF) for internally generated bias current
16 Rset IA Sets internal master bias current; connect to AGND via 12K Res.
25 VCL1 IA AC Clamp Voltage for AVO output.
26 VCL2 IA AC Clamp Voltage for AVORef output.

ANALOGUE OUTPUT STAGE

31 AVO OA Buffered analogue video output; Inverted - low = white
29 AVORef OA Buffered black level voltage reference.
55 SELRef ID SELRef=0 - Selects sensor output (video) at AVO.

SELRef=1 - Selects ‘Line Reference’
54 SAMRef ID Samples the ‘Line Reference’ from VRT
56 CLAMP ID Controls AC Clamping circuit in output stage.

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Package Details

Key:

RESET AND READ VERTICAL SHIFT REGISTERS (VSR)

74 LCK ID Line clock input for Reset and Read Vertical Shift Registers
71 EVEN ID ODD /EV EN Lin e Clock.
72 PXRD ID Pixel Read: Control input to read a row of pixel voltages.
73 CDSR ID↓ Correlated Double Sampling: Control input to allow the row of pix-

els currently being read to be reset without advancing the reset

VSR.
67 VCLRB ID↑ Clear Reset and Read VSR’s.
68 VSETB ID↑ Preset the Reset VSR to all ones. The Read VSR is not preset.
69 FI ID Field Integrate: Resets VSR. High duration sets exposure time.
70 FR ID Field Read: Reads VSR. Starts field read out.

HORIZONTAL SHIFT REGISTER (HSR)

60 PCK ID Pixel clock
66 HCLRB ID↑ Clear Horizontal Shift Register
59 LS ID Line Start: Starts horizontal scan/pixel output.
58 EC ID ODD /EV ER Col umn Selec t.
57 COLsam ID Sample the Column Source Follower Inputs (pixel row).

SERIAL DATA INTERFACE (SDI)

63 DIN ID↓ Serial Data Input
64 DOUT OD Serial Data Output
62 DLAT ID↓ Latch Serial Data into Control Register
61 DCK ID↓ Serial Data Clock Must be generated by host.

5-BIT RESISTIVE LADDER DAC

22 Vdactop IA Voltage reference for the top of the resistive ladder
23 Vdac3/4 OA Three-Quarter-point of the resistive ladder (Unbuffered)
27 Vdacbot IA Voltage reference for the bottom of the resistive ladder
26 Vdac OA DAC Output Voltage (Unbuffered)

OA Analogue output pad ID Digital input
IA Analogue input pad ID↑ Digital input with internal pull-up
OD Digital output pad OD↓ Digital output with internal pull-down

Pin Name Type Function/Comment

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VISION

VV6850 & 5850 Sensors: Product Datasheet Revision 1.0

ADC INTERFACE CIRCUIT

AVO

AVORef

Sensor

Pipelined ADC

2k

Black

White

Black

White

REFTF

REFBF

Line

Reference

Pixel Array
+ Columns

VCL2

VCL1

CLAMP

5-bit

Resistor

Ladder DAC

Vdactop

Vdacbot

Vdac

Vdac3/4

25k

25k

2p

1k

1k

33

10p

A_IN

10 bit / 20 Msps

CR[15..11]

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Analogue Reference Buffering

ANALOGUE REFERENCE BUFFERING

VV6850

VRT

VBloom

VBL TW

VBG

IC1-IC3 = Low Noise FET I/P OPAMPS

RSET

12K

VRTref

Vblmref

Vbltwref

1K

3K9

10

2n2

0µ1

0µ22

0µ1

1K

3K9

10

2n2

0µ1

0µ22

1K

3K9

10

2n2

0µ1

0µ22

IC1

IC3

IC2

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VISION

VV6850 & 5850 Sensors: Product Datasheet Revision 1.0

APPENDIX A - FPN CANCELLATION SCHEMES

There are many possible ways achieve FPN cancellation in order to produce the hig hest quality
stills images from the VV6850 sensor. The exact method chosen will depend on the intended use
of the imager system, and the ancillary devices availab le in the system, such as the frame buffer
and mechanical shutter typical of a Digital Stills Camera. A number of schemes are discussed.

Multiple Dark Current Periods

The basic FPN cancellation scheme outlined in

O

PERATING MODES

- S

TILL IMAGE CAPTURE

can be
modified in many ways to suit a particula r appl icati on. One such var iati on mig ht be to ext end the
post image exposure ‘dark image’ ca pture period to some in tegral multiple of t he image exposure
period, in order to obtain a more accurate assessment of the dark current F PN:

1. With the shutter closed, release the sensor from reset and immediately read a frame into

buffer ‘A’ memory; this captures the array threshold FPN and reset noise (‘V

Reset

’)

2. Open the shutter and expose the sensor to the required scene

3. Close the shutter and immediately read the array; as each pixel is read, subtract the value for

that position stored in the frame buffer to obtain the image plus dark current FPN (V

im+VDark1

)

value; store this value in

second

frame buffer, ‘B’

4. After a further (say) four frame periods, read the array again; as each pixel is read, subtract

the reset value for that position as stored in the ‘A’ frame buffer, and overwrite the position,
leaving the V

im

+ V

Dark1

+ V

Dark2

value in the buffer

5. For each pixel, subtract the value in ‘B’ from that in ‘A’ to give V

Dark2

dark current value,

which is equivalent to four times the V

Dark1

value

6. Divide the V

Dark2

values in ‘A’ by 4, then subtract them from the (Vim + V

Dark1

) values in ‘B’

and store the result, which is the V

im

image data

The frame buffer now contains the corrected image values, which can be transferred to image
storage memory. This scheme is illustrated below:

Reset[n]
Read[n]

V

pix

VRT

V

Black

V

White

Read 1

V

Reset

Read 2 Read 3

V

Dark1

V

im

V

Dark2

Shutter

Exposure

Not to scale

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Appendix A - FPN Cancellation Schemes

16/06/97

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