Datasheet UPC8104GR-E1, UPC8104GR Datasheet (NEC)

DATA SHEET

DATA SHEET

BIPOLAR ANALOG INTEGRATED CI RCUIT

PC8104GR

µµµµ

UP CONVERTER + QUADRATURE MODULATOR IC
FOR DIGITAL MOBILE COMMUNICATION SYSTEMS

DESCRIPTION

The µPC8104GR is a silicon monolithic integrated circuit designed as quadrature modulator for digital mobile
communication systems. This modulator consists of 1.9 GHz up-converter and 400 MHz quadrature modulator which
are packaged in 20 pin SSOP. The device has power save function and can operate 2.7 to 5.5 V supply voltage,
therefore, it can contribute to make RF block small, high performance and low power consumption.

FEATURES

•

20 pin SSOP suitable for high density surface mounting.

•

High linearity up converter is incorporated; P

•

Low phase difference due to digital phase shifter is adopted.

•

Wide operating frequency range. Up converter; f

Modulator ; f

•

External IF filter can be applied between modulator output and up converter input terminal.

•

Supply voltage: VCC = 2.7 to 5.5 V

•

Equipped with power save function.

RFout(sat)

RFout
MODout

= −6 dBm TYP.

= 800 MHz to 1.9 GHz

= 100 MHz to 400 MHz, f

I/Q

= DC to 10 MHz

APPLICATION

•

Digital cordless phones

•

Digital cellular phones

ORDERING INFORMATION

PART NUMBER PACKAGE SUPPLYING FORM

µ

PC8104GR-E1 20 pin plastic SSOP Embossed tape 12 mm wide. QTY 2.5 kp/Reel.

Pin 1 indicates pull-out di rection of tape.

* For evaluation sample order, please contact your local NEC sales office. (Order number: µPC8104GR)

Caution electro-static sensitive device

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.

Document No. P10099EJ4V0DS00 (4th edition)
Date Published October 1999 N CP(K)
Printed in Japan

The mark shows major revised points.

©

1995, 1999

INTERNAL BLOCK DIAGRAM AND PIN CONNECTIONS (Top View)

1

Lo1 in

Lo1 in

GND

(MOD)

90˚

2

3

4

I

Phase
Shifter

REG.

CC

20

V

Power Save

19

GND

18

GND

17

µµµµ

PC8104GR

APPLICATION EXAMPLE

(PHS)

RX

SW

TX

PA

Q

Q

GND

(UP Con)

RF out

GND

(UP Con)

5

I

6

7

8

9

10

PLL÷N

PC8104GR

µ

MOD out

16

Up Con in

15

Up Con in

14

V

13

(UP Con)

Lo2 in

12

Lo2 in

11

0˚

φ

90˚

CC

DEMO.

PLL

I

Q

I

Q

Filter

2

Data Sheet P10099EJ4V0DS00

ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL RATING UNIT TEST CONDITION

µµµµ

PC8104GR

Supply Voltage V
Power Save Voltage V
Power Dissipation P
Operating Temperature T
Storage Temperature T

: Mounted on 50 × 50 × 1.6 mm double copper clad epoxy glass board

Note 1

CC

PS

D

A

stg

RECOMMENDED OPERATING CONDITIONS

PARAMETER SYMBOL MIN. TYP. MAX. UNIT TEST CONDITIONS
Supply Voltage V
Operating Temperature T
Up Converter RF Frequency f
Up Converter Input Freq. f
Modulator Output Frequency f
Lo1 Input Frequency f
Lo2 Input Frequency f
I/Q Input Frequency f

CC

A

RFout

UpConin

MODout

Lo1in

Lo2in

I/Qin

2.7 3.0 5.5 V
40 +25 +85

−

0.8 1.9 GHz

100 400 MHz

800 1800 MHz P
DC 10 MHz P

6.0 V TA = +25 °C

6.0 V TA = +25 °C

C
C

P

T

Lo1in

= −10 dBm

Lo2in

= −10 dBm

I/Qin

= 600 mV

430 mW

40 to +85

−

55 to +150

−

°
°

C

°

A

= +85 °C

Note1

p-p

MAX (Single ended)

ELECTRICAL CHARACTERISTICS (TA = +25

PARAMETER SYMBOL MIN. TYP. MAX. UNIT TEST CONDITIONS
UP CONVERTER + QUADRATURE MODULATOR TOTAL
Total Circuit Current I
Total Circuit Current at

Power-Save Mode
Total Output Power P
Lo Carrier Leak

Note2

Image Rejection (Side Band
Leak)

: Lo1 + Lo2

Note 2

ccTOTAL

cc(PS)TOTAL

I

RFout

LOL

ImR

18 28 37 m A No input signal

18.5

−

C, VCC = 3.0 V, Unless Otherwise Specified VPS

°°°°

0.1 10

13.5

−

40

−

40

−

8.5 dBm

−

30 dBc

−

30 dBc

−

AVPS ≤ 1.0 V

µ

I/Q DC = 1.5 V

I/Qin

= 500 mV

P

p-p

(Single ended)

1.8 V)

≥≥≥≥

Data Sheet P10099EJ4V0DS00

3

STANDARD CHARACTERISTICS FOR REFERENCE
(TA = +25

UP CONVERTER BLOCK
Up Con. Circuit Current I
Up Con. Circuit Current at

Power-Save Mode
Conversion Gain CG 4 dB f
Maximum Output Power P
Output Intercept Point OIP3 0 dBm
QUADRATURE MODULATOR BLOCK
MOD. Circuit Current I
MOD. Circuit Current at

Power-Save Mode
Output Power P
Lo1 Carrier Leak LOL
Image Rejection

(Side Band Leak)
I/Q 3rd Order Intermodulation

Distortion
I/Q Input Impedance Z
I/Q Bias Current I
Lo1 Input VSWR Z
Power Save Rise Time T
Power Save Fall Time T

C, VCC = 3.0 V, Unless Otherwise Specified VPS

°°°°

1.8 V)

≥≥≥≥

PARAMETER SYMBOL MIN. TYP. MAX. UNIT TEST CONDITIONS

ccUpCon

cc(PS)UpCon

I

RF(sat)

ccMOD

cc(PS)MOD

I

MODout

ImR

M3I/Q

I

I/Q

I/Q

Lo1

PS(RISE)

PS(FALL)

10 16 21 m A No input signal

12 m A No input signal

5

6dBm

−

5

16.5 dBm

−

40

−

40

−

50

−

30 dBc

−

30 dBc

−

30 dBc

−

20 k

5

AVPS ≤ 1.0 V

µ

AVPS ≤ 1.0 V

µ

Ω

A

µ

1.2:1 X:1

2.0 5.0

2.0 5.0

sV

µ

sV

µ

RFout

= 1.9 GHz

UpConin

= 240.0 MHz/240.2 MHz

f

I/Q DC = 1.5 V

I/Qin

P

= 500 mV

p-p

I/Q DC = 1.5 V

I/Qin

P

= 500 mV

p-p

(I → I, Q → Q)

PS(OFF)

PS(ON)

→ V

→ V

PS(ON)

PS(OFF)

µµµµ

PC8104GR

(Single ended)

(Single ended)

4

Data Sheet P10099EJ4V0DS00

PIN EXPLANATION

µµµµ

PC8104GR

PIN
NO.

ASSIGN­MENT

1 Lo1in

2 Lo1in

3 G ND for

SUPPLY
VOL. (V)

−

−

0

modulator

4IV

CC

/2

PIN
VOL.(V)

FUNCTION AND APPLICATION EQUIPMENT CIRCUIT

0 Lo1 input for phase shi f ter.

This input impedance is 50
matched internally.

2.4 Bypas s of Lo1 input.
This pin is grounded through
internal capacitor.
Open in case of single ended.

Connect to the ground with

−

minimum inductance.
Track length should be kept as
short as possible.

Input for I signal. This input

−

impedance is larger than 20 kΩ.
Relations between amplitude

CC

/2 bias of input signal

and V
are following.

VCC/2 (v) Amp. (mV

1.35 400

≥

1.5 600

≥

1.75 1000

≥

Ω

p-p

)

Note

1

50 Ω

2

45

5IV

6QV

7QV

16 MODout

CC

/2

CC

/2

CC

/2

−

Input for I signal. This input

−

impedance is larger than 20 kΩ.

CC

/2 biased DC signal should

V
be input.

Input for Q signal. This i nput

−

impedance is larger than 20 kΩ.

CC

/2 biased DC signal should

V
be input.

Input for Q signal. This i nput

−

impedance is larger than 20 kΩ.
Relations between amplitude

CC

/2 bias of input signal

and V
are following.

VCC/2 (v) Amp. (mV

1.35 400

≥

1.5 600

≥

1.75 1000

≥

1.5 Output from modulator.
This is emitter follower output.

76

p-p

)

Note

16

In case of that I/Q input signals are single ended.

Note

Of course, I/Q signal inputs can be used either single endedly or differentially with proper terminations.

Data Sheet P10099EJ4V0DS00

5

PIN EXPLANATION

µµµµ

PC8104GR

PIN
NO.

10

11 Lo2in

12 Lo2in

13 VCC for Up-

14 UpConin

ASSIGN­MENT

GND

80

for Up­converter

converter

9 RFout V

SUPPLY
VOL. (V)

−

−

2.7 to 5.5

CC

−

PIN
VOL.(V)

2.0 Bypas s of Lo2 input.

2.0 IF input f or Up-converter.

FUNCTION AND APPLICATION EQUIPMENT CIRCUIT

Connect to the ground with

−

minimum inductance.
Track length should be kept as
short as possible.

Grounded through external
capacitor.

0 Lo2 input of Up-convert er.

This pin is high impedance
input.

Supply voltage pin for Up-

−

converter.
RF output from Up-Converter.

−

This pin is open collect or out put.

This pin is high impedance
input.

12

11

9

15 UpConin

17 GND 0

18

19 Power

Save

20 VCC for

Modulator

V

2.7 to 5.5

: Externally

−

P/S

2.0 Bypas s of IF input.
Grounded through external
capacitor.

Connect to the ground with

−

minimum inductance.
Track length should be kept as
short as possible.

Power save control pin can be

−

controlled ON/SLEEP state with
bias as follows;

P/S

(v) STATE

V

1.8 to 5.5 ON
0 to 1.0 SLEEP

Supply voltage pin for

−

modulator. Internal regulator
can be kept stable condit i on of
supply bias against the variable
temperature or V

1514

19

CC

.

6

Data Sheet P10099EJ4V0DS00

EXPLANATION OF INTERNAL FUNCTION

BLOCK FUNCTION/OPERATI ON BLOCK DIAGRAM

µµµµ

PC8104GR

90° PHASE
SHIFTER

BUFFER AMP. Buffer amplifiers f or each phase signals to

MIXER Each signals from buffer amp. are

Input signal from Lo1 is s end to digital
circuit of T-type f l i p-flop through frequency
doubler. Output signal from T-ty pe F/ F i s
changed to same frequency as Lo1 i nput
and that have quadrature phase shift, 0°,
90°, 180°, 270°. These circuits hav e
function of self phas e correction to make
correctly quadrature signals.

send to each mixers.

quadrature modulated with two double­balanced mixers.
High accurate phase and amplitude i nput s
are realized to good performance for
image rejection.

from Lo1in

× 2

÷ 2 F/F

I
I

Q
Q

ADDER Output signals from eac h mixers are

added with adder and send to final
amplifier.

to MODout

Data Sheet P10099EJ4V0DS00

7

µµµµ

PC8104GR

TYPICAL CHARACTERISTICS (TA = +25

CC

Unless otherwise specified V

(single ended), P

Lo1in

= −10 dBm, P

= VPS = 3 V, I/Q DC offset = I/Q DC offset = 1.5 V, I/Q Input Signal = 500 mV

Lo2in

= −10 dBm, (continuous wave)

SUPPLY VOLTAGE vs CIRCUIT CURRENT

40

35

30

25

20

15

ICC - Circuit Current - mA

10

5

VCC = VPS = 3 V
RF None

CC Total

I
I

CC MOD
CC Up Con

I

C)

°°°°

p-p

[UP CONVERTER BLOCK]

SUPPLY VOLTAGE vs CONVERSION GAIN

: 1.9 GHz

RF

: 1.66 GHz, –20 dBm

Lo2

: 240 MHz, –20 dBm

IF

10

PS = VCC = 3 V

V

5

CG - Conversion Gain - dB

0

0123456

CC - Supply Voltage - V

V

0

0123456

CC - Supply Voltage - V

V

8

Data Sheet P10099EJ4V0DS00

[UP CONVERTER BLOCK] [UP CONVERTER BLOCK]

µµµµ

PC8104GR

INPUT POWER vs OUTPUT POWER, IM

+10

OIP3 = +0.2 dBm

0

–10

–20

- dBm

3

–30

–40

–50

- Up Con. Output Power, IM

out

P

–60

–70

–80

–40 –30 –20 –10 0 +10

P

RFout

IM

3

P

UpConin

- Up Con. Input Power - dBm

f

RFout

= 1.9 GHz

Lo2in

= 1.66 GHz

f

Lo2in

= –10 dBm

P

IFin1

= 240.0 MHz

f

IFin2

= 240.2 MHz

f

CC

= VPS = 3V

V

3

Lo2 INPUT POWER vs CONVERSION GAIN

f

RFout

= 1.9 GHz

Lo2in

= 1.66 GHz

f

10

IFin

= 240 MHz

f

IFin

= –20 dBm

P
V

CC

= VPS = 3 V

5

CG - Conversion Gain - dB

0

–40

–30 –20 –10 0 +10

P

Lo2in

- Lo2 Input Power - dBm

Data Sheet P10099EJ4V0DS00

9

[UP CONVERTER BLOCK] [UP CONVERTER BLOCK]

INPUT POWER vs OUTPUT POWER, IM

3

+10

0

–10

–20

–30

–40

–50

–60

–70

–80

–40 –30 –20 –10 0 +10

f

RFout

= 900 MHz

f

Lo2in

= 1 140 MHz

P

Lo2in

= –10 dBm

f

IFin1

= 240.0 MHz

f

IFin2

= 240.2 MHz

V

CC

= VPS = 3 V

P

UpConin

- Up Con. Input Power - dBm

P

out

- Up Con. Output Power, IM

3

- dBm

OIP3 = +7 dBm

P

RFout

IM

3

µµµµ

PC8104GR

SUPPLY VOLTAGE vs CONVERSION GAIN

RF

: 900 MHz

Lo2

: 1 140 MHz, –20 dBm

IF

15

: 240 MHz, –20 dBm

V

PS

= VCC = 3 V

10

GC - Conversion Gain - dB

5

0123456

V

CC

[UP CONVERTER BLOCK] [MODULATOR BLOCK]

- Supply Voltage - V

Lo2 INPUT POWER vs CONVERSION GAIN

f

RFout

= 900 MHz

Lo2in

= 1 140 MHz

f
f

IFin

= 240 MHz

IFin

= –20 dBm

P

15

V

CC

= VPS = 3 V

10

CG - Conversion Gain - dB

5

–40

–30 –20 –10 0 +10

P

Lo2in

- Lo2 Input Power - dBm

Lo1 INPUT POWER vs OUTPUT POWER,
LOCAL LEAK, IMAGE REJECTION,
I/Q 3RD ORDER INTERMODULATION
DISTORTION

10

<PHS>
384 kbps
RNYQ

0

α = 0.5
<0000>
All zero

I/Q - dBc

3

–10

P

out

–10

–20

10

–20

–30

–40

) - Local Leak, ImR - Image Rejection, IM

–50

LO

LOL (ISO

–60

–70

Data Sheet P10099EJ4V0DS00

LOL (ISOLO)

ImR

IM

3I/Q

–30 –20 –10 0 +10

P

Lo1in

- Lo1 Input Power - dBm

–30

- Modulator Output Power - dBm

MODout

P

–40

–50

[MODULATOR BLOCK] [MODULATOR BLOCK]

10

0

–10

–20

–30

–40

–50

–60

–70

–10

–20

–30

–40

–50

0 0.5 1

P

I/Qin

- I/Q Input Signal - V

p-p

LOL (ISO

LO

) - Local Leak, ImR - Image Rejection, IM

3

I/Q - dBc

I/Q INPUT SIGNAL vs OUTPUT POWER,
LOCAL LEAK, IMAGE REJECTION,
I/Q 3RD ORDER INTERMODULATION
DISTORTION

P

MODout

- Modulator Output Power - dBm

IM

3I/Q

ImR

P

out

(PHS) 384 Kbps
RNYQ α = 0.5
(0000) All zero

LOL (ISOLO)

LOL(ISO

LO

) - Local Leak, ImR - Image Rejection, IM

3

I/Q - dBC

P

MODout

- Modulator Output - Power - dBm

IM

3I/Q

ImR

P

out

LOL (ISOLO)

–10

–20

–30

–40

–50

–60

–70

–10

–20

–30

–40

–50

–60

–70

f

Lo1

- Lo1 Input Frequency - MHz

50 100 200 500

Lo1 INPUT FREQUENCY vs OUTPUT POWER,
LOCAL LEAK, IMAGE REJECTION, I/Q 3RD,
ORDER INTERMODULATION DISTORTION

µµµµ

PC8104GR

[MODULATOR + UP CONVERTER] [MODULATOR BLOCK]

I/Q INPUT SIGNAL vs VECTOR ERROR,
MAGNITUDE ERROR, PHASE ERROR

- Phase Error - deg.

∆φ

10

7

5

3

A - Magnitude Error - %rms

M - Vector Error - %rms

∆

∆

2
1
0

0 500 1 000 1 500

P

I/Qin

- I/Q Input Signal - mV

VCC = 3 V
Lo1: 240 MHz

–10 dBm

Lo2: 1 660 MHz

–8 dBm
I/Q DC 1 500 mV
AC
<PHS> 384 kbps
RNYQ α = 0.5

∆

∆

∆φ

PN9

M

A

p-p

Lo1 INPUT FREQUENCY vs VECTOR ERROR,
MAGNITUDE ERROR, PHASE ERROR

VCC = 3 V
Lo1: 15 dBm
I/Q DC 1 500 mV

10

AC 430 mV
<PHS> 384 kbps
RNYQ α = 0.5
PN9

7

5

3

- Phase Error - deg.

A - Magnitude Error - %rms

M - Vector Error - %rms

∆

∆

∆φ

2
1
0

0 200 400

p-p

∆

M

∆

A

∆φ

100 300 500

Lo1 - Lo1 Input Frequency - MHz

f

Data Sheet P10099EJ4V0DS00

11

[MODULATOR + UP CONVERTER] [MODULATOR BLOCK]

µµµµ

PC8104GR

TYPICAL SINE WAVE MODULATION
OUTPUT SPECTRUM

CENTER 240.0000 MHz

REF 0.0 dBm
10 dB/

RBW
3 kHz
VBW
10 kHz
SWP

5.0 s

TYPICAL SINE WAVE MODULATION
OUTPUT SPECTRUM

–ATT 10 dB

CENTER 1.9000000 GHz

<PHS> 384 Kbps, RNYQ α = 0.5, MOD Pattern (0000), all zero.

SPAN 200.0 kHz

REF 0.0 dBm
10 dB/

RBW
1 kHz
VBW
1 kHz
SWP

2.0 s

[MODULATOR + UP CONVERTER] [MODULATOR BLOCK]

TYPICAL π/4 DQPSK MODULATION OUTPUT SPECTRUM
<PDC> 42 kbps, RNYQ α = 0.5, MOD Pattern <PN9>

REF 0.0 dBm
10 dB/

ADJ BS

21.0 kHz
DL 0.0 dBm
RBW 3 kHz

VBW 3 kHz
SWP 5.0 s

CENTER 1.500000 GHz SPAN 500 kHz

∗∗∗ Multi Marker List ∗∗∗
No. 1: 1.4999000 GHz –72.00 dB
No. 2: 1.4999500 GHz –66.00 dB
No. 3: 1.5000500 GHz –68.75 dB
No. 4: 1.5001000 GHz –72.00 dB

1

ATT 10 dB

2

MARKER

1.4999000 GHz

72.00 dB

3

4

REF –10.0 dBm
10 dB/

ADJ BS

21.0 kHz
DL –10.0 dBm
RBW 3 kHz

VBW 3 kHz
SWP 5.0 s

CENTER 240.0000 MHz SPAN 500 kHz

∗∗∗ Multi Marker List ∗∗∗
No. 1: 239.9000 MHz –76.50 dB
No. 2: 239.9500 MHz –70.50 dB
No. 3: 240.0500 MHz –71.00 dB
No. 4: 240.1000 MHz –75.75 dB

1

ATT 0 dB

2

ATT 10 dB

MARKER

289.9000 MHz

76.50 dB

3

4

SPAN 200.0 kHz

[MODULATOR + UP CONVERTER] [MODULATOR BLOCK]

TYPICAL π/4 DQPSK MODULATION OUTPUT SPECTRUM
<PHS> 384 kbps, RNYQ α = 0.5, MOD Pattern (PN9)

REF –10.0 dBm
10 dB/

ADJ BS
192 kHz

DL –10.0 dBm
RBW 3 kHz

VBW 10 kHz
SWP 5.0 s

CENTER 1.900000 GHz SPAN 2.000 MHz

12

ATT 0 dB

MARKER

1.899100 GHz

69.50 dB

21

∗∗∗ Multi Marker List ∗∗∗
No. 1: 1.899100 GHz –69.50 dB
No. 2: 1.899400 GHz –69.00 dB
No. 3: 1.900600 GHz –69.00 dB
No. 4: 1.900900 GHz –69.50 dB

REF –10.0 dBm
10 dB/

ADJ BS
192 kHz

43

Data Sheet P10099EJ4V0DS00

DL –10.0 dBm
RBW 3 kHz

VBW 10 kHz
SWP 5.0 s

CENTER 240.000 MHz SPAN 2.000 MHz

∗∗∗ Multi Marker List ∗∗∗
No. 1: 239.100 MHz –68.75 dB
No. 2: 239.400 MHz –68.25 dB
No. 3: 240.600 MHz –68.25 dB
No. 4: 240.900 MHz –69.00 dB

ATT 0 dB

21

MARKER

239.100 MHz

68.75 dB

43

RFout OUTPUT IMPEDANCE

MARKER 3

1.9 GHz

3; 162.25 Ω –87.695 Ω 955.19 fF

1 900.000 000 MHz

RF out
Marker

µµµµ

PC8104GR

Lo2in INPUT IMPEDANCE

MARKER 2

1.66 GHz

3

1
2

STOP 2 000.000 000 MHzSTART 800.000 000 MHz

2; 20.184 Ω –113.66 Ω 843.51 fF

1 660.000 000 MHz

1. 900 MHz

2. 1.5 GHz

3. 1.9 GHz

Lo2 in
Marker

STOP 1 900.000 000 MHzSTART 800.000 000 MHz

Data Sheet P10099EJ4V0DS00

1. 900 MHz

2. 1.66 GHz

3. 1.8 GHz

1

2

3

13

MODout OUTPUT IMPEDANCE

MARKER 2
240 MHz

2; 49.244 Ω 13.58 Ω 9.0056 nH

240.000 000 MHz

2

3

1

MOD out
(IF out)

Marker

1. 100 MHz

2. 240 MHz

3. 400 MHz

µµµµ

PC8104GR

UP CON. in INPUT IMPEDANCE

MARKER 2
240 MHz

STOP 500.000 000 MHzSTART 50.000 000 MHz

2; 262.19 Ω –394.97 Ω 1.679 pF

240.000 000 MHz

2

1

3

Up Con in
(IF in)

Marker

1. 100 MHz

2. 240 MHz

3. 400 MHz

14

STOP 500.000 000 MHzSTART 50.000 000 MHz

Data Sheet P10099EJ4V0DS00

Lo1in INPUT IMPEDANCE

MARKER 2
240 MHz

2; 51.727 Ω –2.0059 Ω 330.5 pF

240.000 000 MHz

Lo1 in

µµµµ

PC8104GR

TEST CIRCUIT
(fRF = 1.9 GHz)

CC 10 kΩ

V

20 19 18 17 16 15 14 13 12 11

VCC

GND

Power Save

GND

1 000 pF

100
pF

MOD out

Up Con in

2

3

1

STOP 500.000 000 MHzSTART 50.000 000 MHz

CC

V

Up Con in

Lo2 in

100 pF

100 pF

Lo2 in

Marker

1. 100 MHz

2. 240 MHz

3. 400 MHz

Lo2

S.G

f

Lo2 = 1.5 to 1.8 GHz

IN = –10 dBm

P

Lo1

S.G

fLo1 = 100 to 400 MHz
P

IN = –10 dBm

Lo1 in

Lo1 in

GND

I

I

Q

Q

GND

12345678910

Open

1000 pF

IIQQ

I/Q Signal Generator

f : DC to hundreds kHz

p-p (I, Q only)

A : 0.5 V
V : 1.5 V (I, I, Q, Q)

Data Sheet P10099EJ4V0DS00

RFout

L

GND

C

µ

0.1 H

100
pF

L: (Micro Stripline)
C: around 3 pF

S.P.A

f

RF = 1.9 GHz

15

TEST BOARD

CC (MOD)

V

10 000 pF

P.S.

10 000 pF

V

CC (Up Con.)

10 000 pF

µµµµ

PC8104GR

Lo1

1 000 pF

1 000 pF

(OPEN)

1 000 pF

10 K

100 pF

10 000 pF

10 000 pF

1 000 pF

100 pF

100 pF

100 nH

QI

1 000 pF

3 pF

3 pF

100 pF

Lo2

RF

QinIin

In case of this test board,
the output signal from MOD.
is directly connected to the
up converter input port through
1000 pF, which is DC coupling.

We recommend to insert
a low pass filter between
MOD output and up converter

out

input port to reject
harmonics of the Lo1 signal
and to avoid saturation
of the up converter.

GND

fRF = 1.9 GHz

Lo2 = 1.66 GHz

f

Lo1 = 240 MHz

f

16

Data Sheet P10099EJ4V0DS00

PACKAGE DIMENSIONS

20 PIN PLASTIC SSOP (225 mil) (UNIT: mm)

µµµµ

PC8104GR

20

110

6.7 ± 0.3

1.8 MAX.

1.5 ± 0.1

11

detail of lead end

3˚

6.4 ± 0.2

4.4 ± 0.1

+7˚
–3˚

1.0 ± 0.2

NOTE

0.5 ± 0.2

0.15

+0.10
–0.05

0.1 ± 0.1

0.65

0.22

+0.10
–0.05

0.10

0.15

M

0.575 MAX.

Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition.

Data Sheet P10099EJ4V0DS00

17

µµµµ

PC8104GR

NOTE ON CORRECT USE

(1) Observe precautions for handling because of electrostatic sensitive devices.
(2) Form a ground pattern as wide as possible to keep the minimum ground impedance (to prevent undesired

oscillation).
(3) Keep the track length of the ground pins as short as possible.
(4) Connect a bypass capacitor (e.g. 1 000 pF) to the VCC pin.
(5) I, Q DC offset voltage should be same as the I, Q DC offset voltage (to prevent changing the local leak level with

power save control.)

RECOMMENDED SOLDERING CONDITIONS

This product should be soldered in the following recommended conditions. Other soldering methods and

conditions than the recommended conditions are to be consulted with our sales representatives.

PC8104GR

µµµµ

Soldering Method Soldering Conditions Symbol

Infrared ray reflow Peak package’s surface temperature: 235 °C or below,

Reflow time: 30 seconds or bel ow (210 °C or higher),
Number of reflow process: 3, Exposure limit

VPS Peak package’s surface temperature: 215 °C or below,

Reflow time: 40 seconds or bel ow (200 °C or higher),
Number of reflow process: 3, Exposure limit

Wave soldering Solder temperature: 260 °C or below

Flow time: 10 seconds or below,
Number of reflow process: 1, Exposure limit

Partial heating method Terminal temperature: 300 °C or below

Flow time: 3 seconds/pi n or bel ow,
Exposure limit

Exposure limit before soldering after dry-pack package is opened.

Note

Note

: None

Note

Note

Note

: None

: None

: None

IR35-00-3

VP15-00-3

WS60-00-1

Storage conditions: 25 °C and relative humidity at 65 % or less.

Caution Apply only a single process at once, except for “Partial heating method”.

For details of recommended soldering conditions for surface mounting, refer to information
document SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL (C10535E)

The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.

18

Data Sheet P10099EJ4V0DS00

[MEMO]

µµµµ

PC8104GR

Data Sheet P10099EJ4V0DS00

19

µµµµ

PC8104GR

• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.

• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.

• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.

• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.

• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.

M7 98. 8