Datasheet up6212 Datasheets

Page 1

uP6212

3 Phase Synchronous-Rectified Buck Controller

for Next Generation CPU Core Power

General Description

The uP6212 is a multi-phase synchronous-rectified buck controller specifically designed to deliver high quality output voltage for high-performance microprocessors and graphic processors.

The uP6212 provides programmable 2/3-phase operation. It also supports dynamic phase selection by PS1/2 pins that automatically switches to single/two phase operation at light load condition. The uP6212 supports both standalone and tracking mode operation. The output voltage is tightly regulated to local or external reference voltages.

The uP6212 extract phase current signals by R side switches for phase current balance. It senses the output current by DCR of output inductors for load line slope setting and over current protection. This yields both thermal balance and accurate load line adjustment.

The uP6212 includes programmable no-load offset and droop slope functions to adjust the output voltage as a function of the load current, optimally positioning it for a system transient.

Other features include accurate and reliable short-circuit protection, adjustable over current protection, and a delayed power OK output. This part is available in VQFN4x4 - 24L package.

DS(ON)

of low

Features



 Interleaved Two/Three Phase Operation



 Programmable Dynamic Power Saving Mode



Operation



 Simple Single-Loop Voltage-Mode Control



 Lossless R



Current Sensing for Current

DS(ON)

Balance



 Adjustable Operation Frequency form 50kHz to



1MHz Per Phase



 External Compensation



 Adjustable Over Current Protection



 Adjustable Soft Start



 VQFN4x4 -24L Package



 RoHS Compliant and 100% Lead (Pb)-Free



Ordering Information

rebmuNredrOepyTegakcaPkrameR

GAQA2126PuL42-4x4NFQV

Note: uPI products are compatible with the current IPC/ JEDEC J-STD-020 requirements. They are halogen-free, RoHS compliant and 100% matte tin (Sn) plating that are suitable for use in SnPb or Pb-free soldering processes.

pplications



 Desktop PC Core Power Supplies



 Middle/High End Graphic Cards



 Low Output Voltage, High Power Density DC/DC



Converters



 Voltage Regulator Modules



PWM3

PWM2

PWM1

POK

Pin Configuration

VCC5

17 16 1518

REFIN

ISEN1

GND

FBRTN

ISEN2

4321

ISEN3

14 13

GND

PS1

OFS

IMAX

CSN

CSP

COMP

FBVOUT

PS2

1uPI Semiconductor Corp., http://www.upi-semi.com

Rev. F00, File Name: uP6212-DS-F0000

Page 2

uP6212

Typical Application Circuit

PH3

PH1

PH2

CORE1

CORE2

CORE3

POK

PS1

PS2

IMAX

CSP

CSN

ISNE1

PWM1

VCC5

GND

ISNE2

PWM2

ISEN3

VCC5

DrMOS

PWM

REG5V

CGND

DrMOS

PWM

REG5V

CGND

VSWH

VIN

PGND

VSWH

VIN

PGND

CORE1

CORE2

OUT

REF

VCC5

COMP

VOUT

REFIN

FBRTN

PWM3

OFS

DrMOS

PWM

REG5V

CGND

VSWH

VIN

PGND

VCC5

CORE3

OUT

Rev. F00, File Name: uP6212-DS-F0000

2uPI Semiconductor Corp., http://www.upi-semi.com

Page 3

.oNemaNnoitcnuFniP

uP6212

Functional Pin Descriptio

1BT

2NIFER

3NTRBF

4SS

5DNG

62SP

7BF

8PMOC

9PSC

01NSC

11XAMI

21SFO

311SP

.tsooBtneisnarT .roivahebtsoobtneisnartehttesnipTUOVehthtiwgnolanipsihT

.tupnIecnerefeRlanretxE .rotsiserahguorhtegatlovecnereferlanretxenaotnipsihttcennoC

.epolsenildaolehtstesrotsiserehT

.tiucriCecnerefeRehtrofnruteR otsiegatlovtuptuoerehwtniopdnuorgehtotsihttcennoC

.detalugereb

.tratStfoS .emittratstfosehttesotDNGotnipsihtmorfroticapacatcennoC

.dnuorG

.2tupnIgnitteSedoMgnivaSrewoP esahpehttesotDNGotnipsihtmorfrotsiseratcennoC

.leveldlohserhtnoitcuder

.niPkcabdeeF .reifilpmarorreehtfotupnignitrevniehtsinipsihT

.tuptuOnoitasnepmoC reifilpmarorreehtfotuptuoehtsinipsihT

.reifilpmAMGgnisneStnerruCehtfotupnIevitisoP

.reifilpmAMGgnisneStnerruCehtfotupnIevitageN

.noitacidnItnerruCtuptuO tnerrucrevoehttesotDNGotnipsihtmorfrotsiseratcennoC

.levelnoitcetorp

.tesffOtnerruCoreZ tesffotuptuoehttesotDNGro5CCVotnipsihtmrofrotsiseratcennoC

.egatlov

.1tupnIgnitteSedoMgnivaSrewoP ehttesotdnuorgotnipsihtmorfrotsiseratcennoC

.leveldlohserhtnoitcuderesahp

61/51/411/2/3NESI

71TR

815CCV

12/02/911/2/3MWP

22NE

32KOP

42TUOV

DNG

.1/2/3esahProfgnisneStnerruC

.gnimmargorPycneuqerFgnihctiwS ehttesotDNGotnipsihtmorfrotsiseratcennoC

.ycneuqerfgnihctiws

.tupnIylppuS .tiucriclortnocehtrewopotecruosegatlovV5detalugerllewaseviecernipsihT

.1/2/3esahProftuptuOMWP

.elbanEpihC ecivedehtnwodstuhsV4.0nahtrewolnipsihtgnilluP .

.noitacidnIdooGrewoP

.gnisneSegatloVtuptuO .roivahebtsoobtneisnartehttesnipBTehthtiwgnolanipsihT

daPdesopxE

.dnuorGrewoP iTecnadepmitsewolehthguorhtenalp/dnalsidnuorgehtotnipsihte

.elbaliavanoitcennoc

Rev. F00, File Name: uP6212-DS-F0000

3uPI Semiconductor Corp., http://www.upi-semi.com

Page 4

uP6212

Functional Block Diagram

Band GapFBRTN

REFIN

OFS Offset

ISEN1

ISEN2

ISEN3

REFIN

0.8V V

EAP

300mV

REF

–

Reference

Selection

POK

Soft Start

Power OK

UVP OVP

EAP

160mV

EAP

Current

Balance

VCC5

POR

Transient

Boost

VOUT

COMP

PWM1

PWM2

PWM3

IMAX

CSN

CSP

1.2V

GND

OCP

Oscillator

PS1

PS2

Rev. F00, File Name: uP6212-DS-F0000

4uPI Semiconductor Corp., http://www.upi-semi.com

Page 5

The uP6212 is a multi-phase synchronous-rectified buck controller specifically designed to deliver high quality output voltage for high-performance micro processors and graphic processors.

The uP6212 provides programmable 2/3-phase operation. It also supports dynamic phase selection by PS1/2 pins that automatically switches to single phase operation at light load condition. The uP6212 supports both stand-alone and tracking mode operation. The output voltage is tightly regulated to local or external reference voltages.

The uP6212 extract phase current signals by R

DS(ON)

of low side switches for phase current balance. It senses the output current by DCR of output inductors for load line slope setting and over current protection. This yields both thermal balance and accurate load line adjustment.

The uP6212 includes programmable no-load offset and slope functions to adjust the output voltage as a function of the load current, optimally positioning it for a system transient.

Other features include accurate and reliable short-circuit protection, adjustable over current protection, and a delayed power OK output. This part is available in VQFN4x4-24L package.

Supply Input and Power on Reset

uP6212

Functional Description

0.4V

0.8V V

4.0V

REF

uP6212

(kHz)

EAP

FBRTN

REFIN

Band

Gap

REFIN

Figure 1. Reference Voltage Selection.

Oscillation Frequency Programming

A resistor RRT connected to RT pin programs the oscillation frequency as:

10000

)k(R

Ω

OSC

Figure 2 shows the relationship between oscillation frequency and RRT.

1000

The uP6212 receives supply input from VCC5 pin to power the internal control circuit. RC filter is required for locally bypassing the supply input pin. The VCC5 voltage is continuously monitored for power on reset. The POR level is typical 4.2V at VCC5 rising.

Operation Phase Selection

The uP6212 supports 2/3 phase operation. PS2 status is checked at POR for operation phase selection. 2 phase operation is selected if PS2 < 0.1V at VCC5 POR. When operating at 2 phase, phase 3 is turned off and clock signals of phase1/2 are kept output of phase. When operating at 3 phase, clock signals are kept 120OC difference to each other. Leave PWM3 and ISEN3 floating when operating in 2 phase.

Reference Voltage Selection

The uP6212 supports both stand alone and tracking mode operation. REFIN voltage is checked at VCC5 POR for reference voltage selection as shown in Figure 1. The FB voltage is regulated to internal 0.8V reference voltage if V

REFIN

is higher than 4V at VCC POR. Otherwise, the FB voltage is regulated to track V

. See the Voltage Control Loop

REFIN

section for details.

Switching Frequency (kHz)

100

10 100

RRT (kohm)

Figure 2. Switching Frequency vs. RRT.

Output Current Sensing

Figure 3 illustrates the output current sensing block of the uP6212. The voltage VCS across the current sensing capacitor CCS can be expressed as:

= I

VCS

x DCR/P

OUT

if the following condition is true.

P x L / DCR = R

CSP

x C

Rev. F00, File Name: uP6212-DS-F0000

5uPI Semiconductor Corp., http://www.upi-semi.com

Page 6

uP6212

Functional Description

where P is the phase number of operation (P = 2 for two phase operation, P = 3 for three phase operation), L is the output inductor of the buck converter, DCR is the parasitic resistance of the inductor, R

and CCS are the external RC

CSP

network for current sensing.

The GM amplifier will source a current I

to the CSN pin to

AVG

let its inputs virtually short circuit.

x R

CSN

= V

can be expressed

AVG

Therefore the output current signal I as:

DCRI

AVG

The output current signal I

OUT

CSN

is used as droop tuning and

AVG

output over current protection. Please see the related

section for details.

PH1

PH2

CSP

PH3

where V

is the output voltage, I

OUT

is a current source

OFS

for initial offset adjustment, RFB is an external resistor.

The Error Amplifier modulates the COMP voltage V

COMP

and the duty cycle of buck converter to force FB voltage V follows V

= V

OUT

. Therefore, the output voltage will be:

EAP

- K x R

EXT

VV ×+

−=

EXT

DROOP

x I

AVG

××

CSN

+ RFB x I

RDCRI

DROOPOUT

OFS

OFSFB

Please see the related section for details.

4.0V

REFIN

Band

K x I

Gap

0.4V

AVG

0.8V V

EAP

REF

EXT

DROOP

REFIN

FBRTN

COMP

OUT

CSP

uP6212

CSP

DCRDCRDCR

CSP

CSN

Amplifer

AVG

Figure 3. Output Current Sensing of uP6212.

Voltage Control Loop (External Reference Voltage)

Figure 4 illustrates the voltage control loop for external reference voltage of the uP6212. VFB and V

are negative

EAP

and positive inputs of the Error Amplifier respectively. The EAP pin voltage is expressed as:

= V

EAP

where V

- K x R

EXT

is a slew rate limited voltage source, I

EXT

DROOP

x I

AVG

is a current source proportional to output current, K a current mirror gain (K = 3 for three phase operation, K = 2 for two phase operation) and R

is an external resistor for

DROOP

adjusting load line slope.

The FB pin voltage VFB is expressed as:

VFB = V

- RFB x I

OUT

OFS

OUT

OFS

uP6212

Error

Amplifier

Figure 4. Voltage Control Loop for External Reference.

Please note the external reference voltage V

changing

EXT

slew rate should be limited to a safe level. A large step change of V

should be avoided as it may result in

EXT

large inrush current to charge and discharge the output capacitors and result in false triggering of OCP, UVP and OVP protection functions.

Voltage Control Loop (Internal Reference Voltage)

Figure 5 illustrates the voltage control loop for internal reference voltage of the uP6212. VFB and V

are negative

EAP

and positive inputs of the Error Amplifier respectively. The Error Amplifier modulates the COMP voltage V

COMP

and the duty cycle of buck converter to force FB voltage VFB follows V

EAP

= 0.8V

EAP

Note that there is no droop function when internal reference voltage is selected.

Rev. F00, File Name: uP6212-DS-F0000

6uPI Semiconductor Corp., http://www.upi-semi.com

Page 7

uP6212

Functional Description

RRIVR

××−×

where V

is the output voltage, I

OUT

for initial offset adjustment, R

2FB1FB

FB1

and R

2RFB1FBOFSOUT2FB

is a current source

OFS

are external resistor

FB2

divider for voltage setting.

Therefore, the output voltage will be:

OUT

2FB

Please see the related section for details.

4.0V

REFIN

Band

Gap

0.4V

0.8V V

EAP

VCC5

FBRTN

REFIN

COMP

during soft start and V to 0.4V higher than V V

during soft start and V

EAP

changes. Since Vss is clamped

REFIN

, this limit the slew rate of VSS and

EAP

changes. This consequently

REFIN

limits the output voltage ramp up/down slew rate.

The uP6212 is POR and enabled at T0. There is a 800us time delay (T0 ~ T1) before the current source ISS begins charging the CSS. The non-inverting input V voltage V

RRI)RR(V8.0

××++×

2FB1FBOFS2FB1FB

VOUT ramps up to target value during time delay TD2. The

is kept zero during (T0 ~ T2). The V

OUT

and output

EAP

and

uP6212 inserts a time delay TD3 before assertion of power OK. The uP6212 asserts soft start end and set POK to high impedance status at T4.

Time periods are calculated as:

(T2 - T1) = 0.4V x CSS / 10uA

TD1 = T2 - T0 = 800us + 0.4V x CSS / 10uA

REF

TD2 = V

TD3 = (4.1V - V

where V

0.8V for internal reference voltage, V

x CSS / 10uA = V

BOOT

) / 10uA

EAP

is the initial boot up reference voltage. V

BOOT

x CSS / 10uA

EAP

BOOT

= V

for external

EXT

BOOT

reference voltage.

FB2

FB1

OUT

OFS

uP6212

Error

Amplifier

Figure 5. Voltage Control Loop for Internal Reference.

Initial Offset Adjustment

Connect a resistor R set the initial offset voltage. The OFS voltage V

from OFS pin to VCC5 or GND to

OFS

is V

CC5

1.6V or 0.4V when connected to VCC5 or GND respectively. There the current source I

= 0.4V / R

OFS

= 1.6V / R

OFS

sourcing, R

OFS

sinking, R

OFS

The offset current source I

can be calculated as:

OFS

to GND, positive offset

OFS

to VCC5, negative offset.

OFS

is mirrored and injected to FB

OFS

pin for initial offset adjustment. Please see the Voltage Control Loop section for details.

Soft Start and Power OK

Figure 6 illustrates the soft start cycle of uP6212. A capacitor CSS connected to SS pin is used to adjust the soft start cycle.

A 10uA current source ISS is used to charge/discharge C

VCC5

OUT

POK

T0 T1 T2 T3

TD2TD1

4.0V

TD3

Figure 6. Soft Start Cycle of the uP6212.

Channel Current Sensing

The uP6212 extracts phase currents for current balance and over current protection by parasitic on-resistance of the lower switches when turn on as shown in Figure 7. The ISEN1/2/3 pins sense the corresponding phase current when the low side MOSFETs are turns on.

= ((I

SENX

where I

x R

PHX

is the sampled and held phase current signal,

SENX

DS(ON)

) + VDC) / R

SENX

Rev. F00, File Name: uP6212-DS-F0000

7uPI Semiconductor Corp., http://www.upi-semi.com

Page 8

is phase current, R

PHX

is the on-resistance of the low

DS(ON)

side MOSFETs, and VDC is an offset voltage for the current balance circuit. The current balance circuit increases the duty cycle of the phase whose phase current is smaller than others and decrease the duty cycle of the phase whose phase current is larger than others.

PH2PH1 PH3

SEN1

SEN2

SEN3

Current

Balance

ISEN1

SEN1

SEN2

ISEN2

ISEN3

uP6212

Figure 7. Phase Current Sensing and Current Balance.

uP6212

Functional Description

, V

IMAX

PS1

. Take V

PS2

0.25V for example, the uP6212 turns off phase 3 and operates the converter in 2-phase. Note that the uP6212 do not reset the clock sequence during dynamic phase reduction. Phase 1 and phase 2 still has 120O phase shift.

The automatic phase reduction reduces the switching and conduction losses at light load condition and enables high efficiency over a wide range of output current.

PS2

> R

and V

PS1

PS2

programming the phase-reduction threshold level.

Table 1. Operation Phase Selection.

1SP

V8.0>X 3/2/1

XAMI

= 0.2V, V

PS1

= 0.3V and V

PS2

IMAX

> 0.2V are recommended when

2SP

esahPnoitarepO

V1.0<2/1

V1.0<1

XAMI

3/2/1

2/1

Select R is to keep I

to set the current balance gain. A rule of thumb

SEN

= 5uA at rated output current.

SENX

Output Over Current Protection

is mirrored and injected to the IMAX pin and create a

AVG

voltage V

= K x R

IMAX

at IMAX pin.

IMAX

x I

IMAX

AVG

= R

IMAX

x I

OUT

x DCR / R

CSN

The over current protection is activated and shuts down the uP6212 if the IMAX voltage is higher than 1.2V.

Output Over Voltage Protection

The OVP is activated and turns on the low side MOSFETs if ( VFB - V

) > 160mV

EAP

The over voltage protection is latch-off and can only be reset by POR or toggling the EN pin.

Under Voltage Protection

The under voltage protection is activated if FB voltage V is 300mV lower than the V

. UVP turns off and latches

EAP

the uP6212.

Power Saving Mode and Automatic Phase Reduction

The uP6212 sources a 10uA current source out of PS1 and PS2 pins. Connecting resistors R PS2 pins creates voltage levels V

PS1

and R

and V

at PS1 and

PS2

for power

PS2

saving mode operation.

Transient Boost Mechanism

The uP6212 features a novel transient boost mechanism that turns on all high side MOSFETs during a large step load transient as shown in Figure 8. The VOUT and TB are inverting and non-inverting inputs of the transient boost comparator respectively. At steady state, an internal 10uA current source creates a voltage drop between V VTB:

- VTB = 10uA x R

OUT

RTB and CTB form a low pass filter for the VTB. During large step load transient, V relatively constant. Once V

abruptly drops while the VTB keeps

OUT

is smaller than VTB, the

OUT

transient boost mechanism is activated and turns on all high side MOSFETs to provide current to output capacitors as fast as possible.

Select RTB to decide a suitable threshold level for transientboost. For example, a 4.7kΩ RTB will triggered the transient boost mechanism if output voltage is abruptly drops by around 50mV. Also keep the RTB x CTB time constant around 2us.

OUT

and

= 10uA x R

PS1

= 10uA x R

PS1

Table 1 shows the operation phase of uP6212 according to

Rev. F00, File Name: uP6212-DS-F0000

8uPI Semiconductor Corp., http://www.upi-semi.com

Page 9

uP6212

Functional Description

OUT

VOUT

10uA

Figure 8. Transient Boost Mechanism

Transient

Boost

uP6212

Rev. F00, File Name: uP6212-DS-F0000

9uPI Semiconductor Corp., http://www.upi-semi.com

Page 10

uP6212

bsolute Maximum Ratin

Supply Input Voltage, VCC5 (Note 1) ----------------------------------------------------------------------------------------------- -0.3V to +6.0V

Other Pins ---------------------------------------------------------------------------------------------------------------------------- -0.3V to +VCC5 +0.3V Storage Temperature Range ------------------------------------------------------------------------------------------------------------- -65OC to +150OC Junction Temperature ------------------------------------------------------------------------------------------------------------------------------------ 150OC Lead Temperature (Soldering, 10 sec) ------------------------------------------------------------------------------------------------------------ 260OC ESD Rating (Note 2)

HBM (Human Body Mode) --------------------------------------------------------------------------------------------------------------------- 2kV MM (Machine Mode) ----------------------------------------------------------------------------------------------------------------------------- 200V

Thermal Informatio

Package Thermal Resistance (Note 3)

VQFN4x4-24L θJA ------------------------------------------------------------------------------------------------------------------------- 40OC/W VQFN4x4-24L θ

Power Dissipation, PD @ TA = 25°C

VQFN4x4-24L ------------------------------------------------------------------------------------------------------------------------------------- 2.5W

------------------------------------------------------------------------------------------------------------------------ 4OC/W

Recommended Operation Conditions

Operating Junction Temperature Range (Note 4) ------------------------------------------------------------------------ -40°C to +125°C Operating Ambient Temperature Range -------------------------------------------------------------------------------------- -40°C to +85°C Supply Input Voltage, V

------------------------------------------------------------------------------------ 4.5V to 5.5V

CC5

Electrical Characteristics

VCC5 = 5V, TA = 25OC, unless otherwise specified)

retemaraPlobmySsnoitidnoCtseTniMpyTxaMtinU

tupnIylppuS

egatloVtupnIylppuSV

tnerruCylppuSI

dlohserhTROP5CCVV

siseretsyHROP5CCVV

5CC

HTR5CC

SYH5CC

nepoxMWP0.25.40.6Am

21CC

.gnisiR0.42.44.4V

tratStfoS

tnerruCtratStfoSI

V0=5.80.015.11Au

lortnoCelbanE

dlohserhTwoLcigoLV

dlohserhThgiHcigoLV

reifilpmArorrE

5.4--5.5V

--9.0--V

----4.0V

8.0----V

niaGCDpooLnepOOAngiseDybdeetnarauG0708--Bd

tcudorPhtdiwdnaB-niaGWBGC

etaRwelSRSngiseDybdeetnarauG36--su/V

ecnatcudnoc-snarTMGR

&ecruoS(tnerruCmumixaM

)kniS

Rev. F00, File Name: uP6212-DS-F0000

DAOL

PMOC

.Fp5=03----zHM

k02= Ω 00210061--V/Au

V6.1=003063--Au

10uPI Semiconductor Corp., http://www.upi-semi.com

Page 11

uP6212

Electrical Characteristics

retemaraPlobmySsnoitidnoCtseTniMpyTxaMtinU

rotallicsO

ycneuqerFgnihctiwSf

CSO

k33= Ω noitarepOesahP-3.072003033zHk

k42= Ω noitarepOesahP-2.072003033zHk

egnaRycneuqerFelbatsujdA 05--0001zHk

edutilpmApmaR --4--V

noitarepOesahP-2580959

ytuDmumixaM

noitarepOesahP-3287829

egatloVniPTRV

59.0150.1V

egatloVecnerefeR

egatloVecnerefeRlanretnI 97.008.018.0V

V-

ycaruccAegatloVtuptuOV

dlohserhTnoitceleSecnerefeR

leveL

egatloVecnerefeRlanretxE

egnaR

NIFER

egatloVSFO

NIFER

SFO

NIFER

k01= Ω V.5CCVot

k01= Ω .DNGot73.004.034.0

.V2.1=01---01Vm

egatloVecnerefeRlanetnItceleS0.4--

V-

5CC

SFO

4.0--

5.16.17.1

5CCV

5CC

esneStnerruC

tnerruCgnicruoSmumixaM 001----Au

egatloVtesffOtupnI 3---3 Vm

XAMI

ycaruccArorriMtnerruCXAMI

ycaruccArorriMtnerruCpoorD

GVA

XAMI

GVA

POORD

GVA

POORD

GVA

noitarepoesahpeerhtrof072003033%

noitarepoesahpowtrof081002022%

noitarepoesahpeerhtrof072003033%

noitarepoesahpowtrof081002022%

edoMgnivaSrewoP

tnerruCgnicuoS2SP/1SPI

XSP

1SP

k74= Ω 90111Au

2SP

)BT(tsooBtneisnarT

tnerruCgnikniSBTI

90111Au

Rev. F00, File Name: uP6212-DS-F0000

11uPI Semiconductor Corp., http://www.upi-semi.com

Page 12

uP6212

Electrical Characteristics

retemaraPlobmySsnoitidnoCtseTniMpyTxaMtinU

noitcetorP

dlohserhTnoitcetorPnerruClatoTV

noitcetorPegatloVrevOBFV

noitcetorPegatloVrednUBFV

XAMI

V-

PAE

V-

PAE

noitcetorPerutarepmeTrevO

dlohserhT

noitcetorPerutarepmeTrevO

siseretsyH

1.12.13.1V

021061002Vm

004-003-002-Vm

--061--

--02--

ecneuqeSrewoP

ytilibapaCgnikniSKOPV

KOP

.Am4=--50.02.0V

Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device.

These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability.

Note 2. Devices are ESD sensitive. Handling precaution recommended.

Note 3. θJA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of

JEDEC 51-3 thermal measurement standard.

Note 4. The device is not guaranteed to function outside its operating conditions.

Rev. F00, File Name: uP6212-DS-F0000

12uPI Semiconductor Corp., http://www.upi-semi.com

Page 13

uP6212

Typical Operation Characteristics

(1V/Div)

Power On Waveforms

EN (1V/Div)

(1V/Div)

Time (4ms/Div)

Turn On Waveforms

OUT

(500mV/Div)

OUT

(500mV/Div)

Power Off Waveforms

(1V/Div)

OUT

(500mV/Div)

Time (400ms/Div)

Turn Off Waveforms

OUT

(500mV/Div)

(1V/Div)

POK

(2V/Div)

PWM1 (5V/Div)

Time (4ms/Div)

Switching Frequency vs. R

1000

Switching Frequency (kHz)

100

10 100

RRT (kΩ)

POK

(2V/Div)

PWM1 (5V/Div)

Time (100ms/Div)

Efficiency (%)

0204060

Auto Phase Efficiency

— 1 Phase

— 2 Phase

— 3 Phase

Auto Phase

Output Current (A)

Rev. F00, File Name: uP6212-DS-F0000

13uPI Semiconductor Corp., http://www.upi-semi.com

Page 14

pplication Information

This page is intentionally left blank and will be update later.

uP6212

14uPI Semiconductor Corp., http://www.upi-semi.com

Rev. F00, File Name: uP6212-DS-F0000

Page 15

VQFN4x4-24L Package

uP6212

Package Information

0.80 - 1.00

2.30 - 2.50

3.90 - 4.10

2.30 - 2.50

0.35 - 0.45

0.18 - 0.30

Bottom View - Exposed Pad

Pin 1 mark

2.35 - 2.45

3.05 - 3.15

4.45- 4.55

0.0 - 0.05

0.20 BSC

0.20 - 0.30

Recommended Solder Pad Pitch and Dimensions

Note

1.Package Outline Unit Description: BSC: Basic. Represents theoretical exact dimension or dimension target MIN: Minimum dimension specified. MAX: Maximum dimension specified. REF: Reference. Represents dimension for reference use only. This value is not a device specification. TYP. Typical. Provided as a general value. This value is not a device specification.

2.Dimensions in Millimeters.

3.Drawing not to scale.

4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shell not exceed 0.15mm.

Rev. F00, File Name: uP6212-DS-F0000

15uPI Semiconductor Corp., http://www.upi-semi.com