Page 1
Preliminary
A
uP6210
Compact Dual-Phase
Synchronous-Rectified Buck Controller
General Description
The uP6210 is a compact dual-phase synchronous-rectified
Buck controller specifically designed to deliver high quality
output voltage for high power applications. This part is
capable of delivering up to 60A output current thanks to its
embedded bootstrapped drivers that support 12V + 12V
driving capability. The uP6210 features configurable gate
driving voltage for maximum efficiency and optimal
performance. The built-in bootstrap diode simplifies the
circuit design and reduces external part count and PCB
space.
The output voltage is precisely regulated to the reference
input that is dynamically adjustable by external voltage
divider. The uP6210 adopts DCR current sensing technique
for over current protection and droop control. The adjustable
current balance is achieved by R
current sensing
DS(ON)
technique.
This part features comprehensive protection functions
including over current protection, input/output under voltage
protection, over voltage protection and over temperature
protection.
Other features include adjustable soft start, adjustable
operation frequency, and quick response to step load
transient. With aforementioned functions, this part provides
customers a compact, high efficiency, well-protected and
cost-effective solutions. This part comes to VQFN4x4-24L
package.
Ordering Information
Features
Operate with Single Supply Voltage
±±
±2.0% Over Line Voltage and Temperature
±±
Simple Single-Loop Voltage-Mode Control
12V Bootstrapped Drivers with Internal
Bootstrap Diode
Adjustable Over Current Protection by DCR
Current Sensing
Adjustable Current Balancing by R
DS(ON)
Current
Sensing
Adjustable Operation Frequency form 50kHz to
1MHz Per Phase
External Compensation
Dynamic Output Voltage Adjustment
Adjustable Soft Start
VQFN4x4-24L Package
RoHS Compliant and 100% Lead (Pb)-Free
pplications
Middle-High End GPU Core Power
High End Desktop PC Memory Core Power
Low Output Voltage, High Power Density DC-DC
Converters
Voltage Regulator Modules
Pin Configuration
rebmuNredrOepyTegakcaPkrameR
GAQA0126PuL42-4x4NFQV
Note: uPI products are compatible with the current IPC/
JEDEC J-STD-020 and RoHS requirements. They are 100%
matte tin (Sn) plating and suitable for use in SnPb or Pbfree soldering processes.
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6210-DS-P0000
LG2
SW2
HG2
BOOT2
VID
RSET
VCC
19
20
21
22
23
24
REFIN
LG1
PVCC
17 16 1518
GND
VREF
RT/EN
VQFN4x4-24L
SW1
4321
IOFS
14
5
HG1
COMP
BOOT1
13
12
PSI
CSP
11
10
CSN
SS
9
EAP
8
7
FBRTN
6
FB
1
Page 2
Preliminary
VCC
uP6210
Typical Application Circuit
V
IN
PH2
PH1
V
OUT
FBRTN
PVCC
CSP
CSN
PSI
IOFS
VREF
REFIN
RSET
SS
EAP
VID
uP6210
BOOT1
HG1
SW1
LG1
BOOT2
HG2
SW2
LG2
FBRTN
Q
1
V
OUT
RT/EN
GND
FB
COMP
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6210-DS-P0000
2
Page 3
.oNemaNniPnoitcnuFniP
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Preliminary
uP6210
Functional Pin Descriptio
1NIFER
2FERV
3NE/TR
4SFOI
5PMOC
6BF
7NTRBF
8PAE
9SS
01NSC
11PSC
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uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6210-DS-P0000
3
Page 4
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Preliminary
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uP6210
Functional Pin Descriptio
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222TOOB
32DIV
42TESR
DNG
VREF
RSET
VID
FBRTN
REFIN
SS
EAP
FB
COMP
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Functional Block Diagram
Reference
Voltage
Amplifier
Error
POR
VCC
PWM1
IOFS
Internal
Regulator
Gate
Control
Logic
Current
Balance
PVCC
BOOT1
HG1
SW1
LG1
BOOT2
HG2
CSN
CSP
PSI
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6210-DS-P0000
Power Saving
Setting
PWM2
Oscillator
RT/EN GND
Gate
Control
Logic
SW2
LG2
4
Page 5
Preliminary
uP6210
Functional Description
The uP6210 is a compact dual-phase synchronous-rectified
Buck controller specifically designed to deliver high quality
output voltage for high power applications. This part is
capable of delivering up to 60A output current thanks to its
embedded bootstrapped drivers that support 12V + 12V
driving capability. The uP6210 features configurable gate
driving voltage for maximum efficiency and optimal
performance. The built-in bootstrap diode simplifies the
circuit design and reduces external part count and PCB
space.
The output voltage is precisely regulated to the reference
input that is dynamically adjustable by external voltage
divider. The uP6210 adopts DCR current sensing technique
for over current protection and droop control. The adjustable
current balance is achieved by R
current sensing
DS(ON)
technique.
This part features comprehensive protection functions
including over current protection, input/output under voltage
protection, over voltage protection and over temperature
protection.
Other features include adjustable soft start, adjustable
operation frequency, and quick response to step load
transient. With aforementioned functions, this part provides
customers a compact, high efficiency, well-protected and
cost-effective solutions. This part comes to VQFN4x4-24L
package.
Power On Reset and Initialization
The uP6210 works with a single supply voltage at VCC
pin. The VCC voltage is continuously monitored for power
on reset (POR) to ensure the supply voltage is high enough
for normal operation of the device. The POR threshold level
is typically 9V at VCC rising.
9V LDO for Gate Drivers
Figure 1 shows the relationship between oscillation
frequency and RRT.
1000
100
Switching Frequency (kHz)
10
10 100 1000
RRT (kohm)
Figure 1. Switching Frequency vs. RRT.
When released, the RT/EN pin voltage is regulated at 1V.
Pulling the RT/EN pin to ground shuts down the uP6210.
Voltage Control Loop
Figure 2 shows the simplified voltage control loop of uP6210.
VREF is a reference voltage output with 1% accuracy and
up to 1mA sourcing capability. RSET is an open drain output
that is controlled by VID pin. RSET is pulled to FBRTN
when VID = 1 and is set high impedance when VID = 0.
Therefore, the reference input voltage at REFIN pin is
calculated as:
VV
REFREFIN
VV
REFREFIN
2R
×=
×=
2R1R
+
3R//2R
+
)3R//2R(1R
for VID = 0
for VID = 1
The uP6210 provides flexible gate driving voltage for
maximum efficiency and optimal performance. A linear
regulator provides 9V voltage at PVCC pin for gate drives.
9V driving voltage reduces the power dissipation at uP6210
to an acceptable level at large gate capacitance and high
switching frequency applications. Bootstrap diodes are
embedded to facilitates PCB design and reduce the total
BOM cost. No external Schottky diode is required.
Chip Enable Oscillation Frequency Programming
A resistor RRT connected to RT pin programs the oscillation
frequency as:
=
10000
RT
)k(R
Ω
(kHz)
f
OSC
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6210-DS-P0000
Users can control VID pin to get two reference voltage level.
The current-limited buffer receives input at the VREFIN pin
and output a voltage source at SS pin. The output capability
of the buffer is limited to 20uA during soft start and 200uA
after soft start end. A capacitor CSS connected from SS to
FBRTN sets the voltage slew rate.
SS
SS
C
SSSS
SSSS
SS
==
uA20
C
SS
==
uA200
during soft start.
after soft startend.
dV
dV
dt
dt
C
I
C
I
These slew rate are used to control the output voltage slew
at soft start and V
jumping respectively.
REFIN
5
Page 6
Preliminary
uP6210
Functional Description
uP6210
Reference
Voltage
RT/EN
VID
REFIN
R2
VREF
R1
REFIN
R3
RSET
VID
FBRTN
V
OUT
SS
Current Limited
I
Buffer
Error
Amplifier
DRP
R
DRP
EAP
FB
SS = EAP
V
OUT
Figure 3. Soft Start Cycle, R
DRP
= 0Ω
As mentioned in the above section, slew rate of voltage
transition at SS and output voltage during soft start and
V
jumping is controlled by the capacitor connected to
REFIN
the SS pin. This reduces inrush current to charge/discharge
the large output capacitors during soft start and VID changing.
COMP
and prevents OCP, OVP/UVP false trigger.
Figure 2. Voltage Control Loop
The FB voltage is tightly regulated to the positive input of
the error amplifier, EAP. The output current is sensed and
mirrored to the EAP pin, resulting in a voltage droop
between SS and EAP.
IRVV ×−=
DRPDRPSSEAP
where I
is a current signal proportional to output current.
DRP
Consequently, at steady state, the output voltage can be
expressed as:
VV ×−
VV ×−
2R
×=
×=
2R1R
+
3R//2R
+
IR
DRPDRPREFOUT
)3R//2R(1R
for VID = 0
IR
for VID = 1
DRPDRPREFOUT
Soft Start
The uP6210 initiates its soft start cycle when the RT/EN
pin released from ground once the the POR is granted as
shown in Figure 3.
The SS buffer sinking/sourcing capability is limited to 20uA
during soft start and 200uA after soft start end. Therefore,
the slew rate of voltage ramping up/down at SS, EAP and
FB pin during soft start or VID changing is calculated as:
dV
dV
dt
dt
dV
dt
dV
dt
dV
dV
dt
dt
FBEAPSS
FBEAPSS
uA20
===
C
SS
uA200
===
C
SS
during soft start.
after soft start.
The uP6210 features pre-bias start-up capability. If the output
voltage is pre-biased with a voltage, say V
BIAS
, that
accordingly makes VFB higher than reference voltage
ramping V
. The error amplifier keeps V
EAP
lower than
COMP
the valley of the sawtooth waveform and makes PWM
comparators output low until the ramping V
catches up
EAP
the feedback voltage. The uP6210 keeps both upper and
lower MOSFETs off until the first pulse takes place.
Output Current Sensing
Figure 4 illustrates the output current sensing block of the
uP6210. The voltage VCS across the current sensing
capacitor CCS can be expressed as:
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6210-DS-P0000
= I
VCS
x RDC / 2
OUT
if the following condition is true.
6
Page 7
Preliminary
uP6210
Functional Description
2 x L / RDC = R
CSP
x C
CS
where L is the output inductor of the buck converter, RDC is
the parasitic resistance of the inductor, R
and CCS are
CSP
the external RC network for current sensing.
The GM amplifier will source a current I
to the CSN pin to
CSN
let its inputs virtually short circuit.
I
x R
CSN
= V
CS
can be expressed
CSN
CSN
Therefore the output current signal I
as:
RI
×
I
=
CSN
The output current signal I
DCOUT
R2
×
CSN
is used as droop tuning,
CSN
automatic phase reductin, and output over current protection.
Please see the related section for details.
SW1
SW2
R
CSP
uP6210
R
C
CSP
R
GM
CSP
CS
CSN
CSN
Amplifer
I
CSN
L
L
R
DC
V
OUT
R
DC
Figure 4. Output Current Sensing of uP6210.
The sourcing capability of the GM amplifier is 100uA. It is
recommended to scale I
= 30uA at rated output current
AVG
and set the OCP current as twice the rated output current.
Take a 60A converter for example. Assume RDC = 2mΩ,
select the sense resistor according to
Ω×
= k2
R
CSN
m2A60
×
uA302
Ω=
RT/EN or VCC POR.
Figure 5, and Figure 6 illustrate the OCP behaviors during
soft start and after soft start end respectively.
Current Balance
The uP6210 extracts phase currents for current balance by
parasitic on-resistance of the lower switches when turned
on as shown in Figure 5.
IOFS
I
SWx
Figure 5. R
Sample
& Hold
offset
voltage
uP6210
Current Sensing Scheme
DS(ON)
CS1
Current
I
Balance
CS2
The GM amplifier senses the voltage drop across the lower
switch and converts it into current signal each time it turns
on. The sampled and held current is expressed as:
3
where I
−
)ON(DSLXCSX
is the phase X current in Ampere, R
LX
uA6.610RII
+××=
is the on-
DS(ON)
resistance of low side MOSFET in Ω, 6.6uA is a constant
to compensate the offset voltage of the current sensing
circuit.
The uP6210 fine tunes the duty cycle of each channel for
current balance according to the sensed inductor current
signals as shown in Figure 6. If the current of channel 1 is
smaller than the current of channel 2, the uP6210 increases
the duty cycle of the corresponding phase to increase its
phase current accordingly, vice verse.
COMPRAMP1
PWM1
Over Current Protection
The sensed current signals are monitored for over current
protection. If I
is higher than 60uA, the over current
CSN
protection OCP is activated. Take the above case for
example, the OCP level is calculated as:
I
OCP
=
Ω××
m2
Ω
A120
=
k2uA602
The OCP is of latch-off type and can be reset by toggling
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6210-DS-P0000
RAMP2
I
CS2
I
CS1
PWM2
Figure 6. Current Balance Scheme of uP6210.
7
Page 8
Offset Current Tuning
Preliminary
uP6210
Functional Description
The uP6210 features an IOFS pin for tuning the offset current
between phase. The IOFS pin voltage is nominal 0.5V when
connecting a resistor to GND and 1.5V when connecting a
resistor to VREF. Connecting a resistor from IOFS pin to
GND generate a current source as:
R/V5.0I =
OFSOFS
This current is add to phase 1 current signal I
for current
CS1
balance. Consequently, phase 2 will share more percentage
of output current.
Connecting a resistor from IOFS pin to VREF generates a
current source as:
R/)V5.1V2(I −=
OFSOFS
This current is add to phase 2 current signal I
for current
CS2
balance. Consequently, phase 1 will share more percentage
of output current.
Automatic Phase Reduction
The uP6210 features automatic phase reduction that turns
off phase 2 at light load condtion and reduces both switching
and conduction losses. The automatic phase reduction
maintains high power conversion efficiency over the output
current range.
The output current is sensed and mirrored to PSI pin as:
RI
×
II
==
CSNPSI
The I
creates a voltage V
PSI
IRV
The uP6210 operates in dual phase if V
0.6V and in single phase if V
DCOUT
R2
×
CSN
as:
PSI
RDCRI
××
=×=
PSIPSIPSI
R2
×
PSIOUT
CSN
is higher than
is lower than 0.4V. There is
PSI
PSI
a 200mV hystersis at the phase change threshold. There
is a 1ms delay when entering single phase operation and
no time delay when entering dual phase operation. When
operating single phase, both HG2 and LG2 are turned off.
Take the about case for example, with R
= 80kΩ, the
PSI
threshold level of output current for entering single phase
operation is calculated as:
RDCRI
××
CSN
k22V4.0
k80m2
Ω×Ω
PSIOUT
Ω××
I
OUT
OUT
V4.0
=
R2
×
=
A10I
=
The threshold level of output current for entering dual phase
operation is calculated as:
RDCRI
××
CSN
k22V6.0
k80m2
Ω×Ω
PSIOUT
Ω××
I
OUT
OUT
V6.0
=
R2
×
=
A15I
=
Note that when operated in single phase, the rated current
is reduced to 80 percents of normal level. Continuous
demanding high current may damage the converter.
Connect PSI pin to VREF to disable the automatic phase
reduction function. Since the VREF has no sinking
capability, make sure the external loading is higher than
100uA when connecting PSI pin to VREF. Otherwise, VREF
may loss its regulation.
Over Voltage and Under Voltage Protection
The FB voltage is continuously monitored for over voltage
and under voltage protection. The uP6210 asserts over
voltage protection if VFB > VSS + 300mV and turns on the
lower MOSFETs and shuts down the converter. The uP6210
asserts under voltage protection if VFB < VSS - 300mV and
shuts down the converter. The UVP function is disabled
during soft start.
Both UVP and OVP are latch-off type and can be reset
only by toggling the RT/EN pin ro by VCC power on reset.
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6210-DS-P0000
8
Page 9
Preliminary
A
g
n
uP6210
bsolute Maximum Ratin
Supply Input Voltage, VCC (Note 1) --------------------------------------------------------------------------------------------- -0.3V to +15V
SW to GND
DC ------------------------------------------------------------------------------------------------------------------------------------- -0.3V to 15V
< 200ns ---------------------------------------------------------------------------------------------------------------------------- -5V to 30V
BOOT to SW -------------------------------------------------------------------------------------------------------------------------------------- 15V
BOOT to GND
DC ------------------------------------------------------------------------------------------------------------------------- -0.3V to PHASE +15V
< 200ns -------------------------------------------------------------------------------------------------------------------------- -0.3V to 42V
Input, Output or I/O Voltage ---------------------------------------------------------------------------------------------------------- -0.3V to +6V
Storage Temperature Range ------------------------------------------------------------------------------------------------------------- -65OC to +150OC
Junction Temperature ------------------------------------------------------------------------------------------------------------------------------------ 150OC
Lead Temperature (Soldering, 10 sec) ------------------------------------------------------------------------------------------------------------ 260OC
ESD Rating (Note 2)
HBM (Human Body Mode) --------------------------------------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ----------------------------------------------------------------------------------------------------------------------------- 200V
Thermal Informatio
Package Thermal Resistance (Note 3)
VQFN4x4-24L θJA ------------------------------------------------------------------------------------------------------------------------- 40°C/W
Power Dissipation, PD @ TA = 25°C
VQFN4x4-24L ---------------------------------------------------------------------------------------------------------------------------------------- 2.5W
Recommended Operation Conditions
Operating Junction Temperature Range (Note 4) ------------------------------------------------------------------------ -40°C to +125°C
Operating Ambient Temperature Range -------------------------------------------------------------------------------------- -40°C to +85°C
Supply Input Voltage, V
-------------------------------------------------------------------------------------------------------- 10.8V to 13.2V
CC
Electrical Characteristics
(VCC = 12V, TA = 25OC, unless otherwise specified)
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ycaruccAycneuqerFgnihctiwS ∆f
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6210-DS-P0000
R
CSO
f
CSO
k33= Ω 072003033zHk
NE/TR
CSO
zHk005~zHk002=51---51%
9
Page 10
Preliminary
uP6210
Electrical Characteristics
retemaraPlobmySsnoitidnoCtseTniMpyTxaMstinU
tratStfoS
tnerruCtratStfoSI
tnerruCylppuSI
SS
CC
.tratstfosgniruD--02--
Au
.dnetratstfosretfA--002--
rotallicsO
elcyCytuDmumixaM --58--%
elcyCytuDmumixaM --0--%
edutilpmApmaR ∆V
V
CSO
CC
.V21=--5.3--V
edoMgnivaSrewoP
lauDgniretnErofegatloVdlohserhT
esahP
gniretnErofegatloVsiseretsyH
esahPelgniS
V
∆V
V
ISP
V
ISP
.gnisir55.06.056.0V
ISP
.gnillaf--002--Vm
ISP
egatloVecnerefeR
ycaruccAegatloVecnerefeRV
noitalugeRdaoLegatloVecnerefeR ∆V
ycaruccAegatloVtuptuOV
I
FER
FER
I
FER
FER
V|
BF
R
PRD
Au001=89.100.220.2V
Am2~0=5---5Vm
V-
0= Ω V,
V,|
BF
CC
NIFER
NIFER
,daoLoN,V21=
.V6.1~V8.0=
----5Vm
reifilpmArorrE
niaGCDpooLnepOOA.ngisedybdeetnarauG0708--Bd
tcudorPhtdiwdnaB-niaGWBGC
DAOL
.ngisedybdeetnarauG,Fp5=02----zHM
etaRwelSRS.ngisedybdeetnarauG5102--su/V
)ecruoS&kniS(tnerruCmumixaMI
V
PMOC
V6.1=5.10.2--Am
PMOC
esneStnerruClatoT
tnerruCgnicruoSmumixaMI
XAM_NSC
001----Au
tesffOreifilpmAMG 1-01Vm
dlohserhTnoitcetorPtnerruCrevO
I
leveL
ycaruccApoorDI
ycaruccAISPI
PCO_NSC
I/
PRD
NSC
ISPI/NSC
--06--Au
09001011%
09001011%
esneStnerruCesahP
ecnatcudnoc-snarT --0.1--Sm
V
egatloVSFOI
SFO
k001 Ω FERVotSFOImorf--5.1--
k001 Ω DNGotSFOImorf--5.0--
V
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6210-DS-P0000
10
Page 11
Preliminary
uP6210
Electrical Characteristics
retemaraPlobmySsnoitidnoCtseTniMpyTxaMstinU
tupnIlortnoCDIV
leveLdlohserhThgiHcigoLV
leveLdlohserhTwoLcigoLV
TEFSOMTESRfoecnartsiseRnOR
niPTESRfoegakaeLI
LI
LI
TESR
V
TESR
hgiH=DIV--02-- Ω
TESER
V0=DIV,V2=----1.0Au
2.1----V
----4.0V
revirDetaG
gnicruoSetaGreppUR
gnikniSetaGreppUR
ecruoSetaGrewoLR
kniSetaGrewoLR
emiTdaeDT
I
CRS_GH
GH
I
KNS_GH
GH
I
CRS_GL
GL
I
KNS_GL
GL
TD
gnicruosAm001=--24Ω
gniknisAm001=--5.13Ω
gnicruosAm001=--24Ω
gnikgnisAm001=--12Ω
--03--sn
noitcetorP
noitcetorPegatloVrevOV
noitcetorPegatloVrednUV
V-
BF
SS
V-
BF
SS
noitcetorPerutarepmeTrevO --051--
siseretsyHerutarepmeTrevO --02--
--003--Vm
--003---Vm
O
O
Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device.
These are for stress ratings. Functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. θJA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
Note 4. The device is not guaranteed to function outside its operating conditions.
C
C
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6210-DS-P0000
11
Page 12
Preliminary
Typical Operation Characteristics
uP6210
Power On Waveforms
PH1 (10V/Div)
RT/EN (1V/Div)
V
(1V/Div)
OUT
SS (1V/Div)
Turn On Waveforms
PH1 (10V/Div)
Time (2ms/Div)
VIN = 12V, I
OUT
= 40A
Power Off Waveforms
PH1 (10V/Div)
RT/EN (1V/Div)
V
(1V/Div)
OUT
SS (1V/Div)
Time (200us/Div)
VIN = 12V, I
OUT
= 40A
Output Voltage Load Regulation
PH1 (10V/Div)
RT/EN (1V/Div)
V
(1V/Div)
OUT
SS (1V/Div)
UG1 Falling Waveforms
UG1 ( 5V/Div)
PH1 (5V/Div)
Time (200us/Div)
VIN = 12V, I
OUT
= 40A
LG1 (5V/Div)
UG1 Rising Waveforms
LG1 (5V/Div)
Time (100us/Div)
VIN = 12V, I
OUT
= 40A
RT/EN (1V/Div)
V
(1V/Div)
OUT
SS (1V/Div)
UG1 ( 5V/Div)
PH1 (5V/Div)
Time (40ns/Div)
VIN = 12V, I
= 40A, 20MHz Bandwidth Limited
OUT
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6210-DS-P0000
VIN = 12V, I
Time (40ns/Div)
= 40A, 20MHz Bandwidth Limited
OUT
12
Page 13
Preliminary
Typical Operation Characteristics
uP6210
Over Voltage Protection
FB (1V/Div)
PH1 (10V/Div)
LG1 (10V/Div)
Time (2us/Div)
Turn On Waveforms
PSI (1V/Div)
11
10
Power Off Waveforms
(1V/Div)
V
OUT
PSI (1V/Div)
PH1 (10V/Div)
PH2 (10V/Div)
Time (20us/Div)
VCC9 Line Regulation
9
PH1 (10V/Div)
PH2 (10V/Div)
Time (2ms/Div)
VIN = 12V, I
= 0A to 40A
OUT
VREF Load Regulation
0.2
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
VREF Variation (%)
-0.2
-0.25
-0.3
0 5 10 15 20
Loading Current (mA)
8
7
VCC9 Voltage (V)
6
5
4
67891011121314
Input Voltage (V)
VREF Line Regulation
2.05
2.04
2.03
2.02
2.01
2
1.99
VREF Voltage (V)
1.98
1.97
1.96
1.95
6 7 8 9 10 11 12 13 14
Input Voltage (V)
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6210-DS-P0000
13
Page 14
Preliminary
Typical Operation Characteristics
uP6210
Frequency vs. RT
1000
Frequency (KHz)
100
110100
RT (kΩ)
VCC9 Voltage vs. Tempereture
9.33
9.32
9.31
9.3
9.29
VCC9 Voltage (V)
9.28
9.27
-50 -25 0 25 50 75 100 125
Junction Temperature (OC)
Efficiency vs. Output Current with Auto PSI
100
90
80
70
Efficiency (%)
60
50
40
1 Phase
Operation
0 10203040506070
2 Phase
Operation
Output Current (A)
VREF Voltage vs. Temperature
2.05
2.04
2.03
2.02
2.01
2
1.99
1.98
VREF Voltage (V)
1.97
1.96
1.95
-50-25 0 25 50 75100125
Junction Temperature (OC)
Switching Frequency vs. Tempereture
310
308
306
304
302
300
298
296
294
Switching Frequency (KHz)
292
290
-50 -25 0 25 50 75 100 125
Junction Temperature (OC)
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6210-DS-P0000
14
Page 15
A
FBRTN Configuration
Preliminary
uP6210
pplication Information
Since the reference voltage V
is measured with
REF
respective to FBRTN, connect circuits related to VREF,
REFIN, and SS pin to FBRTN locally with short traces as
shown in the Typical Application Circuit.
Total Current Sensing
In the real application, PCB trances are not ideal and have
certain parasitic resistances R
PCB1
and R
as shown in
PCB2
Figure 1. When these parasistic resistances are not
identical, the voltages at inductor terminals are not the
same, contributing meausrement error on total current
sensing. Two 1Ω resistors, connecting directly to inductor
terminals are recommended to elimiate the effects of
parasitic resistance.
A 0.1uF capacitor C
is also recommended to bypassing
BYP
noise when the uP6210 is far away from the output
inductors. Place the C
SW1
SW2
L
R
DC
R
PCB1
V
OUT
L
R
1ohm
R
PCB2
DC
physically near the IC.
BYP
R
CSP
R
CSP
CSP
C
1ohm
CS
CSN
R
CSN
C
BYP
uP6210
I
GM
Amplifer
CSN
Figure 1. Parasitic Resistance of PCB
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6210-DS-P0000
15
Page 16
Preliminary
uP6210
Package Information
0.80 - 1.00
2.30 - 2.75
3.90 - 4.10
3.90 - 4.10
2.30 - 2.75
0.35 - 0.45
0.18 - 0.30
Bottom View - Exposed Pad
Pin 1 mark
(Note 6)
2.65 - 2.75
3.10 - 3.20
4.50 - 4.70
0.0 - 0.05
0.20 BSC
0.20 - 0.30
Recommended Solder Pad Pitch and Dimensions
Note
1.Package Outline Unit Description:
BSC: Basic. Represents theoretical exact dimension or dimension target
MIN: Minimum dimension specified.
MAX: Maximum dimension specified.
REF: Reference. Represents dimension for reference use only. This value is not a device specification.
TYP. Typical. Provided as a general value. This value is not a device specification.
2.Dimensions in Millimeters.
3.Drawing not to scale.
4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shell not exceed 0.15mm.
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6210-DS-P0000
16
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