Datasheet up6203 Datasheets

uP6203

A

Compact Dual-Phase

Synchronous-Rectified Buck Controller

General Description

The uP6203 is a compact dual-phase synchronous-rectified
Buck controller specifically designed to deliver high quality
output voltage for high power applications. This part is
capable of delivering up to 60A output current owing to its
embedded bootstrapped drivers that support 12V + 12V
driving capability. The uP6203 features configurable gate
driving voltage for maximum efficiency and optimal
performance. The built-in bootstrap diode simplifies the
circuit design and reduces external part count and PCB
space.

The output voltage is precisely regulated to internal 0.6V
or external reference voltage from 0.4V to 3.3V. The uP6203
adopts lossless R

current sensing technique for

DS(ON)

channel current balance and over current protection.

A MODE pin programs single- or dual- phase operation
that makes the uP6203 ideally suitable for dual power input
applications such as PCIE interfaced graphic cards. When
programmed as automatic mode, the uP6203 operates in
single phase at light load condition and maintains high
efficiency over the output current range.

This part features comprehensive protection functions
including over current protection, input/output under voltage
protection, over voltage protection and over temperature
protection.

Other features include adjustable soft start, adjustable
operation phase, and quick response to step load transient.
With aforementioned functions, this part provides
customers a compact, high efficiency, well-protected and
cost-effective solutions. This part is available in spacing­saving VQFN4x4 -24L package.

Ordering Information

Features



 Operate with 4.5V ~13.2V Supply Voltage





 Support Single- and Two- Phase Operation





±±



±2.0% Over Line Voltage and Temperature



±±



 Simple Single-Loop Voltage-Mode Control





 12V Bootstrapped Drivers with Internal



Bootstrap Diode



 Lossless R





 Adjustable Operation Frequency form 50kHz to



Current Sensing

DS(ON)

1MHz Per Phase



 External Compensation





 Adjustable Over Current Protection





 Adjustable Soft Start





 VQFN4x4 -24L Package





 RoHS Compliant and 100% Lead (Pb)-Free



pplications



 Middle-High End GPU Core Power





 High End Desktop PC Memory Core Power





 Low Output Voltage, High Power Density DC-DC



Converters



 Voltage Regulator Modules



Pin Configuration

PHASE2

18

LGATE2

VCC121920

UGATE2

PGND

17 16 15

BOOT2

SS/EN

14 13

NC

NC

12

11 FB

rebmuNredrOepyTegakcaPkrameR

GAQA3026PuL42-4x4NFQV

Note: uPI products are compatible with the current IPC/
JEDEC J-STD-020 requirements. They are halogen-free,
RoHS compliant and 100% matte tin (Sn) plating that are
suitable for use in SnPb or Pb-free soldering processes.

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F02, File Name: uP6203-DS-F0200

VCC9

VCC5

LGATE1

PHASE1

21

22

23

24

NC

PGND

QFN4x4 – 24L

GND

UGATE1

4321

BOOT1

10

COMP

RT

9

8

IMAX

MODE

7

65

AGND

REFIN

1

5VCC

VCC9

VCC5

VCC12

BOOT1

uP6203

Typical Application Circuit

V

= 10.8~13.2V

IN

5VCC

REFIN

RT

IMAX

MODE

COMP

FB

VCC9

VCC5

uP6203

AGND

9V Driving Voltage

PGND

UGATE1

PHASE1SS/EN

LGATE1

BOOT2

UGATE2

PHASE2

LGATE2

VCC12

BOOT1

V

= 10.8~13.2V

IN

V

OUT

REFIN

RT

IMAX

MODE

COMP

FB

AGND

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F02, File Name: uP6203-DS-F0200

UGATE1

PHASE1SS/EN

LGATE1

uP6203

BOOT2

UGATE2

PHASE2

LGATE2

PGND

12V Driving Voltage

V

OUT

2

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uP6203

Functional Pin Descriptio

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uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F02, File Name: uP6203-DS-F0200

3

n

.oNemaNnoitcnuFniP

uP6203

Functional Pin Descriptio

0221CCV

129CCV

225CCV

321ETAGL

421ESAHP

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Functional Block Diagram

SS/EN

VCC5

VCC12

REFIN

FB

COMP

BOOT2

UGATE2

PHASE2

LGATE2

AGND

Reference

Selection

Soft Start

Gate

Control

Logic

Operation

Phase

Selection

V

REFX

PWM2

PWM

Comparator

S/H

Error

Amplifier

Current

Balance

Oscillator

POR

PWM1

PWM

Comparator

S/H

Gate

Control

Logic

9V LDO

VCC9

BOOT1

UGATE1

PHASE1

LGATE1

PGND

OCP

MODE

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F02, File Name: uP6203-DS-F0200

IMAXRT

4

uP6203

Functional Description

The uP6203 is a compact dual-phase synchronous-rectified
Buck controller specifically designed to deliver high quality
output voltage for high power applications. This part is
capable of delivering up to 60A output current thanks to its
embedded bootstrapped drivers that support 12V + 12V
driving capability. The built-in bootstrap diode simplifies the
circuit design and reduces external part count and PCB
space.

The output voltage is precisely regulated to internal 0.6V
reference voltage or external reference voltage from 0.4V
to 3.3V. The uP6203 adopts R

current sensing

DS(ON)

technique for channel current balance, and over current
protection.

This part features comprehensive protection functions
including over current protection, input/output under voltage
protection, over voltage protection and over temperature
protection.

Other features include internal soft start, adjustable
operation phase number and quick response to step load
transient. With aforementioned functions, this part provides
customers a compact, high efficiency, well-protected and
cost-effective solutions. This part is available in VQFN4x4

- 24L packages.

to be lower than 5V, external Schottky diode is highly
recommended to get highest gate driving voltage for high
side MOSFET.

V

= 10.8~13.2V

IN

VCC12

VCC9

Figure 1. 9V Drive Application

V

= 4.5~13.2V

IN

VCC12

VCC9

9V

LDO

9V

LDO

uP6203

Gate

Drivers

uP6203

Gate

Drivers

Internal 9V LDO Regulators

The uP6203 integrates a 9V LDO regulator for gate drivers
as shown in Figure 1. The 9V LDO receives input voltage
at VCC12 pin and outputs a regulated voltage at VCC9 pin
for the lower gate drivers and the bootstrap circuit for the
upper gate drivers, providing flexible gate driving voltage for
maximum efficiency and optimal performance. When driving
with 9V gate voltage, the converter reduces 25% power
dissipation in the drivers and maintains high efficiency
comparing to 12V driving voltage. This enables the uP6203
to drive MOSFETs with large input capacitors and provides
up to 60A output current without overheating the controller
itself.

When the VCC12 pin is left open, the VCC9 pin could
received well decoupled 4.5V~13.2V voltage for gate drivers
as shown in Figure 2. Since the uP6203 adopts R

DS(ON)

current sensing technique for current balance and over
current protection, always consider the R

DS(ON)

with the
lowest possible gate driving voltage. If the gate driving
voltage is expected to be lower than 7V, special
consideration should be paid to the threshold voltage of
the MOSFETs.

Bootstrap diodes are embedded to facilitates PCB design
and reduce the total BOM cost. No external Schottky diode
is required. However, if the VCC9 pin voltage is expected

Figure 2. Bypass the Internal 9V LDO Regulator.

The VCC9 pin should be locally bypassed by a minimum
1uF ceramic. Place the capacitor physically near the VCC9
pin.

The VCC5 pin receives a well-decoupled 4.5V~5.5V voltage
for internal control circuits. The VCC5 pin should be locally
bypassed by a minimum 1uF ceramic. Place the capacitor
physically near the VCC5 pin.

Power On Reset and Initialization

The uP6203 continuously monitors VCC9 and VCC5 pins
voltage for power on reset (POR) to ensure the supply
voltage is high enough for normal operation of the device.
The POR threshold level is typically 4.3V at VCC5 and
VCC9 rising.

Reference Voltage Selection

The uP6203 features selectable internal or external
reference voltage. The REFIN voltage level is checked at
POR to select the desired reference voltage. Internal 0.6V
reference voltage is selected if V

> 3.3V at POR,

REFIN

otherwise external reference voltage is selected. Once

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F02, File Name: uP6203-DS-F0200

5

uP6203

Functional Description

selected, the reference source is fixed and can only be
programmed at next POR.

The REFIN sources a 1uA current and pulls its voltage to
5V if this pin is left open when POR is granted. This selects
the internal 0.6V reference voltage. If the external reference
voltage is higher than 3.3V before POR, it may cause
uP6203 to select internal 0.6V reference voltage which
should be avoided.

Oscillation Frequency Programming

A resistor RRT connected to RT pin programs the oscillation
frequency as:

)k(30

Ω

92.0

OSC

(200f

×=

RT

)

)k(R

Ω

(kHz)

Figure 3 shows the relationship between oscillation
frequency and RRT.

1000

lower MOSFETs off until the first pulse takes place.

SS/EN

V

REF

REFIN

t

SS

Figure 4. Timing Diagram of Soft Start Interval.

The uP6203 claims soft start end when V
V

. The total soft start time with external reference

REFIN

catches up

REF

voltage is about

+

=

t

SS

REFINSS

uA10

)V8.0V(C

where 0.8V accounts for the delay time caused by the
MOSFET threshold voltage. When external reference voltage
changes, the slew rate of V

is also limited by the soft

REF

start mechanism. Consequently, this results in a smooth
output voltage transition during external reference voltage
change. The soft start also acts as the timer during OCP
and UVP hiccups as described in the later sections.

Switching Frequency (kHz)

100

1 10 100

(kohm)

R

RT

Figure 3. Switching Frequency vs. RRT.

Soft Start

Once POR releases, the uP6203 initiates its soft start cycle.
Figure 4 shows the softstart cycle with external reference
voltage. A 10uA current charges the soft start capacitor C

SS

and makes its voltage VSS linearly ramp up. The VSS clamps
reference voltage V

with a MOSFET threshold voltage

REF

gat at non-inverting input of the error amplifier. Accordingly,
the output voltage will softly ramp up and draw minimum
inrush current from the power bus.

The uP6203 features pre-bias start-up capability. If the output
voltage is pre-biased with a voltage, say V

BIAS

, that
accordingly makes VFB higher than reference voltage
ramping V

. The error amplifier keeps V

REF

lower than

COMP

the valley of the sawtooth waveform and makes PWM
comparators output low until the ramping V

catches up

REF

the feedback voltage. The uP6203 keeps both upper and

Channel Current Sensing

The uP6203 extracts phase currents for current balance
and over current protection by parasitic on-resistance of the
lower switches when turn on as shown in Figure 5.

Gate

Control

Logic

Current

Balance

PHASE1

Sample

Over

Current

Protection

Figure 5. R

& Hold

Current Sensing Scheme

DS(ON)

PHASE2

The GM amplifier senses the voltage drop across the lower
switch and converts it into current signal each time it turns
on. The sampled and held current is expressed as:

4

DS(ON)LXCSX

−

uA6.610RI3.3I

+×××=

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F02, File Name: uP6203-DS-F0200

6

uP6203

Functional Description

where I

is the phase X current in Ampere, R

LX

DS(ON)

is the on­resistance of low side MOSFET in Ω, 6.6uA is a constant
to compensate the offset of the current sensing circuit. Note

that the valley inductor current is sampled and held.

The sampled and held current is the averaged inductor current
minus half of inductor ripple current:

I2/1II ∆×−=

LXAVG_LXSH_LX

One half of the summation of the sampled and held current
signal (I
in a voltage V

CS1

+I

)/2 is injected to the IMAX pin, that results

CS2

across the resistor R

IMAX

connecting IMAX

IMAX

and AGND.

)II(

+

2CS1CS

V

=

IMAX

=

2

1L

SH_

Take ILX = 20A, ∆ILX = 4A, R
for example, V

V

=

IMAX

V27.1

=

R

×

IMAX

2

is calculated as:

IMAX

)ON(DSSH_2L

= 6mΩ , and R

DS(ON)

2

4

−

+××+×

4

−

+×Ω××−×

]uA2.1310R)II(3.3[

×

IMAX

]uA2.1310m62A)420(3.3[

R

IMAX

= 30kΩ

k30

Ω×

Over Current Protection

V

is compared with a 3.0V reference voltage for over

IMAX

current protection. If V

is higher than 3.0V, OCP is

IMAX

activated. Take above setting for example, the output current
for OCP is calculated as:

4

OUT

−

V0.3

=

=

OUT

2

A3.98I

+×Ω×−×

]uA2.1310m6A)4I(3.3[

k30

Ω×

The uP6203 features hiccup and shutdown mode OCP. If
OCP takes place after soft start end, the uP6203 turns off
both upper and lower MOSFETs and discharges the C

SS

with a constant current of 10uA. When VSS touches down

0.4V, the uP6203 initiates another soft start cycle. The
uP6203 shuts down after 3 times hiccups. If the OCP takes
place during soft start cycle, the uP6203 turns off both upper
and lower MOSFETs but keeps charging the CSS with a
constant current of 10uA until the soft start end. The
shutdown status can only be reset by POR function. Figure
6, and Figure 7 illustrate the OCP behaviors during soft
start and after soft start end respectively.

Note that on-resistance of a MOSFET is highly
dependent of gate voltage and temperature. Always
consider the highest temperature and lowest gate
voltage.

Note that the valley value of the inductor is sampled
and held just before the lower switch is to turn off.

The ripple current of the inductor should be considered
when calculating over current protection level.

SS (1V/Div)

Phase 2 (10V/Div)

V

(1V/Div)

OUT

Figure 6. OCP during Soft Start

SS (1V/Div)

Phase 2 (10V/Div)

V

(1V/Div)

OUT

Figure 7. OCP after Soft Start End.

Current Balance

The uP6203 fine tunes the duty cycle of each channel for
current balance according to the sensed inductor current
signals as shown in Figure 8. If the current of channel 1 is
smaller than the current of channel 2, the uP6203 increases
the duty cycle of the corresponding phase to increase its
phase current accordingly, vice verse.

RAMP2

I

CS2

I

CS1

COMPRAMP1

PWM1

PWM2

Figure 8. Current Balance Scheme of uP6203.

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F02, File Name: uP6203-DS-F0200

7

Automatic Phase of Operation Selection

The uP6203 features automatic phase of operation selection
according to load current. A current I
resistor R

connecting MODE pin and AGND.

MODE

R/V6.0I =

MODEMODE

flows through the

MODE

where 0.6V is the nominal voltage at MODE pin.

If the I
in single phase by turning off phase 2. If the I
than 3/5 of I

Take ∆ILX = 4A, R
example, I

is smaller than 2/5 of I

IMAX

, the uP6203 operates in dual phase.

MODE

DS(ON)

is calculated as 0.6V/30kΩ = 20uA. The

MODE

, the uP6203 operates

MODE

= 6mΩ , and R

IMAX

= 30kΩ for

MODE

is higher

threshold level of output current for entering single phase
operation is calculated as:

×

OUT

I2

=

5

A4.5I

=

OUTMODE

2

−

+×Ω×−×

]uA2.1310m6A)4I(3.3[

4

The threshold level of output current for entering dual phase
operation is calculated as:

×

OUT

I3

=

5

A8.10I

=

OUTMODE

2

−

+×Ω×−×

]uA6.610m6A)2I(3.3[

4

Note that when operated in single phase, the rated current
is reduced to 80 percents of normal level. Continuous
demanding high current may damage the converter.

Manual Phase of Operation Selection

The uP6203 supports manual selecting single- or dual­phase operation. If I
operates in forced single phase mode. If I

is higher than 150uA, the uP6203

MODE

is smaller

MODE

than 4uA, the uP6203 operates in forced dual phase mode.
This feature is important for PCIE interfaced graphic cards
where neither bus power nor external power is capable of
delivering full load current. Configure the converter as shown
in Figure 9. Power the phase 1 converter by PCIE bus
power and power the phase 2 converter by external power.
If the external power code is not plugged into the socket,
the External Power Detection, I

= 0.6V/3kohm >150uA

MODE

and the uP6203 operates in single phase mode. The uP6203
could provide limited current to GPU for required operation
when external power is not plugged.

uP6203

Functional Description

4

+×××

= 30kΩ for

IMAX

uP6203

Operation

Phase

Selection

]uA6.610RA)I(3.3[

R

]uA6.610m6A)2I(3.3[

k30

IMAX

Ω×

PCIE +12V

Phase 1

Converter

Ext. +12V

Phase 2

Converter

External Power Detection
Ext. Pwr Plugged = 0
Ext. Pwr Not Plugged = 1

VCC12

MODE

3kohm

Figure 9. Single/Two Phase Operation

Two-phase operation will make the phase 2 converter acts
like a boost converter if the external power is not available,
boosting the output voltage to the input voltage. The
relationship between input voltage and output voltage is
governed by conventional boost converter equation. Offset
of the current balance function may make the duty cycle of
phase 2 converter smaller than that of phase 1 converter.
This results in external power higher than 15V that may
damage the input capacitors and other devices. Figure 9
configuration turns off phase 2 converter when the external
power is not available, thus eliminates the possibility of
over voltage on input capacitors and other devices of the
phase 2 converter.

Note that when operated in single phase, the over current
protection level is reduced to 70 percents of normal level.
Continuous demanding high current may damage the
converter.

−

V0.37.0 ×

=×

Take ∆ILX = 4A, R

= 6mΩ , and R

DS(ON)

)ON(DSSH_1L

2

example, OCP level in single phase operation is calculated
as:

4

−

+×Ω×−×

OUT

V1.2

=

=

OUT

2

A2.63I

Note that when operating in forced single phase mode, the
uP6203 starts up with single phase operation. When
operating in automatic selection mode, the uP6203 starts
up with dual phase operation, no matter what level the load
current is. The mode selection is enabled only after the
uP6203 claims soft start end.

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F02, File Name: uP6203-DS-F0200

8

uP6203

A

g

n

bsolute Maximum Ratin

Supply Input Voltage, VCC12 (Note 1) ---------------------------------------------------------------------------------------- -0.3V to +15V

BOOTx to PHASEx ------------------------------------------------------------------------------------------------------------------------- -0.3V to +15V
PHASEx to GND

DC --------------------------------------------------------------------------------------------------------------------------------------- -0.7V to 15V
< 200ns ---------------------------------------------------------------------------------------------------------------------------------- -8V to 30V

BOOTx to GND

DC ------------------------------------------------------------------------------------------------------------------------ -0.3V to VCC12 + 15V
< 200ns -------------------------------------------------------------------------------------------------------------------------------- -0.3V to 42V

UGATEx to PHASEx

DC--------------------------------------------------------------------------------------------------------- -0.3V to (BOOTx - PHASEx +0.3V)
<200ns ------------------------------------------------------------------------------------------------- -5V to (BOOTx - PHASEx + 0.3V)

LGATEx to GND

DC ------------------------------------------------------------------------------------------------------------------ -0.3V to + (VCC12 + 0.3V)

<200ns ---------------------------------------------------------------------------------------------------------------- -5V to VCC12 + 0.3V

VCC9 ---------------------------------------------------------------------------------------------------------------------------- -0.3V to VCC12 + 0.3V
VCC5 ---------------------------------------------------------------------------------------------------------------------------------------------- -0.3V to 6V

Other Pins ------------------------------------------------------------------------------------------------------------------------- -0.3V to (VCC5 + 0.3V)
Storage Temperature Range ------------------------------------------------------------------------------------------------------------- -65OC to +150OC
Junction Temperature ------------------------------------------------------------------------------------------------------------------------------------ 150OC
Lead Temperature (Soldering, 10 sec) ------------------------------------------------------------------------------------------------------------ 260OC
ESD Rating (Note 2)

HBM (Human Body Mode) --------------------------------------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ----------------------------------------------------------------------------------------------------------------------------- 200V

Thermal Informatio

Package Thermal Resistance (Note 3)

VQFN4x4 - 24L θJA ----------------------------------------------------------------------------------------------------------------------- 40°C/W
VQFN4x4 - 24L θJC ------------------------------------------------------------------------------------------------------------------------- 6°C/W

Power Dissipation, PD @ TA = 25°C

VQFN4x4 - 24L -------------------------------------------------------------------------------------------------------------------------------------- 2.5W

Recommended Operation Conditions

Operating Junction Temperature Range (Note 4) ------------------------------------------------------------------------ -40°C to +125°C
Operating Ambient Temperature Range -------------------------------------------------------------------------------------- -40°C to +85°C
Supply Input Voltage, V

------------------------------------------------------------------------------------ 4.5V to 5.5V

CC5

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F02, File Name: uP6203-DS-F0200

9

(VCC12 = 12V, VCC9 = 9V, VCC5 = 5V, TA = 25OC, unless otherwise specified)

retemaraPlobmySsnoitidnoCtseTniMpyTxaMstinU

tupnIylppuS

uP6203

Electrical Characteristics

egatloVtupnIylppuSV

egatloVsaiVV

egatloVsaiBdetalugeRV

tnerruCylppuSI

tnerruCylppuStnecseiuQI

dlohserhTROP9CCVV

siseretsyHROP9CCVV

dlohserhTROP5CCVV

siseretsyHROP5CCVV

21CC

5CC

V

9CC

21CC

Q_9CC

HTR9CC

SYH9CC

HTR5CC

SYH9CC

21CC

V

BF

V

9CC

V

5CC

V,V21=

BF

ngiseDybdeetnarauG

gnihctiwSoN,V7.0=

ngiseDybdeetnarauG

.gnisiR8.33.42.4V

.gnisiR1.43.45.4V

rotallicsO

ycneuqerFgninnuReerFf

CSO

R

noitairaVycneuqerFR

k03= Ω 581012532zHk

TR

k03= Ω 01---01%

TR

egnaRycneuqerF 05--0001zHk

elcyCytuDmumixaM 287829%

elcyCytuDmuminiM --0--%

8.01--2.31V

5.4--5.5V

gnihctiwSoN,V7.0=8901V

gnihctiwS;nepOETAGLdnaETAGU

456 Am

5.125.2Am

--3.0--V

--51.0--V

edutilpmApmaR ∆V

CSO

ngiseDybdeetnarauG8.342.4V

egatloVecnerefeR

egatloVkcabdeeFlanimoNV

BF

V

21CC

V,V21=

V2.1=95.06.016.0V

PMOC

reifilpmArorrE

niaGCDpooLnepOOAngiseDybdeetnarauG0607--Bd

tcudorPhtdiwdnaB-niaGWBGngiseDybdeetnarauG601--zHM

etaRwelSRSngiseDybdeetnarauG36--su/V

ecnatcudnoc-snarTMGR

)kniS&ecruoS(tnerruCmumixaMI

PMOC

V

k02= Ω 00210041--V/Au

DAOL

V6.1=022082--Au

PMOC

esneStnerruC

(/ ∆V

∆I

ecnatcudnoc-snarTesneStnerruCMG

dlohserhTtnerruCrevOV

egatloVniPedoMV

noitarepOesahPelgniSdecroF

dlohserhT

XAMI

EDOM

I

EDOMI

XAMI

R@

XAMI

R

XAMII

k03= Ω

+ ∆V

1ESAHP

)

2ESAHP

006066027V/Au

k03= Ω 7.20.33.3V

85.006.026.0V

051----Au

P-P

noitarepOesahPlauDdecroF

I

dlohserhT

EDOMI

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F02, File Name: uP6203-DS-F0200

----4Au

10

uP6203

Electrical Characteristics

retemaraPlobmySsnoitidnoCtseTniMpyTxaMstinU

revirDetaG

gnicruoSetaGreppUR

gnikniSetaGreppUR

ecruoSetaGrewoLR

kniSetaGrewoLR

emiTdaeDT

TD

I

CRS_GH

GH

I

KNS_GH

GH

I

CRS_GL

GL

I

KNS_GL

GL

gnicruosAm001=--36Ω

gniknisAm001=--24Ω

gnicruosAm001=--5.25Ω

gnikgnisAm001=--3.16.2 Ω

--03--sn

tratStfoS

tnerruCtratStfoSI

leveLdlohserhTtratStfoS-eRV

V

SS

PUCCIH_SS

V0=70131Au

SS

--5.0--V

noitcetorP

noitcetorPerutarepmeTrevOngiseDybdeetnarauG041051061

siseretsyHerutarepmeTrevO --02--

O

O

Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device.

These are for stress ratings. Functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may remain possibility to affect device reliability.

Note 2. Devices are ESD sensitive. Handling precaution recommended.

Note 3. θJA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of

JEDEC 51-3 thermal measurement standard.

Note 4. The device is not guaranteed to function outside its operating conditions.

C

C

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F02, File Name: uP6203-DS-F0200

11

uP6203

Typical Operation Characteristics

VCC9 Line Regulation

10

9

8

7

6

VCC9 (V)

5

4

3

2

579111315

VCC12 (V)

Output Voltage Line Regulation (V

0.602

0.6015

(V)

0.601

FB

0.6005

CC12

= VIN)

Switching Frequency vs. R

1000

100

Switching Frequency (kHz)

10

1 10 100

R

(kΩ)

RT

Output Voltage Load Regulation

0.61

(V)

0.605

FB

RT

0.6

0.5995

0.599

Feedback Voltage V

0.5985

0.598

5 7 9 11 13 15

Input Voltage V

CC12

= V

(V)

IN

Power On

V

(2V/Div)

IN

PHASE (5V/Div)

VCC9 (2V/Div)

V

(500mV/Div)

OUT

0.6

0.595

Feedback Voltage V

0.59

0 102030405060

Output Current (A)

Turn On

REFIN

(500mV/Div)

SS/EN (1V/Div)

COMP (1V/Div)

V

(500mV/Div)

OUT

Time (500us/Div)

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F02, File Name: uP6203-DS-F0200

Time (250us/Div)

12

uP6203

Typical Operation Characteristics

Load Transient Response

V

OUT

50mV/Div

I

X1

10A/Div

I

X2

50mV/Div

10A/Div

Time (10us/Div)

R

= 30kΩ

MODE

OCP During Normal Operation

V

OUT

1.0V/Div

PHASE2

MODE Transition

V

OUT

50mV/Div

MODE
1V/Div

LGATE2

5V/Div

Time (10us/Div)

dual phase to single phase transition

MODE Transition

V

OUT

50mV/Div

IMAX

2V/Div

UGATE1

10V/Div

Time (250us/Div)

REFIN Step Change

REFIN

500mV/Div

V

OUT

500mV/Div

MODE
1V/Div

Time (5us/Div)

sigle phase to dual phase transition

ON/OFF from REFIN

REFIN

500mV/Div

V

OUT

500mV/Div

LGATE2

5V/Div

Time (1ms/Div)

REFIN 0.5V to 2.0V Step Change

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F02, File Name: uP6203-DS-F0200

Time (5ms/Div)

REFIN 0V to 2.0V Triangle Wave

13

uP6203

Typical Operation Characteristics

Switching Waveforms (V

Time (100ns/Div)

V

= 12V, 20MHz bandwidth limited

CC9

Steady State Operation

V

OUT

= 12V)

CC9

PHASE (5V/Div)

UGATE - PHASE

(5V/Div)

LGATE (5V/Div)

(20mV/Div)

Switching Waveforms (V

Time (100ns/Div)

V

= 9V, 20MHz bandwidth limited

CC9

= 9V)

CC9

PHASE (5V/Div)

UGATE - PHASE

(5V/Div)

LGATE (5V/Div)

Time (1us/Div)

VIN = 12V, V

PHASE1 (10V/Div)

PHASE2 (10V/Div

= 1.2V

OUT

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F02, File Name: uP6203-DS-F0200

14

A

pplication Information

This page is intentionally left blank and will be update later.

uP6203

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F02, File Name: uP6203-DS-F0200

15

uP6203

Package Information

0.80 - 1.00

0.0 - 0.05

2.30 - 2.75

3.90 - 4.10

3.90 - 4.10

Pin 1 m ark

(Note 6)

0.20 BSC

2.30 - 2.75

Bottom View - Exposed Pad

0.35 - 0.45

0.18 - 0.30

2.65 - 2.75

3.10 - 3.20

4.50 - 4.70

0.20 - 0.30

Recommended Solder Pad Pitch and Dimensions

Note

1.Package Outline Unit Description:

BSC: Basic. Represents theoretical exact dimension or dimension target
MIN: Minimum dimension specified.
MAX: Maximum dimension specified.
REF: Reference. Represents dimension for reference use only. This value is not a device specification.
TYP. Typical. Provided as a general value. This value is not a device specification.

2.Dimensions in Millimeters.

3.Drawing not to scale.

4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shell not exceed 0.15mm.

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F02, File Name: uP6203-DS-F0200

16