Datasheet up6204 Datasheets

Download

Page 1

Preliminary

uP6204

Compact Three-Phase

Synchronous-Rectified Buck Controller

General Description

The uP6204 is a compact three-pha se synchronous-rectified Buck controller specifically designed to deliver high quality output voltage for high power applications. This part is ca pable of delivering up to 90A output current thanks to its embedded bootstrapped drivers that support 12V + 12V driving capa bility . The built-in bootstra p diode simplifies the circuit design and reduces external part count and PCB space.

The output voltage is precisely regulated to the reference inputs R1/R2/R3/R4 that are selected by VID inputs VID1 and VID0. The reference voltage can also be progra mmed by I2C interface.

The uP6204 adopts DCR current sensing technique for over current protection and droop tuning. Current balance is achieved by sen sing the phase current through R lower MOSFET when it turns on.

This part features comprehensive protection functions including over current protection, input/output under voltage protection, over voltage protection and over te mperature protection.

DS(ON)

Features



 Operate with 10.8V ~13.2V Supply Voltage



 12V Bootstrapped Drivers with Internal



Bootstrap Diode



 Flexible Reference Voltage for Power Play





 External Reference Input R1/R2/R3/R4



Selected by VID1 and VID0



 Internal Reference Voltage Programmed by



I2C



 Simple Single-Loop Voltage-Mode Control



 DCR Current Sensing for Over Current



Protection and Droop Tuning



 R



 Adjustable Operation Frequency form 50kHz to



 External Compensation



 Adjustable Soft Start



 VQFN6x6-40L Package



 RoHS Compliant and 100% Lead (Pb)-Free



Current Sensing for Current Balance

DS(ON)

1MHz Per Phase

Other features include adjustable soft start, adjustable operation frequency, and quick response to step load transient. With af orementioned functions, this part provides customers a compact, high ef ficiency , well-prote cted a nd cost-effective solutions. This part comes to VQF N6x6-40L package.

pplications



 Middle-High End GPU Core Power



 High End Desktop PC Memory Core Power



 Low Output V oltage, High Power Density DC-DC



Converters



 Voltage Regulator Modules



Ordering Informatio n

rebmuNredrOepyTegakcaPkrameR

JAQA4026PuL04-6x6NFQV

Note: uPI products are compatible with the current IPC/ JEDEC J-ST D-020 and RoHS requirements. They are 100% matte tin (Sn) plating and suitable f or use in SnPb or Pbfree soldering processes.

PHASE3

LGATE3

VCC2

UGATE2

BOOT2 PHASE2 LGATE2

VCC1 LGATE1 PHASE1

31 32 33 34 35 36 37 38 39 40

BOOT3FBUGTE3

BOOT1

UGATE1

Pin Configuration

IMAX

TCS

5VCC 28

POK

SCL

MODE 26

GND

SDA

VRHOT/EN

EAP 24

VID1

SS 23

VID0

PSI

COMP

20 19 18 17 16 15 14 13 12 11

FBRTN CSP CSN ISEN3 ISEN2 ISEN1 R4 R1 R2

1uPI Semiconductor Corp., http://www.upi-semi.com

Rev. P01, File Name: uP6204-DS-P01000

Page 2

PHASE1 PHASE2 PHASE3

Preliminary

ISEN1 ISEN2 ISEN3 CSP

BOOT1

UGATE1 PHASE1

uP6204

T ypical Applic ation Circui t

IN1

OUT

NTC

OUT

5VCC

CSN

IMAX

FBRTN

COMP

EAP

PSI

R1 R2 R3 R4

uP6204

LGATE1

BOOT2

UGATE2 PHASE2

LGATE2

BOOT3

UGTE3

PHASE3

LGATE3

VCC2 VCC1

GND

IN2

IN1

Rev. P01, File Name: uP6204-DS-P0100

VRHOT/EN

MODE POK SCL SDA

5VCC

TCS

PTC

VID0 VID1

2uPI Semiconductor Corp., http://www.upi-semi.com

Page 3

.oNemaNniPnoitcnuFniP

Preliminary

uP6204

Function al Pin Descripti o

03/53/13/2/1TOOB

92/43/23/2/1ETAGU

3KOP

4LCS 5ADS

6NE/TOHRV

8/70/1DIV

9TR

/11/01

31/21

ylppuSpartstooB tcennoC.ylevitcepser3/2/1lennahcfosrevirdetagreppugn

iucricpartstoob

.CIehtraen

.noitacidnIKOrewoP sinipsihT.noitacidniKOrewoproftuptuon

.tupnIkcolClaireS .langiskcolc

.tupnIataDlaireS .langisatadsublairesfotuptuorotupnisinipsihT

iD .liatedrofsnoitcesdetalerehteeS

.ycneuqerfnoitarepo

/2R/3R

4R/1R

itaolfehtrof

Croticapacpartstoobeht

TOOB

rofseulavlacipyT.TEFSOMC

TOOB

serrocehtnehwenimretedotyrtiucricnoitcetorp

iard-neponasisihT

sublairesseviecernipsihT

uosrevirdetagllA.4026Puehtnwod

.yalPrewoProf0/1stupnIlatig

nnoC

.gnitteSycneuqerFnoitarepO ehttesotDNGdnanipsihtneewtebrotsiseratce

.yalPrewoProfstupnIegatloVecnerefeR esehtotCCV5morfsrediv

.3/2/1lennahCroftuptuOrevirDetaGreppU fosetagehtotsnipesehttcennoC

OgninraWerutarepmeThgiHdnaelbanEpihC stuhsDNGotnipsihtgnilluP

.tuptu

mrofotnip3/2/1ESAHPehtdnanip3/2/1TOOBneewteb

reppuehtnonrutotegrahcehtsedivorproticapacpartstoobehT.st

CtahterusnE.Fu1otFu74.0morfegnar

TOOB

.sruccotluafondnadnetratstfosretfaecnadepmihgihottes

.noitalugerfotuorotratstfosgnirudsiegatlovtuptuoehtnehwecnadepmi

idegatlovtcennoC

fsnoitcesdetalerehteeS.1DIVdna0DIVybdetcelesnehwsegatlovesehtot

decalpsi

uorht-toohsevitpadaehtybderotinomerasnipesehT.TEFSOMreppugnidnopserroc

.ffodenrutsahTEFSOMreppugnidnop

.sTEFSOMrewoldnareppuhtobffonrutotwoltupt

hgihottesdnanoitalugernihtiwsiegatlovtuptuoehtnehwV54.0tadepmalcsinipsi

detalugersiegatlovnipBFehT.yalprewoprofsegatlovecnereferehttesotdnuorgotsnip

.liatedro

61/51/413/2/1NESI

71NSC

81PSC

91NTRBF

02BF

12PMOC

22ISP

uCesahP ehtgnisnesybtnerrucesahpehtesnessnipesehT

ordegatlov

.sliated

rrucrotcudni

.egatloVkcabdeeF nipsihttcennoC.reifilpmarorreehtot

.tuptuOreifilpmArorrE gni

.srotarapmocMWPehtfotupni

esahP ehttesotDNGotnipsihtmorfrotsiseratcennoC

dlohserhtnoitcuderesahp

.noitcnuf

.3/2/1tupnIgnineStnerr

StnerruClatoTroftupnIevitageN latotehtsesnesnipNSChtiwgnolanipsihT

.gnisne

gnisneStnerruClatoTroftupnIevitisoP latotehtsesnesnipPSChtiwgnolanipsihT.

oitcesdetalerehteeS.tnerrucrotcudni

.gnisneSegatloVetomeRrofhtaPnruteR edondnuorgehtotyltceridnipsihttcennoC

.detalugerebotsiegatlovtuptuoehterehw

.gnitteSdlolhserhTnoitcudeR

ehtotsnipesehttcennoC.TEFSOMrewolevitcepserehtssorcap

rofsnoitcesdetalerehteeS.rotsiserlanretxenahguorhtedonESAHPgnidnopserroc

.sliatedrofsnoitcesdetalerehteeS.tne

.sliatedrofsn

tupnignitrevniehtsinipsihT

noitanibmocninipsihtesU.detalugerebotsiegatlovtuptuoehterehwedonehtotyltcer

.retrevnocehtfopoolkcabdeeflortnocegatlovehtetasnepmocotnipPMOCehthtiw

trevni-nonehtdna)AE(reifilpmarorreehtfotuptuoehtsisihT

etasnepmocotnipBFehthtiwnoitanibmocninipsihtesU

.retrevnocehtfopoolkcabdeeflortnoc-egatloveht

noitcuderesahpehtelbasidotV2.0nahtrewolnipsihtlluP.level

Rev. P01, File Name: uP6204-DS-P01000

3uPI Semiconductor Corp., http://www.upi-semi.com

Page 4

.oNemaNniPnoitcnuFniP

Preliminary

uP6204

Function al Pin Descripti o

32SS

42PAE

52XAMI

62EDOM

72SCT

82CCV5

13/6

3/043/2/1ESAHP

.tuptuOtratStfoS .lavretnitratstfosehttesotDNGotnipsihtmorfroticapacatcennoC

.reifilpmArorrEehtfotupnIevitisoP egatlovsihtkcartotdetalugersiegatlovBFehT

oitarepoetatsydaetsdnayalprewop,tratstfosgnirud

.epolspoordehtgninut

dnItnerruCtuptuO sihtneewtebrotsiseratcennoC

httesotDNGdnanip

.tne

rruc

.gnitteSnoitarepOforebmuNesahP .noitarepoesahpeerhtrofDNGotnipsihttcennoC

ahpylnO.noitarepo

.noitarepoesahpowtnehwdelbane

.gnisneSerutarepmeT

.tuptuOrotalugeRlanretnI dna

.3/2/1lennahCrofedoNhctiwS gnidnopserrocehtfoecruosehtotsnipesehttcennoC

toohsevitpadaehtybderotinom

.metsys

.gnitteStnerruCrevOdnanoitaci

psihtteL.noitarepoesahpowtrofCCV5otnipsihttcennoC

.Am02siytilibapactnerructuptuoehT.egasulanretxe

TEFSOMrewolgnidnopserrocehtfoniardehtdnaTEFSOMreppu

otnipSSotrotsiseratcennoC.n

oslanipsihT.noitcetorptnerrucrevorofleveldlohserhtreggirte

tuptuoehtotlanoitroporpyltceridsiegatlovstiecnisnoitacidnitnerructuptuorofsdnetni

esahpelgnisrofneponi era2&1esahpylnO.noitarepoesahpelgnisnehwdelbanesi1es

saiblanretnirofrotalugerraenilfoniptuptuoehtsisihT

oslaerasnipesehT.

reppuehtnehwenimretedotyrtiucricnoitcetorphguorhtsidnuorgdnanipsihtneewtebedoidykttohcSA.ffodenrutsahTEFSOMgnidnopserroc ylp

pusrewopaninommocsihcihwegatlovtneisnartevitagenecuderotdednemmocer

23/73/933/2/1ETAGL

332

831CCV

CCV

daPdesopxE

DNG14

orG yllaciartcelednaBCPotredlosllewebdluohsdapdesopxeehT

nnoc

ahCroftuptuOrevirDetaGrewoL gnidnopserrocehtotsnipesehttcennoC

.3revirDetaGroftupnIylppuS ehtdna,srevirdetagrewolroftnerrucsedivorpnipsihT

.3lennahcro2lennahc

ftupnIylppuS etagrewolroftnerrucsedivorpnipsihT

icpartstoobehtdna,srevird

.CIehtrofdnu

.3/2/1lenn

tinomerasnipesehT.TEFSOMrewolfoetag

.pihCehtdna2/1revirDetaGro

noitcetorphguorht-toohsevitpadaehtybdero

.ffodenrutsahTEFSOMrewolgnidnopserrocehtnehwenimretedotyrtiucric

fotupnirewopehtotnipsihttcennoC.3/2lennahcfosrevirdreppuroftiucricpartstoob

ehtfotiucriclortnocehtdna1lennahcfosrevirdreppuroftiucr

.1lennahcfofotupnirewopehtotnipsihttcennoC.4026Pu

.secartediwdnatrohshtiwenalp/dnalsidnuorgdetce

Rev. P01, File Name: uP6204-DS-P0100

4uPI Semiconductor Corp., http://www.upi-semi.com

Page 5

Preliminary

uP6204

Functional Block Diagram

SCL

SDA

FBRTN

COMP

EAP

IMAX

ISEN1 ISEN2 ISEN3

CSP

P*I

AVG

I2C

Manager

Unit

OTA

3.0V

EAP

+ 200mV

EAP

Reference & DAC

Generator

REF

Error

Amplifier

- 300mV

OCP

Current

Balance

VID1

OVP

VID0

POK

POR

UVP

5VCC

PWM1

PWM2

Internal

Regulator

Gate

Control

Logic

Gate

Control

Logic

VCC1

BOOT1

UGATE1

PHASE1

LGATE1

BOOT2

UGATE2

PHASE2

LGATE2

CSN

MODE

PSI

VRHOT/EN

TCS

AVG

0.3V

GM2

Oscillator

Selection

Chip Enable

28% of 5VCC

Phase

5VCC

PWM3

GND

POR

Gate

Control

Logic

VCC2 BOOT3

UGATE3

PHASE3

LGATE3

Rev. P01, File Name: uP6204-DS-P01000

5uPI Semiconductor Corp., http://www.upi-semi.com

Page 6

Preliminary

The uP6204 is a compact three-pha se synchronous-rectified Buck controller specifically designed to deliver high quality output voltage for high power applications. This part is cap able of delivering up to 90A output current thanks to its embedded bootstrapped drivers that support 12V + 12V driving capa bility . The built-in bootstra p diode simplifies the circuit design and reduces external part count and PCB space.

The output voltage is precisely regulated to the reference inputs R1/R2/R3/R4 that are selected by VID inputs VID1 and VID0. The reference voltage can also be progra mmed by I2C interface.

The uP6204 adopts DCR current sensing technique for over current protection and droop tuning. Current balance is achieved by sensing the phase current through R lower MOSFET when it turns on.

This part features comprehensive protection functions including over current protection, input/output under voltage protection, over voltage protection and over te mperature protection.

Other features include adjustable soft start, adjustable operation frequency, and quick response to step load transient. With af orementioned functions, this part provides customers a compact, high ef ficiency , well-prote cted and cost-effective solutions. This part comes to VQF N6x6-40L package.

DS(ON)

uP6204

Functional Description

IN1

OUT

LGATE1

PHASE1

UGATE1

BOOT1

PWM Controller

BOOT1

LGATE2

Figure 1. Simplified T wo-Pha se Buck Converter .

The uP6204 selects pha se number of operation according to the MODE pin and VCC2 status. The MODE pin is a tristate input. When the MODE pin is pulled low , the uP6204 operates in three phases. When the MODE pin is left floating, only pha se 1 is activated. When the MODE pin is pulled high, only phase 1 & 2 are activated. The uP6204 does not support real-time phase number of operation change. If a ny change of MODE state ha s been detected, the uP6204 will shut down the output voltage and re-softstart again.

T a ble 1. Phase Number of Operation T able.

EDOMROP2CCVnoitarepOforebmuNesahP

hgiHX 2/1esahP

IN2

PHASE2

UGATE2

Selecting Phase Number of Operation

The uP6204 supports single/two/three-phase operation that is important f or PCIE interfaced gra phic cards where neither bus power nor external power is ca pable of delivering full load current. Take a two-pha se buck converter a s shown in Figure 1 for exa mple. T wo-phase operation will make the phase 2 converter a ct like a boost converter if the external power is not available, boosting the output voltage V the input voltage V

. The relationship between input voltage

IN2

OUT

and output voltage is governed by conventional boost converter equation. Offset of the current balance function may make the duty cycle of phase 2 converter smaller than that of pha se 1 converter. This results in input voltage V

higher than 15V that may damage the in put ca pacitors

IN2

and other devices. Therefore, pha se 2 must be turned of f when input voltage VIN2 is not present to eliminate the possibility of over voltage on input capacitors and other devices of the pha se 2 converter.

gnitaolFX1esahP woLSEY3/2/1esahP woLONnwodtuhS

VCC1 powers the gate drives for phase 1/2 while VCC2 powers the gate drivers for phase 1. When MODE pin is pulled low, the uP6204 che cks the VCC2 POR status before soft start to ensure both bus and extern al power inputs are ready for providing current to output voltage. The VCC2 pin should be connected to V

(external power input). Figure

IN2

2 shows an imple mentation example where pha se 1/2 are powered by PECI bus and phase 3 is power by external cable.

Note that when operated in single/dual-phase, the rated current is reduced to fractions of normal level. Continuous demanding high current may da mage the converter.

Rev. P01, File Name: uP6204-DS-P0100

6uPI Semiconductor Corp., http://www.upi-semi.com

Page 7

PCIE +12V

Phase 1/2 Converter

Phase 3

Converter

VCC1

VCC2EXT +12V

Preliminary

uP6204

Operation

Phase

Selection

uP6204

Functional Description

VID Table as shown in Table 3. R1/R2/R3/R4 define four voltage levels through voltage

dividers for power on default setting.

LOW

5CC]4:1[R

where V

is the 5.0V reference output voltage at 5VCC

CC5

pin. Note that the VR2 is the default reference voltage

level for soft start.

×=

LOWHIGH

External Power Detection Ext. Pwr Plugged = 0 Ext. Pwr Not Plugged = 1

MODE

Figure 2. Single/Three Pha se Operation

Dynamic Voltage Management

The uP6204 provides a comprehensive dynamic voltage management scheme as shown in Figure 3. V reference voltage used for voltage control loop. V default connected V V

REFS

The V The V

or V

REFS REFP

by PMBUS, see the related section for details.

REFP

is a reference voltage progra mmed by PMBUS.

is a reference voltage programmed by the VID0

and ca n be progra mmed to either

REF/P

REF

is the

REF

and VID1 inputs. One of the voltage levels Level[1:4] is selected as V are defined a s V

as illustrated in ta ble 2. Initially , Level[1:4]

REFP

defined by R[1:4] pins. Level[1:4] ca n

R[1:4]

also be overwritten by PMBUS according the AMD GPU

T a ble 2. Parallel VID Selection.

]0:1[DIV

PFER

egatloV

4/3R/2R/1RybteSsuBMPybteS 00V 10V 01V 11V

1leveL 2leveL 3leveL 4leveL

Voltage Control Loop and Power On Sequence

Figure 4 and Figure 5 show the voltage control loop and typical power on sequence of uP6204 respectively. The power on reset is acknowledged and the controller is enabled at T0. A buffer with 160uA maximum current capability starts to charge the soft start capacitor

SCL

SDA

PMBUS Select

(SVID)

5VCC

R1 R2 R3 R4

Rev. P01, File Name: uP6204-DS-P01000

AMD GPU Table

6-Bit/64-Level

Range: 0.8V ~ 1.2V

Step: ~12.5mV

PMBUS Programmable

PWR

ON Default Setting

Level 1 Level 2 Level 3 Level 4

Power Play

Table

VID0

Figure 4. Dyn a mic V oltage Ma nagement

2-Bit PVID

Select

VID1

PMBUS enable SVID mode

(Default PVID mode)

REF/S

REF/P

REF

7uPI Semiconductor Corp., http://www.upi-semi.com

Page 8

Preliminary

uP6204

Functional Description

T a ble 3. AMD GPU VID T a ble T a ble 3. AMD GPU VID T a ble

petS5tiB4tiB3tiB2tiB1tiB0tiB

1000000 0053.1 2000001 5733.1 3000010 523.1 4000011 4213.1 5000100 0003.1 6000101 5782.1 7000110 0572.1 8000111 5262.1 9001000 0052.1

01001001 5732.1 11001010 0522. 21001011 5212.1 31001100 0002.1 41001101 5781.1

tuptuO

egatloV

petS5tiB4tiB3tiB2tiB1tiB0tiB

33 100000 0059.0 43 100001 5739.0 53 100010 0529.0 63 100011 5219.0 73100100 0009.0 83100101 5788.0 93100110 0578.0 04100111 5268.0 14 101000 0058.0 24 10 100 1 57 34101010 0528.0 44101011 5218.0 54101100 0008.0 64101101 5787.0

tuptuO egatloV

38.0

51001110 0571.1 61001111 5261.1 71010000 0051.1 81010001 5731.1 91010010 0521.1 02010011 5211.1 12010100 0001.1 22010101 5780.1 32010110 0570.1 42010111 5260.1 52011000 0050.1 62011001 5 72011010 0520.1 82011011 5210.1 92 011100 0000.1 03011101 5789.0

730.1

74101110 0577.0 84101111 5267.0 94 110000 0057.0 05 110001 5737.0 15 110010 0527.0 25 110011 5217.0 35110100 0007.0 45110101 5786.0 55 110 110 0576.0 65 110 111 5266. 75 111000 0056.0 85 111001 5736.0 95 111010 0526.0 06 111011 5216.0 16 111100 0006.0 26 111101 5785.0

13011110 0579.0 23011111 5269.0

Rev. P01, File Name: uP6204-DS-P0100

36 111110 0575.0 46 111111 5265.0

8uPI Semiconductor Corp., http://www.upi-semi.com

Page 9

Preliminary

uP6204

Functional Description

connected to SS pin after a 800us delay time T The non-inverting input of the error a mplifier V to VSS and ramp up linearly to V drop caused by droop setting resistor R

. (Neglect the voltage

REF

, see the related

DRP

DLY

is equal

EAP

at T1.

section for details.) Consequently, the FB voltage VFB is regulated to V

VR2 is default selected as V

and ra mp up linearly to V

EAP

during soft start cycle

REF

regardless of the status of VID0 and VID1. The output voltage reache s power on default output voltage defined by R2 pin at T2 and stays there f or a time interval T

Error

Amplifier

REF

EAP

DRP

Maximum Current =

160uA

SEN

DFT

T a ble 4. T ypical Power On Periods with CSS = 4.7nF

retemaraPlobmyS

emiTyaleDtratST

emiTtratStfoST

tuptuOotelbanE

noitalugeRni

tluafeDNORWP

doirePegatloV

YLD

PMAR

T+

YLD

TFD

lanimoN

eulaV

su002AN

sm3sm4~1

sm2.3sm2.4~2.1

sm002AN

elbatsujdA

egnaR

Operation Frequency Programming

A resistor RRT connected to RT pin progra ms the oscillation frequency as:

10000

)k(R

(kHz)

OSC

Figure 6 shows the relationship between oscillation frequency and RRT.

COMP

uP6204

Figure 4. V oltage Control Loop

The uP6204 enters PVID mode (parallel VID mode) and moves the output voltage to its final level selected by VID[1:0] and voltages at R1/R2/R3/R4 after T3. The output voltage transition slew rate is identical to the slew rate during TSS. Table 4 shows typical time period of soft start cycle of uP6204.

Controller Enable and

Power On Rest

RAMP

PWR ON Default

Output Volt age = V

T0 T1 T2 T3

DLY

DFT

OUT

Output Voltage

Selected by VID[0:1]

Time

PVID Mode

Figure 5. Power On Sequence

1000

100

Switching Frequency (kHz)

10 100 1000

RRT (kohm)

Figure 6. Switching Frequency vs. RRT.

Channel Current Sensing and Current Balance

The uP6204 senses the pha se currents for current balance by sensing the voltage across the lower switches when they turn on as shown in Figure 7. The sampled-and-held current is calculated as:

SEN

−

]3:1[I

PHASE

SEN

]3:1[VmV10

]3:1[R

Rev. P01, File Name: uP6204-DS-P01000

9uPI Semiconductor Corp., http://www.upi-semi.com

Page 10

Preliminary

uP6204

Functional Description

5VCC

S/H

PHASE[1:3]

SEN

ISEN[1:3]

uP6204

10mV

Figure 7. Pha se Current Sensing.

The uP6204 fine tunes the duty cycle of ea ch channel for current balance according to the sensed inductor current signals. If the current of channel 1 is smaller tha n the current of channel 2 a nd 3, the uP6204 increa ses the duty cycle of the corresponding phase to increase its phase current accordingly , vice versa. The user can adjust R

to adjust

SEN

current ratio between phase s. The sampled-and-held current I

phase over current prote ction. If any one of I

[1:3] are monitored for

SEN

[1:3] is higher

SEN

than 20uA, phase over current protection is activated and shuts down the uP6204.

T otal Current Sen sing

The uP6204 extracts output current by para sitic DCR of the inductors for over current protection. A RC network is paralleled to the inductor for current sensing as shown in Figure 8 where DCR is the parasitic resistance. The V across the capacitor equals to V

= IL x DCR across the

DCR

DCR of the inductor if the time consta nts match: R1CS = R2CS = R3CS = 3xL/DCR

DCR

OUT

CSN

CSP

PHASE1 PHASE2 PHASE3

Figure 8. DCR Current Sensing Sche me

The sourcing ca pa bility of the GM amplifier is 100uA. It is recommended to scale I

= 40uA at rated inductor current.

CSN

Take a 90A converter for example. Assume DCR = 2mΩ, select the sense resistor a ccording to

= k5.1

CSN

m2A90

uA403

Ω=

Ω×

Output V oltage Droop Tuning

The uP6204 dynamically adjusts the output voltage according to the output current the droop tuning resistor RDRP as shown in Figure 4. The sensed current signal IA VG is mirrored and in jected to EAP pin, producing a voltage drop between SS pin and EAP pin.

REFDRPAVGSSEAP

DRP

OUT

−=××−=

/ 3 / R

CSN

VRI3VV ×

Since the FB voltage is regulated to track VEAP, it shows

a load line with slope = (DCR x R Short the R

to disable the droop function.

DRP

DCRI

Over Current Protection

AVG

DRP

The GM a mplifier will source a current source I

= VC/R

AVG

to virtually short its two inputs. Consequently I calculated as:

CSN

DCRI

CSN

Rev. P01, File Name: uP6204-DS-P0100

OUT

DCRI

CSN

The sensed current signal I

CSN

IMAX pin for over current protection. If the IMAX pin voltage

is mirrored and injected to

AVG

is higher than 3.0V, over current protection is activated a nd shuts down the uP6204 as shown in Figure 9. A resistor connected to IMAX set the over current protection level a s:

RV33

××

MAX

IMAX

For example, if DCR = 2mΩ, R

CSN

DCRR

= 1.5kΩ, and R

CSN

47kΩ, the over current protection level is calculated a s 144A.

IMAX

10uPI Semiconductor Corp., http://www.upi-semi.com

Page 11

OUT

(1V/Div)

Preliminary

uP6204

Functional Description

is over the over temperature warning level. A PTC network is used to monitor the converter temperature.

The uP6204 asserts over demarcature warning a nd turn s on the internal MOSFET if

PTC

28.0

1RR

IMAX

(2V/Div)

UGATE1

(20V/Div)

Time: (10ms/Div)

Figure 8. Over Current Protection.

Dyna mic Pha se Reduction

The uP6204 dynamically reduces the phase number of operation to reduce the switching and conduction loss at light load condition. This yield high ef ficiency over wide range of output current.

The 20uA current source out of PSI pin produces a voltage cross the resistor R

RIV ×=

PSIPSIPSI

The uP6204 operates with single phase if V than V

PSI

. (V

< 0.2V) disables the dyna mic pha se reduction

PSI

connected to this pin.

PSI

is smaller

IMAX

function.

The VRHOT/EN is cla mped to 0.45V by internal diode a nd is OK to keep the uP6204 enabled. It is highly suggest to

use 10k

ΩΩ

Ω pull high resistance so that the VRHOT/EN

ΩΩ

can be properly clamped.

The uP6204 asserts thermal shutdown a nd turns off upper/ lower MOSFET s if

PTC

33.0

1RR

An NTC network is also OK f or temperature monitoring.

5VCC

uP6204

VRHOT/EN

10k ohm

PTC

0.3V

TCS

Thermal

Shutdown

Chip Enable

33% of

5VCC

28% of

5VCC

Over Voltage and Under Voltage Protection

The FB voltage is monitored for under voltage and over voltage protection. The OVP is triggered a nd turns on the lower MOSFETs if VFB > V

+ 200mV with 10us dealy.

REF

The OVP function is latch-off type a nd can only be reset by POR or toggling the VRHOT/EN pin.

The UVP is triggered a nd turns off upper/lower MOSFET s if VFB < VEAP - 300mV with 10us dealy. The UVP function is latch-off type and ca n only be re set by POR or toggling the VRHOT/EN pin.

The OVP and UVP functions are blocked about 20us when reference voltage is changed either by PVID or SVID.

Temperature Monitoring and Chip Enable

The VRHOT/EN is multifunctional pin: high temperature warning and chip en able a s shown in Figure 9. Pulling this pin low shuts down the uP6204. The VRHOT/EN is pulled high to 5VCC when released. This enables the uP6204. This pin is cla mped to 0.45V when the sensed temperature

Rev. P01, File Name: uP6204-DS-P01000

Figure 9. T emperature Monitoring a nd Chip Ena ble.

11uPI Semiconductor Corp., http://www.upi-semi.com

Page 12

Preliminary

uP6204

bsolute Ma x imum Ratin

Supply Input Voltage, VCC1/VCC2 (Note 1) -------------------------------------------------------------------------------------- -0.3V to +15V

PHASE to GND

DC ------------------------------------------------------------------------------------------------------------------------------------- -1V to 15V < 200ns ---------------------------------------------------------------------------------------------------------------------------- -5V to 30V

BOOT to PHASE -------------------------------------------------------------------------------------------------------------------------------------- 15V BOOT to GND

DC ------------------------------------------------------------------------------------------------------------------------- -0.3V to PHASE +15V < 200ns -------------------------------------------------------------------------------------------------------------------------- -0.3V to 42V

Input, Output or I/O Voltage ---------------------------------------------------------------------------------------------------------- -0.3V to +6V Storage T emperature Range ------------------------------------------------------------------------------------------------------------- -65OC to +150OC Junction T emperature ------------------------------------------------------------------------------------------------------------------------------------ 150OC Lead T emperature (Soldering, 10 se c) ------------------------------------------------------------------------------------------------------------ 260OC ESD Rating (Note 2)

HBM (Human Body Mode) --------------------------------------------------------------------------------------------------------------------- 2kV MM (Machine Mode) ----------------------------------------------------------------------------------------------------------------------------- 200V

Thermal Informatio

Pack age Thermal Resistance (Note 3)

VQF N6x6-40L θJA ------------------------------------------------------------------------------------------------------------------------- TBD

Power Dissipation, PD @ T A = 25°C

VQF N6x6-40L ----------------------------------------------------------------------------------------------------------------------------------------- TBD

Recommen de d Op er at i o n Conditi on s

Operating Junction T emperature Ra nge (Note 4) ------------------------------------------------------------------------ -40°C to +125°C Operating Ambient T emperature Range -------------------------------------------------------------------------------------- -40°C to +85°C Supply Input Voltage, V

------------------------------------------------------------------------------------ 10.8V to 13.2V

Electrical Characteristics

(VCC = 12V, TA = 25OC, unless otherwise specified)

retemaraPlobmySsnoitidnoCtseTniMpyTxaMstinU

tupnIylppuS

egatloVylppuSV

tnerruCylppuSI

tnerruCylppuStnecseiuQI

dlohserhTROPV

siseretsyHROPV

tratStfoS

Q_CC

HTRCC

SYHCC

V;nepOETAGLdnaETAGU

gnihctiwS,V21=--5--Am

8.01--2.31V

--4--Am

89 01V

--3.0--V

tnerruCtratStfoSI

CCV5

ycaruccAegatloVtuptuOCCV5V

daoLegatloVtuptuOCCV5

noitalugeR

Rev. P01, File Name: uP6204-DS-P0100

ΔV

5CC

V21=021061002Au

1CC

5CC

I,V21=

Am0=59.400.550.5V

5CC

Am02~Am0=5.0---5.0%

12uPI Semiconductor Corp., http://www.upi-semi.com

Page 13

Preliminary

uP6204

Electrical Characteristics

retemaraPlobmySsnoitidnoCtseTniMpyTxaMstinU

ycaruccAegatloVtuptuO

V-

ycaruccAegatloVtuptuO

I V

.A0=

TUO

FER

Vnehw

]4:1[1R

FER

I.C2Iybtes

A0=5.1--5.1%

TUO

,]4:1[1Rybtes

01---01Vm

rotallicsO

ycneuqerFgninnuReerFf

CSO

k33=072003033zHk

noitairaVycneuqerF 01---01%

egnaRycneuqerF 05--0001zHk

elcyCytuDmumixaM 580959%

elcyCytuDmuminiM --0--%

lpmApmaR ΔV

eduti

CSO

V21=--0.4--V

reifilpmArorrE

niaGCDpooLnepOOAngiseDybdeetnarauG0607--Bd

tcudorPhtdiwdnaB-niaGWBGngiseDybdeetnarauG601--zHM

SRSngiseDybdeetnarauG36--su/V

etaRwel

esneStnerruC

oitaResneStnerruCI

XAMI

tnerruCgnicroSmumixaMI

GVA

XAM_NSC

GVA

tesffOreifilpmAMGV

TESFFO

R,Au04=

k01= Ω 09001011%

XAMI

001----Au

V|=

V-

TESFFO

PSC

V,|

NSC

RrotsiseratcennoC

PSC

NSCI

k02= Ω morf

,V1.1=

3---3Vm

NSCDNGot

P-P

srevirDetaG

ecruoSetaGreppUR

kniSetaGreppUR

ecruoSetaGrewoLI

kniSetaGrewoLI

emiTdaeDT

gnirotinoMerutarepmeT

gninraWerutarepmeTrevO

leveLdlohserhT

dlohserhTnwodtuhSlamrehT

leveL

egatloVpmalCgninraWTOV

leveLdlohserhTelbnaEpihCV leveLdlohserhTelbnaEpihCV

Rev. P01, File Name: uP6204-DS-P01000

CRS_GU

KNS_GU

CRS_GL

KNS_GL

V-

TOOB

CRS_GL

KNS_GL

ESAHP

V-

ESAHP

Am051=--3.16.1 Ω

Am051=--8.06.1 Ω

I,V21=

CRS_GU

I,V21=

KNS_GU

Am051=--3.16.2 Ω Am051=--10.2 Ω

--03--sn

SCT

NE/TOHRV

SCT

NE/TOHRV

CCV5foegatnecrep--82-- %

CCV5foegatnecrep--33-- %

I,CCV5fo%03=

NE/TOHRV

Au05=--54.0--V

gnisir4.0----V

gnillaf----2.0V

13uPI Semiconductor Corp., http://www.upi-semi.com

Page 14

Preliminary

uP6204

Electrical Characteristics

retemaraPlobmySsnoitidnoCtseTniMpyTxaMstinU

stupnIlortnoC

leveLdlohserhThgiHtupnIDIVV

leveLdlohserhTwoLtupnIDIVV

]1:0[DIV

gnisir1DIV,0DIV4.1----V

gnillaf1DIV,0DIV----4.0V

snoitcetorP

dlohserhTnoitcetorPtnerruCrevO

leveL

leveLdlohserhTKOrewoPV

ytilibapaCgnikniSKOrewoPV

XAMI

leveLdlohserhTnoitcetorPegatlooVrevOV leveLdlohserhTnoitcetorPegatloVrednUV

VBFV-

KOP

FER

Am4=----001Vm

KOP

.gnisir--03--Vm

--0.3--V

--002--Vm

--003---Vm

Note 1. Stresses listed a s the above “Absolute Maximum Ratings” may cause permanent damage to the device.

These are for stress ratings. Functional operation of the device at the se or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to af fect device relia bility .

Note 2. Devices are ESD sensitive. Handling pre caution recommended. Note 3. θJA is mea sured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of

JEDEC 51-3 thermal mea surement standard.

Note 4. The device is not guaranteed to function outside its operating conditions.

Rev. P01, File Name: uP6204-DS-P0100

14uPI Semiconductor Corp., http://www.upi-semi.com

Page 15

Preliminary

Typical Operation Characteri stics

uP6204

T urn On W aveforms

EN (2V/Div)

Time: (10ms/Div)

SS (0.5V/Div)

(0.5V/Div)

OUT

PHASE1 (5V/Div)

Power Off Wavef orms

VCC1 (5V/Div)

Power On Waveforms

VCC1 (5V/Div)

5VCC (2V/Div)

SS (0.5V/Div)

(0.5V/Div)

OUT

Time: (10ms)

Power Play

SS (0.5V/Div)

OUT

(0.5V/Div)

5VCC (2V/Div)

SS (0.5V/Div)

(0.5V/Div)

OUT

Time: (10ms)

Gate Waveforms (UGA TE Falling)

UGATE1 (5V/Div)

PHASE1

(0.5V/Div)

LGATE1 (5V/Div)

VID0 (2V/Div)

Time: (10ms)

Gate Waveforms (UGA TE Rising)

UGATE1 (5V/Div)

LGATE1 (5V/Div)

PHASE1

(0.5V/Div)

Time: (25ns)

Rev. P01, File Name: uP6204-DS-P01000

Time: (25ns)

15uPI Semiconductor Corp., http://www.upi-semi.com

Page 16

Preliminary

Typical Operation Characteri stics

uP6204

Over Current Protection

(1V/Div)

OUT

IMAX

(2V/Div)

PHASE1

(10V/Div)

Time: (10ms)

5VCC Line Regulation

5.2

5.1 5

4.9

4.8

4.7

4.6

5VCC Output V oltage (V)

4.5

4.4

5 6 7 8 9 1011121314

VCC1 V oltage (V)

Steady State Operation

OUT

(50mV/Div)

PHASE1

(10V/Div)

PHASE2 (10V/Div)

PHASE3

(10V/Div)

Time: (400ns)

5VCC Load Regulation

5.6

5.5

5.4

5.3

5.2

5.1

4.9

4.8

5VCC Output V oltage (V)

4.7

4.6

0 102030405060708090100

5VCC Output Current (mA)

Switching Frequency

1000

Switching Frequency (kHz)

100

10 100

RRT (kΩ)

Rev. P01, File Name: uP6204-DS-P0100

VFB Loag Regulation

0.2

0.1

-0.1

V ariation (%)

-0.2

-0.3

0 102030405060708090

Output Current (A)

16uPI Semiconductor Corp., http://www.upi-semi.com

Page 17

Preliminary

Typical Operation Characteri stics

uP6204

1.61

1.605

1.6

1.595

VREF Output V oltage (V)

1.59

VREF Line Regulation

567891011121314

VCC1 (V)

IMAX V oltage vs. Output Current

2.5

1.5

IMAX Output V oltage (V)

0.5

0 102030405060708090

Output Current (A)

Rev. P01, File Name: uP6204-DS-P01000

17uPI Semiconductor Corp., http://www.upi-semi.com

Page 18

Preliminary

pplication I nformation

This page is intentionally left blank a nd will be update later .

uP6204

18uPI Semiconductor Corp., http://www.upi-semi.com

Rev. P01, File Name: uP6204-DS-P0100

Page 19

Preliminary

uP6204

Packag e I nformation

5.90 - 6.10

0.80 - 1.00

5.90 - 6.10

Pin 1 mark

4.65 - 4.95

4.65 -4.9 5

Bottom View - Exposed Pad

0.35 - 0.45

0.18 - 0.30

4.75 - 4.85

4.95 - 5.05

6.55 - 6.65

0.0 - 0.05

0.20 BSC

0.18 - 0.30

Recommended Solder Pad Pitch and Dimensions

Note

1.Package Outline U nit Description: BSC: Basic. Re presents theoretical exa ct di mension or dimen sion target MIN: Minimum dimension specified. MAX: Maximum dimension specified. REF: Reference. Represents dimension f or reference use only . This value is not a device specification. TYP . Typical. Provided a s a general value. This value is not a device spe cification.

2.Dimensions in Millimeters.

3.Drawing not to scale.

4.These dimensions no not include mold fla sh or protrusion s. Mold fla sh or protrusions shell not exceed 0.15mm.

Rev. P01, File Name: uP6204-DS-P01000

19uPI Semiconductor Corp., http://www.upi-semi.com