Datasheet TZA3043B, TZA3043 Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TZA3043; TZA3043B

Gigabit Ethernet/Fibre Channel
transimpedance amplifier

Product specification
Supersedes data of 1998 Jul 08
File under Integrated Circuits, IC19

2000 Mar 28

Philips Semiconductors Product specification

Gigabit Ethernet/Fibre Channel

TZA3043; TZA3043B

transimpedance amplifier

FEATURES

• Wide dynamic range, typically 2.5 µA to 1.5 mA

• Low equivalent input noise, typically 5.7 pA/√Hz

• Differential transimpedance of 8.3 kΩ

• Wide bandwidth from DC to 950 MHz

• Differential outputs

• On-chip Automatic Gain Control (AGC)

• No external components required

• Single supply voltage from 3.0 to 5.5 V

• Bias voltage for PIN diode

• Pin compatible with TZA3023 and SA5223

• Switched output polarity available (B-version).

ORDERING INFORMATION

TYPE

NUMBER

TZA3043T SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
TZA3043U − bare die in waffle pack carriers; die dimensions 1.030 × 1.300 mm −
TZA3043BT SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
TZA3043BU − bare die in waffle pack carriers; die dimensions 1.030 × 1.300 mm −

NAME DESCRIPTION VERSION

APPLICATIONS

• Digital fibre optic receiver in medium and long haul
optical telecommunications transmission systems or in
high speed data networks

• Wideband RF gain block.

GENERAL DESCRIPTION

The TZA3043 is a high speed transimpedance amplifier
with AGC designed to be used in Gigabit Ethernet/Fibre
Channel opticallinks. It amplifies the current generated by
a photo detector (PIN diode or avalanchephotodiode) and
converts it to a differential output voltage.

PACKAGE

2000 Mar 28 2

Philips Semiconductors Product specification

Gigabit Ethernet/Fibre Channel
transimpedance amplifier

BLOCK DIAGRAM

handbook, full pagewidth

V

CC

1 nF

125 Ω

1 (1)

DREF

3 (4)IPhoto

TZA3043T
TZA3043U

125 Ω

10 pF

GND

GAIN

CONTROL

A1

low noise

amplifier single-ended to

2, 4, 5 (2, 3, 5, 6, 7, 8)

(1)

AGC

peak detector

differential converter

A2

BIASING

TZA3043; TZA3043B

V

CC

8 (11, 12)(13)

(10) 7 OUTQ

(9) 6 OUT

MGU096

The numbers in brackets refer to the pad numbers of the bare die version.
(1) AGC analog I/O (pad 13) is only available on the TZA3043U.

Fig.1 Block diagram of TZA3043T and TZA3043U.

handbook, full pagewidth

V

CC

1 nF

DREF

125 Ω

1 (1)

3 (4)IPhoto

TZA3043BT
TZA3043BU

125 Ω

CONTROL

10 pF

2, 4, 5 (2, 3, 5, 6, 7, 8)

GND

(1)

AGC

GAIN

peak detector

A1

low noise

amplifier single-ended to

A2

differential converter

BIASING

V

CC

8 (11, 12)(13)

(9) 6

OUTQ

(10) 7

OUT

MGU097

The numbers in brackets refer to the pad numbers of the bare die version.
(1) AGC analog I/O (pad 13) is only available on the TZA3043BU.

Fig.2 Block diagram of TZA3043BT and TZA3043BU.

2000 Mar 28 3

Philips Semiconductors Product specification

Gigabit Ethernet/Fibre Channel
transimpedance amplifier

PINNING

SYMBOL

PIN

TZA3043T

DREF 1111analog

GND 2 2 2, 3 2, 3 ground ground
IPhoto 3344analog

GND 4 4 5, 6 5, 6 ground ground
GND 5 5 7, 8 7, 8 ground ground
OUT 6 7 9 10 data

OUTQ 7 6 10 9 data

V

CC

8 8 11, 12 11, 12 supply supply voltage

AGC −−13 13 input/

PIN

TZA3043BT

PAD

TZA3043U

PAD

TZA3043BU

TYPE DESCRIPTION

bias voltage for PIN diode; cathode

output

should be connected to this pin

current input; anode of PIN diode

input

should be connected to this pin;
DC bias levelof 822 mV is one diode
voltage above ground

data output; pin OUT goes HIGH

output

when current flows into pin IPhoto
compliment of pin OUT

output

AGC analog I/O

output

TZA3043; TZA3043B

handbook, halfpage

Fig.3 Pin configuration of TZA3043T.

DREF

IPhoto

GND

1
2

TZA3043T

3
4

MGR287

V

8

CC

OUTQGND

7

OUT

6

GND

5

handbook, halfpage

DREF

IPhoto

GND

1
2

TZA3043BT

3
4

MGU098

8
7
6
5

V

CC

OUTGND
OUTQ
GND

Fig.4 Pin configuration of TZA3043BT.

2000 Mar 28 4

Philips Semiconductors Product specification

Gigabit Ethernet/Fibre Channel
transimpedance amplifier

FUNCTIONAL DESCRIPTION

The TZA3043 is a transimpedance amplifier intended for
use in fibre optic links for signal recovery in Fibre Channel
or Gigabit Ethernet applications. It amplifies the current
generated by a photo detector (PIN diode or avalanche
photodiode) and transforms it into a differential output
voltage. The most important characteristics of the
TZA3043 are high receiver sensitivity and wide dynamic
range. High receiver sensitivity is achieved by minimizing
noise in the transimpedance amplifier.

Input circuit

The signal current generated by a PIN diode can vary
between 2.5 µA to 1.5 mA (p-p).

An AGC loop isimplemented tomake it possible to handle
such a wide dynamic range. The AGC loop increases the
dynamic range of the receiver by reducing the feedback
resistance of the preamplifier.

TZA3043; TZA3043B

The AGC loop hold capacitor is integrated on-chip, so an
external capacitor is not needed for AGC.

AGC monitoring

The AGC voltage can be monitored at pad 13 on the bare
die (TZA3043U/TZA3043BU). Pad 13 is not bonded in the
packaged device (TZA3043T/TZA3043BT). This pad can
beleftunconnected during normal operation.It canalsobe
used to force an external AGC voltage. If pad 13 (AGC) is
connected to GND, the internal AGC loop is disabled and
the receiver gain is at a maximum. The maximum input
current is then approximately 75 µA.

Output circuit

A differential amplifier converts the output of the
preamplifier to a differential voltage (see Fig.5).

The logic level symbol definitions for the differential
outputs are shown in Fig.6.

handbook, full pagewidth

handbook, full pagewidth

V

CC

V

O(max)

V

V

V

O(min)

800 Ω 800 Ω

2 mA

Fig.5 Differential data output circuit.

OQH

V

OH

OQL

V

OL

V

OO

4.5 mA

30 Ω
30 Ω

4.5 mA

MGR290

V

CC

V

o(p-p)

MGR243

OUTQ
OUT

Fig.6 Logic level symbol definitions for data outputs OUT and OUTQ.

2000 Mar 28 5

Philips Semiconductors Product specification

Gigabit Ethernet/Fibre Channel
transimpedance amplifier

PIN diode bias voltage DREF

The transimpedance amplifier together with the PIN diode
determines the performance of an optical receiver for a
large extent. Especiallyhow thePIN diode is connected to
the input and the layout around the input pin influence the
key parameters like sensitivity, the bandwidth and the
Power Supply Rejection Ratio (PSRR) of a
transimpedance amplifier. The total capacitance at the
inputpin is critical to obtainthehighest sensitivity. It should
be kept to a minimum by reducing the capacitance of the
PIN diode and the parasitics around the input pin. The
PIN diode should be placed very close to the IC to reduce
the parasitics. Because the capacitance of the PIN diode
depends on the reverse voltage across it, the reverse
voltage should be chosen as high as possible.

The PIN diode can be connected to the input in two ways
as shown in Figs 7 and 8. In Fig.7 the PIN diode is
connected between pins DREF and IPhoto. Pin DREF
provides an easy bias voltage for the PIN diode. The
voltage at DREF is derived from VCC by a low-pass filter.
The low-pass filter consisting of the internal resistors
R1, R2, C1 and the external capacitor C2 rejects the
supply voltage noise.The external capacitor C2 should be
equal or larger then 1 nF for a high PSRR.

TZA3043; TZA3043B

The reverse voltage across the PIN diode is 4.18 V
(5 − 0.82 V) for 5 V supply or 2.48 V (3.3 − 0.82 V) for

3.3 V supply.

It is preferable to connect the cathode of the PIN diode to
a higher voltage then VCC when such a voltage source is
available on the board. In this case pin DREF can be left
unconnected.Whenanegativesupply voltage is available,
the configuration in Fig.8 can be used. It should be noted
that in this case the direction of the signal current is
reversed compared tothe Fig.7. Properfiltering of the bias
voltage for the PIN diode is essential to achieve the
highest sensitivity level.

V

CC

8

R1

125 Ω
C1

10 pF

MGU103

C2

1 nF

I

i

DREF

IPhoto

R2

125 Ω

1

3

TZA3043

Fig.7 ThePIN diodeconnectedbetweentheinput

and pin DREF.

2000 Mar 28 6

V

CC

8

R1

125 Ω
C1

10 pF

MGU104

1

DREF

IPhoto

3

I

i

negative supply voltage

R2

125 Ω

TZA3043

Fig.8 ThePIN diodeconnectedbetweentheinput

and a negative supply voltage.

Philips Semiconductors Product specification

Gigabit Ethernet/Fibre Channel
transimpedance amplifier

AGC

The TZA3043 transimpedance amplifier can handle input
currents from 1 µA to 1.5 mA. This means a dynamic
range of 63 dB. At low input currents, the transimpedance
must be high to get enough output voltage, and the noise
should be low enough to guaranty minimum bit error rate.
At high input currents however, the transimpedance
should be low to avoid pulse width distortion. This means
that the gain of the amplifier has to vary depending on the
input signal level to handle such a wide dynamic range.
This is achieved in the TZA3043 by implementing an
Automatic Gain Control (AGC) loop. The AGC loop
consists of a peak detector, a hold capacitor and a gain
control circuit.

The peak amplitude of the signal is detected by the peak
detector and it is stored on the holdcapacitor. The voltage
over the hold capacitor is compared to a threshold level.
Thethreshold level is setto25 µA (p-p)input current. AGC
becomes active only for input signals larger than the
threshold level.

TZA3043; TZA3043B

It is disabled for smaller signals. The transimpedance is
then at its maximum value (8.3 kΩ differential).

When AGC is active, the feedback resistor of the
transimpedance amplifier is reduced to keep the output
voltage constant. The transimpedance is regulated from

8.3 kΩ at low currents (I < 30 µA) to 1 kΩ at high currents

(I < 500 µA). Above 500 µA the transimpedance is at its
minimum and can not be reduced further but the front-end
remains linear until input currents of 1.5 mA.

The upper part of Fig.9 shows the output voltages of the
TZA3043 (OUT and OUTQ) as a function of the DC input
current. In the lower part, the difference of both voltages is
shown. It can be seen from the figure that the output
changes linearly up to 25 µA input current where AGC
becomes active. From this point on, AGC tries to keep the
differential output voltage constant around 200 mV for
medium range input currents (input currents <200 µA).
The AGC can not regulate any more above 500 µA input
current and the output voltage rises again with the input
current.

3.9

handbook, full pagewidth

V

o

(V)

3.7

3.5

3.3

3.1

600

V

o(dif)

(mV)

400

200

0

110

V

o(dif)=VOUT

(1) VCC=3V.
(2) VCC= 3.3 V.
(3) VCC=5V.

− V

OUTQ

MGU105

V

OUT

VCC = 5 V

V

OUTQ

(1)

(2)
(3)

10

.

2

3

10

Ii (µA)

4

10

Fig.9 AGC characteristics.

2000 Mar 28 7

Philips Semiconductors Product specification

Gigabit Ethernet/Fibre Channel

TZA3043; TZA3043B

transimpedance amplifier

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

SYMBOL PARAMETER MIN. MAX. UNIT

V

CC

V

n

I

n

P

tot

T

stg

T

j

T

amb

supply voltage −0.5 +6 V
DC voltage

pin/pad IPhoto −0.5 +1 V
pins/pads OUT and OUTQ −0.5 V
pad AGC (bare die only) −0.5 V
pin/pad DREF −0.5 V

+ 0.5 V

CC

+ 0.5 V

CC

+ 0.5 V

CC

DC current

pin/pad IPhoto −2.5 +2.5 mA
pins/pads OUT and OUTQ −15 +15 mA
pad AGC (bare die only) −0.2 +0.2 mA

pin/pad DREF −2.5 +2.5 mA
total power dissipation − 300 mW
storage temperature −65 +150 °C
junction temperature − 150 °C
ambient temperature −40 +85 °C

HANDLING

Precautions should be taken to avoid damage through electrostatic discharge. This is particularly important during
assembly and handling of the bare die. Additional safety can be obtained by bonding the VCC and GND pads first, the
remaining pads may then be bonded to their external connections in any order.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient 160 K/W

2000 Mar 28 8

Philips Semiconductors Product specification

Gigabit Ethernet/Fibre Channel

TZA3043; TZA3043B

transimpedance amplifier

CHARACTERISTICS

Typical values at T
temperature range and supply range; all voltages are measured with respect to ground; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CC

I

CC

P

tot

T

j

T

amb

R

tr

supply voltage 3 5 5.5 V
supply current AC coupled; RL=50Ω− 34 47 mA
total power dissipation VCC=5V − 170 259 mW

junction temperature −40 − +125 °C
ambient temperature −40 +25 +85 °C
small-signal transresistance of

the receiver

f

−3dB(h)

high frequency −3 dB point VCC=5V; Ci= 0.7 pF 1000 1200 − MHz

PSRR power supply rejection ratio measured differentially;

Bias voltage: pin DREF

R

DREF

resistance between DREF and
V

Input: pin IPhoto

V

bias(IPhoto)

input bias voltage on
pin IPhoto

I

i(IPhoto)(p-p)

input current on pin IPhoto
(peak-to-peak value)

R

i

I

n(tot)

small-signal input resistance fi= 1 MHz; input current

total integrated RMS noise
current over bandwidth

=25°C and VCC= 5 V; minimum and maximum values are valid over the entire ambient

amb

V

= 3.3 V − 112 169 mW

CC

measured differentially;
AC coupled

R

= ∞ 13.2 16.6 20 kΩ

L

R

=50Ω 6.6 8.3 10 kΩ

L

V

= 3.3 V; Ci= 0.7 pF 850 1100 − MHz

CC

note 1

f = 1 to 100 MHz − 2 −µA/V
f = 1 GHz − 66 −µA/V

tested at DC 210 250 290 Ω

CC

600 822 1000 mV

VCC= 5 V; note 2 −1500 +6 +1500 µA
V

= 3.3 V; note 2 −1000 +6 +1000 µA

CC

− 28 −Ω

<2 µA (p-p)
referenced to input;

− 200 − nA

∆f = 920 MHz; note 3

2000 Mar 28 9

Philips Semiconductors Product specification

Gigabit Ethernet/Fibre Channel

TZA3043; TZA3043B

transimpedance amplifier

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Data outputs: pins OUT and OUTQ

V

o(cm)

V

o(se)(p-p)

V

OO

R

o

t

, t

r

f

Automatic gain control loop: pad AGC

I

th(AGC)

t

att(AGC)

t

decay(AGC)

Notes

1. PSRR is defined as the ratio of the equivalent current change at the input (∆I
PSRR

For example, a +10 mV disturbance on V
The external capacitorbetween pins DREF and GND has a large impacton the PSRR. The specificationis validwith
an external capacitor of 1 nF.

2. The pulse width distortion (PWD) is <5% over the whole input current range. The PWD is defined as:
PWD

PRBS pattern of 10

3. All I

photodiode itself, with 0.3 pF allowed for the printed-circuit board layout and 0.2 pF intrinsic to the package. Noise
performance is measured differentially.

common mode output voltage AC coupled; RL=50Ω VCC− 2VCC− 1.7 VCC− 1.4 V
single-ended output voltage

(peak-to-peak value)
differential output offset

AC coupled; RL=50Ω;
input current 100 µA (p-p)

75 200 330 mV

−100 − +100 mV

voltage
output resistance single-ended; DC tested 40 50 62 Ω
rise time, fall time VCC= 5 V; 20% to 80%;

− 285 430 ps

input current <20 µA (p-p)

= 3.3 V;20% to 80%;

V

CC

− 300 460 ps

input current <20 µA (p-p)

AGC threshold current referenced to the peak

− 25 −µA
input current; tested at
10 MHz

AGC attack time − 5 −µs
AGC decay time − 10 − ms

) to a change in supply voltage:

IPhoto

∆I

IPhoto

=

-------------------­∆V

CC

at 10 MHz will typically add an extra 20 nA to the photodiode current.

CC

pulse width



----------------------------- -



T

measurements were made with an input capacitance of Ci= 1 pF. This was comprised of 0.5 pF for the

n(tot)

−23

1–

.

where T is the clock period. The PWD is measured differentially with

100%×=

2000 Mar 28 10

Philips Semiconductors Product specification

Gigabit Ethernet/Fibre Channel
transimpedance amplifier

TYPICAL PERFORMANCE CHARACTERISTICS

40

handbook, halfpage

I

CC

(mA)

38

36

34

32

30

28

−40 0

(1) VCC=5V.
(2) VCC= 3.3 V.
(3) VCC=3V.

(1)

(2)

(3)

40

MGU112

Tj (°C)

120

80

34.8

handbook, halfpage

I

CC

(mA)

34.4

34.0

33.6

33.2

32.8
34

TZA3043; TZA3043B

MGU113

56

VCC (V)

Fig.10 Supply current as a function of the junction

temperature.

825

handbook, halfpage

V

i

(mV)

823

821

819

817

34

56

MGU114

VCC (V)

Fig.11 Supply current as a function of the supply

voltage.

920

handbook, halfpage

V

i

(mV)

840

760

680

−40 0

(1) VCC=5V.
(2) VCC= 3.3 V.
(3) VCC=3V.

(1)

(2)

(3)

40

MGU115

80

Tj (°C)

120

Fig.12 Input voltage as a function of the supply

voltage.

2000 Mar 28 11

Fig.13 Input voltage as a function of the junction

temperature.

Philips Semiconductors Product specification

Gigabit Ethernet/Fibre Channel
transimpedance amplifier

1.68

handbook, halfpage

V

o(cm)

(V)

1.675

1.67

1.665

1.66

1.655
3

(1) VCC− V
(2) VCC− V

OUT
OUTQ

(1)

(2)

4

.

.

56

MGU116

VCC (V)

1.85

handbook, halfpage

V

o(cm)

(V)

1.75

1.65

1.55

−40 0

VCC=5V.
(1) VCC− V
(2) VCC− V

OUT
OUTQ

TZA3043; TZA3043B

MGU117

(1)

(2)

40

.

.

80

Tj (°C)

120

Fig.14 Common mode voltage at the output as a

function of the supply voltage.

Fig.15 Common mode voltage at the output as a

function of the junction temperature.

2000 Mar 28 12

Philips Semiconductors Product specification

Gigabit Ethernet/Fibre Channel
transimpedance amplifier

APPLICATION AND TEST INFORMATION

handbook, full pagewidth

22 nF

V

CC

8

DREF

1

TZA3043T

IPhoto

3

1 nF

2

GND

4

GND5GND

10 µH

680 nF

TZA3043; TZA3043B

V

P

7

6

OUTQ

OUT

Zo = 50 Ω

(1)

(1)

Zo = 50 Ω

100 nF

100 nF

R3
50 Ω

R4
50 Ω

(1) For TZA3043BT pin 7 is OUT and pin 6 is OUTQ.

MGU101

Fig.16 Application diagram.

2000 Mar 28 13

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2000 Mar 28 14

V

CC

ndbook, full pagewidth

Philips Semiconductors Product specification

Gigabit Ethernet/Fibre Channel

transimpedance amplifier

1 nF

DREF

IPhoto

(1) (1) (1)

22 nF

V

CC

8

(2)

1

TZA3043T TZA3044

3

2

GND4GND5GND

7

6

OUTQ

OUT

4 pF

(2)

noise filter:
1-pole, 800 MHz

680 nF

100

Ω

1.5 nF

1.5 nF

DIN

DINQ

100 nF

4

5

3

AGND

V

6

CCA

1

180 kΩ

RSET7CF

16

SUB8JAM

9

STQ10ST

100 nF

ref

14

11

DGND

V

CCD

13

12

DOUT

DOUTQ

1 kΩ

50 Ω 50 Ω

MGU102

data out

level-detect
status

VCC − 2 V

TZA3043; TZA3043B

V

15

(1) Ferrite bead e.g. Murata BLM10A700S.
(2) For TZA3043BT pin 7 is OUT and pin 6 is OUTQ.

Fig.17 Gigabit Ethernet/Fibre Channel receiver using the TZA3043T and TZA3044.

Philips Semiconductors Product specification

Gigabit Ethernet/Fibre Channel
transimpedance amplifier

Test circuits

handbook, full pagewidth

Zo = 50 Ω

223-1 PRBS

PATTERN

GENERATOR

C

D

C

TRD
C IN

ZT = s21.(R + Zi) . 2 R = 470 Ω, Zi = 28 Ω

NETWORK ANALYZER

S-PARAMETER TEST SET

PORT 1 PORT 2

Zo = 50 Ω

V

CC

100 nF

10 nF

51 Ω

470 Ω

IPhoto

TZA3043

OUT

OUTQ

100 nF

TZA3043; TZA3043B

SAMPLING

OSCILLOSCOPE/

TDR/TDT

1

TR

2

OM5803

Fig.18 Electrical test circuit.

Zo = 50 Ω

MGU106

2000 Mar 28 15

Philips Semiconductors Product specification

Gigabit Ethernet/Fibre Channel
transimpedance amplifier

handbook, full pagewidth

23

2

-1 PRBS

PATTERN

GENERATOR

C

D

C

LIGHTWAVE MULTIMETER

−9.54 dBm

OPTICAL ATTENUATOR
0 dBm/1300

LASER DRIVER

TRD
C IN

TZA3041

DIN

DINQ

OPTICAL

INPUT

IN OUT

Laser

10%90%

PIN

10 nF

V

CC

BLM

DREF

IPhoto

TZA3043

22 nF

OUT

OUTQ

TZA3043; TZA3043B

ERROR DETECTOR

DatainClock

in

100 nF

100 nF

SAMPLING

OSCILLOSCOPE/

TDR/TDT

1
2

TR

1.24416 GHz

OM5804OM5802

Fig.19 Optical test circuit.

Zo = 50 Ω

MGU107

2000 Mar 28 16

Philips Semiconductors Product specification

Gigabit Ethernet/Fibre Channel
transimpedance amplifier

handbook, full pagewidth

TZA3043; TZA3043B

MGU108

Fig.20 Differential output with −25 dBm optical input power [input current of 5.17 µA (p-p)].

handbook, full pagewidth

MGU109

Fig.21 Differential output with −15 dBm optical input power [input current of 51.7 µA (p-p)].

2000 Mar 28 17

Philips Semiconductors Product specification

Gigabit Ethernet/Fibre Channel
transimpedance amplifier

handbook, full pagewidth

TZA3043; TZA3043B

MGU110

handbook, full pagewidth

Fig.22 Differential output with −5 dBm optical input power [input current of 517 µA (p-p)].

MGU111

Fig.23 Differential output with −2 dBm optical input power [input current of 1030 µA (p-p)].

2000 Mar 28 18

Philips Semiconductors Product specification

Gigabit Ethernet/Fibre Channel

TZA3043; TZA3043B

transimpedance amplifier

BONDING PAD LOCATIONS

SYMBOL PAD TZA3043U PAD TZA3043BU

COORDINATES

xy

DREF 1 1 95 881
GND 2 2 95 618
GND 3 3 95 473
IPhoto 4 4 95 285
GND 5 5 215 95
GND 6 6 360 95
GND 7 7 549 95
GND 8 8 691 95
OUT 9 10 785 501
OUTQ 10 9 785 641
V

CC

V

CC

11 11 567 1055
12 12 424 1055

AGC 13 13 259 1055

(1)

Note

1. All coordinates are referenced, in µm, to the bottom left-hand corner of the die.

VCCV

1030

µm

11

GND

CC

10

9

8

GND

OUTQ

OUT

MGU099

1300

µm

DREF

GND

GND

IPhoto

x

0

1

2

3

4

0
y

1300

µm

DREF

GND

GND

IPhoto

x

0

AGC

12

13

1

2

3

4

0

y

TZA3043U

5

67

GND

GND

AGC

13

TZA3043BU

5

67

GND

GND

VCCV

12

1030

µm

11

GND

CC

10

9

8

GND

OUT

OUTQ

MGU100

Fig.24 Bonding pad locations of the TZA3043U.

2000 Mar 28 19

Fig.25 Bonding pad locations of the TZA3043BU.

Philips Semiconductors Product specification

Gigabit Ethernet/Fibre Channel

TZA3043; TZA3043B

transimpedance amplifier

Physical characteristics of the bare die

PARAMETER VALUE

Glass passivation 2.1 µm PSG (PhosphoSilicate Glass) on top of 0.65 µm oxynitride
Bonding pad dimension minimum dimension of exposed metallization is 90 × 90 µm (pad size = 100 × 100 µm)
Metallization 1.22 µm W/AlCu/TiW
Thickness 380 µm nominal
Size 1.03 × 1.30 mm (1.34 mm
Backing silicon; electrically connected to GND potential through substrate contacts
Attach temperature <440 °C; recommended die attach is glue
Attach time <15 s

2

)

2000 Mar 28 20

Philips Semiconductors Product specification

Gigabit Ethernet/Fibre Channel
transimpedance amplifier

PACKAGE OUTLINE

SO8: plastic small outline package; 8 leads; body width 3.9 mm

D

c

y

Z

8

5

TZA3043; TZA3043B

SOT96-1

E

H

E

A

X

v M

A

A

pin 1 index

1

e

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

UNIT

mm

inches

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

A

max.

1.75

0.069

A1A2A

0.25

1.45

0.10

1.25

0.010

0.057

0.004

0.049

0.25

0.01

b

3

p

0.49

0.25

0.36

0.19

0.019

0.0100

0.014

0.0075

4

w M

b

p

0 2.5 5 mm

scale

(1)E(2)

cD

5.0

4.8

0.20

0.19

eHELLpQZywv θ

4.0

1.27

3.8

0.16

0.050

0.15

2

A

6.2

5.8

0.244

0.228

Q

3

A

θ

0.25 0.10.25

0.010.010.041 0.004

(1)

0.7

0.3

0.028

0.012

o

8

o

0

L

p

L

0.7

0.6

0.028

0.024

(A )

1

detail X

1.0

1.05

0.4

0.039

0.016

OUTLINE
VERSION

SOT96-1

IEC JEDEC EIAJ

076E03 MS-012

REFERENCES

2000 Mar 28 21

EUROPEAN

PROJECTION

ISSUE DATE

97-05-22
99-12-27

Philips Semiconductors Product specification

Gigabit Ethernet/Fibre Channel
transimpedance amplifier

SOLDERING
Introduction to soldering surface mount packages

Thistext gives a very briefinsightto a complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages.Wave soldering isnot always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuit boardbyscreen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating,soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

Wave soldering

Conventional single wave soldering is not recommended
forsurfacemount devices (SMDs) orprinted-circuitboards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

TZA3043; TZA3043B

If wave soldering is used the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackageswith leads on foursides, thefootprintmust
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement andbefore soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

2000 Mar 28 22

Philips Semiconductors Product specification

Gigabit Ethernet/Fibre Channel

TZA3043; TZA3043B

transimpedance amplifier

Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

BGA, LFBGA, SQFP, TFBGA not suitable suitable
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable

(3)

PLCC
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

5. Wave soldering is only suitable for SSOP and TSSOP packageswith a pitch (e) equal to or larger than 0.65 mm; it is

, SO, SOJ suitable suitable

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

The package footprint must incorporate solder thieves downstream and at the side corners.

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

SOLDERING METHOD

WAVE REFLOW

(2)

(3)(4)
(5)

suitable

suitable
suitable

(1)

.

2000 Mar 28 23

Philips Semiconductors Product specification

Gigabit Ethernet/Fibre Channel

TZA3043; TZA3043B

transimpedance amplifier

DATA SHEET STATUS

DATA SHEET STATUS

Objective specification Development This data sheet contains the design target or goal specifications for

Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be

Product specification Production This data sheet contains final specifications. Philips Semiconductors

Note

1. Please consult the most recently issued data sheet before initiating or completing a design.

DEFINITIONS
Short-form specification  The data in a short-form

specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
atthese or at anyotherconditions above those giveninthe
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.

Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentationor warranty that such applications willbe
suitable for the specified use without further testing or
modification.

DISCLAIMERS
Life support applications  These products are not

designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expectedto result inpersonal injury. Philips
Semiconductorscustomersusingor selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

PRODUCT

STATUS

DEFINITIONS

product development. Specification may change in any manner without
notice.

published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.

reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.

Right to make changes  Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
theuseof any of theseproducts, conveysnolicenceor title
under any patent, copyright, or mask work right to these
products,and makes no representationsorwarranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.

BARE DIE DISCLAIMER

All die are tested and are guaranteed to comply with all
data sheet limits up to the point of wafer sawing for a
periodof ninety (90)days from thedate of Philips'delivery.
If there are data sheet limits not guaranteed, these will be
separately indicated in the data sheet. There are no post
packing tests performed on individual die or wafer. Philips
Semiconductorshas no controlofthird party procedures in
the sawing, handling, packing or assembly of the die.
Accordingly, Philips Semiconductors assumes no liability
for device functionality or performance of the die or
systems after third party sawing, handling, packing or
assembly of the die. It is the responsibility of the customer
to test and qualify their application in whichthe die is used.

(1)

2000 Mar 28 24

Philips Semiconductors Product specification

Gigabit Ethernet/Fibre Channel
transimpedance amplifier

TZA3043; TZA3043B

NOTES

2000 Mar 28 25

Philips Semiconductors Product specification

Gigabit Ethernet/Fibre Channel
transimpedance amplifier

TZA3043; TZA3043B

NOTES

2000 Mar 28 26

Philips Semiconductors Product specification

Gigabit Ethernet/Fibre Channel
transimpedance amplifier

TZA3043; TZA3043B

NOTES

2000 Mar 28 27

Philips Semiconductors – a w orldwide compan y

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For all other countries apply to: Philips Semiconductors,
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© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

2000

Internet: http://www.semiconductors.philips.com

69

Printed in The Netherlands 403510/200/02/pp28 Date of release: 2000 Mar 28 Document order number: 9397 750 06817