Datasheet TZA3023U-C3, TZA3023T-C3, TZA3023T-C1 Datasheet (Philips)

Page 1
DATA SH EET
Product specification Supersedes data of 1997 Oct 17 File under Integrated Circuits, IC19
2000 Mar 29
INTEGRATED CIRCUITS
TZA3023
Page 2
2000 Mar 29 2
Philips Semiconductors Product specification
SDH/SONET STM4/OC12 transimpedance amplifier
TZA3023
FEATURES
Wide dynamic input range from 1 µA to 1.5 mA
Low equivalent input noise of 3.5 pA/Hz (typical)
Differential transimpedance of 21 k
Wide bandwidth from DC to 600 MHz
Differential outputs
On-chip Automatic Gain Control (AGC)
No external components required
Single supply voltage from 3.0 to 5.5 V
Bias voltage for PIN diode
Pin compatible with SA5223.
APPLICATIONS
Digital fibre optic receiver in short, medium and long haul optical telecommunications transmission systems or in high-speed data networks
Wideband RF gain block.
DESCRIPTION
TheTZA3023isalow-noisetransimpedanceamplifierwith AGC designed to be used in STM4/OC12 fibre optic links. It amplifies the current generated by a photo detector (PIN diode or avalanche photodiode) and converts it to a differential output voltage.
ORDERING INFORMATION
BLOCK DIAGRAM
TYPE
NUMBER
PACKAGE
NAME DESCRIPTION VERSION
TZA3023T SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 TZA3023U bare die in waffle pack carriers; die dimensions 1.030 × 1.300 mm
handbook, full pagewidth
GAIN
CONTROL
BIASING
A1
1 (1)
8 (11, 12)
DREF
3 (4)IPhoto
low noise
amplifier single-ended to
differential converter
V
CC
2, 4, 5 (2, 3, 5, 6, 7, 8)
GND
AGC
(1)
peak detector
TZA3023
6 (9) OUT
7 (10) OUTQ
MGK918
2
k
(13)
Fig.1 Block diagram.
The numbers in brackets refer to the pad numbers of the bare die version. (1) AGC analog I/O is only available on the TZA3023U (pad 13).
Page 3
2000 Mar 29 3
Philips Semiconductors Product specification
SDH/SONET STM4/OC12 transimpedance amplifier
TZA3023
PINNING
SYMBOL
PIN
TZA3023T
PAD
TZA3023U
TYPE DESCRIPTION
DREF 1 1 analog output bias voltage for PIN diode; cathode should be connected to
this pin GND 2 2, 3 ground ground IPhoto 3 4 analog input current input; anode of PIN diode should be connected to this
pin; DC bias level of 800 mV, one diode voltage aboveground GND 4 5, 6 ground ground GND 5 7, 8 ground ground OUT 6 9 output data output; pin OUT goes HIGH when current flows into
pin IPhoto OUTQ 7 10 output data output; compliment of pin OUT V
CC
8 11, 12 supply supply voltage
AGC 13 input/output AGC analog I/O
handbook, halfpage
1 2 3 4
8 7 6 5
MGK917
TZA3023T
V
CC
OUTQGND OUT GND
GND
IPhoto
DREF
Fig.2 Pin configuration.
Page 4
2000 Mar 29 4
Philips Semiconductors Product specification
SDH/SONET STM4/OC12 transimpedance amplifier
TZA3023
FUNCTIONAL DESCRIPTION
The TZA3023 is a transimpedance amplifier intended for use in fibre optic links for signal recovery in STM4/OC12 applications. It amplifies the current generated by a photo detector (PIN diode or avalanche photodiode) and transforms it into a differential output voltage. The most important characteristics of theTZA3023 are highreceiver sensitivity and wide dynamic range.
Highreceiver sensitivity is achieved by minimizing noisein the transimpedance amplifier. The signal current generated by a PIN diode can vary between 1 µA to 1.5 mA (p-p). An AGC loop is implemented to make it possible to handle such a wide dynamic range. TheAGCloop increases the dynamic rangeofthe receiver by reducing the feedback resistance of the preamplifier.
The AGC loop hold capacitor is integrated on-chip, so an external capacitor is not needed for AGC. The AGC voltage can be monitored at pad 13 on the bare die (TZA3023U).Pad 13isnotbondedin the packaged device (TZA3023T). This pad can be left unconnected during normal operation. It can also be used to force an external AGC voltage. If pad 13 is connected to GND, the internal AGC loop is disabled and the receiver gain is at a maximum. The maximum input current is then approximately 50 µA.
A differential amplifier converts the single-ended output of the preamplifier to a differential output voltage (see Fig.3).
handbook, full pagewidth
MGK922
600 600
30
V
CC
V
OUTQ
V
OUT
4.5 mA
2 mA
4.5 mA
30
Fig.3 Data output buffer.
handbook, full pagewidth
MGK885
V
OO
V
O(max)
V
OQH
V
OH
V
OQL
V
OL
V
O(min)
V
o (p-p)
V
CC
CML/PECL OUTPUT
Fig.4 Logic level symbol definitions for data outputs OUT and OUTQ.
Page 5
2000 Mar 29 5
Philips Semiconductors Product specification
SDH/SONET STM4/OC12 transimpedance amplifier
TZA3023
PIN diode bias voltage DREF
The transimpedance amplifier together with the PIN diode determines the performance of an optical receiver for a large extent. Especially how the PIN diode is connected to the input and the layout around the input pin influence the key parameters like sensitivity, bandwidth and the Power Supply Rejection Ratio (PSRR) of a transimpedance amplifier. The total capacitance at the input pin is critical to obtain the highest sensitivity. It should be kept to a minimum by reducing the capacitor of the PIN diode and the parasitics around the input pin. The PIN diode should be placed very close to the IC to reduce the parasitics. Because the capacitance ofthe PIN diode dependson the reverse voltage across it, the reverse voltage should be chosen as high as possible.
The PIN diode can be connected to the input in two ways as shown in Figs 5 and 6. In Fig.5 the PIN diode is connectedbetweenDREFandIPhoto.Pin DREFprovides an easy bias voltage for the PIN diode. The voltage at DREF is derived from VCC by a low-pass filter. The low-passfilterconsistingof the internal resistor R1, C1 and the external capacitor C2 rejects the supply voltage noise. The external capacitor C2 should be equal or larger then 1 nF for a high PSRR.
The reverse voltage across the PIN diode is 4.2 V (5 0.8 V) for 5 V supply or 2.5 V (3.3 0.8 V) for 3.3 V supply.
The DC voltage at DREFdecreases with increasingsignal levels. Consequently the reverse voltage across the PIN diode will also decrease with increasing signal levels. This can be explained with an example. When the PIN diode delivers a peak-to-peak current of 1 mA, the average DC current will be 0.5 mA. This DC current is delivered by VCC through the internal resistor R1 of 2 k which will cause a voltage drop of 1 V across the resistor and the reverse voltage across the PIN diode will be reduced by 1 V.
It is preferable to connect the cathode of the PIN diode to a higher voltage then VCC when such a voltage source is available on the board. In this case pin DREF can be left unconnected.Whenanegativesupplyvoltageisavailable, the configuration in Fig.6 can be used. It should be noted that in this case the direction of the signal current is reversed compared to Fig.5. Proper filtering of the bias voltage for the PIN diode is essential to achieve the highest sensitivity level.
MCD900
R1
2 k
C1
10 pF
C2
1 nF
V
CC
I
i
4
8
TZA3023
7
IPhoto
DREF
Fig.5 ThePIN diodeconnected between the input
and pin DREF.
MCD901
R1
2 k
C1
10 pF
V
CC
I
i
4
8
TZA3023
7
IPhoto
negative supply voltage
DREF
Fig.6 ThePIN diodeconnected between the input
and a negative supply voltage.
Page 6
2000 Mar 29 6
Philips Semiconductors Product specification
SDH/SONET STM4/OC12 transimpedance amplifier
TZA3023
AGC
TZA3023 transimpedance amplifier can handle input currents from 0.5 µA to 1.5 mA. This means a dynamic range of 72 dB. At low input currents, the transimpedance must be high to get enough output voltage, and the noise should be low enough to guaranty minimum bit error rate. At high input currents however, the transimpedance should be low to avoid pulse width distortion. This means that the gain of the amplifier has to vary depending on the input signal level to handle such a wide dynamic range. This is achieved in the TZA3023 by implementing an Automatic Gain Control (AGC) loop.
TheAGCloop consists of a peak detector, aholdcapacitor and a gain control circuit. The peak amplitude of the signal isdetected by the peakdetectorand it is storedonthe hold capacitor.Thevoltage over the hold capacitor iscompared to a threshold level. The threshold level is set to 10 µA (p-p) input current. AGC becomes active only for input signals larger than the threshold level.
It is disabled for smaller signals. The transimpedance is then at its maximum value (21 k differential).
When the AGC is active, the feedback resistor of the transimpedance amplifier is reduced to keep the output voltage constant. The transimpedance is regulated from 21 kat low currents (I < 10 µA) to 800 at high currents (I < 500 µA). Above 500 µA the transimpedance is at its minimum and can not be reduced further but the front-end remains linear until input currents of 1.5 mA.
The upper part of Fig.7 shows the output voltages of the TZA3023 (OUT and OUTQ) as a function of the DC input current. In the lower part, the difference of both voltages is shown. It can be seen from the figure that the output changes linearly up to 10 µA input current where AGC becomes active. From this point on, AGC tries to keep the differential output voltage constant around 200 mV for medium range input currents (input currents <200 µA). The AGC can not regulate any more above 600 µA input current, and the output voltage rises again with the input current.
handbook, full pagewidth
0
600
400
200
MCD914
110
2
10
(1)
(2) (3)
Ii (µA)
V
o
(V)
V
o(dif)
(mV)
10
3
10
4
1
1.2
1.6
1.4
1.8
VCC = 3 V
V
OUT
V
OUTQ
Fig.7 AGC characteristics.
V
o(dif)=VOUT
V
OUTQ
. (1) VCC=3V. (2) VCC= 3.3 V. (3) VCC=5V.
Page 7
2000 Mar 29 7
Philips Semiconductors Product specification
SDH/SONET STM4/OC12 transimpedance amplifier
TZA3023
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
HANDLING
Precautions should be taken to avoid damage through electrostatic discharge. This is particularly important during assembly and handling of the bare die. Additional safety can be obtained by bonding the VCC and GND pads first, the remaining pads may then be bonded to their external connections in any order.
THERMAL CHARACTERISTICS
SYMBOL PARAMETER MIN. MAX. UNIT
V
CC
supply voltage 0.5 +6 V
V
n
DC voltage
pin 3/pad 4: IPhoto 0.5 +1 V pins 6 and 7/pads 9 and 10: OUT and OUTQ 0.5 V
CC
+ 0.5 V
pad 13: AGC (TZA3023U only) 0.5 V
CC
+ 0.5 V
pin 1/pad 1: DREF 0.5 V
CC
+ 0.5 V
I
n
DC current
pin 3/pad 4: IPhoto 1 +2.5 mA pins 6 and 7/pads 9 and 10: OUT and OUTQ 15 +15 mA pad 13: AGC (TZA3023U only) 0.2 +0.2 mA pin 1/pad 1: DREF 2.5 +2.5 mA
P
tot
total power dissipation 300 mW
T
stg
storage temperature 65 +150 °C
T
j
junction temperature 125 °C
T
amb
ambient temperature 40 +85 °C
SYMBOL PARAMETER VALUE UNIT
R
th(j-a)
thermal resistance from junction to ambient 160 K/W
Page 8
2000 Mar 29 8
Philips Semiconductors Product specification
SDH/SONET STM4/OC12 transimpedance amplifier
TZA3023
CHARACTERISTICS
Typical values at T
amb
=25°C and VCC= 5 V; minimum and maximum values are valid over the entire ambient
temperature range and supply range; all voltages are measured with respect to ground; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
CC
supply voltage 3 5 5.5 V
I
CC
supply current VCC= 5 V; ACcoupled;
R
L
=50
23 28 45 mA
V
CC
= 3.3V; ACcoupled;
RL=50
20 28 42 mA
P
tot
total power dissipation VCC=5V 140 248 mW
V
CC
= 3.3 V 95 152 mW
T
j
junction temperature 40 +125 °C
T
amb
ambient temperature 40 +25 +85 °C
R
tr
differential small-signal transresistance of the receiver
VCC= 5 V; ACcoupled; RL=50
17.5 21 25 k
V
CC
= 3.3 V; AC coupled;
RL=50
16 19.5 25 k
f
3dB(h)
high frequency 3 dB point VCC=5V; Ci= 0.7 pF 450 580 750 MHz
V
CC
= 3.3 V; Ci= 0.7 pF 440 520 600 MHz
PSRR power supply rejection ratio measured differentially;
note 1
f = 100 kHz to 10 MHz 12µA/V f = 10 to 100 MHz 25µA/V f = 100 MHz to 1 GHz 5 100 µA/V
Bias voltage: pin DREF
R
DREF
resistance between pins DREF and V
CC
DC tested 1680 2000 2320
Input: pin IPhoto
V
bias(IPhoto)
input bias voltage on pin IPhoto
720 800 970 mV
I
i(IPhoto)(p-p)
input current on pin IPhoto (peak-to-peak value)
VCC= 5 V; note 2 1500 +4 +1500 µA V
CC
= 3.3 V; note 2 1000 +4 +1000 µA
R
i
small-signal input resistance fi= 1 MHz; input current
<2 µA (p-p)
95 −Ω
I
n(tot)
total integrated RMS noise current over bandwidth (referenced to input)
note 3
f = 311 MHz 55 nAf = 450 MHz 80 nAf = 622 MHz 120 nA
Page 9
2000 Mar 29 9
Philips Semiconductors Product specification
SDH/SONET STM4/OC12 transimpedance amplifier
TZA3023
Notes
1. PSRR is defined as the ratio of the equivalent current change at the input (I
IPhoto
) to a change in supply voltage:
For example, a + 4 mV disturbance on V
CC
at 10 MHz will typically add an extra 8 nA to the photodiode current. The external capacitor between pins DREF and GND has a large impact on the PSRR. The specification is valid with an external capacitor of 1 nF. The PSSR is guaranteed by design.
2. The Pulse Width Distortion (PWD) is <5% over the whole input current range. The PWD is defined as: where T is the clock period. The PWD is measured differentially with
PRBS pattern of 10
23
.
3. All I
n(tot)
measurements were made with an input capacitance of Ci= 1.2 pF. This was comprised of 0.7 pF for the photodiode itself, with 0.3 pF allowed for the printed-circuit board layout and 0.2 pF intrinsic to the package. Noise performance is measured differentially.
Data outputs: pins OUT and OUTQ
V
o(cm)
common mode output voltage AC coupled; RL=50 VCC− 2VCC− 1.7 VCC− 1.4 V
V
o(se)(p-p)
single-ended output voltage (peak-to-peak value)
AC coupled; RL=50Ω; input current 100 µA (p-p)
75 200 330 mV
V
OO
differential output offset voltage
100 0 +100 mV
R
o(se)
single-ended output resistance
DC tested 40 50 62
t
r
, t
f
rise time, fall time VCC= 5 V; 20% to 80%;
input current <10 µA (p-p)
400 510 700 ps
V
CC
= 3.3 V;20% to 80%;
input current <10 µA (p-p)
450 550 700 ps
Automatic gain control loop: pad AGC
I
th(AGC)
AGC threshold current referred to the peak input
current; tested at 10 MHz
10 −µA
t
att(AGC)
AGC attack time 5 −µs
t
decay(AGC)
AGC decay time 10 ms
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
PSRR
I
IPhoto
V
CC
------------------- -
=
PWD
pulse width
T
----------------------------- -
1


100%×=
Page 10
2000 Mar 29 10
Philips Semiconductors Product specification
SDH/SONET STM4/OC12 transimpedance amplifier
TZA3023
TYPICAL PERFORMANCE CHARACTERISTICS
handbook, halfpage
40 0
(2)
40
Tj (°C)
I
CC
(mA)
120
40
20
36
80
32
28
24
MCD908
(3)
(1)
Fig.8 Supply current as a function of the junction
temperature.
(1) VCC=5V. (2) VCC= 3.3 V. (3) VCC=3V.
handbook, halfpage
34
I
CC
(mA)
VCC (V)
56
31.4
31.0
30.2
29.8
30.6
MCD909
Fig.9 Supply current as a function of the supply
voltage.
handbook, halfpage
34
V
i
(mV)
VCC (V)
56
808
806
802
800
804
MCD910
Fig.10 Input voltage as a function of the supply
voltage.
handbook, halfpage
40 0
(1)
(2)
(3)
40
Tj (°C)
V
i
(mV)
120
900
660
740
820
80
MCD911
Fig.11 Input voltage as a function of the junction
temperature.
(1) VCC=5V. (2) VCC= 3.3 V. (3) VCC=3V.
Page 11
2000 Mar 29 11
Philips Semiconductors Product specification
SDH/SONET STM4/OC12 transimpedance amplifier
TZA3023
handbook, halfpage
3
(1)
(2)
4
VCC (V)
V
o(cm)
(V)
56
1.686
1.680
1.668
1.662
1.674
MCD912
Fig.12 Common mode voltage at the output as a
function of the supply voltage.
(1) VCC− V
OUT
.
(2) VCC− V
OUTQ
.
handbook, halfpage
40 0
(2)
(1)
40
Tj (°C)
V
o(cm)
(V)
120
1.85
1.55
1.65
1.75
80
MCD913
Fig.13 The common mode voltageat the output as
a function of the junction temperature.
VCC= 3.3 V. (1) VCC− V
OUT
.
(2) VCC− V
OUTQ
.
Page 12
2000 Mar 29 12
Philips Semiconductors Product specification
SDH/SONET STM4/OC12 transimpedance amplifier
TZA3023
APPLICATION AND TEST INFORMATION
handbook, full pagewidth
2
MCD898
1
8
V
CC
DREF
3
IPhoto
GND
4
GND5GND
TZA3023T
7
OUTQ
6
OUT
50 50
Zo = 50
Zo = 50
22 nF
1 nF
680 nF
10 µH
V
P
100 nF
100 nF
Fig.14 Application diagram.
Page 13
2000 Mar 29 13
Philips Semiconductors Product specification
SDH/SONET STM4/OC12
transimpedance amplifier
TZA3023
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k
, full pagewidth
MCD899
12
DOUTQ
6
OUT
7
OUTQ
13
DOUT
1 k
50 50
10 nF
10 nF
100 nF
8 pF
noise filter: 1-pole, 400 MHz
100
61 k
TZA3023T TZA3044
SUB JAM STQ STAGND
8
V
CC
V
CC
6
V
CCA
16
RSET7CF15V
ref
14
V
CCD
DGND
data out
level-detect status
VCC 2 V
5
DINQ
4
DIN
3
IPhoto
1
DREF
22 nF
680 nF
100 nF
1 nF
7.5 pF
1.1 pF
16.4 nH
16.4 nH
optional noise filter: 3-pole, 470 MHz Bessel
(1)
(1) (1)
2
GND4GND5GND
3 1 8 9 10 11
Fig.15 STM4/OC12 receiver using the TZA3023T and postamplifier TZA3044.
(1) Ferrite bead e.g. Murata BLM10A700S.
Page 14
2000 Mar 29 14
Philips Semiconductors Product specification
SDH/SONET STM4/OC12 transimpedance amplifier
TZA3023
Test circuits
handbook, full pagewidth
MCD902
1 k
51
Zo = 50
Zo = 50
Zo = 50
IPhoto
OUT
OUTQ
10 nF
TRD
V
CC
100 nF
TR
1
SAMPLING
OSCILLOSCOPE/
TDR/TDT
2
PORT 1 PORT 2
NETWORK ANALYZER
ZT = s21.(R + Zi) . 2 R = 1 k, Zi = 100
S-PARAMETER TEST SET
100 nF
TZA3023
OM5803
PATTERN
GENERATOR
223-1 PRBS
C IN
D
C C
Fig.16 Electrical test circuit.
Page 15
2000 Mar 29 15
Philips Semiconductors Product specification
SDH/SONET STM4/OC12 transimpedance amplifier
TZA3023
handbook, full pagewidth
MCD903
Zo = 50
IPhoto
PIN
DREF
DIN
DINQ
0 dBm/1300
Laser
IN OUT
OPTICAL
INPUT
OUT
OUTQ
TRD
V
CC
100 nF
22 nF
10 nF
10%90%
DatainClock
in
ERROR DETECTOR
TR
1 2
100 nF
TZA3023
TZA3001
OM5804OM5802
PATTERN
GENERATOR
LASER DRIVER
OPTICAL ATTENUATOR
LIGHTWAVE MULTIMETER
622.080 MHz
2
23
-1 PRBS
C IN
D
C C
9.54 dBm
SAMPLING
OSCILLOSCOPE/
TDR/TDT
Fig.17 Optical test circuit.
Page 16
2000 Mar 29 16
Philips Semiconductors Product specification
SDH/SONET STM4/OC12 transimpedance amplifier
TZA3023
handbook, full pagewidth
MCD904
Fig.18 Differential output with 30 dBm optical input power [input current of 1.63 µA (p-p)].
handbook, full pagewidth
MCD905
Fig.19 Differential output with 20 dBm optical input power [input current of 16.3 µA (p-p)].
Page 17
2000 Mar 29 17
Philips Semiconductors Product specification
SDH/SONET STM4/OC12 transimpedance amplifier
TZA3023
handbook, full pagewidth
MCD906
Fig.20 Differential output with 10 dBm optical input power [input current of 163 µA (p-p)].
handbook, full pagewidth
MCD907
Fig.21 Differential output with 2 dBm optical input power [input current of 1030 µA (p-p)].
Page 18
2000 Mar 29 18
Philips Semiconductors Product specification
SDH/SONET STM4/OC12 transimpedance amplifier
TZA3023
BONDING PAD LOCATIONS
Note
1. All coordinates are referenced, in µm, to the bottom left-hand corner of the die.
SYMBOL PAD
COORDINATES
(1)
xy
DREF 1 95 881 GND 2 95 618 GND 3 95 473 IPhoto 4 95 285 GND 5 215 95 GND 6 360 95 GND 7 549 95 GND 8 691 95 OUT 9 785 501 OUTQ 10 785 641 V
CC
11 567 1055
V
CC
12 424 1055
AGC 13 259 1055
TZA3023U
1
10
9
2
3
4
5
0
x
y
0
13
12
11
67
8
1300
µm
1030
µm
DREF
IPhoto
GND
GND
OUTQ
OUT
MCD897
GND
GND
AGC
VCCV
CC
GND
GND
Fig.22 Bonding pad locations of the TZA3023U.
Physical characteristics of the bare die
PARAMETER VALUE
Glass passivation 2.1 µm PSG (PhosphoSilicate Glass) on top of 0.65 µm oxynitride Bonding pad dimension minimum dimension of exposed metallization is 90 × 90 µm (pad size = 100 × 100 µm) Metallization 1.22 µm W/AlCu/TiW Thickness 380 µm nominal Size 1.03 × 1.30 mm (1.34 mm
2
) Backing silicon; electrically connected to GND potential through substrate contacts Attach temperature <440 °C; recommended die attach is glue Attach time <15 s
Page 19
2000 Mar 29 19
Philips Semiconductors Product specification
SDH/SONET STM4/OC12 transimpedance amplifier
TZA3023
PACKAGE OUTLINE
UNIT
A
max.
A1A2A
3
b
p
cD
(1)E(2)
(1)
eHELLpQZywv θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC EIAJ
mm
inches
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
1.27
6.2
5.8
1.05
0.7
0.6
0.7
0.3
8 0
o o
0.25 0.10.25
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
1.0
0.4
SOT96-1
X
w M
θ
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v M
A
(A )
3
A
4
5
pin 1 index
1
8
y
076E03 MS-012
0.069
0.010
0.004
0.057
0.049
0.01
0.019
0.014
0.0100
0.0075
0.20
0.19
0.16
0.15
0.050
0.244
0.228
0.028
0.024
0.028
0.012
0.010.010.041 0.004
0.039
0.016
0 2.5 5 mm
scale
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
97-05-22 99-12-27
Page 20
2000 Mar 29 20
Philips Semiconductors Product specification
SDH/SONET STM4/OC12 transimpedance amplifier
TZA3023
SOLDERING Introduction to soldering surface mount packages
Thistextgives a very brief insight toacomplextechnology. A more in-depth account of soldering ICs can be found in our
“Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011). There is no soldering method that is ideal for all surface
mount IC packages. Wavesoldering is notalways suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used.
Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied tothe printed-circuit board by screenprinting, stencilling or pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C.
Wave soldering
Conventional single wave soldering is not recommended forsurfacemountdevices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically developed.
If wave soldering is used the following conditions must be observed for optimal results:
Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.
For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
Forpackageswithleads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.
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Suitability of surface mount IC packages for wave and reflow soldering methods
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the
“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”
.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
PACKAGE
SOLDERING METHOD
WAVE REFLOW
(1)
BGA, LFBGA, SQFP, TFBGA not suitable suitable HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable
(2)
suitable
PLCC
(3)
, SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended
(3)(4)
suitable
SSOP, TSSOP, VSO not recommended
(5)
suitable
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DATA SHEET STATUS
Note
1. Please consult the most recently issued data sheet before initiating or completing a design.
DATA SHEET STATUS
PRODUCT
STATUS
DEFINITIONS
(1)
Objective specification Development This data sheet contains the design target or goal specifications for
product development. Specification may change in any manner without notice.
Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be
published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Product specification Production This data sheet contains final specifications. Philips Semiconductors
reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
DEFINITIONS Short-form specification The data in a short-form
specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook.
Limiting values definition  Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device attheseor at any other conditionsabovethosegiven in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information  Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make norepresentationorwarrantythatsuch applications will be suitable for the specified use without further testing or modification.
DISCLAIMERS Life support applications These products are not
designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personalinjury. Philips Semiconductorscustomersusingorsellingtheseproducts for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes  Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for theuseofany of these products, conveys no licence ortitle under any patent, copyright, or mask work right to these products,and makes no representations orwarrantiesthat these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
BARE DIE DISCLAIMER
All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a periodof ninety (90) daysfrom the dateof Philips' delivery. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post packing tests performed on individual die or wafer. Philips Semiconductorshas no control of thirdparty procedures in the sawing, handling, packing or assembly of the die. Accordingly, Philips Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used.
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NOTES
Page 24
© Philips Electronics N.V. SCA All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Internet: http://www.semiconductors.philips.com
2000
69
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Printed in The Netherlands 403510/200/02/pp24 Date of release: 2000 Mar 29 Document order number: 9397 750 06816
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