Page 1
INTEGRATED CIRCUITS
DATA SH EET
TZA3014
2.5 Gbits/s postamplifier with level
detector
Product specification
Supersedes data of 2000 Aug 09
File under Integrated Circuits, IC19
2001 Jun 25
Page 2
Philips Semiconductors Product specification
2.5 Gbits/s postamplifier with level detector TZA3014
FEATURES
• Single 3.3 V power supply
• Wideband operation from 50 kHz to 2.5 GHz (typical
value)
• Fully differential
• On-chip DC-offset compensation without external
capacitor
• Interfacing with supplied positive or negative logic
• PositiveEmitterCoupledLogic (PECL)orCurrent-Mode
Logic (CML) compatible data outputs adjustable from
200 to 800 mV (p-p) single-ended
• Power-down capability for unused output or detector
• Rise and fall times of 80 ps (typical value)
• Inverted output possible
• Inputlevel detection circuit forReceived Signal Strength
Indicator (RSSI) and Loss Of Signal (LOS),
programmable from 0.4 to 400 mV (p-p) single-ended,
with open-drain comparator output for directly
interfacing positive or negative logic
• Reference voltage for output level and LOS adjustment
• HTQFP32 and HBCC32 plastic packages with exposed
pad
• Mute input.
APPLICATIONS
• Postamplifier for SDH/SONET transponder
• SDH/SONET wavelength converter
• PECL driver
• Fibre channel arbitrated loop
• Signal level detectors
• Swing converter CML 200 mV (p-p) to
PECL 800 mV (p-p)
• 2.5 GHz clock amplification.
GENERAL DESCRIPTION
The TZA3014 is a low gain postamplifier with a LOS
detectorand a RSSIdesigned for use in critical signal path
control applications, such as loop-through or Wavelength
DivisionMultiplexing (WDM). The signalpath is capable of
operating from 50 kHz up to 2.5 GHz.
The TZA3014 canbe delivered in HTQFP32 andHBCC32
packages and as bare die.
ORDERING INFORMATION
TYPE
NUMBER
TZA3014HT HTQFP32 plastic, heatsink thin quad flat package; 32 leads; body 5 × 5 × 1.0 mm SOT547-2
TZA3014VH HBCC32 plastic, heatsink bottom chip carrier; 32 terminals; body 5 × 5 × 0.65 mm SOT560-1
TZA3014U − bare die; 2.22 × 2.22 × 0.28 mm −
NAME DESCRIPTION VERSION
PACKAGE
2001 Jun 25 2
Page 3
Philips Semiconductors Product specification
2.5 Gbits/s postamplifier with level detector TZA3014
BLOCK DIAGRAM
handbook, full pagewidth
GNDA
LOSTH
LEVEL
INV
V
CCA
INQ
V
CCA
TEST
MUTE
32 (40)
10 (12)
12 (15)
29 (37)
1
2
IN
3
4
15 (19)
31 (39)
disable LOS output
RSSI
TZA3014
comparator
1×
cross-over
switch
offset compensationoffset compensation
level
buffer
BAND GAP
REFERENCE
5 kΩ
amplifier
(31) 25
(35) 27
(34) 26
(30) 24
(29) 23
(28) 22
(27) 21
(17) 14
MGU122
GNDB
LOS
RSSI
V
CCB
OUT
OUTQ
V
CCB
V
ref
The numbers in parentheses refer to the pad numbers of the bare die version.
Fig.1 Block diagram.
2001 Jun 25 3
Page 4
Philips Semiconductors Product specification
2.5 Gbits/s postamplifier with level detector TZA3014
PINNING
SYMBOL PIN PAD TYPE
V
CCA
1 1 S supply voltage for input and LOS detector
(1)
DESCRIPTION
IN 2 2 I differential input; complimentary to pin INQ; DC bias level is set internally
at approximately V
− 0.33 V
CC
INQ 3 3 I differential input; complimentary to pin IN; DC bias level is set internally at
V
CCA
approximately V
4 4 S supply voltage for input and LOS detector
− 0.33 V
CC
n.c. − 5 − not connected
n.c. − 6 − not connected
n.c. 5 7 − not connected
n.c. 6 8 I not connected
n.c. 7 9 I not connected
n.c. 8 10 S not connected
n.c. 9 11 S not connected
LOSTH 10 12 I input for setting threshold level of LOS detector; threshold level is set by
connecting external resistors between pins V
CCA
and V
; when forced to
ref
GNDA or not connected, the LOS detector is switched off
n.c. 11 13 I not connected
n.c. − 14 − not connected
LEVEL 12 15 I input for setting AC level of the output circuit; output signal level is set by
connecting external resistors between pins V
V
or not connected, pins OUT and OUTQ will be switched off
CCA
CCA
and V
; when forced to
ref
n.c. 13 16 I not connected
V
ref
14 17 O reference voltage for programming output level circuit and LOS threshold;
typical value is VCC− 1.6 V; no external capacitor allowed
n.c. − 18 − not connected
TEST 15 19 I for test purposes only; to be left open-circuit in the application
n.c. 16 20 S not connected
n.c. 17 21 S not connected
n.c. 18 22 O not connected
n.c. 19 23 O not connected
n.c. 20 24 S not connected
n.c. − 25 − not connected
n.c. − 26 − not connected
V
CCB
21 27 S supply voltage for output circuit
OUTQ 22 28 O PECL or CML compatible differential output; complimentary to pin OUT
OUT 23 29 O PECL or CML compatible differential output; complimentary to pin OUTQ
V
CCB
24 30 S supply voltage for output circuit
GNDB 25 31 S ground for output circuit
n.c. − 32 O not connected
n.c. − 33 O-DRN not connected
2001 Jun 25 4
Page 5
Philips Semiconductors Product specification
2.5 Gbits/s postamplifier with level detector TZA3014
SYMBOL PIN PAD TYPE
(1)
DESCRIPTION
RSSI 26 34 O RSSI output
LOS 27 35 O-DRN output of LOS detector; direct drive to either positive or negative supplied
logic via internal 5 kΩ resistor
n.c. 28 36 TTL not connected
INV 29 37 TTL input to invert the signal at pins OUT and OUTQ; supports positive or
negative logic
n.c. 30 38 TTL not connected
MUTE 31 39 TTL input to mute the output signal on pins OUT (‘0’) and OUTQ (‘1’); supports
positive or negative logic
GNDA 32 40 S ground for input and LOS detector
GNDp pad − S ground pad (exposed die pad)
Note
1. Pin type abbreviations: O = output, I = input, S = power supply, TTL = logic input and O-DRN = open-drain output.
handbook, full pagewidth
GNDA
32
MUTE
31
n.c.
30
INV
29
n.c.
28
LOS
27
RSSI
26
GNDB
25
1
V
CCA
2
V
INQ
CCA
n.c.
n.c.
n.c.
n.c.
IN
3
4
5
6
7
8
9
n.c.
exposed pad
TZA3014HT
11
10
n.c.
LOSTH
12
LEVEL
13
n.c.
GNDp
14
ref
V
Fig.2 Pin configuration HTQFP32 package.
15
TEST
16
n.c.
24
23
22
21
20
19
18
17
MGU123
V
CCB
OUT
OUTQ
V
CCB
n.c.
n.c.
n.c.
n.c.
2001 Jun 25 5
Page 6
Philips Semiconductors Product specification
2.5 Gbits/s postamplifier with level detector TZA3014
handbook, full pagewidth
GNDA
MUTE
n.c.
INV
n.c.
LOS
RSSI
GNDB
V
V
CCA
CCA
1 3231302928272625
IN
INQ
2
3
exposed pad
4
n.c.
n.c.
n.c.
n.c.
5
6
7
8
9
n.c.
TZA3014VH
10 11 12 13 14 15
n.c.
LOSTH
n.c.
LEVEL
GNDp
ref
V
16
TEST
n.c.
Fig.3 Pin configuration HBCC32 package.
24
23
22
21
20
19
18
17
V
CCB
OUT
OUTQ
V
CCB
n.c.
n.c.
n.c.
n.c.
MGU124
2001 Jun 25 6
Page 7
Philips Semiconductors Product specification
2.5 Gbits/s postamplifier with level detector TZA3014
FUNCTIONAL DESCRIPTION
The TZA3014 is a postamplifier with a RSSI circuit to
provide output signals for RSSI and LOS (see Fig.1). The
input signal can be amplified to a programmable level.
An active level control circuit ensures this level. The
control voltage on pin INV inverts the outputs, so avoiding
arequiredcomplicatedPrintedCircuit Board (PCB) layout.
An offset compensation circuit minimizes the effect of any
voltage offset present at the input.
The RSSI and LOS detector are based on a 7-stage
‘successive detection’ circuit which provides a logarithmic
output. The LOS detector is followed bya comparator with
aprogrammablethreshold.Theinputsignalleveldetection
is implemented to check if the input signal is above the
user-programmedlevel. The usercan ensure that datawill
only be transmitted when the input signal-to-noise ratio is
sufficient for low bit error rate system operation. A second
offset compensation circuit minimizes the effect of any
voltage offset present in the logarithmic amplifier.
RF input circuit
The input circuit contains internal 50 Ω resistors
decoupled to V
via an internal common mode 12 pF
CCA
capacitor (see Fig.4).
The inputs IN and INQ are DC-biased at approximately
V
− 0.33 V by an internal reference generator. The
CCA
TZA3014 can be DC-coupled, but AC coupling is
preferred. When DC-coupled, the drive source must
operate within the allowable input range
(V
− 1.0 V to V
CCA
+ 0.3 V). The DC-offset voltage
CCA
should stay below a few millivolts since the internal
DC-offset compensation circuit has a limited correction
range. When AC-coupled, do not use capacitors that
cause a 3 dB cut-off point at 50 kHz (postamplifier cut-off
point) or at 1 MHz (RSSI cut-off point).
RF output circuit
Matching the outputs of the postamplifier (seeFig.5) is not
mandatory. In most applications, the receiving end of the
transmission line will be properly matched, causing very
few reflections.
Matching the transmitting end of the transmission line to
absorb reflections only, is recommended for verysensitive
applications.
handbook, halfpage
IN
INQ
12 pF
420 Ω
50 Ω50 Ω
V
CCA
GNDA
MGU125
Fig.4 RF input circuit.
RF output level adjustment
The output level can be made compatible with CML or
PECL by adjusting the voltage on pin LEVEL. The
DC voltages on pins OUT and OUTQ relate to the
DC voltage on pin LEVEL. Due to the effect of the 50 Ω
load resistance at the receiving end, for a given
peak-to-peak value on pins OUT and OUTQ, a different
voltage is required on pin LEVEL in case the output is
AC-coupled and when the output is DC-coupled
(see Figs 5 and 6).
When pin LEVEL is not connected or connected to V
CCA
the postamplifier is in power-down state (see Fig.5).
DC-offset compensation loop
A DC-offset compensation loop connected between the
amplifier output and the buffer input maintains the toggle
point at the buffer input when there is no input signal
(see Fig.1). This active control circuit is integrated and
does not require an external capacitor. The loop
time constant determines the lower cut-off frequency of
the amplifier chain, and is internally fixed at approximately
5 kHz.
,
In such cases, 100 Ω pull-up resistors should be
connected to V
and pins OUT and OUTQ as close as
CCB
possible to the IC. However, for most applications these
matching resistors are not required.
2001 Jun 25 7
Page 8
Philips Semiconductors Product specification
2.5 Gbits/s postamplifier with level detector TZA3014
handbook, full pagewidth
V
= 0.5 × V
LEVEL
V
LEVELVref
V
LEVEL=VCC
V
4
CCA
R1
12 (15)
LEVEL
R2
V
14 (17)
ref
.
o(se)(p-p)
R1
×=
---------------------R1 R2+
for power-down mode.
V
LEVEL
100 Ω
REG
The numbers in parentheses refer to the pad numbers of the bare die version.
a. DC-coupled.
(27) 21
100 Ω
(29) 23
(28) 22
V
CCB
OUT
OUTQ
V
V
CC
LEVEL
V
o
(V)
V
o
Transmission
lines
50
Ω
V
o(se)(p-p)
MGU126
50
Ω
handbook, full pagewidth
V
= 1.5 × V
LEVEL
V
LEVELVref
V
LEVEL=VCC
V
CCA
4
R1
12 (15)
LEVEL
R2
V
14 (17)
ref
.
o(se)(p-p)
R1
×=
---------------------R1 R2+
for power-down mode.
V
LEVEL
100 Ω
REG
The numbers in parentheses refer to the pad numbers of the bare die version.
b. AC-coupled.
Fig.5 RF output configurations.
(27) 21
100 Ω
(29) 23
(28) 22
V
CCB
OUT
OUTQ
V
V
CC
LEVEL
V
o
(V)
V
o
Transmission
lines
50
Ω
V
o(se)(p-p)
MGU127
50
Ω
2001 Jun 25 8
Page 9
Philips Semiconductors Product specification
2.5 Gbits/s postamplifier with level detector TZA3014
handbook, full pagewidth
V
o(se)(p-p)
(mV)
1000
800
DC-coupled AC-coupled
600
400
200
0
0 100
20 40 60 80
V
LEVEL
Fig.6 Output signal as a function of V
(% of V
LEVEL
MGU128
)
ref
.
TTL logic inputs MUTE and INV
It should be noted that switch control voltages in positive
logicare inverted in case anegativesupply voltage is used
(see Fig.7).
Output signal as a function of inputs MUTE and INV
The default logic level for inputs MUTE and INV is 0 in
case these pins are not connected. See Tables 1 and 2.
2001 Jun 25 9
Table 1 OUT and OUTQ as a function of input MUTE
MUTE OUT OUTQ
0 IN INQ
1 ‘0’ ‘1’
Table 2 OUT and OUTQ as a function of input INV
INV OUT OUTQ
0 IN INQ
1 INQ IN
Page 10
Philips Semiconductors Product specification
2.5 Gbits/s postamplifier with level detector TZA3014
handbook, full pagewidth
handbook, full pagewidth
logic
level
1
2.0 V
2.0 V
(1)
TTL
0.8 V
0
GND
−10
1.4 V
+1 +2 +3 +4
a. Positive supply voltage (VCC) and positive input voltage (VCC).
logic
level
1
2.0 V
0.8 V
1.4 V
V
CC
+5 +6
2.0 V
(1)
TTL
0.8 V
0
V
−4 −3 −2 −10
1.4 V
EE
0.8 V
1.4 V
GND
+1 +2 +3
VI (V)
VI (V)
MGS560
MGS559
V
CC
b. Negative supply voltage (VEE) and positive input voltage (VCC).
handbook, full pagewidth
logic
level
2.0 V
1
(1)
TTL
0.8 V
0
V
−4 −3 −2 −10
c. Negative supply voltage (VEE) and negative input voltage (VEE).
(1) Level not defined.
Fig.7 Logic levels on pins MUTE and INV as a function of the supply voltages.
2001 Jun 25 10
1.4 V
EE
GND
2.0 V
0.8 V
1.4 V
+1 +2 +3
MGS558
VI (V)
Page 11
Philips Semiconductors Product specification
2.5 Gbits/s postamplifier with level detector TZA3014
RSSI and LOS detection
The TZA3014 monitors the level of the input AC signal.
Thisfunction can prevent the outputcircuitfrom reacting to
noise in casethere is no valid inputsignal, and can ensure
that only data is transmitted when there is sufficient input
signal for low bit error rate system operation.
The RSSI uses seven limiting amplifiers in a ‘successive
detection’ topology to closely approximate a logarithmic
response over a total range of 70 dB. The AC signal is
full-wave rectified by a detector at each amplifier stage.
Each detector output has a current driver followed by a
low-pass filter providing the first stage in the recovery of
the average value of the demodulated input signal. The
total current from each detector output is converted to a
voltage by an internal load resistor and then buffered.
When the RSSI output is used, input pin LOSTH is not to
be connected to GND (standby mode). The RSSI output
follows the internal 3 dB hysteresis of the LOS
comparator. The LOS comparator detects when the input
signal level rises above a programmable fixed threshold.
Then pin LOS gets a LOW-level. The threshold level is
determined by the voltage on pin LOSTH and by the level
of the input AC signal (see Fig.8). A filter with a nominal
timeconstant of 1 µs preventsnoise spikes from triggering
the level detector.
The LOS comparator has an internal 3 dB hysteresis and
drives an open-drain circuit with a 5 kΩ internal resistor
allowing it to directly interface positive or negative logic
circuits (see Fig.9).
handbook, halfpage
V
(1) PRBS pattern input signal with a frequency <1 GHz.
(2) Linearity error typically 0.5 dB.
(3) ϕ =1/
3
10
i(se)(p-p)
(mV)
2
10
V
10
CC
12.5
10
1
−1
10
−0.16
dB/mV.
LOS
LOW-level
(3)
−0.48 V
CC
Fig.8 Loss of signal assert level.
(1)
(2)
LOS
HIGH-level
50
V
LOSTH
V
−0.8V
CC
6020 40
(% of V
V
RSSI
MGU129
ref
CC
(V)
7030
)
−1.12
Its response isindependent of the input signalpolarity due
to the circuit design and to the demodulating action of the
detector which transforms the alternating input voltage to
a rectified and filtered quasi DC output signal. The
logarithmic voltage slope of the TZA3014 is
ϕ =1/
dB/mVandmostlyisindependentoftemperature
12.5
and supply voltage due to four feedback loops in the
reference circuit. The LOS detector output voltage is
derived from V
ref
.
The sensitivity of the LOS detector is affected by the RMS
value of the input signal which, in its turn, depends on the
frequency.
V
can be calculated using the following formula:
LOSTH
V
LOSTH=VRSSI
V
0.458 S
CC
where S
RSSI
=
20 log
×–+
RSSI
in [mV/dB]; V
V
i(p-p)
------------------- -
26E 8–
, V
LOSTH
RSSI
and V
i(p-p)
(1)
in [V].
2001 Jun 25 11
Example: a 200 mV (p-p) single-ended 1.2 GB/s PRBS
input signal will have a V
voltage of VCC− 1.013 V.
RSSI
If the offset voltage of the first stage increases above a
certain level, the high DC gain of the amplifier circuit will
cause successive stages to limit prematurely. This is
prevented by the LOS detector offset control loop which
extends the lower end of the amplifier’s dynamic range.
The offset isautomatically and continuously compensated
by a feedback path from the last stage. An offset at the
output of the logarithmic converter is equivalent to a
change of amplitude at the input.
UsingDC-coupling, with signal absence, andVINnotequal
to V
(mute), the LOS detector detects full signal. Only
INQ
verysmallsignals with an average valueequaltozero, can
result into a zero output.
Page 12
Philips Semiconductors Product specification
2.5 Gbits/s postamplifier with level detector TZA3014
handbook, halfpage
a. Positive supply and positive logic.
VCC− VEE<7V.
VCC− VEE<7V.
TZA3014
5 kΩ
LOS
GNDA
MGU132
handbook, halfpage
c. Negative supply and negative logic.
V
56 kΩ
I
LOS
GND
TZA3014
CC
5 kΩ
handbook, halfpage
GND
LOS
GNDA
MGU130
V
CC
TZA3014
LOS
5 kΩ
GNDA
5.6 kΩ
MGU131
I
LOS
V
EE
b. Negative supply and positive logic.
GND
56 kΩ
I
LOS
V
EE
Fig.9 Loss of signal output pin LOS.
Supply current
For the supply current I
, see Fig.10.
CCB
Using a positive supply voltage
Although the TZA3014 has been designed to use a single
+3.3 V supply voltage (see Fig.11), some care should be
taken with respect to RF transmission lines. The on-chip
signals refer to the various VCCpins. The external
transmission lines will most likely be referred to the
pins GNDA and GNDB, being the system ground.
The RF signals will change from one reference plane to
another when interfacing the RF inputs and outputs.
A positive supply application is very vulnerable to
interference with respect to this point. For a successful
+3.3 V application, special care should be taken when
designing the PCB layout in order to reduce the influence
of interference and to keep the positive supply voltage as
clean as possible.
(1)
(V)
I
(1) T
CCB
(mA)
amb
60
50
40
30
20
17
10
5
0
0 0.80.2
=25°C.
0.5
V
o(se)(p-p)
Fig.10 Supply current as a function of the output
voltage.
1
MGU133
2001 Jun 25 12
Page 13
Philips Semiconductors Product specification
2.5 Gbits/s postamplifier with level detector TZA3014
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL PARAMETER MIN. MAX. UNIT
V
CC
V
n
I
n
P
tot
T
stg
T
j
T
amb
supply voltage −0.5 +5.5 V
DC voltage
pins IN, INQ, LOSTH, LEVEL, V
V
and V
CCA
CCB
, TEST, OUTQ, OUT, GNDp,
ref
−0.5 VCC+ 0.5 V
pins LOS, INV and MUTE −0.5 +7 V
DC current
pins IN and INQ −20 +20 mA
pins LOSTH and LEVEL 0 14 µA
pins V
, TEST and LOS −1+1mA
ref
pins OUT and OUTQ −30 +30 mA
pins INV and MUTE 0 20 µA
total power dissipation − 0.6 W
storage temperature −65 +150 °C
junction temperature − 150 °C
ambient temperature −40 +85 °C
THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS VALUE UNIT
R
th(j-s)
thermal resistance from junction to
note 1 15 K/W
solder point (exposed die pad)
R
th(j-a)
R
th(s-a)
R
th(s-a)(req)
thermal resistance from junction to
ambient
thermal resistance from solder point to
ambient (exposed die pad)
required thermal resistance from
solder point to ambient
1s2p multi-layer test board; notes 1
33 K/W
and 2
1s2p multi-layer test board; notes 1
18 K/W
and 2
LOS detector switched on
V
= 200 mV (p-p) single-ended 130 K/W
o
V
= 800 mV (p-p) single-ended 75 K/W
o
Notes
1. JEDEC standard.
2. HTQFP32 and HBCC32 packages.
2001 Jun 25 13
Page 14
Philips Semiconductors Product specification
2.5 Gbits/s postamplifier with level detector TZA3014
CHARACTERISTICS
Typical values at T
temperature range and supply voltage range; all voltages referenced to ground; note 1; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
=25°C and VCC= 3.3 V; minimum and maximum values are valid over the entire ambient
amb
Supply (pins V
V
CC
I
CCA
CCA
and V
CCB
)
supply voltage 3.13 3.3 3.47 V
supply current A LOS detector power-down 14 24 34 mA
LOS detector switched on 24 40 56 mA
I
CCB
supply current B amplifier power-down 2 6 10 mA
V
= 200 mV (p-p)
o
single-ended
V
= 800 mV (p-p)
o
single-ended
P
tot
total power dissipation power-down 60 100 240 mW
= 200 mV (p-p)
V
o
single-ended
V
= 800 mV (p-p)
o
single-ended
TC temperature coefficient LOS detector switched on;
I
CCA
= 800 mV (p-p)
V
o
single-ended; I
T
j
T
amb
junction temperature −40 − +125 °C
ambient temperature −40 +25 +85 °C
CCB
RF inputs in general (PECL or CML input pins IN and INQ)
V
V
I(bias)
I
DC input bias voltage VCC− 0.4 VCC− 0.33 VCC− 0.28 V
DC and AC input window
note 2 VCC− 1.0 − VCC+ 0.3 V
voltage
R
i
C
i
input resistance single-ended 35 50 70 Ω
input capacitance single-ended; note 2 0.6 0.8 1.2 pF
Cross-over switch and postamplifier
11 17 24 mA
43 60 77 mA
120 190 270 mW
250 330 450 mW
−80 −50 −30 µA/K
−50 −30 −15 µA/K
PECL OR CML INPUT PINS IN AND INQ
V
i(p-p)
α
OS(red)
input voltage swing
(peak-to-peak value)
input offset reduction Vo= 200 mV (p-p)
single-ended; notes 2
and 3
50 − 500 mV
3.8 9 13.5 dB
single-ended; note 4
V
= 800 mV (p-p)
o
6 1422dB
single-ended; note 4
V
io(cor)
input offset voltage
single-ended −10 − +10 mV
correction range
(peak-to-peak value)
V
n(i)(eq)(rms)
equivalent input noise
voltage (RMS value)
Vo= 800 mV (p-p)
single-ended; note 2
− 75 170 µV
Fn noise factor note 2 − 512dB
2001 Jun 25 14
Page 15
Philips Semiconductors Product specification
2.5 Gbits/s postamplifier with level detector TZA3014
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
BUFFER AND AMPLIFIER
G
v
f
D
f
−3dB(l)
f
−3dB(h)
t
PD
∆t
PD
J total jitter 20 bits of the 28.5 kbits
α
ct
PECL OR CML OUTPUTS (PINS OUT AND OUTQ)
V
o(se)(p-p)
TC
Vo
t
r
t
f
R
o
C
o
LEVEL CONTROL INPUT (PIN LEVEL)
V
i
R
i
SWITCH CIRCUIT
t
a
t
d
TTL INPUT PINS MUTE AND INV
V
IL
V
IH
R
i
I
i
small signal voltage gain Vo= 200 mV (p-p)
9 1520dB
single-ended; note 5
V
= 800 mV (p-p)
o
21 29 34 dB
single-ended; note 5
signal path data rate notes 6 and 7 − 2.5 − Gbits/s
low −3 dB cut-off
note 2 2 5 10 kHz
frequency DC
compensation
high −3 dB cut-off
− 2.0 − GHz
frequency
propagation delay note 2 150 200 250 ps
propagation delay
difference
at the same signal levels;
note 2
− 05ps
− 8 − ps
pattern; notes 2 and 8
crosstalk note 9 − 110 − dB
single-ended output
50 Ω load 200 − 800 mV
voltage
(peak-to-peak value)
temperature coefficient
−10 +1 mV/K
output voltage
rise time 20% to 80%; notes 6 and 8 − 80 − ps
fall time 80% to 20%; notes 6 and 8 − 80 − ps
output resistance single-ended 70 100 130 Ω
output capacitance single-ended; note 2 0.6 0.8 1.2 pF
input voltage VCC− V
input resistance referenced to V
CC
200 350 600 kΩ
− V
ref
CC
V
assert time multiplexer and inverter − 100 − ns
de-assert time multiplexer and inverter − 80 − ns
LOW-level input voltage positive logic; note 10 −0.3 − +0.8 V
HIGH-level input voltage positive logic; note 10 2 − VCC+ 0.8 V
input resistance referenced to GNDA 100 180 400 kΩ
input current −40 − +40 µA
2001 Jun 25 15
Page 16
Philips Semiconductors Product specification
2.5 Gbits/s postamplifier with level detector TZA3014
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
RSSI and LOS detector
PECL OR CML INPUT PINS IN AND INQ
V
i(p-p)
input voltage swing
(peak-to-peak value)
α
OS(red)
V
io(cor)
input offset reduction notes 2 and 4 25 40 50 dB
on-chip DC-offset
compensation correction
range
RSSI CIRCUIT
f
−3dB(l)
low −3 dB cut-off
frequency
f
−3dB(h)
high −3 dB cut-off
frequency
DR dynamic range 57 60 63 dB
S
TC
RSSI
sens
RSSI sensitivity 50 MHz, square; note 11 10 12.5 15 mV/dB
temperature coefficient
sensitivity
LE linearity error see Fig.8; note 2 − 0.5 1 dB
LOS
DETECTOR
hys
LOS
t
a
t
d
LOS hysteresis input signal waveform
assert time note 2 −−5µs
de-assert time note 2 −−5µs
INPUT PIN LOSTH
V
i
R
i
input voltage 0 − V
input resistance referenced to GNDA 150 350 600 kΩ
OUTPUT PIN LOS
I
o(sink)
R
o
output sink current −−1mA
output resistance internal output series
single-ended 0.4 − 400 mV
peak-to-peak value;
−5 − +5 mV
single-ended
0.5 1 2 MHz
note 11 1.5 2 2.5 GHz
620 MHz, square; note 11 10 12 14 mV/dB
1.2 GHz, square; note 11 9 11 13.5 mV/dB
100 MB/s PRBS (2
31
− 1);
9 12.5 15 mV/dB
note 11
1.2 GB/s PRBS (2
31
− 1);
10 12 14.5 mV/dB
note 11
2.4 GB/s PRBS (2
− 1);
10 12 14 mV/dB
31
note 11
−20 +2µV/dBK
2.0 3.0 4.0 dB
dependent
CC
V
3.5 5 6.5 kΩ
resistance
2001 Jun 25 16
Page 17
Philips Semiconductors Product specification
2.5 Gbits/s postamplifier with level detector TZA3014
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
UTPUT PIN RSSI
O
V
o
I
o
output voltage VCC− 1.2 − V
output current −1 − +1 mA
Band gap reference circuit
CC
V
OUTPUT PIN V
V
ref
C
ext
ref
reference voltage VCC− 1.85 VCC− 1.6 VCC− 1.45 V
allowed external
−−10 pF
capacitance
I
o(sink)
output sink current −−500 µA
Notes
1. It is assumed that both CML inputs carry a complementary signal with the specified peak-to-peak value (true
differential excitation).
2. Guaranteed by design.
3. Minimum signal with limiting output.
G
V
------
AC
=
----------G
DC
o
V
i
4. α
5. G
OS(red)
=
V
6. Based on −3 dB cut-off frequency and rise/fall time.
7. Low limit can go as low as DC if the input signal overrides the input offset voltage correction range.
8. V
= 100 mV (p-p) single-ended, Vo= 800 mV (p-p) single-ended.
i
9. Crosstalk of IC only.
10. When using a negative supply voltage, positive or negative logic can be used. The values will be different, see Fig.7.
11. Sensitivity depends on the waveform and is therefore a function of −3 dB cut-off frequency;
see Section “RSSI and LOS detection”, Equation (1).
2001 Jun 25 17
Page 18
Philips Semiconductors Product specification
2.5 Gbits/s postamplifier with level detector TZA3014
APPLICATION INFORMATION
RF input and output connections
Striplines, or microstrips, with an odd mode characteristic
impedanceof Zo=50Ωhaveto be used for thedifferential
RF connections on the PCB. This applies to both signal
inputs and signal outputs. Each pair of lines should have
the same length.
Grounding and power supply decoupling
The PCB ground connection has to be a large area of
copper connected to a common ground plane with an
inductance as low as possible.
Tominimize low frequency switching noiseinthe vicinity of
theTZA3014,the power supply line should be filteredonce
using a beaded capacitor circuit having a low cut-off
frequency.
The exposed die pad GNDp connection on the PCB must
be a large area of copper to aid the transfer of heat from
the IC to the PCB (see Figs 11 and 12).
2001 Jun 25 18
Page 19
Philips Semiconductors Product specification
2.5 Gbits/s postamplifier with level detector TZA3014
handbook, full pagewidth
Boundary of 100 mm2 area
012345mm
RSSI
26
To central
GND decoupling
GNDB
25
1718192021222324
To central
GND decoupling
0603
MUTE
GNDA
323130
0603 0603
V
CCA
IN
INQ
V
CCA
87654321
INV
LOS
29
28
27
0603
V
CCB
OUT
OUTQ
V
CCB
VCCV
CC
GND
signal/GNDp
9
10
11
12
13
14
15
LOSTH
LEVEL
16
V
TEST
ref
06030603
0603
0603
060306030603
HTQFP
In order to enable heat flow out of the package, the following measures have to be taken:
(1) Solder the 3 × 3mm2 exposed die pad to a plane with maximum size.
(2) Add a plane with minimum 100 mm2 in an inner layer, surrounded by ground layers.
(3) Use maximum amount of vias to connect two planes.
(4) Use minimum of openings in heat transport area between hot plane and ground planes.
Fig.11 PCB layout for HTQFP package with positive supply voltage.
cross-section
MGU134
2001 Jun 25 19
Page 20
Philips Semiconductors Product specification
2.5 Gbits/s postamplifier with level detector TZA3014
handbook, full pagewidth
Boundary of 100 mm2 area
012345mm
To central
GND decoupling
0603
GNDA
MUTE
INV
31
30
32
0603 0603
V
CCA
IN
INQ
V
CCA
87654321
29
RSSI
LOS
28
27
26
GNDB
25
To central
GND decoupling
0603
V
CCB
OUT
OUTQ
V
CCB
1718192021222324
VCCV
CC
GND
signal/GNDp
9
10
11
12
13
14
15
LOSTH
LEVEL
16
V
TEST
ref
06030603
0603
0603
060306030603
HTQFP
In order to enable heat flow out of the package, the following measures have to be taken:
(1) Solder the 3 × 3mm2 exposed die pad to a plane with maximum size.
(2) Add a plane with minimum 100 mm2 in an inner layer, surrounded by ground layers.
(3) Use maximum amount of vias to connect two planes.
(4) Use minimum of openings in heat transport area between hot plane and ground planes.
Fig.12 PCB layout for HTQFP package with negative supply voltage.
cross-section
MGU136
2001 Jun 25 20
Page 21
Philips Semiconductors Product specification
2.5 Gbits/s postamplifier with level detector TZA3014
BONDING PAD INFORMATION
COORDINATES
SYMBOL PAD
xy
V
CCA
1 −928 +710
IN 2 −928 +553
INQ 3 −928 +396
V
CCA
4 −928 +239
n.c. 5 −928 +81
n.c. 6 −928 −81
n.c. 7 −928 −239
n.c. 8 −928 −396
n.c. 9 −928 −553
n.c. 10 −928 −710
n.c. 11 −707 −928
LOSTH 12 −550 −928
n.c. 13 −393 −928
n.c. 14 −236 −928
LEVEL 15 −79 −928
n.c. 16 +79 −928
V
ref
17 +236 −928
n.c. 18 +393 −928
TEST 19 +550 −928
n.c. 20 +707 −928
n.c. 21 +928 −710
n.c. 22 +928 −553
n.c. 23 +928 −396
n.c. 24 +928 −239
(1)
COORDINATES
(1)
SYMBOL PAD
xy
n.c. 25 +928 −81
n.c. 26 +928 +81
V
CCB
27 +928 +239
OUTQ 28 +928 +396
OUT 29 +928 +553
V
CCB
30 +928 +710
GNDB 31 +707 +928
n.c. 32 +550 +928
n.c. 33 +393 +928
RSSI 34 +236 +928
LOS 35 +79 +928
n.c. 36 −79 +928
INV 37 −236 +928
n.c. 38 −393 +928
MUTE 39 −550 +928
GNDA 40 −707 +928
Note
1. All x and y coordinates represent the position of the
centreof the pad in µmwithrespect to the centreofthe
die (see Fig.13).
2001 Jun 25 21
Page 22
Philips Semiconductors Product specification
2.5 Gbits/s postamplifier with level detector TZA3014
handbook, full pagewidth
INV
n.c.
x
0
y
TZA3014U
n.c.
n.c.
n.c.
0
LEVEL
LOS
n.c.
RSSI
ref
V
V
V
CCA
INQ
CCA
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
GNDA
MUTE
40 39 38 37 36 35 34 33 32 31
1
2
IN
3
4
5
6
7
8
9
10
11 12 13 14 15 16 17 18 19 20
n.c.
LOSTH
Fig.13 Bonding pad locations TZA3014U.
n.c.
n.c.
n.c.
TEST
GNDB
30
29
28
27
26
25
24
23
22
21
n.c.
V
CCB
OUT
OUTQ
V
CCB
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
MGU135
2001 Jun 25 22
Page 23
Philips Semiconductors Product specification
2.5 Gbits/s postamplifier with level detector TZA3014
PACKAGE OUTLINES
HTQFP32: plastic, heatsink thin quad flat package; 32 leads; body 5 x 5 x 1.0 mm
c
y
heathsink side
D
h
X
SOT547-2
1724
25
E
h
32
pin 1 index
b
p
e
81
w M
D
H
D
Z
D
0 2.5 5 mm
Z
16
e
9
B
E
b
scale
w M
p
v M
v M
A
H
E
E
A
B
A
2
A
A
1
detail X
(A )
3
θ
L
p
L
DIMENSIONS (mm are the original dimensions)
A
UNIT
mm
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT547-2
A1A2A3b
max.
0.15
1.2
0.05
p
1.05
0.95
0.27
0.25
0.17
IEC JEDEC EIAJ
(1)
ceLywvθ
D
0.20
5.1
0.09
4.9
(1)
E
D
h
5.1
3.1
4.9
2.7
REFERENCES
E
3.1
2.7
h
2001 Jun 25 23
0.5
HDH
7.1
6.9
7.1
6.9
(1)
E
L
0.75
0.45
p
0.08 0.080.21.0
EUROPEAN
PROJECTION
Z
Z
D
E
0.89
0.89
0.61
0.61
ISSUE DATE
99-06-15
(1)
7°
0°
Page 24
Philips Semiconductors Product specification
2.5 Gbits/s postamplifier with level detector TZA3014
HBCC32: plastic, heatsink bottom chip carrier; 32 terminals; body 5 x 5 x 0.65 mm
E
x
B
b
1
b
2
detail X
x
C
vA
ball A1
index area
C
B
e
e
D
1
A
SOT560-1
M
w
M
w
b
b
3
M
w
M
w
y
e
2
1
32
DIMENSIONS (mm are the original dimensions)
A
max.
0.80
A
1bA2
0.10
0.05
0.70
0.35
0.60
0.20
IEC JEDEC EIAJ
UNIT
mm
OUTLINE
VERSION
SOT560-1 MO-217
b
0.50
0.30
D
1
e
3
b
1
2
0.50
0.35
e4E
1
X
0 2.5 5 mm
scale
5.1
4.9
E
E
1
3.2
0.5
3.0
D
b
3
5.1
0.50
4.9
0.35
REFERENCES
D
3.2
3.0
1
e
4.2
A
1
A
2
A
we
v
e
1
2
4.2
4
3
4.15
4.15
EUROPEAN
PROJECTION
0.2
e
e
xy
0.15 0.15 0.05
ISSUE DATE
99-09-10
00-02-01
2001 Jun 25 24
Page 25
Philips Semiconductors Product specification
2.5 Gbits/s postamplifier with level detector TZA3014
SOLDERING
Introduction to soldering surface mount packages
Thistextgives a very brief insighttoacomplex technology.
A more in-depth account of soldering ICs can be found in
our
“Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certainsurfacemount ICs, but it is not suitableforfinepitch
SMDs. In these situations reflow soldering is
recommended.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuit board byscreenprinting, stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
Wave soldering
Conventional single wave soldering is not recommended
forsurfacemount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
• Forpackageswith leads on four sides, the footprintmust
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement andbefore soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
2001 Jun 25 25
Page 26
Philips Semiconductors Product specification
2.5 Gbits/s postamplifier with level detector TZA3014
Suitability of surface mount IC packages for wave and reflow soldering methods
PACKAGE
WAVE REFLOW
(1)
BGA, HBGA, LFBGA, SQFP, TFBGA not suitable suitable
SOLDERING METHOD
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS not suitable
(3)
PLCC
, SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended
(2)
(3)(4)
(5)
suitable
suitable
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the
“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”
.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wavesoldering isonly suitablefor SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DATA SHEET STATUS
PRODUCT
DATA SHEET STATUS
(1)
STATUS
(2)
DEFINITIONS
Objective data Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Preliminary data Qualification This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
Product data Production This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
2001 Jun 25 26
Page 27
Philips Semiconductors Product specification
2.5 Gbits/s postamplifier with level detector TZA3014
DEFINITIONS
Short-form specification The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
attheseor at any otherconditionsabovethose given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Application information Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentationorwarrantythat such applications will be
suitable for the specified use without further testing or
modification.
DISCLAIMERS
Life support applications These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductorscustomersusingorselling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
theuseof any of these products, conveys nolicenceortitle
under any patent, copyright, or mask work right to these
products,and makes no representations orwarrantiesthat
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Bare die All die are tested and are guaranteed to
comply with all data sheet limits up to the point of wafer
sawing for a period of ninety (90) days from the date of
Philips' delivery. If there are data sheet limits not
guaranteed, these will be separately indicated in the data
sheet. There are no post packing tests performed on
individual die or wafer. Philips Semiconductors has no
control of third party procedures in the sawing, handling,
packing or assembly of the die. Accordingly, Philips
Semiconductors assumes no liability for device
functionality or performance of the die or systems after
third party sawing, handling, packing or assembly of the
die. It is the responsibility of the customer to test and
qualify their application in which the die is used.
2001 Jun 25 27
Page 28
Philips Semiconductors – a w orldwide compan y
Argentina: see South America
Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,
Tel. +61 2 9704 8141, Fax. +61 2 9704 8139
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773
Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 68 9211, Fax. +359 2 68 9102
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Colombia: see South America
Czech Republic: see Austria
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,
Tel. +45 33 29 3333, Fax. +45 33 29 3905
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615 800, Fax. +358 9 6158 0920
France: 7 - 9 Rue du Mont Valérien, BP317, 92156 SURESNES Cedex,
Tel. +33 1 4728 6600, Fax. +33 1 4728 6638
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 2353 60, Fax. +49 40 2353 6300
Hungary: Philips Hungary Ltd., H-1119 Budapest, Fehervari ut 84/A,
Tel: +36 1 382 1700, Fax: +36 1 382 1800
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Indonesia: PT Philips Development Corporation,Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),
Tel. +39 039 203 6838, Fax +39 039 203 6800
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087
Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. +48 22 5710 000, Fax. +48 22 5710 001
Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. +27 11 471 5401, Fax. +27 11 471 5398
South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2451, Fax. +886 2 2134 2874
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
60/14 MOO 11, Bangna Trad Road KM. 3, Bagna, BANGKOK 10260,
Tel. +66 2 361 7910, Fax. +66 2 398 3447
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 3341 299, Fax.+381 11 3342 553
For all other countries apply to: Philips Semiconductors,
Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN,
The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
2001
Internet: http://www.semiconductors.philips.com
72
Printed in The Netherlands 403510/200/02/pp28 Date of release: 2001 Jun 25 Document order number: 9397 750 08203
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