Datasheet TLE6220GP Specification

Data Sheet TLE 6220 GP

FAULT

RESET

Smart Quad Low-Side Switch

Features Product Summary

• Short Circuit Protection

• Overtemperature Protection

• Overvoltage Protection

• 8 bit Serial Data Input and Diag-

nostic Output (SPI protocol)

• Direct Parallel Control of Four
Channels for PWM Applications

• Cascadable with Other Quad
Switches

• Low Quiescent Current

• µC Compatible Input

• Electostatic Discharge (ESD) Protection

• Green Product (RoHS compliant)

• AEC qualified

Application

• µC Compatible Power Switch for 12 V and 24 V Applications

• Switch for Automotive and Industrial System

• Solenoids, Relays and Resistive Loads

• Injectors

• Robotic controls

General Description

Quad Low-Side Switch in Smart Power Technology (SPT) with a Serial Peripheral Interface (SPI) and
four open drain DMOS output stages. The TLE 6220 GP is protected by embedded protection func­tions and designed for automotive and industrial applications. The output stages can be controlled
direct in parallel for PWM applications (injector coils), or through serial control via the SPI. Therefore
the TLE 6220 GP is particularly suitable for engine management and powertrain systems.

Block Diagram

Supply voltage VS 4.5 – 5.5 V
Drain source voltage V

DS(AZ) max

60 V
On resistance RON 0.32 Ω
Output current (all outp. ON equal) I

D(NOM)

1 A

(individually) 3 A

PG-DSO-20

PRG

VS

GND

IN1

IN2

IN3

IN4

SCLK
SI

CS

SO

as Ch. 1

as Ch. 1

as Ch. 1

8

Serial Interface

SPI

V2.2 Page 2009-11-18

VS

LOGIC

1

8 4

Output Control

Buffer

4

GND

normal function

SCB / overload

open load

short to ground

Output Stage

1

V

BB

OUT1

OUT4

Data Sheet TLE 6220 GP

RESET

CS

FAULT

RESET

CS

FAULT

Pin Description Pin Configuration (Top view)

Pin Symbol Function

1 GND Ground
2 IN2 Input Channel 2
3 OUT1 Power Output Channel 1
4 VS Supply Voltage
5

6
7 PRG Program (inputs high or low active)

8 OUT2 Power Output Channel 2

9 IN1 Input Channel 1
10 GND Ground
11 GND Ground
12 IN4 Input Channel 4
13 OUT3 Power Output Channel 3
14

15 SO Serial Data Output
16 SCLK Serial Clock
17 SI Serial Data Input
18 OUT4 Power Output Channel 4
19 IN3 Input Channel 3
20 GND Ground

General Fault Flag

Reset

Chip Select

GND 1• 20 GND

IN2 2 19 IN3

OUT1 3 18 OUT4

VS

PRG 7 14

OUT2 8 13 OUT3

IN1 9 12 IN4

GND 10 11 GND

Power SO-20

4 17
5 16 SCLK
6 15 SO

SI

Heat slug internally connected to ground pins

V2.2 Page 2009-11-18

2

Data Sheet TLE 6220 GP

Maximum Ratings for Tj = – 40°C to 150°C

Parameter Symbol Values Unit

Supply Voltage VS -0.3 ... +7 V
Continuous Drain Source Voltage (OUT1...OUT4) VDS 45 V
Input Voltage, All Inputs and Data Lines VIN - 0.3 ... + 7 V

2

Load Dump Protection V

Load Dump

= UP+US; UP=13.5 V

V

Load Dump

With Automotive Injector Valve RL = 14 Ω

1

)

R

=2 Ω; td=400ms; IN = low or high

I

With RL= 6.8 Ω (ID = 2A)
RI=2 Ω; td=400ms; IN = low or high
Operating Temperature Range
Storage Temperature Range
Output Current per Channel (see el. characteristics) I
Output Current per Channel @ TA = 25°C

3

(All 4 Channels ON; Mounted on PCB )

)

Output Clamping Energy

Tj
T

stg

D(lim)

ID 1 A

EAS 50 mJ
ID = 1A
Power Dissipation (DC, mounted on PCB) @ TA = 25°C P

Electrostatic Discharge Voltage (human body model)

3 W

tot

V

ESD

according to MIL STD 883D, method 3015.7 and EOS/ESD
assn. standard S5.1 - 1993

DIN Humidity Category, DIN 40 040 E
IEC Climatic Category, DIN IEC 68-1 40/150/56
Thermal resistance
junction – case (die soldered on the frame)
junction - ambient @ min. footprint

R

thJC

R

thJA

junction - ambient @ 6 cm2 cooling area

)

62

52

I

- 40 ... + 150

- 55 ... + 150

D(lim) min

A

°C

2000 V

2
50

K/W

38

V

Minimum footprint

PCB with heat pipes,
backside 6 cm2 cooling area

1

)

RI=internal resistance of the load dump test pulse generator LD200

2

)

V

LoadDump

3

)

Output current rating so long as maximum junction temperature is not exceeded. At TA = 125 °C the output

current has to be calculated using R

V2.2 Page 2009-11-18

is setup without DUT connected to the generator per ISO 7637-1 and DIN 40 839.

according mounting conditions.

thJA

3

Data Sheet TLE 6220 GP

µs

RESET

FAULT

FAULT

K

Electrical Characteristics

Parameter and Conditions Symbol Values Unit

VS = 4.5 to 5.5 V ; Tj = - 40 °C to + 150 °C ; Reset = H

(unless otherwise specified)

1. Power Supply, Reset

min typ max

Supply Voltage4
Supply Current 5 IS
Minimum Reset Duration

VS

t

Reset,min

4.5 -- 5.5

--

1 2 mA

10

(After a reset all parallel inputs are ORed with the SPI
data bits)

2. Power Outputs

ON Resistance VS = 5 V; ID = 1 A TJ = 25°C
TJ = 150°C

Output Clamping Voltage output OFF V
Current Limit I
Output Leakage Current V

RESET

= L
Turn-On Time ID = 1 A, resistive load tON -­Turn-Off Time ID = 1 A, resistive load t

R

D(lim)

I

D(lkg)

OFF

DS(ON)

DS(AZ)

-- --

--

--

-­45

0.32

-­53

3 4.5 6 A

5 10 µs
5 10 µs

3. Digital Inputs

Input Low Voltage V
Input High Voltage V
Input Voltage Hysteresis V
Input Pull Down/Up Current (IN1 ... IN4) I
PRG,

Pull Up Current I
Input Pull Down Current (SI, SCLK) I
Input Pull Up Current (CS) I

- 0.3

INL

2.0

INH

50 100

INHys

20 50 100 µA

IN(1..4)
IN(PRG,Res)
IN(SI,SCLK)
IN(CS)

20 50 100 µA

10 20 50 µA

10 20 50 µA

--

--

0.4

Ω

0.7
60 V

10 µA

1.0 V

VS+0.3

200

mV

V

V

4. Digital Outputs (SO,

SO High State Output Voltage I
SO Low State Output Voltage I
Output Tri-state Leakage Current CS= H, 0 ≤ VSO ≤ VS I

Output Low Voltage I
Current Limitation; Overload Threshold Current I
Overtemperature Shutdown Threshold

Hysteresis6

)

= 2 mA V

SOH

= 2.5 mA V

SOL

= 1.6 mA V

FAULT

VS - 0.4 -- -- V

SOH

-- -- 0.4 V

SOL

-10 0 10 µA

SOlkg

FAULTL

D(lim) 1...4

T

th(sd)

T

hys

-- --

3 4.5 6 A

170

--

-­10

0.4 V

200

--

°C

4

For VS < 4.5V the power stages are switched according the input signals and data bits or are definitely switched

off. This undervoltage reset gets active at VS = 3V (typ. value) and is guaranteed by design.

5

If Reset = L the supply current is reduced to typ. 20µA

6

This parameter will not be tested but guaranteed by design

V2.2 Page 2009-11-18

4

Data Sheet TLE 6220 GP

V

V

V

V

Electrical Characteristics cont.

Parameter and Conditions Symbol Values Unit

VS = 4.5 to 5.5 V ; Tj = - 40 °C to + 150 °C ; Reset = H

min typ max

(unless otherwise specified)

5. Diagnostic Functions

Open Load Detection Voltage V
Output Pull Down Current I
Fault Delay Time t
Short to Ground Detection Voltage V
Short to Ground Detection Current I

V

DS(OL)

50 90 150 µA

PD(OL)

50 110 200 µs

d(fault)

VS –3.3 VS -2.9

DS(SHG)

-50 -100 -150 µA

SHG

-2.5 VS -2

S

S

S

6. SPI-Timing

Serial Clock Frequency (depending on SO load) f
Serial Clock Period (1/fclk) t
Serial Clock High Time t
Serial Clock Low Time t
Enable Lead Time (falling edge of CS to rising edge of

CLK)

Enable Lag Time (falling edge of CLK to rising edge ofCS) t

DC -- 5 MHz

SCK

200 -- -- ns

p(SCK)

50 -- -- ns

SCKH

50 -- -- ns

SCKL

t

250 -- -- ns

lead

250 --- -- ns

lag

Data Setup Time (required time SI to falling of CLK) tSU 20 -- -- ns
Data Hold Time (falling edge of CLK to SI) tH 20 -- -- ns
Disable Time @ CL = 50 pF8 t
Transfer Delay Time7

-- -- 150 ns

DIS

tdt 200 -- -- ns
(CS high time between two accesses)
Data Valid Time CL = 50 pF
CL = 100 pF8
CL = 220 pF8

t

--

valid

--

--

--

--

--

110
120
150

-1.3

-2.5

ns

7

This time is necessary between two write accesses. To get the correct diagnostic information, the transfer delay

time has to be extended to the maximum fault delay time t

8

This parameter will not be tested but guaranteed by design

d(fault)max

V2.2 Page 2009-11-18

= 200µs.

5

Data Sheet TLE 6220 GP

CS

CS

CS

CS

Functional Description

The TLE 6220 GP is an quad-low-side power switch which provides a serial peripheral inter­face (SPI) to control the 4 power DMOS switches, as well as diagnostic feedback. The power
transistors are protected against short to VBB, overload, overtemperature and against over­voltage by an active zener clamp.
The diagnostic logic recognises a fault condition which can be read out via the serial diagnos­tic output (SO).

Circuit Description

Power Transistor Protection Functions9)

Each of the four output stages has its own zener clamp, which causes a voltage limitation at
the power transistor when solenoid loads are switched off. The outputs are provided with a
current limitation set to a minimum of 3 A. The continuous current for each channel is 1A (all
channels ON; depending on cooling).
Each output is protected by embedded protection functions. In the event of an overload or
short to supply, the current is internally limited and the corresponding bit combination is set
(early warning). If this operation leads to an overtemperature condition, a second protection
level (about 170 °C) will change the output into a low duty cycle PWM (selective thermal shut­down with restart) to prevent critical chip temperatures.

SPI Signal Description

- Chip Select. The system microcontroller selects the TLE 6220 GP by means of the
pin. Whenever the pin is in a logic low state, data can be transferred from the µC and vice
versa.

High to Low transition: - Diagnostic status information is transferred from the power

outputs into the shift register.

state corresponding to the SO bits.

To avoid any false clocking the serial clock input pin SCLK should be logic low state during
high to low transition of CS. When CS is in a logic high state, any signals at the SCLK and SI

pins are ignored and SO is forced into a high impedance state.

- Serial input data can be clocked in from then on.

- SO changes from high impedance state to logic high or low

Low to High transition: - Transfer of SI bits from shift register into output buffers

- Reset of diagnosis register.

9 )

The integrated protection functions prevent an IC destruction under fault conditions and may not be used in normal operation or permanently .

V2.2 Page 2009-11-18

6

Data Sheet TLE 6220 GP

CS

CS

RESET

SCLK - Serial Clock. The system clock pin clocks the internal shift register of the TLE

6220 GP. The serial input (SI) accepts data into the input shift register on the falling edge of
SCLK while the serial output (SO) shifts diagnostic information out of the shift register on the
rising edge of serial clock. It is essential that the SCLK pin is in a logic low state whenever

chip select
SI - Serial Input. Serial data bits are shifted in at this pin, the most significant bit first. SI infor-

mation is read in on the falling edge of SCLK. Input data is latched in the shift register and
then transferred to the control buffer of the output stages.
The input data consists of one byte, made up of four control bits and four data bits. The con­trol word is used to program the device, to operate it in a certain mode as well as providing
diagnostic information (see page 11). The four data bits contain the input information for the
four channels, and are high active.

SO - Serial Output. Diagnostic data bits are shifted out serially at this pin, the most significant

makes any transition.

bit first. SO is in a high impedance state until the
nostic data will appear at the SO pin following the rising edge of SCLK.

- Reset pin. If the reset pin is in a logic low state, it clears the SPI shift register and
switches all outputs OFF. An internal pull-up structure is provided on chip. As long as the re­set pin is low the device is in low quiescent current mode and the supply current is reduced to
typ. 20µA.

pin goes to a logic low state. New diag-

Output Stage Control

The four outputs of the TLE 6220 GP can either be controlled in parallel (IN1...IN4), or via the
Serial Peripheral Interface (SPI).

Parallel Control

A Boolean operation (either AND or OR) is performed on each of the parallel inputs and re­spective SPI data bits, in order to determine the states of the respective outputs. The type of
Boolean operation performed is programmed via the serial interface.
The parallel inputs are high or low active depending on the PRG pin. If the parallel input pins
are not connected (independent of high or low activity) it is guaranteed that the outputs 1 to 4
are switched OFF. PRG pin itself is internally pulled up when it is not connected.

PRG - Program pin. PRG = High (VS): Parallel inputs Channel 1 to 4 are high active
PRG = Low (GND): Parallel inputs Channel 1 to 4 are low active.

V2.2 Page 2009-11-18

7

Data Sheet TLE 6220 GP

IN1...4 and serial data bits 'AND'ed. 'Full Diagnosis' performed.

Serial Control of the Outputs: SPI protocol

Each output is independently controlled by an output latch and a common reset line, which
disables all four outputs. The Serial Input (SI) is read on the falling edge of the serial clock. A
logic high input 'data bit' turns the respective output channel ON, a logic low 'data bit' turns it

OFF. CS must be low whilst shifting all the serial data into the device. A low-to-high transition
of CS transfers the serial data input bits to the output control buffer.

As mentioned above, the serial input byte consists of a 4 bit control word and a 4 bit data
word. Via the control word, the specific mode of the device is programmable.

MSB LSB

Five specific control words are recognised, having the following functions:

No. Serial Input Byte Function

1
2
3
4
5

Note: 'X' means 'don't care', because this bit will be ignored
'D' represents the data bit, either being H (=ON) or L (=OFF)

1. LLLL XXXX - Diagnosis only
By clocking in this control byte, it is possible to get pure diagnostic information (two bits per
channel) in accordance with Figure 1 (page 11). The data bits are ignored, so that the state of
the outputs are not influenced. This command is only active once unless the next control com­mand is again "Diagnosis only".

2. HHLL XXXX - Reading back of input, and ‘1-bit Diagnosis’
If the TLE 6220 GP is used as bare die in a hybrid application, it is necessary to know if
proper connections exist between the µC-port and parallel inputs. By entering ‘HHLL’ as the
control word, the first four bits of the SO give the state of the parallel inputs, depending on the
µC signals. By comparing the four IN-bits with the corresponding µC-port signal, the neces­sary connection between the µC and the TLE 6220 can be verified - i.e. ‘read back of the in­puts’.
The second 4-bit word fed out at the serial output contains ‘1-bit’ fault information of the out­puts ( H = no fault, L = fault ). In the expression given below for the output byte, ‘FX’ is the
fault bit for channel X.

MSB LSB
IN4 IN3 IN2 IN1 F4 F3 F2 F1 : Serial Output byte

DDDDCCCC : Serial input byte

321321

Bits DataBits Control

LLLL XXXX Only 'Full Diagnosis' performed. No change to output states.
HHLL XXXX State of four parallel inputs and '1-bit Diagnosis' outputted.
HLHL XXXX Echo-function of SPI; SI direct connected to SO
LLHH DDDD IN1...4 and serial data bits 'OR'ed. 'Full Diagnosis' performed.
HHHH DDDD

V2.2 Page 2009-11-18

8

Data Sheet TLE 6220 GP

CS

CS

IN 1...4

data bits 0...3

CS

SI H H L L X X X X
SO H H H H H H H H

SI command

output state; reading back of
inputs and 1bit diagnosis

SO diagnosis

function

: No change of the

: No fault, normal

CS

SI H H H H L H H L

IN4 IN3 IN2 IN1 F4 F3 F2 F1

SO

SI command: AND-Operation;
Ch1 and 4 OFF, Ch2 and 3 ON.

SO diagnosis

inputs and 1 bit diagnosis performed

: State of four parallel

CS

SI H H H H L L L L
SO H H H H H H H H

SI command: AND-Operation and
all channels OFF.
SO diagnosis: No fault, normal
function

3. HLHL XXXX - Echo-function of SPI
To check the proper function of the serial interface the TLE 6220 GP provides a "SPI Echo

Function". By entering HLHL as control word, SI and SO are connected during the next
period. By comparing the bits clocked in with the serial output bits, the proper function of the

SPI interface can be verified. This internal loop is only closed once (for one

period).

CS

SI H L H L X X X X

SI word

SI SO

SO H H H H L H H H

SI command: No change of the
output states; Echo function of SPI
SO diagnosis: Open load condition
at channel 2, other channels ok.

Echo-function of SPI

directly connected to SO.
SI information

during this cycle

outputs set accordingly after
chip select rising edge

, i.e. SI

will be accepted

and the

4. LLHH DDDD - OR operation, and ‘full diagnosis’
With LLHH as the control word, each of the input signals IN1...IN4 are 'OR'ed with the corre­sponding data bits (DDDD).

Output

Driver

Serial Input,

1

≥

This OR operation enables the serial interface to switch the channel ON, even though the cor­responding parallel input might be in the off state.

⇒ SPI Priority for ON-State

Also parallel control of the outputs is possible without an SPI input.

V2.2 Page 2009-11-18

9

Data Sheet TLE 6220 GP

IN 1...4

The OR-function is the default Boolean operation if the device restarts after a Reset, or when
the supply voltage is switched on for the first time.
If the OR operation is programmed it is latched until it is overwritten by the AND operation.

5. HHHH DDDD - AND operation, and ‘full diagnosis’
With HHHH as the control word, each of the input signals IN1...IN4 are 'AND'ed with the cor­responding data bits (DDDD).

&

Serial Input,
data bits 0...3

The AND operation implies that the output can be switched off by the SPI data bit input, even
if the corresponding parallel input is in the ON state.

This also implies that the serial input data bit can only switch the output channel ON if the cor­responding parallel input is in the ON state.
If the AND operation is programmed it is latched until it is overwritten by the OR operation.

Control words beside No. 1- 5

All control words except those for Diag Only, Read Back of Inputs, SPI echo, will be accepted
as an OR or an AND command with valid data bits depending on the boolean operation which
was programmed before.

Example 1:

LLHH HLLH: OR operation between parallel inputs and data bits, i.e channel 1 and 4 will be
switched on.
The next command is now: LHHH HHLH
LHHH as command word has no special meaning but it will be accepted as an OR operation
and the data bits will be ORed with the inputs and the outputs 1,3 and 4 will be switched on.
See above: 'If the OR operation is programmed it is latched until it is overwritten by the AND
operation.'

Example 2:

HHHH LLHL means: Data bits will be ANDed with the parallel inputs and the outputs switch
accordingly. Then HLLH HHLH is clocked in: AND was latched by the command before and is
now valid again by using the HLLH command word. So the data bits will be accepted and
again ANDed with the parallel input signals.
See above: 'If the AND operation is programmed it is latched until it is overwritten by the OR
operation.'

Output

Driver

⇒ SPI Priority for OFF-state

V2.2 Page 2009-11-18

10

Data Sheet TLE 6220 GP

FAULT

CS

CS

Ch.4

Ch.3

Ch.2

Ch.1

7 6 5 4 3 2 1 0

Diagnostics

- Fault pin. There is a general fault pin (open drain) which shows a high to low transi-

tion as soon as an error occurs for any one of the four channels. This fault indication can be
used to generate a µC interrupt. Therefore a ‘diagnosis’ interrupt routine need only be called
after this fault indication. This saves processor time compared to a cyclic reading of the SO
information.

As soon as a fault occurs, the fault information is latched into the diagnosis register. A new
error will over-write the old error report. Serial data out pin (SO) is in a high impedance state

when
The rising edge of CS will reset all error registers.

Full Diagnosis

For full diagnosis there are two diagnostic bits per channel configured as shown in Figure 1.

is high. If

receives a LOW signal, all diagnosis bits can be shifted out serially.

Diagnostic Serial OUT (SO)

HH Normal function
HL Overload, Shorted Load or Overtemperature
LH Open Load
LL Shorted to Ground

Figure 1: Two bits per channel diagnostic feedback

Normal function: The bit combination HH indicates that there is no fault condition, i.e. normal

function.
Overload, Short Circuit to Battery (SCB) or Overtemperature: HL is set when the current
limitation gets active, i.e. there is a overload, short to supply or overtemperature condition.
Open load: An open load condition is detected when the drain voltage decreases below 3 V
(typ.). LH bit combination is set.
Short Circuit to GND: If a drain to ground short circuit exists and the drain to ground current
exceeds 100 µA, short to ground is detected and the LL bit combination is set.

A definite distinction between open load and short to ground is guaranteed by design.
The standard way of obtaining diagnostic information is as follows:

Clock in serial information into SI pin and wait approximately 150 µs to allow the outputs to
settle. Clock in the identical serial information once again - during this process the data com­ing out at SO contains the bit combinations representing the diagnosis conditions as de­scribed in Figure 1.

V2.2 Page 2009-11-18

11

Data

Bits

Control

Bits

CS

SCLK

CS

Data Sheet TLE 6220 GP

Timing Diagrams

6 74444 84444

SI

SO

Outputs

7 6 5 4 3 2 1 0

MSB

7 6 5 4 3 2 1 0

Figure 2: Serial Interface

0.2 V

S

t

SCKH

t

lead

SCLK

t

SU

SI

t

SCKL

6 74444 84444

LSB

OLD NEW

t

H

0.7V

S

0.2V

S

0.7VS

t

lag

0.7VS

0.2V

t

dt

S

Figure 3: Input Timing Diagram

0.7 V

SCLK

SO

SO

t

valid

0.2 V

0.7 V

S

0.7 V

0.2 V

S

S

S

S

CS

SO

0.2 V

S

t

Dis

Figure 4:
SO Valid Time Waveforms Enable and Disable Time Waveforms

V2.2 Page 2009-11-18

12

Data Sheet TLE 6220 GP

MTSR

V

IN

t

t

V

DS

ON

80%

20%

Figure 5: Power Outputs

Application Circuit

t

OFF

t

V

BB

µC

e.g. C166

MRST

CLK

P xy

VS

10k

PRG

FAULT

RESET

IN1
IN2

IN3

IN4

SI
SO

CLK

VS

OUT1

OUT2

OUT4

TLE

6220

GP

GND

V2.2 Page 2009-11-18

13

Data Sheet TLE 6220 GP

RDS(ON) [Ohm]

VDS (AZ) [V]

Typical electrical Characteristics
Drain-Source on-resistance

R

= f (Tj) ; Vs = 5V

DS(ON)

Typical Drain- Source ON-Resistance

0,58

0,53

0,48

0,43

0,38

0,33

0,28

0,23

-50 -25 0 25 50 75 100 125 150 175

Tj[°C]

Figure 6 : Typical ON Resistance versus Junction-Temperature

Channel 1-4

Channel 1-4

Output Clamping Voltage

V

= f (Tj) ; Vs = 5V

DS(AZ)

Typical Clamping Voltage

55

54

53

52

51

50

49

48

-50 -25 0 25 50 75 100 125 150 175

Channel 1-4

Tj[°C]

Figure 7 : Typical Clamp Voltage versus Junction-Temperature

Channel 1-4

V2.2 Page 2009-11-18

14

Data Sheet TLE 6220 GP

Injector 2

Parallel SPI Configuration

Engine Management Application

TLE 6230 GP in combination with TLE 6240 GP (16-fold switch) for relays and general purpose loads
and TLE 6220 GP (quad switch) to drive the injector valves. This arrangement covers the numerous
loads to be driven in a modern Engine Management/Powertrain system. From 28 channels in sum 16
can be controlled direct in parallel for PWM applications.

µC

C167

P x.1-4

MTSR
MRST

CLK

P x.y

P x.1-4

P x.y

P x.1-8

4

4

4 PWM
Channels

SI
SO
CLK

CS

4 PWM
Channels

SI
SO

CLK

TLE

6220 GP

Quad

TLE

6230 GP

Injector 3

Injector 4

Octal

8

8 PWM
Channels

Injector 1

SI
SO
CLK

P x.y

TLE

6240 GP

16-fold

Daisy Chain Application TLE 6220 GP

V2.2 Page 2009-11-18

µC

MTSR

MRST

Px.1
Px.2

CS

SI

CS

CLK

TLE

6220 GP

Quad

SO

CS

SI

CLK

TLE

6220 GP

Quad

15

SO

CS

SI

CLK

TLE

6220 GP

Quad

SO

Data Sheet TLE 6220 GP

Package and Ordering Code

(all dimensions in mm)

PG - DSO - 20

TLE 6220 GP

+/- 0.1

15.74

13.7

-0.2

9 x = 11.431.27

1.27

1120

0.4

+0.1 3

0.25 AM

1 10

1 x 45°

PIN 1 INDEX MAR KING

A

15.9

+/ -0.1 5

2.8

0.1

8° 8°

8°

1.2

-0.3

+/ -0.1

+/ -0 .1

3.2

5.9

1.3

8°

1)

11

14.2

6.3

+/-0.15

+/ -0.3

V2.2 Page 2009-11-18

16

Data Sheet TLE 6220 GP

Green Product (RoHS compliant)

To meet the world-wide customer requirements for environmentally friendly products and to be com­pliant with government regulations the device is available as a green product. Green products are
RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to
IPC/JEDEC J-STD-020).

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Data Sheet TLE 6220 GP

Revision History
Version Date Changes

V2.1 ->
V2.2

V2.0 ->
V2.1

V1.1 ->
V2.0

V1.1 28.08.2007 Initial Version of “grey” product

18.11.2009 Package changed to PG-DSO-20
Ordering code removed

20.04.2007 Ordering Code removed
Layout Changes
Correct green package name implemented P-DSO-20-12 à PG-DSO­20-26

20.05.2003 Changes to Green Product Version:

- AEC, RoHS Logo and Feature List content added

- Package Name P-DSO -> PGDSO

- Change History added

- Disclaimer re-newed

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Data Sheet TLE 6220 GP

Edition 2007-04-17
Published by

Infineon Technologies AG
81726 Munich, Germany

© 11/19/09 Infineon Technologies AG

All Rights Reserved.

Legal Disclaimer

The information given in this document shall in no event be regarded as a guarantee of conditions or characteris­tics. With respect to any examples or hints given herein, any typical values stated herein and/or any information
regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabili­ties of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any
third party.

Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest In-

fineon Technologies Office (www.infineon.com).
Warnings

Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.

Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the
failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life
support devices or systems are intended to be implanted in the human body or to support and/or maintain and
sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other per­sons may be endangered.

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