Datasheet TLE5203G, TLE5203 Datasheet (Siemens)

3-A DC Motor Driver

TLE 5203

Overview SPT IC

Features

• Output current ± 3 A

• I/O error diagnostics

• Short-circuit proof

• Four-quadrant operation

• Integrated free-wheeling diodes

• Wide temperature range

• Open load detection

• Break low, if break high required, the device

P-TO220-7-1

TLE 5204 will fit

1)

P-TO220-7-8

Type Ordering Code Package

TLE 5203 Q67000-A9096 P-TO220-7-1
TLE 5203 G Q67006-A9242 P-TO220-7-8

Description

TLE 5203 is an integrated power bridge with DMOS output stages for driving DC motors.
This motor bridge is optimized for driving DC motors in reversible operation. The internal

protective circuitry in particular ensures that no crossover currents can occur.
Because the free-wheeling diodes are integrated, the external circuitry that is necessary

is reduced to the capacitors on the supply voltage.
The control inputs have TTL/CMOS-compatible levels.

1)

SIEMENS Power Technology

Semiconductor Group 1 1998-02-01

TLE 5203

TLE 5203 GTLE 5203

4321567

EF

Q1

Ι

1

GND

Ι

2

V

S

Q2

AEP01224

Figure 1 Pin Configuration (top view)

Semiconductor Group 2 1998-02-01

TLE 5203

Pin Definitions and Functions
Pin No. Symbol Function

1Q1Output of channel 1; Short-circuit proof, free-wheeling

diodes integrated for inductive loads

2EFError flag; TTL/CMOS-compatible output for error detection

(open drain)
3 I1 Control input 1; TTL/CMOS-compatible
4GNDGround; connected internally to cooling fin
5 I2 Control input 2; TTL/CMOS-compatible
6

V

S

Supply voltage; wire with capacitor matching load
7Q2Output of channel 2; Short-circuit proof, free-wheeling

diodes integrated for inductive loads

Circuit Description

Input Circuit

The control inputs consist of TTL/CMOS-compatible Schmitt triggers with hysteresis.
Buffer amplifiers are driven by these stages and convert the logic signal into the
necessary form for driving the power output stages.

Output Stages

The output stages form a switched H-bridge. Protective circuits make the outputs short­circuit proof to ground and to the supply voltage throughout the operating range. Positive
and negative voltage s pikes, wh ich occur when switchin g inductive loads, are clamped
by integrated power diodes.

Semiconductor Group 3 1998-02-01

Functional Truth Table
E1 E2 Q1 Q2 Comments

L L H L Motor turns counterclockwise
L H L H Motor turns clockwise
HLLLBrake; both low side transistors turned-ON
H H Z Z Open circuit detection

Notes for Output Stage
Symbol Value

L Low side transistor is turned-ON

High side transistor is turned-OFF

H High side transistor is turned-ON

Low side transistor is turned-OFF

TLE 5203

Z High side transistor is turned-OFF

Low side transistor is turned-OFF

Monitoring Functions

An internal circuit ensures that all output transistors are turned-OFF if the supply voltage
is below the operating range.

A monitoring circuit for each output transistor detects whether the particular transistor is
active and in this case prevents the corresponding source transistor (sink transistor) from
conducting in sink operat ion (source operation). Therefore no crossover currents can
occur. Pulse-width operation is possible up to a maximum switching frequency of 1 kHz
for any load.

Depending on the load current higher frequencies are possible.

Protective Function

V

Various errors like short-circuit to +

, ground or across the load are detected. All faults

S

result in turn-OFF of the output stages after a delay of 40 µs and setting of the error flag
EF to ground. Changing the inputs resets the error flag.

Output Shorted to Ground Detection

If a high side transistor is switched on and its output is shorted to ground, the output
current is limited to typ 8 A. After a delay of 40 µs all outputs will be switched off and the
error flag EF is set to ground.

Semiconductor Group 4 1998-02-01

TLE 5203

Output Shorted to + VS and Overload Detection

An internal circuit detects if the current through the low side transistor is higher than 4 A
typ. In this case all outputs are turned off after 40 µs and the error flag EF is set to
ground.

At a junction temperature higher than 160 °C th e thermal shutdown turns off, all four
output stages commonly and the error flag is set without a delay.

Open Load Detection

The output Q1 has a 10 kΩ pull-up resi stor and the output Q 2 has a 10 kΩ pull-down
resistor. If E1 and E2 a re high, all o utput power s tages are turne d-OFF. In case of no

V

load between Q1 and Q2 the output voltage Q1 is
be detected by two comparators and an error flag will be set after a delay time of 40 µs.
Changing the inputs resets the error flip flop.

and Q2 is ground. This state wil l

S

Diagnosis

Input Output Diagnosis EF

E1 E2 Q1 Q2 Shorted

to GND

Shorted

V

to

S

Overload Open Load

L L H L Q1 Q2 X –L
L H L H Q2 Q1 X – L
HLLL– Q1, Q2 – – L
HHZZ–––XL

Semiconductor Group 5 1998-02-01

TLE 5203

V

=

EH

Pull Up

Ω10 k

EF

Pull
Down

10 kΩ

=

V

EL

&

Figure 2 Simplified Schematic for Open Load Detection

Control Input 1

Error Flag

2

Error

Flag

Protection

Circuit 1

3

V

S

6

40 sµ

1

Output 1

RS
FF

AES01688

Control Input 2

5

7

Output 2

Protection

Circuit 1

4
GND

AEB01225

Figure 3 Block Diagram

Semiconductor Group 6 1998-02-01

Absolute Maximum Ratings

T

= – 40 to 150 °C

j

Parameter Symbol Limit Values Unit Remarks

min. max.

Voltage

TLE 5203

Supply voltage
Supply voltage
Logic input voltage
Diagnostics output voltage

Current

Free-wheeling current
Output current

1)

Junction temperature
Storage temperature

Thermal Resistance

Junction-case
Junction-ambient

Operating Range

Supply voltage
Logic input voltage
Switching frequency

2)

Junction temperature

V
V
V
V

I
I

T
T

R
R

V
V
f
T

S
S
I1 , 2
EF

F
Q

j
stg

th jC
th jA

S
I1 , 2

j

– 0.3
– 1
– 0.3
– 0.3

– 4
– 4

– 40
– 50

–
–

6
– 0.3
–
– 40

40
–
7
7

4
4

150
150

4
65

24
7
1
150

V
V
V
V

A
A

°C
°C

K/W
K/W––

V
V
kHz
°C

–

t < 500 ms; I
V

= 0 – 40 V

S

–

T

≤ 150 °C

j

–
–

–

–
–
–
–

< 5 A

S

1)

During overload condition currents higher than 4 A can dynamically occur, before the device shuts off, without
any damaging the device.

2)

Depending on load higher freq uencies are possible.

Semiconductor Group 7 1998-02-01

TLE 5203

Electrical Characteristics

V

= 6 to 18 V; Tj = – 40 to 150 °C

S

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

General

Quiescent current
Turn-ON delay
Turn-OFF delay
Turn-ON time

Turn-OFF time
Undervoltage

Undervoltage

Logic

Control inputs
H-input voltage
L-input voltage

Hysteresis of
input voltage

H-input current
L-input current

I
t
t
t

t

V
V

V
V

∆

I
I

d1
d2
r

f

q

–
–
–
–

–
10
–
10

10
20
10
20

mA

µs
µs
µs

I

= 0 A

L

Input to output
Input to output

I

= 2.5 A;

Q

cf diagram

I

–

–

10

µs

= 2.5 A;

Q

cf diagram

S
S

IH
IL

V

I

I
I

–
–

2.8
–

0.4 0.8 1.2 V –

–2
–10––420

5.5

4.5

–
–

5.9

5.2

–

1.2

V
V

V
V

µA
µA

I

C ON

I

C OFF

–
–

V

I

V

I

= V
= V

IH
IL

Diagnosis output
Delay time
L-output voltage
Leakage current

t
V
I

d

EF

RD

20
–
–

40
–
–

60

0.4
10

µs
V
µA

–

I = 3 mA

–

Error detection
Switching threshold U
Switching threshold L
Overcurrent 1

Semiconductor Group 8 1998-02-01

V
V
I

EH
EL

F1

2
2
3

2.7

2.7
4

3.5

3.5
5

V
V
A

Error low
Error high
Error low

TLE 5203

Electrical Characteristics (cont’d)

V

= 6 to 18 V; Tj = – 40 to 150 °C

S

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

Outputs

RDSONU
RDSONU
RDSONL
RDSONL
Diode forward voltage
Diode forward voltage
Pull up/pull down

1)

Values for RDSON are for t > 100 µs after applying + V

–
–
–
–

V
V
R

FU
FL

–
–
–
–
–
–
5

–
–
–
–
–
–
10

0.4

0.65

0.4

0.65

1.5

1.5
25

.

S

Ω
Ω
Ω
Ω

V
V
kΩ

V

> 6 V; Tj = 25 °C

S

V

> 6 V; Tj = 150 °C

S

V

> 6 V; Tj = 25 °C

S

V

> 6 V; Tj = 150 °C

S

I

= 3 A

F

I

= 3 A

F

–

1)

1)

1)

1)

Semiconductor Group 9 1998-02-01

TLE 5203

V

S

V

1Ι

V

Ι2

Figure 4 Test Circuit

Ι

q

Ι

Ι1

3

Ι

2Ι

5

4700 Fµ

Ι

,

S

63V

6

TLE 5203

470nF

2

Ι

Q1

1

R

L

Ι

Q2

7

V

EF

4

V

V

Q2

Q1

Ι

M

AES01226

Figure 5 Timing Diagram

Semiconductor Group 10 1998-02-01

TLE 5203

+

V

= 12 V

S

220 nF

5 V

2 kΩ

Error
Flag

*)

6

12

TLE 5203

3

Control
Inputs

5

*) Necessary for isolating supply voltage or interruption (e.g. 470 µF).

Figure 6 Application Circuit

M

7

4

AES01228

Semiconductor Group 11 1998-02-01

Diagrams

R

Resistance of Output Stage

ON

over Temperature

TLE 5203

Output Voltage on Diagnostics
Output versus Current

800

R

ON

m

Ω

600

6 V<

V

S

<18 V

max

AED01305

typ

400

200

0

0

25 50

75

100 150

˚C

T

j

Forward Current of Upper
Free-Wheeling Diode versus Voltage

300

V

EF

mV

AED01306

250

V

S

=12 V

T

= 150 ˚C

j

200

150

T

= 25 ˚C

j

100

50

0

0

1234

mA

6

Forward Current of Lower
Free-Wheeling Diode versus Voltage

4

Ι

F

A

3

= 150 ˚C

T

j

2

1

0

0.2

0.6

AED01303

= 25 ˚C

T

j

1 1.4

V

V

F

4

Ι

F

A

3

T

= 150 ˚C

j

2

1

0

0.2

0.6

AED01304

T

= 25 ˚C

j

1 1.4

V

V

F

Semiconductor Group 12 1998-02-01

TLE 5203

Overcurrent Threshold
versus Temperature

10

Ι

Q

A

8

6

4

2

0

-40

040

typ

min

AED01681

80 120 ˚C 160

T

j

Quiescent Current
versus Temperature

5

Ι

S

mA

4

3

2

1

0

-40

040

typ

AED01682

80 120 ˚C 160

T

j

Input Threshold
versus Temperature

3.5

V

Ι

V

3.0

2.5

2.0

1.5

1.0

-40

040

typ

typ

80 120 ˚C 160

V

V

Ι

H

L

Ι

AED01683

T

j

Switching Threshold
versus Temperature

5.5

V

F

V

5.0

4.5
typ

4.0

3.5

3.0

-40

040

V

EL, EH

AED01684

80 120 ˚C 160

T

j

Semiconductor Group 13 1998-02-01

TLE 5203

E2

8 A

Ι

Q2

V

Q2

R

Short

8 Ax

V

sµ40

FL

EF

Figure 7 Timing Diagram for Output Shorted to Ground

E1 = Low

AED01685

E2

20 A

Ι

Q1

V

S

V

Q1

R

Short

20 Ax

V

FU

sµ40

EF

Figure 8 Timing Diagram for Output Shorted to V

E1 = Low

AED01686

S

Semiconductor Group 14 1998-02-01

TLE 5203

E2

Ι

Load

V

Q1

E1 = Low

Ι

F1

Overcurrent
Switching

Threshold

sµ40

V

S

x

Ι

ONRLoad

V

S

Ι

R

x

Load

ON

V

F

V

Q2

V

F

EF

AED01687

Figure 9 Timing Diagram for Overcurrent

Semiconductor Group 15 1998-02-01

TLE 5203

Normal Mode Open Circuit

E1

E2

V

S

V

/2

V

Q1

S

V

Q2

EF

Figure 10 Timing Diagram for Open Load

sµ40

AED01691

Semiconductor Group 16 1998-02-01

Package Outlines

P-TO220-7-1

(Plastic Transistor Single Outline)

TLE 5203

+0.4

10

10.2

-0.2
+0.1

3.75

2.8

17

1.27

1)

+0.1

0.6

1) 0.75

1) 0.75

at dam bar (max 1.8 from body)

-0.15

im Dichtstegbereich (max 1.8 vom Körper)

-0.15

0.6
7x

4.6

-0.2

1 x 45˚

+0.1

1.27

±0.3

-0.2

±0.4

19.5 max

16

2.6

+0.1

0.4

±0.4

M

4.5

8.4

±0.4

8.8

15.4

±0.3

±0.3

8.6

10.2

GPT05108

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our

Data Book “Package Information”.

Dimensions in mm

Semiconductor Group 17 1998-02-01

P-TO220-7-8 (SMD)

(Plastic Transistor Single Outline)

10.1

10.2

8.0

0.6

TLE 5203

4.6

1.27

0.2

2.6

1)

8.8

3.5

1.5

1.27

6 x 1.27 = 7.62

1) shear and punch direction burr free surface

0.4

GPT05874

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our

Data Book “Package Information”.

SMD = Surface Mounted Device

Dimensions in mm

Semiconductor Group 18 1998-02-01