Datasheet TLE4279GL, TLE4279G, TLE4279A, TLE4279GM Datasheet (Siemens)

5-V Low-Drop Fixed Voltage Regulator

Features

• Output voltage tolerance ≤ ± 2 %

• Very low current consumption

• Early warning

V

• Reset output low down to

• Overtemperature protection

• Reverse polarity proof

• Settable reset threshold

• Very low-drop voltage

• Wide temperature range

Type Ordering Code Package

TLE 4279 A on request P-DIP-8-4

= 1 V

Q

TLE 4279

P-DIP-8-4

TLE 4279 G Q67006-A9225 P-DSO-8-1 (SMD)

▼ TLE 4279 GM Q67006-A9307 P-DSO-14-4 (SMD)

TLE 4279 GL Q67006-A9306 P-DSO-20-6 (SMD)

▼ New type

Functional Description

This device is a voltage regulator with a fixed 5-V output,
e.g. in a P-DSO-8-1 package. The maximum operating
voltage is 45 V. The output is able to drive a 150 mA
load. It is short circuit protected and the thermal
shutdown switches the output off if the junction
temperature is in excess of 150 °C. A reset signal is

V

generated for an output voltage of

< 4.6 V. The reset

Q

threshold voltage can be decreased by external
connection of a voltage divider. The reset delay time can
be set by an external capacitor. If the application
requires pull up resistors at the logic outputs (Reset,
Sense Out) the TLE 4269 with integrated resi stors can

P-DSO-8-1

P-DSO-20-6

P-DSO-14-4

be used. It is also possible to supervise the input voltage by using an integrated
comparator to give a low voltage warning.

Semiconductor Group 1 1998-11-01

Pin Configuration
(top view)

P-DIP-8-4 P-DSO-8-1

18

Ι Q

S

Ι

RE

AEP01813

SO72
R63
GNDD54

TLE 4279

1

Ι

2

ΙS

RE

3

D5

4

8
7
6

AEP01668

Q
SO
R
GND

Pin Definitions and Functions (TLE 4279 A and TLE 4279 G)

Pin No. Symbol Function

1I Input; block directly to GND on the IC with a ceramic capacitor.
2SISense input; if not needed connect to Q.
3REReset threshold; if not needed connect to ground.
4DReset delay; to select the delay time, connect to GND via

external capacitor.
5 GND Ground
6RReset output; open-collector output
7SOSense output; open-collector output
8Q5-V output; connect to GND with a 10 µF capacitor, ESR < 10 Ω.

Semiconductor Group 2 1998-11-01

Pin Configuration
(top view)

TLE 4279

P-DSO-20-6

RE

D

N.C.
GND
GND
GND
GND

N.C.

N.C.

R

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12

11

AEP01802

Ι

S

Ι

N.C.
GND
GND
GND
GND
N.C.
Q
SO

Pin Definitions and Functions (TLE 4279 GL)

Pin No. Symbol Function

1REReset threshold; if not needed connect to ground.
2DReset delay; to select delay time connect to GND via

external capacitor.
4-7, 14-17 GND Ground
10 R Reset output; open-collector output
11 SO Sense output; open-collector output
12 Q Output; connect to GND with 10 µF capacitor, ESR < 10 Ω
19 I Input; block directly to GND at the IC by a ceramic capacitor
20 SI Sense input; if not needed connect to Q

Semiconductor Group 3 1998-11-01

Pin Configuration
(top view)

TLE 4279

P-DSO-14-4

RE

GND
GND
GND
GND

114
2

D

3
4
5
6

R

7

13
12

11

10

9
8

AEP02254

SI

Ι

GND
GND
GND
Q
SO

Pin Definitions and Functions (TLE 4279 GM)

Pin No. Symbol Function

1REReset threshold; if not needed connect to GND
2DReset delay; connect to GND via external delay capacitor for

setting delay time
3, 4, 5, 6 GND Ground
7RReset output; open-collector output
8SOSense output; open-collector output
9Q5-V output; connect to GND with 10 µF capacitor, ESR < 10 Ω
10, 11, 12 GND Ground
13 I Input; block to ground directly at the IC by a ceramic capacitor
14 SI Sense input; if not needed connect to Q

Semiconductor Group 4 1998-11-01

TLE 4279

Circuit Description

The control amplifier compares a reference voltage, made highly accurate by resistance
balancing, with a voltage proportional to the output volta ge and drives the base of the
series PNP transistor via a bu ffer. Saturation control as a function of the load current
prevents any over-saturation of the power element.

In the reset generator block a comparator compares a reference voltage independent of
the input voltage with the scaled-down output voltage. If the output voltage reaches 4.6 V
the reset delay capacitor is discharged and the reset output is se t to low. This low is
guaranteed down to a n output voltage of 1 V. As the output voltage increases again,
from 4.6 V onward the reset delay capacitor is charged with constant current. When the

V

capacitor voltage reaches the upper switching threshold
choosing the val ue of this capacito r, the reset delay ti me can be selecte d over a wide
range. With the reset thre sho ld inp ut RE it i s pos sib le to lower the reset threshold
pin RE is connected to pin Q via a voltage divider, for examp le, the reset condition is
reached when this voltage is decreased below the switching threshold

, the reset returns to high. By

dt

V

V

of 1.35 V.

re

rt

. If

Another comparator compares the signal of the pin SI, normally fed by a voltage divider
from the input voltage, with the reference and gives an early warning on the pin SO. It is
also possible to superwise an other voltage e.g. of a second regulator, or to build a
watchdog circuit with few external components.

Application Description

C

The input capacitor
approx. 1 Ω in series wit h
capacitance can be damped. The output capacitor C

is necessary for compensating line influences. Using a resistor of

I

C

, the oscillating circuit consisting of input inductivity and input

I

is necessary for the stability of the

Q

regulating circuit. Stability is guaranteed at values ≥ 10 µF and an ESR ≤ 10 Ω within the
operating temperature range. Both reset output and sense output are open collector
outputs and have to be connected to 5 V output via external pull-up res istors ≥ 10 kΩ.
For small tolerances of the reset delay the spread of the capacitance of the delay
capacitor and its temperature coefficient should be noted.

Semiconductor Group 5 1998-11-01

TLE 4279

D

RE

Ι

Q

Error

Amplifier

Reference

Current and

Saturation

Control

Trimming

R

Reference

SO

SI

AEB01955

Block Diagram

Semiconductor Group 6 1998-11-01

Absolute Maximum Ratings

T

= – 40 to 150 °C

j

Parameter Symbol Limit Values Unit Notes

min. max.

Input

TLE 4279

Input voltage

Input current

Sense Input

Input voltage
Input current

Reset Threshold

Voltage
Current

Reset Delay

Voltage
Current

V
I

V
I

V
I

V
I

I

SI

RE

D

I

SI

RE

D

– 40 45 V –

– – – internal limited

– 0.3 45 V –

11mA–

– 0.3 7 V –
– 10 10 mA –

– 0.3 7 V –

– – – internal limited

Ground

Current

I

GND

50 – mA –

Reset Output

Voltage
Current

V
I

R

R

– 0.3 7 V –

– – – internal limited

Sense Output

Voltage
Current

Semiconductor Group 7 1998-11-01

V
I

SO

SO

– 0.3 7 V –

– – – internal limited

Absolute Maximum Ratings (cont’d)

T

= – 40 to 150 °C

j

Parameter Symbol Limit Values Unit Notes

min. max.

5-V Output

TLE 4279

Output voltage

Output current

Temperature

Junction temperature
Storage temperature

Operating Range

Input voltage
Junction temperature

Thermal Data

Junction-ambient

V
I

T
T

V
T

R

Q

Q

j

Stg

I

j

thja

– 0.3 7 V –

–5 – mA –

–150°C–

– 50 150 °C –

–45V –

– 40 150 °C –

–100

200
70
70

K/W
K/W
K/W
K/W

P-DIP-8-4
P-DSO-8-1
P-DSO-14-4
P-DSO-20-6

R

thjc

Semiconductor Group 8 1998-11-01

–60

60
30
30

K/W
K/W
K/W
K/W

P-DIP-8-4
P-DSO-8-1
P-DSO-14-4
P-DSO-20-6

Characteristics

V

=13.5V; Tj= – 40 °C<Tj< 125 °C

I

Parameter Symbol Limit Values Unit Measuring

Condition

min. typ. max.

TLE 4279

Output voltage

Current limit

Current consumption;

I

= I

– I

q

I

Q

Current consumption;

I

= I

– I

q

I

Q

Current consumption;

I

= I

– I

q

I

Q

Drop voltage

V

I
I

I

I

V

Q

q

q

q

Load regulation ∆V
Line regulation ∆

Reset Generator

Q

dr

V

4.90 5.00 5.10 V 1 mA ≤ IQ≤ 100 mA

V

6V≤

≤ 16 V

I

150 200 500 mA –
– 150 300 µA IQ≤ 1mA,Tj<85°C

– 250 700 µA IQ=10mA

–28 mAIQ=50mA

– 0.25 0.5 V IQ=100mA

Q

Q

–1030mVIQ= 5 mA to 100 mA
–1040mVVI= 6 V to 26 V

I

=1mA

Q

1)

Switching threshold
Reset low voltage
Delay switching

V
V
V

rt

R

dt

4.50 4.60 4.80 V –
–0.10.4VR

1.4 1.8 2.2 V –

extern

= 20 kΩ

threshold
Switching threshold
Reset delay low voltage
Charge current I

1)

Drop voltage = VI– VQ (measured when the output voltage has dropped 100 mV from the

nominal value obtained at 13.5 V input.)

Semiconductor Group 9 1998-11-01

V
V

st

D

d

0.3 0.45 0.60 V –
––0.1VVQ< V

RT

3.0 6.5 9.5 µA VD=1V

Characteristics (cont’d)

V

= 13.5 V; Tj= – 40 °C<Tj< 125 °C

I

Parameter Symbol Limit Values Unit Measuring

Condition

min. typ. max.

TLE 4279

Delay time L → H

Delay time H → L
Switching voltage

Input Voltage Sense

Sense threshold high
Sence threshold low
Sense output

low voltage

Sense input current

t

d

t

t

V

re

V

si, high

V

si, high

V

SO,low

I

SI

17 28 –msCD= 100 nF

–1– µs CD= 100 nF

1.26 1.35 1.44 V VQ>3.5V

1.24 1.31 1.38 V –

1.16 1.20 1.28 V –
–0.10.4VVSI<1.20V;

V

>3V

I

R

= 20 kΩ

extern

– 10.11 µA –

Semiconductor Group 10 1998-11-01

TLE 4279

Measuring Circuit (P-DIP-8-4, P-DSO-8-1)

V

Ι

t

<

V

RT

V

Q

V

D

t

d

V

RO

Power-on-Reset Voltage Dip Secondary Overload

Thermal
Shutdown

t

RR

Undervoltage

at Input

RR

Ι

V

d

d

=

dt

C

D

at OutputSpike

V

DT

V

ST

AED01542

Reset Timing Diagram

Semiconductor Group 11 1998-11-01

TLE 4279

V

Ι

t

<

RR

V

RT

V

Q

Ι

V

d

d

=

dt

C

D

V

D

t

d

t

RR

V

DT

V

ST

V

RO

Power-on-Reset Voltage Dip Secondary Overload

Thermal
Shutdown

Undervoltage

at Input

Sence Input Timing Diagram

at OutputSpike

AED01542

Semiconductor Group 12 1998-11-01

TLE 4279

Charge Current Id versus

T

Temperature

16

Aµ

Ι

d

14

12

10

8

6

4

2

0

-40

j

V

= 13.5 V

Ι

1.0 V=

V

C

04080120 C 160

AED01803

T

j

Switching Voltage V

T

Temperature

j

3.2
V

V

D

2.8

2.4

2.0

1.6

1.2

0.8

0.4

0

-40

04080120 C 160

and V

dt

V

= 13.5 V

Ι

V

dt

V

st

versus

st

AED01804

T

j

Drop Voltage

V

Output Current

500

V

dr

mV

400

300

T

200

100

0

0

30 60 90 120 180mA

versus

dr

I

Q

j

T

C125=

=25C

j

AED01805

Ι

Q

Reset Switching Threshold
versus Temperature Tj

1.7

V

V

re

1.6

1.5

1.4

1.3

1.2

1.1

1.0

0.9

-40

04080120 C 160

V

re

AED01806

T

j

Semiconductor Group 13 1998-11-01

TLE 4279

Current Consumption Iq versus

V

Input Voltage

30

Ι

q

mA

25

20

15

10

5

0

0

I

Ω

33=

R

L

R

=50

Ω

L

Ω

100=

R

L

R

= 200

L

10 20 30 40

AED01807

Ω

V50

V

Ι

Output Voltage
Input Voltage

12

V

Q

V

10

8

6

4

2

0

0

V

246

V

versus

Q

I

R

=50

L

AED01808

Ω

8 V10

V

Ι

Sense Threshold

V

si

versus Temperature Tj

1.6

V

si

V

V

= 13.5 V

1.5

1.4

1.3

1.2

1.1

1.0

-40 04080120 C 160

Ι

Sense Output High

Sense Output Low

AED01809

T

j

Output Voltage
Temperature

5.2

V

Q

V

5.1

5.0

4.9

4.8

4.7

4.6

-40

T

04080

V

j

Q

versus

V

= 13.5 V

Ι

AED01671

120 C 160

T

j

Semiconductor Group 14 1998-11-01

TLE 4279

Output Current IQ versus

V

Input Voltage

350

Ι

mA

Q

300

250

200

150

100

50

0

0

I

=25C

T

j

T

10 20 30

C125=

j

AED01810

40 V50

V

Ι

Current Consumption

I

Output Current

12

Ι

q

mA

10

8

6

4

2

0

0

20 40 60 80 120mA

Q

V

Ι

T

j

13.5 V=

=25C

I

versus

q

AED01811

Ι

Q

Current Consumption

I

10

Q

13.5 V=

V

Ι

=25C

T

j

20 30 40 50

Output Current

1.6

mA

Ι

q

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

0

I

versus

q

AED01812

mA

Ι

Q

Semiconductor Group 15 1998-11-01

Package Outlines

P-DIP-8-4

(Plastic Dual In-line Package)

TLE 4279

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our

Data Book “Package Information”

GPD05583

Dimensions in mm

Semiconductor Group 16 1998-11-01

P-DSO-8-1 (SMD)

(Plastic Dual Small Outline Package)

TLE 4279

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our

Data Book “Package Information”

GPS05121

SMD = Surface Mounted Device

Semiconductor Group 17 1998-11-01

Dimensions in mm

P-DSO-20-6 (SMD)

(Plastic Dual Small Outline Package)

1.27

+0.15

0.35

2)

0.2 24x

TLE 4279

0.35 x 45˚

-0.2

-0.1

0.2

2.45

2.65 max

0.1

1120

7.6

10.3

-0.2

0.4

±0.3

GPS05094

1)

+0.8

+0.09

0.23

8˚ max

110

12.8

-0.2

1)

Index Marking

1) Does not include plastic or metal protrusions of 0.15 max per side

2) Does not include dambar protrusion of 0.05 max per side

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our

Data Book “Package Information”

SMD = Surface Mounted Device

Dimensions in mm

Semiconductor Group 18 1998-11-01

P-DSO-14-4 (SMD)

(Plastic Dual Small Outline Package)

-0.1

0.2

-0.2

1.45

4

-0.2

1.75 max

TLE 4279

0.35 x 45˚

1)

+0.06

0.19

0.35

1.27

+0.15

2)

0.1

0.2 14x

±0.2

6

0.4

+0.8

8˚ max.

14 8

17

8.75

-0.2

1)

Index Marking

1) Does not include plastic or metal protrusion of 0.15 max. per side

2) Does not include dambar protrusion of 0.05 max. per side

GPS05093

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our

Data Book “Package Information”

SMD = Surface Mounted Device

Dimensions in mm

Semiconductor Group 19 1998-11-01