Datasheet TEA1065T, TEA1065 Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TEA1065

Versatile telephone transmission
circuit with dialler interface

Product specification
File under Integrated Circuits, IC03A

March 1994

Philips Semiconductors Product specification

Versatile telephone transmission circuit with
dialler interface

FEATURES

• Current and voltage regulator mode with adjustable
static resistances

• Provides supply for external circuitry

• Symmetrical high-impedance inputs for piezoelectric

microphone

• Asymmetrical high-impedance input for electret
microphone

• DTMF signal input with confidence tone

• Mute input for pulse or DTMF dialling

• Power-down input for pulse dial or register recall

• Digital pulse input to drive an external switch transistor

• Receiving amplifier for magnetic, dynamic or

piezoelectric earpieces

ORDERING INFORMATION

EXTENDED TYPE

NUMBER

PINS PIN POSITION MATERIAL CODE

TEA1065 24 DIL plastic SOT101L
TEA1065T 24 SO24 plastic SOT137A

• Large gain setting range on microphone and earpiece
amplifiers

• Line loss compensation facility, line current dependent
(on microphone and earpiece amplifiers)

• Adjustable gain control

• DC line voltage adjustment facility

GENERAL DESCRIPTION

The TEA1065 is a bipolar integrated circuit which performs
all speech and line interface functions that are required in
fully electronic telephone sets with adjustable DC mask.
The circuit performs electronic switching between dialling
and speech internally.

PACKAGE

TEA1065

Notes

1. SOT101-1; 1998 Jun 18.

2. SOT137-1; 1998 Jun 18.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V
I
I

LN
line
CC

line voltage I

= 15 mA 4.25 4.45 4.65 V

line

normal operation line current range 10 − 150 mA
internal supply consumption

power-down input LOW − 1.14 1.5 mA
power-down input HIGH − 73 105 µA

V

CC

supply voltage for peripherals I

= 15 mA;

line

MUTE input
HIGH

IP= 1.2 mA 2.7 −−V

= 1.55 mA 2.5 −−V

I

P

G

V

voltage gain range

microphone amplifier 30 − 46 dB
earpiece amplifier 20 − 45 dB

∆G

V

line loss compensation

gain control range −5.5 −5.9 −6.3 dB

T

amb

operating ambient temperature range −25 −+75 °C

March 1994 2

Philips Semiconductors Product specification

Versatile telephone transmission circuit with
dialler interface

handbook, full pagewidth

DTMF

MUTE

MIC+
MIC−

V

CC
PD

17

IR

+

−

TEA1065

8
7

19

dB

+

−

−
+

20
21

SUPPLY AND

18

REFERENCE

CONTROL
CURRENT

CURRENT

REFERENCE

TEA1065

6

GAR

−

+

−

+

−
+

BANDGAP

REFERENCE

+

−

LINE
CURRENT
CONTROL

5

QR+

4

QR−

2

GAS1

1

LN

24

SLPE

3

GAS2

11

VBG

13

REFI

12

DOC

2216

23 9 15

V

EE

REG AGC STAB

Fig.1 Block diagram.

March 1994 3

DPI

14

10

VSI

CURL

MBA557

Philips Semiconductors Product specification

V ersatile telephone transmission circuit with
dialler interface

PINNING

SYMBOL PIN DESCRIPTION

LN 1 positive line terminal
GAS1 2 gain adjustment; sending amplifier
GAS2 3 gain adjustment; sending amplifier
QR− 4 inverting output; receiving amplifier
QR+ 5 non-inverting output; receiving

amplifier
GAR 6 gain adjustment; receiving amplifier
MIC− 7 inverting microphone input
MIC+ 8 non-inverting microphone input
STAB 9 current stabilizer
DPI 10 digital pulse input
VBG 11 bandgap output reference
DOC 12 drive current output
REFI 13 reference voltage input
VSI 14 voltage sense input
CURL 15 current limitation input
V

EE

IR 17 receiving amplifier input
PD 18 power-down input
DTMF 19 dual-tone multifrequency input
MUTE 20 MUTE input
V

CC

REG 22 voltage regulator decoupling
AGC 23 automatic gain control input
SLPE 24 slope (DC resistance) adjustment

16 negative line terminal

21 positive supply decoupling

handbook, halfpage

1

LN

GAS1

2
3

GAS2

4

QR−
QR+

5
6

GAR
MIC−
MIC+

STAB

DPI

VBG

DOC

7
8

9
10
11
12

TEA1065

MBA551

Fig.2 Pinning diagram.

TEA1065

SLPE

24
23

AGC

22

REG
V

21

CC

20

MUTE

19

DTMF

18

PD

17

IR
V

16

EE

CURL

15

VSI

14

REFI

13

March 1994 4

Philips Semiconductors Product specification

V ersatile telephone transmission circuit with
dialler interface

FUNCTIONAL DESCRIPTION
Supply: V

The circuit and its peripherals are usually supplied from the
telephone line. The circuit develops its own supply voltage
at V

CC

and SLPE (pins 1 and 24). The internal supply requires a
decoupling capacitor between VCCand VEE(pin 16); the
internal voltage regulator has to be decoupled by a
capacitor from REG (pin 22) to VEE. The internal current
stabilizer is set by a 3.6 kΩ resistor connected between
STAB (pin 9) and VEE.
The TEA1065 can be set either in a DC voltage regulator
mode or in a DC current regulator mode. The DC mask can
be selected by connecting the appropriate external
components to the dedicated pins (VSI, REFI, DOC,
VBG).
When the DC current regulator mode is not required it can
be cancelled by connecting pin VSI to VEE; pins REFI,
VBG and DOC are left open-circuit.

Voltage regulator mode

The voltage regulator mode is achieved when the line
current is less than the current I
With R13 = R14 = 30 kΩ, the current I
(Ip= 0 mA).

, LN, SLPE, REG and STAB

CC

(pin 21) and regulates its voltage drop between LN

as illustrated in Fig.3.

knee

= 30 mA

knee

TEA1065

This line current value will be reached when the voltage on
pin VSI (almost equal to the voltage on pin SLPE) exceeds
the voltage on pin REFI (equal to the voltage on pin VBG
divided by the resistor tap R13, R14). For other values of
R13 and R14, the I
formula:

I

knee=ICC

+ IP+ (VBG/R9) × {R14/(R14 + R13)}

− (R15/R9) × IO(VSI)

ICCis the current required by the circuit itself
(typ. 1.14 mA). IPis the current required by the peripheral
circuits connected between VCCand VEE. I
output current from pin VSI (typ. 2.5 µA).

The DC slope of the V
determined by R9 (R9 = R9a + R9b) in series with the
rdsof the external line current control transistor (see Fig.4;
rds= ∂VGS/∂IDat VGS=VDS).

Current regulator mode

The current regulator mode is achieved when the line
current is greater than I
V

curve is approximately 1300 Ω with R9 = 20 Ω,

line/Iline

R16 = 1 MΩ, R13 = R14 = 30 kΩ. For other values of
these resistances, the slope value can be approximated by
the following formula:

R9 × {1 + R16 × (1/R13 + 1/R14)}

current is given by the following

knee

O(VSI)

curve is, in this mode,

line/Iline

. In this mode, the slope of the

knee

is the

handbook, full pagewidth

line

current

I

knee

0

0

voltage

regulator

mode

current

regulator

mode

Fig.3 Voltage and current regulator mode.

March 1994 5

MBA567

set

voltage

Philips Semiconductors Product specification

V ersatile telephone transmission circuit with
dialler interface

The DC current flowing into the set is determined by the
exchange supply voltage (V
subscriber line (R

) and the DC voltage on the subscriber

line

set (see Fig.4).
If the line current exceeds ICC+ 0.3 mA, required by the
circuit itself (ICC≈ 1.14 mA), plus the current Iprequired by
the peripheral circuits connected to VCCthen the voltage
regulator will divert the excess current via LN.

VLN=V

where: V

ref

+ I

V

ref

× R9 =

SLPE

+ (I

ref

− ICC− 0.3 × 10−3− Ip) × R9

line

is an internally generated temperature
compensated reference voltage of 4.18 V and R9 is an
external resistor connected between SLPE and VEE.

The preferred value of R9 is 20 Ω. Changing R9 will
influence the microphone gain, gain control
characteristics, sidetone and the maximum output swing
on LN. In this instance, the voltage on the line (excluding
the diode rectifier bridge; see Fig.4) is:

V

line=VLN

+ VGS+ R16 × I

where: VGSis the voltage drop between the gate and
source terminal of the external line current control
transistor and I
(I

= 0 in the voltage regulator mode and increases with

DOC

is the current sunk by pin DOC

DOC

), the DC resistance of the

exch

DOC

TEA1065

I

in the current regulator mode).

line

Under normal conditions I
for the voltage regulator mode (I
behaviour of the circuit is equal to a 4.18 V voltage
regulator diode with an internal resistance of R9 in series
with the V

of the external line current control

GSon

transistor. For the current regulator mode (I
static behaviour of the circuit is equal to a 4.18 V voltage
regulator diode with an internal resistance of R9 in series
with the V

of the external line current control transistor

GSon

and also in series with a DC voltage source R16
× I

(the preferred value of R16 is 1 MΩ at this value the

DOC

current I

is negligible compared to I

DOC

In the audio frequency range the dynamic impedance
between LN and VEEis equal to R1 (see Fig.8). The
internal reference voltage V
of an external resistor RVA. This resistor, connected
between LN and REG, will decrease the internal reference
voltage. When RVAis connected between REG and SLPE
the internal reference voltage will increase.
The maximum allowed line current is given in Figs 5 and 6,
where the current is shown as a function of the required
reference voltage, ambient temperature and applied
package.

>> ICC+ 0.3 mA + Ipand

SLPE

< I

line

can be adjusted by means

ref

), the static

knee

line

).

line

> I

knee

), the

handbook, full pagewidth

V

R

exch

exch

R

line

I

DOC

V

line

I

R16

TEA1065

line

I

SLPE

+ 0.5 mA

DC
AC

22 9
REG V

C3 R5 R9

STAB

Fig.4 Supply arrangement.

March 1994 6

LNDOC

12112

24

SLPE

R1

I

CC

V

CC

0.3 mA

16

EE

C1

peripheral

circuits

MBA550

I

p

Philips Semiconductors Product specification

V ersatile telephone transmission circuit with
dialler interface

The current Ip, available from VCCfor supplying peripheral
circuits, depends on the external components and on the
line current. Fig.7 shows this current for VCC> 2.2 V and
for VCC> 3 V, where 3 V is the minimum supply voltage for
most CMOS circuits including a diode voltage drop for a
back-up diode. If MUTE is LOW the available current is
further reduced when the receiving amplifier is driven
(earpiece amplifier supplied from VCC).

handbook, halfpage

170

I

LN

(mA)

150

130

MBA570

(1)

handbook, halfpage

170

I

LN

(mA)

150

130

TEA1065

MBA571

(1)

110

(2)

90

70

50

30

212

46810

VLN-V

SLPE

(V)

110

90

70

50

30

212

T

amb

(1) 35 °C
(2) 45 °C

T

amb

(1) 65 °C
(2) 75 °C

Fig.5 TEA1065 safe operating area.

P

tot

1.2 W

1.0 W

(3) 55 °C
(4) 65 °C
(5) 75 °C

Fig.6 TEA1065T safe operating area.

(2)

(3)

(4)

(5)

46810

V

LN-VSLPE

P

tot

(V)

1.2 W

1.07 W

0.93 W

0.8 W

0.67 W

March 1994 7

Philips Semiconductors Product specification

V ersatile telephone transmission circuit with
dialler interface

handbook, halfpage

3

I

P

(mA)

2

1

0

(1)

(2)

(3)

(4)

012 4

3

VCC (V)

TEA1065

MBA569

I

= 15 mA at VLN= 4.45 V

line

R1 = 620 Ω
R9 = 20 Ω

Curve (1) and (3) are valid when the receiving amplifier is not driven or when MUTE =HIGH, curves (2) and (4)
are valid when MUTE = LOW and the receiving amplifier is driven, V
(1) = 2.2 mA; (2) = 1.77 mA; (3) = 0.78 mA and (4) = 0.36 mA.

= 150 mV, RL= 150 Ω (asymmetrical).

o(rms)

Fig.7 Maximum current Ipavailable from VCCfor external (peripheral) circuitry with VCC> 2.2 V and VCC> 3 V.

R1

V

C1

MBA552

CC

LN

V

EE

andbook, halfpage

SLPE

Leq=C3×R9 × R
Rp= 17.5 kΩ

L

eq

V

R9
20 Ω

p

ref

R

p

REG

C3

4.7 µF

Fig.8 Equivalent circuit impedance between LN

and VEE.

March 1994 8

Philips Semiconductors Product specification

V ersatile telephone transmission circuit with
dialler interface

Microphone inputs MIC+ and MIC− and gain
adjustment connections GAS1 and GAS2

The TEA1065 has symmetrical microphone inputs, its
input impedance is 40.8 kΩ (2 × 20.4 kΩ) and its voltage
gain is typ. 38 dB with R7 = 68 kΩ. Either dynamic,
magnetic or piezoelectric microphones can be used, or an
electret microphone with a built-in FET buffer.
Arrangements for the microphones types are illustrated in
Fig.9.

handbook, full pagewidth

MIC+

(1)

MIC−

8

7

MIC−

MIC+

TEA1065

The gain of the microphone amplifier is proportional to
external resistor R7, connected between GAS1 and
GAS2, which can be adjusted between 30 dB and 46 dB to
suit the sensitivity of the transducer.

An external 100 pF capacitor (C6) is required between
GAS1 and SLPE to ensure stability. A larger value of C6
may be chosen to obtain a first-order low-pass filter. The
“cut-off” frequency corresponds with the time constant
R7 × C6.

V

CC

21

7

8

16

V

EE

MIC+

MIC−

8

7

MBA553

(a) (b)

(a) magnetic or dynamic microphone,
the resistor (1) may be connected to
reduce the terminating impedance, or
for sensitive types a resistive
attenuator can be used to prevent
overloading the microphone inputs;

(c)

(b) electret microphone; (c) piezoelectric microphone.

Fig.9 Microphone arrangements.

March 1994 9

Philips Semiconductors Product specification

V ersatile telephone transmission circuit with
dialler interface

MUTE input

When MUTE = HIGH the DTMF input is enabled and the
microphone and receiving amplifier inputs are inhibited.
When MUTE = LOW or open-circuit the DTMF input is
inhibited and the microphone and receiving amplifier
inputs are enabled. Switching the MUTE input will cause
negligible clicks at the earpiece outputs and on the line. An
electrostatic discharge protection diode is connected
between pin MUTE and pin VCC(pins 20 and 21).

Dual-tone multifrequency input DTMF

When the DTMF input is enabled, dialling tones may be
sent onto the line. The voltage gain from DTMF to LN is
typ. 12.5 dB less than the gain of the microphone amplifier
and varies with R7 in the same way as the gain of the
microphone amplifier. This means that the tone level at the
DTMF input has to be adjusted after setting the gain of the
microphone amplifier. When R7 = 68 kΩ the gain is
typically 25.5 dB. The signalling tones can be heard in the
earpiece at a low level (confidence tone).

Receiving amplifiers: IR, QR+, QR− and GAR

The receiving amplifier has one input IR and two
complementary outputs, QR+ (non-inverting) and

TEA1065

QR− (inverting). These outputs may be used for
single-ended or differential drive, depending on the type
and sensitivity of the earpiece used (see Fig.10). Gain
from IR to QR+ is typically 31 dB with R4 = 100 kΩ, which
is sufficient for low-impedance magnetic or dynamic
earpieces which are suitable for single-ended drive. By
using both outputs (differential drive) the gain is increased
by 6 dB. Differential drive can be used when earpiece
impedance exceeds 450 Ω as with high impedance
dynamic, magnetic or piezoelectric earpieces.

The output voltage of the receiving amplifier is specified for
continuous-wave drive. The maximum output voltage will
be higher under speech conditions where the ratio of peak
and RMS value is higher.

The gain of the receiving amplifier can be adjusted over a
range of −11 dB to +8 dB to suit the sensitivity of the
transducer that is used. The gain is proportional to external
resistor R4 connected between GAR and QR+.

Two external capacitors, C4 = 100 pF and C7 = 1 nF, are
necessary to ensure stability. A larger value of C4 may be
chosen to obtain a first-order low-pass filter. The “cut-off”
frequency corresponds with the time constant R4 × C4.

handbook, full pagewidth

16

QR+

5

QR−

4

V

EE

(a) (b) (c) (d)

QR+

5

QR−

4

Fig.10 Alternative receiver arrangements:

(a) dynamic earpiece with an impedance less than 450 Ω;
(b) dynamic earpiece with an impedance more than 450 Ω;
(c) magnetic earpiece with an impedance more than 450 Ω, resistor (1) may be connected to prevent
distortion (inductive load);
(d) piezoelectric earpiece, resistor (2) is required to increase the phase margin (stability with capacitive
load).

March 1994 10

5

QR−

4

5

4

(1)

QR+

QR+

QR−

(2)

MBA554

Philips Semiconductors Product specification

V ersatile telephone transmission circuit with

TEA1065

dialler interface

Automatic gain control

Automatic compensation of line loss is obtained by connecting a resistor (R6) between AGC and VEE. The automatic gain
control varies the gain of the microphone amplifier and receiving amplifier in accordance with the DC line current (see
Fig.12). The control range is 5.9 dB; this corresponds to a line length of 3.5 km of twisted pair cable (see Fig.11). The
DTMF gain is not affected by this feature.

If automatic line loss compensation is not required the AGC pin can be left open-circuit, the amplifiers then give their
maximum gain.

handbook, full pagewidth

75 µH75 µH

24.3 nF

13 nF

24.3 nF

75 µH75 µH

34.8 Ω34.8 Ω

34.8 Ω34.8 Ω

MBA572

andbook, full pagewidth

Fig.11 Typical 0.5 km line cell model used for automatic gain control optimization.

MBA549

806040200

(mA)

∆G
(dB)

1

R6 =

I

∞

line

v

0

−1

−3

−5

−7

R6 = 187 kΩ

118 kΩ 147 kΩ86.6 kΩ

Fig.12 Variation of gain as a function of line current with R6 as a parameter; R9 = 20 Ω.

March 1994 11

Philips Semiconductors Product specification

V ersatile telephone transmission circuit with
dialler interface

Power-down input PD

During pulse dialling or register recall (timed-loop-break)
the telephone line is interrupted, consequently it provides
no supply for the transmission circuit and the peripherals
connected to VCC. These gaps have to be bridged by the
charge in the smoothing capacitor C1. The requirement on
this capacitor is relaxed by applying a HIGH level to the PD
input during the loop-break. This reduces the internal
supply current from typ. 1.14 mA to 73 µA.

A HIGH level at PD also disconnects the capacitor at REG
which results in the voltage stabilizer having no switch-on
delay after line interruptions. This results in no contribution
of the IC to the current waveform during pulse dialling or
register recall. When this facility is not required PD may be
left open-circuit or connected to VEE. An electrostatic
discharge protection diode is connected between pin PD
and VCC.

Digital pulse input DPI

TEA1065

activated.
The voltage applied on pin REFI represents a fraction of
the bandgap reference voltage given by pin VBG (resistor
tap R13 and R14) in order to determine I

Drive current output DOC

Pin DOC drives the external line current control transistor
in order to achieve line interruption during pulse dialling (or
register recall) and also the DC slope when I
The current sunk by pin DOC is determined by the voltage
on pin VSI in comparison with the voltage on pin VBG
divided by the resistor tap R13 and R14.
When pin DPI is activated, pin DOC changes to a low
voltage (by trying to sink typ. 900 µA to VEE) to switch off
the external line current control transistor.

Bandgap reference output VBG

This output provides a voltage reference to set the knee
line current with the following formula:

knee

.

line

> I

knee

.

A HIGH level at DPI creates a current which flows from pin
DOC to V

in order to interrupt the line current by the

EE

external line current control transistor (see Fig.18;
MOSFET BUK554). A LOW level (or pin left open-circuit)
disables this current to provide the normal DC regulation
(voltage or current). A simple application without
regulation of current in pulse dialling mode is given in
Fig.18.

When DPI is activated (HIGH level), the external line
current control transistor is switched off resulting in no
current in the TEA1065. The voltage on pin SLPE
becomes zero and capacitor C15 discharges cancelling
the current regulation when DPI becomes inactive (LOW
level).

To provide a constant regulation (in speech mode and
pulse mode), an external transistor is required to keep C15
charged during DPI active (see Fig.19 in which the Field
Effect Transistor BSJ177 is directly driven by the DPI
signal).
An electrostatic discharge protection diode is connected
between pin DPI and pin VCC.

Voltage sense input and reference voltage input VSI and REFI

I

knee=ICC

(VBG/R9) × {R14/(R14 + R13)} − (R15/R9) × 2.5 × 10

+ IP+

−6

In order to improve stability, a capacitive load is not
allowed on this output.

Current limit input CURL

This input is applied to the base of an internal NPN
transistor which has its collector connected to pin DOC
and its emitter to V

(see Fig.13). The transistor limits the

EE

line current just after hook-off or during line transients to a
value given by the following formula:

I

= I(R1) + VBE/R9b

hook-off

VBEis the base-emitter voltage of the transistor
(typ. 700 mV at 25 °C). I(R1) is the current flowing through
R1 to charge C1 just after hook-off.

handbook, halfpage

CURL

DOC

IC (collector current)

The voltage on pin VSI represents the DC voltage of pin
SLPE. The RC filter (R15 × C15) is also intended to
disable the DC regulation when C15 is shunted or not yet
charged (especially directly after hook-off). The time
constant R15 × C15 determines approximately the time
when no regulation (except CURL pin limitation) is

March 1994 12

V

MBA556

EE

Fig.13 Internal current limiting transistor.

Philips Semiconductors Product specification

V ersatile telephone transmission circuit with
dialler interface

The maximum hook-off current then becomes:
I

hook-off=VZ

(R9a + R9b + R1)/(R1 × R9b)
where VZis the Zener voltage of diode D5 (see Fig.18).

Side-tone suppression

Suppression of the transmitted signal in the earpiece is
obtained by the anti-sidetone network comprising R1//Z
R2, R3, R9 and Z
is obtained when the following conditions are fulfilled:

a) R9 × R2 = R1 × (R3 + R8)
b) k = R3 × (R8 + R9)/(R2 × R9)
c) Z

bal

The scale factor k is chosen to meet the compatibility with
a standard capacitor from the E6 or E12 range for Z

In practice Z
line type. Therefore, the value chosen for Z
an average line length giving satisfactory sidetone
suppression with long and short times. The suppression

/R1 + VBE×

=k×Z

line

(see Fig.18). Maximum compensation

bal

line

bal.

varies considerably with the line length and

should be for

bal

line

,

TEA1065

also depends on the accuracy of the match between

and the impedance of the average line.

Z

bal

Example

With k = 1, R1 = 619 Ω, R9 = 20 Ω and an average line
impedance represented by 270Ω+ (120 nF // 1100Ω), the
calculation results in:

• R2 = 130 kΩ

• R3 = 3650 Ω

• R8 = 715 Ω

The anti-sidetone network for the TEA1060 family, shown
in Fig.15, attenuates the signal received from the line by
32 dB before it enters the receiving amplifier. The
attenuation is almost constant over the whole
audio-frequency range.

Note

More information on the balancing of the anti-sidetone
bridges can be obtained in our publication

speech transmission ICs for electronic telephone sets”

order number 9398 341 10011.

“Versatile

,

handbook, full pagewidth

I

line

I

hook-off

0

0

hook-off speech mode pulse dialling mode

MBA568

time

Fig.14 Example of line current shape in pulse dialling mode (see also Fig.18).

March 1994 13

Philips Semiconductors Product specification

Versatile telephone transmission circuit with
dialler interface

handbook, full pagewidth

Z

line

V

EE

R1

R9

Fig.15 Equivalent circuit of TEA1060 family anti-sidetone bridge.

LIMITING VALUES

In accordance with the absolute maximum system (IEC 134)

LN

SLPE

R2

i

m

R8

R3

TEA1065

IR

R

t

Z

bal

MBA555

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V
V
V

LN
DOC
LN

positive line voltage continuous − 12 V
positive DOC voltage continuous − 12 V
repetitive line voltage during

− 13.2 V

switch-on or line interruption

I

LN

V

I

line current (see also Fig.5 and 6) − 150 mA
input voltage on pins other than LN,

VEE− 0.7 VCC+ 0.7 V

DOC, VSI, REFI and CURL

P

tot

T

stg

T

amb

total power dissipation see Figs 5 and 6
storage temperature range −40 + 125 °C
operating ambient temperature

−25 +75 °C

range

T

j

junction temperature −+125 °C

THERMAL RESISTANCE

SYMBOL PARAMETER TYP. MAX. UNIT

R
R

th j-a
th j-a

from junction to ambient in free air; TEA1065 − 50 K/W
from junction to ambient in free air; TEA1065T

(1)

− 75 K/W

Note

1. TEA1065T is mounted on glassy epoxy board 28.5 × 19.1 × 1.5 mm

HANDLING

Every pin withstands the ESD test in accordance with MIL-STD-883C class 2, method 3015 (HBM 1500 Ω, 100 pF,
3 positive pulses and 3 negative pulses on each pin as a function of pin V

EE

.

March 1994 14

Philips Semiconductors Product specification

V ersatile telephone transmission circuit with

TEA1065

dialler interface

CHARACTERISTICS

= 10 to 150 mA; VEE= 0 V; f = 800 Hz; T

I

LN

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply LN and V

V

∆V
V

I

CC

LN

LN

LN

voltage drop over circuit I

/∆T variation with temperature I

voltage drop over circuit I

supply current PD = LOW; VCC= 2.8 V − 1.14 1.5 mA

(pins 1 and 21)

CC

Microphone inputs MIC+ and MIC− (pins 8 and 7)

 Z

 input impedance 18.5 20.4 24.3 kΩ

I

G

v

∆G

f variation with frequency I

v

voltage gain I

referred to 800 Hz f = 300 to 3400 Hz

∆GvT variation with temperature I

referred to 25 °CT

=25°C; R9 = 20 Ω; unless otherwise specified

amb

= 5 mA 3.95 4.25 4.55 V

line

I

= 15 mA 4.25 4.45 4.65 V

line

= 100 mA 5.4 6.1 6.7 V

I

line

= 140 mA −−7.5 V

I

line

= 15 mA −3 −1 +1 mV/K

line

= 15 mA

line

R

VA=R1-22

R

VA=R22-24

PD = HIGH; V

= 15 mA; R7 = 68 kΩ 37 38 39 dB

line

= 15 mA; −0.5 ±0.2 +0.5 dB

line

= 50 mA; −±0.5 − dB

line

amb

= 68 kΩ 3.6 3.9 4.15 V

= 39 kΩ 4.7 5.0 5.3 V

= 2.8 V − 73 105 µA

CC

= −25 to 75 °C;

without R6

Dual-tone multi-frequency input DTMF (pin 19)

 Z

 input impedance 16.8 20.7 24.6 kΩ

I

G

v

∆G

f variation with frequency I

v

voltage gain I

= 15 mA; R7 = 68 kΩ 24.5 25.5 26.5 dB

line

= 15 mA −0.5 ±0.2 +0.5 dB

line

referred to 800 Hz f = 300 to 3400 Hz

∆GvT variation with temperature I

referred to 25 °CT

= 50 mA; −±0.5 − dB

line

= −25 to +75 °C

amb

Gain adjustment GAS1 and GAS2 (pin 2 and 3)
∆G

v

gain variation with R7 −8 −+8dB
connected between pins 2 and 3;
transmitting amplifier

March 1994 15

Philips Semiconductors Product specification

Versatile telephone transmission circuit with

TEA1065

dialler interface

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Transmitting amplifier output LN (pin 1)

V

LN(rms)

V

no(rms)

output voltage (RMS value) I

noise output voltage (RMS I
value) R7 = 68 kΩ;

Receiving amplifier input IR (pin 17)
Z

I

input impedance 17 21 25 kΩ
Receiving amplifier outputs QR+ and QR− (pin 5 and 4)
Z

O

G

v

∆G

f variation with frequency f = 300 to 3400 Hz −0.5 ±0.2 +0.5 dB

v

output impedance − 4 −Ω

voltage gain I

referred to 800 Hz
∆G

T variation with temperature

v

referred to 25 °C
V

O(rms)

output voltage (RMS value) I

= 15 mA

line

d

= 2% 1.9 2.3 − V

tot

d

= 10% − 2.6 − V

tot

= 15 mA; −−68 − dBmp

line

pin 7 and 8 open-circuit
psophometrically
weighted (P53 curve);
control transistor included
(MOS BUK554 type see
Fig.18)

= 15 mA; R4 = 100 kΩ

line

single-ended; RT = 300 Ω 30 31 32 dB
differential; RT = 600 Ω 36 37 38 dB

without R6; I

= −25 to +75 °C

T

amb

= 15 mA; THD = 2%;

line

= 50 mA; −±0.2 − dB

line

sinewave drive;
R4 = 100 kΩ
single-ended; RT = 150 Ω 0.3 0.38 − V
differential; RT = 450 Ω 0.56 0.72 − V
differential; CT = 60 nF; 0.87 1.07 − V
(1500 Ω series resistor);
f = 3400 Hz
I

= 30 mA; differential; 1.02 1.22 − V

line

CT = 60 nF;
(1500 Ω series resistor);
f = 3400 Hz

V

O(rms)

noise output voltage (RMS I

= 15 mA;

line

value) R4 = 100 kΩ

single-ended; RT = 300 Ω− 50 −µV
differential; RT = 600 Ω− 100 −µV

March 1994 16

Philips Semiconductors Product specification

Versatile telephone transmission circuit with

TEA1065

dialler interface

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Gain adjustment GAR (pin 6)

∆G

v

Mute input MUTE (pin 20)
V

IH

V

IL

I

MUTE

∆G

v

G

v

Power-down input PD (pin 18)
V

IH

V

IL

I

PD

Automatic gain control input AGC (pin 23)
∆G

v

I

line

I

line

∆G

v

Current limiting input CURL (pin 15)
V

BE

H

FE

I

C(max)

receiving amplifier, gain −11 −+8dB

adjustment range

input voltage HIGH 1.5 − V

CC

V
input voltage LOW −−0.3 V
input current − 815µA
change of microphone amplifier MUTE = HIGH −−70 − dB
gain
voltage gain from DTMF input MUTE = HIGH; −19 −17 −15 dB
to QR+ or QR− R4 = 100 kΩ

single-ended; RT = 300 Ω

input voltage HIGH 1.5 - V

CC

V
input voltage LOW - - 0.3 V
input current - 2.5 5.0 µA

controlling the gain from IR to R6 = 118 kΩ−5.5 −5.9 −6.3 dB
QR+, QR− and the gain from
MIC+, MIC− to LN; gain control
range with respect to
I

= 15 mA

line

highest line current for − 28 − mA
maximum gain
lowest line current for minimum − 50 − mA
gain
change of gain between − -1.5 − dB
I

= 15 and 35.5 mA

line

base-emitter voltage drop of see Fig.13; − 0.7 − V
internal transistor I

=50µA=I

C

DOC

current gain of internal see Fig.13; 60 120 −
transistor I

=50µA=I

C

DOC

maximum collector current of see Fig.13 −−2mA
internal transistor

Bandgap reference voltage output VBG (pin 12)
V

BG

I

BG

Z

O

reference voltage − 1.22 − V
output drive capability note 1 −100 - +50 µA
output impedance − 12 −Ω

March 1994 17

Philips Semiconductors Product specification

V ersatile telephone transmission circuit with

TEA1065

dialler interface

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Voltage sense input VSI (pin 14)

I

O

output current pin VSI connected to V

Reference input REFI (pin 13)
I

O

output current −−2.0 mA

Drive current output DOC (pin 11)
I

O

output current REFI connected to VEE; 120 300 −µA

VSI not connected;
DPI = LOW
REFI not connected; 200 900 −µA
VSI connected to V

EE

;

DPI = HIGH
Digital pulse input DPI (pin 10)
V

V
I

IH
IL

DPI

input voltage HIGH 1.5 − V
input voltage LOW −−0.3 V
input current − 2.5 5 µA

Note

1. No capacitive load on the VBGoutput. Positive current is defined as conventional current flow into a device.
Negative current is defined as conventional current flow out of a device.

−−2.5 −µA

EE

CC

V

March 1994 18

Philips Semiconductors Product specification

V ersatile telephone transmission circuit with
dialler interface

handbook, full pagewidth

100 µF

C1

10 µF

21

V

CC

17

IR

8

MIC+

V

i

V

i

7

MIC−

19

DTMF

20

MUTE

18

PD

14

VSI

V

EE

R1

620 Ω

13

REFI

12 1

DOC

LN

TEA1065

REG AGC STAB

232216 9

C3

R6

4.7

118

µF

kΩ

R5

3.6
kΩ

VBG

CURL

GAS1

GAS2

SLPE

11

QR−

QR+

GAR

DPI

24

R9
20 Ω

TEA1065

I

line

4

5

15

6

2

10

3

R4

100

kΩ

R7
68
kΩ

100 µF

R

600 Ω

C4
100 pF

C7 1 nF

C6
100 pF

V

o

L

5 to

140 mA

MBA558

Voltage gain is defined as Gv= 20 Log Vo/Vi. For measuring the gain from MIC+
and MIC− the MUTE input should be LOW or open-circuit, for measuring the DTMF
input MUTE should be HIGH. Inputs not under test should be open-circuit except VSI
that should be connected to V

.

EE

Fig.16 Test circuit for defining voltage gain of MIC+, MIC− and DTMF inputs.

March 1994 19

Philips Semiconductors Product specification

V ersatile telephone transmission circuit with
dialler interface

handbook, full pagewidth

C1

100 µF

V

21

V

CC

17

IR

8

MIC+

7

MIC−

19

DTMF

20

MUTE

10 µF

i

18

PD

14

VSI

V

EE

R1

620 Ω

13

REFI

12 1

DOC

LN

TEA1065

REG AGC STAB

232216 9

C3
µF

R6

118

kΩ

4.7

R5

3.6
kΩ

VBG

CURL

GAS1

GAS2

SLPE

11

QR−

QR+

GAR

DPI

24

R9
20 Ω

TEA1065

I

line

V

o

4

5

15

6

2

10

3

Z

R4

100

kΩ

R7
68
kΩ

100 µF

L

R

600 Ω

C4
100 pF

C7 1 nF

C6
100 pF

L

5 to

140 mA

MBA559

Voltage gain is defined as Gv= 20 Log  Vo/Vi.

Fig.17 Test circuit for defining voltage gain of the receiving amplifier.

March 1994 20

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March 1994 21

handbook, full pagewidth

Philips Semiconductors Product specification

Versatile telephone transmission circuit with

dialler interface

telephone

line

BAS11

(4×)

D1

D4

D2

D3

D5

BZX79c

BV2

R3

3.65
kΩ

R2
130 kΩ

R4

100 kΩ

Z

bal

C7

C5

100 nF

R11

1 nF

R8

715 Ω

C4
100 pF

17

4

5

6

8

7

15 Ω

IR

QR−

QR+

GAR

MIC+

MIC−

R9a

R9b

5 Ω

SLPE

R16

1 MΩ

GAS1

24

C6

100 pF

DOC

MOSN1
BUK554

12

1

LN

R1

620 Ω

TEA1065

GAS214VSI13REFI11VBG15CURL9STAB22REG

2

R7

68 kΩ

R15

15 kΩ

3

R13
30
kΩ

C15

6.8 µF

R14
30
kΩ

V

3.6

R5

kΩ

CC

+

MBA561

C1
100 µF

from dial

and

control circuits

−

TEA1065

21

19

DTMF

20

MUTE

18

PD

10

DPI

16

V

EE

R6

23

AGC

C3

4.7 µF

Fig.18 Typical application of the TEA1065, with a piezoelectric earpiece and DTMF dialling.

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March 1994 22

handbook, full pagewidth

Philips Semiconductors Product specification

Versatile telephone transmission circuit with

dialler interface

telephone

line

BAS11

(4×)

D1

D4

D2

D3

D5

BZX79c

BV2

R3

3.65
kΩ

R2
130 kΩ

R4

100 kΩ

Z

bal

C7

C5

100 nF

R11

1 nF

R8

715 Ω

C4
100 pF

17

4

5

6

8

7

15 Ω

IR

QR−

QR+

GAR

MIC+

MIC−

R9a

R9b

5 Ω

SLPE

R16

1 MΩ

GAS1

24

C6

100 pF

DOC

MOSN1
BUK554

12

1

LN

R1

620 Ω

TEA1065

GAS214VSI13REFI11VBG15CURL9STAB22REG

2

68 kΩ

15 kΩ

R7

R15

3

JFP1

BSJ177

C15

6.8 µF

R13
30
kΩ

R14
30
kΩ

V

R5

3.6
kΩ

CC

+

21

19

DTMF

20

MUTE

18

PD

10

DPI

16

V

EE

23

AGC

C3

4.7 µF

R6

MBA560

C1
100 µF

from dial

and

control circuits

−

TEA1065

DTMF dialling requires a different protection arrangement.

Fig.19 Typical application of the TEA1065, with a piezoelectric earpiece and pulse dialling.

Philips Semiconductors Product specification

Versatile telephone transmission circuit with
dialler interface

PACKAGE OUTLINES

DIP24: plastic dual in-line package; 24 leads (600 mil)

D

seating plane

L

Z

24

e

b

b

13

TEA1065

SOT101-1

M

E

A

2

A

A

1

w M

1

c

(e )

1

M

H

pin 1 index

1

0 5 10 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

A

A

UNIT

inches

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

max.

mm

OUTLINE
VERSION

SOT101-1

1 2

min.

max.

0.066

0.051

IEC JEDEC EIAJ

051G02 MO-015AD

1.7

1.3

b

b

1

0.53

0.38

0.021

0.015

0.32

0.23

0.013

0.009

REFERENCES

cD E e M

32.0

31.4

1.26

1.24

12

scale

14.1

13.7

0.56

0.54

E

(1)(1)

L

3.9

15.80

3.4

15.24

EUROPEAN

PROJECTION

M

0.62

0.60

w

H

E

17.15

15.90

0.68

0.63

0.252.54 15.24

0.010.10 0.60

ISSUE DATE

92-11-17
95-01-23

e

1

0.15

0.13

Z

max.

2.25.1 0.51 4.0

0.0870.20 0.020 0.16

(1)

March 1994 23

Philips Semiconductors Product specification

Versatile telephone transmission circuit with
dialler interface

SO24: plastic small outline package; 24 leads; body width 7.5 mm

D

c

y

Z

24

13

TEA1065

SOT137-1

E

H

E

A

X

v M

A

pin 1 index

1

e

0 5 10 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

mm

A

max.

2.65

0.10

A1A

0.30

0.10

0.012

0.004

2

2.45

2.25

0.096

0.089

A

0.25

0.01

b

3

p

0.49

0.32

0.36

0.23

0.019

0.013

0.014

0.009

UNIT

inches

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

(1)E(1) (1)

cD

15.6

15.2

0.61

0.60

12

w M

b

p

scale

eHELLpQ

7.6

1.27

7.4

0.30

0.050

0.29

10.65

10.00

0.419

0.394

A

1.4

0.055

Q

2

A

1

detail X

1.1

1.1

0.4

0.043

0.016

1.0

0.043

0.039

0.25

0.01

L

p

L

(A )

0.25 0.1

0.01

A

3

θ

ywv θ

Z

0.9

0.4

0.035

0.004

0.016

o

8

o

0

OUTLINE
VERSION

SOT137-1

IEC JEDEC EIAJ

075E05 MS-013AD

REFERENCES

March 1994 24

EUROPEAN

PROJECTION

ISSUE DATE

95-01-24
97-05-22

Philips Semiconductors Product specification

V ersatile telephone transmission circuit with
dialler interface

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in

“Data Handbook IC26; Integrated Circuit Packages”

our
(order code 9398 652 90011).

DIP

S

OLDERING BY DIPPING OR BY WAVE

The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

R

EPAIRING SOLDERED JOINTS

Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.

SO

REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO

packages.

stg max

). If the

TEA1065

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

AVE SOLDERING

W
Wave soldering techniques can be used for all SO

packages if the following conditions are observed:

• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

• The longitudinal axis of the package footprint must be
parallel to the solder flow.

• The package footprint must incorporate solder thieves at
the downstream end.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

EPAIRING SOLDERED JOINTS

R
Fix the component by first soldering two diagonally-

opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

March 1994 25

Philips Semiconductors Product specification

Versatile telephone transmission circuit with

TEA1065

dialler interface

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

March 1994 26

Philips Semiconductors Product specification

Versatile telephone transmission circuit with
dialler interface

NOTES

TEA1065

March 1994 27

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Tel. [phone], Fax. [phone]
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Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. [phone], Fax. [phone]

South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone] Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1998 SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 415102/00/02d/pp28 Date of release: March 1994 Document order number: 9397 750 nnnnn