Datasheet TEA0675T, TEA0675 Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TEA0675

Dual Dolby* B-type noise reduction
circuit for playback applications

Preliminary specification
Supersedes data of July 1993
File under Integrated Circuits, IC01

1996 Jun 07

Philips Semiconductors Preliminary specification

Dual Dolby* B-type noise reduction circuit
for playback applications

FEATURES

• Dual noise reduction (NR) channels

• Head pre-amplifiers

• Reverse head switching

• Automatic Music Search (AMS)

• Music scan

• Equalization with electronically switched time constants

• Dolby reference level = 387.5 mV

• 24 pins

• Improved EMC behaviour.

GENERAL DESCRIPTION

The TEA0675 is a bipolar integrated circuit that provides
two channels of Dolby B noise reduction for playback
applications in car radios. It includes head and
equalization amplifiers with electronically switchable time
constants. Furthermore it includes electronically
switchable inputs for tape drivers with reverse heads.

This device also detects pauses of music in the Automatic
Music Search (AMS) scan mode, for applications with an
intelligent controlled tape driver, or AMS-latch mode, for
applications with a simple controlled tape driver. For both
modes, the delay time can be fixed externally by a resistor.
The device operates with power supplies in the range of

7.6 to 12 V, output overload level increasing with increase
in supply voltage.
Current drain varies with the following variables:

Because of this current drain variation it is advisable to use
a regulated power supply or a supply with a long time
constant.

TEA0675

supply voltage
noise reduction on/off
AMS on/off.

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

CC

I

CC

SN+

-------------­N

ORDERING INFORMATION

TYPE

NUMBER

TEA0675 SDIP24
TEA0675T SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

Remark Dolby*: Available only to licensees of Dolby Laboratories Licensing Corporation, San Francisco, CA94111,
USA, from whom licensing and application information must be obtained. Dolby is a registered trade-mark of Dolby
Laboratories Licensing Corporation.

supply voltage 7.6 − 12 V
supply current − 26 31 mA
signal plus noise-to-noise ratio 78 84 − dB

PACKAGE

NAME DESCRIPTION VERSION

plastic shrink dual in-line package; 24 leads (400 mil)

SOT234-1

1996 Jun 07 2

Philips Semiconductors Preliminary specification

Dual Dolby* B-type noise reduction circuit
for playback applications

BLOCK DIAGRAM

pF

470

10

µF

27

kΩ

21

input

headswitch

10 µF

180 Ω

pF

470

PRE

1 kΩ

TEA0675

AMP.

POWER

TEA0675



MED621

pF

470

µF

100

pF

470

PRE

AMP.

SUPPL Y

CC

V

10 µF

180 Ω

1 kΩ

handbook, full pagewidth

AMS

330

output

kΩ

EQ

NR

4.7

15

100

330

70

120

10

nF

nF

nF

nF

nF

kΩ

8.2

µs

18

kΩ

µs

24

kΩ

kΩ

1.5

OFF ON

kΩ

180

270 kΩ

EQ

AMP.

LOGIC

AMS

PROCESSOR

TIME

DELA Y

DOLBY B

24 23 22 21 20 19 18 17 16 15 14 13

RISE TIME

LATCH AND

LEVEL

DETECTOR

EQ

AMP.

DOLBY B

789 1011 12

270 kΩ

12 3 4 5 6

kΩ

8.2

t

R

24

kΩ

kΩ

1.5

kΩ

180

100

330

10

nF

kΩ

330

nF

4.7

(1)

OFFON

AMS

15

nF

nF

nF

Fig.1 Block and application diagram.

for AMS-scan mode.

CC

10 µF

output B

1996 Jun 07 3

10 µF

output A

(1) Switched to V

Philips Semiconductors Preliminary specification

Dual Dolby* B-type noise reduction circuit
for playback applications

PINNING

SYMBOL PIN DESCRIPTION

OUTA 1 output channel A
INTA 2 integrating filter channel A
CONTRA 3 control voltage channel A
HPA 4 high-pass filter channel A
SCA 5 side chain channel A
TD 6 delay time constant
EQA 7 equalizing output channel A
EQFA 8 equalizing input channel A
V

CC

INA1 10 input channel A1 (forward or reverse)
V

ref

INA2 12 input channel A2 (reverse or forward)
INB2 13 input channel B2 (reverse or forward)
HS 14 head switch input
INB1 15 input channel B1 (forward or reverse)
GND 16 ground
EQFB 17 equalizing input channel B
EQB 18 equalizing output channel B
AMSEQ 19 AMS output and EQ switch input
SCB 20 side chain channel B
HPB 21 high-pass filter channel B
CONTRB 22 control voltage channel B
INTB 23 integrating filter channel B
OUTB 24 output channel B

9 supply voltage

11 reference voltage

handbook, halfpage

OUTA

1

INTA

2

CONTRA

HPA
SCA

TD

EQA

EQFA

V

CC

INA1

V

ref

INA2

3
4
5
6
7
8

9
10
11
12

TEA0675

Fig.2 Pin configuration.

MED622

TEA0675

OUTB

24

INTB

23

CONTRB

22

HPB

21

SCB

20
19

AMSEQ
EQB

18
17

EQFB
GND

16

INB1

15

HS

14

INB2

13

1996 Jun 07 4

Philips Semiconductors Preliminary specification

Dual Dolby* B-type noise reduction circuit
for playback applications

FUNCTIONAL DESCRIPTION
Noise Reduction (NR) is enabled when pin HPB is

open-circuit and disabled when connected to GND via an

1.5 kΩ resistor.
Dolby B noise reduction only operates correctly if 0 dB

Dolby level is adjusted at 387.5 mV.
Automatic Music Search (AMS) scan mode is enabled

when pin HPA is connected to VCC via an 1.5 kΩ resistor
and disabled when pin HPA is open-circuit. Switching AMS
on, internally NR is switched OFF simultaneously
(see Figs 5 and 6 for principle timing in AMS-scan mode).

AMS-latch mode is enabled when pin HPA is connected
to GND via an 1.5 kΩ resistor and disabled when pin HPA
is open-circuit. Switching AMS on, NR is switched off
internally. In this mode the device detects a pause level
signal, when a music level signal has appeared first
(see Figs 7 and 8 for principle timing). Furthermore a
longer rise time constant is supplied for suppressing the
detection of plops on tape. The output signal at pin
AMSEQ in this mode may be applied to drive a tape driver
logic circuit.

TEA0675

Equalization time constant switching (70 µs or 120 µs)
is achieved when pin AMSEQ is connected to GND via an
18 kΩ resistor (120 µs), or left open-circuit (70 µs).
This does not affect the AMS output signal during AMS
mode (see Fig.1).

Head switching is achieved when pin HS is connected
(input IN2 active) to GND via a 27 kΩ resistor, or left
open-circuit (input IN1 active). The 10 µF capacitor at pin
HS sets the time constants for smooth switching.

In AMS mode the signals of both channels are rectified and
then added. This means, even if one channel signal
appears inverted to the other channel, the normal AMS
function is ensured. Pins HPB and HPA perform the
function of a logic input for AMS, respectively NR mode
switching in both channels and provide the frequency
dependent feedback of the control chain amplifier in the
corresponding channel. Thus it is important that no voltage
is applied to pins HPB and HPA during NR on/AMS off
mode, otherwise this will cause irregular NR
characteristics.

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CC

V

i

t

short

T

stg

T

amb

V

es

supply voltage 0 14 V
input voltage (except pin 11) −0.3 +V
pin 11 (V

) to VCC short-circuiting duration − 5s

ref

CC

V

storage temperature −55 +150 °C
operating ambient temperature −40 +85 °C
electrostatic handling voltage for all pins note 1 −2+2kV

note 2 −500 +500 V

Notes

1. Human body model (1.5 kΩ, 100 pF).

2. Machine model (0 Ω, 200 pF).

1996 Jun 07 5

Philips Semiconductors Preliminary specification

Dual Dolby* B-type noise reduction circuit

TEA0675

for playback applications

CHARACTERISTICS

VCC= 10 V; f = 20 Hz to 20 kHz; T
pin OUTA or OUTB; see Fig.1; NR on/AMS off; EQ switch in the 70 µs position; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CC

I

CC

α

m

supply voltage 7.6 10 12 V
supply current − 26 31 mA
channel matching f = 1 kHz; Vo= 0 dB; NR off −0.5 − +0.5 dB

THD total harmonic distortion

(2nd and 3rd harmonic)

H

R

SN+

-------------­N

headroom at output VCC= 7.6 V; THD = 1%;

signal plus noise-to-noise
ratio

PSRR power supply ripple

rejection

f

o

frequency response;
referenced to TP

α

cs

α

cc

channel separation Vo= 10 dB; f = 1 kHz;

crosstalk between active
and inactive input

R

L

G

v

load resistance at output AC-coupled; f = 1 kHz;

voltage gain of
pre-amplifier

V

I(offset)(DC)

I

i(bias)

R

EQ

R

i

DC input offset voltage − 2 − mV
input bias current − 0.1 0.4 µA
equalization resistor 4.7 5.8 6.9 kΩ
input resistance head

inputs

A

v

open-loop amplification pin INA1 or

=25°C; all levels are referenced to 387.5 mV (RMS) (0 dB) at test point (TP)

amb

f = 1 kHz; V
f = 10 kHz; V

=0dB − 0.08 0.15 %

o

=10dB − 0.15 0.3 %

o

12 −− dB

f = 1 kHz
internal gain 40 dB, linear;

78 84 − dB
CCIR/ARM weighted;
decode mode; see Fig.25

= 0.25 V; f = 1 kHz;

V

i(rms)

52 57 − dB
see Fig.22

encode mode; see Fig.25

= −25 dB; f = 0.2 kHz −22.9 −24.4 −25.9 dB

V

o

= 0 dB; f = 1 kHz −1.5 0 +1.5 dB

V

o

= −25 dB; f=1kHz −17.8 −19.3 −20.8 dB

V

o

= −25 dB; f=5kHz −18.1 −19.6 −21.1 dB

V

o

= −35 dB; f = 10 kHz −24.4 −25.9 −27.4 dB

V

o

57 63 − dB
see Fig.23

f = 1 kHz; Vo= 10 dB;

70 77 − dB
NR off; see Fig.23

10 −− kΩ
Vo= 12 dB; THD = 1%

from pin INA1 or INA2 to

29 30 31 dB
pin EQFA and from
pin INB1 or
INB2 to pin EQFB;
f = 1 kHz

60 100 − kΩ

INA2 to pin EQA and
pin INB1 or INB2 to
pin EQB

f = 10 kHz 80 86 − dB
f = 400 Hz 104 110 − dB

1996 Jun 07 6

Philips Semiconductors Preliminary specification

Dual Dolby* B-type noise reduction circuit

TEA0675

for playback applications

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

− V

ref

I

O

Z

o

V

no(rms)

V

TD

EMC DC offset voltage at

Switching thresholds

V

NROFF

I

NROFF

I

NRON

V

HPB(max)

HPA (PIN 4)
V

AMSlON

I

AMSlON

V

AMSsON

I

AMSsON

I

AMSOFF

V

HPA(max)

AMSEQ (PIN 19)

DC output offset voltage

OUT

at pins OUTA and OUTB

NR off; pins INA1, INA2,
INB1 and INB2 connected
to V

ref

−0.15 − +0.15 V

DC output current pin OUTA to ground −2 −− mA

pin OUTB to V

CC

0.3 −− mA
output impedance − 80 100 Ω
equivalent input noise

voltage (RMS value)

AMS timing (DC level) resistor Rt connected to

NR off; unweighted;
f = 20 Hz to 20 kHz;
R

source

=0Ω

− 0.7 1.4 µV

VCC− 3 − V

CC

V

pin TD

i(rms)

=6V;

pins OUTA and OUTB

f = 900 MHz; V
see Figs 26, 27 and 28

voltage at HPB (pin 21) NR off 0.19V

− 40 − mV

CC

0.23V

CC

0.25V

CC

V
output current NR off −−0.7 −1mA
input current NR on − open 200 nA
maximum voltage −−0.75V

pin voltage AMS-latch on 0.19V

CC

0.23V

CC

0.25V

CC

CC

V

V
output current −−0.7 −1mA
pin voltage AMS-scan on 0.75V

CC

0.77V

CC

0.81V

CC

V
input current − 0.8 1 mA
pin current AMS off − open 200 nA
maximum voltage −−0.75V

CC

V

AMS output (AMS mode)

V

OH

I

OH1

I

OH2

t

d

HIGH level output voltage 4 4.6 5 V
HIGH level output current note 1 +10 −−150 µA
HIGH level output current note 1 +0.01 −−1mA
minimum pulse width;

see Table 1 − 23 to 160 − ms

delay time range

V

OL

I

OL

t

r

A

M/P

LOW level output voltage − 0.1 0.7 V
LOW level output current −0.02 − +1 mA
minimum pulse width rise

time
signal level at output for

AMS switching

AMS-scan mode 2 6 10 ms
AMS-latch mode 130 150 170 ms
AMS mode; f = 10 kHz;

note 2; see Fig.24

music to pause

1996 Jun 07 7

−25 −22 −19 dB

Philips Semiconductors Preliminary specification

Dual Dolby* B-type noise reduction circuit

TEA0675

for playback applications

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

A

P/M

EQ switch input (not AMS mode)

I

EQ70

I

EQ120

I

EQth

HEAD SWITCHING
V

HSW

I

HSW

V

HSW(HIGH)

V

HSW(LOW)

Notes

1. In AMS off mode, pin AMSEQ is HIGH level, the equalization time constant will be switched by pulling approximately
200 µA out of pin AMSEQ. This means for the device connected to pin AMSEQ, a restriction of input current at HIGH
level less than 200 µA during AMS off; otherwise the selection of the equalization time constant is disabled and fixed
at 120 µs. If the connected devices consume more than 200 µA, this input has to be disconnected in AMS off mode.
(To ensure switching, the currents for the different switched modes are specified with a tolerance of ±50 µA in
Chapter “Characteristics”.) For an application with a fixed EQ time constant of 120 µs the equalizing network may be
applied completely external. Change 8.2 kΩ resistor to 14 kΩ the internal resistor REQ= 5.8 kΩ is short-circuited by
fixing the EQ switch input at the 70 µs position (I

2. The high speed of the tape (FF, REW) at the tape head during AMS mode causes a transformation of level and
frequency of the originally recorded signal. It means a boost of signal level of approximately 10 dB and more for
recorded frequencies from 500 Hz up to 4 kHz. So the threshold level of −22 dB corresponds to signal levels in Play
Back (PB) mode of approximately −32 dB. The AMS inputs for each channel are pin SCA and pin SCB. As the
frequency spectrum is transformed by a factor of approximately 10 to 30 due to the higher tape speed in FF, REW,
the high-pass filter (4.7 nF/24 kΩ) removes the effect of offset voltages but does not affect the music search function.

In the application circuit (Fig.1) the frequency response of the system between tape heads input, e.g. pins INA2 and
INB2, to the AMS input pins SCA and SCB is constant over the whole frequency range (see Fig.3).

3. To activate the inputs IN1, pin HS might be left open-circuit. In this event the DC level at pin HS is 0.775VCC.

signal level at output for

AMS mode; f = 10 kHz; −24 −21 −18 dB
AMS switching
pause to music

input current time constant 70 µs active −150 −− µA
input voltage time constant 120 µs active −1000 −−250 µA
threshold current note 1 −−200 −µA

pin voltage load current +90 to −90 µA − 0.8V
input current V
HIGH level pin voltage inputs INA1 and INB1

HSW

=0toV

CC

−170 − +170 µA

1

⁄2VCC+ 0.5 − V

− V

CC

CC

V

active; note 3
LOW level pin voltage inputs INA2 and INB2

0 −

1

⁄2VCC− 0.5 V

active

).

EQ70

1996 Jun 07 8

Philips Semiconductors Preliminary specification

Dual Dolby* B-type noise reduction circuit
for playback applications

Table 1 Blank delay time set by resistor Rt at pin TD

RESISTOR VALUE R

t

(kΩ)

68 23 20
150 42 15
180 48 15
220 56 15
270 65 10
330 76 10
470 98 10
560 112 10
680 126 10
820 142 10

1000 160 10

General note

It is recommended to switch off V

with a gradient of 400 V/s at maximum to avoid plops on tape in the event of contact

CC

between tape and tape head while switching off.

DELAY TIME t

TYP. (ms)

TEA0675

d

TOLERANCE

(%)

−20

handbook, full pagewidth

(dB)

−30

−40

−50

−60

2

10

(1) AMS threshold level for application circuit (Fig.1).
(2) AMS threshold level for test circuit (Fig.24).

(1)

(2)

3

10

Fig.3 AMS threshold level.

MED623

4

10

(Hz)

5

10

1996 Jun 07 9

Philips Semiconductors Preliminary specification

Dual Dolby* B-type noise reduction circuit
for playback applications

Short description ‘music search’

A system for ‘music search’ mainly consists of a level and
a time detection (see Fig.4). For adapting and decoupling
the input signal will be amplified (A), then rectified (B) and
smoothed with a time constant (C). So the voltage at (C)
corresponds to the signal level and will be compared to the
predefined pause level at the first comparator (D), the level
detector. If the signal level becomes smaller than the
pause level, the level detector changes its output signal.
Due to the output level of the level detector the capacitor
of the second time constant (E) will be charged,

handbook, full pagewidth

INPUT

(A)

(B)

(C)

COMPARATOR 1 COMPARATOR 2

V

I

t

1

TEA0675

respectively discharged. If the pause level of the input
signal remains for a certain time, the voltage at the
capacitor reaches a certain value, which corresponds to
an equivalent time value. The voltage at the capacitor will
be compared to a predefined time-equivalent voltage by
the second comparator (F), the time detector. If the pause
level of the input signal remains for this predefined time,
the time detector changes its output level for ‘pause found’
status.

(D)

(E) (F)

V

t

t

2

OUTPUT

AMPLIFIER RECTIFIER

LEVEL DETECTOR TIME DETECTOR

MED624

Fig.4 Integrated ‘music search’ function.

1996 Jun 07 10

Philips Semiconductors Preliminary specification

Dual Dolby* B-type noise reduction circuit

TEA0675

for playback applications

Description of the principle timing diagram for AMS-scan mode without initial input signal (see Fig.5)

tr: rise time

handbook, full pagewidth

td: delay time
tb: burst time
tp: pause time
tf: fall time

level threshold

upper threshold

(hysteresis)

time threshold

V

V

REF

V

V

in

l

t

AMS on

t

r

t

d

t

f

tb<t

r

tp<t

d

Vl: voltage at
level detector
input
pin 3 (CONTRA)

Vt: voltage at
time detector
input
pin 22 (CONTRB)

t

t

V

AMSEQ

4.5 V

output signal

to microprocessor

t

0

t3t

4t5t6

Fig.5 AMS-scan mode without initial input signal.

By activating AMS-scan mode, the AMS output level
directly indicates whether the input level corresponds to a
pause level (V

= LOW) or not (V

AMSEQ

AMSEQ

= HIGH).
At t0 the AMS-scan mode is activated. Without a signal at
Vin, the following initial procedure runs until the AMS
output changes to LOW level: due to no signal at Vin the
voltage at the level detector input VI (pin 3, CONTRA)
remains below the level threshold and the second time
constant will be discharged (time detector input Vt).
When Vt passes the time threshold level, the time detector
output changes to LOW level. Now the initial procedure is
completed.

If a signal burst appears at t3, the level detector input
voltage rises immediately and causes its output to charge
the second time constant, which supplies the input voltage
Vt for the time detector. When Vt passes the upper

t

t

t

t8t9t

7

10

t11t12t13t

14t15

MED625

threshold level after the rise time tr (at t4), the AMS output
changes to HIGH. If the signal burst ends at t5 the level
detector input VI falls to its LOW level. When passing the
level threshold at t6, the discharging of the second time
constant begins. Now the circuit measures the delay time
td, which is externally fixed by a resistor and defines the
length of a pause to be detected. If no signal appears at V
within the time interval td, the time detector output switches
the AMS output to LOW level at t7.

If a plop noise pulse appears at Vin (t8) with a pulse width
less than the rise time tr>tb, the plop noise will not be
detected as music. The AMS output remains LOW.

Similarly the system handles ‘no music pulses’ tp: when
music appears at t11 with a small interruption at t13, this
interruption will not affect the AMS output for tp<td.

in

1996 Jun 07 11

Philips Semiconductors Preliminary specification

Dual Dolby* B-type noise reduction circuit

TEA0675

for playback applications

Description of the principle timing diagram for AMS-scan mode with initial input signal (see Fig.6)

tr: rise time

handbook, full pagewidth

td: delay time
tb: burst time
tp: pause time
tf: fall time

level threshold

upper threshold

(hysteresis)

time threshold

V

V

REF

V

V

in

l

t

AMS on

t

d

t

f

tb<t

r

tp<t

r

Vl: voltage at
level detector
input
pin 3 (CONTRA)

Vt: voltage at
time detector
input
pin 22 (CONTRB)

t

t

V

AMSEQ

4.5 V

output signal

to microprocessor

t0t

t5t

1

t

6

7

t8t9t

10

Fig.6 AMS-scan mode with initial input signal.

At t0 the AMS-scan mode is activated. With an input signal
at Vin, the following initial procedure runs until the circuit
gets a steady state status.

Due to the signal at Vin the voltage at the level detector
input VI (pin 3, CONTRA) slides to a value which is defined
by a limiter. This voltage causes the level detector output
charging the second time constant (time detector input Vt)

t

t

t11t12t13t

t

15

14

MED626

to its maximum voltage level at t1. Now the initial
procedure is completed.

The following behaviour does not differ from the
description in Section “Description of the principle timing
diagram for AMS-scan mode without initial input signal
(see Fig.5)”.

1996 Jun 07 12

Philips Semiconductors Preliminary specification

Dual Dolby* B-type noise reduction circuit

TEA0675

for playback applications

Description of the principle timing diagram for AMS-latch mode without initial input signal (see Fig.7)

tr: rise time

handbook, full pagewidth

td: delay time
tb: burst time
tp: pause time
tf: fall time

level threshold

upper threshold

(hysteresis)

time threshold

V

V

REF

in

V

V

l

t

AMS on

t

r

t

d

t

f

tb<t

r

tp<t

d

Vl: voltage at
level detector
input
pin 3 (CONTRA)

Vt: voltage at
time detector
input
pin 22 (CONTRB)

t

t



H

internal

latch status

output signal

to power FET

V

AMSEQ

4.5 V

L

t

0

t3t

4t5t6

t

Fig.7 AMS-latch mode without initial input signal.

This is similar to the description of the principle timing
diagram from AMS-scan mode. It only differs in its initial
behaviour and its rise time tr. (Please notice that the
different tr does not occur in the principle timing diagrams
for latch and scan mode).

Running in AMS-latch mode, the circuit may be simply
applied to drive a stop solenoid via a power FET. So the
AMS output signal has not to be processed by a controller.
Because there is no processor to make a decision whether
there is a plop noise or not, for this mode the rise time tr is
extended to approximately 150 ms.

By activating AMS-latch mode the AMS output will not
change to LOW level at t2 if there is no initial signal at Vin.

t

t

t

t8t9t

7

10

t11t12t13t

14t15

MED627

A latch forces the AMS output to be HIGH until a signal
appears at Vin (t4). After t4 the latch will not affect the
output any more until AMS-latch mode is started again.
The existence of the latch appears necessary if the AMS
output for example drives a stop solenoid via a power FET.
The LOW output level will cause a drive of the stop
solenoid. This would happen after a maximum time of t
occurred without any input signal. If there is no music on
tape for a long time (e.g. at tape end), the AMS mode
would be activated repeatedly as long as there is no signal
at Vin. Thus the circuit waits until first music appears before
detecting the pauses.

d

1996 Jun 07 13

Philips Semiconductors Preliminary specification

Dual Dolby* B-type noise reduction circuit

TEA0675

for playback applications

Description of the principle timing diagram for AMS-latch mode with initial input signal (see Fig.8)

tr: rise time

handbook, full pagewidth

td: delay time
tb: burst time
tp: pause time
tf: fall time

level threshold

upper threshold

(hysteresis)

V

V

REF

V

V

in

l

t

AMS on

t

d

t

f

tb<t

r

tp<t

d

Vl: voltage at
level detector
input
pin 3 (CONTRA)

Vt: voltage at
time detector
input
pin 22 (CONTRB)

t

t

time threshold

H

internal

latch status

output signal

to power FET

V

AMSEQ

4.5 V

L

t0t

t5t

1

t

6

7

t8t9t

10

Fig.8 AMS-latch mode with initial input signal.

This is similar to the description in Section “Description of
the principle timing diagram for AMS-scan mode with initial
input signal (see Fig.6)”. It only differs in its rise time tr and
a release of its internal latch when voltage Vt passes the
upper threshold between t0 and t1. Now the initial
procedure is completed.

t

t

t

t11t12t13t

t

15

14

MED628

The following behaviour does not differ from the
description in Section “Description of the principle timing
diagram for AMS-latch mode without initial input signal
(see Fig.7)”.

1996 Jun 07 14

Philips Semiconductors Preliminary specification

Dual Dolby* B-type noise reduction circuit
for playback applications

INTERNAL PIN CONFIGURATIONS

handbook, halfpage

+

65 Ω

1

5 V

65 Ω

MBH506

handbook, halfpage

TEA0675

2

V

±0.23 V

+

ref

Fig.9 Pins 1 and 24: output channel.

handbook, halfpage

MBH507


Fig.10 Pins 2 and 23: integrating filter.

3.4 kΩ1.2 kΩ

3.6 kΩ

3

5 V

+

handbook, halfpage

+

4

5 V

675 Ω

10 kΩ

+

MBH509


+

MBH508


Fig.11 Pins 3 and 22: control voltage. Fig.12 Pins 4 and 21: high-pass filter.

1996 Jun 07 15

Philips Semiconductors Preliminary specification

Dual Dolby* B-type noise reduction circuit
for playback applications

handbook, halfpage

+

5

5 V

MBD510


handbook, halfpage

TEA0675

6

+

8 V

1 KΩ

MBH511

handbook, halfpage

Fig.13 Pins 5 and 20: side chain.

5.8 kΩ

7

5 V

MBH512


+

100 Ω

handbook, halfpage

Fig.14 Pin 6: delay time constant.

+

8

5 V

10 kΩ

1 pF

MBH513

Fig.15 Pins 7 and 18: equalizing output.

1996 Jun 07 16

Fig.16 Pins 8 and 17: equalizing input.

Philips Semiconductors Preliminary specification

Dual Dolby* B-type noise reduction circuit
for playback applications

handbook, halfpage

9

10 V

MBH514

handbook, halfpage

TEA0675

10

5 V

+

220 Ω

100 kΩ

5 V

12 pF

MBH515

handbook, halfpage

Fig.17 Pin 9: supply voltage.

+

2.5 kΩ

5 V

11

2.5 kΩ

MBH516

Fig.18 Pins 10, 12, 13 and 15: input channel.

handbook, halfpage

14

8 V

+

MBH517

Fig.19 Pin 11: reference voltage.

1996 Jun 07 17

Fig.20 Pin 14: head switch input.

Philips Semiconductors Preliminary specification

Dual Dolby* B-type noise reduction circuit
for playback applications

handbook, halfpage

+

19

4.6 V

MBH518

TEA0675

Fig.21 Pin 19: AMS output and EQ switch input.

1996 Jun 07 18

Philips Semiconductors Preliminary specification

Dual Dolby* B-type noise reduction circuit
for playback applications

TEST AND APPLICATION INFORMATION

10

µF

27

kΩ

TEA0675

PRE

AMP.

POWER

SUPPL Y

PRE

TEA0675



MED629

µF

100

AMP.

= 10 V

CC

V

1000

µF

10 kΩ

1 kHz

100

nF

0.25 V RMS

dbook, full pagewidth

AMS

output

10

EQ

NR

4.7

15

100

330

10

µF

10

kΩ

EQ

70 µs

nF

nF

nF

nF

OFF ON

18

24

1.5

180

AMP.

20 kΩ

kΩ

kΩ

kΩ

kΩ

DOLBY B

270 kΩ

24 23 22 21 20 19 18 17 16 15 14 13

AMS

PROCESSOR

RISE TIME

LATCH AND

LOGIC

DELA Y

LEVEL

TIME

DETECTOR

EQ

AMP.

DOLBY B

789 1011 12

56

12 3 4

20 kΩ

R

24

1.5

15

180

270 kΩ

10

t

kΩ

kΩ

nF

kΩ

100

330

kΩ

ON OFF

nF

nF

4.7

(1)

nF

µF

Fig.22 Test circuit for power supply ripple rejection.

for AMS-scan mode.

CC

10 µF

output B

1996 Jun 07 19

10 µF

output A

(1) Switched to V

Philips Semiconductors Preliminary specification

Dual Dolby* B-type noise reduction circuit
for playback applications

10

µF

27

kΩ

TEA0675

PRE

AMP.

POWER

SUPPL Y

PRE

TEA0675



MED630

µF

100

Ω

200

10

µF

AMP.

100

10 V

nF

handbook, full pagewidth

AMS

output

10

nF

nF

nF

µF

kΩ

nF

4.7

Fig.23 Test circuit for channel separation.

10

NR

µF

EQ

4.7

15

100

330

70 µs

nF

nF

nF

nF

ONOFF

10

18

24

1.5

180

kΩ

EQ

AMP.

20 kΩ

kΩ

kΩ

kΩ

kΩ

DOLBY B

270 kΩ

24 23 22 21 20 19 18 17 16 15 14 13

AMS

PROCESSOR

RISE TIME

LATCH AND

LOGIC

DELA Y

LEVEL

TIME

DETECTOR

EQ

AMP.

DOLBY B

789 1011 12

12 3 4 5 6

20 kΩ

270 kΩ

t

R

24

kΩ

kΩ

180

10

15

100

330

10 µF

output B

1996 Jun 07 20

10 µF

output A

Philips Semiconductors Preliminary specification

Dual Dolby* B-type noise reduction circuit
for playback applications

input

voltage

10

µF

27

kΩ

TEA0675

PRE

AMP.

POWER

SUPPL Y

PRE

TEA0675



MED631

µF

100

11 12

AMP.

10 V

100

nF

andbook, full pagewidth

AMS

output

10

µF

10

kΩ

270 kΩ

20 kΩ

t

R

24

kΩ

kΩ

1.5

15

kΩ

180

100

330

10

kΩ

10

µF

nF

4.7

Fig.24 Test circuit for AMS threshold level.

(1)

nF

nF

nF

for AMS-scan mode.

CC

EQ

4.7

15

100

330

70 µs

nF

nF

nF

nF

18

24

1.5

180

EQ

AMP.

20 kΩ

kΩ

kΩ

kΩ

kΩ

DOLBY B

270 kΩ

24 23 22 21 20 19 18 17 16 15 14 13

AMS

PROCESSOR

RISE TIME

LATCH AND

LOGIC

DELA Y

LEVEL

TIME

DETECTOR

EQ

AMP.

DOLBY B

789 10

12 3 4 5 6

10 µF

output B

1996 Jun 07 21

10 µF

output A

(1) Switched to V

Philips Semiconductors Preliminary specification

Dual Dolby* B-type noise reduction circuit
for playback applications

10

µF

TEA0675

AMP.

POWER

SUPPL Y

V

CC

27

kΩ

i

V

10 µF

25 kΩ

−

25 kΩ

+

15 14 13

PRE

PRE

TEA0675



MED632

µF

100

Ω

10 11 12

AMP.

200

pF

470

10

µF

CC

V

i

V

10 V

nF

100

dbook, full pagewidth

AMS

output

EQ

TP

NR

15

100

330

10

70 µs

nF

nF

nF

µF

ON

OFF

10

18

4.7

24

1.5

180

kΩ

EQ

AMP.

20 kΩ

kΩ

nF

kΩ

kΩ

kΩ

DOLBY B

270 kΩ

24 23 22 21 20 19 18 17 16

AMS

PROCESSOR

RISE TIME

LATCH AND

LOGIC

DELA Y

LEVEL

TIME

DETECTOR

EQ

AMP.

DOLBY B

789

12 3 4 5 6

20 kΩ

24

AMS OFF

180

270 kΩ

10

t

R

kΩ

4.7

15

kΩ

100

330

nF

nF

nF

nF

kΩ

10

µF

TP

Fig.25 Test circuit for frequency response (channel B).

10 µF

Encode mode

output B

1996 Jun 07 22

10 µF

output A

Decode mode: pre-amplifier 30 dB and EQ amplifier 10dB linear.

Philips Semiconductors Preliminary specification

Dual Dolby* B-type noise reduction circuit
for playback applications

470

pF

Ω

200

10 µF

27

kΩ

input

haed-switch

200

470

pF

Ω

PRE

TEA0675

AMP.

POWER

SUPPL Y

PRE

TEA0675

pF

470

Ω

200

µF

100

Ω

200

pF

= 10 V

CC

V

470

100

nF

AMP.

10 Ω

40 Ω



MBH497

10

10

µF

10

kΩ

EQ

AMP.

20 kΩ

24 kΩ

4.7 nF
15

nF

kΩ

180

100

330

nF

nF

270 kΩ

DOLBY B

24 23 22 21 20 19 18 17 16 15 14 13

AMS

PROCESSOR

RISE TIME

LATCH AND

LOGIC

DELA Y

LEVEL

TIME

DETECTOR

EQ

AMP.

DOLBY B

789 1011 12

12 3 4 5 6

20 kΩ

t

R

270 kΩ

15

180

100

330

10

nF

kΩ

nF

nF

kΩ

4.7 nF

µF

handbook, full pagewidth

24 kΩ

Fig.26 EMC test circuit.

10 µF

output B

1996 Jun 07 23

10 µF

output A

Decode mode: pre-amplifier 30 dB and EQ amplifier 10dB linear.

Philips Semiconductors Preliminary specification

Dual Dolby* B-type noise reduction circuit
for playback applications

LAYOUT OF PRINTED-CIRCUIT BOARD FOR EMC TEST CIRCUIT (FOR TEA0675T)

handbook, full pagewidth

52

63

TEA0675

Dimensions in mm.

10 kΩ

R

t

20 kΩ
10 kΩ

20 kΩ
24 kΩ
15 nF
100 nF

180 kΩ

270 kΩ

4.7 nF

4.7 nF

270 kΩ

180 kΩ

100 nF
15 nF
24 kΩ

40 Ω

470 pF

200 Ω
200 Ω

470 pF

0 Ω
0 Ω

10 Ω

0 Ω
0 Ω

470 pF

200 Ω
200 Ω

470 pF

27 kΩ

100 nF

TEA0675T

Fig.27 Top side with components.

100 nF

MBH460


1996 Jun 07 24

Philips Semiconductors Preliminary specification

Dual Dolby* B-type noise reduction circuit
for playback applications

k, full pagewidth

63

52

TEA0675

Dimensions in mm.

10 µF

X3

MP

S1

100 µF

HFDR.

10 µF

330 nF

330 nF

10 µF

10 µF

100 µF

10 µF

Fig.28 Bottom side with components.

MP

MP

X4

X1

X2

MBH459


1996 Jun 07 25

Philips Semiconductors Preliminary specification

Dual Dolby* B-type noise reduction circuit
for playback applications

PACKAGE OUTLINES

SDIP24: plastic shrink dual in-line package; 24 leads (400 mil)

D

seating plane

L

Z

24

e

b

b

1

13

TEA0675

SOT234-1

M

E

A

2

A

A

1

w M

c

(e )

M

1

H

pin 1 index

1

0 5 10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

A

A

UNIT b

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

mm

OUTLINE
VERSION

SOT234-1

max.

4.7 0.51 3.8

12

min.

max.

IEC JEDEC EIAJ

1.3

0.8

b

1

0.53

0.40

REFERENCES

0.32

0.23

cEe M

(1) (1)

D

22.3

21.4

9.1

8.7

E

12

(1)

L

3.2

2.8

EUROPEAN

PROJECTION

M

10.7

10.2

E

12.2

10.5

e

1

w

H

0.181.778 10.16

ISSUE DATE

92-11-17
95-02-04

Z

max.

1.6

1996 Jun 07 26

Philips Semiconductors Preliminary specification

Dual Dolby* B-type noise reduction circuit
for playback applications

SO24: plastic small outline package; 24 leads; body width 7.5 mm

D

c

y

Z

24

13

TEA0675

SOT137-1

E

H

E

A

X

v M

A

pin 1 index

1

e

0 5 10 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

mm

A

max.

2.65

0.10

A

1

0.30

0.10

0.012

0.004

A2A

2.45

2.25

0.096

0.089

0.25

0.01

b

3

p

0.49

0.32

0.36

0.23

0.019

0.013

0.014

0.009

UNIT

inches

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

(1)E(1) (1)

cD

15.6

15.2

0.61

0.60

12

w M

b

p

scale

eHELLpQ

7.6

1.27

7.4

0.30

0.050

0.29

10.65

10.00

0.42

0.39

A

1.4

0.055

Q

2

A

1

detail X

1.1

1.1

0.4

0.043

0.016

1.0

0.043

0.039

0.25

0.01

L

p

L

(A )

0.25 0.1

0.01

A

3

θ

ywv θ

Z

0.9

0.4

0.035

0.004

0.016

o

8

o

0

OUTLINE

VERSION

SOT137-1

IEC JEDEC EIAJ

075E05 MS-013AD

REFERENCES

1996 Jun 07 27

EUROPEAN

PROJECTION

ISSUE DATE

92-11-17

95-01-24

Philips Semiconductors Preliminary specification

Dual Dolby* B-type noise reduction circuit
for playback applications

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in

“IC Package Databook”

our

SDIP

OLDERING BY DIPPING OR BY WA VE

S
The maximum permissible temperature of the solder is

260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

R

EPAIRING SOLDERED JOINTS

Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.

SO

REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO

packages.

(order code 9398 652 90011).

). If the

stg max

TEA0675

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

AVE SOLDERING

W
Wave soldering techniques can be used for all SO

packages if the following conditions are observed:

• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

• The longitudinal axis of the package footprint must be
parallel to the solder flow.

• The package footprint must incorporate solder thieves at
the downstream end.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

EPAIRING SOLDERED JOINTS

R
Fix the component by first soldering two diagonally-

opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

1996 Jun 07 28

Philips Semiconductors Preliminary specification

Dual Dolby* B-type noise reduction circuit

TEA0675

for playback applications

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1996 Jun 07 29

Philips Semiconductors Preliminary specification

Dual Dolby* B-type noise reduction circuit
for playback applications

NOTES

TEA0675

1996 Jun 07 30

Philips Semiconductors Preliminary specification

Dual Dolby* B-type noise reduction circuit
for playback applications

NOTES

TEA0675

1996 Jun 07 31

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15thfloor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone], Fax. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. [phone], Fax. [phone]
Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]
France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,

Tel. [phone], Fax. [phone]
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. [phone], Fax. [phone]
Greece: No. 15, 25th March Street, GR 17778 TAVROS,

Tel. [phone], Fax. [phone]

Hungary: see Austria
India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.

Worli, MUMBAI 400 018, Tel. [phone], Fax. [phone]

Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. [phone], Fax. [phone]
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180,

Tel. [phone], Fax. [phone]
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,

20124 MILANO, Tel. [phone], Fax. [phone]
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Tel. [phone], Fax. [phone]
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Tel. [phone], Fax. [phone]
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. [phone], Fax. [phone]
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. [phone], Fax. [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. [phone], Fax. [phone]

South America: Rua do Rocio 220 - 5th floor, Suite 51,
CEP: 04552-903-SÃO PAULO-SP, Brazil, P.O. Box 7383 (01064-970),
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone], Fax. [phone]

Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66,
Chung Hsiao West Road, Sec. 1, P.O. Box 22978,
TAIPEI 100, Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 2A Akademika Koroleva str., Office 165,
252148 KIEV, Tel. [phone]/1642, Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1996 SCA49
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Printed in The Netherlands 517021/50/04/pp32 Date of release: 1996 Jun 07 Document order number: 9397 750 00898

Internet: http://www.semiconductors.philips.com/ps/
(1) ADDRESS CONTENT SOURCE August 6, 1996