Datasheet TEA1062T-C4, TEA1062T-C3, TEA1062A-C4-M1, TEA1062A-C4, TEA1062A-C3 Datasheet (Philips)

DATA SH EET

Product specification
Supersedes data of 1996 Dec 04
File under Integrated Circuits, IC03

1997 Sep 03

INTEGRATED CIRCUITS

TEA1062; TEA1062A

Low voltage transmission circuits
with dialler interface

1997 Sep 03 2

Philips Semiconductors Product specification

Low voltage transmission circuits with
dialler interface

TEA1062; TEA1062A

FEATURES

• Low DC line voltage; operates down to 1.6 V (excluding
polarity guard)

• Voltage regulator with adjustable static resistance

• Provides a supply for external circuits

• Symmetrical high-impedance inputs (64 kΩ) for

dynamic, magnetic or piezoelectric microphones

• Asymmetrical high-impedance input (32 kΩ) for electret
microphones

• DTMF signal input with confidence tone

• Mute input for pulse or DTMF dialling

– TEA1062: active HIGH (MUTE)
– TEA1062A: active LOW (

MUTE)

• Receiving amplifier for dynamic, magnetic or
piezoelectric earpieces

• Large gain setting ranges on microphone and earpiece
amplifiers

• Line loss compensation (line current dependent) for
microphone and earpiece amplifiers

• Gain control curve adaptable to exchange supply

• DC line voltage adjustment facility.

GENERAL DESCRIPTION

The TEA1062 and TEA1062A are integrated circuits that
perform all speech and line interface functions required in
fully electronic telephone sets. They perform electronic
switching between dialling and speech. The ICs operate at
line voltage down to 1.6 V DC (with reduced performance)
to facilitate the use of more telephone sets connected in
parallel.

All statements and values refer to all versions unless
otherwise specified.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

LN

line voltage I

line

= 15 mA 3.55 4.0 4.25 V

I

line

operating line current

normal operation 11 − 140 mA
with reduced performance 1 − 11 mA

I

CC

internal supply current VCC= 2.8 V − 0.9 1.35 mA

V

CC

supply voltage for peripherals I

line

=15mA

TEA1062 I

p

= 1.2 mA; MUTE = HIGH 2.2 2.7 − V

I

p

= 0 mA; MUTE = HIGH − 3.4 − V

TEA1062A I

p

= 1.2 mA; MUTE = LOW 2.2 2.7 − V

I

p

= 0 mA; MUTE = LOW − 3.4 − V

G

v

voltage gain

microphone amplifier 44 − 52 dB
receiving amplifier 20 − 31 dB

T

amb

operating ambient temperature −25 − +75 °C

Line loss compensation

∆G

v

gain control − 5.8 − dB

V

exch

exchange supply voltage 36 − 60 V

R

exch

exchange feeding bridge resistance 0.4 − 1kΩ

1997 Sep 03 3

Philips Semiconductors Product specification

Low voltage transmission circuits with
dialler interface

TEA1062; TEA1062A

ORDERING INFORMATION

BLOCK DIAGRAM

TYPE NUMBER

PACKAGE

NAME DESCRIPTION VERSION

TEA1062 DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-1
TEA1062M1 DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 or

SOT38-9
TEA1062A DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-1
TEA1062AM1 DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 or

SOT38-9
TEA1062T SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
TEA1062A T SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Fig.1 Block diagram for TEA1062A.

(1) Pin 12 is active HIGH (MUTE) for TEA1062.

handbook, full pagewidth

MBA359 - 1

SLPESTABAGCREGV

EE

GAS2

GAS1

V

CC

LN

IR

MIC
MIC

DTMF

MUTE

TEA1062A

GAR

QR

SUPPLY AND

REFERENCE

dB

CURRENT

REFERENCE

CONTROL
CURRENT

LOW VOLTAGE

CIRCUIT

10

7
6

11

12

91415 8 16

3

2

4

5

1

13

(1)

1997 Sep 03 4

Philips Semiconductors Product specification

Low voltage transmission circuits with
dialler interface

TEA1062; TEA1062A

PINNING

Note

1. Pin 12 is active HIGH (MUTE) for TEA1062.

SYMBOL PIN DESCRIPTION

LN 1 positive line terminal
GAS1 2 gain adjustment; transmitting

amplifier

GAS2 3 gain adjustment; transmitting

amplifier

QR 4 non-inverting output; receiving

amplifier

GAR 5 gain adjustment; receiving

amplifier
MIC− 6 inverting microphone input
MIC+ 7 non-inverting microphone input
STAB 8 current stabilizer
V

EE

9 negative line terminal
IR 10 receiving amplifier input
DTMF 11 dual-tone multi-frequency input
MUTE 12 mute input (see note 1)
V

CC

13 positive supply decoupling
REG 14 voltage regulator decoupling
AGC 15 automatic gain control input
SLPE 16 slope (DC resistance) adjustment

Fig.2 Pin configuration for TEA1062A.

handbook, halfpage

MBA354 - 1

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

TEA1062A

LN

GAS1

GAS2

QR

GAR

STAB

SLPE

AGC

REG
V

CC
MUTE
DTMF

IR
V

EE

MIC

MIC

1997 Sep 03 5

Philips Semiconductors Product specification

Low voltage transmission circuits with
dialler interface

TEA1062; TEA1062A

FUNCTIONAL DESCRIPTION
Supplies V

CC

, LN, SLPE, REG and STAB

Power for the IC and its peripheral circuits is usually
obtained from the telephone line. The supply voltage is
derived from the line via a dropping resistor and regulated
by the IC. The supply voltage V

CC

may also be used to

supply external circuits e.g. dialling and control circuits.
Decoupling of the supply voltage is performed by a

capacitor between VCC and VEE. The internal voltage
regulator is decoupled by a capacitor between REG and
VEE.

The DC current flowing into the set is determined by the
exchange supply voltage V

exch

, the feeding bridge

resistance R

exch

and the DC resistance of the telephone

line R

line

.

The circuit has an internal current stabilizer operating at a
level determined by a 3.6 kΩ resistor connected between
STAB and VEE (see Fig.9). When the line current (I

line

) is
more than 0.5 mA greater than the sum of the IC supply
current (ICC) and the current drawn by the peripheral
circuitry connected to VCC (Ip) the excess current is
shunted to VEE via LN.

The regulated voltage on the line terminal (VLN) can be
calculated as:

VLN=V

ref+ISLPE

× R9

VLN=V

ref

+ {(I

line

− ICC− 0.5 × 10−3A) − Ip} × R9

V

ref

is an internally generated temperature compensated
reference voltage of 3.7 V and R9 is an external resistor
connected between SLPE and VEE.

In normal use the value of R9 would be 20 Ω.
Changing the value of R9 will also affect microphone gain,

DTMF gain, gain control characteristics, sidetone level,
maximum output swing on LN and the DC characteristics
(especially at the lower voltages).

Under normal conditions, when I

SLPE

>> ICC + 0.5 mA + Ip,
the static behaviour of the circuit is that of a 3.7 V regulator
diode with an internal resistance equal to that of R9. In the
audio frequency range the dynamic impedance is largely
determined by R1. Fig.3 shows the equivalent impedance
of the circuit.

At line currents below 9 mA the internal reference voltage
is automatically adjusted to a lower value (typically 1.6 V
at 1 mA). This means that more sets can be operated in
parallel with DC line voltages (excluding the polarity guard)
down to an absolute minimum voltage of 1.6 V. At line
currents below 9 mA the circuit has limited sending and
receiving levels. The internal reference voltage can be
adjusted by means of an external resistor (R

VA

).
This resistor when connected between LN and REG will
decrease the internal reference voltage and when
connected between REG and SLPE will increase the
internal reference voltage.

Current (Ip) available from VCC for peripheral circuits
depends on the external components used. Fig.10 shows
this current for VCC> 2.2 V. If MUTE is LOW (TEA1062) or
MUTE is HIGH (TEA1062A) when the receiving amplifier
is driven, the available current is further reduced. Current
availability can be increased by connecting the supply IC
(TEA1081) in parallel with R1 as shown in Fig.19 and
Fig.20, or by increasing the DC line voltage by means of
an external resistor (RVA) connected between REG and
SLPE (Fig.18).

Fig.3 Equivalent impedance circuit.

Leq=C3×R9 × Rp.
Rp= 16.2 kΩ.

handbook, halfpage

REG

V

EE

V

CC

LN

MBA454

L

eq

R

p

R1

V

ref

R9
20 Ω

C3

4.7 µF C1100 µF

1997 Sep 03 6

Philips Semiconductors Product specification

Low voltage transmission circuits with
dialler interface

TEA1062; TEA1062A

Microphone inputs MIC+ and MIC− and gain pins
GAS1 and GAS2

The circuit has symmetrical microphone inputs. Its input
impedance is 64 kΩ (2 × 32 kΩ) and its voltage gain is
typically 52 dB (when R7 = 68 kΩ, see Figures 14
and 15). Dynamic, magnetic, piezoelectric or electret (with
built-in FET source followers) can be used. Microphone
arrangements are illustrated in Fig.11.

The gain of the microphone amplifier can be adjusted
between 44 dB and 52 dB to suit the sensitivity of the
transducer in use. The gain is proportional to the value of
R7 which is connected between GAS1 and GAS2.

Stability is ensured by two external capacitors, C6
connected between GAS1 and SLPE and C8 connected
between GAS1 and V

EE

. The value of C6 is 100 pF but this
may be increased to obtain a first-order low-pass filter.
The value of C8 is 10 times the value of C6. The cut-off
frequency corresponds to the time constant R7 × C6.

Input MUTE (TEA1062)

When MUTE is HIGH the DTMF input is enabled and the
microphone and receiving amplifier inputs are inhibited.
The reverse is true when MUTE is LOW or open-circuit.
MUTE switching causes only negligible clicking on the line
and earpiece output. If the number of parallel sets in use
causes a drop in line current to below 6 mA the speech
amplifiers remain active independent to the DC level
applied to the MUTE input.

Input MUTE (TEA1062A)

When MUTE is LOW or open-circuit, the DTMF input is
enabled and the microphone and receiving amplifier inputs
are inhibited. The reverse is true when MUTE is HIGH.
MUTE switching causes only negligible clicking on the line
and earpiece output. If the number of parallel sets in use
causes a drop in line current to below 6 mA the DTMF
amplifier becomes active independent to the DC level
applied to the MUTE input.

Dual-tone multi-frequency input DTMF

When the DTMF input is enabled dialling tones may be
sent on to the line. The voltage gain from DTMF to LN is
typically 25.5 dB (when R7 = 68 kΩ) and varies with R7 in
the same way as the microphone gain. The signalling
tones can be heard in the earpiece at a low level
(confidence tone).

Receiving amplifier IR, QR and GAR

The receiving amplifier has one input (IR) and a
non-inverting output (QR). Earpiece arrangements are
illustrated in Fig.12. The IR to QR gain is typically 31 dB
(when R4 = 100 kΩ). It can be adjusted between
20 and 31 dB to match the sensitivity of the transducer in
use. The gain is set with the value of R4 which is
connected between GAR and QR. The overall receive
gain, between LN and QR, is calculated by subtracting the
anti-sidetone network attenuation (32 dB) from the
amplifier gain. Two external capacitors, C4 and C7, ensure
stability. C4 is normally 100 pF and C7 is 10 times the
value of C4. The value of C4 may be increased to obtain a
first-order low-pass filter. The cut-off frequency will depend
on the time constant R4 × C4.

The output voltage of the receiving amplifier is specified for
continuous-wave drive. The maximum output voltage will
be higher under speech conditions where the peak to RMS
ratio is higher.

Automatic Gain Control input AGC

Automatic line loss compensation is achieved by
connecting a resistor (R6) between AGC and V

EE

.

The automatic gain control varies the gain of the
microphone amplifier and the receiving amplifier in
accordance with the DC line current. The control range is

5.8 dB which corresponds to a line length of 5 km for a

0.5 mm diameter twisted-pair copper cable with a DC
resistance of 176 Ω/km and average attenuation of

1.2 dB/km). Resistor R6 should be chosen in accordance
with the exchange supply voltage and its feeding bridge
resistance (see Fig.13 and Table 1). The ratio of start and
stop currents of the AGC curve is independent of the value
of R6. If no automatic line-loss compensation is required
the AGC pin may be left open-circuit. The amplifiers, in this
condition, will give their maximum specified gain.

1997 Sep 03 7

Philips Semiconductors Product specification

Low voltage transmission circuits with
dialler interface

TEA1062; TEA1062A

Sidetone suppression

The anti-sidetone network, R1//Z

line

, R2, R3, R8, R9 and

Z

bal

, (see Fig.4) suppresses the transmitted signal in the
earpiece. Maximum compensation is obtained when the
following conditions are fulfilled:

(1)

(2)

If fixed values are chosen for R1, R2, R3 and R9, then
condition (1) will always be fulfilled when |R8//Z

bal

| << R3.

To obtain optimum sidetone suppression, condition (2) has
to be fulfilled which results in:

Where k is a scale factor;

The scale factor k, dependent on the value of R8, is
chosen to meet the following criteria:

• compatibility with a standard capacitor from the E6 or

E12 range for Z

bal

•Z

bal

//R8 << R3 fulfilling condition (a) and thus

ensuring correct anti-sidetone bridge operation

•Z

bal

+ R8 >> R9 to avoid influencing the transmit gain.

In practise Z

line

varies considerably with the line type and

length. The value chosen for Z

bal

should therefore be for
an average line length thus giving optimum setting for
short or long lines.

R9 R2× R1 R3

R8 Z

bal

×

R8 Z

bal

+

------------------------ -

+







×=

Z

bal

Z

bal

R8+

------------------------ -

Z

line

Z

line

R1+

--------------------------

=

Z

bal

R8
R1

------- -

Z

line

kZ

line

×=×=

k

R8
R1

------- -

=

E

XAMPLE

The balance impedance Z

bal

at which the optimum

suppression is present can be calculated by:
Suppose Z

line

= 210 Ω + (1265 Ω//140 nF) representing a
5 km line of 0.5 mm diameter, copper, twisted-pair cable
matched to 600 Ω (176 Ω/km; 38 nF/km).

When k = 0.64 then R8 = 390 Ω;
Z

bal

= 130 Ω + (820 Ω//220 nF).

The anti-sidetone network for the TEA1060 family shown
in Fig.4 attenuates the signal received from the line by
32 dB before it enters the receiving amplifier.
The attenuation is almost constant over the whole
audio-frequency range.

Figure 5 shows a conventional Wheatstone bridge
anti-sidetone circuit that can be used as an alternative.
Both bridge types can be used with either resistive or
complex set impedances. (More information on the
balancing of anti-sidetone bridges can be obtained in our
publication

“Applications Handbook for Wired telecom

systems, IC03b”

, order number 9397 750 00811.)

1997 Sep 03 8

Philips Semiconductors Product specification

Low voltage transmission circuits with
dialler interface

TEA1062; TEA1062A

Fig.4 Equivalent circuit of TEA1060 family anti-sidetone bridge.

handbook, full pagewidth

MSA500 - 1

IR

R3

R8

SLPE

R9

Z

line

V

EE

Z

bal

i

m

R

t

R1 R2

LN

Fig.5 Equivalent circuit of an anti-sidetone network in a Wheatstone bridge configuration.

ok, full pagewidth

MSA501 - 1

IR

R8

SLPE

R9

R1

LN

Z

line

V

EE

Z

bal

R

A

i

m

R

t

1997 Sep 03 9

Philips Semiconductors Product specification

Low voltage transmission circuits with
dialler interface

TEA1062; TEA1062A

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Notes

1. Mostly dependent on the maximum required T

amb

and on the voltage between LN and SLPE (see Figs 6, 7 and 8).

2. Calculated for the maximum ambient temperature specified (T

amb

=75°C) and a maximum junction temperature of

125 °C.

HANDLING

This device meets class 2 ESD test requirements [Human Body Model (HBM)], in accordance with

“MIL STD 883C - method 3015”

.

THERMAL CHARACTERISTICS

Note

1. Mounted on glass epoxy board 28.5 × 19.1 × 1.5 mm.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

LN

positive continuous line voltage − 12 V

V

LN(R)

repetitive line voltage during switch-on
or line interruption

− 13.2 V

V

LN(RM)

repetitive peak line voltage for a 1 ms
pulse per 5 s

R9 = 20 Ω; R10 = 13 Ω;
see Fig.18

− 28 V

I

line

line current R9 = 20 Ω; note 1 − 140 mA

V

I

input voltage on all other pins positive input voltage − VCC+ 0.7 V

negative input voltage −−0.7 V

P

tot

total power dissipation R9 = 20 Ω; note 2

TEA1062; TEA1062A − 666 mW
TEA1062M1; TEA1062AM1 − 617 mW
TEA1062T; TEA1062AT − 454 mW

T

amb

operating ambient temperature −25 +75 °C

T

stg

storage temperature −40 +125 °C

T

j

junction temperature − 125 °C

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air

TEA1062; TEA1062A 75 K/W
TEA1062M1; TEA1062AM1 81 K/W
TEA1062T; TEA1062AT (note 1) 110 K/W

1997 Sep 03 10

Philips Semiconductors Product specification

Low voltage transmission circuits with
dialler interface

TEA1062; TEA1062A

Fig.6 TEA1062 and TEA1062A safe operating

area.

(1) T

amb

=45°C; P

tot

= 1068 mW.

(2) T

amb

=55°C; P

tot

= 934 mW.

(3) T

amb

=65°C; P

tot

= 800 mW.

(4) T

amb

=75°C; P

tot

= 666 mW.

handbook, halfpage

212

150

30

70

110

MLC200

46810

130

90

50

I

LN

(mA)

V

LNVSLPE

(V)

(1)

(2)

(3)

(4)

Fig.7 TEA1062M1 and TEA1062AM1 safe

operating area.

(1) T

amb

=45°C; P

tot

= 988 mW.

(2) T

amb

=55°C; P

tot

= 864 mW.

(3) T

amb

=65°C; P

tot

= 741 mW.

(4) T

amb

=75°C; P

tot

= 617 mW.

handbook, halfpage

212

150

30

70

110

MLC201

46810

130

90

50

I

LN

(mA)

V

LNVSLPE

(V)

(1)

(2)

(3)

(4)

Fig.8 TEA1062T and TEA1062AT safe operating

area.

(1) T

amb

=45°C; P

tot

= 727 mW.

(2) T

amb

=55°C; P

tot

= 636 mW.

(3) T

amb

=65°C; P

tot

= 545 mW.

(4) T

amb

=75°C; P

tot

= 454 mW.

handbook, halfpage

212

150

30

70

110

MLC202

46810

130

90

50

I

LN

(mA)

V

LNVSLPE

(V)

(1)
(2)
(3)

(4)

1997 Sep 03 11

Philips Semiconductors Product specification

Low voltage transmission circuits with
dialler interface

TEA1062; TEA1062A

CHARACTERISTICS

I

line

= 11 to 140 mA; VEE= 0 V; f = 800 Hz; T

amb

=25°C; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies LN and V

CC

(pins 1 and 13)

V

LN

voltage drop over circuit between LN
and V

EE

MIC inputs open-circuit

I

line

=1mA − 1.6 − V

I

line

=4mA − 1.9 − V

I

line

= 15 mA 3.55 4.0 4.25 V

I

line

= 100 mA 4.9 5.7 6.5 V

I

line

= 140 mA −−7.5 V

∆V

LN

/∆T variation with temperature I

line

=15mA −−0.3 − mV/K

V

LN

voltage drop over circuit between LN
and VEE with external resistor R

VA

I

line

=15mA

R

VA

(LN to REG) = 68 kΩ− 3.5 − V

R

VA

(REG to SLPE) = 39 kΩ− 4.5 − V

I

CC

supply current VCC= 2.8 V − 0.9 1.35 mA

V

CC

supply voltage available for peripheral
circuitry

I

line

= 15 mA; MUTE = HIGH

TEA1062 I

p

= 1.2 mA 2.2 2.7 − V

I

p

=0mA − 3.4 − V

V

CC

supply voltage available for peripheral
circuitry

I

line

= 15 mA; MUTE = LOW

TEA1062A I

p

= 1.2 mA 2.2 2.7 − V

I

p

=0mA − 3.4 − V

Microphone inputs MIC− and MIC+ (pins 6 and 7)
Z

i

 input impedance

differential between MIC− and MIC+ − 64 − kΩ
single-ended MIC− or MIC+ to V

EE

− 32 − kΩ
CMRR common mode rejection ratio − 82 − dB
G

v

voltage gain MIC+ or MIC− to LN I

line

= 15 mA; R7 = 68 kΩ 50.5 52.0 53.5 dB

∆G

vf

gain variation with frequency
referenced to 800 Hz

f = 300 and 3400 Hz −±0.2 − dB

∆G

vT

gain variation with temperature
referenced to 25 °C

without R6; I

line

= 50 mA;

T

amb

= −25 and +75 °C

−±0.2 − dB

DTMF input (pin 11)

|Z

i

| input impedance − 20.7 − kΩ

G

v

voltage gain from DTMF to LN I

line

= 15 mA; R7 = 68 kΩ 24.0 25.5 27.0 dB

∆G

vf

gain variation with frequency
referenced to 800 Hz

f = 300 and 3400 Hz −±0.2 − dB

∆G

vT

gain variation with temperature
referenced to 25 °C

I

line

= 50 mA;

T

amb

= −25 and +75 °C

−±0.2 − dB

1997 Sep 03 12

Philips Semiconductors Product specification

Low voltage transmission circuits with
dialler interface

TEA1062; TEA1062A

Gain adjustment inputs GAS1 and GAS2 (pins 2 and 3)

∆G

v

transmitting amplifier gain variation by
adjustment of R7 between
GAS1 and GAS2

−8 − 0dB

Sending amplifier output LN (pin 1)

V

LN(rms)

output voltage (RMS value) THD = 10%

I

line

=4mA − 0.8 − V

I

line

= 15 mA 1.7 2.3 − V

V

no(rms)

noise output voltage (RMS value) I

line

= 15 mA; R7 = 68 kΩ;
200 Ω between MIC− and
MIC+; psophometrically
weighted (P53 curve)

−−69 − dBmp

Receiving amplifier input IR (pin 10)

Zi input impedance − 21 − kΩ

Receiving amplifier output QR (pin 4)

Z

o

 output impedance − 4 −Ω

G

v

voltage gain from IR to QR I

line

= 15 mA; RL= 300 Ω
(from pin 9 to pin 4)

29.5 31 32.5 dB

∆G

vf

gain variation with frequency
referenced to 800 Hz

f = 300 and 3400 Hz −±0.2 − dB

∆G

vT

gain variation with temperature
referenced to 25 °C

without R6; I

line

= 50 mA;

T

amb

= −25 and +75 °C

−±0.2 − dB

V

o(rms)

output voltage (RMS value) THD = 2%; sine wave drive;

R4 = 100 kΩ; I

line

=15mA;

Ip=0mA

R

L

= 150 Ω 0.22 0.33 − V

R

L

= 450 Ω 0.3 0.48 − V

V

o(rms)

output voltage (RMS value) THD = 10%; R4 = 100 kΩ;

RL= 150 Ω; I

line

=4mA

− 15 − mV

V

no(rms)

noise output voltage (RMS value) I

line

= 15 mA; R4 = 100 kΩ;
IR open-circuit
psophometrically weighted
(P53 curve); RL= 300 Ω

− 50 −µV

Gain adjustment input GAR (pin 5)

∆G

v

receiving amplifier gain variation by
adjustment of R4 between GAR and QR

−11 − 0dB

Mute input (pin 12)

V

IH

HIGH level input voltage 1.5 − V

CC

V

V

IL

LOW level input voltage −−0.3 V

I

MUTE

input current − 815µA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1997 Sep 03 13

Philips Semiconductors Product specification

Low voltage transmission circuits with
dialler interface

TEA1062; TEA1062A

Reduction of gain

∆G

v

MIC+ or MIC− to LN

TEA1062 MUTE = HIGH − 70 − dB
TEA1062A

MUTE = LOW − 70 − dB

G

v

voltage gain from DTMF to QR R4 = 100 kΩ; RL= 300 Ω

TEA1062 MUTE = HIGH −−17 − dB
TEA1062A MUTE = LOW −−17 − dB

Automatic gain control input AGC (pin 15)

∆G

v

controlling the gain from IR to QR
and the gain from MIC+, MIC− to LN

R6 = 110 kΩ
(between AGC and VEE)
I

line

=70mA

gain control range −−5.8 − dB

I

lineH

highest line current for maximum gain − 23 − mA

I

lineL

lowest line current for minimum gain − 61 − mA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Fig.9 Supply arrangement.

handbook, full pagewidth

MBA357 - 1

SLPESTABREG

V

EE

V

CC

LN

I

line

SLPE

I

AC

DC

peripheral

circuits

C1

0.5 mA

0.5 mA

SLPE

I

R

exch

V

exch

R

line R1

I

CC

I

p

C3 R5 R9

TEA1062
TEA1062A

1997 Sep 03 14

Philips Semiconductors Product specification

Low voltage transmission circuits with
dialler interface

TEA1062; TEA1062A

Fig.10 Typical current Ip available from VCC for peripheral circuitry.

handbook, halfpage

012 4

2.4

0

0.8

1.6

MSA504

3

VCC(V)

I

p

(mA)

(1)

(2)

The supply possibilities can be increased by setting the voltage drop over the circuit VLN to a higher value by resistor RVA connected between REG and
SLPE.

V

CC

> 2.2 V; I

line

= 15 mA at VLN= 4 V; R1 = 620 Ω; R9 = 20 Ω.
(1) Ip= 2.1 mA. Is valid when the receiving amplifier is not driven or when MUTE = HIGH (TEA1062), MUTE = LOW (TEA1062A).
(2) Ip= 1.7 mA. Is valid when MUTE = LOW (TEA1062), MUTE = HIGH (TEA1062A) and the receiving amplifier is driven; V

o(rms)

= 150 mV,

R

L

= 150 Ω.

1997 Sep 03 15

Philips Semiconductors Product specification

Low voltage transmission circuits with
dialler interface

TEA1062; TEA1062A

Fig.11 Alternative microphone arrangements.

(1) Resistor may be connected to reduce the terminating impedance.

ndbook, full pagewidth

MSA505

V

EE

V

CC

MIC

MIC

MIC

MIC

MIC

MIC

(1)

(a) (b) (c)

13

6

7

9

7

6

7

6

(a) Magnetic or dynamic microphone.
(b) Electret microphone.
(c) Piezoelectric microphone.

Fig.12 Alternative receiver arrangements.

(1) Resistor may be connected to prevent distortion (inductive load).
(2) Resistor is required to increase the phase margin (capacitive load).

andbook, full pagewidth

(1)

MSA506

(2)

QR

(a) (b) (c)

4

9

4

9

V

EE

QR

V

EE

QR

V

EE

4

9

(a) Dynamic earpiece.
(b) Magnetic earpiece.
(c) Piezoelectric earpiece.

1997 Sep 03 16

Philips Semiconductors Product specification

Low voltage transmission circuits with
dialler interface

TEA1062; TEA1062A

Table 1 Values of resistor R6 for optimum line-loss compensation at various values of exchange supply voltage

(V

exch

) and exchange feeding bridge resistance (R

exch

); R9 = 20 Ω.

V

exch

(V)

R6 (kΩ)

R

exch

= 400 Ω R

exch

= 600 Ω R

exch

= 800 Ω R

exch

= 1000Ω

36 100 78.7 −−
48 140 110 93.1 82
60 −−120 102

Fig.13 Variation of gain as a function of line current with R6 as a parameter.

handbook, full pagewidth

MSA507 - 1

6

4

2

0

∆G

v

(dB)

140120100806040200

78.7 kΩ

110 kΩ 140 kΩ

R6 =

∞

I (mA)

line

R9 = 20 Ω.

1997 Sep 03 17

Philips Semiconductors Product specification

Low voltage transmission circuits with
dialler interface

TEA1062; TEA1062A

Fig.14 Test circuit for defining TEA1062 voltage gain of MIC+, MIC− and DTMF inputs.

Voltage gain is defined as Gv=20logVo/Vi.
For measuring gain from MIC+ and MIC− the MUTE input should be LOW or open-circuit.
For measuring the DTMF input, the MUTE input should be HIGH.
Inputs not being tested should be open-circuit.

handbook, full pagewidth

I

line

MSA508

R6

R5

3.6
kΩ

R9
20 Ω

16

SLPESTABAGCREG

V

EE

914 815

GAS2

GAS1

2

3

R7
68 kΩ

R4
100 kΩ

C4
100 pF

C7 1 nF

C8
1 nF

C6

100 pF

100 µF

R

L

600 Ω

V

o

V

CC

13 1

LN

R1

620 Ω

10 to 140 mA

10 µF

V

i

C1

100 µF

V

i

10

7

6

11

12

IR

MIC

MIC

DTMF

MUTE

TEA1062

QR

GAR

4

5

C3

4.7
µF

1997 Sep 03 18

Philips Semiconductors Product specification

Low voltage transmission circuits with
dialler interface

TEA1062; TEA1062A

Fig.15 Test circuit for defining TEA1062A voltage gain of MIC+, MIC− and DTMF inputs.

Voltage gain is defined as Gv=20logVo/Vi.
For measuring gain from MIC+ and MIC− the MUTE input should be HIGH.
For measuring the DTMF input, the MUTE input should be LOW or open-circuit.
Inputs not being tested should be open-circuit.

handbook, full pagewidth

I

line

MBA355

R6

16

SLPESTABAGCREG

V

EE

9

14 815

GAS2

GAS1

2

3

C4
100 pF

C7 1 nF

C8

1 nF

C6

100 pF

R

L

V

o

V

CC

13 1

LN

R1

10 to 140 mA

V

i

C1

V

i

10

7

6

11

12

IR

MIC

MIC

DTMF

MUTE

TEA1062A

QR

GAR

4

5

R5

3.6
kΩ

R9
20 Ω

R7
68 kΩ

R4
100 kΩ

100 µF

600 Ω

620 Ω

10 µF

100 µF

C3

4.7
µF

1997 Sep 03 19

Philips Semiconductors Product specification

Low voltage transmission circuits with
dialler interface

TEA1062; TEA1062A

Fig.16 Test circuit for defining TEA1062 voltage gain of the receiving amplifier.

Voltage gain is defined as Gv=20logVo/Vi.

handbook, full pagewidth

MSA509

R6

16

SLPESTABAGCREG

V

EE

914 815

GAS2

GAS1

2

3

R7

C8
1 nF

C6

100 pF

V

CC

13 1

LN

R1

I

line

10 to 140 mA

V

i

C1

10

7

6

11

12

IR

MIC

MIC

DTMF

MUTE

TEA1062

GAR

C4
100 pF

C7 1 nF

QR

4

5

V

o

C2

Z

L

R5

3.6
kΩ

R9
20 Ω

R4
100
kΩ

100 µF

600 Ω

620 Ω

10 µF

100 µF

C3

4.7
µF

Fig.17 Test circuit for defining TEA1062A voltage gain of the receiving amplifier.

Voltage gain is defined as Gv=20logVo/Vi.

handbook, full pagewidth

MBA356

R6

16

SLPESTABAGCREG

V

EE

914 815

GAS2

GAS1

2

3

R7

C8

1 nF

C6

100 pF

V

CC

13 1

LN

R1

I

line

10 to 140 mA

V

i

C1

10

7

6

11

12

IR

MIC

MIC

DTMF

MUTE

TEA1062A

GAR

C4
100 pF

C7 1 nF

QR

4

5

V

o

C2

Z

L

R5

3.6
kΩ

R9
20 Ω

R4
100
kΩ

100 µF

600 Ω

620 Ω

10 µF

100 µF

C3

4.7
µF

1997 Sep 03 20

Philips Semiconductors Product specification

Low voltage transmission circuits with
dialler interface

TEA1062; TEA1062A

APPLICATION INFORMATION

handbook, full pagewidth

MBA358 - 1

SLPE STABAGCREG

V

EEGAS2GAS1

MIC

MIC

DTMF

MUTE

TEA1062A

GAR

QR

16 2

314

15 8

9

C6

R7

100 pF

R

VA

(R )

16 - 14

R5

3.6

kΩ

R6

C3

4.7

µF

C8

1 nF

R9

20 Ω

6

7

C4

100

pF

C7

1 nF

4

5

R3

3.92

kΩ

R4

C2

10

C5

100 nF

R2

130 kΩ

BZX79 -

C12

R8

390 Ω

Z

bal

R10

13 Ω

BAS11

(2x)

BZW14

(2x)

telephone

line

IR

LN

V

CC

R1

620 Ω

11

12

113

C1

100

µF

from dial

and

control circuits

(1)

Fig.18 Typical application of TEA1062A, with piezoelectric earpiece and DTMF dialling.

The diode bridge, the Zener diode and R10 limit the current into, and the voltage across, the circuit during line transients.

A different protection arrangement is required for pulse dialling or register recall.

The DC line voltage can be set to a higher value by the resistor R

VA

(REG to SLPE).

Further application information can be found in our publication

“Applications Handbook for Wired telecom systems, IC03b”

, order number 9397 750 00811.

(1) Pin 12 is active HIGH (MUTE) for TEA1062.

1997 Sep 03 21

Philips Semiconductors Product specification

Low voltage transmission circuits with
dialler interface

TEA1062; TEA1062A

handbook, full pagewidth

MLC203

telephone

line

cradle

contact

TEA1062

LN V

CC

DTMF
MUTE

V

EE

V

DD

V

SS

M1 PCD3310

BSN254A

DP/FLO

TONE

R1

620 Ω

Fig.19 Typical simplified application of the TEA1062.

(a) DTMF pulse set with CMOS bilingual dialling circuit PCD3310. The dashed line shows an optional flash (register recall by timed loop break).

handbook, full pagewidth

MLC204

telephone

line

cradle

contact

TEA1062A

LN V

CC

DTMF

MUTE

V

EE

V

DD

V

SS

M1 PCD3310T

BSN254A

DP/FLO

TONE

R1

620 Ω

Fig.20 Typical simplified application of the TEA1062A.

(a) DTMF pulse set with CMOS bilingual dialling circuit PCD3310T. The dashed line shows an optional flash (register recall by timed loop break).

1997 Sep 03 22

Philips Semiconductors Product specification

Low voltage transmission circuits with
dialler interface

TEA1062; TEA1062A

PACKAGE OUTLINES

UNIT

A

max.

1 2

b

1

cEe M

H

L

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

inches

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

SOT38-1

92-10-02
95-01-19

A

min.

A

max.

b

max.

w

M

E

e

1

1.40

1.14

0.055

0.045

0.53

0.38

0.32

0.23

21.8

21.4

0.86

0.84

6.48

6.20

0.26

0.24

3.9

3.4

0.15

0.13

0.2542.54 7.62

0.30

8.25

7.80

0.32

0.31

9.5

8.3

0.37

0.33

2.2

0.087

4.7 0.51 3.7

0.15

0.021

0.015

0.013

0.009

0.010.100.0200.19

050G09 MO-001AE

M

H

c

(e )

1

M

E

A

L

seating plane

A

1

w M

b

1

e

D

A

2

Z

16

1

9

8

b

E

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

(1) (1)

D

(1)

Z

DIP16: plastic dual in-line package; 16 leads (300 mil); long body

SOT38-1

1997 Sep 03 23

Philips Semiconductors Product specification

Low voltage transmission circuits with
dialler interface

TEA1062; TEA1062A

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

SOT38-4

92-11-17
95-01-14

M

H

c

(e )

1

M

E

A

L

seating plane

A

1

w M

b

1

b

2

e

D

A

2

Z

16

1

9

8

E

pin 1 index

b

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

UNIT

A

max.

12

b

1

(1) (1)

(1)

b

2

cD E e M

Z

H

L

mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

min.

A

max.

b

max.

w

M

E

e

1

1.73

1.30

0.53

0.38

0.36

0.23

19.50

18.55

6.48

6.20

3.60

3.05

0.2542.54 7.62

8.25

7.80

10.0

8.3

0.764.2 0.51 3.2

inches

0.068

0.051

0.021

0.015

0.014

0.009

1.25

0.85

0.049

0.033

0.77

0.73

0.26

0.24

0.14

0.12

0.010.10 0.30

0.32

0.31

0.39

0.33

0.0300.17 0.020 0.13

DIP16: plastic dual in-line package; 16 leads (300 mil)

SOT38-4

1997 Sep 03 24

Philips Semiconductors Product specification

Low voltage transmission circuits with
dialler interface

TEA1062; TEA1062A

REFERENCES

OUTLINE
VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

SOT38-9

97-07-24

M

H

c

M

E

A

L

seating plane

w M

e

D

A

2

A

1

b

1

b

2

Z

16

1

9

8

E

pin 1 index

b

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.01 inches maximum per side are not included.

UNIT

A

max.

b

1

(1) (1)

(1)

b

2

cD E e M

H

Z

L

mm

DIMENSIONS (mm dimensions are derived from the original inch dimensions)

A

1

min.

A

2

max.

b

max.

w

M

E

e

1

1.65

1.40

0.51

0.41

0.36

0.20

19.30

18.80

6.45

6.24

3.81

2.92

0.2542.54 7.62

8.23

7.62

9.40

8.38

0.764.32 0.38 3.56

inches

0.065

0.055

0.020

0.016

0.014

0.008

1.14

0.76

0.045

0.030

0.76

0.74

0.254

0.246

0.150

0.115

0.010.10 0.30

0.324

0.300

0.37

0.33

0.0300.17 0.015 0.14

DIP16: plastic dual in-line package; 16 leads (300 mil)

SOT38-9

(e1)

1997 Sep 03 25

Philips Semiconductors Product specification

Low voltage transmission circuits with
dialler interface

TEA1062; TEA1062A

X

w M

θ

A

A

1

A

2

b

p

D

H

E

L

p

Q

detail X

E

Z

e

c

L

v M

A

(A )

3

A

8

9

1

16

y

pin 1 index

UNIT

A

max.

A1A2A

3

b

p

cD

(1)E(1) (1)

eHELLpQZywv θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

inches

1.75

0.25

0.10

1.45

1.25

0.25

0.49

0.36

0.25

0.19

10.0

9.8

4.0

3.8

1.27

6.2

5.8

0.7

0.6

0.7

0.3

8
0

o
o

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

1.0

0.4

SOT109-1

95-01-23
97-05-22

076E07S MS-012AC

0.069

0.010

0.004

0.057

0.049

0.01

0.019

0.014

0.0100

0.0075

0.39

0.38

0.16

0.15

0.050

1.05

0.041

0.244

0.228

0.028

0.020

0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

0 2.5 5 mm

scale

SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

1997 Sep 03 26

Philips Semiconductors Product specification

Low voltage transmission circuits with
dialler interface

TEA1062; TEA1062A

SOLDERING
Plastic dual in-line packages

B

Y DIP OR WAVE

The maximum permissible temperature of the solder is
260 °C; this temperature must not be in contact with the
joint for more than 5 s. The total contact time of successive
solder waves must not exceed 5 s.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified storage maximum. If the printed-circuit board has
been pre-heated, forced cooling may be necessary
immediately after soldering to keep the temperature within
the permissible limit.

R

EPAIRING SOLDERED JOINTS

Apply the soldering iron below the seating plane (or not
more than 2 mm above it). If its temperature is below
300 °C, it must not be in contact for more than 10 s; if
between 300 and 400 °C, for not more than 5 s.

Plastic small-outline packages

BYWAVE
During placement and before soldering, the component

must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.

A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.

B

Y SOLDER PASTE REFLOW

Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be
applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.

R

EPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING

IRON OR PULSE

-HEATED SOLDER TOOL)

Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.)

For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.

1997 Sep 03 27

Philips Semiconductors Product specification

Low voltage transmission circuits with
dialler interface

TEA1062; TEA1062A

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Internet: http://www.semiconductors.philips.com

Philips Semiconductors – a worldwide company

© Philips Electronics N.V. 1996 SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

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United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: seeSouth America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15thfloor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. [phone], Fax. [phone]
Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]/xxx
France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,

Tel. [phone], Fax. [phone]
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. [phone], Fax. [phone]
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,

Tel. [phone], Fax. [phone]

Hungary: seeAustria
India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.

Worli, MUMBAI 400 018, Tel. [phone], Fax. [phone]

Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. [phone], Fax. [phone]
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180,

Tel. [phone], Fax. [phone]
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,

20124 MILANO, Tel. [phone], Fax. [phone]
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. [phone], Fax. [phone]
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

Tel. [phone], Fax. [phone]
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. [phone], Fax. [phone]
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. [phone]
Middle East: see Italy

Printed in The Netherlands 417027/1200/05/pp28 Date of release: 1997 Sep 03 Document order number: 9397 750 02819