Datasheet TEA0679T Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TEA0679T

2

I

C-bus controlled dual Dolby*
B-type noise reduction circuit for
playback applications

Product specification
Supersedes data of 1998 Jun 24
File under Integrated Circuits, IC01

1998 Nov 12

Philips Semiconductors Product specification

I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications

FEATURES

• Dual Noise Reduction (NR) channels

• Head preamplifiers

• Reverse head switching

• Automatic Music Search (AMS)

• Blank skip

• Mute position

• Equalization with electronically switched time constants

• Switch functions and level adjustment controlled via

I2C-bus

• Optional switch inputs TTL compatible

• Dolby reference level = 387.5 mV

• Contained in a 32-pin small outline package

• Improved EMC behaviour.

GENERAL DESCRIPTION

The TEA0679T is a bipolar integrated circuit that provides
two channels of Dolby B noise reduction for playback
applications in car radios. It includes head and
equalization amplifiers with electronically switchable time
constants. The device also includes electronically
switchable inputs for tape drivers with reverse heads.

This device detects pauses of music in the Automatic
Music Search (AMS) scan mode (for applications with an
intelligent controlled tape driver) or AMS latch mode (for
applications with a simple controlled tape driver).

For both modes the delay time can be fixed by using an
external resistor. In the blank skip mode the IC can detect
pauses of music during playback and allows a
microcontroller to react on this situation.

The equalization amplifier gain adjustment, the output
offset adjustment and all switching functions are I
controlled. Head switching and equalization time constant
switching can be controlled via separate pins (optional).
The device operates with power supplies from 7.6 to 12 V.
The output overload level increases with increases in
supply voltage.

Current drain varies with the following variables:

• Supply voltage

• Noise reduction on/off

• AMS on/off.

Because of this current drain variation it is advisable to use
a regulated power supply or a supply with a long time
constant.

TEA0679T

2

C-bus

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

CC

I

CC

SN+

-------------­N

ORDERING INFORMATION

TYPE

NUMBER

TEA0679T SO32 plastic small outline package; 32 leads; body width 7.5 mm SOT287-1

Remark Dolby*: Available only to licensees of Dolby Laboratories Licensing Corporation, San Francisco, CA94111,
USA, from whom licensing and application information must be obtained. Dolby is a registered trade-mark of Dolby
Laboratories Licensing Corporation.

1998 Nov 12 2

supply voltage 7.6 − 12 V
supply current − 35 40 mA
signal plus noise-to-noise ratio 78 84 − dB

PACKAGE

NAME DESCRIPTION VERSION

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1998 Nov 12 3

handbook, full pagewidth

BLOCK DIAGRAM

reduction circuit for playback applications

I

2

C-bus controlled dual Dolby* B-type noise

Philips Semiconductors Product specification

BEN
32

1
MAD

SDA
31

I2C-BUS

2
BSC

220 nF

output B

SCL

3
TD

R

t

(ref)

output A

4
BTC

47 nF

EQS
(opt)

10 µF

282930

EQS

10 µF

OUTBDGND AMS
27

65
OUTA

330 nF
(±10%)

270 kΩ
(±10%)

INTB

MUTE

7
INTA

270 kΩ
(±10%)

330 nF

(±10%) (±5%)

100 nF
(±10%)

180 kΩ
(±10%)

CONTRB
2526

DOLBY B

LATCH

AND

RISE TIME

DELAY

TIME

DOLBY B

8
CONTRA

180 kΩ
(±10%)

100 nF
(±10%)

15 nF

(±5%)

HPB
24

AMS

PROCESSOR

LEVEL

DETECTOR

9

(±5%)

4.7 nF
(±5%)

SCB
23

10
SCAHPA

4.7 nF15 nF

BLANK

SKIP

24 kΩ
(±2%)

24 kΩ
(±2%)

390 kΩ

EQB
22

LOGIC

11
EQA

390 kΩ

8.2
nF

5.6
kΩ

5.6
kΩ

8.2
nF

EQ

AMP

EQ

AMP

EQFB
21

12
EQFA

2.7 kΩ

2.7 kΩ

AGND
20

13

V

CC

10 µF

POWER
SUPPLY

10 µF

PRE
AMP

PRE
AMP

470

pF

INB1

INA1

470

pF

HS

(opt)

HS

19

18

TEA0679T

15

14

V

470

pF

INB2
17

16
INA2

ref

100

µF

470

pF

TEA0679T

Fig.1 Block and application diagram.

MHB117

Philips Semiconductors Product specification

I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications

PINNING

SYMBOL PIN DESCRIPTION

MAD 1 programmable address bit
BSC 2 blank skip reference capacitance
TD 3 delay time constant
BTC 4 blank skip integration capacitance
EQS 5 equalization switch input (optional)
OUTA 6 output channel A
INTA 7 integrating filter channel A
CONTRA 8 control voltage channel A
HPA 9 high-pass filter channel A
SCA 10 side chain channel A
EQA 11 equalizing output channel A
EQFA 12 equalizing input channel A
V

CC

INA1 14 input channel A1 (forward or reverse)
V

ref

INA2 16 input channel A2 (reverse or forward)
INB2 17 input channel B2 (reverse or forward)
HS 18 head switch input (optional)
INB1 19 input channel B1 (forward or reverse)
AGND 20 analog ground
EQFB 21 equalizing input channel B
EQB 22 equalizing output channel B
SCB 23 side chain channel B
HPB 24 high-pass filter channel B
CONTRB 25 control voltage channel B
INTB 26 integrating filter channel B
OUTB 27 output channel B
AMS

DGND 29 digital ground
SCL 30 serial clock input
SDA 31 serial data input/output
BEN 32 bus enable

13 supply voltage

15 reference voltage

Automatic Music Search (AMS)

28

output

handbook, halfpage

MAD

1

BSC

2

TD

3

BTC

4

EQS

5

OUTA

6

INTA

7

CONTRA

HPA
SCA
EQA

EQFA

V

CC

INA1

V

INA2

ref

8

TEA0679T

9
10
11
12
13
14
15
16

Fig.2 Pin configuration.

MHB118

TEA0679T

BEN

32

SDA

31

SCL

30

DGND

29

AMS

28

OUTB

27

INTB

26

CONTRB

25

HPB

24

SCB

23

EQB

22

EQFB

21

AGND

20

INB1

19

HS

18

INB2

17

1998 Nov 12 4

Philips Semiconductors Product specification

I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications

FUNCTIONAL DESCRIPTION

The following functions can be controlled via the I2C-bus:

• Equalization time constant switching

• Head switching

• Automatic Music Search (AMS) modes and blank skip

• Noise Reduction (NR) on/off switching

• Mute switching

• Equalization amplifier gain adjustment

• Output offset adjustment.

Dolby B noise reduction only operates correctly if the 0 dB
Dolby level is adjusted at 387.5 mV. The gain adjustment
can also be used to change the AMS level detector
threshold. The IC is able to generate an internal power-on
reset to guarantee a proper start-up behaviour.

Two of the above functions can be controlled via separate
pins (optional), if required.

Head switching is achieved when pin HS is connected to a
LOW level (input IN2 active) or connected to a HIGH level
(input IN1 active).

Equalization time constant switching (70 or 120 µs) is
achieved when pin EQS is connected to a LOW level
(70 µs) or connected to a HIGH level (120 µs).

2

C-bus control is used the respective external function

If I
control pin has to be left open-circuit. When open-circuit
the current state of the function can be observed at these
pins.

Automatic Music Search (AMS) modes and blank skip

If AMS is active (search mode bits SMOD1 = 1 and
SMOD0 = 0 or 1) the NR function is internally switched off
and the equalization time constant is internally forced to
70 µs. The signals of both channels are full-wave rectified
and then added. This means that even if one channel
appears inverted to the other channel the normal AMS
function is ensured.

It is possible to choose between the AMS scan and the
AMS latch mode via the I
internal flip-flop the switching from one mode to the other
must be done via the AMS off state. This guarantees an
appropriate flip-flop reset:

• Start from the initial AMS off state (SMOD1 = 0 and
SMOD0 = 0 or 1)

• Enable the desired AMS operation mode: AMS latch
mode (SMOD1 = 1 and SMOD0 = 0) or AMS scan mode
(SMOD1 = 1 and SMOD0 = 1).

2

C-bus. Due to the usage of an

TEA0679T

For further information on music search see Figs 4 to 8.
If blank skip is active (SMOD1 = 0 and SMOD0 = 1)

periods of music can be detected in the playback mode
using the AMS pin as the detector output. It is possible to
defeat this function via the I
SMOD0 = 0). For further information on blank skip
see Figs 9 and 10.

Offset adjustment procedure

The offset adjustment is performed using two bits in the

2

C-bus write byte 0. The offset monitor bit OMOR enables

I
the AMS output to indicate whether the selected offset
value is positive or negative. The channel select bit OFCH
selects the channel (A or B) which is currently monitored
by the output at pin AMS. The monitoring needs a few
microseconds until the output result is valid. A complete
offset adjustment is performed in the following way:

• Adjust the output to Dolby level using the I
controlled equalization gain adjustment

• Enable the offset monitor and select the channel to be
monitored by transmitting the bits OMOR = 1 and OFCH
(0 = Channel A, 1 = Channel B) to the IC

• If the monitor output (pin AMS) is LOW send the next
offset value OFFCHA or OFFCHB one offset step below
the last valid value. If the monitor output (pin AMS) is
HIGH send the next offset value OFFCHA or OFFCHB
one offset step above the last valid value

• Repeat the last two steps until the monitor output
changes its polarity

• If necessary store the transmitted digital offset value for
the selected channel.

The start value is either set by the power-on reset or the
last I2C-bus transmission. The offset adjustment can be
performed during the power-on reset condition and also
each time the tape driver is not active. A complete digital
offset data set consists of four values: one for each head
(head 1 and head 2) in each channel. After an offset value
transmission the IC stores one value for channel A and
one value for channel B. If a head switch is performed
these values have to be updated via the I2C-bus for the
alternative head.

2

C-bus (SMOD1 = 0 and

2

C-bus

1998 Nov 12 5

Philips Semiconductors Product specification

I2C-bus controlled dual Dolby* B-type noise

TEA0679T

reduction circuit for playback applications

I2C-bus operation mode

The IC is capable of operating with I2C-bus systems that provide either 5 V or digital supply voltage related logic levels
below 5 V. This is achieved using the bus enable (pin 32) with different input voltages. An open pin or input voltages
above 5 V enable 5 V related I2C-bus logic levels. If input voltages between 3 and 5 V are used the IC operates with
I2C-bus logic levels related to these input voltages. To disable the I2C-bus receiver it is necessary to use pin voltages
below the specified LOW level.

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CC

V

i

V

i(n1)

V

i(n2)

V

i(stb)

t

sc

T

stg

T

amb

V

es

supply voltage 0 14 V
input voltage (pins 1 to 32) except pin 5 (EQS),

pin 15 (V
(SDA) to V

), pin 18 (HS), pin 30 (SCL) and pin 31

ref

CC

−0.3 V

CC

V

input voltage at pin 30 (SCL) and pin 31 (SDA) −0.3 +12 V
input voltage at pin 5 (EQS) and pin 18 (HS) −0.3 +6.5 V
standby input voltage at pin 1 (MAD), pin 32 (BEN),

note 1 −0.3 +6.5 V

pin 5 (EQS) and pin 18 (HS)
pin 15 (V

) to VCC short-circuiting duration − 5s

ref

storage temperature −55 +150 °C
operating ambient temperature −40 +85 °C
electrostatic handling voltage for all pins note 2 −2+2kV

note 3 −500 +500 V

Notes

1. The TEA0679T allows a HIGH level at switching pins without voltage (V

= 0; standby mode). This means a

CC

maximum input voltage of 6.5 V for the switching pins.

2. Human body model (1.5 kΩ; 100 pF).

3. Machine model (0 Ω; 200 pF).

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 62 K/W

1998 Nov 12 6

Philips Semiconductors Product specification

I2C-bus controlled dual Dolby* B-type noise

TEA0679T

reduction circuit for playback applications

CHARACTERISTICS

V

= 10 V; f = 20 Hz to 20 kHz; T

CC

(TP) pin OUTA or OUTB; see Fig.1; NR on/AMS off; EQ switch in the 70 µs position; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CC

I

CC

α

m

supply voltage 7.6 10 12 V
supply current − 35 40 mA
channel matching f = 1 kHz; Vo= 0 dB; NR off −0.5 −+0.5 dB

THD total harmonic distortion

(2nd and 3rd harmonic)

H

R

SN+

-------------­N

headroom at output VCC= 7.6 V; THD = 1%;

signal plus noise-to-noise ratio internal gain 40 dB, linear;

PSRR power supply ripple rejection V

V

o

output voltage frequency
response; referenced to TP

α

cs

α

ct

channel separation Vo= 10 dB; f = 1 kHz;

crosstalk between active and
inactive input

R

L

G

v

V

i(offset)(DC)

I

i(bias)

R

EQ

R

i

G

v(ol)

V

− V

ref

load resistance at output AC-coupled; f = 1 kHz;

voltage gain of preamplifier pin INA1/INA2 to pin EQFA;

DC input offset voltage − 2 − mV
input bias current − 0.1 0.4 µA
internal equalization resistor pin EQA/EQB to EQ amplifier

input resistance of head inputs 60 100 − kΩ
open-loop gain pin INA1 or INA2 to pin EQA;

DC output offset voltage at

OUT

pins OUTA and OUTB after
adjustment

=25°C; all levels are referenced to Vo= 387.5 mV (RMS) (0 dB) at test point

amb

f = 1 kHz; V
f = 10 kHz; V

=0dB − 0.08 0.15 %

o

=10dB − 0.15 0.3 %

o

12 −−dB

f = 1 kHz

78 84 − dB
CCIR/ARM weighted;
decode mode; see Fig.41

= 0.25 V; f = 1 kHz;

i(rms)

52 57 − dB
see Fig.38

encode mode; see Fig.41

−25 dB; f = 0.2 kHz −25.9 −24.4 −22.9 dB
0 dB; f = 1 kHz −1.5 0 +1.5 dB

−25 dB; f = 1 kHz −20.8 −19.3 −17.8 dB

−25 dB; f = 5 kHz −21.1 −19.6 −18.1 dB

−35 dB; f = 10 kHz −27.4 −25.9 −24.4 dB

57 63 − dB
see Fig.39

f = 1 kHz; Vo= 10 dB; NR off;

70 77 − dB
see Fig.39

10 −−kΩ
Vo= 12 dB; THD = 1%

29 30 31 dB
pin INB1/INB2 to pin EQFB;
f = 1 kHz

4.7 5.8 6.9 kΩ

A/B output

pin INB1 or INB2 to pin EQB;
additional gain=0dB

f = 10 kHz 80 86 − dB
f = 400 Hz 104 110 − dB

NR off; pins INA1, INA2, INB1
and INB2 connected to V

ref

−20 −+20 mV

1998 Nov 12 7

Philips Semiconductors Product specification

I2C-bus controlled dual Dolby* B-type noise

TEA0679T

reduction circuit for playback applications

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

O

Z

o

V

no(rms)

V

TD

V

offset(DC)

V

offset(AD)

Level adjustment

G

CR

G

step

G

E

DC output current pins OUTA and OUTB

−2 −−mA

connected to ground
pins OUTA and OUTB

connected to V

CC

0.3 −−mA

output impedance − 80 100 Ω
equivalent input noise voltage

(RMS value)

AMS timing (DC level) resistor Rt connected to pin TD VCC− 3 − V
DC offset voltage at pins OUTA

NR off; unweighted;
f = 20 Hz to 20 kHz;
R

f = 900 MHz; V

source

=0Ω

i(rms)

− 0.7 1.4 µV

CC

V

=6V − 40 − mV

and OUTB
overall offset voltage between

−0.4 − +0.4 V
AGND (pin 20) and DGND
(pin 29)

gain control range note 1 24.2 25.2 26.2 dB
step size − 0.4 − dB
step error between any

−−0.4 dB
adjacent step

Switching thresholds

O

PTIONAL EQUALIZATION TIME CONSTANT SWITCH (pin EQS)

V

IL

V

OL

V

IH

V

OH

LOW-level input voltage 70 µs; IL≥−200 µA −0.3 − +0.8 V
LOW-level output voltage 70 µs; IL≤ 1mA −−0.4 V
HIGH-level input voltage 120 µs2−−V
HIGH-level output voltage 120 µs; IL≥−50 µA 2.8 − 3.3 V

OPTIONAL HEAD SWITCH (pin HS)
V

IL

V

OL

V

IH

V

OH

LOW-level input voltage INPUT 2 on; IL≥−150 µA −0.3 − +0.8 V
LOW-level output voltage INPUT 2 on; IL≤ 10 µA −−0.4 V
HIGH-level input voltage INPUT 1 on 2 −−V
HIGH-level output voltage INPUT 1 on; IL≥−50 µA 2.8 − 3.3 V

Search modes

B

LANK SKIP

BS

th(M-P)

t

sw(P-M)

dynamic level threshold blank skip mode; f = 10 kHz −30 −27 −24 dB
switching time pause-to-music blank skip mode; f = 10 kHz;

signal on channel A and B;
note 2

blank skip mode; f = 10 kHz;
signal on one channel; note 2

t

sw(M-P)

switching time music-to-pause blank skip mode; f = 10 kHz;

note 2

2.1 4.15 6.3 ms

4.1 8.3 12.5 ms

10 19 30 ms

1998 Nov 12 8

Philips Semiconductors Product specification

I2C-bus controlled dual Dolby* B-type noise

TEA0679T

reduction circuit for playback applications

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

UTOMATIC MUSIC SEARCH (AMS)

A
t

W(min)(r)

AMS

(P-M)

AMS

(M-P)

OUTPUT (pin AMS)
V

OH

V

OL

Digital part (pins MAD and BEN)

V

IH

V

IL

I

IH

I

IL

Digital part (pins SDA and SCL); note 4
V

IH

V

IL

I

IH

I

IL

V

OL

Notes

1. For Dolby NR level adjust and AMS pause detection level setting.

2. All blank skip timing characteristics are based on the assumption that a signal level change from −33 to −21 dB
pause-to-music or −21 to −33 dB music-to-pause occurs in the specified channels.

3. The high speed of the tape (FF and REW) at the tape head during AMS mode causes a transformation of level and
frequency of the originally recorded signal. It means a boost of signal level of approximately 10 dB and more for
recorded frequencies from 500 Hz to 4 kHz. So the threshold level of−22 dB corresponds to signal levels in PlayBack
(PB) mode of approximately −32 dB. The AMS inputs for each channel are pins SCA and SCB. As the frequency
spectrum is transformed by a factor of approximately 10 to 30 due to the higher tape speed in FF and REW, the
high-pass filter (4.7 nF/24 kΩ) removes the effect of offset voltages but does not affect the music search function.
In the block and application diagram (see Fig.1) the frequency response of the system between tape heads input,
e.g. pins INA2 and INB2, to the AMS input pins SCA and SCB is constant over the whole frequency range (see
Fig.3).

4. These levels correspond to a gain setting of Dolby level at TP (for TP see Fig.41). The gain adjustment can be used
to change the threshold level during AMS operation.

5. The characteristics are in accordance with the I2C-bus specification. Information about the I2C-bus can be found in
the brochure

minimum pulse width rise time AMS scan mode 2 − 10 ms

AMS latch mode 130 − 170 ms

signal level at output for AMS
switching pause-to-music

AMS switching hysteresis

AMS mode; f = 10 kHz;

−23.7 −21 −18 dB

notes 3 and 4; see Fig.40
AMS mode; f = 10 kHz −0.7 −1 −1.3 dB

music-to-pause

HIGH-level output voltage IL≥−1 mA 2.8 − 3.3 V
LOW-level output voltage IL≤ 1mA −−0.4 V

HIGH-level input voltage 3 − V

CC

V
LOW-level input voltage −0.3 −+1.5 V
HIGH-level input current −10 −+10 µA
LOW-level input current −10 −+10 µA

HIGH-level input voltage BEN (pin 32) open-circuit 3 − V

5V≤V
3V≤V

≤ V

BEN
BEN

CC

< 5 V 0.7V

3 − V

− V

BEN

CC
CC
CC

V

V

V
LOW-level input voltage BEN (pin 32) open-circuit −0.3 −+1.5 V

5V≤V
3V≤V

≤ V

BEN
BEN

CC

<5V −0.3 − 0.3V

−0.3 −+1.5 V

BEN

V
HIGH-level input current VCC=0to12V −10 −+10 µA
LOW-level input current −10 −+10 µA
LOW-level output voltage SDA IL=3mA −−0.4 V

“The I2C-bus and how to use it”

(order number 9398 393 40011).

1998 Nov 12 9

Philips Semiconductors Product specification

I2C-bus controlled dual Dolby* B-type noise

TEA0679T

reduction circuit for playback applications

General note

It is recommended to switch off VCC with a gradient of 400 V/s at maximum to avoid plops on tape in the event of contact
between tape and tape head while switching off.

AMS delay time
Table 1 AMS delay time set by resistor R

RESISTOR VALUE R

(kΩ) DELAY TIME tdTYP. (ms) TOLERANCE (%)

t

68 23 20
150 42 15
180 48 15
220 56 15
270 65 10
330 76 10
470 98 10
560 112 10
680 126 10
820 142 10

1000 160 10

at pin TD

t

AMS threshold level

−20

handbook, halfpage

AMS

(P-M)

(dB)

−30

−40

−50

−60

(1) AMS threshold level for application circuit (see Fig.1).
(2) AMS threshold level for test circuit (see Fig.40).

MHB119

(1)

(2)

2

10

3

10

4

10

f (Hz)

5

10

Fig.3 AMS threshold level.

1998 Nov 12 10

Philips Semiconductors Product specification

I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications

Short description of music search

A system for music search consists mainly of a level and a
time detection circuit (see Fig.4). For adapting and
decoupling the input signal is amplified (A), then rectified
(B) and smoothed with a time constant (C). Thus the
voltage at (C) corresponds to the signal level and will be
compared to the predefined pause level at the first
comparator (D), the level detector. If the signal level
becomes smaller than the pause level, the level detector
changes its output signal. Due to the output level of the
level detector the capacitor of the second time constant (E)
will be charged, respectively discharged.

handbook, full pagewidth

INPUT

(A)

(B)

(C)

COMPARATOR 1 COMPARATOR 2

V

I

t

1

TEA0679T

If the pause level of the input signal remains for a certain
time period, the voltage at the capacitor reaches a certain
value, which corresponds to an equivalent time value.
The voltage at the capacitor will be compared to a
predefined time-equivalent voltage by the second
comparator (F), the time detector. If the pause level of the
input signal remains for this predefined time, the time
detector changes its output level to pause found status.

(D)

(E) (F)

V

t

t

2

OUTPUT

AMPLIFIER RECTIFIER

LEVEL DETECTOR TIME DETECTOR

MED624

Fig.4 Integrated music search function.

1998 Nov 12 11

Philips Semiconductors Product specification

I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications

Description of the principle timing diagram for AMS
scan mode without initial input signal (see Fig.5)

By activating the AMS scan mode the AMS output level
directly indicates whether the input level corresponds to a
pause level (V
At t0 the AMS scan mode is activated. Without a signal at
Vin, the following initial procedure runs until the AMS
output changes to a LOW level: due to no signal at Vin the
voltage at the level detector input VI (CONTRA) remains
below the level threshold and the second time constant will
be discharged (time detector input Vt). When Vt exceeds
the time threshold level, the time detector output changes
to LOW level. Now the initial procedure is completed.

If a signal burst appears at t3, the level detector input
voltage rises immediately and causes its output to charge
the second time constant, which supplies the input voltage
Vt for the time detector.

handbook, full pagewidth

= LOW) or not (V

AMSEQ

AMS on

V

in

t

r

AMSEQ

= HIGH).

t

d

t

f

TEA0679T

When V
time tr (at t4) the AMS output changes to HIGH. If the signal
burst ends at t5 the level detector input VI falls to its LOW
level. Discharging of the second time constant begins
when the level threshold is exceeded at t6. The circuit then
measures the delay time td, which is externally fixed by a
resistor and defines the length of a pause to be detected.
If no signal appears at Vin within the time interval td, the
time detector output switches the AMS output to a LOW
level at t7.

If a plop noise pulse appears at Vin (t8) with a pulse width
less than the rise time tr>tb, the plop noise will not be
detected as music. The AMS output remains LOW.

Similarly the system handles no music pulses tp: when
music appears at t11 with a small interruption at t13, this
interruption will not affect the AMS output for tp<td.

tb < t

exceeds the upper threshold level after the rise

t

r

tp < t

d

V

l

level threshold

V

ref

V

t

upper threshold

(hysteresis)

time threshold

V

AMSEQ

4.5 V

output signal

to microprocessor

t

0

tr= rise time; td= delay time; tb= burst time; tp= pause time; tf= fall time.

t3t

t5t

4

6

t

7

t8t9t

t

Vl: voltage at
level detector
input
pin 8 (CONTRA)

t

Vt: voltage at
time detector
input
pin 25 (CONTRB)

t

t

10

t11t

12t13t14

t

15

MHB120

Fig.5 AMS scan mode without initial input signal.

1998 Nov 12 12

Philips Semiconductors Product specification

I2C-bus controlled dual Dolby* B-type noise

TEA0679T

reduction circuit for playback applications

Description of the principle timing diagram for AMS scan mode with initial input signal (see Fig.6)
The AMS scan mode is activated at t0. With an input signal at Vin, the following initial procedure runs until the circuit gets

a steady state status.
Due to the signal at Vin the voltage at the level detector input VI (CONTRA) slides to a value which is defined by a limiter.

This voltage causes the level detector output to charge the second time constant (time detector input Vt) to its maximum
voltage level at t1. The initial procedure is now completed.

The following behaviour does not differ from the description in Section “Description of the principle timing diagram for
AMS scan mode without initial input signal (see Fig.5)”.

handbook, full pagewidth

AMS on

V

in

t

d

t

f

tb < t

r

tp < t

r

t

V

l

level threshold

V

ref

V

t

upper threshold

(hysteresis)

time threshold

V

AMSEQ

4.5 V

output signal

to microprocessor

t0t

tr= rise time; td= delay time; tb= burst time; tp= pause time; tf= fall time.

t5t

1

6

t

7

t8t9t

10

t11t

12t13t14

Vl: voltage at
level detector
input
pin 8 (CONTRA)

t

Vt: voltage at
time detector
input
pin 25 (CONTRB)

t

t

t

15

MHB121

Fig.6 AMS scan mode with initial input signal.

1998 Nov 12 13

Philips Semiconductors Product specification

I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications

Description of the principle timing diagram for AMS
latch mode without initial input signal (see Fig.7)

This is similar to the description of the principle timing
diagram from AMS scan mode. It only differs in its initial
behaviour and its rise time t
different tr does not occur in the principle timing diagrams
for latch and scan mode).

Running in AMS latch mode, the circuit may be simply
applied to drive a stop solenoid via a power FET. So a
further processing of the AMS output signal is not
necessary. Because there is no processor to make a
decision whether there is plop noise or not, for this mode
the rise time tr is extended to approximately 150 ms.

handbook, full pagewidth

AMS on

V

in

(it should be noted that the

r

t

r

t

d

t

f

TEA0679T

By activating the AMS latch mode the AMS output will not
change to a LOW level at t
A latch forces the AMS output to remain HIGH until a
signal appears at Vin (t4). After t4 the latch will not affect the
output until the AMS latch mode is started again.
The existence of the latch appears necessary if the AMS
output, for example, drives a stop solenoid via a power
FET. The LOW output level will cause a drive of the stop
solenoid. This will happen after a maximum time of t
occurs without any input signal. If there is no music on tape
for a long time (e.g. at tape end), the AMS mode will be
activated repeatedly as long as there is no signal at Vin.
Thus the circuit waits until music appears before detecting
the pauses.

tb < t

r

if there is no initial signal at Vin.

0

d

tp < t

d

V

l

level threshold

V

ref

V

t

upper threshold

(hysteresis)

time threshold

H

internal

latch status

output signal

to power FET

tr= rise time; td= delay time; tb= burst time; tp= pause time; tf= fall time.

V

AMSEQ

4.5 V

L

t

0

t3t

t5t

4

6

t

7

t8t9t

t

Vl: voltage at
level detector
input
pin 8 (CONTRA)

t

Vt: voltage at
time detector
input
pin 25 (CONTRB)

t

t

t

10

t11t12t13t

t

14

15

MHB122

Fig.7 AMS latch mode without initial input signal.

1998 Nov 12 14

Philips Semiconductors Product specification

I2C-bus controlled dual Dolby* B-type noise

TEA0679T

reduction circuit for playback applications

Description of the principle timing diagram for AMS latch mode with initial input signal (see Fig.8)
This is similar to the description in Section “Description of the principle timing diagram for AMS scan mode with initial

input signal (see Fig.6)”. It only differs in its rise time tr and a release of its internal latch when voltage Vt exceeds the
upper threshold between t0 and t1. The initial procedure is now completed.

The following behaviour does not differ from the description in Section “Description of the principle timing diagram for
AMS latch mode without initial input signal (see Fig.7)”.

handbook, full pagewidth

AMS on

V

in

V

l

t

d

t

f

tb < t

r

tp < t

d

t

level threshold

V

upper threshold

(hysteresis)

time threshold

internal

latch status

V

AMSEQ

4.5 V

output signal

to power FET

ref

Vl: voltage at
level detector
input
pin 8 (CONTRA)

t

V

t

H

L

t0t

t5t

1

6

t

7

t8t9t

10

t11t

12t13t14

t

15

Vt: voltage at
time detector
input
pin 25 (CONTRB)

t

t

t

MHB123

tr= rise time; td= delay time; tb= burst time; tp= pause time; tf= fall time.

Fig.8 AMS latch mode with initial input signal.

1998 Nov 12 15

Philips Semiconductors Product specification

I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications

Short description of blank skip

The blank skip system is intended to detect pauses of
music during playback mode. It consists of two input signal
level comparators, an integration capacitor and an output
comparator with hysteresis. The DC voltage of the inputs
A and B, increased by the level threshold value, is used as
the reference voltage for the input comparators. If input
A or B exceeds this voltage the integration capacitor is
discharged. If this voltage falls below the lower threshold
the output comparator changes its polarity to the music
found status.

handbook, full pagewidth

INPUT A

COMPARATOR

TEA0679T

In the event that none of the two inputs A or B exceeds the
level threshold the integration capacitor is charged. After
its voltage has exceeded the upper threshold of the output
comparator the output changes its polarity to the pause
found status.

It is recommended to process the output signal with a
microcontroller to perform, for example, spike suppression
for a certain time.

INPUT B

(1) VC: integration capacitor voltage.

REFERENCE

VOLTAGE

COMPARATOR

Fig.9 Integrated blank skip function.

COMPARATOR

(1)

V

C

t

1

OUTPUT

MHB124

1998 Nov 12 16

Philips Semiconductors Product specification

I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications

handbook, full pagewidth

INPUT

V

upper threshold

lower threshold

OUTPUT

V

HIGH

V

LOW

C

t

sw(P-M)

t

sw(M-P)

t

sw(P-M)

TEA0679T

t

sw(M-P)

t

t

t

MHB125

VC; integration capacitor voltage: t

; switching time pause-to-music: t

sw(P-M)

Fig.10 Blank skip timing diagram.

Soft head switching

In general the head switching procedure is recommended
to be performed in four steps:

1. Activate the mute function

2. Switch to the alternative head

3. Adjust the offset for the new head

4. Deactivate the mute function.
In applications without a mute function a soft head switch

via the I2C-bus can be realized using a capacitor
connected to pin 18. A proposal for this switching
mechanism is shown in Fig.11. To guarantee the internal
timing for the head switching operation an externally
connected device to pin 18 should not modify the output
current significantly.

An additional resistor is necessary if the head switching is
performed externally via the optional switching input
capability at pin 18. A proposal for this kind of switching is
shown in Fig.12.

In general soft head switching is only suitable if equal
offset values for head 1 and head 2 exist. A soft offset
value switching is not possible with the TEA0679T.

; switching time music-to-pause.

sw(M-P)

handbook, halfpage

Fig.11 Soft head switching via the I2C-bus.

handbook, halfpage

Fig.12 External soft head switching.

pin 18
HS (optional)

10 µF

MHB126

pin 18
HS (optional)

8 kΩ 10 µF

IN2IN1

MHB127

1998 Nov 12 17

Philips Semiconductors Product specification

I2C-bus controlled dual Dolby* B-type noise

TEA0679T

reduction circuit for playback applications

I2C-BUS PROTOCOL

2

C-bus format

I

S SLAVE ADDRESS A DATA A P

Table 2 Explanation of I

NAME DESCRIPTION

S START condition
SLAVE ADDRESS 101 100 00 (MAD = LOW)

A acknowledge; generated by the slave
DATA see Tables 3 to 10
P STOP condition

Table 3 Write byte 0; SELECT

FUNCTIONS

2

C-bus format to read (slave transmits data)

101 100 10 (MAD = HIGH)

BITS OF DATA BYTE SELECT

MSB LSB

SMOD1 SMOD0 HSW MUTE NROF OFCH OMOR EQT

Equalization time constant

70 µs −−−−−−−0
120 µs −−−−−−−1

Offset monitor

AMS output −−−−−−0−
offset monitor −−−−−−1−

Offset channel

channel A −−−−−0−−
channel B −−−−−1−−

NR on/off

on −−−−0−−−
off −−−−1−−−

Mute off/on

off −−−0−−−−
on −−−1−−−−

Head switch

IN2 −−0−−−−−
IN1 −−1−−−−−

Search mode

off 0 0 −−−−−−
blank skip 0 1 −−−−−−
AMS latch mode 1 0 −−−−−−
AMS scan mode 1 1 −−−−−−

1998 Nov 12 18

Philips Semiconductors Product specification

I2C-bus controlled dual Dolby* B-type noise

TEA0679T

reduction circuit for playback applications

Table 4 Write byte 1; EQADJA

BITS OF DATA BYTE EQADJA

ADDITIONAL GAIN

POSITIONS (dB)

0 0 0 000000

0.4 0 0 000001

0.8 0 0 000010

1.2 0 0 000011

1.6 0 0 000100

2.0 0 0 000101

2.4 0 0 000110

2.8 0 0 000111

3.2 0 0 001000

3.6 0 0 001001

4.0 0 0 001010

4.4 0 0 001011

4.8 0 0 001100

5.2 0 0 001101

5.6 0 0 001110

6.0 0 0 001111

6.4 0 0 010000

6.8 0 0 010001

7.2 0 0 010010

7.6 0 0 010011

8.0 0 0 010100

8.4 0 0 010101

8.8 0 0 010110

9.2 0 0 010111

9.6 0 0 011000

10.0 0 0 0 1 1 0 0 1

10.4 0 0 0 1 1 0 1 0

10.8 0 0 0 1 1 0 1 1

11.2 0 0 011100

11.6 0 0 011101

12.0 0 0 0 1 1 1 1 0

12.4 0 0 0 1 1 1 1 1

12.8 0 0 1 0 0 0 0 0

13.2 0 0 1 0 0 0 0 1

13.6 0 0 1 0 0 0 1 0

14.0 0 0 1 0 0 0 1 1

14.4 0 0 1 0 0 1 0 0

MSB LSB

NOT USED NOT USED EQA5 EQA4 EQA3 EQA2 EQA1 EQA0

1998 Nov 12 19

Philips Semiconductors Product specification

I2C-bus controlled dual Dolby* B-type noise

TEA0679T

reduction circuit for playback applications

BITS OF DATA BYTE EQADJA

ADDITIONAL GAIN

POSITIONS (dB)

14.8 0 0 1 0 0 1 0 1

15.2 0 0 1 0 0 1 1 0

15.6 0 0 1 0 0 1 1 1

16.0 0 0 1 0 1 0 0 0

16.4 0 0 1 0 1 0 0 1

16.8 0 0 1 0 1 0 1 0

17.2 0 0 1 0 1 0 1 1

17.6 0 0 1 0 1 1 0 0

18.0 0 0 1 0 1 1 0 1

18.4 0 0 1 0 1 1 1 0

18.8 0 0 1 0 1 1 1 1

19.2 0 0 1 1 0 0 0 0

19.6 0 0 1 1 0 0 0 1

20.0 0 0 1 1 0 0 1 0

20.4 0 0 1 1 0 0 1 1

20.8 0 0 1 1 0 1 0 0

21.2 0 0 1 1 0 1 0 1

21.6 0 0 1 1 0 1 1 0

22.0 0 0 1 1 0 1 1 1

22.4 0 0 1 1 1 0 0 0

22.8 0 0 1 1 1 0 0 1

23.2 0 0 1 1 1 0 1 0

23.6 0 0 1 1 1 0 1 1

24.0 0 0 1 1 1 1 0 0

24.4 0 0 1 1 1 1 0 1

24.8 0 0 1 1 1 1 1 0

25.2 0 0 1 1 1 1 1 1

MSB LSB

NOT USED NOT USED EQA5 EQA4 EQA3 EQA2 EQA1 EQA0

1998 Nov 12 20

Philips Semiconductors Product specification

I2C-bus controlled dual Dolby* B-type noise

TEA0679T

reduction circuit for playback applications

Table 5 Write byte 2; EQADJB

BITS OF DATA BYTE EQADJB

ADDITIONAL GAIN

POSITIONS (dB)

0 0 0 000000

0.4 0 0 000001

0.8 0 0 000010

1.2 0 0 000011

1.6 0 0 000100

2.0 0 0 000101

2.4 0 0 000110

2.8 0 0 000111

3.2 0 0 001000

3.6 0 0 001001

4.0 0 0 001010

4.4 0 0 001011

4.8 0 0 001100

5.2 0 0 001101

5.6 0 0 001110

6.0 0 0 001111

6.4 0 0 010000

6.8 0 0 010001

7.2 0 0 010010

7.6 0 0 010011

8.0 0 0 010100

8.4 0 0 010101

8.8 0 0 010110

9.2 0 0 010111

9.6 0 0 011000

10.0 0 0 0 1 1 0 0 1

10.4 0 0 0 1 1 0 1 0

10.8 0 0 0 1 1 0 1 1

11.2 0 0 011100

11.6 0 0 011101

12.0 0 0 0 1 1 1 1 0

12.4 0 0 0 1 1 1 1 1

12.8 0 0 1 0 0 0 0 0

13.2 0 0 1 0 0 0 0 1

13.6 0 0 1 0 0 0 1 0

14.0 0 0 1 0 0 0 1 1

14.4 0 0 1 0 0 1 0 0

MSB LSB

NOT USED NOT USED EQB5 EQB4 EQB3 EQB2 EQB1 EQB0

1998 Nov 12 21

Philips Semiconductors Product specification

I2C-bus controlled dual Dolby* B-type noise

TEA0679T

reduction circuit for playback applications

BITS OF DATA BYTE EQADJB

ADDITIONAL GAIN

POSITIONS (dB)

14.8 0 0 1 0 0 1 0 1

15.2 0 0 1 0 0 1 1 0

15.6 0 0 1 0 0 1 1 1

16.0 0 0 1 0 1 0 0 0

16.4 0 0 1 0 1 0 0 1

16.8 0 0 1 0 1 0 1 0

17.2 0 0 1 0 1 0 1 1

17.6 0 0 1 0 1 1 0 0

18.0 0 0 1 0 1 1 0 1

18.4 0 0 1 0 1 1 1 0

18.8 0 0 1 0 1 1 1 1

19.2 0 0 1 1 0 0 0 0

19.6 0 0 1 1 0 0 0 1

20.0 0 0 1 1 0 0 1 0

20.4 0 0 1 1 0 0 1 1

20.8 0 0 1 1 0 1 0 0

21.2 0 0 1 1 0 1 0 1

21.6 0 0 1 1 0 1 1 0

22.0 0 0 1 1 0 1 1 1

22.4 0 0 1 1 1 0 0 0

22.8 0 0 1 1 1 0 0 1

23.2 0 0 1 1 1 0 1 0

23.6 0 0 1 1 1 0 1 1

24.0 0 0 1 1 1 1 0 0

24.4 0 0 1 1 1 1 0 1

24.8 0 0 1 1 1 1 1 0

25.2 0 0 1 1 1 1 1 1

MSB LSB

NOT USED NOT USED EQB5 EQB4 EQB3 EQB2 EQB1 EQB0

Table 6 Write byte 3; OFFCHA

BITS OF DATA BYTE OFFCHA

OFFSET CHANNEL A

POSITIONS

Maximum positive 0 0 0 0 0 0 0 0

Maximum negative 1 1 1 1 1 1 1 1

1998 Nov 12 22

MSB LSB

OFA7 OFA6 OFA5 OFA4 OFA3 OFA2 OFA1 OFA0

... ... ... ... ... ... ... ...

Philips Semiconductors Product specification

I2C-bus controlled dual Dolby* B-type noise

TEA0679T

reduction circuit for playback applications

Table 7 Write byte 4; OFFCHB

BITS OF DATA BYTE OFFCHB

OFFSET CHANNEL B

POSITIONS

Maximum positive 00000000

Maximum negative 11111111

Table 8 Optionally pin controlled switch functions

FUNCTIONS

Equalization time constant

70 µs −−−LOW open-circuit 0
120 µs −−−HIGH open-circuit 1
70 µs −−−LOW LOW −

Head switch

IN2 LOW open-circuit 0 −−−
IN1 HIGH open-circuit 1 −−−
IN2 LOW LOW −−−−

MSB LSB

OFB7 OFB6 OFB5 OFB4 OFB3 OFB2 OFB1 OFB0

... ... ... ... ... ... ... ...

HS (PIN 18) EQS (PIN 5)

PIN STATE

OUTPUT INPUT OUTPUT INPUT

DATA BIT

HSW

PIN STATE

DATA BIT

EQT

Table 9 MAD switch

MODULE ADDRESS MAD (PIN 1)

Table 10 BEN switch

2

I

C-BUS OPERATION MODE BEN (PIN 32)

Active; 5 V thresholds open-circuit
Active; 5 V thresholds HIGH (5 V to VCC)

Active; V

101 100 10 open-circuit
101 100 10 HIGH
101 100 00 LOW

related thresholds HIGH (3 to 5 V)

BEN

Inactive LOW

1998 Nov 12 23

Philips Semiconductors Product specification

I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications

I2C-bus transmission types

The I2C-bus format depends on the kind of data which
should be transmitted. To speed up the offset adjustment
procedure three types of transmissions from master to
slave are possible. The transmission type is controlled by
bits OFCH and OMOR in write byte 0.

If the OMOR bit is set to logic 0 the standard transmission
type is used. The corresponding byte sequence is shown
in Fig.13. This kind of transmission should by used for
changes in the IC settings during normal operation.

handbook, full pagewidth

ADDRESS BYTE 0 BYTE 1

TEA0679T

If the OMOR bit is set to logic 1 and the OFCH bit is set to
logic 0 the transmission type for an offset adjust in
channel A is selected. The byte sequence is shown in
Fig.14. During this kind of transmission the pin AMS is
used as the offset monitor output for channel A.

If the OMOR bit is set to logic 1 and the OFCH bit is set to
logic 1 the transmission type for an offset adjust in
channel B is selected. The byte sequence is shown in
Fig.15. During this kind of transmission the pin AMS is
used as the offset monitor output for channel B.

AS CHIP ADDRESS A AX0R/W

A

APA

handbook, full pagewidth

handbook, full pagewidth

BYTE 2 BYTE 3 BYTE 4

Fig.13 Standard transmission.

ADDRESS BYTE 0 BYTE 3

A

BYTE 3 BYTE 3

Fig.14 Offset adjust channel A transmission.

ADDRESS BYTE 0 BYTE 4

MHB128

AS CHIP ADDRESS A A01R/W

APA

MHB129

AS CHIP ADDRESS A A11R/W

BYTE 4 BYTE 4

Fig.15 Offset adjust channel B transmission.

1998 Nov 12 24

A

APA

MHB130

Philips Semiconductors Product specification

I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications

INTERNAL PIN CONFIGURATIONS

1.6 V

+

1

MHB131

handbook, halfpage

handbook, halfpage

80 kΩ

160 Ω

TEA0679T

2

+

80 kΩ

160 Ω

Fig.16 Pin 1: programmable address bit.

handbook, halfpage

MHB132

Fig.17 Pin 2: blank skip reference capacitance.

+

3

8 V

1 kΩ

MHB133

handbook, halfpage

+

4

MHB134

Fig.18 Pin 3: delay time constant.

1998 Nov 12 25

Fig.19 Pin 4: blank skip integration capacitance.

Philips Semiconductors Product specification

I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications

handbook, halfpage

3 V

+

5

MHB135

handbook, halfpage

TEA0679T

+

85 Ω

6

5 V

85 Ω

47 Ω

MHB136

handbook, halfpage

Fig.20 Pin 5: EQ switch input.

7

V

± 0.23 V

+

3.6 kΩ

ref

MHB137

Fig.21 Pins 6 and 27: output channel.

handbook, halfpage

+

1.2 kΩ 3.4 kΩ

8

5 V

3.6 kΩ
40 kΩ

5 V

MHB138

Fig.22 Pin 7: integrating filter channel A.

1998 Nov 12 26

Fig.23 Pin 8: control voltage channel A.

Philips Semiconductors Product specification

I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications

handbook, halfpage

9

+

5 V

+

670 Ω

9 kΩ

9 kΩ

5 V

MHB139

handbook, halfpage

TEA0679T

10

+

5 V

MHB140

Fig.24 Pins 9 and 24: high-pass filter.

handbook, halfpage

+

160 Ω 5.8 kΩ

MHB141

Fig.25 Pins 10 and 23: side chain.

11

5 V

20 kΩ

20 kΩ

handbook, halfpage

+

12

5 V

10 kΩ

2.7 pF

MHB142

Fig.26 Pins 11 and 22: equalizing output.

1998 Nov 12 27

Fig.27 Pins 12 and 21: equalizing input.

Philips Semiconductors Product specification

I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications

handbook, halfpage

handbook, halfpage

13

10 V

MHB143

TEA0679T

14

5 V

240 Ω

100 kΩ

5 V

6.25
pF

+

MHB144

handbook, halfpage

Fig.28 Pin 13: supply voltage.

+

2.55 kΩ

5 V

15

2.55 kΩ

MHB145

Fig.29 Pins 14, 16, 17 and 19: input channel.

handbook, halfpage

+

18

MHB146

Fig.30 Pin 15: reference voltage.

1998 Nov 12 28

Fig.31 Pin 18: head switch input.

Philips Semiconductors Product specification

I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications

handbook, halfpage

+

1.2 kΩ 3.4 kΩ

+

25

5 V

3.6 kΩ

handbook, halfpage

+

3.6 kΩ

TEA0679T

26

V

± 0.23 V

ref

Fig.32 Pin 25: control voltage channel B.

handbook, halfpage

MHB147

MHB148

Fig.33 Pin 26: integrating filter channel B.

+

3 V

28

handbook, halfpage

+

30

1.9 kΩ

MHB149

Fig.34 Pin 28: AMS output.

1998 Nov 12 29

MHB150

Fig.35 Pin 30: serial clock input.

Philips Semiconductors Product specification

I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications

handbook, halfpage

+

31

handbook, halfpage

1.9 kΩ

MHB151

TEA0679T

+

32

MHB152

Fig.36 Pin 31: serial data input/output.

Fig.37 Pin 32: bus enable.

1998 Nov 12 30

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1998 Nov 12 31

handbook, full pagewidth

TEST AND APPLICATION INFORMATION

Philips Semiconductors Product specification

reduction circuit for playback applications

I

2

C-bus controlled dual Dolby* B-type noise

BEN

32

1
MAD

SDA
31

I2C-BUS

2
BSC

220 nF

output B

SCL

3
TD

R

t

(ref)

4
BTC

47 nF

EQS
(opt)

10 µF

282930

EQS

OUTBDGND AMS
27

65
OUTA

MUTE

270 kΩ

INTB

7
INTA

270 kΩ

330 nF

100 nF330 nF

180 kΩ

CONTRB
2526

DOLBY B

LATCH

AND

RISE TIME

DELAY

TIME

DOLBY B

8
CONTRA

180 kΩ

100 nF

HPB
24

AMS

PROCESSOR

LEVEL

DETECTOR

9

4.7 nF15 nF

SCB
23

10
SCAHPA

4.7 nF15 nF

BLANK

SKIP

24 kΩ

24 kΩ

20 kΩ

EQB
22

LOGIC

11
EQA

20 kΩ

10 kΩ

EQ

AMP

EQ

AMP

10 µF

10 kΩ

EQFB
21

12
EQFA

100

nF

AGND
20

POWER
SUPPLY

13

VCC = 10 V

10 kΩ

1000

µF

PRE
AMP

PRE
AMP

INB1

INA1

HS

(opt)

HS

19

18

TEA0679T

15

14

V

INB2
17

16
INA2

ref

100

µF

output A

10 µF

10 µF

Fig.38 Test circuit for power supply ripple rejection.

0.25 V (RMS)
1 kHz

TEA0679T

MHB153

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1998 Nov 12 32

ndbook, full pagewidth

Philips Semiconductors Product specification

reduction circuit for playback applications

I

2

C-bus controlled dual Dolby* B-type noise

BEN

32

1
MAD

SDA

31

2
BSC

220 nF

SCL

I2C-BUS

3

TD

output B

R

t

(ref)

4
BTC

47 nF

EQS

(opt)

10 µF

282930

EQS

OUTBDGND AMS
27

65
OUTA

MUTE

270 kΩ

INTB

7
INTA

270 kΩ

330 nF

100 nF330 nF

180 kΩ

CONTRB
2526

DOLBY B

LATCH

AND

RISE TIME

DELAY

TIME

DOLBY B

8
CONTRA

180 kΩ

100 nF

HPB
24

AMS

PROCESSOR

LEVEL

DETECTOR

9

4.7 nF15 nF

SCB
23

10
SCAHPA

4.7 nF15 nF

BLANK

SKIP

24 kΩ

24 kΩ

20 kΩ

EQB
22

LOGIC

11
EQA

20 kΩ

10 kΩ

EQ

AMP

EQ

AMP

10 µF

10 kΩ

EQFB
21

12
EQFA

100

HS

(opt)

AGND
20

PRE
AMP

INB1

HS

19

18

INB2
17

TEA0679T

POWER
SUPPLY

PRE
AMP

15

INA1

200 Ω

10 µF

14

V

13

V

CC

10 V

nF

16
INA2

ref

100

µF

output A

10 µF

10 µF

Fig.39 Test circuit for channel separation.

TEA0679T

MHB154

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1998 Nov 12 33

ndbook, full pagewidth

Philips Semiconductors Product specification

reduction circuit for playback applications

I

2

C-bus controlled dual Dolby* B-type noise

BEN

32

1
MAD

SDA
31

2
BSC

220 nF

SCL

I2C-BUS

3

TD

output B

R

t

(ref)

output A

4
BTC

47 nF

EQS
(opt)

10 µF

282930

EQS

10 µF

OUTBDGND AMS
27

65
OUTA

MUTE

270 kΩ

INTB

7
INTA

270 kΩ

330 nF

100 nF330 nF

180 kΩ

CONTRB
2526

DOLBY B

LATCH

AND

RISE TIME

DELAY

TIME

DOLBY B

8
CONTRA

180 kΩ

100 nF

HPB
24

AMS

PROCESSOR

LEVEL

DETECTOR

9

4.7 nF15 nF

SCB
23

10
SCAHPA

4.7 nF15 nF

BLANK

SKIP

24 kΩ

24 kΩ

20 kΩ

EQB
22

LOGIC

11
EQA

20 kΩ

10 kΩ

10 µF

EQ

AMP

EQ

AMP

10 µF

10 kΩ

EQFB
21

12
EQFA

100

HS

(opt)

AGND
20

PRE
AMP

INB1

19

HS
18

INB2
17

TEA0679T

POWER

SUPPLY

PRE
AMP

15

13

V

CC

nF

10 V

14

INA1

16

V

INA2

ref

100

µF

voltage

input

TEA0679T

Fig.40 Test circuit for AMS threshold level.

MHB155

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1998 Nov 12 34

BEN
32

SDA
31

output B

SCL

10 µF

282930

100 nF330 nF

270 kΩ

OUTBDGND AMS

INTB

27

180 kΩ

CONTRB
2526

HPB
24

TP

15 nF

SCB
23

4.7 nF

book, full pagewidth

10 µF

24 kΩ

20 kΩ

EQB
22

10 kΩ

EQFB
21

AGND
20

V

CC

25 kΩ

25 kΩ

25 kΩ25 kΩ

10 µF

INB1

V

i

HS

(opt)

HS

19

18

INB2
17

Philips Semiconductors Product specification

reduction circuit for playback applications

I

2

C-bus controlled dual Dolby* B-type noise

DOLBY B

270 kΩ

330 nF

LATCH

AND

RISE TIME

DELAY

TIME

DOLBY B

8
CONTRA

180 kΩ

100 nF

1
MAD

I2C-BUS

2
BSC

220 nF

3
TD

R

t

(ref)

output A

4
BTC

47 nF

EQS
(opt)

EQS

10 µF

65
OUTA

MUTE

7
INTA

Channel A: Decode mode: pre-amplifier 30 dB and EQ amplifier 10 dB linear.
Channel B: Encode mode.

AMS

PROCESSOR

LEVEL

DETECTOR

9

TP

EQ

AMP

PRE
AMP

TEA0679T

13

V

10 V

CC

µF

10

POWER

SUPPLY

PRE
AMP

V

i

INA1

470
pF

14

200

15
V

Ω

16
INA2

ref

100

µF

BLANK

SKIP

10
SCAHPA

24 kΩ

4.7 nF15 nF

LOGIC

11
EQA

20 kΩ

10 kΩ

10 µF

EQ

AMP

12
EQFA

100

nF

TEA0679T

MHB156

Fig.41 Test circuit for frequency response (channel B).

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1998 Nov 12 35

ndbook, full pagewidth

Philips Semiconductors Product specification

reduction circuit for playback applications

I

2

C-bus controlled dual Dolby* B-type noise

BEN
32

1
MAD

SDA
31

2
BSC

220 nF

SCL

I2C-BUS

3
TD

output B

R

t

(ref)

4
BTC

47 nF

EQS
(opt)

10 µF

282930

EQS

OUTBDGND AMS
27

65
OUTA

MUTE

270 kΩ

INTB

7
INTA

270 kΩ

330 nF

100 nF330 nF

180 kΩ

CONTRB
2526

DOLBY B

LATCH

AND

RISE TIME

DELAY

TIME

DOLBY B

8
CONTRA

180 kΩ

100 nF

HPB
24

AMS

PROCESSOR

LEVEL

DETECTOR

9

4.7 nF15 nF

SCB
23

10
SCAHPA

4.7 nF15 nF

BLANK

SKIP

24 kΩ

24 kΩ

20 kΩ

EQB
22

LOGIC

11
EQA

20 kΩ

10 kΩ

EQ

AMP

EQ

AMP

10 µF

10 kΩ

EQFB
21

12
EQFA

100

nF

AGND
20

13
V

CC

PRE
AMP

POWER

SUPPLY

PRE
AMP

10 V

470
pF

INB1

INA1

470
pF

200

Ω

HS

(opt)

HS

19

18

TEA0679T

14

200

Ω

200

470

Ω

pF

INB2
17

15

16

V

INA2

ref

100

µF

200

470

Ω

pF

output A

10 µF

Fig.42 EMC test circuit.

10 µF

10 Ω

40 Ω

MHB157

TEA0679T

Philips Semiconductors Product specification

I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications

PACKAGE OUTLINE

SO32: plastic small outline package; 32 leads; body width 7.5 mm

D

y

Z

32

17

TEA0679T

SOT287-1

E

c

H

E

A

X

v M

A

pin 1 index

1

e

0 5 10 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

UNIT

mm

inches

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

A

max.

2.65

0.10

A

0.3

0.1

0.012

0.004

1

A2A3b

2.45

0.25

2.25

0.096

0.01

0.086

0.49

0.36

0.02

0.01

p

0.27

0.18

0.011

0.007

(1)E(1)

cD

20.7

20.3

0.81

0.80

7.6

7.4

0.30

0.29

16

b

p

scale

eHELLpQZywv θ

1.27

0.050

10.65

10.00

0.419

0.394

w M

1.4

0.055

A

2

1.1

0.4

0.043

0.016

Q

A

1

detail X

1.2

0.25

1.0

0.047

0.039

(A )

L

p

L

0.25 0.1

0.004

0.010.01

A

3

θ

(1)

0.95

0.55

0.037

0.022

o

8

o

0

OUTLINE

VERSION

SOT287-1

IEC JEDEC EIAJ

REFERENCES

1998 Nov 12 36

EUROPEAN

PROJECTION

ISSUE DATE

95-01-25
97-05-22

Philips Semiconductors Product specification

I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(order code 9398 652 90011).

Reflow soldering

Reflow soldering techniques are suitable for all SO
packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

TEA0679T

Wave soldering

Wave soldering techniques can be used for all SO
packages if the following conditions are observed:

• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

• The longitudinal axis of the package footprint must be
parallel to the solder flow.

• The package footprint must incorporate solder thieves at
the downstream end.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

1998 Nov 12 37

Philips Semiconductors Product specification

I2C-bus controlled dual Dolby* B-type noise

TEA0679T

reduction circuit for playback applications

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale

PURCHASE OF PHILIPS I

Purchase of Philips I
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

2

C COMPONENTS

2

C components conveys a license under the Philips’ I2C patent to use the

1998 Nov 12 38

Philips Semiconductors Product specification

I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications

NOTES

TEA0679T

1998 Nov 12 39

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. [phone],

Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: seeSouth America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15thfloor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. [phone], Fax. [phone]
Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,

Tel. [phone], Fax. [phone]
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. [phone], Fax. [phone]
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,

Tel. [phone], Fax. [phone]

Hungary: seeAustria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. [phone], Fax. [phone]

Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. [phone] ext. 2501, Fax. [phone]

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. [phone], Fax. [phone]

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. [phone], Fax. [phone]

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. [phone], Fax. [phone]

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. [phone], Fax. [phone]

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. [phone], Fax. [phone]

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. [phone]

Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. [phone], Fax. [phone]

South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone] Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1998 SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 545102/750/02/pp40 Date of release: 1998 Nov 12 Document order number: 9397 750 04298