The TDA8712 and TDF8712 are 8-bit digital-to-analog
converters (DACs) for video and other applications. They
convert the digital input signal into an analog voltage
output at a maximum conversion rate of 50 MHz. No
external reference voltage is required and all digital inputs
are TTL compatible.
REF1voltage reference (decoupling)
AGND2analog ground
D23data input; bit 2
D34data input; bit 3
CLK5clock input
DGND6digital ground
D77data input; bit 7 (MSB)
D68data input; bit 6
D59data input; bit 5
D410data input; bit 4
D111data input; bit 1
D012data input; bit 0 (LSB)
V
V
V
V
CCD
OUT
OUT
CCA
13digital supply voltage (+5 V)
14analog output voltage
15complimentary analog output voltage
16analog supply voltage (+5 V)
In accordance with the Absolute Maximum Rating System (IEC134).
SYMBOLPARAMETERMIN.MAX.UNIT
V
V
∆V
∆V
V
I
tot
T
T
T
CCA
CCD
CC
GND
I
stg
amb
j
analog supply voltage−0.3+7.0V
digital supply voltage−0.3+7.0V
supply voltage differences between V
ground voltage differences between V
input voltage (pins 3 to 5 and 7 to 12)−0.3V
total output current (I
OUT
+ I
; pins 14 and 15)−5+26mA
OUT
CCA
AGND
and V
and V
CCD
−0.5+0.5V
−0.1+0.1V
DGND
CCD
V
storage temperature−55+150°C
operating ambient temperature
TDA87120+70°C
TDF8712−40+85°C
junction temperature−+150°C
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOLPARAMETERVALUEUNIT
R
th j-a
thermal resistance from junction to ambient in free air
data set-up time−0.3−−ns
data hold time2.0−−ns
propagation delay time−−1.0ns
settling time 110% to 90% full-scale
= 50 MHz; notes 4 and 5; see Figs 3, 4 and 5)
clk
−1.11.5ns
change to ±1 LSB
t
S2
settling time 210% to 90% full-scale
−6.58.0ns
change to ±1 LSB
t
d
Output transients (glitches; f
E
g
input to 50% output delay time−3.05.0ns
= 50 MHz; note 6; see Fig.6)
clk
glitch energy from codetransition 127 to 128−−30LSB⋅ns
Notes
1. D0 to D7 are connected to V
2. The analog output voltages (V
between V
and each of these outputs is typically 75 Ω.
CCA
and CLK is connected to DGND.
CCD
OUT
and V
) are negative with respect to V
OUT
(see Table 1). The output resistance
CCA
3. The −3 dB analog output bandwidth is determined by real time analysis of the output transient at a maximum input
code transition (code 0 to 255).
4. The worst case characteristics are obtained at the transition from input code 0 to 255 and if an external load
impedance greater than 75 Ω is connected between V
measured with an active probe between V
and AGND. No further load impedance between V
OUT
OUT
or V
OUT
and V
. The specified values have been
CCA
and AGND has
OUT
been applied. All input data is latched at the rising edge of the clock. The output voltage remains stable (independent
of input data variations) during the HIGH level of the clock (CLK = HIGH). During a LOW-to-HIGH transition of the
clock (CLK = LOW), the DAC operates in the transparent mode (input data will be directly transferred to their
corresponding analog output voltages; see Fig.5.
5. The data set-up time (t
) is the minimum period preceding the rising edge of the clock that the input data must
SU;DAT
be stable in order to be correctly registered. A negative set-up time indicates that the data may be initiated after the
rising edge of the clock and still be recognized. The data hold time (t
) is the minimum period following the rising
HD;DAT
edge of the clock that the input data must be stable in order to be correctly registered. A negative hold time indicates
that the data may be released prior to the rising edge of the clock and still be recognized.
6. The definition of glitch energy and the measurement set-up are shown in Fig.6. The glitch energy is measured at the
input transition between code 127 and 128 and on the falling edge of the clock.
The shaded areas indicate when the input data may change and be correctly registered. Data input update must be completed within 0.3 ns after the first
rising edge of the clock (t
is negative; −0.3 ns). Data must be held at least 2 ns after the rising edge (t
input data
(example of a
full-scale input
transition)
CLK
code 0
1.3 V
1 LSB
V
CCA
(code 0)
t
d
V
OUT
t
S1
t
PD
t
S2
Fig.4 Switching characteristics.
1.3 V
code 255
1 LSB
MBC913
10 %
50 %
90 %
V
1.6 V
CCA
(code 255)
andbook, full pagewidth
During the transparent mode (CLK = LOW), any change of input data will be seen at the output. During the latched mode (CLK = HIGH), the analog output
remains stable regardless of any change at the input. A change of input data during the latched mode will be seen on the falling edge of the clock
(beginning of the transparent mode).
B
The maximum permissible temperature of the solder is
260 °C; this temperature must not be in contact with the
joint for more than 5 s. The total contact time of successive
solder waves must not exceed 5 s.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified storage maximum. If the printed-circuit board has
been pre-heated, forced cooling may be necessary
immediately after soldering to keep the temperature within
the permissible limit.
EPAIRING SOLDERED JOINTS
R
Apply a low voltage soldering iron below the seating plane
(or not more than 2 mm above it). If its temperature is
below 300 °C, it must not be in contact for more than 10 s;
if between 300 and 400 °C, for not more than 5 s.
Plastic small-outline packages
YWAVE
B
During placement and before soldering, the component
must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.
A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.
Y SOLDER PASTE REFLOW
B
Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be
applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.
EPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
R
IRON OR PULSE
-HEATED SOLDER TOOL)
Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.)
For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.
Objective specificationThis data sheet contains target or goal specifications for product development.
Preliminary specificationThis data sheet contains preliminary data; supplementary data may be published later.
Product specificationThis data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. (800)234-7381, Fax. (708)296-8556
DISCRETE SEMICONDUCTORS: 2001 West Blue Heron Blvd.,
P.O. Box 10330, RIVIERA BEACH, FLORIDA 33404,
Tel. (800)447-3762 and (407)881-3200, Fax. (407)881-3300
Uruguay: Coronel Mora 433, MONTEVIDEO,
Tel. (02)70-4044, Fax. (02)92 0601
For all other countries apply to: Philips Semiconductors,
International Marketing and Sales, Building BAF-1,
P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. +31-40-724825
All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.
Printed in The Netherlands
533061/1500/03/pp24Date of release: June 1994
Document order number:9397 734 70011
Philips Semiconductors
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