Datasheet TDA6503A, TDA6502A, TDA6502 Datasheet (Philips)

Page 1
INTEGRATED CIRCUITS
DATA SH EET
TDA6502; TDA6502A; TDA6503; TDA6503A
Preliminary specification Supersedes data of 2000 Jan 24 File under Integrated Circuits, IC02
2000 Mar 16
Page 2
Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
CONTENTS
1 FEATURES 2 APPLICATIONS 3 GENERAL DESCRIPTION
3.1 I2C-bus format
3.2 3-wire bus format 4 QUICK REFERENCE DATA 5 ORDERING INFORMATION 6 BLOCK DIAGRAM 7 PINNING 8 FUNCTIONAL DESCRIPTION
8.1 Control mode selection
8.2 I2C-bus data format
8.2.1 I2C-bus address selection
8.2.2 Write mode
8.2.3 Read mode
8.2.4 Power-on reset
8.3 3-wire bus data format
8.3.1 Power-on reset 9 LIMITING VALUES 10 THERMAL CHARACTERISTICS 11 CHARACTERISTICS 12 TIMING CHARACTERISTICS
13 TEST AND APPLICATION INFORMATION
13.1 Test circuits
13.2 Measurement circuit
13.3 Tuning amplifier
13.4 Crystal oscillator
13.5 ExamplesofI2C-busdataformatsequencesfor
13.5.1 Write sequences to register C2
13.5.2 Read sequences from register C3
13.6 Examplesof 3-wire busdata format sequences
13.6.1 18-bit sequence
13.6.2 19-bit sequence
13.6.3 27-bit sequence 14 INTERNAL PIN CONFIGURATION 15 PACKAGE OUTLINE 16 SOLDERING
16.1 Introduction to soldering surface mount
16.2 Reflow soldering
16.3 Wave soldering
16.4 Manual soldering 17 DEFINITIONS 18 LIFE SUPPORT APPLICATIONS 19 PURCHASE OF PHILIPS I2C COMPONENTS
TDA6502; TDA6502A;
TDA6503; TDA6503A
TDA6502 and TDA6503
for TDA6502 and TDA6503
packages
2000 Mar 16 2
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Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
1 FEATURES
Single-chip 5 V mixer/oscillator and synthesizer for cable TV and VCR tuners
Pin-to-pin compatible with TDA6402, TDA6402A, TDA6403 and TDA6403A
Universal bus protocol (I2C-bus or 3-wire bus) – Bus protocol for 18 or 19-bit transmission (3-wire
bus)
– Extraprotocolfor27-bittransmission(testmodesand
features for 3-wire bus)
– Address + 4 data bytes transmission (I2C-bus ‘write’
mode) – Address + 1 status byte (I2C-bus ‘read’ mode) – 4 independent I2C-bus addresses.
1 PMOS buffer for UHF band selection (25 mA)
3 PMOS buffers for general purpose, e.g. 2 VHF
sub-bands, FM sound trap (25 mA)
33 V tuning voltage output
In-lock detector
5-step analog-to-digital converter (3 bits in I2C-bus
mode)
15-bit programmable divider
Programmable reference divider ratio (64, 80 or 128)
Programmable charge pump current (60 or 280 µA)
Varicap drive disable
Balanced mixer with a common emitter input for VHF
(single input)
Balanced mixer with a common base input for UHF (balanced input)
2-pin common emitter oscillator for VHF
4-pin common emitter oscillator for UHF
IF preamplifier with asymmetrical 75 output impedance able to drive loads from 75 upwards
Low power
Low radiation
Small size
TheTDA6502AandTDA6503Adiffer from the TDA6502
and TDA6503 by the UHF port protocol in the I2C-bus mode (see Tables 3 and 4).
TDA6502; TDA6502A;
TDA6503; TDA6503A
2 APPLICATIONS
Cable tuners for TV and VCR (switched concept for VHF).
3 GENERAL DESCRIPTION
The TDA6502, TDA6502A, TDA6503 and TDA6503A are programmable2-band mixers/oscillators andsynthesizers intended for VHF/UHF TV and VCR tuners (see Fig.1).
Partitioning of the bands is the responsibility of the customer providing VHF is below 500 MHz and UHF is below 900 MHz.
The devices include two double balanced mixers and two oscillators for the VHF and UHF band respectively, an IF amplifier and a PLL synthesizer. The VHF band can be split-up into two sub-bands using a proper oscillator application and a switchable inductor.
Two pins are available between the mixer output and the IF amplifier input to enable IF filtering for improved signal handling.
The port register provides four PMOS ports. Band selection is provided by port register UHF. When port register UHF is ‘on’, the UHF mixer-oscillator is active and the VHF band is switched off. When port register UHF is ‘off’, the VHF mixer-oscillator is active and the UHF band is off. Port registers VHFL and VHFH are used to select the VHF sub-bands. Port register FMST is a general purposeport, that can be usedtoswitch an FM sound trap. Whenthe ports areused,the sum ofthedrain currents has to be limited to 30 mA.
Thesynthesizerconsists of a 15-bitprogrammabledivider, a crystal oscillator and its programmable reference divider and a phase comparator (phase/frequency detector) combined with a charge pump which drives the tuning amplifier, including the 33 V output at pin VT. Depending on the reference divider ratio (64, 80 or 128), the phase comparator operates at 62.5, 50 or 31.25 kHz with a 4 MHz crystal.
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Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
Depending on thevoltage applied to pin SW (see Table 2) the device is operating in the I2C-bus mode or 3-wire bus mode.
In the 3-wire bus mode, pin LOCK/ADCis the ‘lock’ output of the PLL and is at LOW level when the PLL is locked. Lockdetectorbit FL of the statusbyteisset to logic 1 when the loop is locked and is read on the SDA line during a READ operation in I2C-bus mode only.
In the I2C-bus mode only,pin LOCK/ADC is the ADC input for digital AFC control. The ADC code is read during a READ operation on the I2C-bus.
In the test mode, in both I2C-bus mode and 3-wire bus mode, pin LOCK/ADC is used as a test output for f
1
⁄2f
.
DIV
2
3.1 I
Five serial bytes (including the address byte) are required to address thedevice, select the VCO frequency, program the four ports, set the charge pump current and set the reference divider ratio. The device has four independent I2C-bus addresses which can be selected by applying a specific voltage to pin CE/AS.
C-bus format
REF
and
TDA6502; TDA6502A;
TDA6503; TDA6503A
Table 1 Data word length for 3-wire bus format
DATA WORD
18-bit 64 62.50 kHz 19-bit 128 31.25 kHz 27-bit programmable programmable
Note
1. The selection of the reference divider is given by an
automatic identification of the data word length. When the 27-bit format is used, the reference divider is controlled by bits RSA and RSB (see Table 8). More details are given in Section 8.3.
REFERENCE
DIVIDER
(1)
FREQUENCY
STEP
3.2 3-wire bus format
Data is transmitted to the device during a HIGH level on pin CE/AS (enable line). The device is accessible with 18-bit and 19-bit data formats (see Figs 4 and 5). The first four bits are used to program the PMOS ports and the remaining bits control the programmable divider. A 27-bit data format (seeFig.6) may alsobe used to set thecharge pump current, the reference divider ratio and the test modes.
It is not allowed to address the device with words whose length is different from 18, 19 or 27 bits.
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Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
TDA6502; TDA6502A;
TDA6503; TDA6503A
4 QUICK REFERENCE DATA
Measured over full voltage and temperature ranges.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V I
CC
CC
supply voltage operating 4.5 5 5.5 V supply current all PMOS ports are off;
71 mA
VCC=5V
f
XTAL
I
o(PMOS)
P
tot
T
stg
T
amb
f
RF
crystal oscillator frequency 4.0 MHz PMOS port output current note 1 −−30 mA total power dissipation note 2 −−520 mW IC storage temperature 40 +150 °C ambient temperature 20 +85 °C RF frequency VHF band 40 800 MHz
UHF band 200 900 MHz
G
V
voltage gain VHF band 20 dB
UHF band 32 dB
NF noise figure VHF band 7.5 dB
UHF band 7 dB
V
o
output voltage (causing 1% cross modulation in channel)
VHF band 110 dBµV UHF band 110 dBµV
Notes
1. One buffer ‘on’, Io= 25 mA; two buffers ‘on’, maximum sum of Io= 30 mA.
2. The power dissipation is calculated as follows: P
tot
V
CCICCIo
()V
P(sat)Io
0.5 33V×()
+×+×=
--------------------------------­22 k
2
where: V
= output saturation voltage on the buffer output
P(sat)
I
= source current for one buffer output.
o
5 ORDERING INFORMATION
TYPE
NUMBER
TDA6502;
NAME DESCRIPTION VERSION
SSOP28 plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1
PACKAGE
TDA6502A; TDA6503; TDA6503A
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Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
6 BLOCK DIAGRAM
handbook, full pagewidth
VHFIN
RFGND
UHFIN1
UHFIN2
3 (26)
BS
4 (25)
1 (28) 2 (27)
RF INPUT
VHF
TDA6502 TDA6502A (TDA6503)
(TDA6503A)
RF INPUT
UHF
IFFIL1 IFFIL2
5 (24)
6 (23)
BS
BSBS
VHF
MIXER
UHF
MIXER
V
CC
19 (10)
BS
TDA6502; TDA6502A;
TDA6503; TDA6503A
(5) 24
VHF
BS
OSCILLATOR
IF
PREAMPLIFIER
UHF
OSCILLATOR
(7) 22 (6) 23
(9) 20
(1) 28 (2) 27 (3) 26 (4) 25
VHFOSCOC
VHFOSCIB OSCGND
IFOUT
UHFOSCIB2 UHFOSCOC2 UHFOSCOC1 UHFOSCIB1
XTAL
CL
DA
SW
CE/AS
18 (11)
14 (15) 13 (16) 11 (18)
12 (17)
XTAL
OSCILLATOR
4 MHz
POWER-DOWN
DETECTOR
SCL SDA SW
I
CE/AS
REFERENCE
RSA RSB
PROGRAMMABLE
FREQUENCY
FL
2
C-bus / 3-WIRE BUS
TRANSCEIVER
3-BIT ADC
DIVIDER
64, 80, 128
15-BIT
DIVIDER
15-BIT
REGISTER
f
REF
COMPARATOR
f
DIV
DETECTOR
f
REF
FL
GATE
15 (14)
LOCK/ADC
PHASE
IN-LOCK
FL
1/2f
DIV
T0, T1, T2
CHARGE
PUMP
T0, T1, T2
CP T2 T1 T0 RSA RSB OS
UHF VHFH VHFL FMST
BS
9 (20)
PUHF
CP
CONTROL
REGISTER
REGISTER
PVHFH
PORT
8 (21)
OPAMP
OS
7 (22)
PVHFL
FMST
10 (19)
(13) 16 (12) 17
(8) 21
FCE527
CP
VT
GND
The pin numbers in parenthesis represent the TDA6503 and TDA6503A.
Fig.1 Block diagram.
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Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
7 PINNING
PIN
SYMBOL
UHFIN1 1 28 UHF RF input 1 UHFIN2 2 27 UHF RF input 2 VHFIN 3 26 VHF RF input RFGND 4 25 RF ground IFFIL1 5 24 IF filter output 1 IFFIL2 6 23 IF filter output 2 PVHFL 7 22 PMOS port output, general purpose (e.g. VHF low sub-band) PVHFH 8 21 PMOS port output, general purpose (e.g. VHF high sub-band) PUHF 9 20 PMOS port output, UHF band FMST 10 19 PMOS port output, general purpose (e.g. FM sound trap) SW 11 18 bus format selection input: I CE/AS 12 17 chip enable input in 3-wire bus mode or address selection input in
DA 13 16 serial data input/output CL 14 15 serial clock input LOCK/ADC 15 14 lock detector output in 3-wire bus mode or ADC input in I
CP 16 13 charge pump output VT 17 12 tuning voltage output XTAL 18 11 crystal oscillator input V
CC
IFOUT 20 9 IF output GND 21 8 digital ground VHFOSCIB 22 7 VHF oscillator input base OSCGND 23 6 oscillator ground VHFOSCOC 24 5 VHF oscillator output collector UHFOSCIB1 25 4 UHF oscillator input 1 (base) UHFOSCOC1 26 3 UHF oscillator output 1 (collector) UHFOSCOC2 27 2 UHF oscillator output 2 (collector) UHFOSCIB2 28 1 UHF oscillator input 2 (base)
TDA6502;
TDA6502A
19 10 supply voltage
TDA6503;
TDA6503A
2
I
C-bus mode
mode
TDA6502; TDA6502A;
TDA6503; TDA6503A
DESCRIPTION
2
C-bus mode or 3-wire bus mode
2
C-bus
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Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
handbook, halfpage
UHFIN1
UHFIN2
VHFIN
RFGND
IFFIL1 IFFIL2
PVHFL
PVHFH
PUHF FMST
SW
CE/AS
DA
CL
1 2 3 4 5 6 7
TDA6502
TDA6502A
8
9 10 11 12 13
FCE570
UHFOSCIB2
28
UHFOSCOC2
27
UHFOSCOC1
26
UHFOSCIB1
25
VHFOSCOC
24 23
OSCGND VHFOSCIB
22 21
GND IFOUT
20
V
19
CC
XTAL
18
VT
17
CP
16 1514
LOCK/ADC
handbook, halfpage
UHFOSCIB2 UHFOSCOC2 UHFOSCOC1
UHFOSCIB1
VHFOSCOC
VHFOSCIB
LOCK/ADC
OSCGND
GND
IFOUT
V
CC
XTAL
VT
CP
TDA6502; TDA6502A;
TDA6503; TDA6503A
1 2
3 4 5 6 7
TDA6503
TDA6503A
8 9
10 11 12 13
FCE571
28 27 26 25 24 23 22 21 20 19 18 17 16 1514
UHFIN1 UHFIN2 VHFIN RFGND IFFIL1 IFFIL2 PVHFL PVHFH PUHF FMST SW CE/AS DA CL
Fig.2 Pin configuration for TDA6502 and
TDA6502A.
Fig.3 Pin configuration for TDA6503 and
TDA6503A.
8 FUNCTIONAL DESCRIPTION
8.1 Control mode selection
The device is controlled via the I2C-bus or the 3-wire bus, depending on the voltage applied to pin SW (see Table 2). A LOW level on pin SW enables the I2C-bus: pins CE/AS, DA and CL are used as address selection (AS), serial data
(SDA) and serial clock (SCL) input respectively. A HIGH level on pin SW enables the 3-wire bus: pins CE/AS, DA and CL are used as chip enable (CE), data and clock
inputs respectively.
Table 2 Bus format selection
PIN
SYMBOL
TDA6502;
TDA6502A
TDA6503;
TDA6503A
I2C-BUS MODE 3-WIRE BUS MODE
SW 11 18 LOW-level voltage or ground HIGH-level voltage or open-circuit CE/AS 12 17 address selection input enable input DA 13 16 serial data input data input CL 14 15 serial clock input clock input LOCK/ADC 15 14 ADC input or test output lock detector output or test output
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Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
8.2 I2C-bus data format
2
8.2.1 I The module address contains programmable address
bits MA1 and MA0 (see Tables 3, 4 and 9) which offer the possibility of having several synthesizers (up to 4) in one system by applying a specific voltage on pin CE/AS. The relationship between bits MA1 and MA0 and theinput voltage applied to pin CE/AS is given in Table 6.
8.2.2 W The write mode is defined by the address byte ADB with
bit R/W = 0 (see Tables 3 and 4). Data bytes can be sent to the device after the address
transmission (first byte). Four data bytes are needed to fully program the device.
Table 3 I
Address byte ADB 11000MA1MA0R/ Divider byte 1 DB1 0 N14 N13 N12 N11 N10 N9 N8 Divider byte 2 DB2 N7 N6 N5 N4 N3 N2 N1 N0 Control byte CB 1 CP T2 T1 T0 RSA RSB OS Band-switch byte BB XXXXFMST PUHF PVHFH PVHFL
C-BUS ADDRESS SELECTION
RITE MODE
2
C-bus data format for write mode of TDA6502 and TDA6503
NAME BYTE
MSB LSB
The bus transceiver has an auto-increment facility which permits the programming of the device within one single transmission (address byte + 4 data bytes). The device can also be partially programmed providing that the first data byte following the address byte is divider byte DB1 or the control byte CB.
The first bit of byte DB1 indicates whether frequency data (first bit = 0) or control and band-switch data (first bit = 1) will follow. Until an I controller,additional data bytescanbe entered without the need to re-address the device.
The frequency register is loaded after the 8th clock pulse of byte DB2, the control register is loaded after the 8th clock pulse of the byte CB and the band-switch register is loaded after the 8th clock pulse of byte BB.
BITS
TDA6502; TDA6502A;
TDA6503; TDA6503A
2
C-bus STOP command is sent by the
W=0
2
Table 4 I
Address byte ADB 11000MA1MA0R/ Divider byte 1 DB1 0 N14 N13 N12 N11 N10 N9 N8 Divider byte 2 DB2 N7 N6 N5 N4 N3 N2 N1 N0 Control byte CB 1 CP T2 T1 T0 RSA RSB OS Band-switch byte BB XXXXPUHF FMST PVHFH PVHFL
2000 Mar 16 9
C-bus data format for write mode of TDA6502A and TDA6503A
BIT
NAME BYTE
MSB LSB
W=0
Page 10
Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
Table 5 Description of the bits used in Tables 3 and 4
BIT DESCRIPTION
MA1 and MA0 programmable address bits (see Table 6)
W logic 0 for write mode
R/
14
N14 to N0 programmable divider bits: N = N14 × 2 CP charge pump current control bit:
logic 0: charge pump current is 60 µA
logic 1: charge pump current is 280 µA (default) T2, T1 and T0 test bits (see Table 7) RSA and RSB reference divider ratio select bits (see Table 8) OS tuning amplifier control bit:
logic 0: tuning voltage is ‘on’ (during normal operating)
logic 1: tuning voltage is ‘off’; high-impedance output of pin VT (default) PVHFL, PVHFH, PUHF and FMST PMOS ports control bits:
logic 0: corresponding buffer is ‘off’ (default)
logic 1: corresponding buffer is ‘on’ X don’t care
+ N13 × 213+ ... + N1 × 21+N0
TDA6502; TDA6502A;
TDA6503; TDA6503A
Table 6 Address selection bits (I
2
C-bus mode)
MA1 MA0 VOLTAGE APPLIED TO PIN CE/AS
0 0 0 V to 0.1V
CC
0 1 0.2VCCto 0.3VCC or open-circuit 1 0 0.4V 1 1 0.9VCCto 1.0V
CC
to 0.6V
CC CC
Table 7 Test mode bits
T2 T1 T0 TEST MODE
0 0 0 normal mode 0 0 1 normal mode (note 1) 0 1 X charge pump is off 1 1 0 charge pump is sinking current 1 1 1 charge pump is sourcing current 100f 101
is available on pin LOCK/ADC (note 2)
REF
1
f
is available on pin LOCK/ADC (note 2)
2
DIV
Notes
1. This is the default mode at Power-on reset.
2. The ADC input cannot be used when these test modes are active; see Section 8.2.3 for more information.
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Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
Table 8 Reference divider ratio select bits
RSA RSB REFERENCE DIVIDER RATIO FREQUENCY STEP (kHz)
X 0 80 50 0 1 128 31.25 1 1 64 62.5
8.2.3 R The read mode is defined by the address byte ADB with bit R/W = 1 (see Table 9). After the slave address has been recognized, the device generates an acknowledge pulse and status byte SB is
transferred on the SDA line (MSB first). Data is valid on the SDA line during a HIGH level of the SCL line. A second data bytecan be read from the device if the microcontroller generates an acknowledge on the SDA line (masteracknowledge).
End of transmission will occur if no master acknowledge occurs. The device will then release the data line to allow the microcontroller to generate a STOP condition.
Bit POR is set to logic 1 at power-on. The bit is reset when an end-of-data is detected by the device (end of a read sequence). Control of the loop is made possible with bit FL which indicates when the loop is locked (bit FL = 1)
A built-in ADC input is available on pin LOCK/ADC (I2C-bus mode only). This converter can be used to apply AFC information to the microcontroller of the IF section of the television.
EAD MODE
TDA6502; TDA6502A;
TDA6503; TDA6503A
Table 9 Read data format
NAME BYTE
Address byte ADB 1 1 0 0 0 MA1 MA0 R/ Status byte SB POR FL R 1 1 A2 A1 A0
Note
1. MSB is transmitted first.
Table 10 Description of the bits used in Table 9
BIT DESCRIPTION
MA1 and MA0 programmable address bits (see Table 6) R/
W logic1 for read mode
POR Power-on reset flag:
logic 0: at power-off logic 1: at power-on
FL in-lock flag:
logic 0: loop is not locked logic 1: loop is locked
R ready flag:
logic 0: mode after Power-on reset (bit T2 = 0, bit T1 = 0 and bit T0 = 1) and the PLL is locked logic 1: in other conditions
A2, A1 and A0 digital outputs of the 5-level ADC (see Table 11)
MSB
(1)
BIT
LSB
W=1
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Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
Table 11 Digital outputs for analog input levels (note 1)
A2 A1 A0 VOLTAGE APPLIED TO PIN LOCK/ADC
0 0 0 0 to 0.15V 0 0 1 0.15VCCto 0.30V 0 1 0 0.30VCCto 0.45V 0 1 1 0.45VCCto 0.60V 1 0 0 0.60VCCto 1.00V
Note
1. Accuracy is ±0.03 × V
8.2.4 POWER-ON RESET The power-on detection threshold voltage V
reset to the power-on state. At power-on state the following actions take place:
The charge pump current is set to 280 µA
The tuning voltage output is disabled
The test bits T2, T1 and T0 are set to logic ‘001’
The divider bit RSB is set to logic 1
Port register UHF is ‘off’, which means that the UHF oscillator and the UHF mixer are switched off. Consequently, the
VHF oscillator and the VHFmixer areswitched on.Port registers VHFL and VHFH are ‘off’, which means that the VHF tank circuit is operating in the VHF low sub-band. The tuning amplifier is switched off untilthe firsttransmission. Inthat case, the tank circuit is supplied with the maximum tuning voltage. The oscillator is therefore operating at the end of the VHF low sub-band.
CC
.
is set to 3.2 V at room temperature. Below this threshold the device is
POR
CC
TDA6502; TDA6502A;
TDA6503; TDA6503A
CC CC CC CC
Table 12 Default setting of the bits at Power-on reset
NAME BYTE
MSB LSB
Address byte ADB 1 1 0 0 0 MA1 MA0 X Divider byte 1 DB1 0 XXXXXXX Divider byte 2 DB2 XXXXXXXX Control byte CB 1 1 0 0 1 X 1 1 Band switch byte BB XXXX0000
2000 Mar 16 12
BITS
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Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
8.3 3-wire bus data format
During a HIGH level on pin CE/AS (enable line), the data is clocked into the data register at the HIGH-to-LOW transition of the clock (see Figs 4 and 5).
The first four bits control the PMOS ports and are loaded intothe internal band-switchregisteron the 5thrising edge of the clock pulse.
The frequency bits are loaded into the frequency register at the HIGH-to-LOW transition of the enable line when an 18-bit or 19-bit data word is transmitted. When a 27-bit dataword is transmitted,thefrequency bits areloadedinto the frequency register on the 20th rising edge of the clock pulseand the controlbits at theHIGH-to-LOW transition of the enable line (see Fig.6).
In this control mode the reference divider is given by bits RSA and RSB (see Table 8).
The test bits T2, T1 and T0, the charge pump bit CP, the ratio select bit RSB and bit OS can only be selected or changed with a 27-bit transmission. They remain programmed if an 18-bit or 19-bit transmission occurs. Onlybit RSA is controlledbythe transmission lengthwhen the 18-bit or 19-bit format is used. When an 18-bit data word is transmitted, the most significant bit of the divider (bit N14) is internally set to logic 0 and bit RSA is set to logic 1. When a 19-bit data word is transmitted, bit RSA is set to logic 0.
It is not allowed to address the devices with words whose length is different from 18, 19 or 27 bits. A data word of lessthan 18 bits willnot affect the frequencyregister of the device.
TDA6502; TDA6502A;
TDA6503; TDA6503A
8.3.1 POWER-ON RESET The power-on detection threshold voltage V
3.2 Vatroom temperature. Below this threshold thedevice is reset to the power-on state.
At power-on state the following actions take place:
The charge pump current is set to 280 µA
The test bits T2, T1 and T0 are set to logic ‘001’
The divider bit RSB is set to logic 1
The tuning voltage output is disabled
The tuning amplifiercontrol bit OS isautomatically reset
to logic 0 in 18-bit and 19-bit modes when the first data word is received to allow normal operation
Port register UHF is ‘off’, which means that the UHF oscillator and the UHF mixer are switched off. Consequently,the VHF oscillatorandthe VHF mixerare switched on. Port registers VHFL and VHFH are ‘off’, which means that theVHF tank circuitis operating inthe VHF low sub-band. The tuning amplifier is switched off until the first transmission. In that case, the tank circuit is supplied with the maximum tuning voltage. The oscillator is therefore operating at the end of the VHF low sub-band
The reference divider ratio is set to 64 or 128 if the first sequence to the device has 18 bits or 19 bits; if the sequence has 27 bits, the reference divider ratio is set by bits RSA and RSB (see Table 8).
POR
is set to
The definition of the bits is unchanged compared to the I2C-bus mode.
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5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
handbook, full pagewidth
DA
CL
CE
INVALID
DATA
BAND-SWITCH
DATA
FMST
PVHFL
PUHF
PVHFH
145 18
LOAD BAND-SWITCH
N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0
REGISTER
FREQUENCY
DATA
TDA6502; TDA6502A;
TDA6503; TDA6503A
INVALID
DATA
LOAD FREQUENCY
REGISTER
FCE572
handbook, full pagewidth
INVALID
DATA
DA
CL
CE
Fig.4 18-bit data format (bit RSA = 1).
BAND-SWITCH
DATA
FMST
PVHFL
PUHF
PVHFH
145 19
LOAD BAND-SWITCH
REGISTER
N13N14 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0
FREQUENCY
DATA
LOAD FREQUENCY
INVALID
DATA
REGISTER
FCE573
Fig.5 19-bit data format (bit RSA = 0).
2000 Mar 16 14
Page 15
Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
handbook, full pagewidth
DA
CL
CE
INVALID
DATA
BAND-SWITCH
DATA
FMST
PVHFL
PUHF
PVHFH
145 272019
LOAD BAND-SWITCH
REGISTER
FREQUENCY
DATA
N13N14 N12 N2 N1 N0 X CP T2 T1 T0 RSA RSB OS
LOAD FREQUENCY
REGISTER
TDA6502; TDA6502A;
TDA6503; TDA6503A
TEST AND FEATURES
DATA
LOAD CONTROL
REGISTER
INVALID
DATA
FCE574
Fig.6 27-bit data format; test and features mode.
2000 Mar 16 15
Page 16
Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
9 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); note 1.
PIN
SYMBOL
V
CC
V
Pn
I
Pn
V
CP
V
SW
V
VT
V
LOCK/ADC
V
CL
V
DA
I
DA
V
CE/AS
V
XTAL
I
O(n)
t
sc(max)
T
stg
T
amb
T
j
TDA6502;
TDA6502A
TDA6503;
TDA6503A
19 10 DC supply voltage 0.3 +6 V
OVSpulse time is 1 s; maximum current is
1 A 7 to 10 19 to 22 PMOS port output voltage 0.3 VCC+0.3 V 7 to 10 19 to 22 PMOS port output current 1 +30 mA
16 13 charge pump output voltage 0.3 VCC+0.3 V 11 18 bus format selection input voltage 0.3 VCC+ 0.3 V 17 12 tuning voltage output 0.3 +35 V 15 14 lock/ADC output/input voltage 0.3 VCC+0.3 V 14 15 serial clock input voltage 0.3 +6 V 13 16 serial data input/output voltage 0.3 +6 V 13 16 data output current (I2C-bus mode) 1 +10 mA 12 17 chip enable/address selection input
voltage
18 11 crystal input voltage 0.3 VCC+0.3 V
1to6,
19 to 28
1 to 10,
23 to 28
output current of each pin to ground −−10 mA
−−maximumshort-circuit time (all pins to V and all pins to GND, OSCGND and RFGND)
−−storage temperature −40 +150 °C
−−ambient temperature −20 +85 °C
−−junction temperature 150 °C
PARAMETER MIN. MAX. UNIT
TDA6502; TDA6502A;
TDA6503; TDA6503A
8V
0.3 +6 V
10 s
CC
Note
1. Maximum ratings can not be exceeded, not even momentarily without causing irreversible IC damage. Maximum ratings can not be accumulated.
10 THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS TYP. UNIT
R
th(j-a)
thermal resistance from junction to ambient in free air 110 K/W
2000 Mar 16 16
Page 17
Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
TDA6502; TDA6502A;
TDA6503; TDA6503A
11 CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supply; T
V
CC
I
CC
=25oC
amb
supply voltage 4.5 5.0 5.5 V supply current at VCC=5V
all PMOS ports ‘off’ 71 78 mA one PMOS port ‘on’ and
103 113 mA
sourcing 25 mA one PMOS port ‘on’and sourcing
111 122 mA 25 mA; a second port ‘on’ and sourcing 5 mA
PLL part; V
F
UNCTIONAL RANGE
V
POR
= 4.5 to 5.5 V; T
CC
power-on reset supply voltage
= 20 to +85 °C; unless otherwise specified
amb
below this supply voltage power-on reset becomes active
3.2 V
N divider ratio 15-bit frequency word 64 32767
14-bit frequency word 64 16383
f
XTAL
Z
XTAL
crystal oscillator frequency R
input impedance
=25to300Ω−4.0 MHz
XTAL
f
= 4 MHz 600 1200 −Ω
XTAL
(absolute value) PMOS PORTS: PINS PUHF, PVHFL, PVHFH AND FMST I
Pn(off)
V
Pn(sat)
leakage current VCC= 5.5 V; VPn=0V −10 −−µA
output saturation voltage V
Pn(sat)=VCC
VPn;
0.25 0.4 V
one buffer output is ‘on’ and
sourcing 25 mA LOCK OUTPUT: PIN LOCK/ADC (IN 3-WIRE BUS MODE) I
UNLOCK
output current when the PLL
VCC= 5.5 V; VO= 5.5 V −−200 µA
is out-of-lock
V
UNLOCK
output saturation voltage
V
UNLOCK=VCC
VO; IO= 200 µA 0.4 0.8 V
when the PLL is out-of-lock
V
LOCK
output voltage the PLL is locked 0.2 0.40 V ADC INPUT: PIN LOCK/ADC (IN I2C-BUS MODE) V
ADC
I
ADC(H)
I
ADC(L)
ADC input voltage see Table 11 0 V
HIGH-level input current V
LOW-level input current V
ADC=VCC
=0V −10 −−µA
ADC
−−10 µA
CC
V
BUS FORMAT SELECTION: PIN SW V
SW(L)
V
SW(H)
I
SW(H)
I
SW(L)
LOW-level input voltage 0 1.5 V
HIGH-level input voltage 3 V
HIGH-level input current VSW=V
CC
−−10 µA
CC
V
LOW-level input current VSW=0V −100 −−µA
2000 Mar 16 17
Page 18
Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
TDA6502; TDA6502A;
TDA6503; TDA6503A
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
CHIP ENABLE/ADDRESS SELECTION INPUT: PIN CE/AS V
CE/AS(L)
V
CE/AS(H)
I
CE/AS(H)
I
CE/AS(L)
LOW-level input voltage 0 1.5 V
HIGH-level input voltage 3 5.5 V
HIGH-level input current V
LOW-level input current V
= 5.5 V −−10 µA
CE/AS
=0V −10 −−µA
CE/AS
CLOCK AND DATA INPUTS: PINS CL AND DA V
CL(L)
V
DA(L)
V
CL(H)
V
DA(H)
I
CL(H)
I
CL(L)
,
,
, I
, I
LOW-level input voltage 0 1.5 V
HIGH-level input voltage 3 5.5 V
HIGH-level input current V
DA(H)
LOW-level input current V
DA(L)
= 5.5 V; VCC=0V −−10 µA
BUS
V
= 5.5 V; VCC= 5.5 V −−10 µA
BUS
= 1.5 V; VCC=0V −−10 µA
BUS
V
=0V; VCC= 5.5 V 10 −−µA
BUS
DATA OUTPUT: PIN DA (IN I2C-BUS MODE ONLY) I
DA(H)
V
DA(H)
HIGH-level output current VDA= 5.5 V −−10 µA
HIGH-level output voltage IDA= 3 mA (sink current) −−0.4 V CLOCK FREQUENCY (I2C-BUS MODE) f
clk
clock frequency −−400 kHz CHARGE PUMP OUTPUT: PIN CP
I
HIGH-level input current
CP(H)
CP = 1 280 −µA
(absolute value)
I
LOW-level input current
CP(L)
CP = 0 60 −µA
(absolute value) I
CP(leak)
off-state leakage current T2 = 0; T1 = 1 15 0.5 +15 nA TUNING VOLTAGE OUTPUT: PIN VT I
VT(off)
leakage current when
OS = 1; tuning supply is 33 V −−10 µA
switched-off V
VT
output voltage when the loop
is closed
OS = 0; T2 = 0; T1 = 0; T0 = 1; RL=27kΩ; tuning supply is 33 V
0.2 32.7 V
Mixer/oscillator part; V
VHF
MIXER (INCLUDING IF PREAMPLIFIER)
f
RF(o)
f
RF
G
v
RF operational frequency 40 800 MHz
RF frequency note 1 55.25 361.25 MHz
voltage gain fRF= 57.5 MHz; see Fig.12 17.5 20 22.5 dB
=5V; T
CC
NF noise figure f
=25oC; measurements related to the measurement circuit (see Fig.19)
amb
= 363.5 MHz; see Fig.12 17.5 20 22.5 dB
f
RF
= 50 MHz; see Figs 13 and 14 7.5 10 dB
RF
= 150 MHz; see Figs 13 and 14 7.5 10 dB
f
RF
f
= 300 MHz; see Fig.14 7.5 10 dB
RF
2000 Mar 16 18
Page 19
Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
TDA6502; TDA6502A;
TDA6503; TDA6503A
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
o
V
i
output voltage (causing 1%
cross modulation in channel)
input voltage (causing
fRF= 55.25 MHz; see Fig.15 107 110 dBµV f
= 361.25 MHz; see Fig.15 107 110 dBµV
RF
fRF= 361.25 MHz; note 2 83 dBµV
pulling-in channel at 750 Hz) g
os
g
i
C
i
optimum source
conductance for noise figure
fRF=50MHz 0.7 mS f
= 150 MHz 0.9 mS
RF
= 300 MHz 1.5 mS
f
RF
input conductance fRF= 55.25 MHz; see Fig.7 0.3 mS
f
= 361.25 MHz; see Fig.7 0.4 mS
RF
input capacitance fRF= 57.5 to 357.5 MHz; see Fig.7 1.35 pF VHF OSCILLATOR f
OSC(o)
oscillator operational
60 600 MHz
frequency f
OSC
f
OSC(V)
f
OSC(T)
f
OSC(t)
Φ
OSC
RSC ripple susceptibility of V
oscillator frequency note 3 101 407 MHz
oscillator frequency variation
with supply voltage
oscillator frequency variation
with temperature
VCC= 5%; note 4 60 kHz ∆V
= 10%; note 4 110 kHz
CC
T=25°C; with compensation;
1600 kHz
note 5 oscillator frequency drift 5 s to 15 min after switch-on;note 6 400 kHz phasenoise, carrier-to-noise
sideband
(peak-to-peak value)
±100 kHz frequency offset; worst
case in the frequency range
VCC= 5 V; worst case in the
CC
frequency range; ripple frequency
105 dBc/Hz
15 30 mV
500 kHz; note 7
UHF MIXER (INCLUDING IF PREAMPLIFIER) f
RF(o)
f
RF
G
v
NF noise figure (not corrected
V
o
V
i
RF operational frequency 200 900 MHz RF frequency note 1 367.25 801.25 MHz voltage gain fRF= 369.5 MHz; see Fig.16 29 32 35 dB
= 803.5 MHz; see Fig.16 29 32 35 dB
f
RF
f
= 369.5 MHz; see Fig.17 79dB
RF
for image) output voltage (causing 1%
cross modulation in channel) input voltage (causing
f
= 803.5 MHz; see Fig.17 79dB
RF
fRF= 367.25 MHz; see Fig.18 107 110 dBµV
f
= 801.25 MHz; see Fig.18 107 110 dBµV
RF
fRF= 801.25 MHz; note 2 85 dBµV pulling in channel at 750 Hz)
2000 Mar 16 19
Page 20
Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
TDA6502; TDA6502A;
TDA6503; TDA6503A
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Z
i
input impedance (RS+jLSω)RS at fRF= 367.25 MHz; see Fig.8 26 −Ω
R
at fRF= 801.25 MHz; see Fig.8 28 −Ω
S
L
at fRF= 367.25 MHz; see Fig.8 8.5 nH
S
L
at fRF= 801.25 MHz; see Fig.8 8 nH
S
UHF OSCILLATOR f
OSC(o)
oscillator operational
300 1000 MHz
frequency
f
OSC
f
OSC(V)
f
OSC(T)
f
OSC(t)
oscillator frequency note 3 413 847 MHz oscillator frequency variation
with supply voltage oscillator frequency variation
with temperature oscillator frequency drift 5 s to 15 min after switching on;
VCC= 5%; note 4 35 kHz
= 10%; note 4 100 kHz
V
CC
T=25°C; with compensation;
500 kHz
note 5
120 kHz
note 6
Φ
OSC
RSC ripple susceptibility of V
phasenoise, carrier-to-noise sideband
CC
(peak-to-peak value)
±100 kHz frequency offset; worst
case in the frequency range
VCC= 5 V; worst case in the
frequency range; ripple frequency
105 dBc/Hz
15 30 mV
500 kHz; note 7
IF PREAMPLIFIER IF IF operational frequency 30 60 MHz
S
22
output reflection coefficient magnitude; see Fig.9 −−12.8 dB
phase; see Fig.9 0.2 degree
Z
o
output impedance (RS+jLSω)
RS at 43.5 MHz; see Fig.9 80 −Ω
L
at 43.5 MHz; see Fig.9 0.5 nH
S
REJECTION AT THE IF OUTPUT INT
div
level of divider interferences
worst case; note 8 16 20 dBµV in the IF signal
INT
INT
xtal
ref
crystal oscillator interferences rejection
reference frequency rejection
VIF= 100 dBµV; worst case in the
frequency range; note 9
VIF= 100 dBµV; worst case in the
frequency range; f
= 62.5 kHz;
REF
60 −−dBc
60 −−dBc
note 10
INT
ch6
channel 6 beat V
RF(pix)=VRF(snd)
=80dBµV;
tbf 54 dBc
note 11
INT
chA-5
channel A-5 beat V
=80dBµV; note 12 tbf 60 dBc
RF(pix)
Notes
1. The RF frequency range is defined by the oscillator frequency range and the IF frequency.
2. This is the level of the RF signal (100% amplitude modulated with 11.89 kHz) that causes a 750 Hz frequency deviation on the oscillator signal; it produces sidebands 30 dB below the level of the oscillator signal.
3. Limits are related to the tank circuits used in Fig.19; frequency bands may be adjusted by the choice of external components.
2000 Mar 16 20
Page 21
Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
TDA6502; TDA6502A;
TDA6503; TDA6503A
4. The frequency shift is defined as a change in oscillator frequency when the supply voltage varies from VCC= 5 to 4.75 V (4.5 V) or from VCC= 5 to 5.25 V (5.5 V). The oscillator is free running during this measurement.
5. The frequency drift is defined as a change in oscillator frequency when the ambient temperature varies from T
=25to50°C or from T
amb
=25to0°C. The oscillator is free running during this measurement.
amb
6. Switch-on drift isdefined as thechange in oscillator frequency between5 s and 15 min after switch-on.The oscillator is free running during this measurement.
7. The ripple susceptibility is measured for a 500 kHz ripple at the IF output using the measurement circuit of Fig.19; the level ofthe ripplesignal is increased until a difference of53.5 dB occurs between the IF carrier fixed at100 dBµV and the sideband components.
8. This is the level of divider interferences close to the IF frequency. For example channel C: f
1
⁄4f
= 44.75 MHz. The VHFIN input must be left open (i.e. not connected to any load or cable); The UHFIN1 and
OSC
= 179 MHz,
OSC
UHFIN2 inputs are connected to a hybrid.
9. Crystal oscillator interference means the 4 MHz sidebands caused by the crystal oscillator. The rejection has to be greater than 60 dB for an IF output signal of 100 dBµV.
10. The reference frequency rejection is the level of reference frequency sidebands related to the sound sub-carrier.
11. Channel 6 beat is the interfering product of f
RF(pix)+fRF(snd)
12. Channel A-5 beat is the interfering product of f The possible mechanisms are: f
2 × fIF or 2 × f
OSC
RF(pix), fIF
RF(pix)
and f
f
f
of channel 6 at 42 MHz.
OSC
of channel A-5: f
OSC
. For the measurement: VRF=80dBµV.
OSC
= 45.5 MHz.
beat
handbook, full pagewidth
1
2
5
10
10
5
2
1
0.5
0.20.512510
400 MHz
0.5
40 MHz
FCE528
0.2
j
0
+ j
0.2
Fig.7 Input admittance (S11) of the VHF mixer input (40 to 400 MHz); Y0= 20 mS.
2000 Mar 16 21
Page 22
Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
handbook, full pagewidth
0.5
0.2 350 MHz
+ j
0
j
0.2
0.5
0.5 10.2 1052
1
860 MHz
TDA6502; TDA6502A;
TDA6503; TDA6503A
2
5
10
10
5
2
handbook, full pagewidth
1
FCE529
Fig.8 Input impedance (S11) of the UHF mixer input (350 to 860 MHz); Z0=50Ω.
1
0.5
0.2
+ j
0
j
0.2
0.5 10.2 1052
20 MHz
100 MHz
2
5
10
10
5
0.5
1
Fig.9 Output impedance (S22) of the IF amplifier (20 to 60 MHz); Z0=50Ω.
2000 Mar 16 22
2
FCE530
Page 23
Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
TDA6502; TDA6502A;
TDA6503; TDA6503A
12 TIMING CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN. UNIT
3-wire bus timing
t
HIGH
t
SU;DA
t
HD;DA
t
SU;ENCL
t
HD;ENDA
t
EN
clock HIGH time see Fig.10 2 µs data set-up time see Fig.10 2 µs data hold time see Fig.10 2 µs enable-to-clock set-up time see Fig.10 10 µs enable-to-data hold time see Fig.10 2 µs enable time between two
see Fig.11 10 µs
transmissions
t
HD;ENCL
handbook, full pagewidth
enable-to-clock active edge hold time see Fig.11 6 µs
DA
INVALID
DATA
MSB
LSB
INVALID
DATA
CL
t
HIGH
t
SU;DA
t
HD;DA
CE
t
SU;ENCL
Fig.10 Timing diagram for 3-wire bus; DA, CL and CE.
handbook, halfpage
CE
CL
t
t
HD;ENCL
EN
t
HD;ENDA
FCE576
FCE575
Fig.11 Timing diagram for 3-wire bus; CE and CL.
2000 Mar 16 23
Page 24
Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
13 TEST AND APPLICATION INFORMATION
13.1 Test circuits
handbook, full pagewidth
Zi>> 50 Ω⇒Vi=2×V Vi=V
V
G
=V’
o
= 20 log
v
meas
meas
+6dB=80dBµV
50 27+
×
-------------------
V
o
-----­V
i
e
=80dBµV
meas
50
50
signal source
V
meas
V
RMS
voltmeter
50
VHFIN
V
i
D.U.T.
IFOUT
TDA6502; TDA6502A;
TDA6503; TDA6503A
27
V
V'
o
meas
spectrum analyzer
50
FCE577
Fig.12 Gain measurement in VHF band.
handbook, full pagewidth
(a) For fRF= 50 MHz:
mixer A frequency response measured = 57 MHz, loss = 0 dB image suppression = 16 dB C1 = 9 pF C2 = 15 pF L1 = 7 turns (5.5 mm, wire = 0.5 mm) l1 = semi rigid cable (RIM) of 5 cm long
(semi rigid cable (RIM); 33 dB/100 m; 50 ; 96 pF/m).
C1
BNC BNC
L1 C2
I1
RIM-RIM
(a) (b)
C4
I3
I2
RIM-RIM
PCB
FCE578
PCB
C3
plug plug
(b) For fRF= 150 MHz:
mixer A frequency response measured = 150.3 MHz, loss = 1.3 dB image suppression = 13 dB C3 = 5 pF C4=25pF l2 = semi rigid cable (RIM): 30 cm long l3 = semi rigid cable (RIM) of 5 cm long
(semi rigid cable (RIM); 33 dB/100 m; 50 Ω; 96 pF/m).
Fig.13 Input circuit for optimum noise figure in VHF band.
2000 Mar 16 24
Page 25
Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
handbook, full pagewidth
NOISE
SOURCE
BNC
INPUT
CIRCUIT
RIM
VHFIN
D.U.T.
IFOUT
TDA6502; TDA6502A;
TDA6503; TDA6503A
27
NOISE
FIGURE
METER
FCE579
NF = NF
loss (of input circuit) (dB).
meas
Fig.14 Noise figure (NF) measurement in VHF band.
handbook, full pagewidth
e
u
e
w
Vo=V Wanted output signal at f
Measuring the level of the unwanted output signal V f
OSC
Filter characteristics: fc= 45.75 MHz, f
50 27+
×
-------------------
meas
50
= 101 (407) MHz.
50
50
AM = 30%
2 kHz
unwanted
signal
source
wanted
signal
source
= 55.25 (361.25) MHz; V
RF(w)
A
HYBRID
B
3 dB(BW)
C
D
o(u)
= 1.4 MHz, f
VHFIN
50
= 100 dBµV.
o(w)
causing 0.3% AM modulation in the wanted output signal; f
30 dB(BW)
IFOUT
D.U.T.
= 3.1 MHz.
27
V
o
RMS
voltmeter
18 dB
attenuator
V
V
meas
FILTER
45.75 MHz
= 59.75 (366.75) MHz.
RF(u)
modulation analyzer
50
FCE580
Fig.15 Cross modulation measurement in VHF band.
2000 Mar 16 25
Page 26
Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
handbook, full pagewidth
Loss (in hybrid) = 1 dB. Vi=V
V
G
loss (in hybrid) = 70 dBµV.
meas
meas
50 27+
×
-------------------
V
o
-----­V
i
=V’
o
= 20 log
v
e
50
50
signal source
V
meas
V
RMS
voltmeter
50
50
V
i
A
HYBRID
B
C
D
UHFIN1
D.U.T.
UHFIN2
IFOUT
TDA6502; TDA6502A;
TDA6503; TDA6503A
27
V
V'
o
meas
spectrum analyzer
50
FCE581
handbook, full pagewidth
Loss (in hybrid) = 1 dB. NF = NF
loss (in hybrid).
meas
NOISE
SOURCE
Fig.16 Gain (Gv) measurement in UHF band.
A
HYBRID
B
50
UHFIN
C
UHFIN
D
IFOUT
D.U.T.
27
NOISE
FIGURE
METER
FCE582
Fig.17 Noise figure (NF) measurement in bands UHF.
2000 Mar 16 26
Page 27
Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
handbook, full pagewidth
e
u
e
w
Vo=V
meas
Wanted output signal at f Measuring the level of the unwanted output signal V f
= 413 (847) MHz.
OSC
Filter characteristics: fc= 45.75 MHz, f
50
50
×
AM = 30%
unwanted
50 27+
------------------­50
2 kHz
signal
source
wanted
signal
source
A
C
HYBRID
B
D
50 50
= 367.25 (801.25) MHz; V
RF(w)
3 dB(BW)
A
C
UHFIN
HYBRID
B
D
UHFIN
= 100 dBµV.
o(w)
causing 0.3% AM modulation in the wanted output signal; f
o(u)
= 1.4 MHz, f
30 dB(BW)
= 3.1 MHz.
D.U.T.
IFOUT
V
TDA6502; TDA6502A;
TDA6503; TDA6503A
FILTER
45.75 MHz
= 371.25 (805.75) MHz.
RF(u)
27
o
attenuator
V
RMS
voltmeter
18 dB
V
meas
modulation analyzer
50
FCE583
Fig.18 Cross modulation measurement in UHF band.
2000 Mar 16 27
Page 28
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2000 Mar 16 28
13.2 Measurement circuit
Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
W1
D4
LED
D5
LED
D6
LED
D7
LED
for test purpose only
BC847B
C27 10 µF (16 V)
CON1
TR1
RIPPLE
R15
R16
R17 R18
V
CC
R26
6.8 k
C26
10 µF
(16 V)
W2
330
330
330 330
C1
4.7 nF
W3
R21
330
C2
4.7 nF
C3
4.7 nF
C4
15 pF
C5
15 pF
open for 3-wire
R20
330
01 02
CLOCK
0303040405 06
GND
DATA
L4
CON4
+5 V
UHFIN1
UHFIN2
VHFIN
RFGND
IFFIL1
IFFIL2
PVHFL
PVHFH
PUHF
FMST
SW
CE/AS
DA
CL
R19
330
LOCK
EN/AS
1(28)
2(27)
3(26)
4(25)
5(24)
6(23)
7(22)
8(21)
9(20)
10(19)
11(18)
12(17) 13(16)
14(15)
J3
TDA6502/2A
(TDA6503/3A)
R22
330
R25
1 k
R24
68 k
BC847B
for test purpose only
28(1)
27(2) 26(3)
25(4)
24(5)
23(6)
22(7)
21(8)
20(9)
19(10)
18(11)
17(12)
16(13)
15(14)
UHFOSCOC2
UHFOSCIB2
UHFOSCOC1
UHFOSCIB1
VHFOSCOC
OSCGND
VHFOSCIB
GND
IFOUT
V
CC
XTAL
VT
CP
LOCK/ADC
LOCK/ADC
TR2
V
CC
Y1
C21
100 nF
C8 1.2 pF
C9 1.2 pF
C10 1.2 pF
C11 1.2 pF
C13 2 pF
C14
2 pF
L5
C19 4.7 nF
C20
18 pF
R12
12 k
C22
330 pF
R2 27
BB178
D2
L2
C18 4.7 nF
CON3
J2
L1
J1
R13
22 k
+5 V
C15
82 pF
L3
C16
4.7 nF
02
VS
2.2 k
01
+33 V
R14
GND
D1 BB179
C12 27 pF
R6 5.6
C17
4.7 nF
BA792
D3
3.9 k
3.9 k
R9
R10
C23 10 nF
27
R3
22 k
R4
22 k
10 k
680
R11
R7
C6
22 nF
R8
for test purpose only
R5
22 k
VHF-HIGH
VHF-LOW
FCE481
TDA6502; TDA6502A;
TDA6503; TDA6503A
The pin numbers in brackets represent the TDA6503 and TDA6503A.
handbook, full pagewidth
Fig.19 Measurement circuit.
Page 29
Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
Table 13 Capacitors (all SMD and NP0)
COMPONENT VALUE
C1 4.7 nF C2 4.7 nF C3 4.7 nF C4 15 pF C5 15 pF C6 22 nF C8 1.2 pF (N750) C9 1.2 pF (N750) C10 1.2 pF(N750) C11 1.2 pF (N750) C12 27 pF (N750) C13 2 pF (N750) C14 2 pF (N750) C15 82 pF (N750) C16 4.7 nF C17 4.7 nF C18 4.7 nF C19 4.7 nF C20 18 pF C21 100 nF C22 330 pF C23 10 nF C26 10 µF (16 V, electrolytic) C27 10 µF (16 V, electrolytic)
Table 14 Resistors (all SMD)
COMPONENT VALUE
R2 27 R3 22 k R4 22 k R5 22 k R6 5.6 R7 10 k R8 680 R9 3.9 k R10 3.9 k R11 27 R12 12 k R13 22 k R14 2.2 k
TDA6502; TDA6502A;
TDA6503; TDA6503A
COMPONENT VALUE
R15 330 R16 330 R17 330 R18 330 R19 330 R20 330 R21 330 R22 330 R24 68 k R25 1 k R26 6.8 k
Table 15 Diodes and ICs
COMPONENT VALUE
D1 BB179 D2 BB178 D3 BA792 IC TDA6502; TDA6502A
TDA6503; TDA6503A
Table 16 Coils (note 1)
COMPONENT VALUE
L1 1.5 turns; diameter 1.5 mm L2 2.5 turns; diameter 2.5 mm L3 7.5 turns; diameter 3.0 mm L5 2.5 turns; diameter 2.5 mm
Note
1. Wire size is 0.4 mm.
Table 17 Transformer (note 1)
COMPONENT VALUE
L4 2x 5 turns
Note
1. Coil type: TOKO 7kN; material: 113 kN; screw core: 03-0093; pot core: 04-0026.
Table 18 Crystal
COMPONENT VALUE
Y1 4 MHz
2000 Mar 16 29
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Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
Table 19 Transistors
COMPONENT VALUE
TR1 BC847B TR2 BC847B
13.3 Tuning amplifier
The tuning amplifier is capable of driving the varicap voltage without an external transistor. The tuning voltage output must be connected to an external load of 27 k which is connected to the tuning voltage supply rail. The loop filter design depends on the oscillator characteristics and the selected reference frequency.
13.4 Crystal oscillator
The crystal oscillator uses a 4 MHz crystal connected in series with an 18 pF capacitor thereby operating in the series resonance mode. Connecting the crystal to the ground is preferred, but it can also be connected to the supply voltage.
TDA6502; TDA6502A;
TDA6503; TDA6503A
2
13.5 Examples of I
TDA6502 and TDA6503
Tables 20 to 24 show the various write sequences where:
S = START bit A = acknowledge bit P = STOP bit.
Conditions:
f
= 4 MHz
xtal
N = 1600 f
= 100 MHz
osc
f
= 62.5 kHz
step
Port register VHFL is ‘on’ to switch-on band VHF low Port register FMST is ‘on’ to switch-on an FM sound trap ICP= 280 µA.
C-bus data format sequences for
13.5.1 WRITE SEQUENCES TO REGISTER C2
Table 20 Complete sequence with first the divider bytes (first data bit = 0)
START
S C2 A 06 A 40 A CE A 09 A P
Table 21 Complete sequence with first the control and band-switch bytes (first data bit = 1)
START
S C2ACEA09A06A40AP
Table 22 Sequence with divider bytes only (first data bit = 0)
START ADDRESS BYTE ACK DIVIDER BYTE 1 ACK DIVIDER BYTE 2 ACK STOP
S C2A06A40AP
Table 23 Sequence with control and band-switch bytes only (first data bit = 1)
START ADDRESS BYTE ACK CONTROL BYTE ACK BAND-SWITCH BYTE ACK STOP
S C2ACEA09AP
ADDRESS
BYTE
ADDRESS
BYTE
ACK
ACK
DIVIDER
BYTE 1
CONTROL
BYTE
ACK
ACK
DIVIDER
BYTE 2
BAND-
SWITCH
BYTE
ACK
ACK
CONTROL
BYTE
DIVIDER
BYTE 1
ACK
ACK
BAND-
SWITCH
BYTE
DIVIDER
BYTE 2
ACK STOP
ACK STOP
Table 24 Sequence with control byte only (first data bit = 1)
START ADDRESS BYTE ACK CONTROL BYTE ACK STOP
SC2ACEAP
2000 Mar 16 30
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Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
13.5.2 READ SEQUENCES FROM REGISTER C3 Tables 25 and 26 show the various read sequences where:
S = START bit A = acknowledge bit XX = read status byte X = no acknowledge from the master means end of sequence P = STOP bit
Table 25 One status byte acquisition
START ADDRESS BYTE ACK STATUS BYTE ACK STOP
SC3AXXXP
Table 26 Two status bytes acquisition
START ADDRESS BYTE ACK STATUS BYTE ACK STATUS BYTE ACK STOP
S C3 A XX A XX X P
13.6 Examples of 3-wire bus data format sequences for TDA6502 and TDA6503
TDA6502; TDA6502A;
TDA6503; TDA6503A
13.6.1 18-BIT SEQUENCE Conditions:
f
= 800 MHz
osc
Port register PUHF is ‘on’.
Table 27 18-bit sequence
PUHF FMST PVHFH PVHFL N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0
1 0 0 0 1 1 1 0 0100000000
The reference divideris automaticallyset to 64 assuming that bit RSB has beenset to logic 1 at power-on. If bit RSBhas been set to logic 0, in a previous 27-bit sequence, the reference divider will still be set at 80. In this event, the 18-bit sequence has to be adapted to the 80 divider ratio.
13.6.2 19­Conditions:
f
osc
Port register PUHF is ‘on’.
Table 28 19-bit sequence
PUHF FMST PVHFH PVHFL N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0
1 0 0 0 101000101000000
BIT SEQUENCE
= 650 MHz
The reference divider is automatically set to 128 assuming that bit RSB has been set to logic 1 at power-on. If bit RSB has been set to logic 0 in a previous 27-bit sequence, the reference divider will still be set at 80. In this event, the 19-bit sequence has to be adapted to the 80 divider ratio.
2000 Mar 16 31
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Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
13.6.3 27-BIT SEQUENCE Conditions:
f
= 750 MHz
osc
Port register PUHF is ‘on’ Reference divider is set at 80 ICP=60µA No test function.
Table 29 27-bit sequence
PORT BITS
14131211109876543210XCPT2T1T0RSARSBOS
100001110101001100010 001 0 0 0
To change the oscillator frequency to 600 MHz in 50 kHz steps a 19-bit sequence or an 18-bit sequence can be used. The charge pump current remains at 60 µA.
Table 30 Changing frequency with a 19-bit sequence
FREQUENCY DATA BITS CONTROL DATA BITS
TDA6502; TDA6502A;
TDA6503; TDA6503A
PORT BITS
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1000010111011100000
Table 31 Changing frequency with an 18-bit sequence
PORT BITS
13 12 11 10 9 8 7 6 5 4 3 2 1 0
100010111011100000
FREQUENCY DATA BITS
FREQUENCY DATA BITS
2000 Mar 16 32
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Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
14 INTERNAL PIN CONFIGURATION
PIN
SYMBOL
TDA6502;
TDA6502A
TDA6503;
TDA6503A
UHFIN1 1 28 1.0 V UHFIN2 2 27 1.0 V
VHFIN 3 26 −−
DC VOLTAGE
(AVERAGE VALUE)
VHF UHF
(2)
TDA6502; TDA6502A;
TDA6503; TDA6503A
EQUIVALENT CIRCUIT
1
(28)
3
(26)
(1)
2
(27)
FCE584
RFGND 4 25 0.0 V 0.0 V
IFFIL1 5 24 3.6 V 3.6 V IFFIL2 6 23 3.6 V 3.6 V
PVHFL 7 22 n.a. or 4.8 V n.a. PVHFH 8 21 4.8 V or n.a. n.a. PUHF 9 20 n.a. 4.8 V FMST 10 19 n.a. or 4.8 V n.a. or 4.8 V
(22)
(20)
FCE585
4
(25)
FCE586
65 (23)(24)
FCE587
7
9
8
(21)
10
(19)
FCE588
2000 Mar 16 33
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Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
PIN
SYMBOL
TDA6502;
TDA6502A
TDA6503;
TDA6503A
SW 11 18 5.0 V 5.0 V
CE/AS 12 17 1.25 V 1.25 V
DC VOLTAGE
(AVERAGE VALUE)
VHF UHF
(2)
TDA6502; TDA6502A;
TDA6503; TDA6503A
EQUIVALENT CIRCUIT
11
(18)
FCE189
12
(17)
FCE191
(1)
DA 13 16 −−
CL 14 15 −−
LOCK/ADC 15 14 4.6 V 4.6 V
13
(16)
FCE190
14
(15)
FCE192
15
(14)
2000 Mar 16 34
FCE193
Page 35
Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
PIN
SYMBOL
TDA6502;
TDA6502A
TDA6503;
TDA6503A
CP 16 13 1 V 1V
VT 17 12 V
DC VOLTAGE
(AVERAGE VALUE)
VHF UHF
VT
V
VT
(2)
TDA6502; TDA6502A;
TDA6503; TDA6503A
EQUIVALENT CIRCUIT
FCE194
(1)
16
(13)
17
(12)
XTAL 18 11 2.6 V 2.6 V
V
CC
19 10 5.0 V 5.0 V supply voltage
IFOUT 20 9 2.1 V 2.1 V
GND 21 8 0.0 V 0.0 V
FCE591
FCE589
18
(11)
FCE590
20 (9)
21 (8)
FCE592
2000 Mar 16 35
Page 36
Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
PIN
SYMBOL
TDA6502;
TDA6502A
TDA6503;
TDA6503A
OSCGND 23 6 0.0 V 0.0 V
VHFOSCIB 22 7 1.8 V VHFOSCOC 24 5 3.0 V
DC VOLTAGE
(AVERAGE VALUE)
VHF UHF
(2)
TDA6502; TDA6502A;
TDA6503; TDA6503A
EQUIVALENT CIRCUIT
23 (6)
FCE593
22 (7)
(1)
24
(5)
FCE594
UHFOSCIB1 25 4 1.9 V UHFOSCOC1 26 3 2.9 V UHFOSCOC2 27 2 2.9 V UHFOSCIB2 28 1 1.9 V
Notes
1. The pin numbers in parenthesis represent the TDA6503 and TDA6503A.
2. Measured in circuit of Fig.19.
(2) 27
(4)
(3) 26
25
28
(1)
FCE595
2000 Mar 16 36
Page 37
Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
15 PACKAGE OUTLINE
SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm
D
c
y
Z
28 15
TDA6502; TDA6502A;
TDA6503; TDA6503A
SOT341-1
E
H
E
A
X
v M
A
pin 1 index
114
w M
b
e
DIMENSIONS (mm are the original dimensions)
mm
A
max.
2.0
0.21
0.05
1.80
1.65
0.25
b
p
cD
0.20
0.09
3
0.38
0.25
UNIT A1A2A
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
p
0 2.5 5 mm
scale
(1)E(1) (1)
10.4
10.0
eHELLpQZywv θ
5.4
0.65 1.25
5.2
7.9
7.6
Q
A
2
A
1
detail X
1.03
0.9
0.63
0.7
(A )
L
p
L
0.13 0.10.2
A
3
θ
1.1
0.7
o
8
o
0
OUTLINE VERSION
SOT341-1 MO-150
IEC JEDEC EIAJ
REFERENCES
2000 Mar 16 37
EUROPEAN
PROJECTION
ISSUE DATE
95-02-04 99-12-27
Page 38
Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
16 SOLDERING
16.1 Introduction to soldering surface mount packages
Thistext gives a very briefinsightto a complex technology. A more in-depth account of soldering ICs can be found in our
“Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011). There is no soldering method that is ideal for all surface
mount IC packages.Wave soldering isnot always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used.
16.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied tothe printed-circuit boardbyscreen printing, stencilling or pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating,soldering and cooling) vary between 100 and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C.
TDA6502; TDA6502A;
TDA6503; TDA6503A
If wave soldering is used the following conditions must be observed for optimal results:
Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.
For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
Forpackageswith leads on foursides,thefootprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners.
During placement andbefore soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
16.3 Wave soldering
Conventional single wave soldering is not recommended forsurfacemount devices (SMDs) orprinted-circuitboards with a high component density, as solder bridging and non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically developed.
2000 Mar 16 38
16.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.
Page 39
Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
16.5 Suitability of surface mount IC packages for wave and reflow soldering methods
PACKAGE
BGA, LFBGA, SQFP, TFBGA not suitable suitable HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable
(3)
PLCC LQFP, QFP, TQFP not recommended SSOP, TSSOP, VSO not recommended
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
5. Wave soldering is only suitable for SSOP and TSSOP packageswith a pitch (e) equal to or larger than 0.65 mm; it is
, SO, SOJ suitable suitable
temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
The package footprint must incorporate solder thieves downstream and at the side corners.
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”
TDA6502; TDA6502A;
TDA6503; TDA6503A
SOLDERING METHOD
WAVE REFLOW
(2)
(3)(4) (5)
suitable
suitable suitable
(1)
.
2000 Mar 16 39
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Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
17 DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
18 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
TDA6502; TDA6502A;
TDA6503; TDA6503A
19 PURCHASE OF PHILIPS I
Purchase of Philips I components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
2
C COMPONENTS
2
C components conveys a license under the Philips’ I2C patent to use the
2000 Mar 16 40
Page 41
Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
NOTES
TDA6502; TDA6502A;
TDA6503; TDA6503A
2000 Mar 16 41
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Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
NOTES
TDA6502; TDA6502A;
TDA6503; TDA6503A
2000 Mar 16 42
Page 43
Philips Semiconductors Preliminary specification
5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners
NOTES
TDA6502; TDA6502A;
TDA6503; TDA6503A
2000 Mar 16 43
Page 44
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Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398
South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SÃO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382
Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087
Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 3341 299, Fax.+381 11 3342 553
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. SCA All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
2000
Internet: http://www.semiconductors.philips.com
69
Printed in The Netherlands 753504/02/pp44 Date of release: 2000 Mar 16 Document order number: 9397 750 06924
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