• 5-step analog-to-digital converter (3 bits in I2C-bus
mode)
• 15-bit programmable divider
• Programmable reference divider ratio (64, 80 or 128)
• Programmable charge pump current (60 or 280 µA)
• Varicap drive disable
• Balanced mixer with a common emitter input for VHF
(single input)
• Balanced mixer with a common base input for UHF
(balanced input)
• 2-pin common emitter oscillator for VHF
• 4-pin common emitter oscillator for UHF
• IF preamplifier with asymmetrical 75 Ω outputimpedance able to drive loads from 75 Ω upwards
• Low power
• Low radiation
• Small size
• TheTDA6502AandTDA6503Adiffer from the TDA6502
and TDA6503 by the UHF port protocol in the I2C-bus
mode (see Tables 3 and 4).
TDA6502; TDA6502A;
TDA6503; TDA6503A
2APPLICATIONS
• Cable tuners for TV and VCR (switched concept for
VHF).
3GENERAL DESCRIPTION
The TDA6502, TDA6502A, TDA6503 and TDA6503A are
programmable2-band mixers/oscillators andsynthesizers
intended for VHF/UHF TV and VCR tuners (see Fig.1).
Partitioning of the bands is the responsibility of the
customer providing VHF is below 500 MHz and UHF is
below 900 MHz.
The devices include two double balanced mixers and two
oscillators for the VHF and UHF band respectively, an
IF amplifier and a PLL synthesizer. The VHF band can be
split-up into two sub-bands using a proper oscillator
application and a switchable inductor.
Two pins are available between the mixer output and the
IF amplifier input to enable IF filtering for improved signal
handling.
The port register provides four PMOS ports. Band
selection is provided by port register UHF. When port
register UHF is ‘on’, the UHF mixer-oscillator is active and
the VHF band is switched off. When port register UHF is
‘off’, the VHF mixer-oscillator is active and the UHF band
is off. Port registers VHFL and VHFH are used to select
the VHF sub-bands. Port register FMST is a general
purposeport, that can be usedtoswitch an FM sound trap.
Whenthe ports areused,the sum ofthedrain currents has
to be limited to 30 mA.
Thesynthesizerconsists of a 15-bitprogrammabledivider,
a crystal oscillator and its programmable reference divider
and a phase comparator (phase/frequency detector)
combined with a charge pump which drives the tuning
amplifier, including the 33 V output at pin VT. Depending
on the reference divider ratio (64, 80 or 128), the phase
comparator operates at 62.5, 50 or 31.25 kHz with a
4 MHz crystal.
2000 Mar 163
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Philips SemiconductorsPreliminary specification
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
Depending on thevoltage applied to pin SW (see Table 2)
the device is operating in the I2C-bus mode or 3-wire bus
mode.
In the 3-wire bus mode, pin LOCK/ADCis the ‘lock’ output
of the PLL and is at LOW level when the PLL is locked.
Lockdetectorbit FL of the statusbyteisset to logic 1 when
the loop is locked and is read on the SDA line during a
READ operation in I2C-bus mode only.
In the I2C-bus mode only,pin LOCK/ADC is the ADC input
for digital AFC control. The ADC code is read during a
READ operation on the I2C-bus.
In the test mode, in both I2C-bus mode and 3-wire bus
mode, pin LOCK/ADC is used as a test output for f
1
⁄2f
.
DIV
2
3.1I
Five serial bytes (including the address byte) are required
to address thedevice, select the VCO frequency, program
the four ports, set the charge pump current and set the
reference divider ratio. The device has four independent
I2C-bus addresses which can be selected by applying a
specific voltage to pin CE/AS.
1. The selection of the reference divider is given by an
automatic identification of the data word length. When
the 27-bit format is used, the reference divider is
controlled by bits RSA and RSB (see Table 8). More
details are given in Section 8.3.
REFERENCE
DIVIDER
(1)
FREQUENCY
STEP
3.23-wire bus format
Data is transmitted to the device during a HIGH level on
pin CE/AS (enable line). The device is accessible with
18-bit and 19-bit data formats (see Figs 4 and 5). The first
four bits are used to program the PMOS ports and the
remaining bits control the programmable divider. A 27-bit
data format (seeFig.6) may alsobe used to set thecharge
pump current, the reference divider ratio and the test
modes.
It is not allowed to address the device with words whose
length is different from 18, 19 or 27 bits.
2000 Mar 164
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Philips SemiconductorsPreliminary specification
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
TDA6502; TDA6502A;
TDA6503; TDA6503A
4QUICK REFERENCE DATA
Measured over full voltage and temperature ranges.
SYMBOLPARAMETERCONDITIONSMIN.TYP.MAX.UNIT
V
I
CC
CC
supply voltageoperating4.555.5V
supply currentall PMOS ports are off;
−71−mA
VCC=5V
f
XTAL
I
o(PMOS)
P
tot
T
stg
T
amb
f
RF
crystal oscillator frequency−4.0−MHz
PMOS port output currentnote 1−−30mA
total power dissipationnote 2−−520mW
IC storage temperature−40−+150°C
ambient temperature−20−+85°C
RF frequencyVHF band40−800MHz
UHF band200−900MHz
G
V
voltage gainVHF band−20−dB
UHF band−32−dB
NFnoise figureVHF band−7.5−dB
UHF band−7−dB
V
o
output voltage (causing 1% cross
modulation in channel)
VHF band−110−dBµV
UHF band−110−dBµV
Notes
1. One buffer ‘on’, Io= 25 mA; two buffers ‘on’, maximum sum of Io= 30 mA.
2. The power dissipation is calculated as follows:
P
tot
V
CCICCIo
–()V
P(sat)Io
0.5 33V×()
+×+×=
--------------------------------22 kΩ
2
where:
V
= output saturation voltage on the buffer output
P(sat)
I
= source current for one buffer output.
o
5ORDERING INFORMATION
TYPE
NUMBER
TDA6502;
NAMEDESCRIPTIONVERSION
SSOP28plastic shrink small outline package; 28 leads; body width 5.3 mmSOT341-1
PACKAGE
TDA6502A;
TDA6503;
TDA6503A
2000 Mar 165
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Philips SemiconductorsPreliminary specification
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
6BLOCK DIAGRAM
handbook, full pagewidth
VHFIN
RFGND
UHFIN1
UHFIN2
3 (26)
BS
4 (25)
1 (28)
2 (27)
RF INPUT
VHF
TDA6502
TDA6502A
(TDA6503)
(TDA6503A)
RF INPUT
UHF
IFFIL1 IFFIL2
5 (24)
6 (23)
BS
BSBS
VHF
MIXER
UHF
MIXER
V
CC
19 (10)
BS
TDA6502; TDA6502A;
TDA6503; TDA6503A
(5) 24
VHF
BS
OSCILLATOR
IF
PREAMPLIFIER
UHF
OSCILLATOR
(7) 22
(6) 23
(9) 20
(1) 28
(2) 27
(3) 26
(4) 25
VHFOSCOC
VHFOSCIB
OSCGND
IFOUT
UHFOSCIB2
UHFOSCOC2
UHFOSCOC1
UHFOSCIB1
XTAL
CL
DA
SW
CE/AS
18 (11)
14 (15)
13 (16)
11 (18)
12 (17)
XTAL
OSCILLATOR
4 MHz
POWER-DOWN
DETECTOR
SCL
SDA
SW
I
CE/AS
REFERENCE
RSARSB
PROGRAMMABLE
FREQUENCY
FL
2
C-bus / 3-WIRE BUS
TRANSCEIVER
3-BIT ADC
DIVIDER
64, 80, 128
15-BIT
DIVIDER
15-BIT
REGISTER
f
REF
COMPARATOR
f
DIV
DETECTOR
f
REF
FL
GATE
15 (14)
LOCK/ADC
PHASE
IN-LOCK
FL
1/2f
DIV
T0, T1, T2
CHARGE
PUMP
T0, T1, T2
CP T2 T1 T0 RSA RSB OS
UHF VHFH VHFL FMST
BS
9 (20)
PUHF
CP
CONTROL
REGISTER
REGISTER
PVHFH
PORT
8 (21)
OPAMP
OS
7 (22)
PVHFL
FMST
10 (19)
(13) 16
(12) 17
(8) 21
FCE527
CP
VT
GND
The pin numbers in parenthesis represent the TDA6503 and TDA6503A.
Fig.1 Block diagram.
2000 Mar 166
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Philips SemiconductorsPreliminary specification
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
7PINNING
PIN
SYMBOL
UHFIN1128UHF RF input 1
UHFIN2227UHF RF input 2
VHFIN326VHF RF input
RFGND425RF ground
IFFIL1524IF filter output 1
IFFIL2623IF filter output 2
PVHFL722PMOS port output, general purpose (e.g. VHF low sub-band)
PVHFH821PMOS port output, general purpose (e.g. VHF high sub-band)
PUHF920PMOS port output, UHF band
FMST1019PMOS port output, general purpose (e.g. FM sound trap)
SW1118bus format selection input: I
CE/AS1217chip enable input in 3-wire bus mode or address selection input in
DA1316serial data input/output
CL1415serial clock input
LOCK/ADC1514lock detector output in 3-wire bus mode or ADC input in I
CP1613charge pump output
VT1712tuning voltage output
XTAL1811crystal oscillator input
V
The device is controlled via the I2C-bus or the 3-wire bus, depending on the voltage applied to pin SW (see Table 2).
A LOW level on pin SW enables the I2C-bus: pins CE/AS, DA and CL are used as address selection (AS), serial data
(SDA) and serial clock (SCL) input respectively.
A HIGH level on pin SW enables the 3-wire bus: pins CE/AS, DA and CL are used as chip enable (CE), data and clock
inputs respectively.
Table 2 Bus format selection
PIN
SYMBOL
TDA6502;
TDA6502A
TDA6503;
TDA6503A
I2C-BUS MODE3-WIRE BUS MODE
SW1118LOW-level voltage or groundHIGH-level voltage or open-circuit
CE/AS1217address selection inputenable input
DA1316serial data inputdata input
CL1415serial clock inputclock input
LOCK/ADC1514ADC input or test outputlock detector output or test output
2000 Mar 168
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Philips SemiconductorsPreliminary specification
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
8.2I2C-bus data format
2
8.2.1I
The module address contains programmable address
bits MA1 and MA0 (see Tables 3, 4 and 9) which offer the
possibility of having several synthesizers (up to 4) in one
system by applying a specific voltage on pin CE/AS.
The relationship between bits MA1 and MA0 and theinput
voltage applied to pin CE/AS is given in Table 6.
8.2.2W
The write mode is defined by the address byte ADB with
bit R/W = 0 (see Tables 3 and 4).
Data bytes can be sent to the device after the address
transmission (first byte). Four data bytes are needed to
fully program the device.
C-bus data format for write mode of TDA6502 and TDA6503
NAMEBYTE
MSBLSB
The bus transceiver has an auto-increment facility which
permits the programming of the device within one single
transmission (address byte + 4 data bytes). The device
can also be partially programmed providing that the first
data byte following the address byte is divider byte DB1 or
the control byte CB.
The first bit of byte DB1 indicates whether frequency data
(first bit = 0) or control and band-switch data (first bit = 1)
will follow. Until an I
controller,additional data bytescanbe entered without the
need to re-address the device.
The frequency register is loaded after the 8th clock pulse
of byte DB2, the control register is loaded after the 8th
clock pulse of the byte CB and the band-switch register is
loaded after the 8th clock pulse of byte BB.
C-bus data format for write mode of TDA6502A and TDA6503A
BIT
NAMEBYTE
MSBLSB
W=0
Page 10
Philips SemiconductorsPreliminary specification
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
Table 5 Description of the bits used in Tables 3 and 4
BITDESCRIPTION
MA1 and MA0programmable address bits (see Table 6)
Wlogic 0 for write mode
R/
14
N14 to N0programmable divider bits: N = N14 × 2
CPcharge pump current control bit:
logic 0: charge pump current is 60 µA
logic 1: charge pump current is 280 µA (default)
T2, T1 and T0test bits (see Table 7)
RSA and RSBreference divider ratio select bits (see Table 8)
OStuning amplifier control bit:
logic 0: tuning voltage is ‘on’ (during normal operating)
logic 1: tuning voltage is ‘off’; high-impedance output of pin VT (default)
PVHFL, PVHFH, PUHF and FMSTPMOS ports control bits:
logic 0: corresponding buffer is ‘off’ (default)
logic 1: corresponding buffer is ‘on’
Xdon’t care
+ N13 × 213+ ... + N1 × 21+N0
TDA6502; TDA6502A;
TDA6503; TDA6503A
Table 6 Address selection bits (I
2
C-bus mode)
MA1MA0VOLTAGE APPLIED TO PIN CE/AS
000 V to 0.1V
CC
010.2VCCto 0.3VCC or open-circuit
100.4V
110.9VCCto 1.0V
CC
to 0.6V
CC
CC
Table 7 Test mode bits
T2T1T0TEST MODE
000normal mode
001normal mode (note 1)
01Xcharge pump is off
110charge pump is sinking current
111charge pump is sourcing current
100f
101
is available on pin LOCK/ADC (note 2)
REF
1
⁄
f
is available on pin LOCK/ADC (note 2)
2
DIV
Notes
1. This is the default mode at Power-on reset.
2. The ADC input cannot be used when these test modes are active; see Section 8.2.3 for more information.
2000 Mar 1610
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Philips SemiconductorsPreliminary specification
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
Table 8 Reference divider ratio select bits
RSARSBREFERENCE DIVIDER RATIOFREQUENCY STEP (kHz)
X08050
0112831.25
116462.5
8.2.3R
The read mode is defined by the address byte ADB with bit R/W = 1 (see Table 9).
After the slave address has been recognized, the device generates an acknowledge pulse and status byte SB is
transferred on the SDA line (MSB first). Data is valid on the SDA line during a HIGH level of the SCL line. A second data
bytecan be read from the device if the microcontroller generates an acknowledge on the SDA line (masteracknowledge).
End of transmission will occur if no master acknowledge occurs. The device will then release the data line to allow the
microcontroller to generate a STOP condition.
Bit POR is set to logic 1 at power-on. The bit is reset when an end-of-data is detected by the device (end of a read
sequence). Control of the loop is made possible with bit FL which indicates when the loop is locked (bit FL = 1)
A built-in ADC input is available on pin LOCK/ADC (I2C-bus mode only). This converter can be used to apply AFC
information to the microcontroller of the IF section of the television.
EAD MODE
TDA6502; TDA6502A;
TDA6503; TDA6503A
Table 9 Read data format
NAMEBYTE
Address byteADB11000MA1MA0R/
Status byteSBPORFLR11A2A1A0
Note
1. MSB is transmitted first.
Table 10 Description of the bits used in Table 9
BITDESCRIPTION
MA1 and MA0programmable address bits (see Table 6)
R/
Wlogic1 for read mode
PORPower-on reset flag:
logic 0: at power-off
logic 1: at power-on
FLin-lock flag:
logic 0: loop is not locked
logic 1: loop is locked
Rready flag:
logic 0: mode after Power-on reset (bit T2 = 0, bit T1 = 0 and bit T0 = 1) and the PLL is locked
logic 1: in other conditions
A2, A1 and A0digital outputs of the 5-level ADC (see Table 11)
MSB
(1)
BIT
LSB
W=1
2000 Mar 1611
Page 12
Philips SemiconductorsPreliminary specification
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
Table 11 Digital outputs for analog input levels (note 1)
8.2.4POWER-ON RESET
The power-on detection threshold voltage V
reset to the power-on state.
At power-on state the following actions take place:
• The charge pump current is set to 280 µA
• The tuning voltage output is disabled
• The test bits T2, T1 and T0 are set to logic ‘001’
• The divider bit RSB is set to logic 1
• Port register UHF is ‘off’, which means that the UHF oscillator and the UHF mixer are switched off. Consequently, the
VHF oscillator and the VHFmixer areswitched on.Port registers VHFL and VHFH are ‘off’, which means that the VHF
tank circuit is operating in the VHF low sub-band. The tuning amplifier is switched off untilthe firsttransmission. Inthat
case, the tank circuit is supplied with the maximum tuning voltage. The oscillator is therefore operating at the end of
the VHF low sub-band.
CC
.
is set to 3.2 V at room temperature. Below this threshold the device is
POR
CC
TDA6502; TDA6502A;
TDA6503; TDA6503A
CC
CC
CC
CC
Table 12 Default setting of the bits at Power-on reset
NAMEBYTE
MSBLSB
Address byteADB11000MA1MA0X
Divider byte 1DB10XXXXXXX
Divider byte 2DB2XXXXXXXX
Control byteCB11001X11
Band switch byteBBXXXX0000
2000 Mar 1612
BITS
Page 13
Philips SemiconductorsPreliminary specification
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
8.33-wire bus data format
During a HIGH level on pin CE/AS (enable line), the data
is clocked into the data register at the HIGH-to-LOW
transition of the clock (see Figs 4 and 5).
The first four bits control the PMOS ports and are loaded
intothe internal band-switchregisteron the 5thrising edge
of the clock pulse.
The frequency bits are loaded into the frequency register
at the HIGH-to-LOW transition of the enable line when an
18-bit or 19-bit data word is transmitted. When a 27-bit
dataword is transmitted,thefrequency bits areloadedinto
the frequency register on the 20th rising edge of the clock
pulseand the controlbits at theHIGH-to-LOW transition of
the enable line (see Fig.6).
In this control mode the reference divider is given by
bits RSA and RSB (see Table 8).
The test bits T2, T1 and T0, the charge pump bit CP, the
ratio select bit RSB and bit OS can only be selected or
changed with a 27-bit transmission. They remain
programmed if an 18-bit or 19-bit transmission occurs.
Onlybit RSA is controlledbythe transmission lengthwhen
the 18-bit or 19-bit format is used. When an 18-bit data
word is transmitted, the most significant bit of the divider
(bit N14) is internally set to logic 0 and bit RSA is set to
logic 1. When a 19-bit data word is transmitted, bit RSA is
set to logic 0.
It is not allowed to address the devices with words whose
length is different from 18, 19 or 27 bits. A data word of
lessthan 18 bits willnot affect the frequencyregister of the
device.
TDA6502; TDA6502A;
TDA6503; TDA6503A
8.3.1POWER-ON RESET
The power-on detection threshold voltage V
3.2 Vatroom temperature. Below this threshold thedevice
is reset to the power-on state.
At power-on state the following actions take place:
• The charge pump current is set to 280 µA
• The test bits T2, T1 and T0 are set to logic ‘001’
• The divider bit RSB is set to logic 1
• The tuning voltage output is disabled
• The tuning amplifiercontrol bit OS isautomatically reset
to logic 0 in 18-bit and 19-bit modes when the first data
word is received to allow normal operation
• Port register UHF is ‘off’, which means that the UHF
oscillator and the UHF mixer are switched off.
Consequently,the VHF oscillatorandthe VHF mixerare
switched on. Port registers VHFL and VHFH are ‘off’,
which means that theVHF tank circuitis operating inthe
VHF low sub-band. The tuning amplifier is switched off
until the first transmission. In that case, the tank circuit
is supplied with the maximum tuning voltage.
The oscillator is therefore operating at the end of the
VHF low sub-band
• The reference divider ratio is set to 64 or 128 if the first
sequence to the device has 18 bits or 19 bits; if the
sequence has 27 bits, the reference divider ratio is set
by bits RSA and RSB (see Table 8).
POR
is set to
The definition of the bits is unchanged compared to the
I2C-bus mode.
2000 Mar 1613
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Philips SemiconductorsPreliminary specification
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
handbook, full pagewidth
DA
CL
CE
INVALID
DATA
BAND-SWITCH
DATA
FMST
PVHFL
PUHF
PVHFH
14518
LOAD BAND-SWITCH
N13 N12 N11 N10 N9N8 N7N6N5N4 N3N2N1N0
REGISTER
FREQUENCY
DATA
TDA6502; TDA6502A;
TDA6503; TDA6503A
INVALID
DATA
LOAD FREQUENCY
REGISTER
FCE572
handbook, full pagewidth
INVALID
DATA
DA
CL
CE
Fig.4 18-bit data format (bit RSA = 1).
BAND-SWITCH
DATA
FMST
PVHFL
PUHF
PVHFH
14519
LOAD BAND-SWITCH
REGISTER
N13N14N12 N11 N10 N9 N8N7 N6 N5 N4 N3 N2 N1N0
FREQUENCY
DATA
LOAD FREQUENCY
INVALID
DATA
REGISTER
FCE573
Fig.5 19-bit data format (bit RSA = 0).
2000 Mar 1614
Page 15
Philips SemiconductorsPreliminary specification
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
handbook, full pagewidth
DA
CL
CE
INVALID
DATA
BAND-SWITCH
DATA
FMST
PVHFL
PUHF
PVHFH
145272019
LOAD BAND-SWITCH
REGISTER
FREQUENCY
DATA
N13N14N12N2 N1 N0XCP T2T1T0 RSA RSB OS
LOAD FREQUENCY
REGISTER
TDA6502; TDA6502A;
TDA6503; TDA6503A
TEST AND FEATURES
DATA
LOAD CONTROL
REGISTER
INVALID
DATA
FCE574
Fig.6 27-bit data format; test and features mode.
2000 Mar 1615
Page 16
Philips SemiconductorsPreliminary specification
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
9LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); note 1.
PIN
SYMBOL
V
CC
V
Pn
I
Pn
V
CP
V
SW
V
VT
V
LOCK/ADC
V
CL
V
DA
I
DA
V
CE/AS
V
XTAL
I
O(n)
t
sc(max)
T
stg
T
amb
T
j
TDA6502;
TDA6502A
TDA6503;
TDA6503A
1910DC supply voltage−0.3+6V
OVSpulse time is 1 s; maximum current is
1 A
7 to 1019 to 22PMOS port output voltage−0.3VCC+0.3V
7 to 1019 to 22PMOS port output current−1+30mA
1613charge pump output voltage−0.3VCC+0.3V
1118bus format selection input voltage−0.3VCC+ 0.3V
1712tuning voltage output−0.3+35V
1514lock/ADC output/input voltage−0.3VCC+0.3V
1415serial clock input voltage−0.3+6V
1316serial data input/output voltage−0.3+6V
1316data output current (I2C-bus mode)−1+10mA
1217chip enable/address selection input
voltage
1811crystal input voltage−0.3VCC+0.3V
1to6,
19 to 28
1 to 10,
23 to 28
output current of each pin to ground−−10mA
−−maximumshort-circuit time (all pins to V
and all pins to GND, OSCGND and
RFGND)
−−storage temperature−40+150°C
−−ambient temperature−20+85°C
−−junction temperature−150°C
PARAMETERMIN.MAX.UNIT
TDA6502; TDA6502A;
TDA6503; TDA6503A
−8V
−0.3+6V
−10s
CC
Note
1. Maximum ratings can not be exceeded, not even momentarily without causing irreversible IC damage. Maximum
ratings can not be accumulated.
10 THERMAL CHARACTERISTICS
SYMBOLPARAMETERCONDITIONSTYP.UNIT
R
th(j-a)
thermal resistance from junction to ambient in free air110K/W
2000 Mar 1616
Page 17
Philips SemiconductorsPreliminary specification
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
TDA6502; TDA6502A;
TDA6503; TDA6503A
11 CHARACTERISTICS
SYMBOLPARAMETERCONDITIONSMIN.TYP.MAX.UNIT
Supply; T
V
CC
I
CC
=25oC
amb
supply voltage4.55.05.5V
supply currentat VCC=5V
all PMOS ports ‘off’−7178mA
one PMOS port ‘on’ and
−103113mA
sourcing 25 mA
one PMOS port ‘on’and sourcing
−111122mA
25 mA; a second port ‘on’ and
sourcing 5 mA
PLL part; V
F
UNCTIONAL RANGE
V
POR
= 4.5 to 5.5 V; T
CC
power-on reset supply
voltage
= −20 to +85 °C; unless otherwise specified
amb
below this supply voltage power-on
reset becomes active
−3.2−V
Ndivider ratio15-bit frequency word64−32767
14-bit frequency word64−16383
f
XTAL
Z
XTAL
crystal oscillator frequencyR
input impedance
=25to300Ω−4.0−MHz
XTAL
f
= 4 MHz6001200−Ω
XTAL
(absolute value)
PMOS PORTS: PINS PUHF, PVHFL, PVHFH AND FMST
I
Pn(off)
V
Pn(sat)
leakage currentVCC= 5.5 V; VPn=0V−10−−µA
output saturation voltageV
Pn(sat)=VCC
− VPn;
−0.250.4V
one buffer output is ‘on’ and
sourcing 25 mA
LOCK OUTPUT: PIN LOCK/ADC (IN 3-WIRE BUS MODE)
I
UNLOCK
output current when the PLL
VCC= 5.5 V; VO= 5.5 V−−200µA
is out-of-lock
V
UNLOCK
output saturation voltage
V
UNLOCK=VCC
− VO; IO= 200 µA−0.40.8V
when the PLL is out-of-lock
V
LOCK
output voltagethe PLL is locked−0.20.40V
ADC INPUT: PIN LOCK/ADC (IN I2C-BUS MODE)
V
ADC
I
ADC(H)
I
ADC(L)
ADC input voltagesee Table 110−V
HIGH-level input currentV
LOW-level input currentV
ADC=VCC
=0V−10−−µA
ADC
−−10µA
CC
V
BUS FORMAT SELECTION: PIN SW
V
SW(L)
V
SW(H)
I
SW(H)
I
SW(L)
LOW-level input voltage0−1.5V
HIGH-level input voltage3−V
HIGH-level input currentVSW=V
CC
−−10µA
CC
V
LOW-level input currentVSW=0V−100−−µA
2000 Mar 1617
Page 18
Philips SemiconductorsPreliminary specification
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
TDA6502; TDA6502A;
TDA6503; TDA6503A
SYMBOLPARAMETERCONDITIONSMIN.TYP.MAX.UNIT
CHIP ENABLE/ADDRESS SELECTION INPUT: PIN CE/AS
V
CE/AS(L)
V
CE/AS(H)
I
CE/AS(H)
I
CE/AS(L)
LOW-level input voltage0−1.5V
HIGH-level input voltage3−5.5V
HIGH-level input currentV
LOW-level input currentV
= 5.5 V−−10µA
CE/AS
=0V−10−−µA
CE/AS
CLOCK AND DATA INPUTS: PINS CL AND DA
V
CL(L)
V
DA(L)
V
CL(H)
V
DA(H)
I
CL(H)
I
CL(L)
,
,
, I
, I
LOW-level input voltage0−1.5V
HIGH-level input voltage3−5.5V
HIGH-level input currentV
DA(H)
LOW-level input currentV
DA(L)
= 5.5 V; VCC=0V−−10µA
BUS
V
= 5.5 V; VCC= 5.5 V−−10µA
BUS
= 1.5 V; VCC=0V−−10µA
BUS
V
=0V; VCC= 5.5 V−10−−µA
BUS
DATA OUTPUT: PIN DA (IN I2C-BUS MODE ONLY)
I
DA(H)
V
DA(H)
HIGH-level output currentVDA= 5.5 V−−10µA
HIGH-level output voltageIDA= 3 mA (sink current)−−0.4V
CLOCK FREQUENCY (I2C-BUS MODE)
f
off-state leakage currentT2 = 0; T1 = 1−15−0.5+15nA
TUNING VOLTAGE OUTPUT: PIN VT
I
VT(off)
leakage current when
OS = 1; tuning supply is 33 V−−10µA
switched-off
V
VT
output voltage when the loop
is closed
OS = 0; T2 = 0; T1 = 0; T0 = 1;
RL=27kΩ; tuning supply is 33 V
0.2−32.7V
Mixer/oscillator part; V
VHF
MIXER (INCLUDING IF PREAMPLIFIER)
f
RF(o)
f
RF
G
v
RF operational frequency40800MHz
RF frequencynote 155.25−361.25MHz
voltage gainfRF= 57.5 MHz; see Fig.1217.52022.5dB
=5V; T
CC
NFnoise figuref
=25oC; measurements related to the measurement circuit (see Fig.19)
amb
= 363.5 MHz; see Fig.1217.52022.5dB
f
RF
= 50 MHz; see Figs 13 and 14−7.510dB
RF
= 150 MHz; see Figs 13 and 14 −7.510dB
f
RF
f
= 300 MHz; see Fig.14−7.510dB
RF
2000 Mar 1618
Page 19
Philips SemiconductorsPreliminary specification
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
TDA6502; TDA6502A;
TDA6503; TDA6503A
SYMBOLPARAMETERCONDITIONSMIN.TYP.MAX.UNIT
V
o
V
i
output voltage (causing 1%
cross modulation in channel)
input voltage (causing
fRF= 55.25 MHz; see Fig.15107110−dBµV
f
= 361.25 MHz; see Fig.15107110−dBµV
RF
fRF= 361.25 MHz; note 2−83−dBµV
pulling-in channel at 750 Hz)
g
os
g
i
C
i
optimum source
conductance for noise figure
fRF=50MHz−0.7−mS
f
= 150 MHz−0.9−mS
RF
= 300 MHz−1.5−mS
f
RF
input conductancefRF= 55.25 MHz; see Fig.7−0.3−mS
f
= 361.25 MHz; see Fig.7−0.4−mS
RF
input capacitancefRF= 57.5 to 357.5 MHz; see Fig.7−1.35−pF
VHF OSCILLATOR
f
OSC(o)
oscillator operational
60600MHz
frequency
f
OSC
∆f
OSC(V)
∆f
OSC(T)
∆f
OSC(t)
Φ
OSC
RSCripple susceptibility of V
oscillator frequencynote 3101−407MHz
oscillator frequency variation
with supply voltage
oscillator frequency variation
with temperature
∆VCC= 5%; note 4−60−kHz
∆V
= 10%; note 4−110−kHz
CC
∆T=25°C; with compensation;
−1600−kHz
note 5
oscillator frequency drift5 s to 15 min after switch-on;note 6 −400−kHz
phasenoise, carrier-to-noise
sideband
(peak-to-peak value)
±100 kHz frequency offset; worst
case in the frequency range
VCC= 5 V; worst case in the
CC
frequency range; ripple frequency
−105−dBc/Hz
1530−mV
500 kHz; note 7
UHF MIXER (INCLUDING IF PREAMPLIFIER)
f
RF(o)
f
RF
G
v
NFnoise figure (not corrected
V
o
V
i
RF operational frequency200900MHz
RF frequencynote 1367.25 −801.25 MHz
voltage gainfRF= 369.5 MHz; see Fig.16293235dB
= 803.5 MHz; see Fig.16293235dB
f
RF
f
= 369.5 MHz; see Fig.17−79dB
RF
for image)
output voltage (causing 1%
cross modulation in channel)
input voltage (causing
f
= 803.5 MHz; see Fig.17−79dB
RF
fRF= 367.25 MHz; see Fig.18107110−dBµV
f
= 801.25 MHz; see Fig.18107110−dBµV
RF
fRF= 801.25 MHz; note 2−85−dBµV
pulling in channel at 750 Hz)
2000 Mar 1619
Page 20
Philips SemiconductorsPreliminary specification
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
TDA6502; TDA6502A;
TDA6503; TDA6503A
SYMBOLPARAMETERCONDITIONSMIN.TYP.MAX.UNIT
Z
i
input impedance (RS+jLSω)RS at fRF= 367.25 MHz; see Fig.8−26−Ω
R
at fRF= 801.25 MHz; see Fig.8−28−Ω
S
L
at fRF= 367.25 MHz; see Fig.8−8.5−nH
S
L
at fRF= 801.25 MHz; see Fig.8−8−nH
S
UHF OSCILLATOR
f
OSC(o)
oscillator operational
3001000MHz
frequency
f
OSC
∆f
OSC(V)
∆f
OSC(T)
∆f
OSC(t)
oscillator frequencynote 3413−847MHz
oscillator frequency variation
with supply voltage
oscillator frequency variation
with temperature
oscillator frequency drift5 s to 15 min after switching on;
∆VCC= 5%; note 4−35−kHz
= 10%; note 4−100−kHz
∆V
CC
∆T=25°C; with compensation;
−500−kHz
note 5
−120−kHz
note 6
Φ
OSC
RSCripple susceptibility of V
phasenoise, carrier-to-noise
sideband
CC
(peak-to-peak value)
±100 kHz frequency offset; worst
case in the frequency range
VCC= 5 V; worst case in the
frequency range; ripple frequency
−105−dBc/Hz
1530−mV
500 kHz; note 7
IF PREAMPLIFIER
IFIF operational frequency3060MHz
S
22
output reflection coefficientmagnitude; see Fig.9−−12.8−dB
phase; see Fig.9−0.2−degree
Z
o
output impedance
(RS+jLSω)
RS at 43.5 MHz; see Fig.9−80−Ω
L
at 43.5 MHz; see Fig.9−0.5−nH
S
REJECTION AT THE IF OUTPUT
INT
div
level of divider interferences
worst case; note 8−1620dBµV
in the IF signal
INT
INT
xtal
ref
crystal oscillator
interferences rejection
reference frequency
rejection
VIF= 100 dBµV; worst case in the
frequency range; note 9
VIF= 100 dBµV; worst case in the
frequency range; f
= 62.5 kHz;
REF
60−−dBc
60−−dBc
note 10
INT
ch6
channel 6 beatV
RF(pix)=VRF(snd)
=80dBµV;
tbf54−dBc
note 11
INT
chA-5
channel A-5 beatV
=80dBµV; note 12tbf60−dBc
RF(pix)
Notes
1. The RF frequency range is defined by the oscillator frequency range and the IF frequency.
2. This is the level of the RF signal (100% amplitude modulated with 11.89 kHz) that causes a 750 Hz frequency
deviation on the oscillator signal; it produces sidebands 30 dB below the level of the oscillator signal.
3. Limits are related to the tank circuits used in Fig.19; frequency bands may be adjusted by the choice of external
components.
2000 Mar 1620
Page 21
Philips SemiconductorsPreliminary specification
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
TDA6502; TDA6502A;
TDA6503; TDA6503A
4. The frequency shift is defined as a change in oscillator frequency when the supply voltage varies from
VCC= 5 to 4.75 V (4.5 V) or from VCC= 5 to 5.25 V (5.5 V). The oscillator is free running during this measurement.
5. The frequency drift is defined as a change in oscillator frequency when the ambient temperature varies from
T
=25to50°C or from T
amb
=25to0°C. The oscillator is free running during this measurement.
amb
6. Switch-on drift isdefined as thechange in oscillator frequency between5 s and 15 min after switch-on.The oscillator
is free running during this measurement.
7. The ripple susceptibility is measured for a 500 kHz ripple at the IF output using the measurement circuit of Fig.19;
the level ofthe ripplesignal is increased until a difference of53.5 dB occurs between the IF carrier fixed at100 dBµV
and the sideband components.
8. This is the level of divider interferences close to the IF frequency. For example channel C: f
1
⁄4f
= 44.75 MHz. The VHFIN input must be left open (i.e. not connected to any load or cable); The UHFIN1 and
OSC
= 179 MHz,
OSC
UHFIN2 inputs are connected to a hybrid.
9. Crystal oscillator interference means the 4 MHz sidebands caused by the crystal oscillator. The rejection has to be
greater than 60 dB for an IF output signal of 100 dBµV.
10. The reference frequency rejection is the level of reference frequency sidebands related to the sound sub-carrier.
11. Channel 6 beat is the interfering product of f
RF(pix)+fRF(snd)
12. Channel A-5 beat is the interfering product of f
The possible mechanisms are: f
− 2 × fIF or 2 × f
OSC
RF(pix), fIF
RF(pix)
and f
− f
− f
of channel 6 at 42 MHz.
OSC
of channel A-5: f
OSC
. For the measurement: VRF=80dBµV.
OSC
= 45.5 MHz.
beat
handbook, full pagewidth
1
2
5
10
∞
10
5
2
1
0.5
0.20.512510
400 MHz
0.5
40 MHz
FCE528
0.2
− j
0
+ j
0.2
Fig.7 Input admittance (S11) of the VHF mixer input (40 to 400 MHz); Y0= 20 mS.
2000 Mar 1621
Page 22
Philips SemiconductorsPreliminary specification
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
handbook, full pagewidth
0.5
0.2
350 MHz
+ j
0
− j
0.2
0.5
0.510.21052
1
860 MHz
TDA6502; TDA6502A;
TDA6503; TDA6503A
2
5
10
∞
10
5
2
handbook, full pagewidth
1
FCE529
Fig.8 Input impedance (S11) of the UHF mixer input (350 to 860 MHz); Z0=50Ω.
1
0.5
0.2
+ j
0
− j
0.2
0.510.21052
20 MHz
100 MHz
2
5
10
∞
10
5
0.5
1
Fig.9 Output impedance (S22) of the IF amplifier (20 to 60 MHz); Z0=50Ω.
2000 Mar 1622
2
FCE530
Page 23
Philips SemiconductorsPreliminary specification
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
TDA6502; TDA6502A;
TDA6503; TDA6503A
12 TIMING CHARACTERISTICS
SYMBOLPARAMETERCONDITIONSMIN.UNIT
3-wire bus timing
t
HIGH
t
SU;DA
t
HD;DA
t
SU;ENCL
t
HD;ENDA
t
EN
clock HIGH timesee Fig.102µs
data set-up timesee Fig.102µs
data hold timesee Fig.102µs
enable-to-clock set-up timesee Fig.1010µs
enable-to-data hold timesee Fig.102µs
enable time between two
see Fig.1110µs
transmissions
t
HD;ENCL
handbook, full pagewidth
enable-to-clock active edge hold time see Fig.116µs
DA
INVALID
DATA
MSB
LSB
INVALID
DATA
CL
t
HIGH
t
SU;DA
t
HD;DA
CE
t
SU;ENCL
Fig.10 Timing diagram for 3-wire bus; DA, CL and CE.
handbook, halfpage
CE
CL
t
t
HD;ENCL
EN
t
HD;ENDA
FCE576
FCE575
Fig.11 Timing diagram for 3-wire bus; CE and CL.
2000 Mar 1623
Page 24
Philips SemiconductorsPreliminary specification
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
13 TEST AND APPLICATION INFORMATION
13.1Test circuits
handbook, full pagewidth
Zi>> 50 Ω⇒Vi=2×V
Vi=V
V
G
=V’
o
= 20 log
v
meas
meas
+6dB=80dBµV
50 27+
×
-------------------
V
o
-----V
i
e
=80dBµV
meas
50
50 Ω
signal
source
V
meas
V
RMS
voltmeter
50 Ω
VHFIN
V
i
D.U.T.
IFOUT
TDA6502; TDA6502A;
TDA6503; TDA6503A
27 Ω
V
V'
o
meas
spectrum
analyzer
50 Ω
FCE577
Fig.12 Gain measurement in VHF band.
handbook, full pagewidth
(a) For fRF= 50 MHz:
mixer A frequency response measured = 57 MHz, loss = 0 dB
image suppression = 16 dB
C1 = 9 pF
C2 = 15 pF
L1 = 7 turns (∅ 5.5 mm, wire ∅ = 0.5 mm)
l1 = semi rigid cable (RIM) of 5 cm long
mixer A frequency response measured = 150.3 MHz, loss = 1.3 dB
image suppression = 13 dB
C3 = 5 pF
C4=25pF
l2 = semi rigid cable (RIM): 30 cm long
l3 = semi rigid cable (RIM) of 5 cm long
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
Table 19 Transistors
COMPONENTVALUE
TR1BC847B
TR2BC847B
13.3Tuning amplifier
The tuning amplifier is capable of driving the varicap
voltage without an external transistor. The tuning voltage
output must be connected to an external load of 27 kΩ
which is connected to the tuning voltage supply rail.
The loop filter design depends on the oscillator
characteristics and the selected reference frequency.
13.4Crystal oscillator
The crystal oscillator uses a 4 MHz crystal connected in
series with an 18 pF capacitor thereby operating in the
series resonance mode. Connecting the crystal to the
ground is preferred, but it can also be connected to the
supply voltage.
TDA6502; TDA6502A;
TDA6503; TDA6503A
2
13.5Examples of I
TDA6502 and TDA6503
Tables 20 to 24 show the various write sequences where:
S = START bit
A = acknowledge bit
P = STOP bit.
Conditions:
f
= 4 MHz
xtal
N = 1600
f
= 100 MHz
osc
f
= 62.5 kHz
step
Port register VHFL is ‘on’ to switch-on band VHF low
Port register FMST is ‘on’ to switch-on an FM sound trap
ICP= 280 µA.
C-bus data format sequences for
13.5.1WRITE SEQUENCES TO REGISTER C2
Table 20 Complete sequence with first the divider bytes (first data bit = 0)
START
SC2A06A40ACEA09AP
Table 21 Complete sequence with first the control and band-switch bytes (first data bit = 1)
START
S C2ACEA09A06A40AP
Table 22 Sequence with divider bytes only (first data bit = 0)
The reference divideris automaticallyset to 64 assuming that bit RSB has beenset to logic 1 at power-on. If bit RSBhas
been set to logic 0, in a previous 27-bit sequence, the reference divider will still be set at 80. In this event, the 18-bit
sequence has to be adapted to the 80 divider ratio.
The reference divider is automatically set to 128 assuming that bit RSB has been set to logic 1 at power-on. If bit RSB
has been set to logic 0 in a previous 27-bit sequence, the reference divider will still be set at 80. In this event, the 19-bit
sequence has to be adapted to the 80 divider ratio.
2000 Mar 1631
Page 32
Philips SemiconductorsPreliminary specification
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
13.6.327-BIT SEQUENCE
Conditions:
f
= 750 MHz
osc
Port register PUHF is ‘on’
Reference divider is set at 80
ICP=60µA
No test function.
Table 29 27-bit sequence
PORT BITS
14131211109876543210XCPT2T1T0RSARSBOS
100001110101001100010 001 00 0
To change the oscillator frequency to 600 MHz in 50 kHz steps a 19-bit sequence or an 18-bit sequence can be used.
The charge pump current remains at 60 µA.
Table 30 Changing frequency with a 19-bit sequence
FREQUENCY DATA BITSCONTROL DATA BITS
TDA6502; TDA6502A;
TDA6503; TDA6503A
PORT BITS
14131211109876543210
1000010111011100000
Table 31 Changing frequency with an 18-bit sequence
PORT BITS
131211109876543210
100010111011100000
FREQUENCY DATA BITS
FREQUENCY DATA BITS
2000 Mar 1632
Page 33
Philips SemiconductorsPreliminary specification
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
14 INTERNAL PIN CONFIGURATION
PIN
SYMBOL
TDA6502;
TDA6502A
TDA6503;
TDA6503A
UHFIN1128−1.0 V
UHFIN2227−1.0 V
VHFIN326−−
DC VOLTAGE
(AVERAGE VALUE)
VHFUHF
(2)
TDA6502; TDA6502A;
TDA6503; TDA6503A
EQUIVALENT CIRCUIT
1
(28)
3
(26)
(1)
2
(27)
FCE584
RFGND4250.0 V0.0 V
IFFIL15243.6 V3.6 V
IFFIL26233.6 V3.6 V
PVHFL722n.a. or 4.8 Vn.a.
PVHFH8214.8 V or n.a.n.a.
PUHF920n.a.4.8 V
FMST1019n.a. or 4.8 V n.a. or 4.8 V
(22)
(20)
FCE585
4
(25)
FCE586
65(23)(24)
FCE587
7
9
8
(21)
10
(19)
FCE588
2000 Mar 1633
Page 34
Philips SemiconductorsPreliminary specification
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
PIN
SYMBOL
TDA6502;
TDA6502A
TDA6503;
TDA6503A
SW11185.0 V5.0 V
CE/AS12171.25 V1.25 V
DC VOLTAGE
(AVERAGE VALUE)
VHFUHF
(2)
TDA6502; TDA6502A;
TDA6503; TDA6503A
EQUIVALENT CIRCUIT
11
(18)
FCE189
12
(17)
FCE191
(1)
DA1316−−
CL1415−−
LOCK/ADC15144.6 V4.6 V
13
(16)
FCE190
14
(15)
FCE192
15
(14)
2000 Mar 1634
FCE193
Page 35
Philips SemiconductorsPreliminary specification
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
PIN
SYMBOL
TDA6502;
TDA6502A
TDA6503;
TDA6503A
CP16131 V1V
VT1712V
DC VOLTAGE
(AVERAGE VALUE)
VHFUHF
VT
V
VT
(2)
TDA6502; TDA6502A;
TDA6503; TDA6503A
EQUIVALENT CIRCUIT
FCE194
(1)
16
(13)
17
(12)
XTAL18112.6 V2.6 V
V
CC
19105.0 V5.0 Vsupply voltage
IFOUT2092.1 V2.1 V
GND2180.0 V0.0 V
FCE591
FCE589
18
(11)
FCE590
20
(9)
21
(8)
FCE592
2000 Mar 1635
Page 36
Philips SemiconductorsPreliminary specification
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
PIN
SYMBOL
TDA6502;
TDA6502A
TDA6503;
TDA6503A
OSCGND2360.0 V0.0 V
VHFOSCIB2271.8 V−
VHFOSCOC2453.0 V−
DC VOLTAGE
(AVERAGE VALUE)
VHFUHF
(2)
TDA6502; TDA6502A;
TDA6503; TDA6503A
EQUIVALENT CIRCUIT
23
(6)
FCE593
22
(7)
(1)
24
(5)
FCE594
UHFOSCIB1254−1.9 V
UHFOSCOC1263−2.9 V
UHFOSCOC2272−2.9 V
UHFOSCIB2281−1.9 V
Notes
1. The pin numbers in parenthesis represent the TDA6503 and TDA6503A.
2. Measured in circuit of Fig.19.
(2)
27
(4)
(3)
26
25
28
(1)
FCE595
2000 Mar 1636
Page 37
Philips SemiconductorsPreliminary specification
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
15 PACKAGE OUTLINE
SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm
D
c
y
Z
2815
TDA6502; TDA6502A;
TDA6503; TDA6503A
SOT341-1
E
H
E
A
X
v M
A
pin 1 index
114
w M
b
e
DIMENSIONS (mm are the original dimensions)
mm
A
max.
2.0
0.21
0.05
1.80
1.65
0.25
b
p
cD
0.20
0.09
3
0.38
0.25
UNITA1A2A
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
p
02.55 mm
scale
(1)E(1)(1)
10.4
10.0
eHELLpQZywv θ
5.4
0.651.25
5.2
7.9
7.6
Q
A
2
A
1
detail X
1.03
0.9
0.63
0.7
(A )
L
p
L
0.130.10.2
A
3
θ
1.1
0.7
o
8
o
0
OUTLINE
VERSION
SOT341-1 MO-150
IEC JEDEC EIAJ
REFERENCES
2000 Mar 1637
EUROPEAN
PROJECTION
ISSUE DATE
95-02-04
99-12-27
Page 38
Philips SemiconductorsPreliminary specification
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
16 SOLDERING
16.1Introduction to soldering surface mount
packages
Thistext gives a very briefinsightto a complex technology.
A more in-depth account of soldering ICs can be found in
our
“Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface
mount IC packages.Wave soldering isnot always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
16.2Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuit boardbyscreen printing, stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating,soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
TDA6502; TDA6502A;
TDA6503; TDA6503A
If wave soldering is used the following conditions must be
observed for optimal results:
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
• Forpackageswith leads on foursides,thefootprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement andbefore soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
16.3Wave soldering
Conventional single wave soldering is not recommended
forsurfacemount devices (SMDs) orprinted-circuitboards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
2000 Mar 1638
16.4Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
Page 39
Philips SemiconductorsPreliminary specification
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
16.5Suitability of surface mount IC packages for wave and reflow soldering methods
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
5. Wave soldering is only suitable for SSOP and TSSOP packageswith a pitch (e) equal to or larger than 0.65 mm; it is
, SO, SOJsuitablesuitable
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
The package footprint must incorporate solder thieves downstream and at the side corners.
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
17 DEFINITIONS
Data sheet status
Objective specificationThis data sheet contains target or goal specifications for product development.
Preliminary specificationThis data sheet contains preliminary data; supplementary data may be published later.
Product specificationThis data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
18 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
TDA6502; TDA6502A;
TDA6503; TDA6503A
19 PURCHASE OF PHILIPS I
Purchase of Philips I
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2
C COMPONENTS
2
C components conveys a license under the Philips’ I2C patent to use the
2000 Mar 1640
Page 41
Philips SemiconductorsPreliminary specification
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
NOTES
TDA6502; TDA6502A;
TDA6503; TDA6503A
2000 Mar 1641
Page 42
Philips SemiconductorsPreliminary specification
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
NOTES
TDA6502; TDA6502A;
TDA6503; TDA6503A
2000 Mar 1642
Page 43
Philips SemiconductorsPreliminary specification
5 V mixers/oscillators and synthesizers for
cable TV and VCR 2-band tuners
NOTES
TDA6502; TDA6502A;
TDA6503; TDA6503A
2000 Mar 1643
Page 44
Philips Semiconductors – a w orldwide compan y
Argentina: see South America
Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,
Indonesia: PTPhilips Development Corporation, SemiconductorsDivision,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 3341 299, Fax.+381 11 3342 553
For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
2000
Internet: http://www.semiconductors.philips.com
69
Printed in The Netherlands753504/02/pp44 Date of release: 2000 Mar 16Document order number: 9397 750 06924
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