The SuperM ESH™ s eries is obtained through an
extreme optimi za tio n of ST’s well established stripbased PowerMESH™ layout. In addition to pushing
on-resistance significantly down, spec ial care is taken to ensure a very good dv/dt capability fo r the
most demanding applications. Such series com plements ST full range of high voltage MOSF ETs including revolutionary MDmesh™ products.
3
2
TO-220
1
TO-220FP
1
INTERNAL SCHEMATIC DIAGRAM
3
2
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ IDEAL FOR OFF-LINE POWER SUPPLIES,
ADAPTORS AND PFC
ORDERING INFORMATION
SALES TYPEMARKINGPACKAGEPACKAGING
STP9NK65ZP9NK65ZTO-220TUBE
STP9NK65ZFPP9NK65ZFPTO-220FPTUBE
July 2003
1/7
Page 2
STP9NK65 - ST P9NK 65ZFP
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
STP9NK65ZSTP9NK65ZFP
V
DS
V
DGR
V
GS
I
D
I
D
IDM()
P
TOT
V
ESD(G-S)
dv/dt (1)Peak Diode Recovery voltage slopeTBDV/ns
V
ISO
T
j
T
stg
() Pulse width limited by safe operating area
(1) I
≤TBD, di/dt ≤TBD, VDD≤ V
SD
(*) Limited only by maximum temperature allowed
Drain-source Voltage (VGS=0)
Drain-gate Voltage (RGS=20kΩ)
650V
650V
Gate- source Voltage± 30V
Drain Current (continuous) at TC= 25°C
Drain Current (continuous) at TC= 100°C
77 (*)A
4.44.4 (*)A
Drain Current (pulsed)2828 (*)A
Total Dissipation at TC= 25°C
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
E
AS
Single Pulse Avalanche Energy
(starting T
max)
j
= 25 °C, ID=IAR,VDD=50V)
j
7A
TBDmJ
GATE-SOURCE ZENER DIODE
SymbolParameterTest ConditionsMin.Typ.Max.Unit
BV
GSO
Gate-Source Breakdown
Igs=± 1mA (Open Drain)30V
Voltage
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIOD ES
The built-in bac k-to-back Zener diodes have specif ically been designed to enhance not only the device’s
ESD capability, but also to make them s a fely absorb possible voltage transients that may occasionally be
applied from gate tosouce. In this respect the Zener voltage is appropriateto achieve an efficient and costeffective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage
of external components.
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use o f suc h inf ormat ion n or f or an y infr ingeme nt of paten ts or oth er ri gh ts of third part ies whic h may resul t f rom
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.