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1/9May 2000
STP9NB50
STP9NB50FP
N-CHANNEL 500V - 0.75 Ω - 8.6 A TO-220/TO-220FP
PowerMesh™ MOSFET
■ TYPICAL R
DS
(on) = 0.75 Ω
■ EXTREMELY HIGH dv/dt CAPABILITY
■ 100% AVALANCHE TESTED
■ VERY LOW INTRINSIC CAPACITANCES
■ GATE CHARGE MINIMIZED
DESCRIPTION
Using the latest high voltage MESH OVERLAY™
process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding
performances. The new patent pending strip layout
coupled with the Company’s proprieraty edge termination structure, gives the lowest R
DS(on)
per area,
exceptional avalanche and dv/dt capabilities and
unrivalled gate charge and switching characteristics.
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ SWITH MODE POWER SUPPLIES (SMPS)
■ DC-AC CONVERTERS FOR WELDING
EQUIPMENT AND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVE
ABSOLUTE MAXIMUM RATINGS
(•)Pulse width limited by safe operating area
TYPE V
DSS
R
DS(on)
I
D
STP9NB50 500 V < 0.85
Ω
8.6 A
STP9NB50FP 500 V < 0.85
Ω
4.9 A
Symbol Parameter Value Unit
STP9NB50 STP9NB50FP
V
DS
Drain-source Voltage (VGS = 0)
500 V
V
DGR
Drain-gate Voltage (RGS = 20 kΩ)
500 V
V
GS
Gate- source Voltage ±30 V
I
D
Drain Current (continuos) at TC = 25°C
8.6 4.9 A
I
D
Drain Current (continuos) at TC = 100°C
5.4 3.1 A
I
DM
(●)
Drain Current (pulsed) 34.4 34.4 A
P
TOT
Total Dissipation at TC = 25°C
125 40 W
Derating Factor 1 0.32 W/°C
dv/dt (1) Peak Diode Recovery voltage slope 4.5 4.5 V/ns
V
ISO
Insulation Withstand Voltage (DC) - 2000 V
T
stg
Storage Temperature –65 to 150 °C
T
j
Max. Operating Junction Temperature 150 °C
(1)ISD<9A, di/dt<200A/µ, VDD<V
(BR)DSS
,TJ<T
JMAX
INTERNAL SCHEMATIC DIAGRAM
1
2
3
1
2
3
TO-220
TO-220FP
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STP9NB50/FP
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THERMAL DATA
AVALANCHE CHARACTERISTICS
ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)
OFF
ON
(1)
DYNAMIC
TO-220 TO-220FP
Rthj-case Thermal Resistance Junction-case Max 1 3.13 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W
Rthc-sink Thermal Resistance Case-sink Typ 0.5 °C/W
T
l
Maximum Lead Temperature For Soldering Purpose 300 °C
Symbol Parameter Max Value Unit
I
AR
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
j
max)
8.6 A
E
AS
Single Pulse Avalanche Energy
(starting T
j
= 25 °C, ID = IAR, VDD = 50 V)
520 mJ
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
Drain-source
Breakdown Voltage
I
D
= 250 µA, VGS = 0
500 V
I
DSS
Zero Gate Voltage
Drain Current (V
GS
= 0)
V
DS
= Max Rating
1 µA
V
DS
= Max Rating, TC = 125 °C
50 µA
I
GSS
Gate-body Leakage
Current (V
DS
= 0)
V
GS
= ±30V
±100 nA
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
GS(th)
Gate Threshold Voltage
V
DS
= VGS, ID = 250 µA
3 4 5 V
R
DS(on)
Static Drain-source On
Resistance
V
GS
= 10V, ID = 4.3 A
0.75 0.85
Ω
I
D(on)
On State Drain Current
V
DS
> I
D(on)
x R
DS(on)max,
VGS= 10V
8.6 A
Symbol Parameter Test Conditions Min. Typ. Max. Unit
g
fs
(1)
Forward Transconductance
V
DS
> I
D(on)
x R
DS(on)max,
ID= 4.3 A
5.7 S
C
iss
Input Capacitance
V
DS
= 25V, f = 1 MHz, VGS = 0
1250 pF
C
oss
Output Capacitance 175 pF
C
rss
Reverse Transfer
Capacitance
20 pF
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STP9NB50/FP
ELECTRICAL CHARACTERISTICS (CONTINUED)
SWITCHING ON
SWITCHING OFF
SOURCE DRAIN DIODE
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
2. Pulse width limited by safe operating area.
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(on)
Turn-on Delay Time
Rise Time
V
DD
= 250 V, ID = 4.3 A
R
G
= 4.7Ω VGS = 10 V
(see test circuit, Figure 3)
19 ns
t
r
11 ns
Q
g
Total Gate Charge
V
DD
= 400V, ID = 8.6 A,
V
GS
= 10V
32 45 nC
Q
gs
Gate-Source Charge 10.6 nC
Q
gd
Gate-Drain Charge 13.7 nC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
r(Voff)
Off-voltage Rise Time
V
DD
= 400V, ID = 8.6 A,
R
G
= 4.7Ω, V
GS
= 10V
(see test circuit, Figure 5)
11.5 ns
t
f
Fall Time 11 ns
t
c
Cross-over Time 20 ns
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
Source-drain Current 8.6 A
I
SDM
(2)
Source-drain Current (pulsed) 34.4 A
V
SD
(1)
Forward On Voltage
ISD = 8.6 A, VGS = 0
1.6 V
t
rr
Reverse Recovery Time
I
SD
= 8.6 A, di/dt = 100A/µs,
V
DD
= 100V, Tj = 150°C
(see test circuit, Figure 5)
420 ns
Q
rr
Reverse Recovery Charge 3.5 µC
I
RRM
Reverse Recovery Current 16.5 A
Safe Operating Area Safe Operating Area for TO-220FP
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STP9NB50/FP
4/9
Static Drain-source On Resistance
Thermal Impedence for TO-220
Output Characteristics
Thermal Impedence for TO-220FP
Transfer Characteristics
Transconductance
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5/9
STP9NB50/FP
Source-drain Diode Forward Characteristics
Capacitance Variations
Normalized On Resistance vs Temperature
Normalized Gate Threshold Voltage vs Temp.
Gate Charge vs Gate-source Voltage
Page 6
STP9NB50/FP
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Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
Fig. 4: Gate Charge test Circuit
Fig. 2: Unclamped Inductive WaveformFig. 1: Unclamped Inductive Load Test Circuit
Fig. 3: Switching Times Test Circuit For
Resistive Load
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7/9
STP9NB50/FP
DIM.
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.40 4.60 0.173 0.181
C 1.23 1.32 0.048 0.051
D 2.40 2.72 0.094 0.107
D1 1.27 0.050
E 0.49 0.70 0.019 0.027
F 0.61 0.88 0.024 0.034
F1 1.14 1.70 0.044 0.067
F2 1.14 1.70 0.044 0.067
G 4.95 5.15 0.194 0.203
G1 2.4 2.7 0.094 0.106
H2 10.0 10.40 0.393 0.409
L2 16.4 0.645
L4 13.0 14.0 0.511 0.551
L5 2.65 2.95 0.104 0.116
L6 15.25 15.75 0.600 0.620
L7 6.2 6.6 0.244 0.260
L9 3.5 3.93 0.137 0.154
DIA. 3.75 3.85 0.147 0.151
L6
A
C
D
E
D1
F
G
L7
L2
Dia.
F1
L5
L4
H2
L9
F2
G1
TO-220 MECHANICAL DATA
P011C
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8/9
STP9NB50/FP
DIM.
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.4 4.6 0.173 0.181
B 2.5 2.7 0.098 0.106
D 2.5 2.75 0.098 0.108
E 0.45 0.7 0.017 0.027
F 0.75 1 0.030 0.039
F1 1.15 1.7 0.045 0.067
F2 1.15 1.7 0.045 0.067
G 4.95 5.2 0.195 0.204
G1 2.4 2.7 0.094 0.106
H 10 10.4 0.393 0.409
L2 16 0.630
L3 28.6 30.6 1.126 1.204
L4 9.8 10.6 0.385 0.417
L6 15.9 16.4 0.626 0.645
L7 9 9.3 0.354 0.366
Ø 3 3.2 0.118 0.126
L2
A
B
D
E
H
G
L6
¯
F
L3
G1
1 2 3
F2
F1
L7
L4
TO-220FP MECHANICAL DATA
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STP9NB50/FP
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infring ement of patents or other rights of third parties which m ay resu lt from its use. N o license is
granted by implicatio n or otherwise under any patent or patent rights of STM icroelectronics. Specification mentioned in this publicatio n are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support device s or systems without expres s written approval of STMicroelectronics.
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