Page 1
1/9March 2003
STB95NF03
N-CHANNEL 30V - 0.0065 Ω - 95A D²PAK
STripFET™ II POWER MOSFET
■ TYPICAL R
DS
(on) = 0.0065 Ω
■ STANDARD THRESHOLD DRIVE
■ 100% AVALANCHE TESTED
■ SURFACE-MOUNTING D
2
PAK (TO-263)
POWER PACKAG E IN TU BE (NO SU FFIX) OR
IN TAPE & REEL (SUFFIX “T4”)
DESCRIPTION
This Power MOSFET is the latest dev elo pment of
STMicroelectronis unique "Single Feature Size™"
strip-based process. The resulting transistor
shows extremely high packing density for low onresistance, rugged avalanche characteristics and
less critical alignment steps therefore a remarkable manufacturing reproducibility.
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ DC-DC & DC-AC CONVERTERS
■ SOLENOID AND RELAY DRIVERS
TYPE
V
DSS
R
DS(on)
I
D
STB95NF03 30 V <0.007
Ω
80 A
1
3
D2PAK
TO-263
(Suffix “T4”)
ABSOLUTE MAXIMUM RATINGS
(
•)
Pulse width limited by safe operating area.
(*) Curren t Lim i ted by Pack age
(1) ISD ≤ 95A, di/dt ≤ 150A/µs, VDD ≤ V
(BR)DSS
, Tj ≤ T
JMAX.
(2) Starting Tj = 25 oC, ID = 47.5A, VDD = 25V
Symbol Parameter Value Unit
V
DS
Drain-source Voltage (VGS = 0)
30 V
V
DGR
Drain-gate Voltage (RGS = 20 kΩ)
30 V
V
GS
Gate- source Voltage ± 20 V
I
D
(
∗
)
Drain Current (continuous) at T
C
= 25°C
80 A
I
D
Drain Current (continuous) at TC = 100°C
80 A
I
DM
(
•)
Drain Current (pulsed) 320 A
P
tot
Total Dissipation at TC = 25°C
150 W
Derating Factor 1 W/°C
dv/dt
(1)
Peak Diode Recovery voltage slope 3.0 V/ns
E
AS
(2)
Single Pulse Avalanche Energy 720 mJ
T
stg
Storage Temperature
-55 to 175 °C
T
j
Operating Junction Temperature
INTERNAL SCHEMATIC DIAGRAM
Page 2
STB95NF03
2/9
THERMA L D ATA
ELECTRICAL CHARACTERISTICS (T
case
= 25 °C unless otherwise specified)
OFF
ON
(*)
DYNAMIC
Rthj-case
Rthj-amb
T
l
Thermal Resistance Junction-case
Thermal Resistance Junction-ambient
Maximum Lead Temperature For Soldering Purpose
Max
Max
1
62.5
300
°C/W
°C/W
°C
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
Drain-source
Breakdown Voltage
I
D
= 250 µA VGS = 0
30 V
I
DSS
Zero Gate Voltage
Drain Current (V
GS
= 0)
V
DS
= Max Rating
V
DS
= Max Rating TC = 125°C
1
10
µA
µA
I
GSS
Gate-body Leakage
Current (V
DS
= 0)
V
GS
= ± 20 V
±100 nA
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
ID = 250 µA
24V
R
DS(on)
Static Drain-source On
Resistance
V
GS
= 10 V ID = 45 A
0.0065 0.0070
Ω
Symbol Parameter Test Conditions Min. Typ. Max. Unit
g
fs
(*)
Forward Transconductance
V
DS
= 15 V ID =45 A
50 S
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
V
DS
= 25V f = 1 MHz VGS = 0
2450
880
170
pF
pF
pF
Page 3
3/9
STB95NF03
SWITCHING ON
(*)
SWITCHING OFF
(*)
SOURCE DRAIN DIODE
(*)
(*)
Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
(
•)
Pulse width l i m i ted by T
jmax
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(on)
t
r
Turn-on Time
Rise Time
V
DD
= 15 V ID = 47.5 A
R
G
= 4.7
Ω
VGS = 10 V
20
195
ns
ns
Q
g
Q
gs
Q
gd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DD
=15V ID=95A VGS=10V
59
18
21
70 nC
nC
nC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(off)
t
f
Turn-off Delay Time
Fall Time
V
DD
= 20 V ID = 47.5 A
R
G
= 4.7Ω, V
GS
= 10 V
35
35
ns
ns
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
(
•)
Source-drain Current
Source-drain Current (pulsed)
95
320
A
A
V
SD
(*)
Forward On Voltage
I
SD
= 95 A VGS = 0
1.3 V
t
rr
Q
rr
I
RRM
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
SD
= 95 A di/dt = 100A/µs
V
DD
= 20 V Tj = 150°C
(see test circuit, Figure 5)
60
120
4
ns
nC
A
Thermal Impedance
ELECTRICAL CHARACTERISTICS (continued)
Safe Operating Area
Page 4
STB95NF03
4/9
Output Characteristics Transfer Characteristics
Transconductance Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage Capacitance Variations
Page 5
5/9
STB95NF03
. .
Normalized Gate Threshold Voltage vs Temperature Normalized on Resistance vs Temperature
Source-drain Diode Forward Characteristics Normalized Breakdown Voltage vs Temperature.
. .
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STB95NF03
6/9
Fig. 1: Unclamped Inductive Load Test CircuitFig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For Resistive
Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
Page 7
7/9
STB95NF03
DIM.
mm. inch.
MIN. TYP. MAX. MIN. TYP. TYP.
A 4.4 4.6 0.173 0.181
A1 2.49 2.69 0.098
0.106
A2 0.03 0.23 0.001 0.009
B 0.7 0.93 0.028 0.037
B2 1.14 1.7 0.045 0.067
C 0.45 0.6 0.018 0.024
C2 1.21 1.36 0.048 0.054
D 8.95 9.35 0.352 0.368
D1 8 0.315
E 10 10.4 0.394 0.409
E1 8.5 0.334
G 4.88 5.28 0.192 0.208
L 15 15.85 0.591 0.624
L2 1.27 1.4 0.050 0.055
L3 1.4 1.75 0.055 0.069
M 2.4 3.2 0.094 0.126
R 0.4 0.015
V2 0° 8° 0° 8°
D2PAK MECHANICAL DATA
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STB95NF03
8/9
DIM.
mm inch
MIN. MAX. MIN. MAX.
A0 10.5 10.7 0.413 0.421
B0 15.7 15.9 0.618 0.626
D 1.5 1.6 0.059 0.063
D1 1.59 1.61 0.062 0.063
E 1.65 1.85 0.065 0.073
F 11.4 11.6 0.449 0.456
K0 4.8 5.0 0.189 0.197
P0 3.9 4.1 0.153 0.161
P1 11.9 12.1 0.468 0.476
P2 1.9 2.1 0075 0.082
R50 1.574
T0.25 0.35 .0.0098 0.0137
W 23.7 24.3 0.933 0.956
DIM.
mm inch
MIN. MAX. MIN. MAX.
A 330 12.992
B 1.5 0.059
C 12.8 13.2 0.504 0.520
D 20.2 0.795
G 24.4 26.4 0.960 1.039
N 100 3.937
T 30.4 1.197
BASE QTY BULK QTY
1000 1000
REEL MECHANICAL DATA
* on sales type
TUBE SHIPMENT (no suffix)*
TAPE AND REEL SHIPMENT (suffix ”T4”)*
D2PAK FOOTPRINT
TAPE MECHANICAL DATA
Page 9
9/9
STB95NF03
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
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authorized for use as cri tical comp onents in lif e support devi ces or systems without express written approva l of STMicroe l ectronics.
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