Datasheet STLC1512 Datasheet (SGS Thomson Microelectronics)

■

Low power architecture -- Class AB, current
drive, output stage through a centre tapped
transformer to facilitate power supply switching
between 5.0V and a lower voltage. (3.3V in the
reference design) This gives a reduction in
power consumption.

■

480mW power consumption with a typical G.lite
signal.

■

600mA current driving capability

■

Positive +5.0V and one lower supply. (3.3V in
the reference design)

■

Switching power supplies to save power

■

Thermal overload shutdown

■

Four programmable receive gains

■

Opamp for a low pass filter in the receive path

■

Undedicated opamp with separate power down
control (used as a transmit path filter in the
reference design)

■

Separate power down control for Tx and Rx
path

■

48-pin TQFP (7x7x1.4mm) package

STLC1512

NorthenLite™ G.lite Loop Driver

PRODUCT PREVIEW

TQFP48 (7x7x1.40)

ORDERING NUM BER: STLC 1512

1.0 GENERAL DESCRIPTION

The STLC1512 G.lite line driver chip contai ns the l ine
driver as well as part of the receive path required i n a
central office G.lite modem. It provides an interface
between the AFE chip (STLC1511) and the tele­phone line. The line driver chip has been designed
with low power consumption, high signal to noise
plus distortion ratio and high current driving capabili­ty.

Figure 1. Block Diagram

DCFBON

PAIN

DCFBOP

AMPIN

TX REF

Buffer

RX REF

Buffer

LPF AMP

OPAMP

Thermal

Shutdown

BIAS

AMPIP

AMPOUT

PAI P

TXANG

RBIAS

REF2P5

RXANG

LPFIN

LPFOUT

November 2000

This is preliminary information on a new product now in development. Details are subject to change without notice.

Feedback

Preamp

PGA

DC

Amp

Power

Stage

DCFBIP

DCFBIN
FPP

PWRVEE x

PAOPx
BUFFP
BUFFN

FPN

PAON x

RXPD
AMPPD
TXPD

PGAIN
PGA1

PGA0
PGAOUT

1/26

STLC1512

1.0 GENERAL DESCRIPTION

The line driver transmit path contains a preamplifier
followed by a power output stage. The power stage
has current outputs that directly drive the primary
side of a center tapped transformer.

The receive path contains a programmable gain am­plifier followed by an opamp which is used with off
chip passive components in an active low pass filter.
The Programmable Grain Amplifier (PGA) has four
steps optimized for the recommended G.lite CO line
interface.

There is also an undedicated opamp which can be
used for active filtering in either the transmit or re-

Figure 2. STLC1512 pinout

AMPIP

AMPIN

AMPOUT

TXVCC3

TXVCC2

DCFBON

ceive paths

2.0 PACKAGING AND PIN INFORMATION

2.1 Package Technology

STLC1512 will be packaged in a TQFP 48 package,
according to JEDEC Specification reference MS­026-BBC.

2.2 STLC1512 Pin Allocation

The pin out for the STLC1512 is depicted in the fol­lowing Figure 2.

TXVCC1

TXVEE1

TXVEE2

TXVEE3

QVEETX

DCFBIP

DCFBIN

NC

DCFBOP

TXANG

FPP

FPN
PAIP
PAIN

RBIAS

REF2P5

NC

LPFOUT

LPFIN

48

PWRVEE1
PWRVEE2

PAOP1
PAOP2
BUFFP

TQFP48 (7x7x1.4mm)

BUFFN
PAON1

PAON2
PWRVEE3

PWRVEE4

1

PGAIN

RXANG

RXVCC1

PGAOUT

RXVCC2

RXVEE1

QVEERX

PGA0

RXVEE2

PGA1

TXPD

AMPPD

RXPD

2/26

2.3 Pin Description

The pin description for the STLC1512 is given in the following Table 1.

Table 1. Pin Description

STLC1512

Pin # Pin Name Pin Type

1 PGAOUT AO Rx PGA output (programmable gain amplifier)
2 PGAIN AI Rx PGA input
3 RXANG AO 2.5V Rx buffered reference
4 RXVCC1 VCC +5.0V supply for Rx path circuitry
5 RXVCC2 VCC +5.0V supply for Rx path circuitry
6 QVEERX VEE Quiet ground for the Rx circuitry
7 RXVEE1 VEE Ground for Rx path circuitry
8 RXVEE2 VEE Ground for Rx path circuitry
9 PGA0 DI PGA gain setting control bit 0
10 PGA1 DI PGA gain setting control bit 1
11 TXPD DI Tx path power down control (Active low)
12

13 RXPD DI Rx path power down control (Active low)
14 PWRVEE4 VEE Power stage ground.
15 PWRVEE3 VEE Power stage ground.
16 PAON2 AO Tx Power Amplifier Negative output

AMPPD

2

DI Undedicated opamp power down control (Active low)

Pin Description

1

17 PAON1 AO Tx Power Amplifier Negative output
18 BUFFN AO Current generator buffer negative output
19 BUFFP AO Current generator buffer positive output
20 PAOP2 AO Tx Power Amplifier Positive output
21 PAOP1 AO Tx Power Amplifier Positive output
22 PWRVEE2 VEE Power stage ground.
23 PWRVEE1 VEE Power stage ground.
24 NC Not connected
25 DCFBIN AI Power amp DC feedback amplifier negative input
26 DCFBIP AI Power amp DC feedback amplifier positive input
27 QVEETX VEE Quiet ground for Tx circuitry
28 TXVEE3 VEE Ground for Tx path circuitry
29 TXVEE2 VEE Ground for Tx path circuitry
30 TXVEE1 VEE Ground for Tx path circuitry
31 TXVCC1 VCC +5.0V supply for power amp output stage

3/26

STLC1512

Table 1. Pin Description

32 TXVCC2 VCC +5.0V supply for power amp output stage
33 TXVCC3 VCC +5.0V supply for Tx path circuitry and bias blocks
34 AMPOUT AO Undedicated opamp output
35 AMPIN AI Undedicated opamp negative input
36 AMPIP AI Undedicated opamp positive input
37 DCFBON AO Power amp DC feedback amplifier negative output
38 DCFBOP AO Power amp DC feedback amplifier positive output
39 TXANG AO 2.5V Tx buffered reference
40 FPP AO Fast path positive output
41 FPN AO Fast path negative output
42 PAIP AI Tx Power amplifier positive input
43 PAIN AI Tx Power amplifier negative input
44 RBIAS AO Reference resistor generating bias current
45 REF2P5 AI Externally supplied 2.5V reference
46 NC Not connected
47 LPFOUT AO LPF (low pass filter) Op Amp output
48 LPFIN AI LPF (low pass filter) Op Amp negative input

<1>The values of the components that are conne ct ed to the pins a re shown in Figure 11.
<2>If the undedicated opamp is used in the transmit path, AMPPD can be connected to TXPD on the board. If the undedicated opamp

is used in t he receive pat h, AMPPD can be connected to RXPD on the board. This opamp is powered of f of TXVCC3.

3.0 FUNCTIONAL DESCRIPTION

The STLC1512 consists of the following functional
blocks:

■

Transmit Signal Path

■

Receive Signal Path

■

Thermal Protection

The transmit signal that comes from the AFE is fil­tered before it reaches the line driver. STLC1512
contains an opamp that can be utilized as part of this
filter. The AMPPD pin allows this op amp to be pow­ered down independently. The line driver consists of
a preamp followed by a current drive power stage.
The preamplifier provides large open loop gain while
the power stage provides open collec tor current drive
to allow for single supply sw itchi ng. The center tap of
the primary side of the transformer is connected to a
supply that can be switched between 5.0V and a low­er supply to realize power savings on a DMT signal.
The reference design sets this supply at 3.3V. The
line driver can be powered down by a low at the
TXPD pin.

The receive path consists of a Programmable Gain
Amplifier (PGA) and an active low pass filter. The
PGA is programmable in four steps. The active low
pass filter is composed of an on chip op amp and ex­ternal passive components. The receive signa l pass­es through the PGA, is low pass filtered and then
driven off chip to the AFE chip. Both the PGA and the
opamp can be powered down by RXPD signal.

A thermal protection circuit has als o been implement­ed on the chip to prevent the chip from overheating
under fault conditions.

4.0 SPECIFICATIONS

4.1 Chip Specifications

The cross-talk specifications are based on the as­sumption that cross-talk should not degrade the
SNDR of the receive signal. If there is receive cross­talk into the transmit path, this signal will come back
through the hybrid balance and cause noi se in the re­ceive path. If the signal is undistorted it will cause a
small gain and phase error which will not affect per­formance. If it is distorted it will cause an increased

4/26

STLC1512

noise floor which will degrade the SNDR of the re­ceive signal.

The same is true of the transmit signal. If the signal is
undistorted it will show up out of band in the receive
path and will not degrade SNDR. However, if the

Table 2. Chip Performance Specifications

Description min nom max Units Comments

Rx Cross-Talk into Tx
Undistorted

Rx Cross-Talk into Tx
Distorted

Tx Cross-talk into Rx
Undistorted

Tx Cross-talk into Rx
Distorted

-55 dB Measured from the active low pass filter

-73 dB Measured from the active low pass filter

-50 dB Measured from tip and ring to the active

-86 dB Measured from tip and ring to the active

4.2 Pow er A mpl ifi e r P erf or m a nce
Specifications

The power amplifier must be specified with all of the
external components in the application diagram.
Without these components the ampli fier wi ll not func­tion correctly. S pecifications th at are measured at the
chip are specified as such in the comments.

transmit signal is distorted by the cross-talk mecha­nism it will show up in the receive band and could re­duce the SNDR.

The cross-talk numbers are specified from output to
output under maximum gain conditions.

output in the receive path to tip and ring.

output in the receive path to tip and ring.

low pass filter output with the maximum
gain setting in place.

low pass filter output with the maximum
gain setting in place.

Table 3 contains the conditions over which the spec­ifications in Table 4 apply . The limits on the speci fica­tions in Table are valid over all of the ranges
specified in Table 3. The nominal values of the spec­ification occur at the nom inal v alue of all of the condi­tions in Table 3 unless otherwise specified.

...

Table 3. Power A m pl i fier P erf ormance Limi t s

Description min nom max Units

Gain 19.9 20.1 20.3 dB

Ambient Temperature -40 27 85

Line Impedance 80 100 160 W A nominal chip will have no problem

Supply voltage for TXVCC 4.75 5.0 5.25 V

<1>Nomi nal specifica tions are for n om i nal bias and pr ocess
<2>Maxim um and minimum specificat i ons are for worst case proc ess and bias co nditions

o

C

driving 200 Ω or 50 Ω.

Comments

1,2

5/26

STLC1512

Table 4. Power Amplifier Performance Specifications

Unless otherwise specified nom specs apply to the nom conditions in attribute and the max and min conditions are
defined by the process and other spec limits that give these worst case corners.

Description min nom max Goal Units Comments
Quiescent current at PAOP/

1

PAON

Total quiescent current at
output stage

Input bias current

2

3

Minimum Voltage at PAOP/

4

PAON
High Current Drive

Minimum Voltage at PAOP/

5

PAON
Low Current Drive

Common mode input
voltage range

6

Peak output sink
current on pin PAOP and

7

PAON

10 15 18 mA The spec is measured as the

sum of the currents at
POAP1+PAOP2 or
PAON1+PAON2.

20 30 36 mA Measured at the center tap of

the transformer.

15 µA Measured at pin PAIP/PAIN.

This parameter cannot be
measured very accurately.

0.85 Vpeak Measured at pin PAOP1,2/
PAON1,2

0.70 Vpeak Measured at pin PAOP1,2/
PAON1,2

1.6 VCC-

V Measured at pin PAIP/PAIN

0.5

600 1000 mA This is the sum of the current

from PAOP1 and PAOP2 or
the sum of the currents from
PAON1 and PAON2

Power supply rejection See Figure 3.

Slew Rate

8

Output referred noise

9

voltage

Signal to distortion ratio
Two tone A

10

Im2 @ 200 kHz
Im3 @ 100 kHz
Two tone B<Superscript>10
Im3 @ 550 kHz

Output DS Multi-tone

11

28kHz < f < 121kHz
151kHz < f < 541kHz

35 V/µS Measured across the 100

Ohm line impedance

78 120 nV/÷√Hz measured at f=120kHz

Simulated to be good from
30kHz to 540kHz.

Measured at the line
impedance. The 4 to 1

78
78

86
86

dB
dB

transformer must have total
harmonic distortion better
than 50dB over 30kHz < f <

59

59

dB

550kHz.
The multi-tone spec is the

78
59

85
66

86
59

dB
dB

important spec. The two tone
specs exist because the test
equipment may not be able to
create a good enough multi­tone input signal.

6/26

Table 4. Power Amplifier Performance Specifications

STLC1512

e

------------------------- -log=

n

2

100

o

C

x 1000

Only the power amplifier is
shut down under overheat
condition

Thermal shutdown junction
temperature

<1> The quiescent current is th e current flo wi ng into pin PAOP/PAON when there is no signal.
<2> This is the cu rrent drawn from the power supply that is connected to the center tap on the primary side of the transforme r.
<3> This is the cu rrent flowing into the pin PAIN or PAI P when there is no signal. The nature of the test set up m akes this qua n tity

<4> This will allow the distortion specs to be met while driving a 160W line impedance. This applies for a 550mA output current. The
<5> This spec is meant as an aid in calculating the proper switching poi nt. It appli es for a 225mA ou tput current.

<6> This is a requirement on the input signal that allows the distortion spec to be met. It is not a testable parameter. The range has
<7> The minim um sink current refers to peak signal current in normal operation. This is tested by placing a 80 W lo ad as th e l i n e

<8> Slew Rate spec is to guarantee that there is no slewing limit on a ma xi m um amplitude sine wave at 540kHz. A 100 mV ste p is
<9> Measured ac ross the 100 Ohm l i ne impedanc e. This noise spec can be converted to dB/Hz through the followin g formula,

<10> Two tone dis torti on is measur ed w ith tw o sin e wave s wi th eac h sine wa ve at an amp litu de of 1/2 f ull scal e (fo r sig nal g ain of

<11> A multi-tone sine wave is used for the DS (Down Stream) Multi-tone test. (The multi-tone signal will be 91 sine waves equally

<12> The thermal shut down can not be directly tested in pr oduction. It will b e investigated at bench and a correlation will be done

12

very difficult to measure. It is verified through simulation.
worst case impedance f or a nominal chi p i s 200 W.

been arrive d at from simu l ations.
impedance and ensuring that the amplifier still passes the distortion tests. The maximum sink current refers to the current that

will be delivered if tip and ring are shorted. A nominal chip can drive a 50W load while a worst case chip will drive 80W.
placed at the power amp input and the slew rate at the output of the amplifier is measured across the 100 Ohm load impedance.

The effect of the noise in the receive path can be obtained by subtracting the hybrid balance number.

20.1dB, the full scale signal at power amplifier input is 1.05 Vp). The two tone distortion requirement is measured from the rms
voltage of a single signal tone to the rms voltage of the distortion product. For the Two Tone A spec the tones are at f1=500KHz
and f2=300KH z gi ving Im2=20 0kHz and Im3=100 kHz. For the Two tone B the to nes are at f1= 500kHz and f2=450kHz so that
Im3=550kHz.

spaced from 35x4.3125kHz to 125x4.3125kHz with a peak-to-rms voltage ratio of 5.3 and an rms voltage equal to 208mV. Each
tone will have a peak amplitude of 30.8mV) The multi-tone test measures the difference between the power of the test tones
and the maximum power of a s i ngl e distortion product in the given bands .

hermal shut down temperature.

130 150 175

N

dB

10

7/26

STLC1512

)

Figure 3. Powe r Su ppl y Re j ect io n of t he P ower Amplifie r

WDB (PAOUT

-40

-60

dB

-80

1

-100

3.00e+04 1 .00e+ 05

6.00e+05

Hz

<1>This is a nominal specification. 6 dB of margi n should be added to arrive at a worst case spec.

4.3 Programmable Gain Ampl ifier (PGA) Performanc e Specification s

It should be noted that the PGA and LPF in the receive path must be AC coupled to avoid problems with ampli­fying any offsets.

Both the PGA and the amplifiers are specified in terms of the silicon only. This is to allow the system design to
be more flexible. The appendices show how to convert some of the silicon specs to system specs.

Table 5. PGA performance Specifications

Unless otherwise specified, NOM specifications apply for VCC=5.0V, temperature range outlined in Table 4.4,
nominal process and bias current. MAX and MIN performances with 5% variation on VCC, -40 <= T

and worst case process and bias current and a minimum load of 440 W.

DESCRIPTION MIN NOM MAX UNITS COMMENTS

Absolute Voltage Gain
D=00
D=01
D=10
D=11

1,2

11.4

1.4

-5.6

-19.8

11.8

1.8

-5.2

-19.2

12.2

2.2

-4.8

-18.8

dB
dB
dB
dB

Where ‘D’ is the binary value
of the control word
[PGA1, PGA0]
Gain settings are from the pin
PGAIN to pin PGAOUT (See
‘application diagram’)

ambient

<=85oC,

8/26

Table 5. PGA performance Specifications

STLC1512

Relative Gain Accuracy

2,3

11.8<--> 1.8dB step

1.8<--> -5.2 dB step

-5.2 <--> -19.2 dB step

Gain Variation with
Temperature<Superscript>2

erscript>3,

Gain Variation with Supply
Voltage<Superscript>2

pt>3,

,<Superscri

,<Sup

-0.15

-0.17

-0.2

0
0
0

0.15

0.17

0.2

dB
dB
dB

-0.1 0 0.1 dB For a fixed Vcc and frequency

-0.1 0 0.1 dB For a fixed frequency (30kHz

Assume a fixed Vcc,
temperature, and frequency

(30kHz <=f<=120kHz) relative

o

to 27

<=f<=120kHz) and fixed
temperature relative to
Vcc=5.0V

Gain Variation with
Frequency

For a fixed Vcc and
temperature relative to 30kHz

30KHz <= f <= 120Khz -0.1 -0.001 dB

Signal to Distortion Ratio Measured at pin PGAOUT for

a minimum load impedance of

D=00
Two tone

4

IM2 @ 200kHz
IM3 @ 100kHz

Output DS Multi-tone Echo
30kHz<=f<=120kHz

D=01
Two tone

4

IM2 @ 200kHz
IM3 @ 100kHz

Output DS Multi-tone Echo
30kHz<=f<=120kHz

86
86

5

86

80
80

5

80

dB
dB

dB

dB
dB

dB

440 Ohm and maximum
output signal of 1.1Vp. The
important test is the multi tone
test. The two tone specs exist
because there may be a
problem testing a multi tone
wave. They will be correlated
at bench.

D=10
Two tone

4

IM2 @ 200kHz
IM3 @ 100kHz

Output DS Multi-tone Echo
30kHz<=f<=120kHz

D=11
Two tone

4

IM2 @ 200kHz
IM3 @ 100kHz

Output DS Multi-tone Echo
30kHz<=f<=120kHz

Input Referred Noise Voltage
at D=00
at D=01
at D=10
at D=11

76
76

5

76

76
76

5

76

6

dB
dB

dB

dB
dB

dB

Measured at PGAOUT and
referred to PGAIN.

5.8

11.6

22.5
95

7.5
15
30
133

nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz

Te sted at
f=30kHz,120kHz,150kHz and
500kHz

9/26

STLC1512

Table 5. PGA performance Specifications

Input Impedance (over
process)

7,8

Input Impedance (over
temperature)

7,9

Input Impedance (over process
and temperature)

7,10

Input Signal Level @ PGAIN 0 V

Maximum Output Signal Level @
PGAOUT

Power

11

12

<1> The absolut e gain test sh oul d be done at 30k Hz, 75kHz and 120kHz wi th maximum out put si gnal level of 1.1Vp.
<2> The calculation to show how to deter m i ne the gain from the l i ne is give n i n Appendix A. This appendix also shows how to cal

culate the gai n variations in the appli cation
<3> These are chi p specs only. T he applicati on specs are cal culated in Ap pendix A.
<4> Two tone d i st ortion is m easured with two sin e waves ha ving an ampli t ude given i n 6. Tone one is at f1= 500kHz and tone two

is at f2=300kHz, IM2 ap pears at 200kHz and IM3 a ppears ar 100k Hz.
<5> A multi-tone sine wave is used for the DS (Down Stream) Multi-tone test. (The multi-tone signal will be 91 sine waves equally

spaced fro m 35x4.3125kHz to 125x4.3125kHz with a pe ak-to-rms ratio of 5.3 and an rms voltage given in Table 6. T he multi-

tone tes t measures the differen ce betwe en the r m s voltage of a single tone at t he output to t he rms voltage of the maximum

distortion product at the output in the frequency band betwe en 30kHz to 120kHz.
<6> This is the noise referred to the PGA input pin PGAIN. The input noise can be referenced to tip and ring in dBm/Hz through the

formula,

where NdB i s the line noi se in dBm/Hz, Vn is the i nput referred voltage noise of the PGA, H is the hybrid loss (9.54d B) and G

is the gain from the hybrid output to the in put of the PGA. See Appendi x A for calculation of G. Ap pendix B show s pl ots of the

noise performance of th e entire receive path as shown in Figure 9.
<7> These numbers are required to determine the gain variations in the appli cation.
<8> The input impedance specified here i s the nomina l value and the va ri ation is due onl y to processing.
<9> The input impedance specified here is the nominal value and the variation is due only to temperature. This variation is specified

from the no m i nal value at 27°C.
<10> The input impedance specified here i s the nomina l value with the v ari ation due to both process and temperature.
<11> This spec is g uaranteed by the distorti on test.
<12> This power c an not be verif ied independently. It ca n only be meas ured as part of th e power from the RXVCC su ppl y.

4.0 5 6.0 kΩ Measure at pin PGAIN. For all
PGA gains

-10% 10% kΩ Measure at pin PGAIN. For all
PGA gains

3.5 5 6.5 kΩ Measure at pin PGAIN. For all
PGA gains

+0.1 V Single ended input

cc

1.1 Vpeak Referenced to RXANG. For
minimum load impedance of
440 Ohms.

19 mW Active Power

2

100



N

dB

------------ -

10

log G H++=



1000

V

n

Table 6. Multi-tone sine waves

Gain Setting 2 Tone Amplitudes Multi-tone RMS

00 173 mV 66 mV 9.78 mV
01 550 mV 207 mV 30.7 mV

10 1.125 V 414 mV 61.4 mV

11 1.125 V 414 mV 61.4 mV

10/26

Multi-Tone

Amplitudes

STLC1512

Figure 4. Powe r Su ppl y Re j ect io n of t he P GA

1

dB

<1>These curves repr esent typical performance. 6dB of margin is required for worst case.

4.4 Amplifier Performance Specification

The two amplifiers on the STLC1512 are identical. One of them is used for the second order active low pass
filter that follows the PGA in the rec eive path. The oth er is an undedi cated opamp that c an be used ei ther in the
transmit or receive paths.
The LPF amplifier is powered from the RXVCC supply and is therefore intended to be used in the receive path.
It has its positive terminal tied to the receive AC ground (RXANG) on chip.
The undedicated op amp is powered from TXVCC. It is intended for use in the transmit path but could be used
in the receive path. Using it in the receive path may cause receive noise to be coupled into the transmit path.
There should not be an issue with transmit noise coupling into the receive path in either configuration.

11/26

STLC1512

Table 7. Amplifier Performance Specifications.

Unless otherwise specified, NOM specifications apply for VCC=5V, temperature range outlined in Table 3, nominal
process and bias current. MAX and MIN performances with 5% variation on VCC, -40 <= T

worst case process and bias current

PARAMETER MIN NOM MAX UNITS COMMENTS

Input Offset Voltage 5 mV

Unity Gain Bandwidth 30 50 MHz

Phase Margin 50 degrees
Gain Margin 9 dB

DC open loop gain 80 dB
Slew Rate 25 V / us

<=115oC, and

junction

Signal to Distortion
Ratio in negative unity

1

gain
Two Tone A

2

IM2 @ 200 kHz
IM3 @ 100 kHz

Two Tone B

3

IM3 @ 550 kHz

Output DS Multi-tone
30kHz<=f<=120kHz
150kHz<=f<=550kHz

Signal to Distortion
Ratio in positive unity
gain. Undedicated

opamp only.
Two Tone A

1,5

2

IM2
IM3

Two Tone B

3

IM3
Output DS Multi-tone

30kHz<=f<=120kHz
150kHz<=f<=550kHz

Input referred voltage
noise

Maximum output signal
level=1.1Vp

89
89

dB
dB

The two tone B spec only

59

dB

applies to the undedicated
opamp

4

89
59

dB
dB

Maximum output signal
level=1.1Vp

78
78

59

4

78
59

dB
dB

dB
dB

dB

3.5 5 nV/√Hz

Input referred current

2pA/√Hz

noise

<1>The multi tone spec is the spec which defines system performance. The two tone spec is available because it may not be possible

to create an adequat e m ul ti-tone signal with the test hard ware.

<2>Two t one A d istortio n is m easure d with t wo si ne wave s with e ach s ine wa ve at a n ampli tude o f 1/2 ful l scal e. Tone one is at

f1=500 kH z and tone two i s at f2=300kHz.

<3>Two t one B d istortio n is m easure d with t wo si ne wave s with e ach s ine wa ve at a n ampli tude o f 1/2 ful l scal e. Tone one is at

f1=500 kH z and tone two i s at f2=450kHz.

12/26

<4>A multi-tone sine wave is used for the DS (Down Stream) Multi-tone test. (The multi-tone signal will be 91 sine waves equally

)

spaced from 35x4.3125kHz to 125x4.3125kHz with a peak-to-rms ratio of 5.3, an rms voltage equal to 207mV and a tone amplitude
of 30.7mV.) The multi-tone test measures the difference between the rms voltage of a single tone at the output to the rms voltage
of the maxi m um distortion product at t he output in the band of interest.

<5>The undedicated op amp specs are available in two configurations since it is undetermined which way the opamp will be used in

the application. Th e di st ortion spec s for the 2 conf ig urations are very different.

Figure 5. Circuit Co nnection for Me as uring Distor t ion

R

R

-

STLC1512

-

Vin

+

Nega tive Unity Gain Positive Unity Gain

Figure 6. Powe r Supply R ejecti on of the A m plifier

VDB (AMPOUTX

10

0

-20

dB

Vin

+

1

-40

-60

-80

1e+02

<1>This curve is a nomi nal simulation. 6 dB of margin should be added for worst case.

Hz

1e+081e+05

13/26

STLC1512

4.5 Supply Rating and Operating Environment

4.5.1 Environm e nt C onditions

Table 8. Environment conditions

PARAMETER UNITS CONDITIONS

Ambient Temperature Range (long-term) -40 to +80

Ambient Temperature Range (Shor t-ter m )

<1>Short- term is defi ned as no great er t han 96 consec utive hours and 15 days per y ear

1

-40 to +85 °C

o

C

4.5.2 Maximum and Minimum Voltage Ratings

Table 9. Maximum and Minimum Voltage Ratings

PINS Maximum Minimum

All Vcc pins 6.5V -0.5V

All other pins Vcc+0.4V -0.4V

4.5.3 Power Supplies

Table 10. Power Supply

V/I (PIN NAMES) Description MIN N OM MAX UNIT COMM ENTS

V(TXVCC1..2) Supply voltage for

Power Stage

V(TXVCC3) Supply voltage for TX

Path

V(RXVCC1..2) Supply voltage for RX

path
V(PWRVEE1..4) Ground for PA 0 V
V(TXVEE1..3)) Ground for Tx path 0 V
V(RXVEE1..2)) Ground for Rx path 0 V
P(TXVCC1..2) Current drawn by

TXVCC1..2
P(TXVCC1..2) Current drawn by

TXVCC1..2
P(TXVCC3) Current drawn by

TXVCC3

P(TXVCC3) Current drawn by

TXVCC3

4.75 5.0 5.25 V

4.75 5.0 5.25 V

4.75 5.0 5.25 V

36.6 mArms While passing a
full scale signal.

12.8 15.6 mArms Quiescent Current

12 mArms While passing a

full scale
signal.<Superscri
pt>1

7.5 9.2 mArms Quiescent Current

1

14/26

Table 10. Power Supply

STLC1512

P(RXVCC1..2) Current drawn by

RXVCC

P(RXVCC1..2) Current drawn by

RXVCC

P(PAON/PAOP) Current supplied

through the center
tap of the
transformer.

P(PAON/PAOP) Current supplied

through the center
tap of the
transformer.

<1>The nom i nal power is al l tha t is available for the activ e power because the power i s very dependent on the line i m pedance.

6.6 8.4 mArms Quiescent Current

20 36 mArms Quiescent Current

8.6 mArms While passing a
full scale
signal.<Superscri
pt>1

93 mA rms RMS wh il e dri vi ng

a DMT
signal.<Superscri
pt>1

4.5.4 Power Suppl y N oi se

Table 11. Power Supply Noise

Noise Band

30kHz<f<120kHz 0.2uVrms/√Hz

150kHz<f<540kHz 0.1uVrms/√Hz

Maximum RXVCC Supply Noise

Spectral Density

decade for decreasing frequency

decade for decreasing frequency

@ 120kHz, rising 20dB per

@540kHz, rising 20dB per

Maximum TXVCC Supply Noise Spectral

Density

10uVrms/√Hz@120kH,following 10dB per
decade for decreasing frequency to
3uVrms/√Hz

1uVrms/√Hz@540kHz, rising 20dB per
decade for decreasing frequency to
7uVrms/√Hz

@ 30kHz

@150kHz

4.5.5 References

Table 12. References

PIN NAMES D escri ption M IN NOM MAX UNIT COMMENTS

RBIAS External resistance

REF2P5 External reference

I(REF2P5) Current supplied to

TXANG/
RXANG

for bias current
generation

voltage for AC
Ground.

REF2P5
Tx and Rx AC ground

current sinking
capability

12.3 12.4 12.5 KΩ To create 200uA

2.425 2.5 2.575 V External reference

3.75uA 8.25uA V

REF2P5*

0.97

REF2P5 REF2P5*

1.03

V 1mA source/sink

bias current.

voltage must be
3% accurate

15/26

STLC1512

4.6 Digital Interface Logic Level

Table 13. De fin iti on of Logic Levels for Digita l Control Input P in s

SYMBOL DESCRIPTION MIN NOM MAX UNITS COMMENTS

VIL Input low voltage 0.8 V Signal from STLC1510

VIH Input high voltage 2.0 V Signal from STLC1510

4.7 ESD and Latch Up

Table 14. ESD and Latch up

Parameter Co nditions Min Obj Max Unit

Electrostatic Discharge
Latchup current 100 200 mA

<1>Test assumes standard Human body ESD mod el . Industry standard requ i rem ent is 1kV .

1

12 kV

5.0 APPLICATION DIAGRAM

To reduce the power consump tion of the power ampl ifier, the two output po wer transistors of the power amplifier
are powered by a switching power supply at the center tap of the transformer. (See Figure 7.) The switching is
controlled by the digital chip (STLC1510) that senses the future signal level.

The stability and offset of the power amplifier are optimized with the feedback scheme and the component val­ues shown in this applic ation diagram. A s such, the appl ication of the STLC1512 has to follow the topology and
component values in the diagram to avoid stability and offset problems.

16/26

Figure 7. Application Diagram

STLC1512

17/26

STLC1512

Appendix A - PGA Gain Calculations

The application requires some drop from the output of the hybrid balance to the input of the PGA in order to
keep the signal level at an acceptable level. (see Table 5) The input is reduced by placing a resistor between
the output of the hybrid balance network and PGAIN. This resistor (R
a resistor divider between the hybrid balance and the input. Second, it allows a capacitor to be placed across
the input of the PGA to create a first order low pass filter. This further reduces the signal in long loop cases.

The resistor divider is formed by the external resistor and the input impedance of the PGA. The gain from the
hybrid balance to the output of the PGA is therefore given by

R



input

----------------------------------

log G

20



R



+

inputRext

+

) serves two purposes. First, it creates

ext

table

where G
R

input

R

is the resistance placed between the hybrid balance and PGAIN.

ext

is the gain number given in Table ,

table

is the input impedance of the PGA given in Table

Equation can also be used to determine variations over process and temperature. To accomplish this just de­termine the max and min values using the input resistance variation given in Table .

To convert the noise numbers in Table to line referred noise numbers use

100

2

++=

V

n

Where N
V

is the input referred noise from Table ,

n

is the noise on the line in dBm/Hz,

db

1000



N

dB

10

------------ -

log G H



H is the hybrid loss (9.54dB in the reference design),
and G is given by

+

R



inputRext

=

G20

----------------------------------

log



R



input

18/26

STLC1512

Appendix B - Rx Path Noise Perfo rmance

The following plots show the noise performance of the receive path as it is shown in Figure 7. They show the
effects of different gain settings as well as typical and worst case performance of the receiver. These noise num­bers are referred to the line.

Figure 8. Noise for Various Gain Settings

19/26

STLC1512

Appendix C - Transmit Path Noise Performance

The following plots show the noise performance of the transmit path as it is connected in Figure 7.

Figure 9. Transmit Filter Noise Performance at he Filter Output (nV/

√Hz

)

20/26

STLC1512

Figure 10. Power Amp Noise Performance at the Line (nV/

√Hz)

21/26

STLC1512

Figure 11. Total Transmit Path Noise Performance at the Line (nV/

√Hz

)

22/26

STLC1512

Appendix D - Headroom Calculation for Swi t ching

The headroom for switching can be determined from the numbers in Table 4. The switching headroom is 0.70
V at low currents ( i.e. while on the l ow s upply rai l) and 0.85 V at high currents (i.e. w hile on the high supply rail) .
The most difficult number to arrive at is the voltage that will appear at the pins PAOP1,2 and PAON1,2. This is
a combination of the input voltage, the line impedance and the losses in the transformers.
For a 100Ω load the maximum signal on the line will be 10.7 V. Since we are generating an active 100Ω output
impedance the voltage on the line for any other load is given by:

Z



o

V

line

=

()

2 10.7

---------------------- -



+

100 Z



o

(EQ D.1)

where Zo is the line impedance and V

is the voltage on the line.

line

There are various losses in the transformers that can be modeled as resistors. To calculate the effect of these
losses we must know the current through the load which is given by:

V

line

I

load

------------=

Z

o

(EQ D.2)

The loss through the line transformer can be modeled as a 2.6Ω resistor. There is also a drop across the two
10Ω reference resistors. Therefore to determine the voltage at the output of the switched transformer we have:

V

swtxout

V

line

+=

20 2.6

I

load

(EQ D.3)

+()

At this poi nt ther e is some ad diti onal cur re nt that flows through the hybr id bala nce ne twork. This cur rent f lows th rough
a resistance that is equivalent to 1270

Ω

. Therefore the current flowing out of the switched transformer is:

V

swtxou t

I

swtxoutIload

----------------------+=

1270

(EQ D.4)

The switched transformer has losses that can be modeled as a 3.6Ω resistor and has a 4:1 turns ratio. Therefore
the voltage at the primary side of the transformer is given by:

V

swtxout

---------------------------------------------------------------=

Where V

V

PAOx

is the voltage at the output pins of the power amp. This is essentially the amount of headroom

PAOx

required to drive a full scale signal into the desired line impedance (Z

()+

3.6 I

swtxout

4

(EQ D.5)

). Equation D.1 to Equation D.5 can be

o

combined to calculate the required headroom to drive a certain impedance.

++

20 2.6

Z

o



--------------------------------- -1+



1270

+

100

o

(EQ D.6)

V

PAOx



++ +

Z

20 2.6 3.6

o

V



n

------

-------------------------------------------------------------------------------------------------- -

=



2



Z



Where V

is the required headroom to drive Vn volts out onto a line with the impedance Zo. This equation

PAOx

can be rearranged to calculate the s witc hing threshold . Th e headroom can be d etermined fr om the drop ac ross
the diode from the low supply and the low current drive capability of the amplifier given in Table (0.70V).

––=

0.70 V

headroom

diode

(EQ D.7)

is the headroom available on the low supply

Where V
and V

supplymin

is the voltage dr op across the diode when it has the appropriate amount of current flowing through it.

diode

Substituting V

V

headroom

V

supplymin

is the minimum value for the lower supply, V

headroom

in for V

in Equation D.7 you c an determine the allowabl e outpu t v oltage Vn. This can

PAOx

be scaled to the nominal value of 10.7V (full scale) to determine a switching threshold based on the full scale
level of the signal.
The headroom calculation is worst at maximum line impedance. There is also a supply rail requirement for the
high (5.0V) suppl y which is based on being able to supply enough cur rent to drive an 80 Ω line impedance. This
is not a trivial calculation and has been based on simulations . The possibility exists that the requirements on the
minimum supply voltage may be able to be reduced in the future.

23/26

STLC1512

Appendix E - Board Issues for Heat Dissipation

The internal temperature of the device must remain below 125oC. There are a number of ways to ensure that
this happens.

There are various combinations of maximum ambient temperature and board issues that can contribute to the
junction temperature of the devices on the chip. Different la yout techniques can be used to enhance the thermal
coefficient of the package. The following conditions must be true to ensure reliable operation of the line driver.

<

125

o

C

(EQ E.1)

()+

Where T

is the maximum ambient temperature that will be experienced by the device, Rj is the thermal

ambient

coefficient as described below and P

T

ambientRjPD

is the power dissipation of the chip which is 480mW.

D

The thermal coefficient is determined by the board layout characteristics and the rate that air is being forced
across the board. The board layout is defined in 2 ways. One is a 2 layer board with signal layers on the top and
bottom. The signal layer has a heat spreading copper plane that spreads from the corner pins of the chip. There
are also thermal vias dir ectl y under the chi p. The second l ayout is an 8 layer boar d with si gnal layer s on the top
an bottom, 4 copper lattice planes (80% 1 ounce copper) and 2 copper ground planes (solid 1 ounce copper).
This layout also has a heat spreading copper plane on the signal layer and thermal vias under the die and in the
copper plane.

The thermal coefficients for these two different boards are given in Table 15. These coefficients are modified
based on the amount of air flow over the board..

Table 15. Thermal Coefficients for Different Board Conditions

No Air Flow

R

Board Type

2 Layer 87.2 75.6 63.6 59.4

8 Layer 54.7 50.6 48.0 46.1

j

o

C/W)

(

R

1m/s Air Flow

j

o

C/W)

(

R

3m/s Air Flow

j

o

C/W)

(

R

5m/s Air Flow

j

o

(

C/W)

24/26

6.0 MECHANICAL SPECIFICATIONS

The STLC1512 is packaged in a 48 pin 7x7x1.4mm Lowprofile Quad Flat Pack (LQFP) package.

STLC1512

DIM.

MIN. TYP. MAX. MIN. TYP. MAX.

A 1.60 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057

B 0.17 0.22 0.27 0.006 0.008 0.010

C 0.09 0.20 0.004 0.008

D 9.00 0.354
D1 7.00 0.276
D3 5.50 0.217

e 0.50 0.020

E 9.00 0.354
E1 7.00 0.276
E3 5.50 0.217

L 0.45 0.60 0.75 0.018 0.024 0.030

L1 1.00 0.039

K 0°(min.), 3.5˚(typ.), 7°(max.)

mm inch

OUTLINE AND

MECHANICAL DATA

Body: 7 x 7 x 1.40mm

TQFP48

25/26

STLC1512

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or otherwise under any patent or p at ent rights of STMicroelectronics. Spec i fications mentioned i n this publication are subject
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authorized for use as cri t i cal compone nts in life support device s or systems without express written approval of STMicroel ectronics.

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26/26