Datasheet STL6NK55Z Datasheet (SGS Thomson Microelectronics)

STL6NK55Z

N-CHANNEL 550V - 1.2Ω - 5.2A PowerFLAT™

Zener-Protected SuperMESH™Power MOSFET

TYPE V

STL6NK55Z 550 V < 1.4 Ω 5.2 A 75 W

■ TYPICAL R

■ EXTREMELY HIGH dv /d t C APABILITY

■ IMPROVED ESD CAPABILITY

■ 100% AVALANCHE RATED

■ GATE CHARGE MINIMIZED

■ VERY LOW INTRINSIC CAPAC ITANCES

■ VERY GOOD MANUFACTURING

(on) = 1.2 Ω

DS

DSS

R

DS(on)ID

(1)

Pw (1)

REPEATIBILITY

DESCRIPTION

The SuperMESH™ series is obtained through an
extreme optimization of ST ’s well established strip­based PowerMESH™ layout. In addition to pushing
on-resistance significantly down, special care is tak­en to ensure a very good dv/dt capability for the
most demanding applications. Such series c om pl e­ments ST full range of high voltage MOSFE Ts in­cluding revolutionary MDmesh™ products.

PowerFLAT™(5x5)

(Chip Scale Package)

INTERNAL SCHEMATIC DIAGRAM

APPLICATIONS

■ LIGHTING

■ IDEAL F OR OFF-LINE POWER SUPP L IES,

ADAPTORS AND PFC

ORDERING INFORMATION

SALES TYPE MARKING PACKAGE PACKAGING

STL6NK55Z L6NK55Z PowerFLAT™ (5x5) TAPE & REEL

1/8July 2002

STL6NK55Z

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V

DS

V

DGR

V

GS

I

(2) Drain Current (continuous) at TC = 25°C (Steady State)

D

I

DM

P

TOT

P

TOT

V

ESD(G-S)

dv/dt (4) Peak Diode Recovery voltage slope 4.5 V/ns

T

stg

T

THERMA L D ATA

Symbol Parameter Max. Unit

Rthj-F Thermal Resistance Junction-Foot (Drain) 1.67 °C/W

Rthj-amb (2) Thermal Resistance Junction-ambient 50 °C/W

Note: 1. The va l u e i s ra t ed according to R

2. When M ounted on FR-4 Board of 1i nch

3. Pulse wi dth limited by safe operating area

4. I

Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)

550 V
550 V

Gate- source Voltage ± 30 V

0.86

Drain Current (continuous) at TC = 100°C

(2)

Drain Current (pulsed) 3.44 A

0.54

(2) Total Dissipation at TC = 25°C (Steady State) 2.5
(1) Total Dissipation at TC = 25°C (Steady State) 75 W

Derating Factor (2) 0.02 W/°C
Gate source ESD(HBM-C=100pF, R=1.5KΩ) 3000 V/ns

Storage Temperature
Max. Operating Junction Temperature

j

<5.7A, di/dt<300A/µs, VDD<V

SD

.

thj-F

(BR)DSS

2

, 2 oz Cu

, TJ<T

JMAX

–55 to 150 °C

A
A

W

AVALANCHE CHARACTERISTICS

Symbol Parameter Max Value Unit

I

AR

E

AS

Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T

max)

j

Single Pulse Avalanche Energy
(starting T

= 25 °C, ID = IAR, VDD = 50 V)

j

5.2 A

160 mJ

GATE-SOURCE ZENER DIODE

Symbol Parameter Test Conditions Min. Typ. Max. Unit

BV

GSO

Gate-Source Breakdown

Igs=± 1mA (Open Drain) 30 V

Voltage

PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES

The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components.

2/8

STL6NK55Z

ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED)

ON/OFF

Symbol Parameter Test Conditions Min. Typ. Max. Unit

V

(BR)DSS

Drain-source
Breakdown Voltage

I

I

V

GS(th)

R

DS(on)

DSS

GSS

Zero Gate Voltage
Drain Current (V

GS

= 0)

Gate-body Leakage
Current (V

DS

= 0)
Gate Threshold Voltage
Static Drain-source On

Resistance

DYNAMIC

Symbol Parameter Test Conditions Min. Typ. Max. Unit

g

(1) Forward Transconductance VDS = 10 V, ID= 2.6 A 3.5 S

fs

C

oss eq.

C

iss

C

oss

C

rss

Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance

(3) Equivalent Output

Capacitance

R

G

Gate Input Resistance f=1 MHz Gate DC Bias = 0

SWITCHING

Symbol Parameter Test Conditions Min. Typ. Max. Unit

t

d(on)

t

d(off)

Q
Q
Q

t

r

t

f

g
gs
gd

Turn-on Delay Time
Rise time
Turn-off Delay Time
Fall Time

Total Gate Charge
Gate-Source Charge
Gate-Drain Charge

ID = 1 mA, VGS = 0 550 V

V

= Max Rating

DS

VDS = Max Rating, TC = 125 °C

V

= ± 20V ±10 µA

GS

V

= VGS, ID = 50µA

DS

3 3.75 4.5 V

1

50

VGS = 10V, ID = 2.6 A 1.2 1.4 Ω

= 25V, f = 1 MHz, VGS = 0 695

V

DS

88
20

VGS = 0V, VDS = 0V to 440 V 48 pF

3 Ω
Test Signal Level = 20mV
Open Drain

= 275 V, ID = 2.6 A

V

DD

RG= 4.7Ω VGS = 10 V
(Resistive Load see, Figure 3)

14
20

31.5
18

= 440V, ID = 5.2 A,

V

DD

VGS = 10V

25

4.5

35

14

µA
µA

pF
pF
pF

ns
ns
ns
ns

nC
nC
nC

SOURCE DRAIN DIODE

Symbol Parameter Test Conditions Min. Typ. Max. Unit

I

SD

I

SDM

VSD (1)

t

rr

Q

rr

I

RRM

Note: 1. Pulsed: Pulse duration = 300 µs, duty cycl e 1.5 %.

2. Pulse wi dth limited by safe operating area.

3. C

Source-drain Current

(2)

Source-drain Current (pulsed)
Forward On Voltage
Reverse Recovery Time

Reverse Recovery Charge
Reverse Recovery Current

is defined as a constant equivalent capacitance giving the same charging time as C

oss eq.

V

.

DSS

ISD =5.2 A, VGS = 0
I

SD

VDD =40V, Tj = 150°C
(see test circuit, Figure 5)

= 5.2 A, di/dt = 100A/µs

350

2.2

12.5

when VDS increase s fr om 0 to 80%

oss

0.86

3.44

1.6 V

A
A

ns

µC

A

3/8

STL6NK55Z

Transfer CharacteristicsOutput Characteristics

Transconductanc e

Gate Charge vs Gate-source Voltage

Static Drain-source On Resistance

Capacitance Variations

4/8

STL6NK55Z

Normalized On Resistance vs Temperatur eNormalized Gate Thereshold Voltage vs Temp.

Source-drain Diode Forward Characteristics

Normalized BVDSS vs Temperature

5/8

STL6NK55Z

Fig. 2: Unclamped Inductive WaveformFig. 1: Unclamped Inductive Load Test Circuit

Fig. 3: Switching Times Test Circuit For

Resistive Load

Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times

Fig. 4: Gate Charge test Circuit

6/8

PowerFLAT™( 5x5) MECHANICAL DATA

STL6NK55Z

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

A 0.90 1.00 0.035 0.039

A1 0.02 0.05 0.001 0.002

b 0.43 0.51 0.58 0.017 0.020 0.023
c 0.64 0.71 0.79 0.025 0.028 0.031

D 5.00 0.197

E 5.00 0.197

E2 2.49 2.57 2.64 0.098 0.101 0.104

e 1.27 0.050

mm. inch

7/8

STL6NK55Z

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consequences of use of su ch in formation nor for any in fringement of patents or other rights of third parties w hich may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously suppli ed. STMi croelect ronics pr oducts are not author ized for use as cr itical component s in li fe suppo rt devi ces or
systems without express written approval of STMicroelectronics.

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