Datasheet ST1S40 Datasheet (ST)

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Page 1

3 A DC step-down switching regulator

VFQFPN 4x4SO8

9,16:

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Features

■ 3 A DC output current

■ 4.0 V to 18 V input voltage

■ Output voltage adjustable from 0.8 V

■ 850 kHz switching frequency

■ Internal soft-start

■ Integrated 95 mΩ and 69 mΩ Power MOSFETs

■ All ceramic capacitor

■ Enable

■ Cycle-by-cycle current limiting

■ Current fold back short-circuit protection

■ VFQFPN4x4-8L, HSOP-8, and SO-8 and

packages

Applications

■ μP/ASIC/DSP/FPGA core and I/O supplies

■ Point of load for: STB, TVs, DVD

■ Optical storage, hard disk drive, printers,

audio/graphic cards

Figure 1. Application circuit

ST1S40

Description

The ST1S40 is an internally compensated 850 kHz fixed-frequency PWM synchronous stepdown regulator. ST1S40 operates from 4.0 V to 18 V input, while it regulates an output voltage as low as 0.8 V and up to V

The ST1S40 integrates a 95 mΩ high side switch and 69 mΩ synchronous rectifier allowing very high efficiency with very low output voltages.

The peak current mode control with internal compensation delivers a very compact solution with a minimum component count.

The ST1S40 is available in VFQFPN 4 mm x 4 mm 8 lead package, HSOP-8 and standard SO-8.

March 2012 Doc ID 17928 Rev 4 1/30

www.st.com

Page 2

Contents ST1S40

Contents

1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

5.1 Internal soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5.2 Error amplifier and control loop stability . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5.3 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.4 Enable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.5 Hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.1 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.2 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.3 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.4 Thermal dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.5 Layout consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7 Demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

8 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

10 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2/30 Doc ID 17928 Rev 4

Page 3

ST1S40 Pin settings

1 Pin settings

1.1 Pin connection

Figure 2. Pin connection (top view)

VINA

GND

PGND

VINSW

VFQFPN

1.2 Pin description

No.

S08-BW

Type Description

Unregulated DC input voltage

INA

Enable input. With EN higher than 1.2 V the device in ON and with EN lower than

0.4 V the device is OFF (ST1S40Ixx).

Feedback input. Connecting the output voltage directly to this pin the output voltage is regulated at 0.8 V. To have higher regulated voltages an external resistor divider is required from Vout to the FB pin.

Table 1. Pin description

VFQFPN

and HSOP8

24EN

35FB

4 6 AGND Ground

5 - NC It can be connected to ground

VINA

GND

PGND

VINSW

SW VINSW

PGND

VINA

HSOP8SO8-BW

GND

AGND

6 8 VINSW Power input voltage

7 1 SW Regulator output switching pin

8 2 PGND Power ground

- 7 Ground

9 - ePad Exposed pad mandatory connected to ground

Doc ID 17928 Rev 4 3/30

Page 4

Maximum ratings ST1S40

2 Maximum ratings

Table 2. Absolute maximum ratings

Symbol Parameter Value Unit

Power input voltage -0.3 to 20

INSW

Input voltage -0.3 to 20

INA

Enable voltage -0.3 to V

Output switching voltage -1 to V

Feedback voltage -0.3 to 2.5

FB current -1 to +1 mA

Power dissipation at TA < 60 °C

TOT

Operating junction temperature range -40 to 150 °C

Storage temperature range -55 to 150 °C

stg

3 Thermal data

Table 3. Thermal data

Symbol Parameter Value Unit

Maximum thermal resistance junction-ambient

thJA

2.25 (HSOP8/DFN4x4);

VFQFPN 40

(1)

SO8-BW 55

INA

1.6 SO8-BW

°C/WHSOP8 40

1. Package mounted on demonstration board.

4/30 Doc ID 17928 Rev 4

Page 5

ST1S40 Electrical characteristics

4 Electrical characteristics

TJ=25 °C, VCC=12 V, unless otherwise specified.

Table 4. Electrical characteristics

Val ues

Symbol Parameter Test condition

Min. Typ. Max.

Unit

Operating input voltage

range

Tur n-o n VCC threshold

Threshold hysteresis

High side switch ON

-P resistance

Low side switch ON

-N resistance

Maximum limiting current

INON

INHYS

DSON

LIM

Oscillator

MAX

Switching frequency 0.7 0.85 1 MHz

Maximum duty cycle

Dynamic characteristics

ΔI

ΔV

OUT

Feedback voltage

Reference load regulation Isw=10 mA to I

Reference line regulation VIN= 4.0 V to 18 V

DC characteristics

(1)

ISW=750 mA

418

2.9

0.250

mΩ

ISW=750 mA 69 mΩ

(2)

4.0 6.0 A

100 %

0.784 0.8 0.816

(1)

LIM

0.776 0.8 0.824

(2)

0.5 %

0.4 %

QST-BY

Quiescent current

Total standby quiescent current

Duty cycle=0, no load

=1.2 V

OFF 2 15 μA

IFB FB bias current 50

Enable

Device ON level 1.2

EN threshold voltage

Device OFF level 0.4

EN current 2 μA

Doc ID 17928 Rev 4 5/30

1.5 2.5 mA

Page 6

Electrical characteristics ST1S40

Table 4. Electrical characteristics (continued)

Val ues

Symbol Parameter Test condition

Min. Typ. Max.

Soft start

Unit

Soft-start duration 1 ms

Protection

Thermal shutdown 150

SHDN

1. Specification referred to TJ from -40 to +125 °C. Specifications in the -40 to +125 °C temperature range are assured by design, characterization and statistical correlation.

2. Guaranteed by design.

Hysteresis 15

°C

6/30 Doc ID 17928 Rev 4

Page 7

ST1S40 Functional description

OSC

E/A

DRIVER

DMD

OTP

MOSFET

CONTROL

LOGIC

REGULATOR

SHUT-DOWN

I_SENSE

COMP

OCP REF

0.8V

SOFTSTART

Vsum

OCP

UVLO

Vdrv_p

Vdrv_n

I2V

SENSE

VINA VINSW

GNDPGNDAENFB

5 Functional description

The ST1S40 is based on a “peak current mode”, constant frequency control. The output voltage V providing an error signal that, compared to the output of the current sense amplifier, controls the ON and OFF time of the power switch.

The main internal blocks are shown in the block diagram in Figure 3. They are:

● A fully integrated oscillator that provides the internal clock and the ramp for the slope

compensation avoiding sub-harmonic instability

● The soft-start circuitry to limit inrush current during the startup phase

● The transconductance error amplifier with integrated compensation network

● The pulse width modulator and the relative logic circuitry necessary to drive the internal

power switches

● The drivers for embedded P-channel and N-channel Power MOSFET switches

● The high side current sensing block

● The low side current sense to implement diode emulation

● A voltage monitor circuitry (UVLO) that checks the input and internal voltages

● A thermal shutdown block, to prevent thermal run-away.

is sensed by the feedback pin (FB) compared to an internal reference (0.8 V)

OUT

Figure 3. Block diagram

5.1 Internal soft-start

The soft-start is essential to assure correct and safe startup of the step-down converter. It avoids inrush current surge and causes the output voltage to increase monothonically.

Doc ID 17928 Rev 4 7/30

Page 8

Functional description ST1S40

Cout

Cur rent s ense

Logic

And

Driver

Slope

Com pensati on

PW M comparator

Error Amp

0.8 V

Hi gh side

Swi tch

Low s i de

Swi tch

GCO(s)

DIV

(s)

VIN

OUT

The soft-start is performed by ramping the non-inverting input (V from 0 V to 0.8 V in around 1 ms.

5.2 Error amplifier and control loop stability

The error amplifier compares the FB pin voltage with the internal 0.8 V reference and it provides the error signal to be compared with the output of the current sense circuitry, that is the high side Power MOSFET current. Comparing the output of the error amplifier and the peak inductor current implements the peak current mode control loop.

The error amplifier is a transconductance amplifier (OTA). The uncompensated characteristics are listed inTable 5.

Table 5. Error amplifier characteristics

DC Gain 95 dB

Gm 251 µA/V

Ro 240 MΩ

The ST1S40 embeds the compensation network that assures the stability of the loop in the whole operating range. All the tools needed to check the loop stability are shown below.

Figure 4. shows the simple small signal model for the peak current mode control loop.

Figure 4. Block diagram of the loop for the small signal analysis

) of the error amplifier

REF

8/30 Doc ID 17928 Rev 4

Page 9

ST1S40 Functional description

GCOs()

LOAD

----------------- -

outTSW

⋅

--------------------------- -

1D–()0,5–⋅[]⋅+

-------------------------------------------------------------------------------------------- -

------+





------+





--------------------- - FHs()⋅⋅⋅=

ESR C

OUT

⋅

-------------------------------=

LOADCOUT

⋅

------------------------------------- -

1D–()0,5–⋅

OUTfSW

⋅⋅

---------------------------------------------+=

mC1

------ +=

Vppf

⋅=

VINV

OUT

–

----------------------------- -

Ri⋅=







FHs()

nQP

⋅

------------------ -

------++

------------------------------------------ -=

Three main terms can be identified to obtain the loop transfer function:

1. from control (output of E/A) to output, G

2. from output (Vout) to the FB pin, G

DIV

3. from the FB pin to control (output of E/A), G

The transfer function from control to output G

(s)

(s).

(s) results:

Equation 1

where R current sense circuitry, ω

represents the load resistance, Ri (0.3 Ω) the equivalent sensing resistor of the

LOAD

the single pole introduced by the LC filter and ωz the zero given by

the ESR of the output capacitor.

(s) accounts for the sampling effect performed by the PWM comparator on the output of

the error amplifier that introduces a double pole at one half of the switching frequency.

Equation 2

Equation 3

where:

Equation 4

represents the ON time slope of the sensed inductor current, Se the slope of the external

ramp (V

peak-to-peak amplitude 1.25 V) that implements the slope compensation to

avoid sub-harmonic oscillations at duty cycle over 50%.

The sampling effect contribution F

(s) is:

Equation 5

where:

Doc ID 17928 Rev 4 9/30

Page 10

Functional description ST1S40

π m

1D–()0,5–⋅[]⋅

----------------------------------------------------------=

ωnπ fSW⋅=

DIV

s()

R1R2+

--------------------=

&R5R

*P9G

5()

GEAs()

EA0

1s+ RcC

⋅⋅()⋅

R0C0Cp+()RcCcsR0Cc⋅ R0C0Cp+()RcCc⋅+⋅+()1+⋅+⋅⋅ ⋅⋅

-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------=

Equation 6

and

Equation 7

The resistor to adjust the output voltage gives the term from output voltage to the FB pin. G

(s) is:

DIV

The transfer function from FB to Vcc (output of E/A) introduces the singularities (poles and zeroes) to stabilize the loop. Figure 5 shows the small signal model of the error amplifier with the internal compensation network.

Figure 5. Small signal model for the error amplifier

and CC introduce a pole and a zero in the open loop gain. CP does not significantly affect

system stability and can be neglected.

So G

(s) results:

Equation 8

where G

= Gm · R

The poles of this transfer function are (if Cc >> C0+CP):

10/30 Doc ID 17928 Rev 4

Page 11

ST1S40 Functional description

P LF

2 π R

0Cc

⋅⋅ ⋅

--------------------------------- -=

P HF

2 π R

cC0Cp

+()⋅⋅ ⋅

----------------------------------------------------=

2 π R

cCc

⋅⋅ ⋅

---------------------------------=

fZ11 6 kHz,= f

P LF

34 Hz,=

LOOP

s() GCOs()G

DIV

s()GEAs()⋅⋅=

Equation 9

Equation 10

whereas the zero is defined as:

Equation 11

The embedded compensation network is R

=70 kΩ, CC=195 pF while CP and CO can be

considered as negligible. The error amplifier output resistance is 240 M singularities are:

Equation 12

so by closing the loop, the loop gain G

LOOP

(s) is:

Equation 13

Example:

VIN=12 V, VOUT=1.2 V, Iomax=3 A, L=1.5 µH, Cout=47 µF (MLCC), R1=10 k R2=20 k

(see Section 6.2 and Section 6.3 for inductor and output capacitor selection

guidelines).

The module and phase Bode plot are reported in Figure 6.

The bandwidth is 100 kHz and the phase margin is 45 degrees.

Ω so the relevant

Doc ID 17928 Rev 4 11/30

Page 12

Functional description ST1S40

Figure 6. Module and phase Bode plot

5.3 Overcurrent protection

The ST1S40 implements the pulse-by-pulse overcurrent protection. The peak current is sensed through the high side Power MOSFET and when it exceeds the first overcurrent threshold (OCP1) the high side is immediately turned off and the low side conducts the inductor current for the rest of the clock period.

During overload condition, since the duty cycle is not set by the control loop but is limited by the overcurrent threshold, the output voltage drops out of regulation. If the feedback falls below 0.3 V the switching frequency is reduced to one fourth and the current limit threshold is folded back to around 2 A. Thanks to the current and frequency fold back the stress on the device and on the external power components is reduced in case of severe overload or dead-short to ground of the output.

The current fold back is disabled during the startup, in order to allow the Vout to rise up properly in case of the big output capacitor requiring high extra current to be charged.

12/30 Doc ID 17928 Rev 4

Page 13

ST1S40 Functional description

An additional mechanism is protecting the device in case of short-circuit on the output and high input voltage. A further threshold (OCP2, 1A higher than OCP1) is compared to the inductor current. If the inductor current exceeds OCP2, the device stops switching and restarts with a soft-start cycle.

5.4 Enable function

The enable feature allows the device to be put into standby mode. With the EN pin lower than 0.4 V, the device is disabled and the power consumption is reduced to less than 15 µA. With the EN pin higher than 1.2 V, the device is enabled. If the EN pin is left floating, an internal pull-down ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. The pin is also V

compatible.

5.5 Hysteretic thermal shutdown

The thermal shutdown block generates a signal that turns off the power stage if the junction temperature goes above 150 °C. Once the junction temperature goes back to about 130 °C, the device restarts in normal operation.

Doc ID 17928 Rev 4 13/30

Page 14

Application information ST1S40

RMSIO

⋅

-------------- -–

------ -+⋅=

CINFSW⋅

------------------------- 1

--- -–





--- - 1D–()⋅+⋅ ESR I

⋅+⋅=

VPPFSW⋅

-------------------------- - 1

--- -–





--- - 1D–()⋅+⋅⋅=

6 Application information

6.1 Input capacitor selection

The capacitor connected to the input must be capable of supporting the maximum input operating voltage and the maximum RMS input current required by the device. The input capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR, affecting the overall system efficiency.

So the input capacitor must have an RMS current rating higher than the maximum RMS input current and an ESR value compliant with the expected efficiency.

The maximum RMS input current flowing through the capacitor can be calculated as:

Equation 14

where Io is the maximum DC output current, D is the duty cycle, η is the efficiency. Considering η=1, this function has a maximum at D=0.5 and is equal to Io/2.

The peak-to-peak voltage across the input capacitor can be calculated as:

Equation 15

where ESR is the equivalent series resistance of the capacitor.

Given the physical dimension, ceramic capacitors can well meet the requirements of the input filter sustaining a higher input RMS current than electrolytic / tantalum types. In this case the equation of C

as a function of the target peak-to-peak voltage ripple (VPP) can be

written as follows:

Equation 16

neglecting the small ESR of ceramic capacitors.

Considering η=1, this function has its maximum in D=0.5, therefore, given the maximum peak-to-peak input voltage (V

14/30 Doc ID 17928 Rev 4

PP_MAX

), the minimum input capacitor (C

IN_MIN

) value is:

Page 15

ST1S40 Application information

IN_MIN

PP_MAXFSW

⋅⋅

----------------------------------------------- -=

ΔI

VINV

OUT

–

----------------------------- - T

⋅

OUT

-------------- T

OFF

⋅==

MIN

OUT

ΔI

MAX

----------------

MIN

–

SWMIN

---------------------- -⋅=

Equation 17

Typically, C of 1% of V

is dimensioned to keep the maximum peak-to-peak voltage ripple in the order

INMAX

In Table 6 some multi layer ceramic capacitors suitable for this device are reported.

Table 6. Input MLCC capacitors

Manufacturer Series Cap value (μF) Rated voltage (V)

Murata

TDK C3225 10 25

A ceramic bypass capacitor, as close as possible to the V ESR and ESL are minimized, is suggested in order to prevent instability on the output voltage due to noise. The value of the bypass capacitor can go from 330 nF to 1 µF.

6.2 Inductor selection

The inductance value fixes the current ripple flowing through the output capacitor. So the minimum inductance value, to have the expected current ripple, must be selected. The rule to fix the current ripple value is to have a ripple at 20% to 40% of the output current.

In continuous current mode (CCM), the inductance value can be calculated by the following equation:

GRM31 10 25

GRM55 10 25

pin, so that additional parasitic

INA

Equation 18

where T the low side switch (in CCM, F Vout, is obtained at maximum T

is the conduction time of the high side switch and T

=1/(TON + T

, that is at minimum duty cycle. So by fixing ΔIL=20% to

OFF

)). The maximum current ripple, given the

OFF

is the conduction time of

OFF

30% of the maximum output current, the minimum inductance value can be calculated:

Equation 19

where F

is the minimum switching frequency, according to Ta bl e 4

SWMIN

The peak current through the inductor is given by:

Doc ID 17928 Rev 4 15/30

Page 16

Application information ST1S40

LPK,

ΔI

--------+=

ΔV

OUT

ESR ΔI

MAX

⋅

ΔI

MAX

OUTfSW

⋅⋅

------------------------------------ -+=

Equation 20

so if the inductor value decreases, the peak current (that must be lower than the current limit of the device) increases. The higher the inductor value, the higher the average output current that can be delivered, without reaching the current limit.

In Ta bl e 7 below some inductor part numbers are listed.

Table 7. Inductors

Manufacturer Series Inductor value (μH) Saturation current (A)

XPL7030 2.2 to 4.7 6.8 to 10.5

Coilcraft

Wurth

MSS1048 2.2 to 6.8 4.14 to 6.62

MSS1260 10 5.5

WE-HC/HCA 3.3 to 4.7 7 to 11

WE-TPC typ XLH 3.6 to 6.2 4.5 to 6.4

WE-PD type L 10 5.6

TDK RLF7030T 2.2 to 4.7 4 to 6

6.3 Output capacitor selection

The current in the output capacitor has a triangular waveform which generates a voltage ripple across it. This ripple is due to the capacitive component (charge or discharge of the output capacitor) and the resistive component (due to the voltage drop across its ESR). So the output capacitor must be selected in order to have a voltage ripple compliant with the application requirements.

The amount of the voltage ripple can be calculated starting from the current ripple obtained by the inductor selection.

Equation 21

For ceramic (MLCC) capacitors the capacitive component of the ripple dominates the resistive one. Whilst for electrolytic capacitors the opposite is true.

Since the compensation network is internal, the output capacitor should be selected in order to have a proper phase margin and then a stable control loop.

The equations of Chapter 5.2 help to check loop stability given the application conditions, the value of the inductor, and of the output capacitor.

In Ta bl e 8 below some capacitor series are listed.

16/30 Doc ID 17928 Rev 4

Page 17

ST1S40 Application information

COND

RHSI

OUT

DRLSI

OUT

1D–()⋅⋅+⋅⋅=

SWVINIOUT

RISETFALL

+()

------------------------------------------ -

Fsw⋅⋅ ⋅ V

INIOUTTSWFSW

⋅⋅⋅==

VINIQ⋅=

Table 8. Output capacitors

Manufacturer Series Cap value (μF) Rated voltage (V) ESR (mΩ)

MURATA

PANASONIC

SANYO TPA/B/C 100 to 470 4 to 16 40 to 80

TDK C3225 22 to 100 6.3 < 5

GRM32 22 to 100 6.3 to 25 < 5

GRM31 10 to 47 6.3 to 25 < 5

ECJ 10 to 22 6.3 < 5

EEFCD 10 to 68 6.3 15 to 55

6.4 Thermal dissipation

The thermal design is important in order to prevent thermal shutdown of the device if junction temperature goes above 150 °C. The three different sources of losses within the device are:

a) conduction losses due to the ON resistance of high side switch (R

switch (R

Equation 22

); these are equal to:

) and low side

where D is the duty cycle of the application. Note that the duty cycle is theoretically given by the ratio between V

and VIN, but is actually slightly higher to compensate the losses of

OUT

the regulator.

b) switching losses due to high side Power MOSFET turn ON and OFF; these can be

calculated as:

Equation 23

where T switch (V in Figure 7. T

and T

RISE

) and the current flowing into it during turn ON and turn OFF phases, as shown

are the overlap times of the voltage across the high side power

FAL L

is the equivalent switching time. For this device the typical value for the

equivalent switching time is 20 ns.

c) Quiescent current losses, calculated as:

Equation 24

Doc ID 17928 Rev 4 17/30

Page 18

Application information ST1S40

TJTARthJAP

TOT

⋅+=

SW,HS

DS,HS

COND,HS

COND,LS

FALL

RISE

where IQ is the quiescent current (IQ=2.5 mA maximum).

The junction temperature T

can be calculated as:

Equation 25

where T

Rth

is the ambient temperature and P

is the equivalent thermal resistance junction to ambient of the device; it can be

is the sum of the power losses just seen.

TOT

calculated as the parallel of many paths of heat conduction from the junction to the ambient. For this device the path through the exposed pad is the one conducting the largest amount of heat. The Rth

measured on the demonstration board described in the following

paragraph is about 40 °C/W for the VFQFPN and HSOP packages and about 55 °C/W for the SO8-BW package.

Figure 7. Switching losses

6.5 Layout consideration

The PC board layout of switching DC-DC regulator is very important in order to minimize the noise injected in high impedance nodes, to reduce interferences generated by the high switching current loops, and to optimize the reliability of the device.

In order to avoid EMC problems, the high switching current loops must be as short as possible. In the buck converter there are two high switching current loops: during the ON time, the pulsed current flows through the input capacitor, the high side power switch, the inductor and the output capacitor; during the OFF time, through the low side power switch, the inductor and the output capacitor.

The input capacitor connected to VINSW must be placed as close as possible to the device, to avoid spikes on VINSW due to the stray inductance and the pulsed input current.

18/30 Doc ID 17928 Rev 4

Page 19

ST1S40 Application information

Input cap as close as possible to VINSW pin

Star center for common ground

Short FB trace

VINA derived from Cin To avoid dynamic voltage drop Between VINA and VINSW

Short high switching current loop

Via to connect the thermal pad To bottom or inner ground plane

In order to prevent dynamic unbalance between VINSW and V V

pin to the input must be derived from VINSW.

INA

, the trace connecting the

INA

The feedback pin (FB) connection to the external resistor divider is a high impedance node, so the interferences can be minimized through the routing of the feedback node with a very short trace and as far as possible from the high current paths.

A single point connection from signal ground to power ground is suggested.

Thanks to the exposed pad of the device, the ground plane helps to reduce the thermal resistance junction to ambient; so a large ground plane, soldered to the exposed pad, enhances the thermal performance of the converter allowing high power conversion.

Figure 8. PCB layout guidelines

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Demonstration board ST1S40

7 Demonstration board

Figure 9. Demonstration boards schematic

Table 9. Component list

Reference Part number Description Manufacturer

U1 ST1S40 STM

L1 DRA74 3R3 3.3 µH, Isat=5.4 A Coiltronics

C1 C3225X7RE106K 10 µF 25 V X7R TDK

C2 C3225X7R1C226M 22 µF 16 V X7R TDK

C3 1 µF 25 V X7R

C4 NC

R1 62.5 kΩ

R2 20 kΩ

R3 10 kΩ

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ST1S40 Demonstration board

Figure 10. Demonstration board PCB top and bottom: HSOP8 package

Figure 11. Demonstration board PCB top and bottom: VFQFPN package

Figure 12. Demonstration board PCB top and bottom: SO8-BW package

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Typical characteristics ST1S40

100

0.00 0.50 1.00 1.50 2.00 2.50 3.00

Efficie ncy [%]

Iout [A]

Vin=5V

Vo=3 .3V

Vo=1 .8V

Vo=1 .2V

0.00 0.50 1.00 1.50 2.00 2.50 3.00

Efficiency [% ]

Iout [A]

Vin=12V

Vo=1 .8V

Vo=1 .2V

100

0.00 0.50 1.00 1.50 2.00 2.50 3.00

Efficiency [%]

Iout [A]

Vin=12V

Vo=5 V

Vo=3 .3V

Ta mb =6 0d eg C

Tjmax=150degC

Maximum I

OUT

according to 1.6W power dissipation

Limit with SO8-BW package

8 Typical characteristics

Figure 13. Efficiency vs. I

Figure 15. Efficiency vs. I

OUT

Figure 14. Efficiency vs. I

OUT

Figure 16. Overcurrent protection

Figure 17. Short-circuit protection Figure 18. SO8-BW maximum I

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OUT

Page 23

ST1S40 Package mechanical data

9 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK

packages, depending on their level of environmental compliance. ECOPACK®

is an ST trademark.

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Page 24

Package mechanical data ST1S40

%

Table 10. VFQFPN8 (4x4x1.0 mm) mechanical data

mm inch

Dim.

Min. Typ. Max. Min. Typ. Max.

A 0.80 0.90 1.00 0.0315 0.0354 0.0394

A1 0.02 0.05 0.0008 0.0020

A3 0.20 0.0079

b 0.23 0.30 0.38 0.009 0.0117 0.0149

D 3.90 4.00 4.10 0.153 0.157 0.161

D2 2.82 3.00 3.23 0.111 0.118 0.127

E 3.90 4.00 4.10 0.153 0.157 0.161

E2 2.05 2.20 2.30 0.081 0.087 0.091

e 0.80 0.031

L 0.40 0.50 0.60 0.016 0.020 0.024

Figure 19. VFQFPN8 (4x4x1.0 mm) package dimensions

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Page 25

ST1S40 Package mechanical data

Table 11. SO8-BW mechanical data

mm inch

Dim

Min. Typ. Max. Min. Typ. Max.

A 135 1.75 0.053 0.069

A1 0.10 0.25 0.004 0.001

A2 1.10 1.65 0.043 0.065

B 0.33 0.51 0.013 0.020

C 0.19 0.25 0.007 0.01

(1)

E 3.80 4.00 0.15 0.157

e1.27 0.050

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.0098 0.0197

L 0.40 1.27 0.0157 0.0500

k 0°(min.), 8° (max.)

ddd 0.10 0.0039

4.80 5.00 0.1890 0.1929 0.1969

1. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs must not exceed 0.15 mm (.006 inch) in total (both sides).

Figure 20. SO8-BW package dimensions

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Doc ID 17928 Rev 4 25/30

Page 26

Package mechanical data ST1S40

Table 12. HSOP8 mechanical data

mm inch

Dim

Min. Typ. Max. Min. Typ. Max.

A 1.70 0.0669

A1 0.00 0.150 0.00 0.0059

A2 1.25 0.0492

b 0.31 0.51 0.0122 0.0201

c 0.17 0.25 0.0067 0.0098

D 4.80 4.90 5.00 0.1890 0.1929 0.1969

E 5.80 6.00 6.20 0.2283 0.2362 0.2441

E1 3.80 3.90 4.00 0.1496 0.1535 0.1575

e 1.27 0.0500

h 0.25 0.50 0.0098 0.0197

L 0.40 1.27 0.0157 0.0500

k 0.00 8.00 0.3150

ccc 0.10 0.0039

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ST1S40 Package mechanical data

' PP7\S ( PP7\S

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Figure 21. HSOP8 package dimensions

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Page 28

Order codes ST1S40

10 Order codes

Table 13. Ordering information

Order codes Package Function

ST1S40IPUR VFQFPN 4x4 8L

EnableST1S40IPHR HSOP8

ST1S40IDR SO8-BW

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Page 29

ST1S40 Revision history

11 Revision history

Table 14. Document revision history

Date Revision Changes

15-Dec-2010 1 First release

04-Mar-2011 2 Updated: Ta b l e 1 , Tab le 2, Ta bl e 3 and Ta bl e 1 3 .

20-Dec-2011 3

01-Mar-2012 4

Updated cover page: Tab le 1, Ta b le 2 , Section 5 Added Section 6, Section 7 and Section 8

HSOP8 mechanical data and package dimensions have been updated.

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Page 30

ST1S40

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