Page 1
OptiMOS
Power-Transistor
Feature
N-Channel
Enhancement mode
Logic Level
Preliminary data
SPD100N03S2L-04
Product Summary
V
DS
R
DS(on
I
D
30 V
4.2 m
100 A
Excellent Gate Charge x R
Superior thermal resistance
175°C operating temperature
Avalanche rated
dv /dt rated
DS(on
product (FOM)
Type Package Ordering Code
SPD100N03S2L-04 P-TO252-5-1 Q67042-S4128
Marking
PN03L04
P-TO252-5-1
6
1)
Gate
pin 1
n.c.: pin 2
1
3
2
Drain
pin 3,6
Source
pin 4,5
Maximum Ratings,at T j = 25 °C, unless otherwise specified
Parameter Symbol Value Unit
Continuous drain current
TC=25°C2)
T
=100°C
C
Pulsed drain current
TC=25°C
I
D
I
D puls
100
100
400
A
5
4
Avalanche energy, single pulse
ID=80A, V DD=25V, R GS=25
Avalanche energy, periodic limited by T
Reverse diode dv /dt
IS=100A, V DS=24V, di /d t =200A/µs, T
jmax
=175°C
max
E
E
dv /dt 6 kV/µs
Gate source voltage V
Power dissipation
TC=25°C
P
Operating and storage temperature T
AS
AR
GS
tot
,
T
st
325 mJ
15
±20
150 W
-55... +175
V
°C
IEC climatic category; DIN IEC 68-1 55/175/56
Page 1
2001-12-04
Page 2
Preliminary data
SPD100N03S2L-04
Thermal Characteristics
Parameter Symbol Values Unit
min. typ. max.
Characteristics
Thermal resistance, junction - case
SMD version, device on PCB:
@ min. footprint
@ 6 cm
2
cooling area
3)
R
R
thJC
thJA
- - 1 K/W
-
-
-
-
75
50
Electrical Characteristics, at T j = 25 °C, unless otherwise specified
Parameter Symbol Values Unit
min. typ. max.
Static Characteristics
Drain-source breakdown voltage
VGS=0V, I D=1mA
Gate threshold voltage, VGS = V
I
= 100 µA
D
Zero gate voltage drain current
VDS=30V, VGS=0V, Tj=25°C
DS
V
(BR)DSS
V
GS(th)
I
DSS
30 - - V
1.2 1.6 2
-
0.01
1
µA
V
=30V, VGS=0V, Tj=125°C
DS
Gate-source leakage current
VGS=20V, VDS=0V
Drain-source on-state resistance
VGS=4.5V, I D=50A
Drain-source on-state resistance
VGS=10V, I D=50A
1
pin 1 and 2 have to be connected together on the PCB as well as pin 4 and 5.
2
Current limited by bondwire and calculated with max. source pin temperature of 85°C;
with a R
3
Device on 40mm*40mm*1.5mm epoxy PCB FR4 with 6cm² (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical without blown air.
= 1K/W the chip is able to carry I D= 146A.
thJC
I
GSS
R
DS(on)
R
DS(on)
-
10
100
- 1 100 nA
- 5 6.3
- 3.4 4.2
m
Page 2
2001-12-04
Page 3
Preliminary data
SPD100N03S2L-04
Electrical Characteristics, at T j = 25 °C, unless otherwise specified
Parameter Symbol Conditions Values Unit
min. typ. max.
Dynamic Characteristics
Transconductance g
Input capacitance C
Output capacitance C
Reverse transfer capacitance C
Turn-on delay time t
Rise time t
Turn-off delay time t
Fall time t
Gate Charge Characteristics
Gate to source charge Q
Gate to drain charge Q
Gate charge total Q
fs
iss
oss
rss
d(on)
r
d(off)
f
gs
gd
g
VDS
2*I D*R
DS(on)max
I
=100A
D
VGS=0V, VDS=25V,
f=1MHz
,
59 118 - S
- 2590 3450 pF
- 1025 1360
- 205 310
VDD=15V, VGS=10V,
I
=50A, R G=2.7
D
- 12 18 ns
- 245 365
- 45 67
- 24 36
VDD=24V, I D=100A - 9.7 12.9 nC
- 22.6 33.9
VDD=24V, I D=100A,
V
=0 to 10V
GS
- 72 96
Gate plateau voltage V
Reverse Diode
Inverse diode continuous
I
forward current
Inverse diode direct current,
I
pulsed
Inverse diode forward voltage V
Reverse recovery time t
Reverse recovery charge Q
S
SM
SD
rr
rr
lateau
VDD=24V, I D=100A - 3.6 - V
TC=25°C - - 100 A
- - 400
VGS=0V, IF=80A - 0.9 1.3 V
VR=15V, I
di
/dt=200A/µs
F
lS,
=
F
- 48 72 ns
- 100 150 nC
Page 3
2001-12-04
Page 4
Preliminary data
SPD100N03S2L-04
1 Power dissipation
P
= f (T C)
tot
SPD100N03S2L-04
160
W
120
tot
100
P
80
60
40
20
0
0 20 40 60 80 100 120 140 160°C190
2 Drain current
ID = f (T C)
parameter: V
SPD100N03S2L-04
110
A
90
80
70
D
I
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140 160°C190
T
C
GS
10 V
T
C
3 Safe operating area
ID = f ( VDS )
parameter : D = 0 , T C = 25 °C
3
SPD100N03S2L-04
10
A
2
10
D
I
1
10
0
10
-1
10
R
D
I
/
S
D
V
=
)
n
o
(
S
D
0
10
10
DC
1
tp = 8.5µs
10 µs
100 µs
1 ms
10 ms
V
V
DS
10
4 Transient thermal impedance
Z
= f (t p)
thJC
parameter : D = t p/T
1
SPD100N03S2L-04
10
K/W
0
10
thJC
-1
Z
10
-2
10
-3
10
single pulse
-4
2
10
10
-7
-6
10
-5
10
10
D = 0.50
0.20
0.10
0.05
0.02
0.01
-4
-3
10
10
-2
s
t
0
10
p
Page 4
2001-12-04
Page 5
Preliminary data
SPD100N03S2L-04
5 Typ. output characteristic
ID = f (V DS); T j=25°C
parameter: t p = 80 µs
SPD100N03S2L-04
240
P
= 150W
tot
A
i
g
h
f
200
180
160
D
I
140
120
100
80
60
40
20
0
0 0.5 1 1.5 2 2.5 3 3.5 4
VGS [V]
e
d
c
b
a
a 2.5
b 3.0
c 3.5
d 4.0
e 4.5
f 5.0
g 5.5
h 6.0
i 10.0
V
V
DS
6 Typ. drain-source on resistance
R
DS(on)
parameter: V
R
5
= f (I D)
GS
SPD100N03S2L-04
14
12
11
10
DS(on)
9
8
7
6
5
4
3
2
1
0
0 20 40 60 80 100 120 140 160
c
V
[V] =
GS
c
d
e
f
g
3.5
4.0
4.5
5.0
5.5
6.0
h
d
10.0
e
f
g
h
i
i
200
A
I
D
7 Typ. transfer characteristics
ID= f ( VGS ); V
2 x I D x R
DS
DS(on)max
parameter: t p = 20 µs
180
A
140
120
D
I
100
80
60
40
20
0
0 0.5 1 1.5 2 2.5 3 3.5
V
V
GS
4.5
8 Typ. forward transconductance
gfs = f(I D); Tj=25°C
parameter: g
130
S
110
100
90
fs
80
g
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120
fs
160
A
I
D
Page 5
2001-12-04
Page 6
Preliminary data
SPD100N03S2L-04
9 Drain-source on-state resistance
R
DS(on)
= f (T j)
parameter : I D = 50 A, V GS = 10 V
SPD100N03S2L-04
11
9
8
DS(on)
7
R
6
5
4
3
2
1
0
-60 -20 20 60 100 140
98%
typ
°C
10 Typ. gate threshold voltage
V
GS(th)
= f (T j)
parameter: V GS = V DS
2.35
V
1.95
1.75
GS(th)
V
1.55
1.35
ID=110µA
1.15
0.95
0.75
0.55
200
T
j
0.35
-60 -20 20 60 100
ID=6.4mA
°C
180
T
j
11 Typ. capacitances
C = f (V DS)
parameter: V GS=0V, f =1 MHz
4
10
pF
C
3
10
2
10
0 5 10 15 20
12 Forward character. of reverse diode
IF = f (VSD)
parameter: T j , tp = 80 µs
3
SPD100N03S2L-04
10
A
C
iss
2
10
F
C
oss
C
rss
V
30
DS
V
I
1
10
Tj = 25 °C typ
Tj = 175 °C typ
Tj = 25 °C (98%)
Tj = 175 °C (98%)
0
10
0 0.4 0.8 1.2 1.6 2 2.4
3
V
V
SD
Page 6
2001-12-04
Page 7
Preliminary data
SPD100N03S2L-04
13 Typ. avalanche energy
EAS = f (T j)
par.: I D = 80 A, V DD = 25 V, R GS = 25
350
mJ
250
AS
E
200
150
100
50
0
25 45 65 85 105 125 145
°C
T
14 Typ. gate charge
V
GS
= f (Q
Gate
)
parameter: I D = 100 A pulsed
SPD100N03S2L-04
16
V
12
GS
10
V
8
6
4
2
185
j
0
0 20 40 60 80
0,2
V
DS max
0,8 V
DS max
nC
Q
120
Gate
15 Drain-source breakdown voltage
V
(BR)DSS
= f (T j)
parameter: I D=10 mA
SPD100N03S2L-04
36
V
34
33
(BR)DSS
V
32
31
30
29
28
27
-60 -20 20 60 100 140
°C
200
T
j
Page 7
2001-12-04
Page 8
Preliminary data
Published by
Infineon Technologies AG,
Bereichs Kommunikation
St.-Martin-Strasse 53,
D-81541 München
© Infineon Technologies AG 1999
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement,
regarding circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Reprensatives worldwide (see address list).
Warnings
Due to technical requirements components may contain dangerous substances.
For information on the types in question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express
written approval of Infineon Technologies, if a failure of such components can reasonably be expected to
cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device
or system Life support devices or systems are intended to be implanted in the human body, or to support
and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
SPD100N03S2L-04
Further information
Please notice that the part number is BSPD100N03S2L-04, for simplicity the device is referred to by the term
SPD100N03S2L-04 throughout this documentation.
Page 8
2001-12-04
Page 9